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I have a situation where I want capture compiler directives in a SystemVerilog file. Be it an include or ifdef. Currently, I haven't found a clean way to do it. Here is what I tried, which I've taken mostly from existing code:
This works alright, but it requires me to bring nom into the client code, which I am hesitant about. I was wondering if there is a better way to do this, or are their any plans to do it in the future?
The text was updated successfully, but these errors were encountered:
Hi,
First of, thank you for the amazing work.
I have a situation where I want capture compiler directives in a SystemVerilog file. Be it an
include or
ifdef. Currently, I haven't found a clean way to do it. Here is what I tried, which I've taken mostly from existing code:This works alright, but it requires me to bring nom into the client code, which I am hesitant about. I was wondering if there is a better way to do this, or are their any plans to do it in the future?
The text was updated successfully, but these errors were encountered: