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`IFDEFs and such cause incorrect line numbers #72
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@MahmoudKMaarouf Would you add a testcase to https://github.com/dalance/sv-parser/blob/master/sv-parser-pp/src/preprocess.rs#L1213 |
@DaveMcEwan |
Nice and easy :) The full flow would be something like this:
Is that helpful? |
Much appreciated Dave. |
Placing this on top of code:
will cause the line numbers of the original file to be shifted 1 up (equivalent to minus 1) more than what it currently is. More lines within the IF_DEF that are not executed will shift it even further, making the lines almost completely useless with large Verilog files and many IF DEFs. This is very hard to work around since the line numbers are critical for my tool.
Any help is appreciated.
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