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section 6.23 of LRM 2017 results in a syntax error #100
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The actual code in section 6.23 is like below. bit [12:0] A_bus, B_bus;
parameter type bus_t = type(A_bus);
generate
case (type(bus_t))
type(bit[12:0]): addfixed_int #(bus_t) (A_bus,B_bus);
type(real): add_float #(type(A_bus)) (A_bus,B_bus);
endcase
endgenerate This shows
But the expression which can be used in
On the other hand, generate case takes
|
Making that expression constant is not possible in my code. It would remove the purpose of using that feature in the first place. I am using the preprocessor to remove problematic code from sv-parse (since the preprocessor actually works properly!) Despite these small problems, sv-parse is the best open-source SystemVerilog parser that I can find anywhere--for lots of reasons. This is excellent work that has made things possible for me that were kludgy at best in the past. I appreciate it. It would be interesting to see the discrepancies between the LRM and the grammars the commercial tools actually use. I imagine there are lots of differences. |
I am sorry for inconvenience, but supporting tool-specific behavior is difficult. |
The following code produces an error:
Error:
$ svinst test2.sv
files:
parse failed: "test2.sv"
test2.sv:11:1
|
11 | class Container #(type T);
| ^
Commenting out the case statement allows the parser to succeed.
This code compiles fine on a commercial parser. See section 6.23 of the 1800-2017 LRM.
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