[AMD][Genoa] Unexpected HSMP values on Epyc 9274F (#discussioncomment-9476811) #487

garceri · 2024-03-05T18:45:25Z

garceri
Mar 5, 2024

I can't get any temperature readings under Ubuntu 22.04 running kernel 6.5

cyring · 2024-03-06T06:33:47Z

cyring
Mar 6, 2024
Maintainer

Can you post the text output of this CLI command:

corefreq-cli -s -n -m -n -B -n -M -n -k -n -C 1 -n -i 1 -n -V 1 -n -W 1

Do you confirm using latest commits of the master branch ?
Do you confirm no other agent is monitoring temperature in parallel of CoreFreq ? Is the kernel module k10temp running ? (show lsmod)
Is the PCI known by CoreFreq well identified ? Please provide lspci -nn

For all these outputs, please employ the Markdown formatting.

0 replies

cyring · 2024-03-16T18:44:19Z

cyring
Mar 16, 2024
Maintainer

I think Genoa and Zen4/Hawk Point (#84) are missing the temperature for the same reason: no thermal register known.

0 replies

cyring · 2024-03-16T18:50:37Z

cyring
Mar 16, 2024
Maintainer

Meanwhile I can fix the voltage Vcore if you provide me the CLI output requested above.

0 replies

cyring · 2024-03-17T17:48:00Z

cyring
Mar 17, 2024
Maintainer

Can you please pull develop branch and test temperature ?

0 replies

garceri · 2024-03-17T19:25:54Z

garceri
Mar 17, 2024
Author

Server is a HPE Proliant DL945 Gen11
k10temp was loaded, unloading it did not make any difference:

Here is the output for the develop branch: as you can see temps seems to be stuck at 99

Here is the corefreq-cli output that was also requested (from the develop branh as well), the DIMM size is wrong these modules are 96GB not 64GB as reported by corefreq:

        Array Handle: 0x0016
        Error Information Handle: Not Provided
        Total Width: 80 bits
        Data Width: 64 bits
        Size: 96 GB
        Form Factor: DIMM
        Set: 2
        Locator: PROC 1 DIMM 3
        Bank Locator: Not Specified
        Type: DDR5
        Type Detail: Synchronous Registered (Buffered)
        Speed: 4800 MT/s
        Manufacturer: Samsung
        Serial Number: 04CC87F6
        Asset Tag: Not Specified
        Part Number: M321RYGA0BB0-CQKZJ
        Rank: 2
        Configured Memory Speed: 4800 MT/s
        Minimum Voltage: 1.1 V
        Maximum Voltage: 1.1 V
        Configured Voltage: 1.1 V
        Memory Technology: DRAM
        Memory Operating Mode Capability: Volatile memory
        Firmware Version: Not Specified
        Module Manufacturer ID: Bank 1, Hex 0xCE
        Module Product ID: Unknown
        Memory Subsystem Controller Manufacturer ID: Unknown
        Memory Subsystem Controller Product ID: Unknown
        Non-Volatile Size: None
        Volatile Size: 96 GB
        Cache Size: None
        Logical Size: None

Processor                                     [AMD EPYC 9274F 24-Core Processor]
|- PPIN#                                                      [ 2b6a56a45d98031]
|- Architecture                                                     [EPYC/Genoa]
|- Vendor ID                                                      [AuthenticAMD]
|- Firmware                                                        [ 71.121.0-5]
|- Microcode                                                        [0x0a101144]
|- Signature                                                           [  AF_11]
|- Stepping                                                            [      1]
|- Online CPU                                                          [ 48/ 48]
|- Base Clock                                                          [101.099]
|- Frequency            (MHz)                      Ratio
                 Min   1516.48                    <  15 >
                 Max   4043.95                    <  40 >
|- Factory                                                             [100.000]
                       4000                       [  40 ]
|- Performance
   |- P-State
                 TGT   4043.95                    <  40 >
   |- CPPC
                 Min    808.79                    <   8 >
                 Max    101.10                    <   1 >
                 TGT    808.79                    <   8 >
|- Turbo Boost                                                         [   LOCK]
                 XFR    808.79                    [   8 ]
                 CPB    808.79                    [   8 ]
                  1C   2729.67                    <  27 >
                  2C   1516.48                    <  15 >
|- Uncore                                                              [   LOCK]
                 CLK   2426.37                    [  24 ]
                 MEM   2426.37                    [  24 ]

Instruction Set Extensions
|- 3DNow!/Ext [N/N]          ADX [Y]          AES [Y]  AVX/AVX2 [Y/Y]
|- AVX512-F     [Y]    AVX512-DQ [Y]  AVX512-IFMA [Y]   AVX512-PF [N]
|- AVX512-ER    [N]    AVX512-CD [Y]    AVX512-BW [Y]   AVX512-VL [Y]
|- AVX512-VBMI  [Y] AVX512-VBMI2 [Y]  AVX512-VNNI [Y]  AVX512-ALG [Y]
|- AVX512-VPOP  [Y] AVX512-VNNIW [N] AVX512-FMAPS [N] AVX512-VP2I [N]
|- AVX512-BF16  [Y] AVX-VNNI-VEX [N]    AVX-FP128 [N]   AVX-FP256 [Y]
|- BMI1/BMI2  [Y/Y]         CLWB [Y]      CLFLUSH [Y] CLFLUSH-OPT [Y]
|- CLAC-STAC    [Y]         CMOV [Y]    CMPXCHG8B [Y]  CMPXCHG16B [Y]
|- F16C         [Y]          FPU [Y]         FXSR [Y]   LAHF-SAHF [Y]
|- MMX/Ext    [Y/Y] MON/MWAITX [Y/Y]        MOVBE [Y]   PCLMULQDQ [Y]
|- POPCNT       [Y]       RDRAND [Y]       RDSEED [Y]      RDTSCP [Y]
|- SEP          [Y]          SHA [Y]          SSE [Y]        SSE2 [Y]
|- SSE3         [Y]        SSSE3 [Y]  SSE4.1/4A [Y/Y]      SSE4.2 [Y]
|- SERIALIZE    [N]      SYSCALL [Y]        RDPID [Y]        UMIP [Y]
|- VAES         [Y]   VPCLMULQDQ [Y]   PREFETCH/W [Y]       LZCNT [Y]

Features
|- 1 GB Pages Support                                      1GB-PAGES   [Capable]
|- 100 MHz multiplier Control                            100MHzSteps   [Missing]
|- Advanced Configuration & Power Interface                     ACPI   [Capable]
|- Advanced Programmable Interrupt Controller                   APIC   [Capable]
|- Advanced Virtual Interrupt Controller                        AVIC   [Capable]
|- APIC Timer Invariance                                        ARAT   [Capable]
|- LOCK prefix to read CR8                                    AltMov   [Capable]
|- Clear Zero Instruction                                     CLZERO   [Capable]
|- Core Multi-Processing                                  CMP Legacy   [Capable]
|- L1 Data Cache Context ID                                  CNXT-ID   [Missing]
|- Collaborative Processor Performance Control                  CPPC   [Capable]
|- Direct Cache Access                                           DCA   [Missing]
|- Debugging Extension                                            DE   [Capable]
|- Debug Store & Precise Event Based Sampling               DS, PEBS   [Missing]
|- CPL Qualified Debug Store                                  DS-CPL   [Missing]
|- 64-Bit Debug Store                                         DTES64   [Missing]
|- Fast Short REP MOVSB                                         FSRM   [Capable]
|- Fast-String Operation                                        ERMS   [Capable]
|- Fused Multiply Add                                           FMA4   [Missing]
|- Fused Multiply Add                                            FMA   [Capable]
|- Hardware Lock Elision                                         HLE   [Missing]
|- Hyper-Threading Technology                                    HTT   [Capable]
|- Hardware P-state control                                      HwP   [Capable]
|- Instruction Based Sampling                                    IBS   [Capable]
|- Instruction INVLPGB                                       INVLPGB   [Capable]
|- Instruction INVPCID                                       INVPCID   [Capable]
|- Long Mode 64 bits                                       IA64 | LM   [Capable]
|- LightWeight Profiling                                         LWP   [Missing]
|- Memory Bandwidth Enforcement                                  MBE   [Capable]
|- Machine-Check Architecture                                    MCA   [Capable]
|- Instruction MCOMMIT                                       MCOMMIT   [Missing]
|- Model Specific Registers                                      MSR   [Capable]
|- Memory Type Range Registers                                  MTRR   [Capable]
|- No-Execute Page Protection                                     NX   [Capable]
|- OS-Enabled Ext. State Management                          OSXSAVE   [Capable]
|- OS Visible Work-around                                       OSVW   [Capable]
|- Physical Address Extension                                    PAE   [Capable]
|- Page Attribute Table                                          PAT   [Capable]
|- Pending Break Enable                                          PBE   [Missing]
|- Process Context Identifiers                                  PCID   [Capable]
|- Perfmon and Debug Capability                                 PDCM   [Missing]
|- Page Global Enable                                            PGE   [Capable]
|- Page Size Extension                                           PSE   [Capable]
|- 36-bit Page Size Extension                                  PSE36   [Capable]
|- Processor Serial Number                                       PSN   [Missing]
|- Resource Director Technology/PQE                            RDT-A   [Capable]
|- Resource Director Technology/PQM                            RDT-M   [Capable]
|- Read Processor Register at User level                       RDPRU   [Capable]
|- Restricted Transactional Memory                               RTM   [Missing]
|- Safer Mode Extensions                                         SMX   [Missing]
|- Self-Snoop                                                     SS   [Missing]
|- Supervisor-Mode Access Prevention                            SMAP   [Capable]
|- Supervisor-Mode Execution Prevention                         SMEP   [Capable]
|- Trailing Bit Manipulation                                     TBM   [Missing]
|- Translation Cache Extension                                   TCE   [Capable]
|- Time Stamp Counter                                            TSC [Invariant]
|- Time Stamp Counter Deadline                          TSC-DEADLINE   [Missing]
|- TSX Force Abort MSR Register                            TSX-ABORT   [Missing]
|- TSX Suspend Load Address Tracking                       TSX-LDTRK   [Missing]
|- User-Mode Instruction Prevention                             UMIP   [Capable]
|- Virtual Mode Extension                                        VME   [Capable]
|- Virtual Machine Extensions                                    VMX   [Missing]
|- Write Back & Do Not Invalidate Cache                     WBNOINVD   [Capable]
|- Extended xAPIC Support                                     x2APIC   [  xAPIC]
|- AVIC controller for x2APIC                                 x2AVIC   [Capable]
|- XSAVE/XSTOR States                                          XSAVE   [Capable]
|- xTPR Update Control                                          xTPR   [Missing]
|- Extended Operation Support                                    XOP   [Missing]
Mitigation mechanisms
|- Indirect Branch Restricted Speculation                       IBRS   [Capable]
   |- IBRS Always-On preferred by processor                            [ Unable]
   |- IBRS preferred over software solution                            [Capable]
   |- IBRS provides same speculation limits                            [Capable]
|- Indirect Branch Prediction Barrier                           IBPB   [Capable]
|- Single Thread Indirect Branch Predictor                     STIBP   [ Enable]
|- Speculative Store Bypass Disable                             SSBD   [Capable]
   |- SSBD use VIRT_SPEC_CTRL register                                 [ Unable]
   |- SSBD not needed on this processor                                [ Unable]
|- No Branch Type Confusion                                   BTC_NO   [Capable]
|- BTC on Non-Branch instruction                            BTC-NOBR   [Capable]
|- Limited Early Redirect Window                            AGENPICK   [ Unable]
|- Arch - No Fast Predictive Store Forwarding                   PSFD   [Capable]
|- Arch - Enhanced Predictive Store Forwarding                  EPSF   [Capable]
|- Arch - Cross Processor Information Leak                XPROC_LEAK   [ Unable]
Security Features
|- CET Shadow Stack features                                  CET-SS   [Capable]
|- Secure Init and Jump with Attestation                      SKINIT   [Capable]
|- Secure Encrypted Virtualization                               SEV   [Capable]
|- SEV - Encrypted State                                      SEV-ES   [Capable]
|- SEV - Secure Nested Paging                                SEV-SNP   [Capable]
|- Guest Mode Execute Trap                                      GMET   [Capable]
|- Supervisor Shadow Stack                                       SSS   [Capable]
|- VM Permission Levels                                         VMPL   [Capable]
|- VMPL Supervisor Shadow Stack                             VMPL-SSS   [Capable]
|- Secure Memory Encryption                                      SME   [Capable]
|- Transparent SME                                              TSME   [ Enable]
|- Secure Multi-Key Memory Encryption                         SME-MK   [Capable]
|- DRAM Data Scrambling                                    Scrambler   [ Enable]

Technologies
|- Instruction Cache Unit
   |- L1 IP Prefetcher                                          L1 HW IP   < ON>
|- Data Cache Unit
   |- L1 Prefetcher                                                L1 HW   < ON>
|- Cache Prefetchers
   |- L2 Prefetcher                                                L2 HW   < ON>
   |- L1 Stride Prefetcher                                     L1 Stride   < ON>
   |- L1 Region Prefetcher                                     L1 Region   < ON>
   |- L1 Burst Prefetch Mode                                    L1 Burst   < ON>
   |- L2 Stream HW Prefetcher                                  L2 Stream   <OFF>
   |- L2 Up/Down Prefetcher                                   L2 Up/Down   < ON>
|- System Management Mode                                       SMM-Lock   [ ON]
|- Simultaneous Multithreading                                       SMT   [ ON]
|- PowerNow!                                                         CnQ   [OFF]
|- Core C-States                                                     CCx   [ ON]
|- Core Performance Boost                                            CPB   < ON>
|- Watchdog Timer                                                    WDT   <OFF>
|- Virtualization                                                    SVM   [OFF]
   |- I/O MMU                                                      AMD-V   [OFF]
   |- Version                                                     [         N/A]
   |- Hypervisor                                                           [OFF]
   |- Vendor ID                                                   [         N/A]

Performance Monitoring
|- Version                                                        PM       [  2]
|- Counters:          General                   Fixed
|           {  6,  6, 16 } x 48 bits            3 x 64 bits
|- Enhanced Halt State                                           C1E       <OFF>
|- C2 UnDemotion                                                 C2U       < ON>
|- C3 UnDemotion                                                 C3U       < ON>
|- Core C6 State                                                 CC6       < ON>
|- Package C6 State                                              PC6       <OFF>
|- Legacy Frequency ID control                                   FID       [OFF]
|- Legacy Voltage ID control                                     VID       [OFF]
|- P-State Hardware Coordination Feedback                MPERF/APERF       [ ON]
|- Core C-States
   |- C-States Base Address                                      BAR   [ 0x413 ]
|- ACPI Processor C-States                                      _CST   [      2]
|- MONITOR/MWAIT
   |- State index:    #0    #1    #2    #3    #4    #5    #6    #7
   |- Sub C-State:     1     1     0     0     0     0     0     0
   |- Monitor-Mwait Extensions                                   EMX   [Capable]
   |- Interrupt Break-Event                                      IBE   [Capable]
|- Core Cycles                                                         [Capable]
|- Instructions Retired                                                [Capable]
|- Reference Cycles                                                    [Capable]
|- Last Level Cache References                                         [Capable]
|- Global Time Stamp Counter                                           [Missing]
|- Data Fabric Performance Counter                                     [Capable]
|- Core Performance Counter                                            [Capable]
|- Processor Performance Control                                _PCT   [Missing]
|- Performance Supported States                                 _PSS   [Missing]
|- Performance Present Capabilities                             _PPC   [Missing]
|- Continuous Performance Control                               _CPC   [Missing]

Power, Current & Thermal
|- Temperature Offset:Junction                                 TjMax [  0:  0 C]
|- CPPC Energy Preference                                        EPP   <      0>
|- Digital Thermal Sensor                                        DTS   [Capable]
|- Power Limit Notification                                      PLN   [Missing]
|- Package Thermal Management                                    PTM   [Missing]
|- Thermal Monitor 1                                             TTP   [ Enable]
|- Thermal Monitor 2                                             HTC   [ Enable]
|- Thermal Design Power                                          TDP   [Missing]
   |- Minimum Power                                              Min   [Missing]
   |- Maximum Power                                              Max   [Missing]
|- Thermal Design Power                                      Package   < Enable>
   |- Power Limit                                                PL1   <  400 W>
   |- Time Window                                                TW1   <   0 ns>
   |- Power Limit                                                PL2   <  400 W>
   |- Time Window                                                TW2   <   0 ns>
|- Thermal Design Power                                         Core   [Disable]
   |- Power Limit                                                PL1   [    0 W]
   |- Time Window                                                TW1   [   0 ns]
|- Thermal Design Power                                       Uncore   [Disable]
   |- Power Limit                                                PL1   [    0 W]
   |- Time Window                                                TW1   [   0 ns]
|- Thermal Design Power                                         DRAM   [Disable]
   |- Power Limit                                                PL1   [    0 W]
   |- Time Window                                                TW1   [   0 ns]
|- Thermal Design Power                                     Platform   [Disable]
   |- Power Limit                                                PL1   [    0 W]
   |- Time Window                                                TW1   [   0 ns]
   |- Power Limit                                                PL2   [    0 W]
   |- Time Window                                                TW2   [   0 ns]
|- Package Power Tracking                                        PPT   [Missing]
|- Electrical Design Current                                     EDC   [Missing]
|- Thermal Design Current                                        TDC   [Missing]
|- Core Thermal Point
|- Package Thermal Point
   |- Thermal Monitor Trip                                     Limit   [  115 C]
   |- HTC Temperature Limit                                    Limit   [    0 C]
   |- HTC Temperature Hysteresis                           Threshold   [    0 C]
|- Units
   |- Power                                               watt   [      Missing]
   |- Energy                                             joule   [  0.000015259]
   |- Window                                            second   [  0.000976562]

CPU Pkg  Apic  Core/Thread  Caches      (w)rite-Back (i)nclusive
 #   ID   ID CCD CCX ID/ID L1-Inst Way  L1-Data Way      L2  Way      L3  Way
000:BSP    0   0  0   0  0      32  8        32  8      1024  8 i  262144 16w
001:  0    2   0  0   1  0      32  8        32  8      1024  8 i  262144 16w
002:  0    4   0  0   2  0      32  8        32  8      1024  8 i  262144 16w
003:  0   32   4  4  16  0      32  8        32  8      1024  8 i  262144 16w
004:  0   34   4  4  17  0      32  8        32  8      1024  8 i  262144 16w
005:  0   36   4  4  18  0      32  8        32  8      1024  8 i  262144 16w
006:  0   16   2  2   8  0      32  8        32  8      1024  8 i  262144 16w
007:  0   18   2  2   9  0      32  8        32  8      1024  8 i  262144 16w
008:  0   20   2  2  10  0      32  8        32  8      1024  8 i  262144 16w
009:  0   48   6  6  24  0      32  8        32  8      1024  8 i  262144 16w
010:  0   50   6  6  25  0      32  8        32  8      1024  8 i  262144 16w
011:  0   52   6  6  26  0      32  8        32  8      1024  8 i  262144 16w
012:  0   24   2  3  12  0      32  8        32  8      1024  8 i  262144 16w
013:  0   26   2  3  13  0      32  8        32  8      1024  8 i  262144 16w
014:  0   28   2  3  14  0      32  8        32  8      1024  8 i  262144 16w
015:  0   56   6  7  28  0      32  8        32  8      1024  8 i  262144 16w
016:  0   58   6  7  29  0      32  8        32  8      1024  8 i  262144 16w
017:  0   60   6  7  30  0      32  8        32  8      1024  8 i  262144 16w
018:  0    8   0  1   4  0      32  8        32  8      1024  8 i  262144 16w
019:  0   10   0  1   5  0      32  8        32  8      1024  8 i  262144 16w
020:  0   12   0  1   6  0      32  8        32  8      1024  8 i  262144 16w
021:  0   40   4  5  20  0      32  8        32  8      1024  8 i  262144 16w
022:  0   42   4  5  21  0      32  8        32  8      1024  8 i  262144 16w
023:  0   44   4  5  22  0      32  8        32  8      1024  8 i  262144 16w
024:  0    1   0  0   0  1      32  8        32  8      1024  8 i  262144 16w
025:  0    3   0  0   1  1      32  8        32  8      1024  8 i  262144 16w
026:  0    5   0  0   2  1      32  8        32  8      1024  8 i  262144 16w
027:  0   33   4  4  16  1      32  8        32  8      1024  8 i  262144 16w
028:  0   35   4  4  17  1      32  8        32  8      1024  8 i  262144 16w
029:  0   37   4  4  18  1      32  8        32  8      1024  8 i  262144 16w
030:  0   17   2  2   8  1      32  8        32  8      1024  8 i  262144 16w
031:  0   19   2  2   9  1      32  8        32  8      1024  8 i  262144 16w
032:  0   21   2  2  10  1      32  8        32  8      1024  8 i  262144 16w
033:  0   49   6  6  24  1      32  8        32  8      1024  8 i  262144 16w
034:  0   51   6  6  25  1      32  8        32  8      1024  8 i  262144 16w
035:  0   53   6  6  26  1      32  8        32  8      1024  8 i  262144 16w
036:  0   25   2  3  12  1      32  8        32  8      1024  8 i  262144 16w
037:  0   27   2  3  13  1      32  8        32  8      1024  8 i  262144 16w
038:  0   29   2  3  14  1      32  8        32  8      1024  8 i  262144 16w
039:  0   57   6  7  28  1      32  8        32  8      1024  8 i  262144 16w
040:  0   59   6  7  29  1      32  8        32  8      1024  8 i  262144 16w
041:  0   61   6  7  30  1      32  8        32  8      1024  8 i  262144 16w
042:  0    9   0  1   4  1      32  8        32  8      1024  8 i  262144 16w
043:  0   11   0  1   5  1      32  8        32  8      1024  8 i  262144 16w
044:  0   13   0  1   6  1      32  8        32  8      1024  8 i  262144 16w
045:  0   41   4  5  20  1      32  8        32  8      1024  8 i  262144 16w
046:  0   43   4  5  21  1      32  8        32  8      1024  8 i  262144 16w
047:  0   45   4  5  22  1      32  8        32  8      1024  8 i  262144 16w

[ 0] HPE
[ 1] 1.58
[ 2] 01/04/2024
[ 3] HPE
[ 4] ProLiant DL345 Gen11
[ 5]
[ 6] M---3---W-
[ 7] P58792-B21
[ 8] ProLiant
[ 9] HPE
[10] ProLiant DL345 Gen11
[11]
[12] P---C---G---A-
[13] Number Of Devices:12\Maximum Capacity:6597069766656 kilobytes
[14] PROC 1 DIMM 1\PROC 1 DIMM 1
[15] PROC 1 DIMM 2\PROC 1 DIMM 2
[16] PROC 1 DIMM 3\PROC 1 DIMM 3
[17] PROC 1 DIMM 4\PROC 1 DIMM 4
[18] Samsung
[19] Samsung
[20] Samsung
[21] Samsung
[22] M321RYGA0BB0-CQKZJ
[23] M321RYGA0BB0-CQKZJ
[24] M321RYGA0BB0-CQKZJ
[25] M321RYGA0BB0-CQKZJ

                              Zen UMC  [14AD]
Controller #0                                                    Disabled
 Bus Rate  2400 MHz       Bus Speed 2426 MHz       REG DDR5 Speed 4852 MT/s

 Cha   CL  RCDr RCDw  RP  RAS   RC  RRDs RRDl FAW  WTRs WTRl  WR  clRR clWW
  #0   40   39   39   39   77  116    8   12   32    6   24   72    5   41
  #1   40   39   39   39   77  116    8   12   32    6   24   72    5   41
  #2   40   39   39   39   77  116    8   12   32    6   24   72    5   41
  #3   40   39   39   39   77  116    8   12   32    6   24   72    5   41
  #4   40   39   39   39   77  116    8   12   32    6   24   72    5   41
  #5   40   39   39   39   77  116    8   12   32    6   24   72    5   41
  #6   40   39   39   39   77  116    8   12   32    6   24   72    5   41
  #7   40   39   39   39   77  116    8   12   32    6   24   72    5   41
  #8   40   39   39   39   77  116    8   12   32    6   24   72    5   41
  #9   40   39   39   39   77  116    8   12   32    6   24   72    5   41
  #10  40   39   39   39   77  116    8   12   32    6   24   72    5   41
  #11  40   39   39   39   77  116    8   12   32    6   24   72    5   41
      CWL  RTP RdWr WrRd scWW sdWW ddWW scRR sdRR ddRR drRR drWW drWR drRRD
  #0   38   18   20    5    1    9    9    1    8    8    0    0    0    0
  #1   38   18   20    5    1    9    9    1    8    8    0    0    0    0
  #2   38   18   20    5    1    9    9    1    8    8    0    0    0    0
  #3   38   18   19    5    1    9    9    1    8    8    0    0    0    0
  #4   38   18   20    5    1    9    9    1    8    8    0    0    0    0
  #5   38   18   20    5    1    9    9    1    8    8    0    0    0    0
  #6   38   18   20    5    1    9    9    1    8    8    0    0    0    0
  #7   38   18   20    5    1    9    9    1    8    8    0    0    0    0
  #8   38   18   20    5    1    9    9    1    8    8    0    0    0    0
  #9   38   18   19    5    1    9    9    1    8    8    0    0    0    0
  #10  38   18   20    5    1    9    9    1    8    8    0    0    0    0
  #11  38   18   20    5    1    9    9    1    8    8    0    0    0    0
      REFI RFC1 RFC2 RFCsb RCPB RPPB BGS:Alt  Ban  Page  CKE  CMD  GDM  ECC
  #0  9347  983  528  456   0    0    ON OFF  R0W0   0    0   1T   OFF   1
  #1  9347  983  528  456   0    0    ON OFF  R0W0   0    0   1T   OFF   1
  #2  9347  983  528  456   0    0    ON OFF  R0W0   0    0   1T   OFF   1
  #3  9347  983  528  456   0    0    ON OFF  R0W0   0    0   1T   OFF   1
  #4  9347  983  528  456   0    0    ON OFF  R0W0   0    0   1T   OFF   1
  #5  9347  983  528  456   0    0    ON OFF  R0W0   0    0   1T   OFF   1
  #6  9347  983  528  456   0    0    ON OFF  R0W0   0    0   1T   OFF   1
  #7  9347  983  528  456   0    0    ON OFF  R0W0   0    0   1T   OFF   1
  #8  9347  983  528  456   0    0    ON OFF  R0W0   0    0   1T   OFF   1
  #9  9347  983  528  456   0    0    ON OFF  R0W0   0    0   1T   OFF   1
  #10 9347  983  528  456   0    0    ON OFF  R0W0   0    0   1T   OFF   1
  #11 9347  983  528  456   0    0    ON OFF  R0W0   0    0   1T   OFF   1
      MRD:PDA   MOD:PDA  WRMPR STAG PDM RDDATA WRD  WRL  RDL  XS   XP CPDED
  #0   32  32    32  32    24   36 0:P:0   31   6   29   36 1007   18   12
  #1   32  32    32  32    24   36 0:P:0   31   6   29   36 1007   18   12
  #2   32  32    32  32    24   36 0:P:0   31   6   29   36 1007   18   12
  #3   32  32    32  32    24   36 0:P:0   31   6   29   34 1007   18   12
  #4   32  32    32  32    24   36 0:P:0   31   6   29   36 1007   18   12
  #5   32  32    32  32    24   36 0:P:0   31   6   29   36 1007   18   12
  #6   32  32    32  32    24   36 0:P:0   31   6   29   36 1007   18   12
  #7   32  32    32  32    24   36 0:P:0   31   6   29   36 1007   18   12
  #8   32  32    32  32    24   36 0:P:0   31   6   29   36 1007   18   12
  #9   32  32    32  32    24   36 0:P:0   31   6   29   34 1007   18   12
  #10  32  32    32  32    24   36 0:P:0   31   6   29   34 1007   18   12
  #11  32  32    32  32    24   36 0:P:0   31   6   29   36 1007   18   12

 DIMM Geometry for channel #0
      Slot Bank Rank     Rows   Columns    Memory Size (MB)
       #0    32    1    131072      2048          65536  M321RYGA0BB0-CQKZJ
       #1
 DIMM Geometry for channel #1
      Slot Bank Rank     Rows   Columns    Memory Size (MB)
       #0    32    1    131072      2048          65536  M321RYGA0BB0-CQKZJ
       #1
 DIMM Geometry for channel #2
      Slot Bank Rank     Rows   Columns    Memory Size (MB)
       #0    32    1    131072      2048          65536  M321RYGA0BB0-CQKZJ
       #1
 DIMM Geometry for channel #3
      Slot Bank Rank     Rows   Columns    Memory Size (MB)
       #0    32    1    131072      2048          65536  M321RYGA0BB0-CQKZJ
       #1
 DIMM Geometry for channel #4
      Slot Bank Rank     Rows   Columns    Memory Size (MB)
       #0    32    1    131072      2048          65536  M321RYGA0BB0-CQKZJ
       #1
 DIMM Geometry for channel #5
      Slot Bank Rank     Rows   Columns    Memory Size (MB)
       #0    32    1    131072      2048          65536  M321RYGA0BB0-CQKZJ
       #1
 DIMM Geometry for channel #6
      Slot Bank Rank     Rows   Columns    Memory Size (MB)
       #0    32    1    131072      2048          65536  M321RYGA0BB0-CQKZJ
       #1
 DIMM Geometry for channel #7
      Slot Bank Rank     Rows   Columns    Memory Size (MB)
       #0    32    1    131072      2048          65536  M321RYGA0BB0-CQKZJ
       #1
 DIMM Geometry for channel #8
      Slot Bank Rank     Rows   Columns    Memory Size (MB)
       #0    32    1    131072      2048          65536  M321RYGA0BB0-CQKZJ
       #1
 DIMM Geometry for channel #9
      Slot Bank Rank     Rows   Columns    Memory Size (MB)
       #0    32    1    131072      2048          65536  M321RYGA0BB0-CQKZJ
       #1
 DIMM Geometry for channel #10
      Slot Bank Rank     Rows   Columns    Memory Size (MB)
       #0    32    1    131072      2048          65536  M321RYGA0BB0-CQKZJ
       #1
 DIMM Geometry for channel #11
      Slot Bank Rank     Rows   Columns    Memory Size (MB)
       #0    32    1    131072      2048          65536  M321RYGA0BB0-CQKZJ
       #1

Linux:
|- Release                                                      [6.5.0-1016-oem]
|- Version         [#17-Ubuntu SMP PREEMPT_DYNAMIC Thu Feb 22 11:09:43 UTC 2024]
|- Machine                                                              [x86_64]
Memory:
|- Total RAM                                                       1188654888 KB
|- Shared RAM                                                       860411708 KB
|- Free RAM                                                          62023172 KB
|- Buffer RAM                                                          833880 KB
|- Total High                                                               0 KB
|- Free High                                                                0 KB
Clock Source                                                  <             tsc>
CPU-Freq driver                                               [      amd-pstate]
Governor                                                      [     performance]
CPU-Idle driver                                               [       acpi_idle]
|- Idle Limit                                                 [              C2]
   |- State        POLL      C1      C2
   |-           CPUIDLE ACPI FF ACPI IO
   |- Power          -1       0       0
   |- Latency         0       1      18
   |- Residency       0       2      36

CPU Freq(MHz) VID  Vcore  TMP(C)    Accumulator       Energy(J)     Power(W)
000 4162.79   183  1.1438  100  000000000000258595    3.945846558   3.945846558
001 1153.21   183  1.1438  100  000000000000160368    2.447021484   2.447021484
002 1081.02   183  1.1438  100  000000000000154294    2.354339600   2.354339600
003 1257.23   183  1.1438  100  000000000000173854    2.652801514   2.652801514
004 1277.75   183  1.1438  100  000000000000167559    2.556747437   2.556747437
005 1286.78   183  1.1438  100  000000000000167985    2.563247681   2.563247681
006 1323.43   182  1.1375  100  000000000000186172    2.840759277   2.840759277
007 1501.77   181  1.1313  100  000000000000204768    3.124511719   3.124511719
008 1393.65   181  1.1313  100  000000000000198337    3.026382446   3.026382446
009 1463.22   181  1.1313  100  000000000000198736    3.032470703   3.032470703
010 1377.03   182  1.1375  100  000000000000193596    2.954040527   2.954040527
011 1445.08   182  1.1375  100  000000000000194932    2.974426270   2.974426270
012 1389.25   183  1.1438  100  000000000000203761    3.109146118   3.109146118
013 1424.31   181  1.1313  100  000000000000188212    2.871887207   2.871887207
014 1277.50   183  1.1438  100  000000000000177562    2.709381104   2.709381104
015 1364.04   183  1.1438  100  000000000000186556    2.846618652   2.846618652
016 4162.18   183  1.1438  100  000000000000226852    3.461486816   3.461486816
017 1311.32   181  1.1313  100  000000000000176960    2.700195312   2.700195312
018 4162.79   181  1.1313  100  000000000000375918    5.736053467   5.736053467
019 1128.81   182  1.1375  100  000000000000170545    2.602310181   2.602310181
020 1497.25   182  1.1375  100  000000000000184583    2.816513062   2.816513062
021 4157.43   181  1.1313  100  000000000000238430    3.638153076   3.638153076
022 1056.63   182  1.1375  100  000000000000158001    2.410903931   2.410903931
023 1301.44   182  1.1375  100  000000000000212187    3.237716675   3.237716675
024 1119.62   183  1.1438  100  000000000000000000    0.000000000   0.000000000
025 1104.64   183  1.1438  100  000000000000000000    0.000000000   0.000000000
026 1104.00   183  1.1438  100  000000000000000000    0.000000000   0.000000000
027 1293.57   181  1.1313  100  000000000000000000    0.000000000   0.000000000
028 1181.20   181  1.1313  100  000000000000000000    0.000000000   0.000000000
029 1160.12   183  1.1438  100  000000000000000000    0.000000000   0.000000000
030 1221.64   182  1.1375  100  000000000000000000    0.000000000   0.000000000
031 1544.27   182  1.1375  100  000000000000000000    0.000000000   0.000000000
032 1402.13   182  1.1375  100  000000000000000000    0.000000000   0.000000000
033 1342.06   182  1.1375  100  000000000000000000    0.000000000   0.000000000
034 1431.90   182  1.1375  100  000000000000000000    0.000000000   0.000000000
035 1417.87   182  1.1375  100  000000000000000000    0.000000000   0.000000000
036 1871.26   183  1.1438  100  000000000000000000    0.000000000   0.000000000
037 1439.78   183  1.1438  100  000000000000000000    0.000000000   0.000000000
038 1286.90   183  1.1438  100  000000000000000000    0.000000000   0.000000000
039 1385.63   183  1.1438  100  000000000000000000    0.000000000   0.000000000
040 1265.93   183  1.1438  100  000000000000000000    0.000000000   0.000000000
041 1245.41   183  1.1438  100  000000000000000000    0.000000000   0.000000000
042 1366.77   182  1.1375  100  000000000000000000    0.000000000   0.000000000
043 1272.81   182  1.1375  100  000000000000000000    0.000000000   0.000000000
044 1258.59   182  1.1375  100  000000000000000000    0.000000000   0.000000000
045 1394.37   182  1.1375  100  000000000000000000    0.000000000   0.000000000
046 1186.81   182  1.1375  100  000000000000000000    0.000000000   0.000000000
047 2269.01   182  1.1375  100  000000000000000000    0.000000000   0.000000000

             Package[0]    Cores         Uncore        Memory        Platform
Energy(J): 157.293884277  72.612960815  29.650711060   0.000000000   0.000000000
Power(W) : 157.293884277  72.612960815  29.650711060   0.000000000   0.000000000


CPU     IPS            IPC            CPI
000     1.104910/s     1.105073/c     0.904918/i
001     0.239565/s     1.254067/c     0.797405/i
002     0.226498/s     1.167384/c     0.856616/i
003     0.245160/s     1.353565/c     0.738790/i
004     0.223878/s     1.152326/c     0.867810/i
005     0.199901/s     1.135369/c     0.880771/i
006     0.345716/s     1.635588/c     0.611401/i
007     0.397520/s     1.537115/c     0.650569/i
008     0.395279/s     1.579540/c     0.633096/i
009     0.526254/s     1.842706/c     0.542680/i
010     0.393380/s     1.473119/c     0.678832/i
011     0.557895/s     1.807423/c     0.553274/i
012     0.306117/s     1.028320/c     0.972460/i
013     0.339535/s     0.919952/c     1.087013/i
014     0.228797/s     1.056098/c     0.946881/i
015     0.297207/s     0.679771/c     1.471084/i
016     0.452873/s     0.512993/c     1.949343/i
017     0.219807/s     0.985290/c     1.014930/i
018     2.131657/s     2.131656/c     0.469119/i
019     0.474259/s     1.718207/c     0.582002/i
020     0.410603/s     1.612979/c     0.619971/i
021     0.483934/s     1.244447/c     0.803570/i
022     0.699578/s     0.843688/c     1.185272/i
023     0.487634/s     1.793516/c     0.557564/i
024     0.238627/s     1.062101/c     0.941530/i
025     0.224874/s     1.204314/c     0.830348/i
026     0.271348/s     1.318219/c     0.758599/i
027     0.199718/s     1.087351/c     0.919666/i
028     0.276756/s     1.234665/c     0.809936/i
029     0.232171/s     1.248764/c     0.800792/i
030     0.480750/s     1.830185/c     0.546393/i
031     0.332710/s     1.646405/c     0.607384/i
032     0.461341/s     1.846786/c     0.541481/i
033     0.501015/s     1.723937/c     0.580068/i
034     0.627693/s     1.864687/c     0.536283/i
035     0.520771/s     1.775528/c     0.563213/i
036     0.282157/s     1.045838/c     0.956171/i
037     0.242157/s     1.011075/c     0.989047/i
038     0.256461/s     1.107056/c     0.903297/i
039     0.295813/s     1.022453/c     0.978040/i
040     0.277113/s     0.827807/c     1.208012/i
041     0.365593/s     1.299289/c     0.769652/i
042     0.331352/s     1.232642/c     0.811265/i
043     0.370741/s     1.439792/c     0.694545/i
044     0.458952/s     1.647577/c     0.606952/i
045     0.434989/s     1.614336/c     0.619450/i
046     0.372586/s     1.173434/c     0.852200/i
047     0.340160/s     1.407639/c     0.710410/i


CPU Freq(MHz) VID  Min     Vcore   Max
000 4161.74   184  1.1250  1.1500  1.1750
001  915.41   184  1.1250  1.1500  1.1750
002  940.46   184  1.1250  1.1500  1.1750
003  994.28   184  1.1250  1.1500  1.1750
004  935.99   184  1.1250  1.1500  1.1750
005  915.42   184  1.1250  1.1500  1.1750
006 1176.63   184  1.1188  1.1500  1.1687
007 1156.77   183  1.1188  1.1438  1.1687
008  973.08   183  1.1188  1.1438  1.1687
009 1267.98   183  1.1188  1.1438  1.1687
010 1209.39   184  1.1188  1.1500  1.1687
011 1208.11   184  1.1188  1.1500  1.1687
012 1396.06   184  1.1250  1.1500  1.1750
013 1113.36   184  1.1250  1.1500  1.1750
014 1367.12   184  1.1250  1.1500  1.1750
015 1428.13   184  1.1250  1.1500  1.1750
016 2884.03   184  1.1250  1.1500  1.1750
017 1109.87   184  1.1250  1.1500  1.1750
018 3543.52   183  1.1188  1.1438  1.1687
019 1130.11   184  1.1188  1.1500  1.1687
020 1234.25   184  1.1188  1.1500  1.1625
021 1402.24   183  1.1188  1.1438  1.1687
022 2245.05   184  1.1188  1.1500  1.1687
023 1505.33   184  1.1188  1.1500  1.1687
024  946.01   184  1.1250  1.1500  1.1750
025  814.30   184  1.1250  1.1500  1.1750
026  999.62   184  1.1250  1.1500  1.1750
027  860.58   184  1.1250  1.1500  1.1750
028  922.15   184  1.1250  1.1500  1.1750
029 1658.44   184  1.1250  1.1500  1.1750
030 1288.85   183  1.1188  1.1438  1.1687
031 1174.27   184  1.1188  1.1500  1.1687
032 1238.16   184  1.1188  1.1500  1.1687
033 1341.76   184  1.1188  1.1500  1.1625
034 1536.40   183  1.1188  1.1438  1.1687
035 1407.95   184  1.1188  1.1500  1.1687
036 1329.28   184  1.1250  1.1500  1.1750
037 1235.38   184  1.1250  1.1500  1.1750
038 1417.60   184  1.1250  1.1500  1.1750
039 1148.07   184  1.1250  1.1500  1.1750
040 2546.99   184  1.1250  1.1500  1.1750
041 1416.93   184  1.1250  1.1500  1.1750
042 1290.17   184  1.1188  1.1500  1.1687
043 1122.19   184  1.1188  1.1500  1.1687
044 1035.74   184  1.1188  1.1500  1.1625
045 1281.88   184  1.1188  1.1500  1.1687
046 3336.83   184  1.1188  1.1500  1.1687
047 1475.88   184  1.1188  1.1500  1.1687


CPU Freq(MHz)    Accumulator      Min  Energy(J) Max    Min  Power(W)  Max
000 4163.47  000000000000256543    3.55   3.91   4.61    3.55   3.91   4.61
001 1103.67  000000000000157973    1.09   2.41   3.73    1.09   2.41   3.73
002  999.39  000000000000157195    1.04   2.40   3.75    1.04   2.40   3.75
003 2512.29  000000000000272538    0.84   4.16   4.16    0.84   4.16   4.16
004 1305.29  000000000000173483    0.95   2.65   4.29    0.95   2.65   4.29
005 1301.90  000000000000176257    1.00   2.69   4.09    1.00   2.69   4.09
006 1525.53  000000000000213313    1.18   3.25   4.99    1.18   3.25   4.99
007 1665.51  000000000000220819    1.11   3.37   4.66    1.11   3.37   4.66
008 1448.38  000000000000209622    1.15   3.20   4.05    1.15   3.20   4.05
009 1383.93  000000000000197180    0.67   3.01   4.49    0.67   3.01   4.49
010 1503.09  000000000000239907    0.87   3.66   4.49    0.87   3.66   4.49
011 1462.02  000000000000202506    0.94   3.09   4.51    0.94   3.09   4.51
012 1779.47  000000000000214334    1.26   3.27   6.10    1.26   3.27   6.10
013 1541.88  000000000000199430    1.48   3.04   4.17    1.48   3.04   4.17
014 1555.92  000000000000200559    1.32   3.06   5.31    1.32   3.06   5.31
015 1566.82  000000000000196099    1.24   2.99   3.89    1.24   2.99   3.89
016 2710.52  000000000000222903    1.21   3.40   3.81    1.21   3.40   3.81
017 1422.75  000000000000195765    1.24   2.99   4.46    1.24   2.99   4.46
018 4127.85  000000000000384027    1.51   5.86   5.91    1.51   5.86   5.91
019 1446.72  000000000000193095    1.11   2.95   5.75    1.11   2.95   5.75
020 1634.84  000000000000200099    1.17   3.05   5.80    1.17   3.05   5.80
021 1429.24  000000000000196839    0.79   3.00   5.86    0.79   3.00   5.86
022 1497.26  000000000000244236    0.61   3.73   5.88    0.61   3.73   5.88
023 1464.08  000000000000196131    0.47   2.99   5.85    0.47   2.99   5.85
024 1102.48  000000000000000000    0.00   0.00   0.00    0.00   0.00   0.00
025 1059.67  000000000000000000    0.00   0.00   0.00    0.00   0.00   0.00
026 1156.61  000000000000000000    0.00   0.00   0.00    0.00   0.00   0.00
027 1329.31  000000000000000000    0.00   0.00   0.00    0.00   0.00   0.00
028 1225.47  000000000000000000    0.00   0.00   0.00    0.00   0.00   0.00
029 1267.69  000000000000000000    0.00   0.00   0.00    0.00   0.00   0.00
030 1634.24  000000000000000000    0.00   0.00   0.00    0.00   0.00   0.00
031 1679.72  000000000000000000    0.00   0.00   0.00    0.00   0.00   0.00
032 1598.17  000000000000000000    0.00   0.00   0.00    0.00   0.00   0.00
033 1291.64  000000000000000000    0.00   0.00   0.00    0.00   0.00   0.00
034 2012.85  000000000000000000    0.00   0.00   0.00    0.00   0.00   0.00
035 1338.42  000000000000000000    0.00   0.00   0.00    0.00   0.00   0.00
036 1642.79  000000000000000000    0.00   0.00   0.00    0.00   0.00   0.00
037 1512.87  000000000000000000    0.00   0.00   0.00    0.00   0.00   0.00
038 1577.19  000000000000000000    0.00   0.00   0.00    0.00   0.00   0.00
039 1479.53  000000000000000000    0.00   0.00   0.00    0.00   0.00   0.00
040 2579.83  000000000000000000    0.00   0.00   0.00    0.00   0.00   0.00
041 1503.37  000000000000000000    0.00   0.00   0.00    0.00   0.00   0.00
042 1886.47  000000000000000000    0.00   0.00   0.00    0.00   0.00   0.00
043 1454.90  000000000000000000    0.00   0.00   0.00    0.00   0.00   0.00
044 1555.02  000000000000000000    0.00   0.00   0.00    0.00   0.00   0.00
045 1629.49  000000000000000000    0.00   0.00   0.00    0.00   0.00   0.00
046 4164.05  000000000000000000    0.00   0.00   0.00    0.00   0.00   0.00
047 1460.64  000000000000000000    0.00   0.00   0.00    0.00   0.00   0.00

Energy(J)  Package[0]         Cores               Uncore              Memory
 135.36159.76192.24   43.11 78.14 90.08    0.46 29.65 88.04    0.00  0.00  0.00
Power(W)
 135.36159.76192.24   43.11 78.14 90.08    0.46 29.65 88.04    0.00  0.00  0.00

lspci -nm output:

00:00.0 "0600" "1022" "14a4" -r01 "1022" "14a4"
00:00.3 "0807" "1022" "14a6" "1022" "14a6"
00:01.0 "0600" "1022" "149f" -r01 "" ""
00:01.1 "0604" "1022" "14ab" -r01 "" ""
00:01.2 "0604" "1022" "14ab" -r01 "" ""
00:01.3 "0604" "1022" "14ab" -r01 "" ""
00:01.4 "0604" "1022" "14ab" -r01 "" ""
00:02.0 "0600" "1022" "149f" -r01 "" ""
00:03.0 "0600" "1022" "149f" -r01 "" ""
00:03.1 "0604" "1022" "14a5" -r01 "" ""
00:04.0 "0600" "1022" "149f" -r01 "" ""
00:05.0 "0600" "1022" "149f" -r01 "" ""
00:05.1 "0604" "1022" "14aa" -r01 "" ""
00:07.0 "0600" "1022" "149f" -r01 "" ""
00:07.1 "0604" "1022" "14a7" -r01 "" ""
00:07.2 "0604" "1022" "14a7" -r01 "" ""
00:14.0 "0c05" "1022" "790b" -r71 "1590" "0278"
00:14.3 "0601" "1022" "790e" -r51 "1022" "790e"
00:18.0 "0600" "1022" "14ad" "" ""
00:18.1 "0600" "1022" "14ae" "" ""
00:18.2 "0600" "1022" "14af" "" ""
00:18.3 "0600" "1022" "14b0" "" ""
00:18.4 "0600" "1022" "14b1" "" ""
00:18.5 "0600" "1022" "14b2" "" ""
00:18.6 "0600" "1022" "14b3" "" ""
00:18.7 "0600" "1022" "14b4" "" ""
01:00.0 "1300" "1022" "14ac" -r01 "1022" "14ac"
01:00.1 "0880" "1022" "14dc" "1022" "14dc"
01:00.4 "0c03" "1022" "14c9" -rda -p30 "1590" "0278"
01:00.5 "1080" "1022" "14ca" "1022" "14ca"
02:00.0 "0106" "1022" "7901" -r91 -p01 "1590" "02f0"
02:00.1 "0106" "1022" "7901" -r91 -p01 "1590" "02f0"
40:00.0 "0600" "1022" "14a4" -r01 "1022" "14a4"
40:00.3 "0807" "1022" "14a6" "1022" "14a6"
40:01.0 "0600" "1022" "149f" -r01 "" ""
40:01.1 "0604" "1022" "14ab" -r01 "" ""
40:01.2 "0604" "1022" "14ab" -r01 "" ""
40:01.3 "0604" "1022" "14ab" -r01 "" ""
40:01.4 "0604" "1022" "14ab" -r01 "" ""
40:02.0 "0600" "1022" "149f" -r01 "" ""
40:03.0 "0600" "1022" "149f" -r01 "" ""
40:03.1 "0604" "1022" "14a5" -r01 "" ""
40:03.2 "0604" "1022" "14a5" -r01 "" ""
40:03.3 "0604" "1022" "14a5" -r01 "" ""
40:04.0 "0600" "1022" "149f" -r01 "" ""
40:05.0 "0600" "1022" "149f" -r01 "" ""
40:07.0 "0600" "1022" "149f" -r01 "" ""
40:07.1 "0604" "1022" "14a7" -r01 "" ""
41:00.0 "1300" "1022" "14ac" -r01 "1022" "14ac"
41:00.1 "0880" "1022" "14dc" "1022" "14dc"
46:00.0 "0200" "14e4" "16d8" -r01 "14e4" "1592"
46:00.1 "0200" "14e4" "16d8" -r01 "14e4" "1592"
80:00.0 "0600" "1022" "14a4" -r01 "1022" "14a4"
80:00.3 "0807" "1022" "14a6" "1022" "14a6"
80:01.0 "0600" "1022" "149f" -r01 "" ""
80:01.1 "0604" "1022" "14ab" -r01 "" ""
80:01.2 "0604" "1022" "14ab" -r01 "" ""
80:01.3 "0604" "1022" "14ab" -r01 "" ""
80:01.4 "0604" "1022" "14ab" -r01 "" ""
80:02.0 "0600" "1022" "149f" -r01 "" ""
80:03.0 "0600" "1022" "149f" -r01 "" ""
80:03.1 "0604" "1022" "14a5" -r01 "" ""
80:04.0 "0600" "1022" "149f" -r01 "" ""
80:05.0 "0600" "1022" "149f" -r01 "" ""
80:07.0 "0600" "1022" "149f" -r01 "" ""
80:07.1 "0604" "1022" "14a7" -r01 "" ""
81:00.0 "1300" "1022" "14ac" -r01 "1022" "14ac"
81:00.1 "0880" "1022" "14dc" "1022" "14dc"
86:00.0 "0604" "111d" "8018" -r0e "" ""
87:02.0 "0604" "111d" "8018" -r0e "" ""
87:04.0 "0604" "111d" "8018" -r0e "" ""
88:00.0 "0200" "8086" "10bc" -r06 "103c" "704b"
88:00.1 "0200" "8086" "10bc" -r06 "103c" "704b"
89:00.0 "0200" "8086" "10bc" -r06 "103c" "704b"
89:00.1 "0200" "8086" "10bc" -r06 "103c" "704b"
c0:00.0 "0600" "1022" "14a4" -r01 "1022" "14a4"
c0:00.3 "0807" "1022" "14a6" "1022" "14a6"
c0:01.0 "0600" "1022" "149f" -r01 "" ""
c0:01.1 "0604" "1022" "14ab" -r01 "" ""
c0:01.2 "0604" "1022" "14ab" -r01 "" ""
c0:01.3 "0604" "1022" "14ab" -r01 "" ""
c0:01.4 "0604" "1022" "14ab" -r01 "" ""
c0:02.0 "0600" "1022" "149f" -r01 "" ""
c0:03.0 "0600" "1022" "149f" -r01 "" ""
c0:03.1 "0604" "1022" "14a5" -r01 "" ""
c0:03.2 "0604" "1022" "14a5" -r01 "" ""
c0:03.3 "0604" "1022" "14a5" -r01 "" ""
c0:04.0 "0600" "1022" "149f" -r01 "" ""
c0:05.0 "0600" "1022" "149f" -r01 "" ""
c0:05.2 "0604" "1022" "14aa" -r01 "" ""
c0:07.0 "0600" "1022" "149f" -r01 "" ""
c0:07.1 "0604" "1022" "14a7" -r01 "" ""
c0:07.2 "0604" "1022" "14a7" -r01 "" ""
c1:00.0 "0880" "103c" "3306" -r08 "1590" "00e4"
c1:00.1 "0300" "102b" "0538" -r03 "1590" "00e4"
c1:00.2 "0880" "103c" "3307" -r08 "1590" "00e4"
c1:00.4 "0c03" "103c" "22f6" -r01 -p20 "1590" "00e4"
c2:00.0 "1300" "1022" "14ac" -r01 "1022" "14ac"
c2:00.1 "0880" "1022" "14dc" "1022" "14dc"
c2:00.4 "0c03" "1022" "14c9" -rda -p30 "1590" "0278"
c3:00.0 "0106" "1022" "7901" -r91 -p01 "1590" "02f0"
c3:00.1 "0106" "1022" "7901" -r91 -p01 "1590" "02f0"
c8:00.0 "0104" "1000" "10e2" "1590" "03c8"

0 replies

cyring · 2024-03-17T19:38:04Z

cyring
Mar 17, 2024
Maintainer

Which temperature are we reading when System is idling ?

corefreq-cli -C 1 -n -c 1

0 replies

garceri · 2024-03-17T23:52:21Z

garceri
Mar 17, 2024
Author

Let the server idle for ten minutes, Temp readings reported by corefreq seem to be off:
And, are the Mhz numbers correct ? ie can the cpu cores run at 2.11 Mhz) ?

This is what lm-sensors report

power_meter-acpi-0
Adapter: ACPI interface
power1:      531.00 W  (interval = 300.00 s)

bnxt_en-pci-4600
Adapter: PCI adapter
temp1:        +51.0°C

k10temp-pci-00c3
Adapter: PCI adapter
Tctl:         +43.8°C
Tccd1:        +32.2°C
Tccd2:        +32.0°C
Tccd3:        +33.6°C
Tccd4:        +33.1°C
Tccd5:        +31.8°C
Tccd6:        +30.8°C
Tccd7:        +32.2°C
Tccd8:        +31.1°C

bnxt_en-pci-4601
Adapter: PCI adapter
temp1:        +51.0°C

this is what the ILO reports:

and finally this is what corefreq reports:

CPU Freq(MHz) VID  Vcore  TMP(C)    Accumulator       Energy(J)     Power(W)
000    4.06   193  1.2063   92  000000000000002464    0.037597656   0.037597656
001    1.05   193  1.2063   92  000000000000002008    0.030639648   0.030639648
002    0.90   193  1.2063   92  000000000000002035    0.031051636   0.031051636
003    1.17   193  1.2063   92  000000000000002027    0.030929565   0.030929565
004    6.60   193  1.2063   92  000000000000002387    0.036422729   0.036422729
005    1.52   193  1.2063   92  000000000000002029    0.030960083   0.030960083
006    1.15   193  1.2063   92  000000000000002084    0.031799316   0.031799316
007    1.20   193  1.2063   92  000000000000002044    0.031188965   0.031188965
008    0.92   193  1.2063   92  000000000000007890    0.120391846   0.120391846
009    0.91   193  1.2063   92  000000000000002076    0.031677246   0.031677246
010    1.05   193  1.2063   92  000000000000006834    0.104278564   0.104278564
011    0.69   193  1.2063   92  000000000000002018    0.030792236   0.030792236
012    7.45   193  1.2063   92  000000000000005280    0.080566406   0.080566406
013   22.15   193  1.2063   92  000000000000010238    0.156219482   0.156219482
014   18.18   193  1.2063   92  000000000000037448    0.571411133   0.571411133
015    7.70   193  1.2063   92  000000000000002270    0.034637451   0.034637451
016    1.52   193  1.2063   92  000000000000002144    0.032714844   0.032714844
017    1.75   193  1.2063   92  000000000000003654    0.055755615   0.055755615
018    3.59   193  1.2063   92  000000000000002121    0.032363892   0.032363892
019    1.04   193  1.2063   92  000000000000002005    0.030593872   0.030593872
020    1.05   193  1.2063   92  000000000000002036    0.031066895   0.031066895
021    1.17   193  1.2063   92  000000000000002007    0.030624390   0.030624390
022    1.10   193  1.2063   92  000000000000002004    0.030578613   0.030578613
023    0.63   193  1.2063   92  000000000000002012    0.030700684   0.030700684
024    8.84   193  1.2063   92  000000000000000000    0.000000000   0.000000000
025    0.84   193  1.2063   92  000000000000000000    0.000000000   0.000000000
026    0.96   193  1.2063   92  000000000000000000    0.000000000   0.000000000
027    1.01   193  1.2063   92  000000000000000000    0.000000000   0.000000000
028    0.89   193  1.2063   92  000000000000000000    0.000000000   0.000000000
029    0.92   193  1.2063   92  000000000000000000    0.000000000   0.000000000
030    0.89   193  1.2063   92  000000000000000000    0.000000000   0.000000000
031    2.82   193  1.2063   92  000000000000000000    0.000000000   0.000000000
032   66.44   193  1.2063   92  000000000000000000    0.000000000   0.000000000
033    1.51   193  1.2063   92  000000000000000000    0.000000000   0.000000000
034   57.22   193  1.2063   92  000000000000000000    0.000000000   0.000000000
035    0.92   193  1.2063   92  000000000000000000    0.000000000   0.000000000
036   34.75   193  1.2063   92  000000000000000000    0.000000000   0.000000000
037    9.56   193  1.2063   92  000000000000000000    0.000000000   0.000000000
038  451.17   193  1.2063   92  000000000000000000    0.000000000   0.000000000
039    2.54   193  1.2063   92  000000000000000000    0.000000000   0.000000000
040    3.01   193  1.2063   92  000000000000000000    0.000000000   0.000000000
041   13.19   193  1.2063   92  000000000000000000    0.000000000   0.000000000
042    1.00   193  1.2063   92  000000000000000000    0.000000000   0.000000000
043    1.06   193  1.2063   92  000000000000000000    0.000000000   0.000000000
044    1.57   193  1.2063   92  000000000000000000    0.000000000   0.000000000
045    1.26   193  1.2063   92  000000000000000000    0.000000000   0.000000000
046    1.27   193  1.2063   92  000000000000000000    0.000000000   0.000000000
047    1.16   193  1.2063   92  000000000000000000    0.000000000   0.000000000

             Package[0]    Cores         Uncore        Memory        Platform
Energy(J): 100.496719360   1.664962769  29.650711060   0.000000000   0.000000000
Power(W) : 100.496719360   1.664962769  29.650711060   0.000000000   0.000000000


CPU Freq(MHz) Ratio  Turbo  C0(%)  C1(%)  C3(%)  C6(%)  C7(%)  Min TMP:TS  Max
000    5.23 ( 0.05)   0.13   0.12  99.88   0.00   0.00   0.00  91 / 93:751/104
001    0.91 ( 0.01)   0.02   0.02  99.98   0.00   0.00   0.00  91 / 93:751/104
002    0.90 ( 0.01)   0.02   0.02  99.98   0.00   0.00   0.00  91 / 93:751/104
003    1.94 ( 0.02)   0.05   0.05  99.95   0.00   0.00   0.00  91 / 93:751/104
004   12.37 ( 0.12)   0.31   0.29  99.71   0.00   0.00   0.00  91 / 93:751/104
005    0.72 ( 0.01)   0.02   0.02  99.98   0.00   0.00   0.00  91 / 93:751/104
006   36.18 ( 0.36)   0.89   0.84  99.16   0.00   0.00   0.00  91 / 93:751/104
007    2.09 ( 0.02)   0.05   0.05  99.95   0.00   0.00   0.00  91 / 93:751/104
008    1.74 ( 0.02)   0.04   0.04  99.96   0.00   0.00   0.00  91 / 93:751/104
009    0.91 ( 0.01)   0.02   0.02  99.98   0.00   0.00   0.00  91 / 93:751/104
010    1.22 ( 0.01)   0.03   0.03  99.97   0.00   0.00   0.00  91 / 93:751/104
011    0.74 ( 0.01)   0.02   0.02  99.98   0.00   0.00   0.00  91 / 93:751/104
012  130.61 ( 1.29)   3.23   3.04  96.96   0.00   0.00   0.00  91 / 93:751/104
013   10.54 ( 0.10)   0.26   0.25  99.75   0.00   0.00   0.00  91 / 93:751/104
014    8.74 ( 0.09)   0.22   0.20  99.80   0.00   0.00   0.00  91 / 93:751/104
015    7.14 ( 0.07)   0.18   0.17  99.83   0.00   0.00   0.00  91 / 93:751/104
016    1.18 ( 0.01)   0.03   0.03  99.97   0.00   0.00   0.00  91 / 93:751/104
017    1.55 ( 0.02)   0.04   0.04  99.96   0.00   0.00   0.00  91 / 93:751/104
018   58.32 ( 0.58)   1.44   1.36  98.64   0.00   0.00   0.00  91 / 93:751/104
019    2.11 ( 0.02)   0.05   0.05  99.95   0.00   0.00   0.00  91 / 93:751/104
020    0.88 ( 0.01)   0.02   0.02  99.98   0.00   0.00   0.00  91 / 93:751/104
021    1.03 ( 0.01)   0.03   0.02  99.98   0.00   0.00   0.00  91 / 93:751/104
022    1.05 ( 0.01)   0.03   0.02  99.98   0.00   0.00   0.00  91 / 93:751/104
023    0.82 ( 0.01)   0.02   0.02  99.98   0.00   0.00   0.00  91 / 93:751/104
024    1.06 ( 0.01)   0.03   0.02  99.98   0.00   0.00   0.00  91 / 93:751/104
025    1.01 ( 0.01)   0.02   0.02  99.98   0.00   0.00   0.00  91 / 93:751/104
026    1.04 ( 0.01)   0.03   0.02  99.98   0.00   0.00   0.00  91 / 93:751/104
027    0.74 ( 0.01)   0.02   0.02  99.98   0.00   0.00   0.00  91 / 93:751/104
028    0.55 ( 0.01)   0.01   0.01  99.99   0.00   0.00   0.00  91 / 93:751/104
029    0.65 ( 0.01)   0.02   0.02  99.98   0.00   0.00   0.00  91 / 93:751/104
030    2.98 ( 0.03)   0.07   0.07  99.93   0.00   0.00   0.00  91 / 93:751/104
031    3.06 ( 0.03)   0.08   0.07  99.93   0.00   0.00   0.00  91 / 93:751/104
032   83.08 ( 0.82)   2.05   1.94  98.06   0.00   0.00   0.00  91 / 93:751/104
033    0.97 ( 0.01)   0.02   0.02  99.98   0.00   0.00   0.00  91 / 93:751/104
034    1.16 ( 0.01)   0.03   0.03  99.97   0.00   0.00   0.00  91 / 93:751/104
035    0.87 ( 0.01)   0.02   0.02  99.98   0.00   0.00   0.00  91 / 93:751/104
036    3.56 ( 0.04)   0.09   0.08  99.92   0.00   0.00   0.00  91 / 93:751/104
037   23.61 ( 0.23)   0.58   0.55  99.45   0.00   0.00   0.00  91 / 93:751/104
038 1488.55 (14.72)  36.81  34.67  65.33   0.00   0.00   0.00  91 / 93:751/104
039    3.34 ( 0.03)   0.08   0.08  99.92   0.00   0.00   0.00  91 / 93:751/104
040    4.55 ( 0.05)   0.11   0.11  99.89   0.00   0.00   0.00  91 / 93:751/104
041   42.59 ( 0.42)   1.05   0.99  99.01   0.00   0.00   0.00  91 / 93:751/104
042    0.88 ( 0.01)   0.02   0.02  99.98   0.00   0.00   0.00  91 / 93:751/104
043   34.77 ( 0.34)   0.86   0.81  99.19   0.00   0.00   0.00  91 / 93:751/104
044   22.38 ( 0.22)   0.55   0.52  99.48   0.00   0.00   0.00  91 / 93:751/104
045    1.11 ( 0.01)   0.03   0.03  99.97   0.00   0.00   0.00  91 / 93:751/104
046    1.19 ( 0.01)   0.03   0.03  99.97   0.00   0.00   0.00  91 / 93:751/104
047    1.03 ( 0.01)   0.03   0.02  99.98   0.00   0.00   0.00  91 / 93:751/104

    Averages:        Turbo  C0(%)  C1(%)  C3(%)  C6(%)  C7(%)    TjMax:    Pkg:
                      1.04   0.98  99.02   0.00   0.00   0.00       0 C    92 C

0 replies

cyring · 2024-03-18T00:11:12Z

cyring
Mar 18, 2024
Maintainer

First Gen needed an temperature offset. Perhaps same with Genoa.

Can you compile my SMU tool zencli ?

cc zencli.c -o zencli

As root, you will peek the thermal registers I just know:

## since Zen gen1
zencli smu 0x59800
## per CCD
zencli smu 0x59954
zencli smu 0x59958
zencli smu 0x5995C
zencli smu 0x59960
zencli smu 0x59964
zencli smu 0x59968
zencli smu 0x5996C
## Family 19h APU
zencli smu 0x59B08

And, are the Mhz numbers correct ? ie can the cpu cores run at 2.11 Mhz) ?

As a défaut, CoreFreq is showing the relative frequency.
Press shortkey ! to toggle view to absolute frequency.
There is also a CLI argument to start in absolute frequency. See corefreq-cli -h

0 replies

garceri · 2024-03-18T00:26:30Z

garceri
Mar 18, 2024
Author

The Mhz reported, are relative to what ?

Here are the zencli outputs you requested:

# ./zencli smu 0x59800
[0x00059800] READ(smu) = 0x61e30000 (1642266624)
   60   56   52   48   44   40   36   32   28   24   20   16   12   08   04   00
 0000 0000 0000 0000 0000 0000 0000 0000 0110 0001 1110 0011 0000 0000 0000 0000
# ./zencli smu 0x59954
[0x00059954] READ(smu) = 0x00000000 (0)
   60   56   52   48   44   40   36   32   28   24   20   16   12   08   04   00
 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000
# ./zencli smu 0x59B08
[0x00059b08] READ(smu) = 0x00000ac4 (2756)
   60   56   52   48   44   40   36   32   28   24   20   16   12   08   04   00
 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 1010 1100 0100

0 replies

cyring · 2024-03-18T00:43:41Z

cyring
Mar 18, 2024
Maintainer

The Mhz reported, are relative to what ?

Those are cycles counted by hardware
When no activity they fall down to no cycle

Relative comes from the Intel terminlogy about HARDWARE COORDINATION

Somehow AMD provides the same counters.

0 replies

cyring · 2024-03-18T00:46:07Z

cyring
Mar 18, 2024
Maintainer

Can you also dump the CCD range ?

## per CCD
zencli smu 0x59954
zencli smu 0x59958
zencli smu 0x5995C
zencli smu 0x59960
zencli smu 0x59964
zencli smu 0x59968
zencli smu 0x5996C

0 replies

cyring · 2024-03-18T00:53:56Z

cyring
Mar 18, 2024
Maintainer

I see, k10temp found them at offset 0x300 of 0x59800

https://elixir.bootlin.com/linux/latest/source/drivers/hwmon/k10temp.c#L475

So SMU address is 0x59B00 + (CCD number * 4)

0 replies

cyring · 2024-03-18T01:05:51Z

cyring
Mar 18, 2024
Maintainer

Fortunately thermal function was already made for Raphael.
Genoa is now pointing to it.
Please pull and test latest commit 7c926af from develop

0 replies

cyring · 2024-03-18T07:37:37Z

cyring
Mar 18, 2024
Maintainer

It may be a wrong Register address
Still based on develop branch, can you edit the header file at that line:

CoreFreq/x86_64/amd_reg.h

Line 208 in 87344fa

#define SMU_AMD_THM_TCTL_CCD_REGISTER_F19H_61H \

and replace code with this one:

#define SMU_AMD_THM_TCTL_CCD_REGISTER_F19H_61H				\
	(SMU_AMD_THM_TCTL_REGISTER_F17H + 0x300)

Next please rebuild, unload, reload and test for temperature

EDIT: For DIMM geometry, can you also peek those addresses

## Prior Zen4
./zencli smu 0x50030
./zencli smu 0x50034
./zencli smu 0x50038
./zencli smu 0x5003C
## Since Zen4
./zencli smu 0x50040
./zencli smu 0x50044
./zencli smu 0x50048
./zencli smu 0x5004C

0 replies

garceri · 2024-03-18T11:25:24Z

garceri
Mar 18, 2024
Author

I pulled and recompiled the commit you mentioned (7c926af from develop) and seems to have improved a bit, still there are some cores whose's temperatures are somehow reported as 0 C..

CPU Freq(MHz) VID  Vcore  TMP(C)    Accumulator       Energy(J)     Power(W)
000 4158.57   184  1.1500   38  000000000000254752    3.887207031   3.887207031
001 1155.50   184  1.1500   38  000000000000164422    2.508880615   2.508880615
002  975.78   184  1.1500   38  000000000000153330    2.339630127   2.339630127
003 1101.39   184  1.1500   38  000000000000156543    2.388656616   2.388656616
004 1040.26   184  1.1500   38  000000000000151524    2.312072754   2.312072754
005  976.49   184  1.1500   38  000000000000156197    2.383377075   2.383377075
006 1194.84   184  1.1500   39  000000000000175520    2.678222656   2.678222656
007 1253.40   184  1.1500   39  000000000000171429    2.615798950   2.615798950
008 1078.62   184  1.1500   39  000000000000168110    2.565155029   2.565155029
009 1065.19   184  1.1500    0  000000000000159550    2.434539795   2.434539795
010 1317.53   184  1.1500    0  000000000000173951    2.654281616   2.654281616
011 1144.12   184  1.1500    0  000000000000175765    2.681961060   2.681961060
012 1405.92   184  1.1500   39  000000000000194216    2.963500977   2.963500977
013 1571.54   184  1.1500   39  000000000000195119    2.977279663   2.977279663
014 1792.37   184  1.1500   39  000000000000200345    3.057022095   3.057022095
015 1372.33   184  1.1500    0  000000000000192656    2.939697266   2.939697266
016 1565.62   184  1.1500    0  000000000000198408    3.027465820   3.027465820
017 1351.56   184  1.1500    0  000000000000192128    2.931640625   2.931640625
018 3506.43   184  1.1500   38  000000000000231040    3.525390625   3.525390625
019 3699.47   184  1.1500   38  000000000000333141    5.083328247   5.083328247
020 1384.05   184  1.1500   38  000000000000190392    2.905151367   2.905151367
021 1114.08   184  1.1500   38  000000000000157730    2.406768799   2.406768799
022 1002.75   184  1.1500   38  000000000000276418    4.217803955   4.217803955
023 4158.57   184  1.1500   38  000000000000224629    3.427566528   3.427566528
024 1006.49   184  1.1500   38  000000000000000000    0.000000000   0.000000000
025 1044.69   184  1.1500   38  000000000000000000    0.000000000   0.000000000
026 1007.88   184  1.1500   38  000000000000000000    0.000000000   0.000000000
027 1020.24   184  1.1500   38  000000000000000000    0.000000000   0.000000000
028  979.97   184  1.1500   38  000000000000000000    0.000000000   0.000000000
029 1113.24   184  1.1500   38  000000000000000000    0.000000000   0.000000000
030 1284.31   184  1.1500   39  000000000000000000    0.000000000   0.000000000
031 1109.47   184  1.1500   39  000000000000000000    0.000000000   0.000000000
032 1164.28   184  1.1500   39  000000000000000000    0.000000000   0.000000000
033 1111.59   184  1.1500    0  000000000000000000    0.000000000   0.000000000
034 1189.57   184  1.1500    0  000000000000000000    0.000000000   0.000000000
035 1287.66   184  1.1500    0  000000000000000000    0.000000000   0.000000000
036 1582.32   184  1.1500   39  000000000000000000    0.000000000   0.000000000
037 1416.99   184  1.1500   39  000000000000000000    0.000000000   0.000000000
038 1338.64   184  1.1500   39  000000000000000000    0.000000000   0.000000000
039 1502.98   184  1.1500    0  000000000000000000    0.000000000   0.000000000
040 1464.83   184  1.1500    0  000000000000000000    0.000000000   0.000000000
041 1598.45   184  1.1500    0  000000000000000000    0.000000000   0.000000000
042 1769.44   184  1.1500   38  000000000000000000    0.000000000   0.000000000
043 1120.63   184  1.1500   38  000000000000000000    0.000000000   0.000000000
044 1427.70   184  1.1500   38  000000000000000000    0.000000000   0.000000000
045  972.31   184  1.1500   38  000000000000000000    0.000000000   0.000000000
046 4158.56   184  1.1500   38  000000000000000000    0.000000000   0.000000000
047 1147.79   184  1.1500   38  000000000000000000    0.000000000   0.000000000

             Package[0]    Cores         Uncore        Memory        Platform
Energy(J): 166.636291504  70.912399292  29.650711060   0.000000000   0.000000000
Power(W) : 166.636291504  70.912399292  29.650711060   0.000000000   0.000000000


CPU Freq(MHz) Ratio  Turbo  C0(%)  C1(%)  C3(%)  C6(%)  C7(%)  Min TMP:TS  Max
000 4159.27 (41.14) 102.85 100.00   0.00   0.00   0.00   0.00  37 / 44:748/ 50
001  993.01 ( 9.82)  24.56  23.87  76.13   0.00   0.00   0.00  37 / 44:748/ 51
002 1067.17 (10.56)  26.39  25.65  74.35   0.00   0.00   0.00  37 / 44:748/ 51
003 1005.40 ( 9.94)  24.86  24.16  75.84   0.00   0.00   0.00  36 / 38:702/ 45
004 1088.16 (10.76)  26.91  26.15  73.85   0.00   0.00   0.00  36 / 38:698/ 45
005  990.94 ( 9.80)  24.50  23.81  76.19   0.00   0.00   0.00  36 / 38:698/ 45
006  963.20 ( 9.53)  23.82  23.15  76.85   0.00   0.00   0.00  35 / 41:722/ 46
007 1113.60 (11.01)  27.54  26.76  73.24   0.00   0.00   0.00  35 / 41:722/ 46
008 1021.29 (10.10)  25.25  24.55  75.45   0.00   0.00   0.00  35 / 40:714/ 46
009 1265.57 (12.52)  31.30  30.42  69.58   0.00   0.00   0.00  0  /  0:0  /  0
010 1203.92 (11.91)  29.77  28.94  71.06   0.00   0.00   0.00  0  /  0:0  /  0
011 1396.79 (13.82)  34.54  33.58  66.42   0.00   0.00   0.00  0  /  0:0  /  0
012 1460.91 (14.45)  36.13  35.12  64.88   0.00   0.00   0.00  35 / 40:714/ 46
013 1460.37 (14.44)  36.11  35.10  64.90   0.00   0.00   0.00  35 / 40:714/ 46
014 1507.86 (14.91)  37.29  36.25  63.75   0.00   0.00   0.00  35 / 40:714/ 46
015 1371.19 (13.56)  33.91  32.97  67.03   0.00   0.00   0.00  0  /  0:0  /  0
016 1538.59 (15.22)  38.05  36.99  63.01   0.00   0.00   0.00  0  /  0:0  /  0
017 1526.73 (15.10)  37.75  36.70  63.30   0.00   0.00   0.00  0  /  0:0  /  0
018 4149.52 (41.04) 102.61  99.77   0.23   0.00   0.00   0.00  37 / 44:748/ 51
019 4159.27 (41.14) 102.85 100.00   0.00   0.00   0.00   0.00  37 / 44:748/ 51
020 1034.72 (10.23)  25.59  24.86  75.14   0.00   0.00   0.00  37 / 44:748/ 50
021 1129.47 (11.17)  27.93  27.15  72.85   0.00   0.00   0.00  36 / 38:698/ 45
022 1141.95 (11.30)  28.24  27.44  72.56   0.00   0.00   0.00  36 / 38:702/ 45
023 4159.26 (41.14) 102.85 100.00   0.00   0.00   0.00   0.00  36 / 38:702/ 45
024 1229.23 (12.16)  30.40  29.54  70.46   0.00   0.00   0.00  37 / 44:748/ 50
025 1044.66 (10.33)  25.83  25.11  74.89   0.00   0.00   0.00  37 / 44:748/ 51
026 1089.58 (10.78)  26.94  26.18  73.82   0.00   0.00   0.00  37 / 44:748/ 50
027 1060.35 (10.49)  26.22  25.47  74.53   0.00   0.00   0.00  36 / 38:702/ 45
028 1132.07 (11.20)  27.99  27.20  72.80   0.00   0.00   0.00  36 / 38:702/ 45
029 1131.36 (11.19)  27.98  27.19  72.81   0.00   0.00   0.00  36 / 38:698/ 45
030 1170.12 (11.57)  28.93  28.13  71.87   0.00   0.00   0.00  35 / 40:714/ 46
031 1177.30 (11.65)  29.11  28.30  71.70   0.00   0.00   0.00  35 / 41:722/ 46
032 1227.64 (12.14)  30.36  29.52  70.48   0.00   0.00   0.00  35 / 40:714/ 46
033 1169.10 (11.56)  28.91  28.10  71.90   0.00   0.00   0.00  0  /  0:0  /  0
034 1223.32 (12.10)  30.25  29.40  70.60   0.00   0.00   0.00  0  /  0:0  /  0
035 1254.64 (12.41)  31.03  30.16  69.84   0.00   0.00   0.00  0  /  0:0  /  0
036 1339.88 (13.25)  33.13  32.21  67.79   0.00   0.00   0.00  35 / 40:714/ 46
037 1634.24 (16.16)  40.41  39.28  60.72   0.00   0.00   0.00  35 / 41:722/ 46
038 1235.64 (12.22)  30.56  29.69  70.31   0.00   0.00   0.00  35 / 40:714/ 46
039 1619.09 (16.01)  40.04  38.91  61.09   0.00   0.00   0.00  0  /  0:0  /  0
040 1599.46 (15.82)  39.55  38.45  61.55   0.00   0.00   0.00  0  /  0:0  /  0
041 1601.11 (15.84)  39.59  38.49  61.51   0.00   0.00   0.00  0  /  0:0  /  0
042 1078.27 (10.67)  26.66  25.91  74.09   0.00   0.00   0.00  37 / 44:748/ 50
043 1192.15 (11.79)  29.48  28.65  71.35   0.00   0.00   0.00  37 / 44:748/ 50
044 1113.22 (11.01)  27.53  26.75  73.25   0.00   0.00   0.00  37 / 44:748/ 50
045  992.32 ( 9.82)  24.54  23.85  76.15   0.00   0.00   0.00  36 / 38:702/ 45
046 4159.26 (41.14) 102.85 100.00   0.00   0.00   0.00   0.00  36 / 38:698/ 45
047 1155.77 (11.43)  28.58  27.77  72.23   0.00   0.00   0.00  36 / 38:702/ 45

    Averages:        Turbo  C0(%)  C1(%)  C3(%)  C6(%)  C7(%)    TjMax:    Pkg:
                     37.88  36.83  63.17   0.00   0.00   0.00       0 C    39 C

Here are the zencli peeks you requested:

# ./zencli smu 0x50030
[0x00050030] READ(smu) = 0x07fff7fe (134215678)
   60   56   52   48   44   40   36   32   28   24   20   16   12   08   04   00
 0000 0000 0000 0000 0000 0000 0000 0000 0000 0111 1111 1111 1111 0111 1111 1110
# ./zencli smu 0x50034
[0x00050034] READ(smu) = 0x07fff7fe (134215678)
   60   56   52   48   44   40   36   32   28   24   20   16   12   08   04   00
 0000 0000 0000 0000 0000 0000 0000 0000 0000 0111 1111 1111 1111 0111 1111 1110
# ./zencli smu 0x50038
[0x00050038] READ(smu) = 0x00000000 (0)
   60   56   52   48   44   40   36   32   28   24   20   16   12   08   04   00
 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000
# ./zencli smu 0x5003C
[0x0005003c] READ(smu) = 0x00000000 (0)
   60   56   52   48   44   40   36   32   28   24   20   16   12   08   04   00
 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000
# ./zencli smu 0x50040
[0x00050040] READ(smu) = 0x0026070c (2492172)
   60   56   52   48   44   40   36   32   28   24   20   16   12   08   04   00
 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0010 0110 0000 0111 0000 1100
# ./zencli smu 0x50044
[0x00050044] READ(smu) = 0x0026070c (2492172)
   60   56   52   48   44   40   36   32   28   24   20   16   12   08   04   00
 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0010 0110 0000 0111 0000 1100
# ./zencli smu 0x50048
[0x00050048] READ(smu) = 0x00150508 (1377544)
   60   56   52   48   44   40   36   32   28   24   20   16   12   08   04   00
 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0001 0101 0000 0101 0000 1000
# ./zencli smu 0x5004A
[0x0005004a] READ(smu) = 0x00150508 (1377544)
   60   56   52   48   44   40   36   32   28   24   20   16   12   08   04   00
 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0001 0101 0000 0101 0000 1000

0 replies

cyring · 2024-03-22T21:45:50Z

cyring
Mar 22, 2024
Maintainer

P-States

You can reprogram P-States from UI but also using the driver parameters.

For example, your EPYC default P-States were discovered as bellow.

|- Turbo Boost                                                         [   LOCK]
                 XFR   4347.25                    [  43 ]
                 CPB   4347.25                    [  43 ]
                  1C   2729.67                    <  27 >
                  2C   1516.48                    <  15 >

Now suppose you want to alter these two enabled P-States to respectively 12 and 30 frequency ratios:

insmod build/corefreqk.ko Register_ClockSource=1 \
Register_Governor=1 Register_CPU_Idle=1 Register_CPU_Freq=1 \
Turbo_Ratio_Unlock=1 TurboBoost_Enable="0,1" \
Ratio_Boost="-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,12,30"

Remarks

Ratio_Boost is the P-States array from 18C down to 1C.
-1 means " don't touch value "
This EPYC has only 1C and 2C enabled by hardware
Turbo_Ratio_Unlock allows reprogrammation of P-States
TurboBoost_Enable="0,1" is first disabled, hence value "0", next P-States are reprogrammed, finally "1" means re-enable Turbo Boost

I hope you won't find this method too complicated.
Please try it out of Production and post the results.

0 replies

garceri · 2024-03-26T16:32:43Z

garceri
Mar 26, 2024
Author

It will be some time until I can test it, the server is running production workloads and I'll need to take it offline to test this.
BTW, I could not find the IOMMU option on BIOS.

0 replies

cyring · 2024-03-26T17:53:04Z

cyring
Mar 26, 2024
Maintainer

It will be some time until I can test it, the server is running production workloads and I'll need to take it offline to test this. BTW, I could not find the IOMMU option on BIOS.

Actions are transferred to the todo list

To refresh the EPYC 9274F Wiki, can you however pull the latest from master branch and post the output of:

corefreq-cli -s -n -m -n -z -n -B -n -M -n -k -n -C 1 -n -i 1 -n -V 1 -n -W 1 -n -R

0 replies

garceri · 2024-03-27T16:40:30Z

garceri
Mar 27, 2024
Author

Here ya go:

# ./corefreq-cli -s -n -m -n -z -n -B -n -M -n -k -n -C 1 -n -i 1 -n -V 1 -n -W 1 -n -R
Processor                                     [AMD EPYC 9274F 24-Core Processor]
|- PPIN#                                                      [ 2b6a56a45d98031]
|- Architecture                                                     [EPYC/Genoa]
|- Vendor ID                                                      [AuthenticAMD]
|- Firmware                                                        [ 71.121.0-5]
|- Microcode                                                        [0x0a101144]
|- Signature                                                           [  AF_11]
|- Stepping                                                            [      1]
|- Online CPU                                                          [ 48/ 48]
|- Base Clock                                                          [101.099]
|- Frequency            (MHz)                      Ratio
                 Min   1516.49                    <  15 >
                 Max   4043.97                    <  40 >
|- Factory                                                             [100.000]
                       4000                       [  40 ]
|- Performance
   |- P-State
                 TGT   4043.97                    <  40 >
   |- CPPC
                 Min   4347.27                    <  43 >
                 Max    404.40                    <   4 >
                 TGT   4347.27                    <  43 >
|- Turbo Boost                                                         [   LOCK]
                 XFR   4347.27                    [  43 ]
                 CPB   4347.27                    [  43 ]
                  1C   2729.68                    <  27 >
                  2C   1516.49                    <  15 >
|- Uncore                                                              [   LOCK]
                 CLK   2426.38                    [  24 ]
                 MEM   2426.38                    [  24 ]

Instruction Set Extensions
|- 3DNow!/Ext [N/N]          ADX [Y]          AES [Y]  AVX/AVX2 [Y/Y]
|- AVX512-F     [Y]    AVX512-DQ [Y]  AVX512-IFMA [Y]   AVX512-PF [N]
|- AVX512-ER    [N]    AVX512-CD [Y]    AVX512-BW [Y]   AVX512-VL [Y]
|- AVX512-VBMI  [Y] AVX512-VBMI2 [Y]  AVX512-VNNI [Y]  AVX512-ALG [Y]
|- AVX512-VPOP  [Y] AVX512-VNNIW [N] AVX512-FMAPS [N] AVX512-VP2I [N]
|- AVX512-BF16  [Y] AVX-VNNI-VEX [N]    AVX-FP128 [N]   AVX-FP256 [Y]
|- BMI1/BMI2  [Y/Y]         CLWB [Y]      CLFLUSH [Y] CLFLUSH-OPT [Y]
|- CLAC-STAC    [Y]         CMOV [Y]    CMPXCHG8B [Y]  CMPXCHG16B [Y]
|- F16C         [Y]          FPU [Y]         FXSR [Y]   LAHF-SAHF [Y]
|- MMX/Ext    [Y/Y] MON/MWAITX [Y/Y]        MOVBE [Y]   PCLMULQDQ [Y]
|- POPCNT       [Y]       RDRAND [Y]       RDSEED [Y]      RDTSCP [Y]
|- SEP          [Y]          SHA [Y]          SSE [Y]        SSE2 [Y]
|- SSE3         [Y]        SSSE3 [Y]  SSE4.1/4A [Y/Y]      SSE4.2 [Y]
|- SERIALIZE    [N]      SYSCALL [Y]        RDPID [Y]        UMIP [Y]
|- VAES         [Y]   VPCLMULQDQ [Y]   PREFETCH/W [Y]       LZCNT [Y]

Features
|- 1 GB Pages Support                                      1GB-PAGES   [Capable]
|- 100 MHz multiplier Control                            100MHzSteps   [Missing]
|- Advanced Configuration & Power Interface                     ACPI   [Capable]
|- Advanced Programmable Interrupt Controller                   APIC   [Capable]
|- Advanced Virtual Interrupt Controller                        AVIC   [Capable]
|- APIC Timer Invariance                                        ARAT   [Capable]
|- LOCK prefix to read CR8                                    AltMov   [Capable]
|- Clear Zero Instruction                                     CLZERO   [Capable]
|- Core Multi-Processing                                  CMP Legacy   [Capable]
|- L1 Data Cache Context ID                                  CNXT-ID   [Missing]
|- Collaborative Processor Performance Control                  CPPC   [Capable]
|- Direct Cache Access                                           DCA   [Missing]
|- Debugging Extension                                            DE   [Capable]
|- Debug Store & Precise Event Based Sampling               DS, PEBS   [Missing]
|- CPL Qualified Debug Store                                  DS-CPL   [Missing]
|- 64-Bit Debug Store                                         DTES64   [Missing]
|- Fast Short REP MOVSB                                         FSRM   [Capable]
|- Fast-String Operation                                        ERMS   [Capable]
|- Fused Multiply Add                                           FMA4   [Missing]
|- Fused Multiply Add                                            FMA   [Capable]
|- Hardware Lock Elision                                         HLE   [Missing]
|- Hyper-Threading Technology                                    HTT   [Capable]
|- Hardware P-state control                                      HwP   [Capable]
|- Instruction Based Sampling                                    IBS   [Capable]
|- Instruction INVLPGB                                       INVLPGB   [Capable]
|- Instruction INVPCID                                       INVPCID   [Capable]
|- Long Mode 64 bits                                       IA64 | LM   [Capable]
|- LightWeight Profiling                                         LWP   [Missing]
|- Memory Bandwidth Enforcement                                  MBE   [Capable]
|- Machine-Check Architecture                                    MCA   [Capable]
|- Instruction MCOMMIT                                       MCOMMIT   [Missing]
|- Model Specific Registers                                      MSR   [Capable]
|- Memory Type Range Registers                                  MTRR   [Capable]
|- No-Execute Page Protection                                     NX   [Capable]
|- OS-Enabled Ext. State Management                          OSXSAVE   [Capable]
|- OS Visible Work-around                                       OSVW   [Capable]
|- Physical Address Extension                                    PAE   [Capable]
|- Page Attribute Table                                          PAT   [Capable]
|- Pending Break Enable                                          PBE   [Missing]
|- Process Context Identifiers                                  PCID   [Capable]
|- Perfmon and Debug Capability                                 PDCM   [Missing]
|- Page Global Enable                                            PGE   [Capable]
|- Page Size Extension                                           PSE   [Capable]
|- 36-bit Page Size Extension                                  PSE36   [Capable]
|- Processor Serial Number                                       PSN   [Missing]
|- Resource Director Technology/PQE                            RDT-A   [Capable]
|- Resource Director Technology/PQM                            RDT-M   [Capable]
|- Read Processor Register at User level                       RDPRU   [Capable]
|- Restricted Transactional Memory                               RTM   [Missing]
|- Safer Mode Extensions                                         SMX   [Missing]
|- Self-Snoop                                                     SS   [Missing]
|- Supervisor-Mode Access Prevention                            SMAP   [Capable]
|- Supervisor-Mode Execution Prevention                         SMEP   [Capable]
|- Trailing Bit Manipulation                                     TBM   [Missing]
|- Translation Cache Extension                                   TCE   [Capable]
|- Time Stamp Counter                                            TSC [Invariant]
|- Time Stamp Counter Deadline                          TSC-DEADLINE   [Missing]
|- TSX Force Abort MSR Register                            TSX-ABORT   [Missing]
|- TSX Suspend Load Address Tracking                       TSX-LDTRK   [Missing]
|- User-Mode Instruction Prevention                             UMIP   [Capable]
|- Virtual Mode Extension                                        VME   [Capable]
|- Virtual Machine Extensions                                    VMX   [Missing]
|- Write Back & Do Not Invalidate Cache                     WBNOINVD   [Capable]
|- Extended xAPIC Support                                     x2APIC   [  xAPIC]
|- AVIC controller for x2APIC                                 x2AVIC   [Capable]
|- XSAVE/XSTOR States                                          XSAVE   [Capable]
|- xTPR Update Control                                          xTPR   [Missing]
|- Extended Operation Support                                    XOP   [Missing]
Mitigation mechanisms
|- Indirect Branch Restricted Speculation                       IBRS   [Capable]
   |- IBRS Always-On preferred by processor                            [ Unable]
   |- IBRS preferred over software solution                            [Capable]
   |- IBRS provides same speculation limits                            [Capable]
|- Indirect Branch Prediction Barrier                           IBPB   [Capable]
|- Single Thread Indirect Branch Predictor                     STIBP   [ Enable]
|- Speculative Store Bypass Disable                             SSBD   [Capable]
   |- SSBD use VIRT_SPEC_CTRL register                                 [ Unable]
   |- SSBD not needed on this processor                                [ Unable]
|- No Branch Type Confusion                                   BTC_NO   [Capable]
|- BTC on Non-Branch instruction                            BTC-NOBR   [Capable]
|- Limited Early Redirect Window                            AGENPICK   [ Unable]
|- Arch - No Fast Predictive Store Forwarding                   PSFD   [Capable]
|- Arch - Enhanced Predictive Store Forwarding                  EPSF   [Capable]
|- Arch - Cross Processor Information Leak                XPROC_LEAK   [ Unable]
Security Features
|- CET Shadow Stack features                                  CET-SS   [Capable]
|- Secure Init and Jump with Attestation                      SKINIT   [Capable]
|- Secure Encrypted Virtualization                               SEV   [Capable]
|- SEV - Encrypted State                                      SEV-ES   [Capable]
|- SEV - Secure Nested Paging                                SEV-SNP   [Capable]
|- Guest Mode Execute Trap                                      GMET   [Capable]
|- Supervisor Shadow Stack                                       SSS   [Capable]
|- VM Permission Levels                                         VMPL   [Capable]
|- VMPL Supervisor Shadow Stack                             VMPL-SSS   [Capable]
|- Secure Memory Encryption                                      SME   [Capable]
|- Transparent SME                                              TSME   [ Enable]
|- Secure Multi-Key Memory Encryption                         SME-MK   [Capable]
|- DRAM Data Scrambling                                    Scrambler   [ Enable]

Technologies
|- Instruction Cache Unit
   |- L1 IP Prefetcher                                          L1 HW IP   < ON>
|- Data Cache Unit
   |- L1 Prefetcher                                                L1 HW   < ON>
|- Cache Prefetchers
   |- L2 Prefetcher                                                L2 HW   < ON>
   |- L1 Stride Prefetcher                                     L1 Stride   < ON>
   |- L1 Region Prefetcher                                     L1 Region   < ON>
   |- L1 Burst Prefetch Mode                                    L1 Burst   < ON>
   |- L2 Stream HW Prefetcher                                  L2 Stream   < ON>
   |- L2 Up/Down Prefetcher                                   L2 Up/Down   < ON>
|- System Management Mode                                       SMM-Lock   [OFF]
|- Simultaneous Multithreading                                       SMT   [ ON]
|- PowerNow!                                                         CnQ   [OFF]
|- Core C-States                                                     CCx   [ ON]
|- Core Performance Boost                                            CPB   < ON>
|- Watchdog Timer                                                    WDT   <OFF>
|- Virtualization                                                    SVM   [OFF]
   |- I/O MMU                                                      AMD-V   [OFF]
   |- Version                                                     [         N/A]
   |- Hypervisor                                                           [OFF]
   |- Vendor ID                                                   [         N/A]

Performance Monitoring
|- Version                                                        PM       [  2]
|- Counters:          General                   Fixed
|           {  6,  6, 16 } x 48 bits            3 x 64 bits
|- Enhanced Halt State                                           C1E       <OFF>
|- C2 UnDemotion                                                 C2U       < ON>
|- C3 UnDemotion                                                 C3U       < ON>
|- Core C6 State                                                 CC6       < ON>
|- Package C6 State                                              PC6       <OFF>
|- Legacy Frequency ID control                                   FID       [OFF]
|- Legacy Voltage ID control                                     VID       [OFF]
|- P-State Hardware Coordination Feedback                MPERF/APERF       [ ON]
|- Core C-States
   |- C-States Base Address                                      BAR   [ 0x413 ]
|- ACPI Processor C-States                                      _CST   [      2]
|- MONITOR/MWAIT
   |- State index:    #0    #1    #2    #3    #4    #5    #6    #7
   |- Sub C-State:     1     1     0     0     0     0     0     0
   |- Monitor-Mwait Extensions                                   EMX   [Capable]
   |- Interrupt Break-Event                                      IBE   [Capable]
|- Core Cycles                                                         [Capable]
|- Instructions Retired                                                [Capable]
|- Reference Cycles                                                    [Capable]
|- Last Level Cache References                                         [Capable]
|- Global Time Stamp Counter                                           [Missing]
|- Data Fabric Performance Counter                                     [Capable]
|- Core Performance Counter                                            [Capable]
|- Processor Performance Control                                _PCT   [Missing]
|- Performance Supported States                                 _PSS   [Missing]
|- Performance Present Capabilities                             _PPC   [Missing]
|- Continuous Performance Control                               _CPC   [Missing]

Power, Current & Thermal
|- Temperature Offset:Junction                                 TjMax [ 49:  0 C]
|- CPPC Energy Preference                                        EPP   <      0>
|- Digital Thermal Sensor                                        DTS   [Capable]
|- Power Limit Notification                                      PLN   [Missing]
|- Package Thermal Management                                    PTM   [Missing]
|- Thermal Monitor 1                                             TTP   [ Enable]
|- Thermal Monitor 2                                             HTC   [ Enable]
|- Thermal Design Power                                          TDP   [Missing]
   |- Minimum Power                                              Min   [Missing]
   |- Maximum Power                                              Max   [Missing]
|- Thermal Design Power                                      Package   < Enable>
   |- Power Limit                                                PL1   <  400 W>
   |- Time Window                                                TW1   <   0 ns>
   |- Power Limit                                                PL2   <  400 W>
   |- Time Window                                                TW2   <   0 ns>
|- Thermal Design Power                                         Core   [Disable]
   |- Power Limit                                                PL1   [    0 W]
   |- Time Window                                                TW1   [   0 ns]
|- Thermal Design Power                                       Uncore   [Disable]
   |- Power Limit                                                PL1   [    0 W]
   |- Time Window                                                TW1   [   0 ns]
|- Thermal Design Power                                         DRAM   [Disable]
   |- Power Limit                                                PL1   [    0 W]
   |- Time Window                                                TW1   [   0 ns]
|- Thermal Design Power                                     Platform   [Disable]
   |- Power Limit                                                PL1   [    0 W]
   |- Time Window                                                TW1   [   0 ns]
   |- Power Limit                                                PL2   [    0 W]
   |- Time Window                                                TW2   [   0 ns]
|- Package Power Tracking                                        PPT   [Missing]
|- Electrical Design Current                                     EDC   [Missing]
|- Thermal Design Current                                        TDC   [Missing]
|- Core Thermal Point
|- Package Thermal Point
   |- Thermal Monitor Trip                                     Limit   [  115 C]
   |- HTC Temperature Limit                                    Limit   [    0 C]
   |- HTC Temperature Hysteresis                           Threshold   [    0 C]
|- Units
   |- Power                                               watt   [      Missing]
   |- Energy                                             joule   [  0.000015259]
   |- Window                                            second   [  0.000976562]

CPU Pkg  Apic  Core/Thread  Caches      (w)rite-Back (i)nclusive
 #   ID   ID CCD CCX ID/ID L1-Inst Way  L1-Data Way      L2  Way      L3  Way
000:BSP    0   0  0   0  0      32  8        32  8      1024  8 i  262144 16w
001:  0    2   0  0   1  0      32  8        32  8      1024  8 i  262144 16w
002:  0    4   0  0   2  0      32  8        32  8      1024  8 i  262144 16w
003:  0   32   4  4  16  0      32  8        32  8      1024  8 i  262144 16w
004:  0   34   4  4  17  0      32  8        32  8      1024  8 i  262144 16w
005:  0   36   4  4  18  0      32  8        32  8      1024  8 i  262144 16w
006:  0   16   2  2   8  0      32  8        32  8      1024  8 i  262144 16w
007:  0   18   2  2   9  0      32  8        32  8      1024  8 i  262144 16w
008:  0   20   2  2  10  0      32  8        32  8      1024  8 i  262144 16w
009:  0   48   6  6  24  0      32  8        32  8      1024  8 i  262144 16w
010:  0   50   6  6  25  0      32  8        32  8      1024  8 i  262144 16w
011:  0   52   6  6  26  0      32  8        32  8      1024  8 i  262144 16w
012:  0   24   2  3  12  0      32  8        32  8      1024  8 i  262144 16w
013:  0   26   2  3  13  0      32  8        32  8      1024  8 i  262144 16w
014:  0   28   2  3  14  0      32  8        32  8      1024  8 i  262144 16w
015:  0   56   6  7  28  0      32  8        32  8      1024  8 i  262144 16w
016:  0   58   6  7  29  0      32  8        32  8      1024  8 i  262144 16w
017:  0   60   6  7  30  0      32  8        32  8      1024  8 i  262144 16w
018:  0    8   0  1   4  0      32  8        32  8      1024  8 i  262144 16w
019:  0   10   0  1   5  0      32  8        32  8      1024  8 i  262144 16w
020:  0   12   0  1   6  0      32  8        32  8      1024  8 i  262144 16w
021:  0   40   4  5  20  0      32  8        32  8      1024  8 i  262144 16w
022:  0   42   4  5  21  0      32  8        32  8      1024  8 i  262144 16w
023:  0   44   4  5  22  0      32  8        32  8      1024  8 i  262144 16w
024:  0    1   0  0   0  1      32  8        32  8      1024  8 i  262144 16w
025:  0    3   0  0   1  1      32  8        32  8      1024  8 i  262144 16w
026:  0    5   0  0   2  1      32  8        32  8      1024  8 i  262144 16w
027:  0   33   4  4  16  1      32  8        32  8      1024  8 i  262144 16w
028:  0   35   4  4  17  1      32  8        32  8      1024  8 i  262144 16w
029:  0   37   4  4  18  1      32  8        32  8      1024  8 i  262144 16w
030:  0   17   2  2   8  1      32  8        32  8      1024  8 i  262144 16w
031:  0   19   2  2   9  1      32  8        32  8      1024  8 i  262144 16w
032:  0   21   2  2  10  1      32  8        32  8      1024  8 i  262144 16w
033:  0   49   6  6  24  1      32  8        32  8      1024  8 i  262144 16w
034:  0   51   6  6  25  1      32  8        32  8      1024  8 i  262144 16w
035:  0   53   6  6  26  1      32  8        32  8      1024  8 i  262144 16w
036:  0   25   2  3  12  1      32  8        32  8      1024  8 i  262144 16w
037:  0   27   2  3  13  1      32  8        32  8      1024  8 i  262144 16w
038:  0   29   2  3  14  1      32  8        32  8      1024  8 i  262144 16w
039:  0   57   6  7  28  1      32  8        32  8      1024  8 i  262144 16w
040:  0   59   6  7  29  1      32  8        32  8      1024  8 i  262144 16w
041:  0   61   6  7  30  1      32  8        32  8      1024  8 i  262144 16w
042:  0    9   0  1   4  1      32  8        32  8      1024  8 i  262144 16w
043:  0   11   0  1   5  1      32  8        32  8      1024  8 i  262144 16w
044:  0   13   0  1   6  1      32  8        32  8      1024  8 i  262144 16w
045:  0   41   4  5  20  1      32  8        32  8      1024  8 i  262144 16w
046:  0   43   4  5  21  1      32  8        32  8      1024  8 i  262144 16w
047:  0   45   4  5  22  1      32  8        32  8      1024  8 i  262144 16w

|- Collaborative Processor Performance Control                  CPPC       < ON>
   |- Capabilities     Lowest      Efficient     Guaranteed        Highest
   |- CPU #0     404.40 (  4)  2729.68 ( 27)  4043.97 ( 40)  4347.27 ( 43)
   |- CPU #1     404.40 (  4)  2729.68 ( 27)  4043.97 ( 40)  4347.27 ( 43)
   |- CPU #2     404.40 (  4)  2729.68 ( 27)  4043.97 ( 40)  4347.27 ( 43)
   |- CPU #3     404.40 (  4)  2729.68 ( 27)  4043.97 ( 40)  4347.27 ( 43)
   |- CPU #4     404.40 (  4)  2729.68 ( 27)  4043.97 ( 40)  4347.27 ( 43)
   |- CPU #5     404.40 (  4)  2729.68 ( 27)  4043.97 ( 40)  4347.27 ( 43)
   |- CPU #6     404.40 (  4)  2729.68 ( 27)  4043.97 ( 40)  4347.27 ( 43)
   |- CPU #7     404.37 (  4)  2729.50 ( 27)  4043.71 ( 40)  4346.98 ( 43)
   |- CPU #8     404.40 (  4)  2729.68 ( 27)  4043.97 ( 40)  4347.27 ( 43)
   |- CPU #9     404.40 (  4)  2729.68 ( 27)  4043.97 ( 40)  4347.27 ( 43)
   |- CPU #10    404.40 (  4)  2729.68 ( 27)  4043.97 ( 40)  4347.27 ( 43)
   |- CPU #11    404.40 (  4)  2729.68 ( 27)  4043.97 ( 40)  4347.27 ( 43)
   |- CPU #12    404.40 (  4)  2729.68 ( 27)  4043.96 ( 40)  4347.26 ( 43)
   |- CPU #13    404.40 (  4)  2729.68 ( 27)  4043.97 ( 40)  4347.27 ( 43)
   |- CPU #14    404.40 (  4)  2729.68 ( 27)  4043.97 ( 40)  4347.27 ( 43)
   |- CPU #15    404.40 (  4)  2729.68 ( 27)  4043.97 ( 40)  4347.27 ( 43)
   |- CPU #16    404.40 (  4)  2729.68 ( 27)  4043.97 ( 40)  4347.27 ( 43)
   |- CPU #17    404.40 (  4)  2729.68 ( 27)  4043.97 ( 40)  4347.26 ( 43)
   |- CPU #18    404.40 (  4)  2729.68 ( 27)  4043.97 ( 40)  4347.27 ( 43)
   |- CPU #19    404.40 (  4)  2729.68 ( 27)  4043.97 ( 40)  4347.27 ( 43)
   |- CPU #20    404.40 (  4)  2729.68 ( 27)  4043.97 ( 40)  4347.27 ( 43)
   |- CPU #21    404.40 (  4)  2729.68 ( 27)  4043.97 ( 40)  4347.26 ( 43)
   |- CPU #22    404.40 (  4)  2729.68 ( 27)  4043.97 ( 40)  4347.27 ( 43)
   |- CPU #23    404.40 (  4)  2729.67 ( 27)  4043.95 ( 40)  4347.25 ( 43)
   |- CPU #24    404.40 (  4)  2729.68 ( 27)  4043.97 ( 40)  4347.27 ( 43)
   |- CPU #25    404.40 (  4)  2729.68 ( 27)  4043.97 ( 40)  4347.27 ( 43)
   |- CPU #26    404.40 (  4)  2729.68 ( 27)  4043.97 ( 40)  4347.27 ( 43)
   |- CPU #27    404.40 (  4)  2729.68 ( 27)  4043.97 ( 40)  4347.27 ( 43)
   |- CPU #28    404.40 (  4)  2729.68 ( 27)  4043.97 ( 40)  4347.27 ( 43)
   |- CPU #29    404.40 (  4)  2729.68 ( 27)  4043.97 ( 40)  4347.27 ( 43)
   |- CPU #30    404.40 (  4)  2729.68 ( 27)  4043.97 ( 40)  4347.27 ( 43)
   |- CPU #31    404.40 (  4)  2729.68 ( 27)  4043.97 ( 40)  4347.27 ( 43)
   |- CPU #32    404.40 (  4)  2729.68 ( 27)  4043.97 ( 40)  4347.27 ( 43)
   |- CPU #33    404.40 (  4)  2729.68 ( 27)  4043.97 ( 40)  4347.27 ( 43)
   |- CPU #34    404.40 (  4)  2729.68 ( 27)  4043.97 ( 40)  4347.27 ( 43)
   |- CPU #35    404.40 (  4)  2729.68 ( 27)  4043.97 ( 40)  4347.27 ( 43)
   |- CPU #36    404.40 (  4)  2729.68 ( 27)  4043.97 ( 40)  4347.26 ( 43)
   |- CPU #37    404.40 (  4)  2729.68 ( 27)  4043.97 ( 40)  4347.27 ( 43)
   |- CPU #38    404.40 (  4)  2729.68 ( 27)  4043.97 ( 40)  4347.27 ( 43)
   |- CPU #39    404.40 (  4)  2729.68 ( 27)  4043.97 ( 40)  4347.27 ( 43)
   |- CPU #40    404.40 (  4)  2729.68 ( 27)  4043.97 ( 40)  4347.27 ( 43)
   |- CPU #41    404.40 (  4)  2729.68 ( 27)  4043.97 ( 40)  4347.27 ( 43)
   |- CPU #42    404.40 (  4)  2729.68 ( 27)  4043.97 ( 40)  4347.27 ( 43)
   |- CPU #43    404.40 (  4)  2729.68 ( 27)  4043.97 ( 40)  4347.27 ( 43)
   |- CPU #44    404.40 (  4)  2729.68 ( 27)  4043.97 ( 40)  4347.27 ( 43)
   |- CPU #45    404.40 (  4)  2729.68 ( 27)  4043.97 ( 40)  4347.27 ( 43)
   |- CPU #46    404.40 (  4)  2729.68 ( 27)  4043.97 ( 40)  4347.27 ( 43)
   |- CPU #47    404.40 (  4)  2729.68 ( 27)  4043.97 ( 40)  4347.27 ( 43)

[ 0] HPE
[ 1] 1.58
[ 2] 01/04/2024
[ 3] HPE
[ 4] ProLiant DL345 Gen11
[ 5]
[ 6] M---3---W-
[ 7] P58792-B21
[ 8] ProLiant
[ 9] HPE
[10] ProLiant DL345 Gen11
[11]
[12] P---C---G---A-
[13] Number Of Devices:12\Maximum Capacity:6597069766656 kilobytes
[14] PROC 1 DIMM 1\PROC 1 DIMM 1
[15] PROC 1 DIMM 2\PROC 1 DIMM 2
[16] PROC 1 DIMM 3\PROC 1 DIMM 3
[17] PROC 1 DIMM 4\PROC 1 DIMM 4
[18] Samsung
[19] Samsung
[20] Samsung
[21] Samsung
[22] M321RYGA0BB0-CQKZJ
[23] M321RYGA0BB0-CQKZJ
[24] M321RYGA0BB0-CQKZJ
[25] M321RYGA0BB0-CQKZJ

                              Zen UMC  [14AD]
Controller #0                                                    Disabled
 Bus Rate  2400 MHz       Bus Speed 2426 MHz       REG DDR5 Speed 4852 MT/s

 Cha   CL  RCDr RCDw  RP  RAS   RC  RRDs RRDl FAW  WTRs WTRl  WR  clRR clWW
  #0   40   39   39   39   77  116    8   12   32    6   24   72    5   41
  #1   40   39   39   39   77  116    8   12   32    6   24   72    5   41
  #2   40   39   39   39   77  116    8   12   32    6   24   72    5   41
  #3   40   39   39   39   77  116    8   12   32    6   24   72    5   41
  #4   40   39   39   39   77  116    8   12   32    6   24   72    5   41
  #5   40   39   39   39   77  116    8   12   32    6   24   72    5   41
  #6   40   39   39   39   77  116    8   12   32    6   24   72    5   41
  #7   40   39   39   39   77  116    8   12   32    6   24   72    5   41
  #8   40   39   39   39   77  116    8   12   32    6   24   72    5   41
  #9   40   39   39   39   77  116    8   12   32    6   24   72    5   41
  #10  40   39   39   39   77  116    8   12   32    6   24   72    5   41
  #11  40   39   39   39   77  116    8   12   32    6   24   72    5   41
      CWL  RTP RdWr WrRd scWW sdWW ddWW scRR sdRR ddRR drRR drWW drWR drRRD
  #0   38   18   20    5    1    9    9    1    8    8    0    0    0    0
  #1   38   18   20    5    1    9    9    1    8    8    0    0    0    0
  #2   38   18   20    5    1    9    9    1    8    8    0    0    0    0
  #3   38   18   19    5    1    9    9    1    8    8    0    0    0    0
  #4   38   18   20    5    1    9    9    1    8    8    0    0    0    0
  #5   38   18   20    5    1    9    9    1    8    8    0    0    0    0
  #6   38   18   20    5    1    9    9    1    8    8    0    0    0    0
  #7   38   18   20    5    1    9    9    1    8    8    0    0    0    0
  #8   38   18   20    5    1    9    9    1    8    8    0    0    0    0
  #9   38   18   19    5    1    9    9    1    8    8    0    0    0    0
  #10  38   18   20    5    1    9    9    1    8    8    0    0    0    0
  #11  38   18   20    5    1    9    9    1    8    8    0    0    0    0
      REFI RFC1 RFC2 RFCsb RCPB RPPB BGS:Alt  Ban  Page  CKE  CMD  GDM  ECC
  #0  9347  983  528  456   0    0    ON OFF  R0W0   0    0   1T   OFF   1
  #1  9347  983  528  456   0    0    ON OFF  R0W0   0    0   1T   OFF   1
  #2  9347  983  528  456   0    0    ON OFF  R0W0   0    0   1T   OFF   1
  #3  9347  983  528  456   0    0    ON OFF  R0W0   0    0   1T   OFF   1
  #4  9347  983  528  456   0    0    ON OFF  R0W0   0    0   1T   OFF   1
  #5  9347  983  528  456   0    0    ON OFF  R0W0   0    0   1T   OFF   1
  #6  9347  983  528  456   0    0    ON OFF  R0W0   0    0   1T   OFF   1
  #7  9347  983  528  456   0    0    ON OFF  R0W0   0    0   1T   OFF   1
  #8  9347  983  528  456   0    0    ON OFF  R0W0   0    0   1T   OFF   1
  #9  9347  983  528  456   0    0    ON OFF  R0W0   0    0   1T   OFF   1
  #10 9347  983  528  456   0    0    ON OFF  R0W0   0    0   1T   OFF   1
  #11 9347  983  528  456   0    0    ON OFF  R0W0   0    0   1T   OFF   1
      MRD:PDA   MOD:PDA  WRMPR STAG PDM RDDATA WRD  WRL  RDL  XS   XP CPDED
  #0   32  32    32  32    24   36 0:P:0   31   6   29   36 1007   18   12
  #1   32  32    32  32    24   36 0:P:0   31   6   29   36 1007   18   12
  #2   32  32    32  32    24   36 0:P:0   31   6   29   36 1007   18   12
  #3   32  32    32  32    24   36 0:P:0   31   6   29   34 1007   18   12
  #4   32  32    32  32    24   36 0:P:0   31   6   29   36 1007   18   12
  #5   32  32    32  32    24   36 0:P:0   31   6   29   36 1007   18   12
  #6   32  32    32  32    24   36 0:P:0   31   6   29   36 1007   18   12
  #7   32  32    32  32    24   36 0:P:0   31   6   29   36 1007   18   12
  #8   32  32    32  32    24   36 0:P:0   31   6   29   36 1007   18   12
  #9   32  32    32  32    24   36 0:P:0   31   6   29   34 1007   18   12
  #10  32  32    32  32    24   36 0:P:0   31   6   29   34 1007   18   12
  #11  32  32    32  32    24   36 0:P:0   31   6   29   36 1007   18   12

 DIMM Geometry for channel #0
      Slot Bank Rank     Rows   Columns    Memory Size (MB)
       #0    32    1    131072      2048          65536  M321RYGA0BB0-CQKZJ
       #1
 DIMM Geometry for channel #1
      Slot Bank Rank     Rows   Columns    Memory Size (MB)
       #0    32    1    131072      2048          65536  M321RYGA0BB0-CQKZJ
       #1
 DIMM Geometry for channel #2
      Slot Bank Rank     Rows   Columns    Memory Size (MB)
       #0    32    1    131072      2048          65536  M321RYGA0BB0-CQKZJ
       #1
 DIMM Geometry for channel #3
      Slot Bank Rank     Rows   Columns    Memory Size (MB)
       #0    32    1    131072      2048          65536  M321RYGA0BB0-CQKZJ
       #1
 DIMM Geometry for channel #4
      Slot Bank Rank     Rows   Columns    Memory Size (MB)
       #0    32    1    131072      2048          65536  M321RYGA0BB0-CQKZJ
       #1
 DIMM Geometry for channel #5
      Slot Bank Rank     Rows   Columns    Memory Size (MB)
       #0    32    1    131072      2048          65536  M321RYGA0BB0-CQKZJ
       #1
 DIMM Geometry for channel #6
      Slot Bank Rank     Rows   Columns    Memory Size (MB)
       #0    32    1    131072      2048          65536  M321RYGA0BB0-CQKZJ
       #1
 DIMM Geometry for channel #7
      Slot Bank Rank     Rows   Columns    Memory Size (MB)
       #0    32    1    131072      2048          65536  M321RYGA0BB0-CQKZJ
       #1
 DIMM Geometry for channel #8
      Slot Bank Rank     Rows   Columns    Memory Size (MB)
       #0    32    1    131072      2048          65536  M321RYGA0BB0-CQKZJ
       #1
 DIMM Geometry for channel #9
      Slot Bank Rank     Rows   Columns    Memory Size (MB)
       #0    32    1    131072      2048          65536  M321RYGA0BB0-CQKZJ
       #1
 DIMM Geometry for channel #10
      Slot Bank Rank     Rows   Columns    Memory Size (MB)
       #0    32    1    131072      2048          65536  M321RYGA0BB0-CQKZJ
       #1
 DIMM Geometry for channel #11
      Slot Bank Rank     Rows   Columns    Memory Size (MB)
       #0    32    1    131072      2048          65536  M321RYGA0BB0-CQKZJ
       #1

Linux:
|- Release                                                      [6.5.0-1018-oem]
|- Version         [#19-Ubuntu SMP PREEMPT_DYNAMIC Thu Mar 14 21:40:46 UTC 2024]
|- Machine                                                              [x86_64]
Memory:
|- Total RAM                                                       1188654896 KB
|- Shared RAM                                                       859928224 KB
|- Free RAM                                                          49593740 KB
|- Buffer RAM                                                          757016 KB
|- Total High                                                               0 KB
|- Free High                                                                0 KB
Clock Source                                                  <             tsc>
CPU-Freq driver                                               [      amd-pstate]
Governor                                                      [     performance]
CPU-Idle driver                                               [       acpi_idle]
|- Idle Limit                                                 [              C2]
   |- State        POLL      C1      C2
   |-           CPUIDLE ACPI FF ACPI IO
   |- Power          -1       0       0
   |- Latency         0       1      18
   |- Residency       0       2      36

CPU Freq(MHz) VID  Vcore  TMP(C)    Accumulator       Energy(J)     Power(W)
000 4154.88   183  1.1438   47  000000000000299498    4.569976807   4.569976807
001 1912.14   183  1.1438   46  000000000000233454    3.562225342   3.562225342
002 1937.81   183  1.1438   46  000000000000247121    3.770767212   3.770767212
003 1860.08   183  1.1438   45  000000000000225962    3.447906494   3.447906494
004 1913.62   183  1.1438   46  000000000000235448    3.592651367   3.592651367
005 2100.28   183  1.1438   46  000000000000251572    3.838684082   3.838684082
006 1932.31   184  1.1500   45  000000000000216682    3.306304932   3.306304932
007 3559.21   184  1.1500   44  000000000000265083    4.044845581   4.044845581
008 1726.96   184  1.1500   44  000000000000214621    3.274856567   3.274856567
009 1982.01   184  1.1500   42  000000000000269450    4.111480713   4.111480713
010 1934.85   184  1.1500   42  000000000000235321    3.590713501   3.590713501
011 1936.73   184  1.1500   42  000000000000243263    3.711898804   3.711898804
012 2247.38   183  1.1438   44  000000000000237227    3.619796753   3.619796753
013 2081.39   183  1.1438   44  000000000000234486    3.577972412   3.577972412
014 3618.75   183  1.1438   44  000000000000349899    5.339035034   5.339035034
015 2326.15   183  1.1438   42  000000000000247739    3.780197144   3.780197144
016 2513.36   183  1.1438   42  000000000000270469    4.127029419   4.127029419
017 2133.88   183  1.1438   42  000000000000237484    3.623718262   3.623718262
018 1631.22   184  1.1500   46  000000000000212608    3.244140625   3.244140625
019 1525.88   184  1.1500   46  000000000000191242    2.918121338   2.918121338
020 1537.82   184  1.1500   46  000000000000207364    3.164123535   3.164123535
021 1658.47   184  1.1500   46  000000000000218501    3.334060669   3.334060669
022 1698.20   184  1.1500   46  000000000000236623    3.610580444   3.610580444
023 1823.60   184  1.1500   46  000000000000230500    3.517150879   3.517150879
024 1791.82   183  1.1438   46  000000000000000000    0.000000000   0.000000000
025 1728.60   183  1.1438   46  000000000000000000    0.000000000   0.000000000
026 1868.98   183  1.1438   46  000000000000000000    0.000000000   0.000000000
027 1841.32   183  1.1438   46  000000000000000000    0.000000000   0.000000000
028 1948.04   183  1.1438   46  000000000000000000    0.000000000   0.000000000
029 2032.12   183  1.1438   46  000000000000000000    0.000000000   0.000000000
030 1538.26   184  1.1500   44  000000000000000000    0.000000000   0.000000000
031 2336.78   184  1.1500   44  000000000000000000    0.000000000   0.000000000
032 1714.61   184  1.1500   44  000000000000000000    0.000000000   0.000000000
033 4153.87   184  1.1500   42  000000000000000000    0.000000000   0.000000000
034 1914.31   184  1.1500   42  000000000000000000    0.000000000   0.000000000
035 1886.97   184  1.1500   42  000000000000000000    0.000000000   0.000000000
036 2181.18   183  1.1438   44  000000000000000000    0.000000000   0.000000000
037 2323.41   183  1.1438   44  000000000000000000    0.000000000   0.000000000
038 2255.56   183  1.1438   44  000000000000000000    0.000000000   0.000000000
039 2153.99   183  1.1438   42  000000000000000000    0.000000000   0.000000000
040 2381.70   183  1.1438   42  000000000000000000    0.000000000   0.000000000
041 2181.16   183  1.1438   42  000000000000000000    0.000000000   0.000000000
042 1702.48   184  1.1500   46  000000000000000000    0.000000000   0.000000000
043 1366.00   184  1.1500   46  000000000000000000    0.000000000   0.000000000
044 1601.79   184  1.1500   46  000000000000000000    0.000000000   0.000000000
045 1754.73   184  1.1500   46  000000000000000000    0.000000000   0.000000000
046 4154.88   184  1.1500   46  000000000000000000    0.000000000   0.000000000
047 1915.94   184  1.1500   46  000000000000000000    0.000000000   0.000000000

             Package[0]    Cores         Uncore        Memory        Platform
Energy(J): 156.348937988  88.678237915  29.650711060   0.000000000   0.000000000
Power(W) : 156.348937988  88.678237915  29.650711060   0.000000000   0.000000000


CPU     IPS            IPC            CPI
000     1.264158/s     1.264157/c     0.791041/i
001     0.357006/s     2.006611/c     0.498353/i
002     0.454265/s     1.959536/c     0.510325/i
003     0.476303/s     2.281499/c     0.438308/i
004     0.692764/s     2.097233/c     0.476819/i
005     0.880800/s     2.534534/c     0.394550/i
006     0.519501/s     2.063373/c     0.484643/i
007     0.360482/s     1.651127/c     0.605647/i
008     0.260595/s     1.616141/c     0.618758/i
009     0.470489/s     1.736760/c     0.575785/i
010     0.225451/s     1.669842/c     0.598859/i
011     0.154493/s     1.194131/c     0.837429/i
012     0.431097/s     1.354858/c     0.738085/i
013     0.507504/s     1.742507/c     0.573886/i
014     2.094940/s     2.094940/c     0.477341/i
015     0.215139/s     0.907528/c     1.101894/i
016     0.364123/s     1.251673/c     0.798931/i
017     0.360520/s     1.173886/c     0.851872/i
018     0.231032/s     1.454735/c     0.687410/i
019     0.174986/s     1.235650/c     0.809291/i
020     0.181693/s     1.364428/c     0.732908/i
021     0.172682/s     1.231783/c     0.811831/i
022     0.113896/s     0.879999/c     1.136365/i
023     0.111229/s     1.217100/c     0.821625/i
024     0.187730/s     1.366183/c     0.731967/i
025     0.192444/s     1.525635/c     0.655465/i
026     0.407544/s     1.874414/c     0.533500/i
027     0.525290/s     2.284043/c     0.437820/i
028     0.542800/s     1.851640/c     0.540062/i
029     0.237531/s     1.764825/c     0.566628/i
030     0.307411/s     1.624485/c     0.615580/i
031     0.924647/s     0.924647/c     1.081493/i
032     0.102146/s     0.842534/c     1.186895/i
033     0.823147/s     0.823146/c     1.214851/i
034     0.271408/s     1.495621/c     0.668619/i
035     0.197269/s     1.703865/c     0.586901/i
036     0.556279/s     1.660119/c     0.602367/i
037     0.356926/s     0.885227/c     1.129653/i
038     0.302332/s     1.244475/c     0.803552/i
039     0.471297/s     1.690849/c     0.591419/i
040     0.307201/s     1.130677/c     0.884426/i
041     0.272712/s     1.174556/c     0.851386/i
042     0.374068/s     1.640322/c     0.609636/i
043     0.157723/s     1.382155/c     0.723508/i
044     0.157465/s     1.174947/c     0.851102/i
045     0.199416/s     1.129669/c     0.885215/i
046     0.648318/s     0.648318/c     1.542454/i
047     0.142824/s     1.139500/c     0.877578/i


CPU Freq(MHz) VID  Min     Vcore   Max
000 4162.43   181  1.1188  1.1313  1.1500
001 1061.69   181  1.1188  1.1313  1.1500
002  988.31   180  1.1188  1.1250  1.1500
003 1188.09   181  1.1188  1.1313  1.1500
004 1267.98   180  1.1188  1.1250  1.1500
005 1286.57   181  1.1188  1.1313  1.1500
006 1078.33   182  1.1313  1.1375  1.1562
007 1361.68   182  1.1313  1.1375  1.1562
008 1260.71   182  1.1313  1.1375  1.1625
009 1229.99   182  1.1313  1.1375  1.1625
010  990.50   182  1.1313  1.1375  1.1562
011 1059.32   182  1.1313  1.1375  1.1562
012 1616.26   181  1.1188  1.1313  1.1500
013 1325.86   181  1.1188  1.1313  1.1500
014 4162.42   180  1.1188  1.1250  1.1500
015 1676.97   181  1.1188  1.1313  1.1500
016 1577.43   180  1.1188  1.1250  1.1500
017 1650.61   180  1.1188  1.1250  1.1500
018 1011.82   182  1.1313  1.1375  1.1625
019  979.31   182  1.1313  1.1375  1.1625
020 1030.34   182  1.1313  1.1375  1.1625
021 1001.07   182  1.1313  1.1375  1.1625
022 1143.51   182  1.1313  1.1375  1.1625
023 1043.40   182  1.1313  1.1375  1.1625
024 1034.64   180  1.1188  1.1250  1.1500
025  986.54   180  1.1188  1.1250  1.1500
026 1136.09   180  1.1188  1.1250  1.1500
027 1342.80   180  1.1188  1.1250  1.1500
028 1370.17   180  1.1188  1.1250  1.1500
029 1375.28   180  1.1188  1.1250  1.1500
030 1096.73   182  1.1313  1.1375  1.1625
031 4109.00   182  1.1313  1.1375  1.1625
032 1202.32   182  1.1313  1.1375  1.1625
033 4154.58   182  1.1313  1.1375  1.1625
034 1098.64   182  1.1313  1.1375  1.1625
035 1096.52   182  1.1313  1.1375  1.1625
036 1700.27   180  1.1188  1.1250  1.1500
037 1483.17   180  1.1188  1.1250  1.1500
038 1500.85   180  1.1188  1.1250  1.1500
039 1559.35   180  1.1188  1.1250  1.1500
040 1504.55   180  1.1188  1.1250  1.1500
041 1446.35   180  1.1188  1.1250  1.1500
042 1064.70   182  1.1313  1.1375  1.1625
043 1004.79   182  1.1313  1.1375  1.1625
044 1112.90   182  1.1313  1.1375  1.1625
045 1023.77   182  1.1313  1.1375  1.1625
046 4162.39   182  1.1313  1.1375  1.1625
047 1077.47   182  1.1313  1.1375  1.1625


CPU Freq(MHz)    Accumulator      Min  Energy(J) Max    Min  Power(W)  Max
000 4157.52  000000000000285729    4.04   4.36   4.70    4.04   4.36   4.70
001 1202.93  000000000000176594    1.49   2.69   3.64    1.49   2.69   3.64
002 1204.44  000000000000178601    1.69   2.73   3.77    1.69   2.73   3.77
003 1373.36  000000000000197349    1.13   3.01   3.89    1.13   3.01   3.89
004 1355.20  000000000000192354    1.44   2.94   3.69    1.44   2.94   3.69
005 1521.45  000000000000204454    1.43   3.12   3.84    1.43   3.12   3.84
006 1209.44  000000000000175859    2.32   2.68   4.12    2.32   2.68   4.12
007 1661.63  000000000000215840    1.64   3.29   4.04    1.64   3.29   4.04
008 1374.33  000000000000194910    1.44   2.97   3.66    1.44   2.97   3.66
009 3171.01  000000000000246651    1.26   3.76   4.11    1.26   3.76   4.11
010 1305.57  000000000000199200    1.32   3.04   3.59    1.32   3.04   3.59
011 1246.89  000000000000190082    1.63   2.90   4.73    1.63   2.90   4.73
012 1995.22  000000000000211279    1.68   3.22   5.79    1.68   3.22   5.79
013 1629.59  000000000000200438    1.86   3.06   3.87    1.86   3.06   3.87
014 2355.41  000000000000249530    1.70   3.81   5.69    1.70   3.81   5.69
015 1889.45  000000000000240723    2.14   3.67   5.62    2.14   3.67   5.62
016 1908.89  000000000000282559    2.06   4.31   5.78    2.06   4.31   5.78
017 1544.75  000000000000201088    1.50   3.07   4.34    1.50   3.07   4.34
018 1114.41  000000000000159990    1.08   2.44   3.38    1.08   2.44   3.38
019 1177.58  000000000000168219    1.09   2.57   3.31    1.09   2.57   3.31
020 1153.99  000000000000163060    1.07   2.49   3.40    1.07   2.49   3.40
021 1114.09  000000000000157445    1.11   2.40   3.81    1.11   2.40   3.81
022 1200.66  000000000000218201    2.96   3.33   3.68    2.96   3.33   3.68
023 1167.37  000000000000163952    1.19   2.50   3.52    1.19   2.50   3.52
024 1244.83  000000000000000000    0.00   0.00   0.00    0.00   0.00   0.00
025 1268.85  000000000000000000    0.00   0.00   0.00    0.00   0.00   0.00
026 1273.19  000000000000000000    0.00   0.00   0.00    0.00   0.00   0.00
027 1550.02  000000000000000000    0.00   0.00   0.00    0.00   0.00   0.00
028 1420.03  000000000000000000    0.00   0.00   0.00    0.00   0.00   0.00
029 1547.79  000000000000000000    0.00   0.00   0.00    0.00   0.00   0.00
030 1251.90  000000000000000000    0.00   0.00   0.00    0.00   0.00   0.00
031 2463.81  000000000000000000    0.00   0.00   0.00    0.00   0.00   0.00
032 1410.42  000000000000000000    0.00   0.00   0.00    0.00   0.00   0.00
033 2394.33  000000000000000000    0.00   0.00   0.00    0.00   0.00   0.00
034 1540.25  000000000000000000    0.00   0.00   0.00    0.00   0.00   0.00
035 1424.24  000000000000000000    0.00   0.00   0.00    0.00   0.00   0.00
036 1574.15  000000000000000000    0.00   0.00   0.00    0.00   0.00   0.00
037 1793.76  000000000000000000    0.00   0.00   0.00    0.00   0.00   0.00
038 1785.87  000000000000000000    0.00   0.00   0.00    0.00   0.00   0.00
039 2155.69  000000000000000000    0.00   0.00   0.00    0.00   0.00   0.00
040 2779.61  000000000000000000    0.00   0.00   0.00    0.00   0.00   0.00
041 1757.84  000000000000000000    0.00   0.00   0.00    0.00   0.00   0.00
042 1188.96  000000000000000000    0.00   0.00   0.00    0.00   0.00   0.00
043 1263.02  000000000000000000    0.00   0.00   0.00    0.00   0.00   0.00
044 1157.95  000000000000000000    0.00   0.00   0.00    0.00   0.00   0.00
045 1261.98  000000000000000000    0.00   0.00   0.00    0.00   0.00   0.00
046 4157.53  000000000000000000    0.00   0.00   0.00    0.00   0.00   0.00
047 1333.11  000000000000000000    0.00   0.00   0.00    0.00   0.00   0.00

Energy(J)  Package[0]         Cores               Uncore              Memory
 144.02169.12187.09   50.31 74.37 88.88    0.46 29.65 88.04    0.00  0.00  0.00
Power(W)
 144.02169.12187.09   50.31 74.37 88.88    0.46 29.65 88.04    0.00  0.00  0.00


CPU FLAG CF  ZF  SF  TF  IF  DF  OF IOPL NT  RF  VM  AC  VIF VIP ID
#0        1   1   1   0   1   1   1   0   0   0   0   0   0   0   0
#1        1   1   1   0   1   1   1   0   0   0   0   0   0   0   0
#2        1   1   1   0   1   1   1   0   0   0   0   0   0   0   0
#3        1   1   1   0   1   1   1   0   0   0   0   0   0   0   0
#4        1   1   1   0   1   1   1   0   0   0   0   0   0   0   0
#5        1   1   1   0   1   1   1   0   0   0   0   0   0   0   0
#6        1   1   1   0   1   1   1   0   0   0   0   0   0   0   0
#7        1   1   1   0   1   1   1   0   0   0   0   0   0   0   0
#8        1   1   1   0   1   1   1   0   0   0   0   0   0   0   0
#9        1   1   1   0   1   1   1   0   0   0   0   0   0   0   0
#10       1   1   1   0   1   1   1   0   0   0   0   0   0   0   0
#11       1   1   1   0   1   1   1   0   0   0   0   0   0   0   0
#12       1   1   1   0   1   1   1   0   0   0   0   0   0   0   0
#13       1   1   1   0   1   1   1   0   0   0   0   0   0   0   0
#14       1   1   1   0   1   1   1   0   0   0   0   0   0   0   0
#15       1   1   1   0   1   1   1   0   0   0   0   0   0   0   0
#16       1   1   1   0   1   1   1   0   0   0   0   0   0   0   0
#17       1   1   1   0   1   1   1   0   0   0   0   0   0   0   0
#18       1   1   1   0   1   1   1   0   0   0   0   0   0   0   0
#19       1   1   1   0   1   1   1   0   0   0   0   0   0   0   0
#20       1   1   1   0   1   1   1   0   0   0   0   0   0   0   0
#21       1   1   1   0   1   1   1   0   0   0   0   0   0   0   0
#22       1   1   1   0   1   1   1   0   0   0   0   0   0   0   0
#23       1   1   1   0   1   1   1   0   0   0   0   0   0   0   0
#24       1   1   1   0   1   1   1   0   0   0   0   0   0   0   0
#25       1   1   1   0   1   1   1   0   0   0   0   0   0   0   0
#26       1   1   1   0   1   1   1   0   0   0   0   0   0   0   0
#27       1   1   1   0   1   1   1   0   0   0   0   0   0   0   0
#28       1   1   1   0   1   1   1   0   0   0   0   0   0   0   0
#29       1   1   1   0   1   1   1   0   0   0   0   0   0   0   0
#30       1   1   1   0   1   1   1   0   0   0   0   0   0   0   0
#31       1   1   1   0   1   1   1   0   0   0   0   0   0   0   0
#32       1   1   1   0   1   1   1   0   0   0   0   0   0   0   0
#33       1   1   1   0   1   1   1   0   0   0   0   0   0   0   0
#34       1   1   1   0   1   1   1   0   0   0   0   0   0   0   0
#35       1   1   1   0   1   1   1   0   0   0   0   0   0   0   0
#36       1   1   1   0   1   1   1   0   0   0   0   0   0   0   0
#37       1   1   1   0   1   1   1   0   0   0   0   0   0   0   0
#38       1   1   1   0   1   1   1   0   0   0   0   0   0   0   0
#39       1   1   1   0   1   1   1   0   0   0   0   0   0   0   0
#40       1   1   1   0   1   1   1   0   0   0   0   0   0   0   0
#41       1   1   1   0   1   1   1   0   0   0   0   0   0   0   0
#42       1   1   1   0   1   1   1   0   0   0   0   0   0   0   0
#43       1   1   1   0   1   1   1   0   0   0   0   0   0   0   0
#44       1   1   1   0   1   1   1   0   0   0   0   0   0   0   0
#45       1   1   1   0   1   1   1   0   0   0   0   0   0   0   0
#46       1   1   1   0   1   1   1   0   0   0   0   0   0   0   0
#47       1   1   1   0   1   1   1   0   0   0   0   0   0   0   0
CR0: PE  MP  EM  TS  ET  NE  WP  AM  NW  CD  PG CR3: PWT PCD U57 U48
#0    1   1   0   0   1   1   1   1   0   0   1       0   0   0   0
#1    1   1   0   0   1   1   1   1   0   0   1       0   0   0   0
#2    1   1   0   0   1   1   1   1   0   0   1       0   0   0   0
#3    1   1   0   0   1   1   1   1   0   0   1       0   0   0   0
#4    1   1   0   0   1   1   1   1   0   0   1       0   0   0   0
#5    1   1   0   0   1   1   1   1   0   0   1       0   0   0   0
#6    1   1   0   0   1   1   1   1   0   0   1       0   0   0   0
#7    1   1   0   0   1   1   1   1   0   0   1       0   0   0   0
#8    1   1   0   0   1   1   1   1   0   0   1       0   0   0   0
#9    1   1   0   0   1   1   1   1   0   0   1       0   0   0   0
#10   1   1   0   0   1   1   1   1   0   0   1       0   0   0   0
#11   1   1   0   0   1   1   1   1   0   0   1       0   0   0   0
#12   1   1   0   0   1   1   1   1   0   0   1       0   0   0   0
#13   1   1   0   0   1   1   1   1   0   0   1       0   0   0   0
#14   1   1   0   0   1   1   1   1   0   0   1       0   0   0   0
#15   1   1   0   0   1   1   1   1   0   0   1       0   0   0   0
#16   1   1   0   0   1   1   1   1   0   0   1       0   0   0   0
#17   1   1   0   0   1   1   1   1   0   0   1       0   0   0   0
#18   1   1   0   0   1   1   1   1   0   0   1       0   0   0   0
#19   1   1   0   0   1   1   1   1   0   0   1       0   0   0   0
#20   1   1   0   0   1   1   1   1   0   0   1       0   0   0   0
#21   1   1   0   0   1   1   1   1   0   0   1       0   0   0   0
#22   1   1   0   0   1   1   1   1   0   0   1       0   0   0   0
#23   1   1   0   0   1   1   1   1   0   0   1       0   0   0   0
#24   1   1   0   0   1   1   1   1   0   0   1       0   0   0   0
#25   1   1   0   0   1   1   1   1   0   0   1       0   0   0   0
#26   1   1   0   0   1   1   1   1   0   0   1       0   0   0   0
#27   1   1   0   0   1   1   1   1   0   0   1       0   0   0   0
#28   1   1   0   0   1   1   1   1   0   0   1       0   0   0   0
#29   1   1   0   0   1   1   1   1   0   0   1       0   0   0   0
#30   1   1   0   0   1   1   1   1   0   0   1       0   0   0   0
#31   1   1   0   0   1   1   1   1   0   0   1       0   0   0   0
#32   1   1   0   0   1   1   1   1   0   0   1       0   0   0   0
#33   1   1   0   0   1   1   1   1   0   0   1       0   0   0   0
#34   1   1   0   0   1   1   1   1   0   0   1       0   0   0   0
#35   1   1   0   0   1   1   1   1   0   0   1       0   0   0   0
#36   1   1   0   0   1   1   1   1   0   0   1       0   0   0   0
#37   1   1   0   0   1   1   1   1   0   0   1       0   0   0   0
#38   1   1   0   0   1   1   1   1   0   0   1       0   0   0   0
#39   1   1   0   0   1   1   1   1   0   0   1       0   0   0   0
#40   1   1   0   0   1   1   1   1   0   0   1       0   0   0   0
#41   1   1   0   0   1   1   1   1   0   0   1       0   0   0   0
#42   1   1   0   0   1   1   1   1   0   0   1       0   0   0   0
#43   1   1   0   0   1   1   1   1   0   0   1       0   0   0   0
#44   1   1   0   0   1   1   1   1   0   0   1       0   0   0   0
#45   1   1   0   0   1   1   1   1   0   0   1       0   0   0   0
#46   1   1   0   0   1   1   1   1   0   0   1       0   0   0   0
#47   1   1   0   0   1   1   1   1   0   0   1       0   0   0   0
CR4: VME PVI TSD DE  PSE PAE MCE PGE PCE FX XMM UMIP 5LP VMX SMX FS
#0    0   0   0   0   1   1   1   1   0   1   1   1   1   0   0   1
#1    0   0   0   0   0   1   1   1   0   1   1   1   1   0   0   1
#2    0   0   0   0   0   1   1   1   0   1   1   1   1   0   0   1
#3    0   0   0   0   0   1   1   1   0   1   1   1   1   0   0   1
#4    0   0   0   0   0   1   1   1   0   1   1   1   1   0   0   1
#5    0   0   0   0   0   1   1   1   0   1   1   1   1   0   0   1
#6    0   0   0   0   0   1   1   1   0   1   1   1   1   0   0   1
#7    0   0   0   0   0   1   1   1   0   1   1   1   1   0   0   1
#8    0   0   0   0   0   1   1   1   0   1   1   1   1   0   0   1
#9    0   0   0   0   0   1   1   1   0   1   1   1   1   0   0   1
#10   0   0   0   0   0   1   1   1   0   1   1   1   1   0   0   1
#11   0   0   0   0   0   1   1   1   0   1   1   1   1   0   0   1
#12   0   0   0   0   0   1   1   1   0   1   1   1   1   0   0   1
#13   0   0   0   0   0   1   1   1   0   1   1   1   1   0   0   1
#14   0   0   0   0   0   1   1   1   0   1   1   1   1   0   0   1
#15   0   0   0   0   0   1   1   1   0   1   1   1   1   0   0   1
#16   0   0   0   0   0   1   1   1   0   1   1   1   1   0   0   1
#17   0   0   0   0   0   1   1   1   0   1   1   1   1   0   0   1
#18   0   0   0   0   0   1   1   1   0   1   1   1   1   0   0   1
#19   0   0   0   0   0   1   1   1   0   1   1   1   1   0   0   1
#20   0   0   0   0   0   1   1   1   0   1   1   1   1   0   0   1
#21   0   0   0   0   0   1   1   1   0   1   1   1   1   0   0   1
#22   0   0   0   0   0   1   1   1   0   1   1   1   1   0   0   1
#23   0   0   0   0   0   1   1   1   0   1   1   1   1   0   0   1
#24   0   0   0   0   0   1   1   1   0   1   1   1   1   0   0   1
#25   0   0   0   0   0   1   1   1   0   1   1   1   1   0   0   1
#26   0   0   0   0   0   1   1   1   0   1   1   1   1   0   0   1
#27   0   0   0   0   0   1   1   1   0   1   1   1   1   0   0   1
#28   0   0   0   0   0   1   1   1   0   1   1   1   1   0   0   1
#29   0   0   0   0   0   1   1   1   0   1   1   1   1   0   0   1
#30   0   0   0   0   0   1   1   1   0   1   1   1   1   0   0   1
#31   0   0   0   0   0   1   1   1   0   1   1   1   1   0   0   1
#32   0   0   0   0   0   1   1   1   0   1   1   1   1   0   0   1
#33   0   0   0   0   0   1   1   1   0   1   1   1   1   0   0   1
#34   0   0   0   0   0   1   1   1   0   1   1   1   1   0   0   1
#35   0   0   0   0   0   1   1   1   0   1   1   1   1   0   0   1
#36   0   0   0   0   0   1   1   1   0   1   1   1   1   0   0   1
#37   0   0   0   0   0   1   1   1   0   1   1   1   1   0   0   1
#38   0   0   0   0   0   1   1   1   0   1   1   1   1   0   0   1
#39   0   0   0   0   0   1   1   1   0   1   1   1   1   0   0   1
#40   0   0   0   0   0   1   1   1   0   1   1   1   1   0   0   1
#41   0   0   0   0   0   1   1   1   0   1   1   1   1   0   0   1
#42   0   0   0   0   0   1   1   1   0   1   1   1   1   0   0   1
#43   0   0   0   0   0   1   1   1   0   1   1   1   1   0   0   1
#44   0   0   0   0   0   1   1   1   0   1   1   1   1   0   0   1
#45   0   0   0   0   0   1   1   1   0   1   1   1   1   0   0   1
#46   0   0   0   0   0   1   1   1   0   1   1   1   1   0   0   1
#47   0   0   0   0   0   1   1   1   0   1   1   1   1   0   0   1
CR4:PCID SAV  KL SME SMA PKE CET PKS U-I LAM FRD            CR8: TPL
#0    1   1   0   1   1   1   0   0   0   0   0                   0
#1    1   1   0   1   1   1   0   0   0   0   0                   0
#2    1   1   0   1   1   1   0   0   0   0   0                   0
#3    1   1   0   1   1   1   0   0   0   0   0                   0
#4    1   1   0   1   1   1   0   0   0   0   0                   0
#5    1   1   0   1   1   1   0   0   0   0   0                   0
#6    1   1   0   1   1   1   0   0   0   0   0                   0
#7    1   1   0   1   1   1   0   0   0   0   0                   0
#8    1   1   0   1   1   1   0   0   0   0   0                   0
#9    1   1   0   1   1   1   0   0   0   0   0                   0
#10   1   1   0   1   1   1   0   0   0   0   0                   0
#11   1   1   0   1   1   1   0   0   0   0   0                   0
#12   1   1   0   1   1   1   0   0   0   0   0                   0
#13   1   1   0   1   1   1   0   0   0   0   0                   0
#14   1   1   0   1   1   1   0   0   0   0   0                   0
#15   1   1   0   1   1   1   0   0   0   0   0                   0
#16   1   1   0   1   1   1   0   0   0   0   0                   0
#17   1   1   0   1   1   1   0   0   0   0   0                   0
#18   1   1   0   1   1   1   0   0   0   0   0                   0
#19   1   1   0   1   1   1   0   0   0   0   0                   0
#20   1   1   0   1   1   1   0   0   0   0   0                   0
#21   1   1   0   1   1   1   0   0   0   0   0                   0
#22   1   1   0   1   1   1   0   0   0   0   0                   0
#23   1   1   0   1   1   1   0   0   0   0   0                   0
#24   1   1   0   1   1   1   0   0   0   0   0                   0
#25   1   1   0   1   1   1   0   0   0   0   0                   0
#26   1   1   0   1   1   1   0   0   0   0   0                   0
#27   1   1   0   1   1   1   0   0   0   0   0                   0
#28   1   1   0   1   1   1   0   0   0   0   0                   0
#29   1   1   0   1   1   1   0   0   0   0   0                   0
#30   1   1   0   1   1   1   0   0   0   0   0                   0
#31   1   1   0   1   1   1   0   0   0   0   0                   0
#32   1   1   0   1   1   1   0   0   0   0   0                   0
#33   1   1   0   1   1   1   0   0   0   0   0                   0
#34   1   1   0   1   1   1   0   0   0   0   0                   0
#35   1   1   0   1   1   1   0   0   0   0   0                   0
#36   1   1   0   1   1   1   0   0   0   0   0                   0
#37   1   1   0   1   1   1   0   0   0   0   0                   0
#38   1   1   0   1   1   1   0   0   0   0   0                   0
#39   1   1   0   1   1   1   0   0   0   0   0                   0
#40   1   1   0   1   1   1   0   0   0   0   0                   0
#41   1   1   0   1   1   1   0   0   0   0   0                   0
#42   1   1   0   1   1   1   0   0   0   0   0                   0
#43   1   1   0   1   1   1   0   0   0   0   0                   0
#44   1   1   0   1   1   1   0   0   0   0   0                   0
#45   1   1   0   1   1   1   0   0   0   0   0                   0
#46   1   1   0   1   1   1   0   0   0   0   0                   0
#47   1   1   0   1   1   1   0   0   0   0   0                   0
EFCR    LCK VMX^SGX [SENTER] [ SGX ] LMC
#0        -   -   -   -   -   -   -   -
#1        -   -   -   -   -   -   -   -
#2        -   -   -   -   -   -   -   -
#3        -   -   -   -   -   -   -   -
#4        -   -   -   -   -   -   -   -
#5        -   -   -   -   -   -   -   -
#6        -   -   -   -   -   -   -   -
#7        -   -   -   -   -   -   -   -
#8        -   -   -   -   -   -   -   -
#9        -   -   -   -   -   -   -   -
#10       -   -   -   -   -   -   -   -
#11       -   -   -   -   -   -   -   -
#12       -   -   -   -   -   -   -   -
#13       -   -   -   -   -   -   -   -
#14       -   -   -   -   -   -   -   -
#15       -   -   -   -   -   -   -   -
#16       -   -   -   -   -   -   -   -
#17       -   -   -   -   -   -   -   -
#18       -   -   -   -   -   -   -   -
#19       -   -   -   -   -   -   -   -
#20       -   -   -   -   -   -   -   -
#21       -   -   -   -   -   -   -   -
#22       -   -   -   -   -   -   -   -
#23       -   -   -   -   -   -   -   -
#24       -   -   -   -   -   -   -   -
#25       -   -   -   -   -   -   -   -
#26       -   -   -   -   -   -   -   -
#27       -   -   -   -   -   -   -   -
#28       -   -   -   -   -   -   -   -
#29       -   -   -   -   -   -   -   -
#30       -   -   -   -   -   -   -   -
#31       -   -   -   -   -   -   -   -
#32       -   -   -   -   -   -   -   -
#33       -   -   -   -   -   -   -   -
#34       -   -   -   -   -   -   -   -
#35       -   -   -   -   -   -   -   -
#36       -   -   -   -   -   -   -   -
#37       -   -   -   -   -   -   -   -
#38       -   -   -   -   -   -   -   -
#39       -   -   -   -   -   -   -   -
#40       -   -   -   -   -   -   -   -
#41       -   -   -   -   -   -   -   -
#42       -   -   -   -   -   -   -   -
#43       -   -   -   -   -   -   -   -
#44       -   -   -   -   -   -   -   -
#45       -   -   -   -   -   -   -   -
#46       -   -   -   -   -   -   -   -
#47       -   -   -   -   -   -   -   -
EFER     SCE LME LMA NX SVM LMS FFX TCE MCM WBI UAI IBRS
#0        1   1   1   1   0   0   0   0   0   0   0   1
#1        1   1   1   1   0   0   0   0   0   0   0   1
#2        1   1   1   1   0   0   0   0   0   0   0   1
#3        1   1   1   1   0   0   0   0   0   0   0   1
#4        1   1   1   1   0   0   0   0   0   0   0   1
#5        1   1   1   1   0   0   0   0   0   0   0   1
#6        1   1   1   1   0   0   0   0   0   0   0   1
#7        1   1   1   1   0   0   0   0   0   0   0   1
#8        1   1   1   1   0   0   0   0   0   0   0   1
#9        1   1   1   1   0   0   0   0   0   0   0   1
#10       1   1   1   1   0   0   0   0   0   0   0   1
#11       1   1   1   1   0   0   0   0   0   0   0   1
#12       1   1   1   1   0   0   0   0   0   0   0   1
#13       1   1   1   1   0   0   0   0   0   0   0   1
#14       1   1   1   1   0   0   0   0   0   0   0   1
#15       1   1   1   1   0   0   0   0   0   0   0   1
#16       1   1   1   1   0   0   0   0   0   0   0   1
#17       1   1   1   1   0   0   0   0   0   0   0   1
#18       1   1   1   1   0   0   0   0   0   0   0   1
#19       1   1   1   1   0   0   0   0   0   0   0   1
#20       1   1   1   1   0   0   0   0   0   0   0   1
#21       1   1   1   1   0   0   0   0   0   0   0   1
#22       1   1   1   1   0   0   0   0   0   0   0   1
#23       1   1   1   1   0   0   0   0   0   0   0   1
#24       1   1   1   1   0   0   0   0   0   0   0   1
#25       1   1   1   1   0   0   0   0   0   0   0   1
#26       1   1   1   1   0   0   0   0   0   0   0   1
#27       1   1   1   1   0   0   0   0   0   0   0   1
#28       1   1   1   1   0   0   0   0   0   0   0   1
#29       1   1   1   1   0   0   0   0   0   0   0   1
#30       1   1   1   1   0   0   0   0   0   0   0   1
#31       1   1   1   1   0   0   0   0   0   0   0   1
#32       1   1   1   1   0   0   0   0   0   0   0   1
#33       1   1   1   1   0   0   0   0   0   0   0   1
#34       1   1   1   1   0   0   0   0   0   0   0   1
#35       1   1   1   1   0   0   0   0   0   0   0   1
#36       1   1   1   1   0   0   0   0   0   0   0   1
#37       1   1   1   1   0   0   0   0   0   0   0   1
#38       1   1   1   1   0   0   0   0   0   0   0   1
#39       1   1   1   1   0   0   0   0   0   0   0   1
#40       1   1   1   1   0   0   0   0   0   0   0   1
#41       1   1   1   1   0   0   0   0   0   0   0   1
#42       1   1   1   1   0   0   0   0   0   0   0   1
#43       1   1   1   1   0   0   0   0   0   0   0   1
#44       1   1   1   1   0   0   0   0   0   0   0   1
#45       1   1   1   1   0   0   0   0   0   0   0   1
#46       1   1   1   1   0   0   0   0   0   0   0   1
#47       1   1   1   1   0   0   0   0   0   0   0   1
XCR0     FPU SSE AVX MPX 512 MPK CEU CES AMX APX LWP
#0        1   1   1   0   7   1   0   0   0   0   0
#1        1   1   1   0   7   1   0   0   0   0   0
#2        1   1   1   0   7   1   0   0   0   0   0
#3        1   1   1   0   7   1   0   0   0   0   0
#4        1   1   1   0   7   1   0   0   0   0   0
#5        1   1   1   0   7   1   0   0   0   0   0
#6        1   1   1   0   7   1   0   0   0   0   0
#7        1   1   1   0   7   1   0   0   0   0   0
#8        1   1   1   0   7   1   0   0   0   0   0
#9        1   1   1   0   7   1   0   0   0   0   0
#10       1   1   1   0   7   1   0   0   0   0   0
#11       1   1   1   0   7   1   0   0   0   0   0
#12       1   1   1   0   7   1   0   0   0   0   0
#13       1   1   1   0   7   1   0   0   0   0   0
#14       1   1   1   0   7   1   0   0   0   0   0
#15       1   1   1   0   7   1   0   0   0   0   0
#16       1   1   1   0   7   1   0   0   0   0   0
#17       1   1   1   0   7   1   0   0   0   0   0
#18       1   1   1   0   7   1   0   0   0   0   0
#19       1   1   1   0   7   1   0   0   0   0   0
#20       1   1   1   0   7   1   0   0   0   0   0
#21       1   1   1   0   7   1   0   0   0   0   0
#22       1   1   1   0   7   1   0   0   0   0   0
#23       1   1   1   0   7   1   0   0   0   0   0
#24       1   1   1   0   7   1   0   0   0   0   0
#25       1   1   1   0   7   1   0   0   0   0   0
#26       1   1   1   0   7   1   0   0   0   0   0
#27       1   1   1   0   7   1   0   0   0   0   0
#28       1   1   1   0   7   1   0   0   0   0   0
#29       1   1   1   0   7   1   0   0   0   0   0
#30       1   1   1   0   7   1   0   0   0   0   0
#31       1   1   1   0   7   1   0   0   0   0   0
#32       1   1   1   0   7   1   0   0   0   0   0
#33       1   1   1   0   7   1   0   0   0   0   0
#34       1   1   1   0   7   1   0   0   0   0   0
#35       1   1   1   0   7   1   0   0   0   0   0
#36       1   1   1   0   7   1   0   0   0   0   0
#37       1   1   1   0   7   1   0   0   0   0   0
#38       1   1   1   0   7   1   0   0   0   0   0
#39       1   1   1   0   7   1   0   0   0   0   0
#40       1   1   1   0   7   1   0   0   0   0   0
#41       1   1   1   0   7   1   0   0   0   0   0
#42       1   1   1   0   7   1   0   0   0   0   0
#43       1   1   1   0   7   1   0   0   0   0   0
#44       1   1   1   0   7   1   0   0   0   0   0
#45       1   1   1   0   7   1   0   0   0   0   0
#46       1   1   1   0   7   1   0   0   0   0   0
#47       1   1   1   0   7   1   0   0   0   0   0
CFG:     MFD MDM MVD TOM FWB MEM SNP PL  HMK
#0        1   0   1   1   1   0   0   0   0
#1        1   0   1   1   1   0   0   0   0
#2        1   0   1   1   1   0   0   0   0
#3        1   0   1   1   1   0   0   0   0
#4        1   0   1   1   1   0   0   0   0
#5        1   0   1   1   1   0   0   0   0
#6        1   0   1   1   1   0   0   0   0
#7        1   0   1   1   1   0   0   0   0
#8        1   0   1   1   1   0   0   0   0
#9        1   0   1   1   1   0   0   0   0
#10       1   0   1   1   1   0   0   0   0
#11       1   0   1   1   1   0   0   0   0
#12       1   0   1   1   1   0   0   0   0
#13       1   0   1   1   1   0   0   0   0
#14       1   0   1   1   1   0   0   0   0
#15       1   0   1   1   1   0   0   0   0
#16       1   0   1   1   1   0   0   0   0
#17       1   0   1   1   1   0   0   0   0
#18       1   0   1   1   1   0   0   0   0
#19       1   0   1   1   1   0   0   0   0
#20       1   0   1   1   1   0   0   0   0
#21       1   0   1   1   1   0   0   0   0
#22       1   0   1   1   1   0   0   0   0
#23       1   0   1   1   1   0   0   0   0
#24       1   0   1   1   1   0   0   0   0
#25       1   0   1   1   1   0   0   0   0
#26       1   0   1   1   1   0   0   0   0
#27       1   0   1   1   1   0   0   0   0
#28       1   0   1   1   1   0   0   0   0
#29       1   0   1   1   1   0   0   0   0
#30       1   0   1   1   1   0   0   0   0
#31       1   0   1   1   1   0   0   0   0
#32       1   0   1   1   1   0   0   0   0
#33       1   0   1   1   1   0   0   0   0
#34       1   0   1   1   1   0   0   0   0
#35       1   0   1   1   1   0   0   0   0
#36       1   0   1   1   1   0   0   0   0
#37       1   0   1   1   1   0   0   0   0
#38       1   0   1   1   1   0   0   0   0
#39       1   0   1   1   1   0   0   0   0
#40       1   0   1   1   1   0   0   0   0
#41       1   0   1   1   1   0   0   0   0
#42       1   0   1   1   1   0   0   0   0
#43       1   0   1   1   1   0   0   0   0
#44       1   0   1   1   1   0   0   0   0
#45       1   0   1   1   1   0   0   0   0
#46       1   0   1   1   1   0   0   0   0
#47       1   0   1   1   1   0   0   0   0
HWCR SMM SLW TLB WBI FF FERR IG  MW U-MW HLT SMI RSM SSE WRP MC  IO
#0    1   0   0   1   0   0   0   0   0   0   1   1   0   0   0   0
#1    1   0   0   1   0   0   0   0   0   0   1   1   0   0   0   0
#2    1   0   0   1   0   0   0   0   0   0   1   1   0   0   0   0
#3    1   0   0   1   0   0   0   0   0   0   1   1   0   0   0   0
#4    1   0   0   1   0   0   0   0   0   0   1   1   0   0   0   0
#5    1   0   0   1   0   0   0   0   0   0   1   1   0   0   0   0
#6    1   0   0   1   0   0   0   0   0   0   1   1   0   0   0   0
#7    1   0   0   1   0   0   0   0   0   0   1   1   0   0   0   0
#8    1   0   0   1   0   0   0   0   0   0   1   1   0   0   0   0
#9    1   0   0   1   0   0   0   0   0   0   1   1   0   0   0   0
#10   1   0   0   1   0   0   0   0   0   0   1   1   0   0   0   0
#11   1   0   0   1   0   0   0   0   0   0   1   1   0   0   0   0
#12   1   0   0   1   0   0   0   0   0   0   1   1   0   0   0   0
#13   1   0   0   1   0   0   0   0   0   0   1   1   0   0   0   0
#14   1   0   0   1   0   0   0   0   0   0   1   1   0   0   0   0
#15   1   0   0   1   0   0   0   0   0   0   1   1   0   0   0   0
#16   1   0   0   1   0   0   0   0   0   0   1   1   0   0   0   0
#17   1   0   0   1   0   0   0   0   0   0   1   1   0   0   0   0
#18   1   0   0   1   0   0   0   0   0   0   1   1   0   0   0   0
#19   1   0   0   1   0   0   0   0   0   0   1   1   0   0   0   0
#20   1   0   0   1   0   0   0   0   0   0   1   1   0   0   0   0
#21   1   0   0   1   0   0   0   0   0   0   1   1   0   0   0   0
#22   1   0   0   1   0   0   0   0   0   0   1   1   0   0   0   0
#23   1   0   0   1   0   0   0   0   0   0   1   1   0   0   0   0
#24   1   0   0   1   0   0   0   0   0   0   1   1   0   0   0   0
#25   1   0   0   1   0   0   0   0   0   0   1   1   0   0   0   0
#26   1   0   0   1   0   0   0   0   0   0   1   1   0   0   0   0
#27   1   0   0   1   0   0   0   0   0   0   1   1   0   0   0   0
#28   1   0   0   1   0   0   0   0   0   0   1   1   0   0   0   0
#29   1   0   0   1   0   0   0   0   0   0   1   1   0   0   0   0
#30   1   0   0   1   0   0   0   0   0   0   1   1   0   0   0   0
#31   1   0   0   1   0   0   0   0   0   0   1   1   0   0   0   0
#32   1   0   0   1   0   0   0   0   0   0   1   1   0   0   0   0
#33   1   0   0   1   0   0   0   0   0   0   1   1   0   0   0   0
#34   1   0   0   1   0   0   0   0   0   0   1   1   0   0   0   0
#35   1   0   0   1   0   0   0   0   0   0   1   1   0   0   0   0
#36   1   0   0   1   0   0   0   0   0   0   1   1   0   0   0   0
#37   1   0   0   1   0   0   0   0   0   0   1   1   0   0   0   0
#38   1   0   0   1   0   0   0   0   0   0   1   1   0   0   0   0
#39   1   0   0   1   0   0   0   0   0   0   1   1   0   0   0   0
#40   1   0   0   1   0   0   0   0   0   0   1   1   0   0   0   0
#41   1   0   0   1   0   0   0   0   0   0   1   1   0   0   0   0
#42   1   0   0   1   0   0   0   0   0   0   1   1   0   0   0   0
#43   1   0   0   1   0   0   0   0   0   0   1   1   0   0   0   0
#44   1   0   0   1   0   0   0   0   0   0   1   1   0   0   0   0
#45   1   0   0   1   0   0   0   0   0   0   1   1   0   0   0   0
#46   1   0   0   1   0   0   0   0   0   0   1   1   0   0   0   0
#47   1   0   0   1   0   0   0   0   0   0   1   1   0   0   0   0
HWCR P0  PRB INC CPB HCF ROC SMU CSE IR SMMB TPR PG U-ID
#0    0   0   1   0   0   1   0   0   1   1   1   0   0
#1    0   0   1   0   0   1   0   0   1   1   1   0   0
#2    0   0   1   0   0   1   0   0   1   1   1   0   0
#3    0   0   1   0   0   1   0   0   1   1   1   0   0
#4    0   0   1   0   0   1   0   0   1   1   1   0   0
#5    0   0   1   0   0   1   0   0   1   1   1   0   0
#6    0   0   1   0   0   1   0   0   1   1   1   0   0
#7    0   0   1   0   0   1   0   0   1   1   1   0   0
#8    0   0   1   0   0   1   0   0   1   1   1   0   0
#9    0   0   1   0   0   1   0   0   1   1   1   0   0
#10   0   0   1   0   0   1   0   0   1   1   1   0   0
#11   0   0   1   0   0   1   0   0   1   1   1   0   0
#12   0   0   1   0   0   1   0   0   1   1   1   0   0
#13   0   0   1   0   0   1   0   0   1   1   1   0   0
#14   0   0   1   0   0   1   0   0   1   1   1   0   0
#15   0   0   1   0   0   1   0   0   1   1   1   0   0
#16   0   0   1   0   0   1   0   0   1   1   1   0   0
#17   0   0   1   0   0   1   0   0   1   1   1   0   0
#18   0   0   1   0   0   1   0   0   1   1   1   0   0
#19   0   0   1   0   0   1   0   0   1   1   1   0   0
#20   0   0   1   0   0   1   0   0   1   1   1   0   0
#21   0   0   1   0   0   1   0   0   1   1   1   0   0
#22   0   0   1   0   0   1   0   0   1   1   1   0   0
#23   0   0   1   0   0   1   0   0   1   1   1   0   0
#24   0   0   1   0   0   1   0   0   1   1   1   0   0
#25   0   0   1   0   0   1   0   0   1   1   1   0   0
#26   0   0   1   0   0   1   0   0   1   1   1   0   0
#27   0   0   1   0   0   1   0   0   1   1   1   0   0
#28   0   0   1   0   0   1   0   0   1   1   1   0   0
#29   0   0   1   0   0   1   0   0   1   1   1   0   0
#30   0   0   1   0   0   1   0   0   1   1   1   0   0
#31   0   0   1   0   0   1   0   0   1   1   1   0   0
#32   0   0   1   0   0   1   0   0   1   1   1   0   0
#33   0   0   1   0   0   1   0   0   1   1   1   0   0
#34   0   0   1   0   0   1   0   0   1   1   1   0   0
#35   0   0   1   0   0   1   0   0   1   1   1   0   0
#36   0   0   1   0   0   1   0   0   1   1   1   0   0
#37   0   0   1   0   0   1   0   0   1   1   1   0   0
#38   0   0   1   0   0   1   0   0   1   1   1   0   0
#39   0   0   1   0   0   1   0   0   1   1   1   0   0
#40   0   0   1   0   0   1   0   0   1   1   1   0   0
#41   0   0   1   0   0   1   0   0   1   1   1   0   0
#42   0   0   1   0   0   1   0   0   1   1   1   0   0
#43   0   0   1   0   0   1   0   0   1   1   1   0   0
#44   0   0   1   0   0   1   0   0   1   1   1   0   0
#45   0   0   1   0   0   1   0   0   1   1   1   0   0
#46   0   0   1   0   0   1   0   0   1   1   1   0   0
#47   0   0   1   0   0   1   0   0   1   1   1   0   0

0 replies

cyring · 2024-03-30T09:31:25Z

cyring
Mar 30, 2024
Maintainer

Commit dc6280f fixes the spacing in the Power Monitoring bottom area, especially when a 3 digits power is measured.

Format:

corefreq-cli -W

CPU Freq(MHz)    Accumulator      Min  Energy(J) Max    Min  Power(W)  Max
000 3798.08  000000000000411306    0.00   6.28   8.87    0.00   6.28   8.87
001 3682.77  000000000000496376    0.00   7.57   8.20    0.00   7.57   8.20
002 3850.84  000000000000417714    0.00   6.37   9.53    0.00   6.37   9.53
003 3830.85  000000000000496311    0.00   7.57   8.59    0.00   7.57   8.59
004 3860.38  000000000000437088    0.00   6.67   8.64    0.00   6.67   8.64
005 3826.94  000000000000448859    0.00   6.85   8.19    0.00   6.85   8.19
006 3951.14  000000000000407283    0.00   6.21   8.10    0.00   6.21   8.10
007 3820.92  000000000000512015    0.00   7.81   8.20    0.00   7.81   8.20
008 3838.89  000000000000453518    0.00   6.92   7.74    0.00   6.92   7.74
009 3807.62  000000000000450171    0.00   6.87   8.38    0.00   6.87   8.38
010 3969.38  000000000000451074    0.00   6.88   7.74    0.00   6.88   7.74
011 4025.41  000000000000339855    0.00   5.19   7.88    0.00   5.19   7.88
012 3892.19  000000000000417007    0.00   6.36   7.74    0.00   6.36   7.74
013 3905.71  000000000000386342    0.00   5.90   7.68    0.00   5.90   7.68
014 3726.84  000000000000527824    0.00   8.05   9.04    0.00   8.05   9.04
015 3908.34  000000000000494423    0.00   7.54   8.21    0.00   7.54   8.21
016 3984.11  000000000000000000    0.00   0.00   0.00    0.00   0.00   0.00
017 3749.12  000000000000000000    0.00   0.00   0.00    0.00   0.00   0.00
018 3783.17  000000000000000000    0.00   0.00   0.00    0.00   0.00   0.00
019 3755.73  000000000000000000    0.00   0.00   0.00    0.00   0.00   0.00
020 3774.03  000000000000000000    0.00   0.00   0.00    0.00   0.00   0.00
021 3810.57  000000000000000000    0.00   0.00   0.00    0.00   0.00   0.00
022 4013.79  000000000000000000    0.00   0.00   0.00    0.00   0.00   0.00
023 3953.22  000000000000000000    0.00   0.00   0.00    0.00   0.00   0.00
024 3711.33  000000000000000000    0.00   0.00   0.00    0.00   0.00   0.00
025 4015.93  000000000000000000    0.00   0.00   0.00    0.00   0.00   0.00
026 3878.68  000000000000000000    0.00   0.00   0.00    0.00   0.00   0.00
027 3880.01  000000000000000000    0.00   0.00   0.00    0.00   0.00   0.00
028 3820.70  000000000000000000    0.00   0.00   0.00    0.00   0.00   0.00
029 3956.70  000000000000000000    0.00   0.00   0.00    0.00   0.00   0.00
030 3721.36  000000000000000000    0.00   0.00   0.00    0.00   0.00   0.00
031 3987.81  000000000000000000    0.00   0.00   0.00    0.00   0.00   0.00

Energy(J)  Package[0]         Cores               Uncore              Memory
 17.68 145.5 145.50   0.02 109.1 126.85  10.50  17.1  18.67   0.00   0.0   0.00
Power(W)
 17.68 145.5 145.50   0.02 109.1 126.85  10.50  17.1  18.67   0.00   0.0   0.00

Can you please show me yours ?

0 replies

garceri · 2024-04-05T19:36:15Z

garceri
Apr 5, 2024
Author

Compiled with that commit:

CPU Freq(MHz)    Accumulator      Min  Energy(J) Max    Min  Power(W)  Max
000 4158.46  000000000000287548    3.96   4.39   4.58    3.96   4.39   4.58
001  815.78  000000000000140811    0.99   2.15   3.20    0.99   2.15   3.20
002 1242.39  000000000000168693    0.99   2.57   3.03    0.99   2.57   3.03
003  822.40  000000000000134472    1.45   2.05   3.48    1.45   2.05   3.48
004  867.54  000000000000128800    1.06   1.97   3.56    1.06   1.97   3.56
005 4158.45  000000000000213139    1.61   3.25   3.49    1.61   3.25   3.49
006 1218.80  000000000000175362    1.39   2.68   3.88    1.39   2.68   3.88
007 1174.40  000000000000183114    1.41   2.79   3.61    1.41   2.79   3.61
008 1059.32  000000000000163275    1.34   2.49   3.43    1.34   2.49   3.43
009 1020.70  000000000000156604    1.77   2.39   4.36    1.77   2.39   4.36
010 1076.38  000000000000163866    1.43   2.50   3.77    1.43   2.50   3.77
011 1161.18  000000000000166150    1.35   2.54   3.44    1.35   2.54   3.44
012 1554.54  000000000000208391    1.59   3.18   3.88    1.59   3.18   3.88
013 1557.12  000000000000193716    1.50   2.96   3.97    1.50   2.96   3.97
014 1593.36  000000000000219877    1.92   3.36   4.09    1.92   3.36   4.09
015 2129.36  000000000000213482    2.09   3.26   3.95    2.09   3.26   3.95
016 1363.04  000000000000194069    2.33   2.96   3.79    2.33   2.96   3.79
017 2811.99  000000000000261894    2.65   4.00   4.36    2.65   4.00   4.36
018 1393.42  000000000000195983    1.56   2.99   3.38    1.56   2.99   3.38
019 1330.79  000000000000188547    2.06   2.88   3.46    2.06   2.88   3.46
020 1442.29  000000000000199629    1.42   3.05   3.31    1.42   3.05   3.31
021 1127.02  000000000000171821    1.02   2.62   4.11    1.02   2.62   4.11
022 1405.24  000000000000200195    0.55   3.05   3.93    0.55   3.05   3.93
023 2114.84  000000000000269604    2.28   4.11   5.29    2.28   4.11   5.29
024  987.82  000000000000000000    0.00   0.00   0.00    0.00   0.00   0.00
025  881.87  000000000000000000    0.00   0.00   0.00    0.00   0.00   0.00
026  998.60  000000000000000000    0.00   0.00   0.00    0.00   0.00   0.00
027  923.60  000000000000000000    0.00   0.00   0.00    0.00   0.00   0.00
028  898.90  000000000000000000    0.00   0.00   0.00    0.00   0.00   0.00
029 1102.39  000000000000000000    0.00   0.00   0.00    0.00   0.00   0.00
030 1150.28  000000000000000000    0.00   0.00   0.00    0.00   0.00   0.00
031 1320.70  000000000000000000    0.00   0.00   0.00    0.00   0.00   0.00
032 1094.68  000000000000000000    0.00   0.00   0.00    0.00   0.00   0.00
033 1050.02  000000000000000000    0.00   0.00   0.00    0.00   0.00   0.00
034 1147.96  000000000000000000    0.00   0.00   0.00    0.00   0.00   0.00
035 1094.74  000000000000000000    0.00   0.00   0.00    0.00   0.00   0.00
036 1929.81  000000000000000000    0.00   0.00   0.00    0.00   0.00   0.00
037 1689.75  000000000000000000    0.00   0.00   0.00    0.00   0.00   0.00
038 1725.64  000000000000000000    0.00   0.00   0.00    0.00   0.00   0.00
039 1429.20  000000000000000000    0.00   0.00   0.00    0.00   0.00   0.00
040 1668.44  000000000000000000    0.00   0.00   0.00    0.00   0.00   0.00
041 2993.88  000000000000000000    0.00   0.00   0.00    0.00   0.00   0.00
042 1368.23  000000000000000000    0.00   0.00   0.00    0.00   0.00   0.00
043 1432.18  000000000000000000    0.00   0.00   0.00    0.00   0.00   0.00
044 1646.60  000000000000000000    0.00   0.00   0.00    0.00   0.00   0.00
045 1360.20  000000000000000000    0.00   0.00   0.00    0.00   0.00   0.00
046 1654.89  000000000000000000    0.00   0.00   0.00    0.00   0.00   0.00
047 3433.35  000000000000000000    0.00   0.00   0.00    0.00   0.00   0.00

Energy(J)  Package[0]         Cores               Uncore              Memory
137.49 166.2 178.57  12.81  70.2  83.26   0.46  29.7  88.04   0.00   0.0   0.00
Power(W)
137.49 166.2 178.57  12.81  70.2  83.26   0.46  29.7  88.04   0.00   0.0   0.00

0 replies

cyring · 2024-04-05T22:35:12Z

cyring
Apr 5, 2024
Maintainer

Compiled with that commit:

Thank you.
It looks as expected.

Version 1.97.1 is now released.

0 replies

cyring · 2024-04-07T01:15:43Z

cyring
Apr 7, 2024
Maintainer

It looks like some bits have architecturally been fixed since kernel 6.8.4

I'm now reading the PSE of CR4 register set to 1 on all Cores rather than the only Bootstrap Core

Is it still case on Genoa ?

0 replies

cyring · 2024-04-07T08:39:22Z

cyring
Apr 7, 2024
Maintainer

Hello,

In this AMD HSMP source code, I'm reading an address exception for Zen family 1A

Can you edit and replace value of SMU_HSMP_CMD

CoreFreq/x86_64/amd_reg.h

Line 222 in 3a25d36

#define SMU_HSMP_CMD 0x3b10534

with this value:

#define SMU_HSMP_CMD		0x3b10934

I would also like to put the case AMD_Zen4_Genoa

CoreFreq/x86_64/corefreqk.c

Line 7892 in 3a25d36

case AMD_Zen4_Genoa:

as below:

	switch (PUBLIC(RO(Proc))->ArchID) {
	case AMD_Zen4_PHX2:
	case AMD_Zen4_HWK:
	case AMD_Zen4_PHX:
	case AMD_Zen4_RPL:
	case AMD_Zen3Plus_RMB:
	case AMD_Zen3_VMR:
	case AMD_Zen2_MTS:
		Core_AMD_SMN_Read(XtraCOF,
				SMU_AMD_F17H_MATISSE_COF,
				PRIVATE(OF(Zen)).Device.DF);
		break;
	case AMD_Zen4_Bergamo:
	case AMD_EPYC_Rome_CPK:
	case AMD_Zen4_Genoa:
		Core_AMD_SMN_Read(XtraCOF,
				SMU_AMD_F17H_ZEN2_MCM_COF,
				PRIVATE(OF(Zen)).Device.DF);
		break;
	}

Rebuild and reload CoreFreq

Finally post the output of corefreq-cli -s

Thank you for helping.

1 reply

cyring May 18, 2024
Maintainer

9476811

garceri · 2024-04-07T18:44:39Z

garceri
Apr 7, 2024
Author

Will do as soon as I can, pleased to help!

0 replies

garceri · 2024-04-18T18:53:26Z

garceri
Apr 18, 2024
Author

Here you go, sorry for the delay:

Processor                                     [AMD EPYC 9274F 24-Core Processor]
|- PPIN#                                                      [ 2b6a56a45d98031]
|- Architecture                                                     [EPYC/Genoa]
|- Vendor ID                                                      [AuthenticAMD]
|- Microcode                                                        [0x0a101144]
|- Signature                                                           [  AF_11]
|- Stepping                                                            [      1]
|- Online CPU                                                          [ 48/ 48]
|- Base Clock                                                          [101.099]
|- Frequency            (MHz)                      Ratio
                 Min   1516.48                    <  15 >
                 Max   4043.95                    <  40 >
|- Factory                                                             [100.000]
                       4000                       [  40 ]
|- Performance
   |- P-State
                 TGT   4043.95                    <  40 >
   |- CPPC
                 Min    808.79                    <   8 >
                 Max    101.10                    <   1 >
                 TGT    808.79                    <   8 >
|- Turbo Boost                                                         [   LOCK]
                 XFR    808.79                    [   8 ]
                 CPB    808.79                    [   8 ]
                  1C   2729.67                    <  27 >
                  2C   1516.48                    <  15 >
|- Uncore                                                              [   LOCK]
                 CLK   2426.37                    [  24 ]
                 MEM   2426.37                    [  24 ]

Instruction Set Extensions
|- 3DNow!/Ext [N/N]          ADX [Y]          AES [Y]  AVX/AVX2 [Y/Y]
|- AVX512-F     [Y]    AVX512-DQ [Y]  AVX512-IFMA [Y]   AVX512-PF [N]
|- AVX512-ER    [N]    AVX512-CD [Y]    AVX512-BW [Y]   AVX512-VL [Y]
|- AVX512-VBMI  [Y] AVX512-VBMI2 [Y]  AVX512-VNNI [Y]  AVX512-ALG [Y]
|- AVX512-VPOP  [Y] AVX512-VNNIW [N] AVX512-FMAPS [N] AVX512-VP2I [N]
|- AVX512-BF16  [Y] AVX-VNNI-VEX [N]    AVX-FP128 [N]   AVX-FP256 [Y]
|- BMI1/BMI2  [Y/Y]         CLWB [Y]      CLFLUSH [Y] CLFLUSH-OPT [Y]
|- CLAC-STAC    [Y]         CMOV [Y]    CMPXCHG8B [Y]  CMPXCHG16B [Y]
|- F16C         [Y]          FPU [Y]         FXSR [Y]   LAHF-SAHF [Y]
|- MMX/Ext    [Y/Y] MON/MWAITX [Y/Y]        MOVBE [Y]   PCLMULQDQ [Y]
|- POPCNT       [Y]       RDRAND [Y]       RDSEED [Y]      RDTSCP [Y]
|- SEP          [Y]          SHA [Y]          SSE [Y]        SSE2 [Y]
|- SSE3         [Y]        SSSE3 [Y]  SSE4.1/4A [Y/Y]      SSE4.2 [Y]
|- SERIALIZE    [N]      SYSCALL [Y]        RDPID [Y]        UMIP [Y]
|- VAES         [Y]   VPCLMULQDQ [Y]   PREFETCH/W [Y]       LZCNT [Y]

Features
|- 1 GB Pages Support                                      1GB-PAGES   [Capable]
|- 100 MHz multiplier Control                            100MHzSteps   [Missing]
|- Advanced Configuration & Power Interface                     ACPI   [Capable]
|- Advanced Programmable Interrupt Controller                   APIC   [Capable]
|- Advanced Virtual Interrupt Controller                        AVIC   [Capable]
|- APIC Timer Invariance                                        ARAT   [Capable]
|- LOCK prefix to read CR8                                    AltMov   [Capable]
|- Clear Zero Instruction                                     CLZERO   [Capable]
|- Core Multi-Processing                                  CMP Legacy   [Capable]
|- L1 Data Cache Context ID                                  CNXT-ID   [Missing]
|- Collaborative Processor Performance Control                  CPPC   [Capable]
|- Direct Cache Access                                           DCA   [Missing]
|- Debugging Extension                                            DE   [Capable]
|- Debug Store & Precise Event Based Sampling               DS, PEBS   [Missing]
|- CPL Qualified Debug Store                                  DS-CPL   [Missing]
|- 64-Bit Debug Store                                         DTES64   [Missing]
|- Fast Short REP MOVSB                                         FSRM   [Capable]
|- Fast-String Operation                                        ERMS   [Capable]
|- Fused Multiply Add                                           FMA4   [Missing]
|- Fused Multiply Add                                            FMA   [Capable]
|- Hardware Lock Elision                                         HLE   [Missing]
|- Hyper-Threading Technology                                    HTT   [Capable]
|- Hardware P-state control                                      HwP   [Capable]
|- Instruction Based Sampling                                    IBS   [Capable]
|- Instruction INVLPGB                                       INVLPGB   [Capable]
|- Instruction INVPCID                                       INVPCID   [Capable]
|- Long Mode 64 bits                                       IA64 | LM   [Capable]
|- LightWeight Profiling                                         LWP   [Missing]
|- Memory Bandwidth Enforcement                                  MBE   [Capable]
|- Machine-Check Architecture                                    MCA   [Capable]
|- Instruction MCOMMIT                                       MCOMMIT   [Missing]
|- Model Specific Registers                                      MSR   [Capable]
|- Memory Type Range Registers                                  MTRR   [Capable]
|- No-Execute Page Protection                                     NX   [Capable]
|- OS-Enabled Ext. State Management                          OSXSAVE   [Capable]
|- OS Visible Work-around                                       OSVW   [Capable]
|- Physical Address Extension                                    PAE   [Capable]
|- Page Attribute Table                                          PAT   [Capable]
|- Pending Break Enable                                          PBE   [Missing]
|- Process Context Identifiers                                  PCID   [Capable]
|- Perfmon and Debug Capability                                 PDCM   [Missing]
|- Page Global Enable                                            PGE   [Capable]
|- Page Size Extension                                           PSE   [Capable]
|- 36-bit Page Size Extension                                  PSE36   [Capable]
|- Processor Serial Number                                       PSN   [Missing]
|- Resource Director Technology/PQE                            RDT-A   [Capable]
|- Resource Director Technology/PQM                            RDT-M   [Capable]
|- Read Processor Register at User level                       RDPRU   [Capable]
|- Restricted Transactional Memory                               RTM   [Missing]
|- Safer Mode Extensions                                         SMX   [Missing]
|- Self-Snoop                                                     SS   [Missing]
|- Supervisor-Mode Access Prevention                            SMAP   [Capable]
|- Supervisor-Mode Execution Prevention                         SMEP   [Capable]
|- Trailing Bit Manipulation                                     TBM   [Missing]
|- Translation Cache Extension                                   TCE   [Capable]
|- Time Stamp Counter                                            TSC [Invariant]
|- Time Stamp Counter Deadline                          TSC-DEADLINE   [Missing]
|- TSX Force Abort MSR Register                            TSX-ABORT   [Missing]
|- TSX Suspend Load Address Tracking                       TSX-LDTRK   [Missing]
|- User-Mode Instruction Prevention                             UMIP   [Capable]
|- Virtual Mode Extension                                        VME   [Capable]
|- Virtual Machine Extensions                                    VMX   [Missing]
|- Write Back & Do Not Invalidate Cache                     WBNOINVD   [Capable]
|- Extended xAPIC Support                                     x2APIC   [  xAPIC]
|- AVIC controller for x2APIC                                 x2AVIC   [Capable]
|- XSAVE/XSTOR States                                          XSAVE   [Capable]
|- xTPR Update Control                                          xTPR   [Missing]
|- Extended Operation Support                                    XOP   [Missing]
Mitigation mechanisms
|- Indirect Branch Restricted Speculation                       IBRS   [Capable]
   |- IBRS Always-On preferred by processor                            [ Unable]
   |- IBRS preferred over software solution                            [Capable]
   |- IBRS provides same speculation limits                            [Capable]
|- Indirect Branch Prediction Barrier                           IBPB   [Capable]
|- Single Thread Indirect Branch Predictor                     STIBP   [ Enable]
|- Speculative Store Bypass Disable                             SSBD   [Capable]
   |- SSBD use VIRT_SPEC_CTRL register                                 [ Unable]
   |- SSBD not needed on this processor                                [ Unable]
|- No Branch Type Confusion                                   BTC_NO   [Capable]
|- BTC on Non-Branch instruction                            BTC-NOBR   [Capable]
|- Limited Early Redirect Window                            AGENPICK   [ Unable]
|- Arch - No Fast Predictive Store Forwarding                   PSFD   [Capable]
|- Arch - Enhanced Predictive Store Forwarding                  EPSF   [Capable]
|- Arch - Cross Processor Information Leak                XPROC_LEAK   [ Unable]
Security Features
|- CET Shadow Stack features                                  CET-SS   [Capable]
|- Secure Init and Jump with Attestation                      SKINIT   [Capable]
|- Secure Encrypted Virtualization                               SEV   [Capable]
|- SEV - Encrypted State                                      SEV-ES   [Capable]
|- SEV - Secure Nested Paging                                SEV-SNP   [Capable]
|- Guest Mode Execute Trap                                      GMET   [Capable]
|- Supervisor Shadow Stack                                       SSS   [Capable]
|- VM Permission Levels                                         VMPL   [Capable]
|- VMPL Supervisor Shadow Stack                             VMPL-SSS   [Capable]
|- Secure Memory Encryption                                      SME   [Capable]
|- Transparent SME                                              TSME   [ Enable]
|- Secure Multi-Key Memory Encryption                         SME-MK   [Capable]
|- DRAM Data Scrambling                                    Scrambler   [ Enable]

Technologies
|- Instruction Cache Unit
   |- L1 IP Prefetcher                                          L1 HW IP   <OFF>
|- Data Cache Unit
   |- L1 Prefetcher                                                L1 HW   <OFF>
|- Cache Prefetchers
   |- L2 Prefetcher                                                L2 HW   <OFF>
   |- L1 Stride Prefetcher                                     L1 Stride   <OFF>
   |- L1 Region Prefetcher                                     L1 Region   <OFF>
   |- L1 Burst Prefetch Mode                                    L1 Burst   <OFF>
   |- L2 Stream HW Prefetcher                                  L2 Stream   <OFF>
   |- L2 Up/Down Prefetcher                                   L2 Up/Down   <OFF>
|- System Management Mode                                       SMM-Lock   [ ON]
|- Simultaneous Multithreading                                       SMT   [ ON]
|- PowerNow!                                                         CnQ   [OFF]
|- Core C-States                                                     CCx   [ ON]
|- Core Performance Boost                                            CPB   < ON>
|- Watchdog Timer                                                    WDT   <OFF>
|- Virtualization                                                    SVM   [OFF]
   |- I/O MMU                                                      AMD-V   [OFF]
   |- Version                                                     [         N/A]
   |- Hypervisor                                                           [OFF]
   |- Vendor ID                                                   [         N/A]

Performance Monitoring
|- Version                                                        PM       [  2]
|- Counters:          General                   Fixed
|           {  6,  6, 16 } x 48 bits            3 x 64 bits
|- Enhanced Halt State                                           C1E       <OFF>
|- C2 UnDemotion                                                 C2U       < ON>
|- C3 UnDemotion                                                 C3U       < ON>
|- Core C6 State                                                 CC6       < ON>
|- Package C6 State                                              PC6       <OFF>
|- Legacy Frequency ID control                                   FID       [OFF]
|- Legacy Voltage ID control                                     VID       [OFF]
|- P-State Hardware Coordination Feedback                MPERF/APERF       [ ON]
|- Core C-States
   |- C-States Base Address                                      BAR   [ 0x413 ]
|- ACPI Processor C-States                                      _CST   [      2]
|- MONITOR/MWAIT
   |- State index:    #0    #1    #2    #3    #4    #5    #6    #7
   |- Sub C-State:     1     1     0     0     0     0     0     0
   |- Monitor-Mwait Extensions                                   EMX   [Capable]
   |- Interrupt Break-Event                                      IBE   [Capable]
|- Core Cycles                                                         [Capable]
|- Instructions Retired                                                [Capable]
|- Reference Cycles                                                    [Capable]
|- Last Level Cache References                                         [Capable]
|- Global Time Stamp Counter                                           [Missing]
|- Data Fabric Performance Counter                                     [Capable]
|- Core Performance Counter                                            [Capable]
|- Processor Performance Control                                _PCT   [Missing]
|- Performance Supported States                                 _PSS   [Missing]
|- Performance Present Capabilities                             _PPC   [Missing]
|- Continuous Performance Control                               _CPC   [Missing]

Power, Current & Thermal
|- Temperature Offset:Junction                                 TjMax [ 49:  0 C]
|- CPPC Energy Preference                                        EPP   <      0>
|- Digital Thermal Sensor                                        DTS   [Capable]
|- Power Limit Notification                                      PLN   [Missing]
|- Package Thermal Management                                    PTM   [Missing]
|- Thermal Monitor 1                                             TTP   [ Enable]
|- Thermal Monitor 2                                             HTC   [ Enable]
|- Thermal Design Power                                          TDP   [Missing]
   |- Minimum Power                                              Min   [Missing]
   |- Maximum Power                                              Max   [Missing]
|- Thermal Design Power                                      Package   [Disable]
   |- Power Limit                                                PL1   [    0 W]
   |- Time Window                                                TW1   [   0 ns]
   |- Power Limit                                                PL2   [    0 W]
   |- Time Window                                                TW2   [   0 ns]
|- Thermal Design Power                                         Core   [Disable]
   |- Power Limit                                                PL1   [    0 W]
   |- Time Window                                                TW1   [   0 ns]
|- Thermal Design Power                                       Uncore   [Disable]
   |- Power Limit                                                PL1   [    0 W]
   |- Time Window                                                TW1   [   0 ns]
|- Thermal Design Power                                         DRAM   [Disable]
   |- Power Limit                                                PL1   [    0 W]
   |- Time Window                                                TW1   [   0 ns]
|- Thermal Design Power                                     Platform   [Disable]
   |- Power Limit                                                PL1   [    0 W]
   |- Time Window                                                TW1   [   0 ns]
   |- Power Limit                                                PL2   [    0 W]
   |- Time Window                                                TW2   [   0 ns]
|- Package Power Tracking                                        PPT   [Missing]
|- Electrical Design Current                                     EDC   [Missing]
|- Thermal Design Current                                        TDC   [Missing]
|- Core Thermal Point
|- Package Thermal Point
   |- Thermal Monitor Trip                                     Limit   [  115 C]
   |- HTC Temperature Limit                                    Limit   [    0 C]
   |- HTC Temperature Hysteresis                           Threshold   [    0 C]
|- Units
   |- Power                                               watt   [      Missing]
   |- Energy                                             joule   [  0.000015259]
   |- Window                                            second   [  0.000976562]

0 replies

cyring · 2024-04-19T05:20:34Z

cyring
Apr 19, 2024
Maintainer

Thanks.
Looking at CPB ratio and PL1, PL2, it appears that changing the address as below is a regression on HSMP

#define SMU_HSMP_CMD		0x3b10934

0 replies

cyring · 2024-04-19T05:55:23Z

cyring
Apr 19, 2024
Maintainer

Reading once again the commit, it concerns the future Zen5/EPYC
Redhat boot issue on Genoa.
Nothing else found

0 replies

cyring · 2024-09-28T03:19:48Z

cyring
Sep 28, 2024
Maintainer

@garceri Hello.

No clue about the TjMax of Genoa 9004 series.
Can you tell which max temperature your EPYC can reach ?
A corefreq-cli -C output of stressed processor to its limits should be fine.

EDIT: you may also find thermal limits into the BMC screens and/or the CPU cooler datasheet.

0 replies

cyring · 2024-09-29T07:37:47Z

cyring
Sep 29, 2024
Maintainer

Source: BIOS / BMC / Bundle Firmware for MBD-H13SSL-N : IPMI Firmware / BIOS Release Notes

Per AMD thermal design requirement, change Tclt,limit value to 95

0 replies

[AMD][Genoa] Unexpected HSMP values on Epyc 9274F (#discussioncomment-9476811) #487

garceri Mar 5, 2024

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