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PianoTile.qsf
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PianoTile.qsf
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# -------------------------------------------------------------------------- #
#
# Copyright (C) 2016 Intel Corporation. All rights reserved.
# Your use of Intel Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Intel Program License
# Subscription Agreement, the Intel Quartus Prime License Agreement,
# the Intel MegaCore Function License Agreement, or other
# applicable license agreement, including, without limitation,
# that your use is for the sole purpose of programming logic
# devices manufactured by Intel and sold by Intel or its
# authorized distributors. Please refer to the applicable
# agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus Prime
# Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition
# Date created = 11:34:34 December 26, 2020
#
# -------------------------------------------------------------------------- #
#
# Notes:
#
# 1) The default values for assignments are stored in the file:
# PianoTile_assignment_defaults.qdf
# If this file doesn't exist, see file:
# assignment_defaults.qdf
#
# 2) Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus Prime software
# and any changes you make may be lost or overwritten.
#
# -------------------------------------------------------------------------- #
set_global_assignment -name FAMILY "Cyclone V"
set_global_assignment -name DEVICE 5CEBA4F23C7
set_global_assignment -name TOP_LEVEL_ENTITY PianoTile
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 16.1.0
set_global_assignment -name PROJECT_CREATION_TIME_DATE "11:34:34 DECEMBER 26, 2020"
set_global_assignment -name LAST_QUARTUS_VERSION "16.1.0 Lite Edition"
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 256
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_location_assignment PIN_W9 -to btn3
set_location_assignment PIN_M7 -to btn2
set_location_assignment PIN_M6 -to btn1
set_location_assignment PIN_M9 -to clk
set_location_assignment PIN_P22 -to rst
set_location_assignment PIN_U22 -to sevenDP1[6]
set_location_assignment PIN_AA17 -to sevenDP1[5]
set_location_assignment PIN_AB18 -to sevenDP1[4]
set_location_assignment PIN_AA18 -to sevenDP1[3]
set_location_assignment PIN_AA19 -to sevenDP1[2]
set_location_assignment PIN_AB20 -to sevenDP1[1]
set_location_assignment PIN_AA20 -to sevenDP1[0]
set_location_assignment PIN_AB21 -to sevenDP2[6]
set_location_assignment PIN_AB22 -to sevenDP2[5]
set_location_assignment PIN_V14 -to sevenDP2[4]
set_location_assignment PIN_Y14 -to sevenDP2[3]
set_location_assignment PIN_AA10 -to sevenDP2[2]
set_location_assignment PIN_AB17 -to sevenDP2[1]
set_location_assignment PIN_Y19 -to sevenDP2[0]
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
set_global_assignment -name VERILOG_FILE Dot.v
set_global_assignment -name VERILOG_FILE check.v
set_global_assignment -name VERILOG_FILE PianoTile.v
set_global_assignment -name VERILOG_FILE SevenDP.v
set_location_assignment PIN_L8 -to dot_col[15]
set_location_assignment PIN_J13 -to dot_col[14]
set_location_assignment PIN_C15 -to dot_col[13]
set_location_assignment PIN_B13 -to dot_col[12]
set_location_assignment PIN_E16 -to dot_col[11]
set_location_assignment PIN_G17 -to dot_col[10]
set_location_assignment PIN_J18 -to dot_col[9]
set_location_assignment PIN_A14 -to dot_col[8]
set_location_assignment PIN_G11 -to dot_col[7]
set_location_assignment PIN_H10 -to dot_col[6]
set_location_assignment PIN_H14 -to dot_col[5]
set_location_assignment PIN_G18 -to dot_col[4]
set_location_assignment PIN_A15 -to dot_col[3]
set_location_assignment PIN_H18 -to dot_col[2]
set_location_assignment PIN_J19 -to dot_col[1]
set_location_assignment PIN_J11 -to dot_col[0]
set_location_assignment PIN_D13 -to dot_row[7]
set_location_assignment PIN_A13 -to dot_row[6]
set_location_assignment PIN_B12 -to dot_row[5]
set_location_assignment PIN_C13 -to dot_row[4]
set_location_assignment PIN_E14 -to dot_row[3]
set_location_assignment PIN_A12 -to dot_row[2]
set_location_assignment PIN_B15 -to dot_row[1]
set_location_assignment PIN_E15 -to dot_row[0]
set_location_assignment PIN_AA22 -to sevenDP0[6]
set_location_assignment PIN_Y21 -to sevenDP0[5]
set_location_assignment PIN_Y22 -to sevenDP0[4]
set_location_assignment PIN_W21 -to sevenDP0[3]
set_location_assignment PIN_W22 -to sevenDP0[2]
set_location_assignment PIN_V21 -to sevenDP0[1]
set_location_assignment PIN_U21 -to sevenDP0[0]
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top