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Hi there,
I am having the same issue from JLCPCB -->
.It seems that there are buried or blind via in your file and we don’t make PCB that with buried or blind via.
Is there any fix for these buried or blind via, can we fix it manually?
Hi @algocrypto,
I merged the new vias into master. No more buried vias, although there might be issue with the annular ring width still (I plan to tackle that next, having the algorithm to pick-up track width and clearance from the board settings).
This is how it looks for a 8-layer widing (the inner layers might still have some cosmetics issues where the end of the coil is not properly trimmed down, but that should not impact functionality)
Blind/buried vias are a significant price increase compared to through vias, would be nice to have the option if possible
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