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sirius8_a1.qsf
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sirius8_a1.qsf
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# -------------------------------------------------------------------------- #
#
# Copyright (C) 2020 Intel Corporation. All rights reserved.
# Your use of Intel Corporation's design tools, logic functions
# and other software and tools, and any partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Intel Program License
# Subscription Agreement, the Intel Quartus Prime License Agreement,
# the Intel FPGA IP License Agreement, or other applicable license
# agreement, including, without limitation, that your use is for
# the sole purpose of programming logic devices manufactured by
# Intel and sold by Intel or its authorized distributors. Please
# refer to the applicable agreement for further details, at
# https://fpgasoftware.intel.com/eula.
#
# -------------------------------------------------------------------------- #
#
# Quartus Prime
# Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
# Date created = 17:18:57 March 06, 2021
#
# -------------------------------------------------------------------------- #
#
# Notes:
#
# 1) The default values for assignments are stored in the file:
# sirius8_a1_assignment_defaults.qdf
# If this file doesn't exist, see file:
# assignment_defaults.qdf
#
# 2) Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus Prime software
# and any changes you make may be lost or overwritten.
#
# -------------------------------------------------------------------------- #
set_global_assignment -name FAMILY "Cyclone IV E"
set_global_assignment -name DEVICE EP4CE6E22C8
set_global_assignment -name TOP_LEVEL_ENTITY sirius8
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 20.1.1
set_global_assignment -name PROJECT_CREATION_TIME_DATE "17:46:06 MARCH 06, 2021"
set_global_assignment -name LAST_QUARTUS_VERSION "20.1.1 Lite Edition"
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
set_global_assignment -name NOMINAL_CORE_SUPPLY_VOLTAGE 1.2V
set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)"
set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation
set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_timing_analysis
set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_formal_verification
set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_timing
set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_symbol
set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_signal_integrity
set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_boundary_scan
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
set_location_assignment PIN_84 -to E[3]
set_location_assignment PIN_85 -to E[2]
set_location_assignment PIN_86 -to E[1]
set_location_assignment PIN_87 -to E[0]
set_location_assignment PIN_91 -to D[3]
set_location_assignment PIN_90 -to D[2]
set_location_assignment PIN_89 -to D[1]
set_location_assignment PIN_88 -to D[0]
set_location_assignment PIN_133 -to dig[0]
set_location_assignment PIN_135 -to dig[1]
set_location_assignment PIN_136 -to dig[2]
set_location_assignment PIN_137 -to dig[3]
set_location_assignment PIN_128 -to seg[0]
set_location_assignment PIN_121 -to seg[1]
set_location_assignment PIN_125 -to seg[2]
set_location_assignment PIN_129 -to seg[3]
set_location_assignment PIN_132 -to seg[4]
set_location_assignment PIN_126 -to seg[5]
set_location_assignment PIN_124 -to seg[6]
set_location_assignment PIN_127 -to seg[7]
set_location_assignment PIN_23 -to clk
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -entity ep4ce6e22c8 -section_id Top
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -entity ep4ce6e22c8 -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -entity ep4ce6e22c8 -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -entity ep4ce6e22c8 -section_id Top
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_global_assignment -name VHDL_FILE mar.vhd
set_global_assignment -name VHDL_FILE register.vhd
set_global_assignment -name VHDL_FILE tristate_buffer.vhd
set_global_assignment -name VHDL_FILE binary_decoder.vhd
set_global_assignment -name VHDL_FILE instruction_decoder.vhdl
set_global_assignment -name VHDL_FILE stack.vhd
set_global_assignment -name VHDL_FILE ram.vhd
set_global_assignment -name VHDL_FILE mux.vhd
set_global_assignment -name VHDL_FILE fulladder_1b.vhd
set_global_assignment -name VHDL_FILE fulladder.vhd
set_global_assignment -name VHDL_FILE flipflop_d.vhd
set_global_assignment -name VHDL_FILE dis4d_3461bs.vhd
set_global_assignment -name VHDL_FILE counter_8b.vhd
set_global_assignment -name VHDL_FILE counter_4b.vhd
set_global_assignment -name VHDL_FILE alu.vhd
set_global_assignment -name VHDL_FILE sirius8.vhd
set_global_assignment -name VHDL_FILE mux32_8.vhd
set_global_assignment -name VHDL_FILE port.vhd
set_global_assignment -name VHDL_FILE clock.vhd
set_global_assignment -name VHDL_FILE bootloader.vhd
set_global_assignment -name VHDL_FILE ir.vhd
set_global_assignment -name VHDL_FILE register_mask.vhd
set_global_assignment -name VHDL_FILE binary_encoder8_3.vhd
set_global_assignment -name VHDL_FILE binary_decoder3_8.vhd
set_location_assignment PIN_25 -to Hard_reset
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top