v0.6

• New features:
  • Support clash-prelude-0.10
  • Pattern matching on CLaSH.Sized.Vector's :> is now supported
  • Unroll "definitions" of the following primitives: fold, dfold, foldr

v0.5.9

• New features:
  • Use new verilog backend which outputs Verilog-2001 instead of Verilog-2005: generated Verilog is now accepted by Altera/Quartus
• Fixes bugs:
  • --systemverilog switch incorrectly generates verilog code instead of systemverilog code
  • Incorrect SV primitive for CLaSH.Prelude.Testbench.assert'
  • Incorrect SV primitive for CLaSH.Sized.Vec.index_int
  • Sometimes created incorrect nested generate statements in SV backend

v0.5.8

• New features:
  • Support for copying string literals from Haskell to generated code
  • Support clash-prelude-0.9
  • Size at below which functions are always inlined is configurable, run with -clash-inline-below=N to set the size limit to N
  • Collect and copy data-files
• Fixes bugs:
  • Signals declared twice when not using a clock-generating component #60
  • This piece of code eat up all CPU when generating verilog #62
  • Can not operate "shiftR" on Int #63
  • Fail to generate verilog when using "quot" and "div" on Index #64

v0.4.1

• Fixes bugs:
  • Treat BlackBox expressions as declarations when DC args. #37
  • Don't inline recursive closed bindings

v0.4

• New features:
  • Support for clash-prelude 0.6
• Fixes bugs:
  • Ambiguous type: 'std_logic_vector' or 'std_ulogic_vector' #33
  • clash-ghc ignores "-package-db" flag #35

v0.3.3

• Fixes bugs:
  • Compile with GHC 7.8.3 #31

v0.3.2

clash-lib

• Fixes bugs:
  • VHDL array constant ambiguous #18
  • Exception: can't create selector #24
  • Calls to vhdlTypeMark don't result to inclusion of VHDL type in types.vhdl #28

clash-ghc

• Fixes bugs:
  • Type synonym improperly expanded #17
  • BlackBox for Signed maxBound and minBound generate incorrect VHDL. #19
  • Generate failure code in the VHDL for recSelError #23

v0.3.1

Add changelog and up version number