Quartus SystemVerilog: error on input port typedef and net type

[DigitalBrains1]

Quartus Prime Lite 23.1.1 complains about a syntax error if you have a custom type in an input port and also specify wire:

module f
    ( // Inputs
      input wire IntelTypes_topEntity_types::Tuple2 c$arg


      // Outputs
    , output IntelTypes_topEntity_types::Tuple2 result
    );

gives

Error (10170): Verilog HDL syntax error at f.sv(8) near text: "::";  expecting ")". Check for and fix any syntax errors that appear immediately before or at the specified keyword. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number.
Error (10112): Ignored design unit "f" at f.sv(6) due to previous errors

If you remove the word wire in the input port declaration, it compiles (not making any recommendations here, I don't know enough SystemVerilog).

The original code works fine in Questa or Vivado.

The reproducer for this code:

IntelTypes.hs

module IntelTypes where

import Clash.Prelude

topEntity ::
  (Unsigned 8, Unsigned 8) ->
  (Unsigned 8, Unsigned 8)
topEntity = f
{-# OPAQUE topEntity #-}

f :: a -> a
f = id
{-# NOINLINE f #-}

[DigitalBrains1]

I'd like to note I already used the -fclash-hdlsyn Quartus flag when translating the reproducer to HDL, so it should have already adjusted for Quartus quirks if we had such adjustments.

Also, I'm using GHC 9.8.2.