From c8620e349724eb584b45d384d5871d1b323b2a70 Mon Sep 17 00:00:00 2001 From: Ed Baker Date: Mon, 8 Jul 2024 15:37:52 -0700 Subject: [PATCH 1/4] readme: Add CounterHTOff Notice Update README.md to include additional notes regarding the availability of CounterHTOff. This attribute is not published on ICL, ICX, and subsequent platforms. --- README.md | 12 +++++++++--- 1 file changed, 9 insertions(+), 3 deletions(-) diff --git a/README.md b/README.md index e7188ccb..0207e6d9 100644 --- a/README.md +++ b/README.md @@ -190,10 +190,16 @@ In some cases, this field will contain a more detailed description of what is co This field lists the fixed (`PERF_FIXED_CTRX`) or programmable (`IA32_PMCX`) counters that can be used to count the event. ### CounterHTOff -This field lists the counters where this event can be sampled when Intel (R) Hyper-Threading Technology (Intel (R) HT Technology) is -disabled. When Intel (R) HT Technology is disabled, some processor cores gain access to the programmable counters of the second +This field lists the counters where this event can be sampled when Intel® Hyper-Threading Technology (Intel® HT Technology) is +disabled. When Intel® HT Technology is disabled, some processor cores gain access to the programmable counters of the second thread, making a total of eight programmable counters available. The additional counters will be numbered 4,5,6,7. Fixed counter -behavior remains unaffected. +behavior remains unaffected. [^counterhtoff_footnote] + +:warning: Starting with ICL, ICX, and subsequent platforms, `CounterHTOff` is not applicable and is accordingly not +published in event files. Downstream tools should reference `Counter` whether Intel® HT Technology is enabled or +disabled. + +[^counterhtoff_footnote]: See **NOTE** in the Intel SDM section, "Architectural Performance Monitoring Version 3". ### PEBScounters This field is only relevant to PEBS events. It lists the counters where the event can be sampled when it is programmed as a PEBS event. From 2121e276e3e5a23549798d178345b5f715ba7d70 Mon Sep 17 00:00:00 2001 From: Ed Baker Date: Tue, 9 Jul 2024 09:16:36 -0700 Subject: [PATCH 2/4] readme: Update registered instances This commit unifies markdown on `®` usage. Instances of `Intel©` were replaced with `Intel®`. `(R) was also replaced with the HTML entity. --- README.md | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/README.md b/README.md index 0207e6d9..c332b042 100644 --- a/README.md +++ b/README.md @@ -120,13 +120,13 @@ In this repository there are three, related, metrics file types. | Files | Description and Additional Information | | ---| --- | -| `TMA_Metrics.xlsx`
`Atom_TMA.xlsx`
`E-core_TMA_Metrics.xlsx`| Official TMA releases. Performance architect maintained metrics for Top-down analysis methodology.
- [Ahmad Yasin, "A Top-Down method for performance analysis and counters architecture", ISPASS 2014](https://doi.org/10.1109/ISPASS.2014.6844459)
- [Intel© VTune™ Top-down Microarchitecture Analysis Method](https://www.intel.com/content/www/us/en/docs/vtune-profiler/cookbook/2024-0/top-down-microarchitecture-analysis-method.html) | +| `TMA_Metrics.xlsx`
`Atom_TMA.xlsx`
`E-core_TMA_Metrics.xlsx`| Official TMA releases. Performance architect maintained metrics for Top-down analysis methodology.
- [Ahmad Yasin, "A Top-Down method for performance analysis and counters architecture", ISPASS 2014](https://doi.org/10.1109/ISPASS.2014.6844459)
- [Intel® VTune™ Top-down Microarchitecture Analysis Method](https://www.intel.com/content/www/us/en/docs/vtune-profiler/cookbook/2024-0/top-down-microarchitecture-analysis-method.html) | | `TMA_Metrics.csv`
`TMA_Metrics-full.csv`
`E-core_TMA_Metrics.csv`
`Atom_TMA.csv`| CSV formatted metrics from the above `.xlsx` spreadsheets. | | `{platform}/metrics` | JSON formatted metrics intended for performance monitoring tools. Full description in the previous documentation section. | # Performance Monitoring Events -This package contains performance monitoring event lists for Intel processors, as well as a mapping file +This package contains performance monitoring event lists for Intel® processors, as well as a mapping file to help match event lists to processor Family/Model/Stepping codes. Event lists are available in JSON (.json) format. @@ -163,7 +163,7 @@ Other files in this package are ALL RIGHTS RESERVED. Below is a list of the fields/headers in the event files and a description of how SW tools should interpret these values. A particular event list from this package may not contain all the fields described below. For more detailed information of the Performance monitoring unit please refer to chapters 18 and 19 -of Intel (R) 64 and IA-32 Architectures Software Developer's Manual Volume 3B: System Programming Guide, Part 2. +of Intel® 64 and IA-32 Architectures Software Developer's Manual Volume 3B: System Programming Guide, Part 2. https://www.intel.com/content/www/us/en/developer/articles/technical/intel-sdm.html @@ -199,7 +199,7 @@ behavior remains unaffected. [^counterhtoff_footnote] published in event files. Downstream tools should reference `Counter` whether Intel® HT Technology is enabled or disabled. -[^counterhtoff_footnote]: See **NOTE** in the Intel SDM section, "Architectural Performance Monitoring Version 3". +[^counterhtoff_footnote]: See **NOTE** in the Intel® SDM section, "Architectural Performance Monitoring Version 3". ### PEBScounters This field is only relevant to PEBS events. It lists the counters where the event can be sampled when it is programmed as a PEBS event. @@ -268,7 +268,7 @@ generated precisely upon completion of the instruction or operation that causes | 32 | Precise distribution is supported on fixed counter 0 for this event. | | 0,1 | Precise distribution is supported on programmable counters 0 and 1 for this event. | -[^pdist_footnote]: Excerpt from Intel SDM section, "PDist: Precise Distribution". +[^pdist_footnote]: Excerpt from Intel® SDM section, "PDist: Precise Distribution". ### Precise The core event attribute `Precise` indicates if an event can collect a precise eventing instruction @@ -286,7 +286,7 @@ The Reduced Skid mechanism mitigates the "skid" problem by providing an early in the counter is about to overflow, allowing the machine to more precisely trap on the instruction that actually caused the counter overflow thus greatly reducing skid. [^reduced_skid_footnote] -[^reduced_skid_footnote]: Excerpt from Intel SDM section, "Reduced Skid PEBS". +[^reduced_skid_footnote]: Excerpt from Intel® SDM section, "Reduced Skid PEBS". ### PRECISE_STORE A '1' in this field means the event uses the Precise Store feature and Bit 3 and bit 63 in IA32_PEBS_ENABLE MSR must be set @@ -333,8 +333,8 @@ Please use SNR core event files. The EHL events folder is populated with a copy ## For additional information * Event documentation https://perfmon-events.intel.com/ -* Intel© Platform Analysis Technology https://www.intel.com/content/www/us/en/developer/topic-technology/platform-analysis-technology/overview.html -* Monitoring Integrated Memory Controller Requests in the 2nd, 3rd, 4th, 5th, 6th generation Intel© Core™ processors https://www.intel.com/content/www/us/en/developer/articles/technical/monitoring-integrated-memory-controller-requests-in-the-2nd-3rd-and-4th-generation-intel.html +* Intel® Platform Analysis Technology https://www.intel.com/content/www/us/en/developer/topic-technology/platform-analysis-technology/overview.html +* Monitoring Integrated Memory Controller Requests in the 2nd, 3rd, 4th, 5th, 6th generation Intel® Core™ processors https://www.intel.com/content/www/us/en/developer/articles/technical/monitoring-integrated-memory-controller-requests-in-the-2nd-3rd-and-4th-generation-intel.html # How to Contribute ## Metrics From 57a45733465da27d15d62f66e1caffa5651512a8 Mon Sep 17 00:00:00 2001 From: Ed Baker Date: Tue, 9 Jul 2024 09:28:26 -0700 Subject: [PATCH 3/4] readme: Replace tabs and fix trailing spaces Replace tabs with spaces in markdown. Combine multiline command sequences into one block. Remove trailing spaces. --- README.md | 42 ++++++++++++++++++++++-------------------- 1 file changed, 22 insertions(+), 20 deletions(-) diff --git a/README.md b/README.md index c332b042..7950c969 100644 --- a/README.md +++ b/README.md @@ -74,37 +74,39 @@ The perf script in /scripts will take the metrics.json file and convert that gen 1. How to build with perf - 1.1 Create working directory - - `mkdir perfmon-metrics` - - `cd perfmon-metrics` - - 1.2 Clone the metric repository into the working directory - + 1.1 Create working directory + + ``` + mkdir perfmon-metrics + cd perfmon-metrics + ``` + + 1.2 Clone the metric repository into the working directory + `git clone https://github.com/intel/perfmon.git` - + 1.3 Clone a copy of linux source code - + `git clone https://github.com/torvalds/linux.git` - + 1.4 Copy the ICX metric file in the linux perf codebase - + `cp ICX/metrics/perf/icx_metrics_perf.json /tools/perf/pmu-events/arch/x86/icelakex/` - - 1.5 Build linux perf (Note: You will need to install dependencies) - - `cd /tools/perf` - - `make` + + 1.5 Build linux perf (Note: You will need to install dependencies) + + ``` + cd /tools/perf + make + ``` 2. Local copy of perf will now be built with the new metrics for Icelake systems - `./perf stat -M -a -- ` + `./perf stat -M -a -- ` 2. Examples - `./perf stat -M cpu_utilization_percent -a -- ./mlc` + `./perf stat -M cpu_utilization_percent -a -- ./mlc` #### Known Issues From 3938e3be1e062044dc991af461ee50ae0f78781b Mon Sep 17 00:00:00 2001 From: Ed Baker Date: Thu, 11 Jul 2024 13:54:46 -0700 Subject: [PATCH 4/4] readme: Add VTune footnote Add required VTune footnote. --- README.md | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/README.md b/README.md index 7950c969..00085174 100644 --- a/README.md +++ b/README.md @@ -122,10 +122,12 @@ In this repository there are three, related, metrics file types. | Files | Description and Additional Information | | ---| --- | -| `TMA_Metrics.xlsx`
`Atom_TMA.xlsx`
`E-core_TMA_Metrics.xlsx`| Official TMA releases. Performance architect maintained metrics for Top-down analysis methodology.
- [Ahmad Yasin, "A Top-Down method for performance analysis and counters architecture", ISPASS 2014](https://doi.org/10.1109/ISPASS.2014.6844459)
- [Intel® VTune™ Top-down Microarchitecture Analysis Method](https://www.intel.com/content/www/us/en/docs/vtune-profiler/cookbook/2024-0/top-down-microarchitecture-analysis-method.html) | +| `TMA_Metrics.xlsx`
`Atom_TMA.xlsx`
`E-core_TMA_Metrics.xlsx`| Official TMA releases. Performance architect maintained metrics for Top-down analysis methodology.
- [Ahmad Yasin, "A Top-Down method for performance analysis and counters architecture", ISPASS 2014](https://doi.org/10.1109/ISPASS.2014.6844459)
- [Intel® VTune™ Top-down Microarchitecture Analysis Method](https://www.intel.com/content/www/us/en/docs/vtune-profiler/cookbook/2024-0/top-down-microarchitecture-analysis-method.html) [^vtune_footnote] | | `TMA_Metrics.csv`
`TMA_Metrics-full.csv`
`E-core_TMA_Metrics.csv`
`Atom_TMA.csv`| CSV formatted metrics from the above `.xlsx` spreadsheets. | | `{platform}/metrics` | JSON formatted metrics intended for performance monitoring tools. Full description in the previous documentation section. | +[^vtune_footnote]: Intel, the Intel logo and VTune are trademarks of Intel Corporation or its subsidiaries. + # Performance Monitoring Events This package contains performance monitoring event lists for Intel® processors, as well as a mapping file