core_common.svh and synthesis

[mosfet-sapeon]

I'm having trouble actually compiling this core. The core issue (heh) seems to be the pattern:

// Verilog-2001 Module definition:
module core_csrs (
  ...
  input       [XL:0] csr_wdata        , // Data to be written to a CSR
  ...
);

// Common core parameters and constants
`include "core_common.svh"

In the above, "core_common.svh" contains the definition of the localparam "XL". This would have worked in Verilog-1995 standard where inputs and outputs were declared after the module definition but it does not work in Verilog-2001 syntax. You can't just move the "`include "core_common.svh" line before the module definition either as localparams must be placed after module definition.

Suggestion is to make these parameters actual parameters and pass them down instead of localparams.