From 0ee115d61d775fffe3ec40924d1deef9784f5853 Mon Sep 17 00:00:00 2001 From: Jake Carter Date: Mon, 9 Oct 2023 09:19:43 -0500 Subject: [PATCH] fix(Examples): Fix RTC and RTC_Backup Example ERFO Initialization for MAX32655 (#760) --- Examples/MAX32655/RTC/main.c | 22 ++-------------------- Examples/MAX32655/RTC_Backup/main.c | 20 +++----------------- 2 files changed, 5 insertions(+), 37 deletions(-) diff --git a/Examples/MAX32655/RTC/main.c b/Examples/MAX32655/RTC/main.c index b9d424b366..3a80d6f186 100644 --- a/Examples/MAX32655/RTC/main.c +++ b/Examples/MAX32655/RTC/main.c @@ -162,28 +162,10 @@ void printTime() int main(void) { int rtcTrim; - volatile int i; - - /* Delay to prevent bricks */ - for (i = 0; i < 0xFFFFFF; i++) {} - - /* Set the system clock to the 32 MHz clock for the RTC trim */ - /* Enable 32 MHz clock if not already enabled */ - if (!(MXC_GCR->clkctrl & MXC_F_GCR_CLKCTRL_ERFO_RDY)) { - /* Power VREGO_D */ - MXC_SIMO->vrego_d = (0x3c << MXC_F_SIMO_VREGO_D_VSETD_POS); - while (!(MXC_SIMO->buck_out_ready & MXC_F_SIMO_BUCK_OUT_READY_BUCKOUTRDYD)) {} - - /* Restore btleldoctrl setting */ - MXC_GCR->btleldoctrl = 0x3055; - while (!(MXC_SIMO->buck_out_ready & MXC_F_SIMO_BUCK_OUT_READY_BUCKOUTRDYD)) {} - - /* Enable 32Mhz oscillator */ - MXC_GCR->clkctrl |= MXC_F_GCR_CLKCTRL_ERFO_EN; - while (!(MXC_GCR->clkctrl & MXC_F_GCR_CLKCTRL_ERFO_RDY)) {} - } + MXC_Delay(MXC_DELAY_SEC(2)); // Delay to give debugger a window to connect /* Switch the system clock to the 32 MHz oscillator */ + MXC_SYS_ClockSourceEnable(MXC_SYS_CLOCK_ERFO); MXC_SYS_Clock_Select(MXC_SYS_CLOCK_ERFO); MXC_SYS_SetClockDiv(MXC_SYS_CLOCK_DIV_1); SystemCoreClockUpdate(); diff --git a/Examples/MAX32655/RTC_Backup/main.c b/Examples/MAX32655/RTC_Backup/main.c index 9835efb0b9..bbc8d51f04 100644 --- a/Examples/MAX32655/RTC_Backup/main.c +++ b/Examples/MAX32655/RTC_Backup/main.c @@ -125,24 +125,10 @@ void printTime() int configureRTC() { int rtcTrim; - volatile int i; + MXC_Delay(MXC_DELAY_SEC(2)); // Delay to give debugger a window to connect - for (i = 0; i < 0xFFFFFF; i++) {} - // Prevent bricks - - if (!(MXC_GCR->clkctrl & - MXC_F_GCR_CLKCTRL_ERFO_RDY)) { // Enable 32Mhz clock if not already enabled - MXC_SIMO->vrego_d = (0x3c << MXC_F_SIMO_VREGO_D_VSETD_POS); // Power VREGO_D - while (!(MXC_SIMO->buck_out_ready & MXC_F_SIMO_BUCK_OUT_READY_BUCKOUTRDYD)) {} - - MXC_GCR->btleldoctrl = 0x3055; // Restore btleldoctrl setting - while (!(MXC_SIMO->buck_out_ready & MXC_F_SIMO_BUCK_OUT_READY_BUCKOUTRDYD)) {} - - MXC_GCR->clkctrl |= MXC_F_GCR_CLKCTRL_ERFO_EN; // Enable 32Mhz oscillator - while (!(MXC_GCR->clkctrl & MXC_F_GCR_CLKCTRL_ERFO_RDY)) {} - } - - MXC_SYS_Clock_Select(MXC_SYS_CLOCK_ERFO); // Set 32MHz clock as system clock + /* Switch the system clock to the 32 MHz oscillator */ + MXC_SYS_ClockSourceEnable(MXC_SYS_CLOCK_ERFO); MXC_SYS_SetClockDiv(MXC_SYS_CLOCK_DIV_1); SystemCoreClockUpdate();