the SLOT_WIDTH in axi_i2s_adi

[sz-CHEN]

When I set the SLOT_WIDTH as 32, error comes.


The Error reported by Vivado:
[Synth 8-549] port width mismatch for port 'out_data': port width = 24, actual width = 32 [axi_i2s_adi.vhd":236]

The code statements in axi_i2s_adi.vhd are as follows:

...
signal tx_data				: std_logic_vector(SLOT_WIDTH - 1 downto 0);
...
	streaming_dma_tx_gen: if DMA_TYPE = 0 and HAS_TX = 1 generate
		tx_fifo : entity axi_streaming_dma_tx_fifo
			generic map(
				RAM_ADDR_WIDTH => FIFO_AWIDTH,
				FIFO_DWIDTH => 24
			)
			port map(
				clk => s_axi_aclk,
				resetn => s_axi_aresetn,
				fifo_reset => tx_fifo_reset,
				enable => tx_enable,

				s_axis_aclk => s_axis_aclk,
				s_axis_tready => s_axis_tready,
				s_axis_tdata => s_axis_tdata(31 downto 8),
				s_axis_tlast => s_axis_tlast,
				s_axis_tvalid => s_axis_tvalid,

				out_stb => tx_stb,
				out_ack => tx_ack,
				out_data => tx_data
			);
	end generate;
...

The width of outdata is defined by FIFO_DWIDTH which always is 24, however, of the tx_data, is defined by SLOT_WIDTH.
According to the tcl file, the SLOT_WIDTH can be 16, 20, 24, 32. Is it right that just fit tx_data witdh to out_data like the s_axis_tdata does?