iis2mdc_regs.yaml

---
map_name: IIS2MDC
default_register_bitwidth: 8

registers:

  OFFSET_X_REG_L:
    adr: 0x45
    reset_val: 0x00
    brief: 16bit two's complement offset to compensate environmental/board effects.
    fields:
      VAL:
        bits: 0-7
        access: [R, W]

  OFFSET_X_REG_H:
    adr: 0x46
    reset_val: 0x00
    brief: 16bit two's complement offset to compensate environmental/board effects.
    fields:
      VAL:
        bits: 0-7
        access: [R, W]

  OFFSET_Y_REG_L:
    adr: 0x47
    reset_val: 0x00
    brief: 16bit two's complement offset to compensate environmental/board effects.
    fields:
      VAL:
        bits: 0-7
        access: [R, W]

  OFFSET_Y_REG_H:
    adr: 0x48
    reset_val: 0x00
    brief: 16bit two's complement offset to compensate environmental/board effects.
    fields:
      VAL:
        bits: 0-7
        access: [R, W]

  OFFSET_Z_REG_L:
    adr: 0x49
    reset_val: 0x00
    brief: 16bit two's complement offset to compensate environmental/board effects.
    fields:
      VAL:
        bits: 0-7
        access: [R, W]

  OFFSET_Z_REG_H:
    adr: 0x4A
    reset_val: 0x00
    brief: 16bit two's complement offset to compensate environmental/board effects.
    fields:
      VAL:
        bits: 0-7
        access: [R, W]

  WHO_AM_I:
    adr: 0x4F
    reset_val: 0x40
    brief: Device identification register.
    fields:
      ID:
        bits: 0-7
        access: [R]

  CFG_REG_A:
    adr: 0x60
    reset_val: 0x03
    fields:
      MD:
        bits: 0-1
        access: [R, W]
        brief: Operating mode selection.
        enum:
          CONTINUOUS:
            val: 0x00
            brief: Continuous-acqusition mode.
          SINGLE:
            val: 0x01
            brief: Single-acquisition mode.
          IDLE:
            val: 0x03
            brief: Idle mode. SPI/I2C are active (default).
      ODR:
        bits: 2-3
        access: [R, W]
        brief: Output data rate selection.
        enum:
          10HZ:
            val: 0x00
            brief: 10Hz (default).
          20HZ:
            val: 0x01
            brief: 20Hz.
          50HZ:
            val: 0x02
            brief: 50Hz.
          100HZ:
            val: 0x03
            brief: 100Hz.
      LP:
        bits: 4
        access: [R, W]
        brief: Set to 1 to enable low-power mode.
      SOFT_RST:
        bits: 5
        access: [R, W]
        brief: Set to 1 to reset. Flash memory content is not affected.
      REBOOT:
        bits: 6
        access: [R, W]
        brief: Set to 1 to reboot memory content
      COMP_TEMP_EN:
        bits: 7
        access: [R, W]
        brief: Temperature compensation enable. This bit MUST be set to 1 for correct
          operation.

  CFG_REG_B:
    adr: 0x61
    reset_val: 0x00
    fields:
      LPF:
        bits: 0
        access: [R, W]
        brief: "Low-pass filter enable. BW: ODR/2 when LP=0, BW: ODR/4 when LP=1"
      OFF_CANC:
        bits: 1
        access: [R, W]
        brief: Set to 1 to enable offset cancellation in single mode only.
      SET_PULSE_FREQ:
        bits: 2
        access: [R, W]
        brief: Selects the frequency of the set pulse (default 0).
        enum:
          63_ODR:
            val: 0x00
            brief: Set pulse released every 63 ODR.
          PD:
            val: 0x01
            brief: Set pulse released only at power on, after PD condition
      INT_ON_DATAOFF:
        bits: 3
        brief: If 1, the interrupt block recognition checks data after the hard-iron correction to discover the interrupt (default 0)
      OFF_CANC_ONE_SHOT:
        bits: 4
        access: [R, W]
        brief: Enables offset cancellation in single measurement mode. The OFF_CANC bit must be set to 1 when enabling offset cancellation in single measurement mode (default 0)

  CFG_REG_C:
    adr: 0x62
    reset_val: 0x00
    always_write:
      bits: [2,7]
      val: 0x0
    fields:
      DRDY_ON_PIN:
        bits: 0
        access: [R, W]
        brief: "If 1, the data-ready signal (Zyxda bit in STATUS_REG (67h)) is driven on the INT/DRDY pin. The INT/DRDY pin is configured in push-pull output mode. Default value: 0"
      SELF_TEST:
        bits: 1
        access: [R, W]
        brief: "Self-test enable. Default value: 0"
      BLE:
        bits: 3
        access: [R, W]
        brief: "Big/little endian data selection. Default value: 0"
      BDU:
        bits: 4
        access: [R, W]
        brief: "Block data update. If enable, grants that high and low parts of the data belong to the same sample. Default value: 0"
      I2C_DIS:
        bits: 5
        access: [R, W]
        brief: "Disable I2C interface. If 1, I2C interface is inhibited and only SPI can be used. Default value: 0"
      INT_ON_PIN:
        bits: 6
        access: [R, W]
        brief: "If 1, the INTERRUPT signal (INT bit in INT_SOURCE_REG (64h)) is driven on the INT/DRDY pin. The INT/DRDY pin is configured in push-pull output mode. Default value: 0"

  INT_CTRL_REG:
    adr: 0x63
    reset_val: 0xE0
    always_write:
      bits: 3-4
      val: 0x0
    fields:
      INT_EN:
        bits: 0
        access: [R, W]
        brief: "Interrupt enable. Default value: 0"
      INT_MODE:
        bits: 1
        access: [R, W]
        brief: "Configures interrupt in pulsed or latched configuration"
        enum:
          PULSED:
            val: 0x00
            brief: Pulsed (default)
          LATCHED:
            val: 0x01
            brief: Latched
      INT_POLARITY:
        bits: 2
        access: [R, W]
        brief: "Interrupt active-high/low. Default value: 0"
        enum:
          ACTIVE_LOW:
            val: 0x00
            brief: Active low (default)
          ACTIVE_HIGH:
            val: 0x01
            brief: Active high
      INT_Z_EN:
        bits: 5
        access: [R, W]
        brief: "Enable interrupt generation on Z axis. Default value: 1"
      INT_Y_EN:
        bits: 6
        access: [R, W]
        brief: "Enable interrupt generation on Y axis. Default value: 1"
      INT_X_EN:
        bits: 7
        access: [R, W]
        brief: "Enable interrupt generation on X axis. Default value: 1"

  INT_SOURCE_REG:
    adr: 0x64
    doc: |
      Interrupt source register.
      @note when interrupt is latched, rall bits are reset upon reading this register.
    fields:
      INT_ACTIVE:
        bits: 0
        access: [R]
        brief: "Interrupt active. Default value: 0"
      MROI:
        bits: 1
        access: [R]
        brief: "Magnetic data overrun. Default value: 0"
      NTH_Z:
        bits: 2
        access: [R]
        brief: "Z negative threshold. Default value: 0"
      NTH_Y:
        bits: 3
        access: [R]
        brief: "Y negative threshold. Default value: 0"
      NTH_X:
        bits: 4
        access: [R]
        brief: "X negative threshold. Default value: 0"
      PTH_Z:
        bits: 5
        access: [R]
        brief: "Z positive threshold. Default value: 0"
      PTH_Y:
        bits: 6
        access: [R]
        brief: "Y positive threshold. Default value: 0"
      PTH_X:
        bits: 7
        access: [R]
        brief: "X positive threshold. Default value: 0"

  INT_THS_L_REG:
    adr: 0x65
    reset_val: 0x00
    brief: This register contains the least significant bits of the threshold value chosen for the interrupt. Threshold is common for all axes, and both positive and negative sides.
    fields:
      THS:
        bits: 0-7
        access: [R, W]
        brief: "Threshold value. Default value: 0"

  INT_THS_H_REG:
    adr: 0x66
    reset_val: 0x00
    brief: This register contains the most significant bits of the threshold value chosen for the interrupt. Threshold is common for all axes, and both positive and negative sides.
    fields:
      THS:
        bits: 0-7
        access: [R, W]
        brief: "Threshold value. Default value: 0"

  STATUS_REG:
    adr: 0x67
    fields:
      XDA:
        bits: 0
        access: [R]
        brief: "X-axis new data available. Default value: 0"
      YDA:
        bits: 1
        access: [R]
        brief: "Y-axis new data available. Default value: 0"
      ZDA:
        bits: 2
        access: [R]
        brief: "Z-axis new data available. Default value: 0"
      ZYXDA:
        bits: 3
        access: [R]
        brief: "X, Y and Z-axis new data available. Default value: 0"
      XOR:
        bits: 4
        access: [R]
        brief: "X-axis data overrun. Default value: 0"
      YOR:
        bits: 5
        access: [R]
        brief: "Y-axis data overrun. Default value: 0"
      ZOR:
        bits: 6
        access: [R]
        brief: "Z-axis data overrun. Default value: 0"
      ZYXOR:
        bits: 7
        access: [R]
        brief: "X, Y and Z-axis data overrun. Default value: 0"

  OUTX_L_REG:
    adr: 0x68
    fields:
      OUTX:
        bits: 0-7
        access: [R]

  OUTX_H_REG:
    adr: 0x69
    fields:
      OUTX:
        bits: 0-7
        access: [R]

  OUTY_L_REG:
    adr: 0x6A
    fields:
      OUTY:
        bits: 0-7
        access: [R]

  OUTY_H_REG:
    adr: 0x6B
    fields:
      OUTY:
        bits: 0-7
        access: [R]

  OUTZ_L_REG:
    adr: 0x6C
    fields:
      OUTZ:
        bits: 0-7
        access: [R]

  OUTZ_H_REG:
    adr: 0x6D
    fields:
      OUTZ:
        bits: 0-7
        access: [R]

  TEMP_OUT_L_REG:
    adr: 0x6E
    fields:
      TEMP:
        bits: 0-7
        access: [R]

  TEMP_OUT_H_REG:
    adr: 0x6F
    fields:
      TEMP:
        bits: 0-7
        access: [R]