From ba98a6e075529cd754275b47242ca5a5da1d0586 Mon Sep 17 00:00:00 2001
From: Ziliang Guo <zguo2@wisc.edu>
Date: Tue, 19 Apr 2016 14:24:27 -0500
Subject: [PATCH] A variety of data width fixes. Use more wildcards in
 sensitivity lists to shut up warnings in Vivado.

---
 src/verilog/rtl/decode/reg_field_encoder.v | 2 +-
 src/verilog/rtl/fpga/compute_unit_fpga.v   | 2 +-
 src/verilog/rtl/issue/mem_wait.v           | 9 +--------
 src/verilog/rtl/rfa/rfa.v                  | 4 ++--
 4 files changed, 5 insertions(+), 12 deletions(-)

diff --git a/src/verilog/rtl/decode/reg_field_encoder.v b/src/verilog/rtl/decode/reg_field_encoder.v
index 33f1e28..60370f5 100644
--- a/src/verilog/rtl/decode/reg_field_encoder.v
+++ b/src/verilog/rtl/decode/reg_field_encoder.v
@@ -38,7 +38,7 @@ assign sgpr_address = sgpr_base + in[6:0];
 assign vgpr_address = vgpr_base + in[7:0];
 assign negative_constant = (~{4'b0,in[5:0]}) + 10'b1;
 
-always @(in or sgpr_base or vgpr_base)
+always @(*)
 begin
   casex(in)
     //invalid operand
diff --git a/src/verilog/rtl/fpga/compute_unit_fpga.v b/src/verilog/rtl/fpga/compute_unit_fpga.v
index 197eabe..07a9871 100644
--- a/src/verilog/rtl/fpga/compute_unit_fpga.v
+++ b/src/verilog/rtl/fpga/compute_unit_fpga.v
@@ -636,7 +636,7 @@ always @( posedge S_AXI_ACLK ) begin
           singleVectorWrData28 <= S_AXI_WDATA;
           singleVectorWrDataMask <= singleVectorWrDataMask |   64'h0000000010000000;
         end
-        9'h511D: begin
+        9'h11D: begin
           singleVectorWrData29 <= S_AXI_WDATA;
           singleVectorWrDataMask <= singleVectorWrDataMask |   64'h0000000020000000;
         end
diff --git a/src/verilog/rtl/issue/mem_wait.v b/src/verilog/rtl/issue/mem_wait.v
index 5148ef1..d3ad568 100644
--- a/src/verilog/rtl/issue/mem_wait.v
+++ b/src/verilog/rtl/issue/mem_wait.v
@@ -24,20 +24,13 @@ decoder_6b_40b_en issue_value_decoder
 );
 
 
-decoder_6b_40b_en retire_sgpr_value_decoder
+decoder_6b_40b_en retire_lsu_value_decoder
 (
     .addr_in(lsu_done_wfid),
     .out(decoded_lsu_retire_value),
     .en(lsu_done)
 );
 
-decoder_6b_40b_en retire_vgpr_value_decoder
-(
-    .addr_in(f_vgpr_lsu_wr_done_wfid),
-    .out(decoded_vgpr_retire_value),
-    .en(f_vgpr_lsu_wr_done)
-);
-
 dff_set_en_rst mem_wait[`WF_PER_CU-1:0]
 (
     .q(mem_waiting_wf),
diff --git a/src/verilog/rtl/rfa/rfa.v b/src/verilog/rtl/rfa/rfa.v
index 76f2dfd..84c1999 100644
--- a/src/verilog/rtl/rfa/rfa.v
+++ b/src/verilog/rtl/rfa/rfa.v
@@ -54,11 +54,11 @@ module rfa(/*AUTOARG*/
 
    // If lsu requests writes, it bypasses the priority encoder
    // but if salu request writes, it bypasses both
-   assign entry_valid = salu_req ? {'b0, simf3_queue_entry_valid, simf2_queue_entry_valid,
+   assign entry_valid = salu_req ? {8'd0, simf3_queue_entry_valid, simf2_queue_entry_valid,
                          simf1_queue_entry_valid, simf0_queue_entry_valid,
                          simd3_queue_entry_valid, simd2_queue_entry_valid,
                          simd1_queue_entry_valid, simd0_queue_entry_valid} &
-			{16{~salu_req}}:{'b0, simf3_queue_entry_valid, simf2_queue_entry_valid,
+			{16{~salu_req}}:{8'd0, simf3_queue_entry_valid, simf2_queue_entry_valid,
                          simf1_queue_entry_valid, simf0_queue_entry_valid,
                          simd3_queue_entry_valid, simd2_queue_entry_valid,
                          simd1_queue_entry_valid, simd0_queue_entry_valid} &