From 440860bcfbe7f3963e3b8876d06d561e33462029 Mon Sep 17 00:00:00 2001 From: d1duarte Date: Mon, 25 Apr 2016 16:43:09 +0100 Subject: [PATCH] Corrected the 'v_RCP_F32' instruction so it produces the correct results. Connected the signals 'start' and 'done' of the fpu correctly for the 'v_RCP_F32' instruction. The instruction is now producing the correct result. --- src/verilog/rtl/simf/simf_alu.v | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/verilog/rtl/simf/simf_alu.v b/src/verilog/rtl/simf/simf_alu.v index 0ecb84e..c65d8ea 100644 --- a/src/verilog/rtl/simf/simf_alu.v +++ b/src/verilog/rtl/simf/simf_alu.v @@ -156,8 +156,8 @@ module simf_alu end {1'b1, `ALU_VOP1_FORMAT, 12'h02A} : //V_RCP_F32 - VIN begin - alu_done <= 1'b1; - fpu_start_i <= 1'b0; + alu_done <= fpu_ready_o; + fpu_start_i <= alu_start; fpu_op_i <= 3'b011; fpu_opa_i <= 32'h3f80_0000; fpu_opb_i <= final_source1_data;