GHDL VHDL -> Yosys code for BLOCKRAM (used as ROM)

[PPlinux]

Dear,

do you know how to define the use of 512 word 16bit RAM (preloaded during FPGA power on and acting as ROM)
in vhdl (using GHDL & Yosys) for FPGA e.g. ICE40 ?

Hoping to receive some help, I remain,

Patrick Pelgrims