Rewrite testbenches and simulation packages for VHDL-2008 only.

[Paebbels]

The simulation packages are not (and will not) be supported by Xilinx ISE, because of a bad shared variable implementation. We will drop the support for VHDL-93 testbenches. We still hope for a correct VHDL-2008 in future Xilinx Vivado Simulator releases.

Work Items:

1. Remove files:
   • sim_random.v93.vhdl
   • sim_simulation.v93.vhdl
   • sim_unprotected.v93.vhdl
2. alter and review *.files files.
3. remove wrappers
   • sim_random.v08.vhdl - remove commented wrappers ("procedural interface")
   • sim_simulation.v08.vhdl
4. Rename globalSimulationStatus to globalSimStatus or SimStatus
   As all global VHDL-93 variables are removed (prefixed with global_) the name can be chooses shorter.
   • alter sim_simulation.v08.vhdl and sim_waveform.vhdl
   • review all testbenches
5. Write a PoC.arith.prng testbench for Xilinx ISE Simulator without simulation package helper usage, so the Python infrastructure can still be tested with this testbench.
   • Manual assertion counting
   • Manual report generation [PASSED | FAILED]