feat: fpga allow setting of custom SYNTH_DEFINES and frontend (language) to yosys synthesis for FPGA target

[dlmiles]

      - name: FPGA bitstream for TT ASIC Sim (ICE40UP5K)
        uses: TinyTapeout/tt-gds-action/fpga/ice40up5k@tt09
        with:
          SYNTH_DEFINES: FOO ANOTHER=42 THIRD=abcdef
          YOSYS_FRONTEND: verilog

SYNTH_DEFINES is based on OpenLane parameter of a similar name with a similar meaning. It should allow a string to set zero or more items passed through to yosys command line like -DFOO -DANOTHER=32 -DTHIRD=abcdef

The YOSYS_FRONTEND is a single word that is used with -f verilog or similar. Maybe some feedback from yosys team is useful to understand how this would be handled. It is unclear to me what the available allowed options area or will be in the future and how to make it future proof (if SV and VHDL were available as well).

This would pass through these options onto the command line at https://github.com/TinyTapeout/tt-support-tools/blob/tt09/project.py#L801

As things stand a very simple project might work with a shared single HDL github project, but providing controls in this area should allow the designer flexibility over targetting FPGA at the same time. The config.tcl/config/json exists to manage this for ASIC.