forked from YosysHQ/yosys
-
Notifications
You must be signed in to change notification settings - Fork 41
/
CHANGELOG
1544 lines (1331 loc) · 58.6 KB
/
CHANGELOG
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937
938
939
940
941
942
943
944
945
946
947
948
949
950
951
952
953
954
955
956
957
958
959
960
961
962
963
964
965
966
967
968
969
970
971
972
973
974
975
976
977
978
979
980
981
982
983
984
985
986
987
988
989
990
991
992
993
994
995
996
997
998
999
1000
List of major changes and improvements between releases
=======================================================
Yosys 0.48 .. Yosys 0.49-dev
--------------------------
Yosys 0.47 .. Yosys 0.48
--------------------------
* Various
- Removed "read_ilang" deprecated pass.
- Enhanced boxing features in the experimental "abc_new" command.
- Added new Tcl methods for design inspection.
- Added clock enable inference to "dfflibmap".
- Added a Han-Carlson and Sklansky option for $lcu mapping.
* New commands and options
- Added "-nopeepopt" option to "clk2fflogic" pass.
- Added "-liberty" and "-dont_use" options to "clockgate" pass.
- Added "-ignore_buses" option to "read_liberty" pass.
- Added "-dont_map" option to "techmap" pass.
- Added "-selected" option to "write_json" pass.
- Added "wrapcell" command for creating wrapper modules
around selected cells.
- Added "portarcs" command for deriving propagation timing arcs.
- Added "setenv" command for setting environment variables.
* Gowin support
- Added "-family" option to "synth_gowin" pass.
- Cell definitions split by family.
* Verific support
- Improved blackbox support.
Yosys 0.46 .. Yosys 0.47
--------------------------
* Various
- Added cxxopts library for handling command line arguments.
- Added docs generation from cells help output.
* New commands and options
- Added "-json" option to "synth_xilinx" pass.
- Added "-derive_luts" option to "cellmatch" pass.
- Added "t:@<name>" syntax to "select" pass.
- Added "-list-mod" option to "select" pass.
- Removed deprecated "qwp" pass.
* Verific support
- Initial state handling for VHDL assertions.
Yosys 0.45 .. Yosys 0.46
--------------------------
* Various
- Added new "functional backend" infrastructure with three example
backends (C++, SMTLIB and Rosette).
- Added new coarse-grain buffer cell type "$buf" to RTLIL.
- Added "-y" command line option to execute a Python script with
libyosys available as a built-in module.
- Added support for casting to type in Verilog frontend.
* New commands and options
- Added "clockgate" pass for automatic clock gating cell insertion.
- Added "bufnorm" experimental pass to convert design into
buffered-normalized form.
- Added experimental "aiger2" and "xaiger2" backends, and an
experimental "abc_new" command
- Added "-force-detailed-loop-check" option to "check" pass.
- Added "-unit_delay" option to "read_liberty" pass.
* Verific support
- Added left and right bound properties to wires when using
specific VHDL types.
Yosys 0.44 .. Yosys 0.45
--------------------------
* Various
- Added cell types help messages.
* New back-ends
- Added initial NG-Ultra support. ( synth_nanoxplore )
Yosys 0.43 .. Yosys 0.44
--------------------------
* Various
- Added ENABLE_LTO compile option to enable link time
optimizations.
- Build support for Haiku OS.
* New commands and options
- Added "keep_hierarchy" pass to add attribute with
same name to modules based on cost.
- Added options "-noopt","-bloat" and "-check_cost" to
"test_cell" pass.
* New back-ends
- Added initial PolarFire support. ( synth_microchip )
Yosys 0.42 .. Yosys 0.43
--------------------------
* Various
- C++ compiler with C++17 support is required.
- Support for IO liberty files for verification.
- Limit padding from shiftadd for "peepopt" pass.
* Verific support
- Support building Yosys with various Verific library
configurations. Can be built now without YosysHQ
specific patch and extension library.
Yosys 0.41 .. Yosys 0.42
--------------------------
* New commands and options
- Added "box_derive" pass to derive box modules.
- Added option "assert-mod-count" to "select" pass.
- Added option "-header","-push" and "-pop" to "log" pass.
* Intel support
- Dropped Quartus support in "synth_intel_alm" pass.
Yosys 0.40 .. Yosys 0.41
--------------------------
* New commands and options
- Added "cellmatch" pass for picking out standard cells automatically.
* Various
- Extended the experimental incremental JSON API to allow arbitrary
smtlib subexpressions.
- Added support for using ABCs library merging when providing multiple
liberty files.
* Verific support
- Expose library name as module attribute.
Yosys 0.39 .. Yosys 0.40
--------------------------
* New commands and options
- Added option "-vhdl2019" to "read" and "verific" pass.
* Various
- Major documentation overhaul.
- Added port statistics to "stat" command.
- Added new formatting features to cxxrtl backend.
* Verific support
- Added better support for VHDL constants import.
- Added support for VHDL 2009.
Yosys 0.38 .. Yosys 0.39
--------------------------
* New commands and options
- Added option "-extra-map" to "synth" pass.
- Added option "-dont_use" to "dfflibmap" pass.
- Added option "-href" to "show" command.
- Added option "-noscopeinfo" to "flatten" pass.
- Added option "-scopename" to "flatten" pass.
* SystemVerilog
- Added support for packed multidimensional arrays.
* Various
- Added "$scopeinfo" cells to preserve information about
the hierarchy during flattening.
- Added sequential area output to "stat -liberty".
- Added ability to record/replay diagnostics in cxxrtl backend.
* Verific support
- Added attributes to module instantiation.
Yosys 0.37 .. Yosys 0.38
--------------------------
* New commands and options
- Added option "-tech" to "opt_lut" pass.
- Added option "-nokeep_prints" to "hierarchy" pass.
- Added option "-nolower" to "async2sync" and "clk2fflogic" pass.
- Added option "-lower" to "chformal" pass.
* Various
- Added $check cell to represent assertions with messages.
- Allow capturing $print cell output in CXXRTL.
- Added API to overwrite existing pass from plugin.
- Follow the XDG Base Directory Specification for storing history files.
- Without a known top module, derive all deferred modules (hierarchy pass).
- Detect and error out on combinational loops in write_aiger.
* Verific support
- Added option "-no-split-complex-ports" to "verific -import".
Yosys 0.36 .. Yosys 0.37
--------------------------
* New commands and options
- Added option "-nodisplay" to read_verilog.
* SystemVerilog
- Correct hierarchical path names for structs and unions.
* Various
- Print hierarchy for failed assertions in "sim" pass.
- Add "--present-only" option to "yosys-witness" to omit unused signals.
- Implement a generic record/replay interface for CXXRTL.
- Improved readability of emitted code with "write_verilog".
Yosys 0.35 .. Yosys 0.36
--------------------------
* New commands and options
- Added option "--" to pass arguments down to tcl when using -c option.
- Added ability on MacOS and Windows to pass options after arguments on cli.
- Added option "-cmp2softlogic" to synth_lattice.
- Added option "-lowpower" to "booth" pass.
* QuickLogic support
- Added "K6N10f" support.
- Added "-nodsp", "-nocarry", "-nobram" and "-bramtypes" options to
"synth_quicklogic" pass.
- Added "ql_bram_merge" pass to merge 18K BRAM cells into TDP36K.
- Added "ql_bram_types" pass to change TDP36K depending on configuration.
- Added "ql_dsp_io_regs" pass to update QL_DSP2 depending on configuration.
- Added "ql_dsp_macc" pass to infer multiplier-accumulator DSP cells.
- Added "ql_dsp_simd" pass to merge DSP pairs to operate in SIMD mode.
* ECP5,iCE40 and Gowin support
- Enabled abc9 by default, added "-noabc9" option to disable.
* MachXO3 support
- Quality of results improvements.
- Enabled "booth" pass by default for it in "synth_lattice".
* Various
- Improved "peepopt" by adding shiftadd pattern support.
- Added "--incremental" mode to smtbmc.
Yosys 0.34 .. Yosys 0.35
--------------------------
* Various
- Improvements on "peepopt" shiftmul matcher.
- Improvements on "ram_style" attributes handling.
* Verific support
- Improved static elaboration for VHDL and mixed HDL designs.
- Expose "hdlname" attribute with original module name.
- Expose "architecture" attribute with VHDL architecture name.
Yosys 0.33 .. Yosys 0.34
--------------------------
* New commands and options
- Added option "-assert" to "sim" pass.
- Added option "-noinitstate" to "sim" pass.
- Added option "-dont_use" to "abc" pass.
- Added "dft_tag" pass to create tagging logic for data flow tracking.
- Added "future" pass to resolve future sampled value functions.
- Added "booth" pass to map $mul cells to Booth multipliers.
- Added option "-booth" to "synth" pass.
* SystemVerilog
- Added support for assignments within expressions, e.g., `x[y++] = z;` or
`x = (y *= 2) - 1;`.
* Verific support
- "src" attribute contain full location info.
- module parameters are kept after import.
- accurate access order semantics in memory inference.
- better "bind" support for mixed language projects.
* Various
- "show" command displays dot instead of box for wire aliases.
Yosys 0.32 .. Yosys 0.33
--------------------------
* Various
- Added "$print" cell, produced by "$display" and "$write"
Verilog tasks.
- Added "$print" cell handling in CXXRTL.
* Lattice FPGA support
- Added generic "synth_lattice" pass (for now MachXO2/XO3/XO3D)
- Removed "synth_machxo2" pass
- Pass "ecp5_gsr" renamed to "lattice_gsr"
- "synth_machxo2" equivalent is "synth_lattice -family xo2"
Yosys 0.31 .. Yosys 0.32
--------------------------
* Verific support
- Added sub option "-lib" to reading commands for VHDL and
SystemVerilog, that will later import all units/modules from
marked files as blackboxes.
* Various
- Added support for $lt, $le, $gt, $ge to the code generating AIGs.
Yosys 0.30 .. Yosys 0.31
--------------------------
* New commands and options
- Added option "-lsbidx" to "write_edif" pass.
* Various
- Added support for $divfloor operator to cxxrtl backend.
- dfflegalize: allow setting mince and minsrst args from scratchpad.
Yosys 0.29 .. Yosys 0.30
--------------------------
* New commands and options
- Added "recover_names" pass to recover names post-mapping.
* Gowin support
- Added remaining primitives blackboxes.
* Various
- "show -colorattr" will now color the cells, wires, and
connection arrows.
- "show -viewer none" will not execute viewer.
Yosys 0.28 .. Yosys 0.29
--------------------------
* New commands and options
- Added "synthprop" pass for synthesizable properties.
* Verific support
- Handle conditions on clocked concurrent assertions in unclocked
procedural contexts.
* Verilog
- Fix const eval of unbased unsized constants.
- Handling of attributes for struct / union variables.
Yosys 0.27 .. Yosys 0.28
--------------------------
* Verilog
- Out of bounds checking for struct/union members.
* Verific support
- Fix enum_values support and signed attribute values.
* ECP5 support
- Added "synth_ecp5 -iopad"
* MachXO2 support
- Added "synth_machxo2 -ccu2"
Yosys 0.26 .. Yosys 0.27
--------------------------
* New commands and options
- Added option "-make_assert" to "equiv_make" pass.
- Added option "-coverenable" to "chformal" pass.
* Verilog
- Resolve package types in interfaces.
- Handle range offsets in packed arrays within packed structs.
- Support for data and array queries on struct/union item expressions.
* GateMate support
- Enable register initialization.
Yosys 0.25 .. Yosys 0.26
--------------------------
* New commands and options
- Added "bwmuxmap" pass to replace $bwmux cells with equivalent logic.
- Added "xprop" experimental pass for formal x propagation.
- Added "splitcells" pass to split up multi-bit cells.
- Added "viz" pass to visualize data flow graph.
- Added option "-make_cover" to "miter" pass.
- Added option "-noparallelcase" to "write_verilog" pass.
- Added option "-chain" to "insbuf" pass.
- Added options "-hierarchy" and "-assume" to "formalff" pass.
- Added options "-append" and "-summary" to "sim" pass.
- Added option "-ywmap" to "write_btor" pass.
- Added option "-ignore-self-reset" to "fsm_detect" pass.
* Verilog
- Support for struct members of union type.
- Support for struct member package types.
* Various
- Added Yosys witness (.yw) cosimulation.
- GCC 4.8 is deprecated, compiler with full C++11 support is required.
Yosys 0.24 .. Yosys 0.25
--------------------------
* Verific support
- Respect "noblackbox" attribute for modules.
* Various
- Documentation is hosted at https://yosyshq.readthedocs.io/projects/yosys/en/latest/
Yosys 0.23 .. Yosys 0.24
--------------------------
* New commands and options
- Added option "-set-def-formal" to "sat" pass.
- Added option "-s" to "tee" command.
* Verilog
- Support for module-scoped identifiers referring to tasks and functions.
- Support for arrays with swapped ranges within structs.
* Verific support
- Support for importing verilog configurations per name.
- "verific -set-XXXXX" commands are now able to set severity to all messages
of certain type (errors, warnings, infos and comments)
* Various
- TCL shell support (use "yosys -C")
- Added FABulous eFPGA frontend
Yosys 0.22 .. Yosys 0.23
--------------------------
* New commands and options
- Added option "-cross" to "miter" pass.
- Added option "-nocheck" to "equiv_opt" pass.
* Formal Verification
- yosys-smtbmc: Added "--detect-loops" option for checking if states are
unique in temporal induction counter examples.
* Verific support
- Added support for reading Liberty files using Verific library.
(Optinally enabled with ENABLE_VERIFIC_LIBERTY)
- Added option "-cells" to "verific -import" enabling import of
all cells from verific design.
* Various
- MinGW build (Windows) plugin support.
- Added YOSYS_ABORT_ON_LOG_ERROR environment variable for debugging.
Setting it to 1 causes abort() to be called when Yosys terminates with an
error message.
Yosys 0.21 .. Yosys 0.22
--------------------------
* Verific support
- Added support for here-document for "verific" command (for reading
source files).
- Added support for reading EDIF files using Verific library.
(Optinally enabled with ENABLE_VERIFIC_EDIF)
* Various
- Added tech specific utilization to "stat" json.
Yosys 0.20 .. Yosys 0.21
--------------------------
* New commands and options
- Added "formalff" pass - transforms FFs for formal verification
- Added option "-formal" to "memory_map" pass
- Added option "-witness" to "rename" - give public names to all signals
present in yosys witness traces
- Added option "-hdlname" to "sim" pass - preserves hiearachy when writing
simulation output for a flattened design
- Addded option "-scramble-name" to "rename" pass
* Formal Verification
- Added $anyinit cell to directly represent FFs with an unconstrained
initialization value. These can be generated by the new formalff pass.
- New JSON based yosys witness format for formal verification traces.
- yosys-smtbmc: Reading and writing of yosys witness traces.
- write_smt2: Emit inline metadata to support yosys witness trace.
- yosys-witness is a new tool to inspect and convert yosys witness traces.
- write_aiger: Option to write a map file for yosys witness trace
conversion.
- yosys-witness: Conversion from and to AIGER witness traces.
* Verific support
- Filename re-writing support for "verific" pass.
* Various
- ABC performance improvements
- Filename re-writing added for "show -lib".
* SmartFusion2 support
- Added $alu support
- Added SYSRESET and XTLOSC cells
- Compatible now with LiberoSoc flow
Yosys 0.19 .. Yosys 0.20
--------------------------
* New commands and options
- Added option "-wb" to "read_liberty" pass
* Various
- Added support for $modfloor operator to cxxrtl backend
- Support build on OpenBSD
- Fixed smt2 backend use of $shift/$shiftx with negative shift amounts,
which affects bit/part-select assignments with a dynamic index. Shift
operators were not affected.
* Verific support
- Proper import of port ranges into Yosys, may result in reversed
bit-order of top-level ports for some synthesis flows.
Yosys 0.18 .. Yosys 0.19
--------------------------
* New commands and options
- Added option "-rom-only" to "memory_libmap" pass
- Added option "-smtcheck" to "hierarchy" pass
- Added option "-keepdc" to "memory_libmap" pass
- Added option "-suffix" to "rename" pass
- Added "gatemate_foldinv" pass
* Formal Verification
- Added support for $pos cell in btor backend
- Added the "smtlib2_module" and "smtlib2_comb_expr" attributes
* GateMate support
- Added LUT tree mapping
* Verific support
- Added option "-pp" to "verific -import"
Yosys 0.17 .. Yosys 0.18
--------------------------
* Various
- Migrated most flows to use memory_libmap based memory inference
* New commands and options
- Added "memory_libmap" pass
- Added "memory_bmux2rom" pass - converts muxes to ROMs
- Added "memory_dff -no-rw-check"
- Added "opt_ffinv" pass - push inverters through FFs
- Added "proc_rom" pass - convert switches to ROMs
- Added "proc -norom" option - will omit the proc_rom pass
- Added option "-no-rw-check" to synth passes
- Added "synth_ice40 -spram" option for automatic inference of SB_SPRAM256KA
- Added options "-nobram" and "-nolutram" to synth_machxo2 pass
* Formal Verification
- Fixed the signedness of $past's return value to be the same as the
argument's instead of always unsigned.
* Verilog
- Fixed an issue where simplifying case statements by removing unreachable
cases could result in the wrong signedness being used for comparison with
the remaining cases
- Fixed size and signedness computation for expressions containing array
querying functions
- Fixed size and signedness computation of functions used in ternary
expressions or case item expressions
* Verific support
- Proper file location for readmem commands
- Added "-vlog-libext" option to specify search extension for libraries
Yosys 0.16 .. Yosys 0.17
--------------------------
* New commands and options
- Added "write_jny" ( JSON netlist metadata format )
- Added "tribuf -formal"
* SystemVerilog
- Fixed automatic `nosync` inference for local variables in `always_comb`
procedures not applying to nested blocks and blocks in functions
Yosys 0.15 .. Yosys 0.16
--------------------------
* Various
- Added BTOR2 witness file co-simulation.
- Simulation calls external vcd2fst for VCD conversion.
- Added fst2tb pass - generates testbench for the circuit using
the given top-level module and simulus signal from FST file.
- yosys-smtbmc: Option to keep going after failed assertions in BMC mode
* Verific support
- Import modules in alphabetic (reproducable) order.
Yosys 0.14 .. Yosys 0.15
--------------------------
* Various
- clk2fflogic: nice names for autogenerated signals
- simulation include support for all flip-flop types.
- Added AIGER witness file co-simulation.
* Verilog
- Fixed evaluation of constant functions with variables or arguments with
reversed dimensions
- Fixed elaboration of dynamic range assignments where the vector is
reversed or is not zero-indexed
- Added frontend support for time scale delay values (e.g., `#1ns`)
* SystemVerilog
- Added support for accessing whole sub-structures in expressions
* New commands and options
- Added glift command, used to create gate-level information flow tracking
(GLIFT) models by the "constructive mapping" approach
* Verific support
- Ability to override default parser mode for verific -f command.
Yosys 0.13 .. Yosys 0.14
--------------------------
* Various
- Added $bmux and $demux cells and related optimization patterns.
* New commands and options
- Added "bmuxmap" and "dmuxmap" passes
- Added "-fst" option to "sim" pass for writing FST files
- Added "-r", "-scope", "-start", "-stop", "-at", "-sim", "-sim-gate",
"-sim-gold" options to "sim" pass for co-simulation
* Anlogic support
- Added support for BRAMs
Yosys 0.12 .. Yosys 0.13
--------------------------
* Various
- Use "read" command to parse HDL files from Yosys command-line
- Added "yosys -r <topmodule>" command line option
- write_verilog: dump zero width sigspecs correctly
* SystemVerilog
- Fixed regression preventing the use array querying functions in case
expressions and case item expressions
- Fixed static size casts inadvertently limiting the result width of binary
operations
- Fixed static size casts ignoring expression signedness
- Fixed static size casts not extending unbased unsized literals
- Added automatic `nosync` inference for local variables in `always_comb`
procedures which are always assigned before they are used to avoid errant
latch inference
* New commands and options
- Added "clean_zerowidth" pass
* Verific support
- Add YOSYS to the implicitly defined verilog macros in verific
Yosys 0.11 .. Yosys 0.12
--------------------------
* Various
- Added iopadmap native support for negative-polarity output enable
- ABC update
* SystemVerilog
- Support parameters using struct as a wiretype
* New commands and options
- Added "-genlib" option to "abc" pass
- Added "sta" very crude static timing analysis pass
* Verific support
- Fixed memory block size in import
* New back-ends
- Added support for GateMate FPGA from Cologne Chip AG
* Intel ALM support
- Added preliminary Arria V support
Yosys 0.10 .. Yosys 0.11
--------------------------
* Various
- Added $aldff and $aldffe (flip-flops with async load) cells
* SystemVerilog
- Fixed an issue which prevented writing directly to a memory word via a
connection to an output port
- Fixed an issue which prevented unbased unsized literals (e.g., `'1`) from
filling the width of a cell input
- Fixed an issue where connecting a slice covering the entirety of a signed
signal to a cell input would cause a failed assertion
* Verific support
- Importer support for {PRIM,WIDE_OPER}_DFF
- Importer support for PRIM_BUFIF1
- Option to use Verific without VHDL support
- Importer support for {PRIM,WIDE_OPER}_DLATCH{,RS}
- Added -cfg option for getting/setting Verific runtime flags
Yosys 0.9 .. Yosys 0.10
--------------------------
* Various
- Added automatic gzip decompression for frontends
- Added $_NMUX_ cell type
- Added automatic gzip compression (based on filename extension) for backends
- Improve attribute and parameter encoding in JSON to avoid ambiguities between
bit vectors and strings containing [01xz]*
- Improvements in pmgen: subpattern and recursive matches
- Support explicit FIRRTL properties
- Improvements in pmgen: slices, choices, define, generate
- Added "_TECHMAP_WIREINIT_*_" parameter and "_TECHMAP_REMOVEINIT_*_" wire for "techmap" pass
- Added +/mul2dsp.v for decomposing wide multipliers to custom-sized ones
- Added new frontend: rpc
- Added --version and -version as aliases for -V
- Improve yosys-smtbmc "solver not found" handling
- Improved support of $readmem[hb] Memory Content File inclusion
- Added CXXRTL backend
- Use YosysHQ/abc instead of upstream berkeley-abc/abc
- Added WASI platform support.
- Added extmodule support to firrtl backend
- Added $divfloor and $modfloor cells
- Added $adffe, $dffsre, $sdff, $sdffe, $sdffce, $adlatch cells
- Added "_TECHMAP_CELLNAME_" parameter for "techmap" pass
- Added firrtl backend support for generic parameters in blackbox components
- Added $meminit_v2 cells (with support for write mask)
- Added $mem_v2, $memrd_v2, $memwr_v2, with the following features:
- write priority masks, per write/write port pair
- transparency and undefined collision behavior masks, per read/write port pair
- read port reset and initialization
- wide ports (accessing a naturally aligned power-of-two number of memory cells)
* New commands and options
- Added "write_xaiger" backend
- Added "read_xaiger"
- Added "abc9" pass for timing-aware techmapping (experimental, FPGA only)
- Added "synth -abc9" (experimental)
- Added "script -scriptwire"
- Added "clkbufmap" pass
- Added "extractinv" pass and "invertible_pin" attribute
- Added "proc_clean -quiet"
- Added "proc_prune" pass
- Added "stat -tech cmos"
- Added "opt_share" pass, run as part of "opt -full"
- Added "-match-init" option to "dff2dffs" pass
- Added "equiv_opt -multiclock"
- Added "techmap_autopurge" support to techmap
- Added "add -mod <modname[s]>"
- Added "paramap" pass
- Added "portlist" command
- Added "check -mapped"
- Added "check -allow-tbuf"
- Added "autoname" pass
- Added "write_verilog -extmem"
- Added "opt_mem" pass
- Added "scratchpad" pass
- Added "fminit" pass
- Added "opt_lut_ins" pass
- Added "logger" pass
- Added "show -nobg"
- Added "exec" command
- Added "design -delete"
- Added "design -push-copy"
- Added "qbfsat" command
- Added "select -unset"
- Added "dfflegalize" pass
- Removed "opt_expr -clkinv" option, made it the default
- Added "proc -nomux
- Merged "dffsr2dff", "opt_rmdff", "dff2dffe", "dff2dffs", "peepopt.dffmux" passes into a new "opt_dff" pass
* SystemVerilog
- Added checking of always block types (always_comb, always_latch and always_ff)
- Added support for wildcard port connections (.*)
- Added support for enum typedefs
- Added support for structs and packed unions.
- Allow constant function calls in for loops and generate if and case
- Added support for static cast
- Added support for logic typed parameters
- Fixed generate scoping issues
- Added support for real-valued parameters
- Allow localparams in constant functions
- Module name scope support
- Support recursive functions using ternary expressions
- Extended support for integer types
- Support for parameters without default values
- Allow globals in one file to depend on globals in another
- Added support for: *=, /=, %=, <<=, >>=, <<<=, >>>=
- Added support for parsing the 'bind' construct
- support declaration in procedural for initialization
- support declaration in generate for initialization
- Support wand and wor of data types
* Verific support
- Added "verific -L"
- Add Verific SVA support for "always" properties
- Add Verific support for SVA nexttime properties
- Improve handling of verific primitives in "verific -import -V" mode
- Import attributes for wires
- Support VHDL enums
- Added support for command files
* New back-ends
- Added initial EFINIX support
- Added Intel ALM: alternative synthesis for Intel FPGAs
- Added initial Nexus support
- Added initial MachXO2 support
- Added initial QuickLogic PolarPro 3 support
* ECP5 support
- Renamed labels/options in synth_ecp5 (e.g. dram -> map_lutram; -nodram -> -nolutram)
- Added "synth_ecp5 -abc9" (experimental)
- Added "synth_ecp5 -nowidelut"
- "synth_ecp5" to now infer DSP blocks (-nodsp to disable, experimental)
* iCE40 support
- Added "synth_ice40 -abc9" (experimental)
- Added "synth_ice40 -device"
- Renamed labels/options in synth_ice40 (e.g. dram -> map_lutram; -nodram -> -nolutram)
- Added "ice40_wrapcarry" to encapsulate SB_LUT+SB_CARRY pairs for techmapping
- Removed "ice40_unlut"
- Added "ice40_dsp" for Lattice iCE40 DSP packing
- "synth_ice40 -dsp" to infer DSP blocks
* Xilinx support
- Added "synth_xilinx -abc9" (experimental)
- Added "synth_xilinx -nocarry"
- Added "synth_xilinx -nowidelut"
- "synth_xilinx" to now infer wide multiplexers (-widemux <min> to enable)
- Renamed labels/options in synth_xilinx (e.g. dram -> map_lutram; -nodram -> -nolutram)
- Added "synth_xilinx -family xc6s" for Spartan 6 support (experimental)
- Added "synth_xilinx -ise" (experimental)
- Added "synth_xilinx -iopad"
- "synth_xilinx" now automatically inserts clock buffers (add -noclkbuf to disable)
- Added "xilinx_srl" for Xilinx shift register extraction
- Removed "shregmap -tech xilinx" (superseded by "xilinx_srl")
- Added "xilinx_dsp" for Xilinx DSP packing
- "synth_xilinx" to now infer DSP blocks (-nodsp to disable)
- Added latch support to synth_xilinx
- Added support for flip-flops with synchronous reset to synth_xilinx
- Added support for flip-flops with reset and enable to synth_xilinx
- Added "xilinx_dffopt" pass
- Added "synth_xilinx -dff"
* Intel support
- Renamed labels in synth_intel (e.g. bram -> map_bram)
- synth_intel: cyclone10 -> cyclone10lp, a10gx -> arria10gx
- Added "intel_alm -abc9" (experimental)
* CoolRunner2 support
- Separate and improve buffer cell insertion pass
- Use extract_counter to optimize counters
Yosys 0.8 .. Yosys 0.9
----------------------
* Various
- Many bugfixes and small improvements
- Added support for SystemVerilog interfaces and modports
- Added "write_edif -attrprop"
- Added "opt_lut" pass
- Added "gate2lut.v" techmap rule
- Added "rename -src"
- Added "equiv_opt" pass
- Added "flowmap" LUT mapping pass
- Added "rename -wire" to rename cells based on the wires they drive
- Added "bugpoint" for creating minimised testcases
- Added "write_edif -gndvccy"
- "write_verilog" to escape Verilog keywords
- Fixed sign handling of real constants
- "write_verilog" to write initial statement for initial flop state
- Added pmgen pattern matcher generator
- Fixed opt_rmdff handling of $_DFFSR_???_ and $_DLATCHSR_???_
- Added "setundef -params" to replace undefined cell parameters
- Renamed "yosys -D" to "yosys -U", added "yosys -D" to set Verilog defines
- Fixed handling of defparam when default_nettype is none
- Fixed "wreduce" flipflop handling
- Fixed FIRRTL to Verilog process instance subfield assignment
- Added "write_verilog -siminit"
- Several fixes and improvements for mem2reg memories
- Fixed handling of task output ports in clocked always blocks
- Improved handling of and-with-1 and or-with-0 in "opt_expr"
- Added "read_aiger" frontend
- Added "mutate" pass
- Added "hdlname" attribute
- Added "rename -output"
- Added "read_ilang -lib"
- Improved "proc" full_case detection and handling
- Added "whitebox" and "lib_whitebox" attributes
- Added "read_verilog -nowb", "flatten -wb" and "wbflip"
- Added Python bindings and support for Python plug-ins
- Added "pmux2shiftx"
- Added log_debug framework for reduced default verbosity
- Improved "opt_expr" and "opt_clean" handling of (partially) undriven and/or unused wires
- Added "peepopt" peephole optimisation pass using pmgen
- Added approximate support for SystemVerilog "var" keyword
- Added parsing of "specify" blocks into $specrule and $specify[23]
- Added support for attributes on parameters and localparams
- Added support for parsing attributes on port connections
- Added "wreduce -keepdc"
- Added support for optimising $dffe and $_DFFE_* cells in "opt_rmdff"
- Added Verilog wand/wor wire type support
- Added support for elaboration system tasks
- Added "muxcover -mux{4,8,16}=<cost>"
- Added "muxcover -dmux=<cost>"
- Added "muxcover -nopartial"
- Added "muxpack" pass
- Added "pmux2shiftx -norange"
- Added support for "~" in filename parsing
- Added "read_verilog -pwires" feature to turn parameters into wires
- Fixed sign extension of unsized constants with 'bx and 'bz MSB
- Fixed genvar to be a signed type
- Added support for attributes on case rules
- Added "upto" and "offset" to JSON frontend and backend
- Several liberty file parser improvements
- Fixed handling of more complex BRAM patterns
- Add "write_aiger -I -O -B"
* Formal Verification
- Added $changed support to read_verilog
- Added "read_verilog -noassert -noassume -assert-assumes"
- Added btor ops for $mul, $div, $mod and $concat
- Added yosys-smtbmc support for btor witnesses
- Added "supercover" pass
- Fixed $global_clock handling vs autowire
- Added $dffsr support to "async2sync"
- Added "fmcombine" pass
- Added memory init support in "write_btor"
- Added "cutpoint" pass
- Changed "ne" to "neq" in btor2 output
- Added support for SVA "final" keyword
- Added "fmcombine -initeq -anyeq"
- Added timescale and generated-by header to yosys-smtbmc vcd output
- Improved BTOR2 handling of undriven wires
* Verific support
- Enabled Verific flags vhdl_support_variable_slice and veri_elaborate_top_level_modules_having_interface_ports
- Improved support for asymmetric memories
- Added "verific -chparam"
- Fixed "verific -extnets" for more complex situations
- Added "read -verific" and "read -noverific"
- Added "hierarchy -chparam"
* New back-ends
- Added initial Anlogic support
- Added initial SmartFusion2 and IGLOO2 support
* ECP5 support
- Added "synth_ecp5 -nowidelut"
- Added BRAM inference support to "synth_ecp5"
- Added support for transforming Diamond IO and flipflop primitives
* iCE40 support
- Added "ice40_unlut" pass
- Added "synth_ice40 -relut"
- Added "synth_ice40 -noabc"
- Added "synth_ice40 -dffe_min_ce_use"
- Added DSP inference support using pmgen
- Added support for initialising BRAM primitives from a file
- Added iCE40 Ultra RGB LED driver cells
* Xilinx support
- Use "write_edif -pvector bra" for Xilinx EDIF files
- Fixes for VPR place and route support with "synth_xilinx"
- Added more cell simulation models
- Added "synth_xilinx -family"
- Added "stat -tech xilinx" to estimate logic cell usage
- Added "synth_xilinx -nocarry"
- Added "synth_xilinx -nowidelut"
- "synth_xilinx" to now infer hard shift registers (-nosrl to disable)
- Added support for mapping RAM32X1D
Yosys 0.7 .. Yosys 0.8
----------------------
* Various
- Many bugfixes and small improvements
- Strip debug symbols from installed binary
- Replace -ignore_redef with -[no]overwrite in front-ends
- Added write_verilog hex dump support, add -nohex option
- Added "write_verilog -decimal"
- Added "scc -set_attr"
- Added "verilog_defines" command
- Remember defines from one read_verilog to next
- Added support for hierarchical defparam
- Added FIRRTL back-end
- Improved ABC default scripts
- Added "design -reset-vlog"
- Added "yosys -W regex", "yosys -w regex", and "yosys -e regex"
- Added Verilog $rtoi and $itor support
- Added "check -initdrv"
- Added "read_blif -wideports"
- Added support for SystemVerilog "++" and "--" operators
- Added support for SystemVerilog unique, unique0, and priority case
- Added "write_edif" options for edif "flavors"
- Added support for resetall compiler directive
- Added simple C beck-end (bitwise combinatorical only atm)
- Added $_ANDNOT_ and $_ORNOT_ cell types
- Added cell library aliases to "abc -g"
- Added "setundef -anyseq"
- Added "chtype" command
- Added "design -import"
- Added "write_table" command
- Added "read_json" command
- Added "sim" command
- Added "extract_fa" and "extract_reduce" commands
- Added "extract_counter" command
- Added "opt_demorgan" command
- Added support for $size and $bits SystemVerilog functions
- Added "blackbox" command
- Added "ltp" command
- Added support for editline as replacement for readline
- Added warnings for driver-driver conflicts between FFs (and other cells) and constants
- Added "yosys -E" for creating Makefile dependencies files
- Added "synth -noshare"
- Added "memory_nordff"
- Added "setundef -undef -expose -anyconst"
- Added "expose -input"
- Added specify/specparam parser support (simply ignore them)
- Added "write_blif -inames -iattr"
- Added "hierarchy -simcheck"
- Added an option to statically link abc into yosys
- Added protobuf back-end
- Added BLIF parsing support for .conn and .cname
- Added read_verilog error checking for reg/wire/logic misuse
- Added "make coverage" and ENABLE_GCOV build option
* Changes in Yosys APIs
- Added ConstEval defaultval feature
- Added {get,set}_src_attribute() methods on RTLIL::AttrObject
- Added SigSpec::is_fully_ones() and Const::is_fully_ones()
- Added log_file_warning() and log_file_error() functions