Paths does not have the same hierarchy separator ("\/" or "/")

[titan73]

Describe the bug

Messages containing paths with "/" hierarchy separator (Note "/" is used to add the pin):

[ERROR DRT-0073] No access point for clkbuf_0_I_digital_top\/alwayson_top_i\/s_clk4M_dft/A.
[INFO CTS-0027] Generating H-Tree topology for net I_digital_top\/nvm_control_top_0\/u_nvm_mmu_softip_top\/u_nvm_ctrl\/c_nvm_wrapper\/n608.
[INFO CTS-0098] Clock net "I_digital_top\/computing_top_i\/average_inst\/net14332"
[WARNING CTS-0041] Net "I_digital_top\/alwayson_top_i\/reg_top_i\/s_power_uv_l_reg_clk" has 1 sinks. Skipping...

Messages containing paths with "/" hierarchy separator:

[ERROR DRT-0073] No access point for I_digital_top/alwayson_top_i/reg_top_i/U82/A.
[INFO CTS-0007] Net "I_digital_top/alwayson_top_i/clkgen_i/int_clk31K" found for clock "clock_osc_4m_div4_div32".
[INFO CTS-0010]  Clock net "I_digital_top/nvm_control_top_0/u_nvm_mmu_softip_top/u_nvm_ctrl/c_nvm_wrapper/s_clk_pckdiv2" has 4 sinks.
[WARNING DRT-0120] Large net I_digital_top/nvm_control_top_0/u_cyclic_crc_check/n311 has 114 pins which may impact routing performance. Consider optimization.
[WARNING STA-0363] pin 'I_digital_top/nvm_control_top_0/u_nvm_mmu_softip_top/u_mux_nvm_remap_rst_n/Z' not found.

Even wierder, [ERROR DRT-0073] can have both separators???

Is there supposed to be a standard separator?

Expected Behavior

Same separator

Environment

Latest git

To Reproduce

Whatever test case.

Relevant log output

No response

Screenshots

No response

Additional Context

No response

[titan73]

Hierarchy separator '/' is escaped for clock nets in src/cts/src/Clock.cpp:

Clock::Clock(const std::string& netName,
             const std::string& clockPin,
             const std::string& sdcClockName,
             int clockPinX,
             int clockPinY)
    : clockPin_(clockPin),
      sdcClockName_(sdcClockName),
      clockPinX_(clockPinX),
      clockPinY_(clockPinY)
{
  // Hierarchy delimiters in the net name must be escape.  We use
  // the name to construct buffer names later and the delimiters
  // will confuse downstream tools like read_spef.
  netName_ = sta::escapeChars(netName.c_str(), '/', '\0', '\\');
}

Disabled escaping makes all messages coherents.
Is escaping clock nets is this still relevant? Signal nets are not escaped and there is no issue apparently. Do I miss something?

[maliberty]

How does changing cts fix drt? Names in EDA are generally awful. I would guess you have escaped verilog names in your netlist. Without a test case it is hard to say.