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I made a proposal for supporting defect descriptions in Verilog-AMS style (which ADMS should cope with), but I need people to join the IEEE effort and vote for it.
I plan to use Python & Xyce for running the simulation & analysis if I can get a standard methodology in place that customers will use.
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There is an IEEE standard being developed for defect analysis and fault coverage -
https://standards.ieee.org/project/2427.html
I made a proposal for supporting defect descriptions in Verilog-AMS style (which ADMS should cope with), but I need people to join the IEEE effort and vote for it.
I plan to use Python & Xyce for running the simulation & analysis if I can get a standard methodology in place that customers will use.
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