From 98d6f433313a3d8dcf08dce25e744617b45aa913 Mon Sep 17 00:00:00 2001 From: Nikodem Kastelik Date: Tue, 27 Jun 2023 19:01:14 +0000 Subject: [PATCH] nrfx 3.1.0 release Signed-off-by: Nikodem Kastelik --- CHANGELOG.md | 17 + doc/nrfx.doxyfile | 2 +- drivers/include/nrfx_nfct.h | 13 +- drivers/include/nrfx_nvmc.h | 2 +- drivers/include/nrfx_saadc.h | 12 +- drivers/include/nrfx_spim.h | 15 +- drivers/nrfx_common.h | 15 + drivers/nrfx_utils_internal.h | 4 +- drivers/src/nrfx_clock.c | 4 - drivers/src/nrfx_gpiote.c | 151 +- drivers/src/nrfx_nfct.c | 404 +- drivers/src/nrfx_nvmc.c | 10 +- drivers/src/nrfx_pwm.c | 36 +- drivers/src/nrfx_qdec.c | 2 +- drivers/src/nrfx_spim.c | 49 +- drivers/src/nrfx_spis.c | 182 +- drivers/src/nrfx_temp.c | 4 + drivers/src/nrfx_wdt.c | 2 +- drivers/src/prs/nrfx_prs.h | 24 +- hal/nrf_cache.h | 229 +- hal/nrf_clock.h | 95 +- hal/nrf_common.h | 15 + hal/nrf_dppi.h | 8 +- hal/nrf_ficr.h | 97 +- hal/nrf_gpio.h | 18 +- hal/nrf_nfct.h | 235 +- hal/nrf_nvmc.h | 101 + hal/nrf_power.h | 586 ++- hal/nrf_pwm.h | 15 +- hal/nrf_radio.h | 5 +- hal/nrf_saadc.h | 37 +- hal/nrf_spim.h | 7 +- hal/nrf_spu.h | 69 +- hal/nrf_temp.h | 38 + hal/nrf_timer.h | 3 +- hal/nrf_twim.h | 8 +- haly/nrfy_dppi.h | 2 +- haly/nrfy_nfct.h | 836 ++++ haly/nrfy_temp.h | 25 + mdk/nrf.h | 4 +- mdk/nrf51.h | 6 +- mdk/nrf52.h | 6 +- mdk/nrf52805.h | 6 +- mdk/nrf52810.h | 6 +- mdk/nrf52811.h | 6 +- mdk/nrf52820.h | 6 +- mdk/nrf52833.h | 6 +- mdk/nrf52840.h | 6 +- mdk/nrf52_erratas.h | 171 + mdk/nrf5340_application.h | 6 +- mdk/nrf5340_network.h | 6 +- mdk/nrf53_erratas.h | 74 +- mdk/nrf9120.h | 73 +- mdk/nrf9120.svd | 6506 ++++++++++++++++-------------- mdk/nrf9120_bitfields.h | 6014 +++++++++++++-------------- mdk/nrf9160.h | 6 +- mdk/nrf_common.ld | 67 +- templates/nrfx_config_nrf51.h | 51 + templates/nrfx_config_nrf52805.h | 6 +- templates/nrfx_config_nrf52810.h | 6 +- templates/nrfx_config_nrf52811.h | 6 +- templates/nrfx_config_nrf52820.h | 6 +- templates/nrfx_config_nrf52832.h | 15 +- templates/nrfx_config_nrf52833.h | 6 +- templates/nrfx_config_nrf52840.h | 6 +- templates/nrfx_config_nrf91.h | 6 +- 66 files changed, 9663 insertions(+), 6797 deletions(-) create mode 100644 haly/nrfy_nfct.h diff --git a/CHANGELOG.md b/CHANGELOG.md index 7e23aea62..4a31d3a94 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -1,6 +1,23 @@ # Changelog All notable changes to this project are documented in this file. +## [3.1.0] - 2023-06-28 + +### Added +- Added the HALY layer for the NFCT. HALY is an extension of the HAL layer that aggregates basic hardware use cases within single functions. Now it is used instead of HAL in the NFCT drivers. +- Added the NRFX_IN_RANGE() macro for checking if a given value is in a given range. +- Added functions for writing a word to the flash and reading a buffer, word, halfword, and byte in the NVMC HAL. + +### Changed +- Updated MDK to version 8.55.0. +- Modified the power management in the SPIM driver. Now the nrfx_spim_abort() function must be called once all expected transactions using the NRFX_SPIM_FLAG_NO_XFER_EVT_HANDLER, NRFX_SPIM_FLAG_HOLD_XFER, or NRFX_SPIM_FLAG_REPEATED_XFER option flags are finalized. + +### Fixed +- Fixed a workaround for the anomaly 109 on the nRF52 family in the SPIM and SPIS drivers. +- Fixed the NRFX_TIMER_FREQUENCY_STATIC_CHECK() and NRFX_SPIM_FREQUENCY_STATIC_CHECK() macros. +- Fixed the nrfx_wdt_reconfigure() function that was returning the NRFX_ERROR_INVALID_STATE error code when the driver instance has been initialized. +- Fixed the nrfx_pwm_stopped_check() function when used without user's handler function. + ## [3.0.0] - 2023-04-25 ### Added - Added the HALY layer for the following peripherals: COMP, DPPI, GPIO, GPIOTE, I2S, LPCOMP, PDM, PWM, QDEC, RTC, SAADC, SPIM, TEMP, TIMER, TWIM, UARTE, WDT. HALY is an extension of the HAL layer that aggregates basic hardware use cases within single functions. Now it is used instead of HAL in the corresponding drivers. diff --git a/doc/nrfx.doxyfile b/doc/nrfx.doxyfile index 5c1b33a3d..c41e75689 100644 --- a/doc/nrfx.doxyfile +++ b/doc/nrfx.doxyfile @@ -50,7 +50,7 @@ PROJECT_NAME = "nrfx" ### EDIT THIS ### -PROJECT_NUMBER = "3.0" +PROJECT_NUMBER = "3.1" # Using the PROJECT_BRIEF tag one can provide an optional one line description # for a project that appears at the top of each page and should give viewer a diff --git a/drivers/include/nrfx_nfct.h b/drivers/include/nrfx_nfct.h index c0d1d8388..813278f1a 100644 --- a/drivers/include/nrfx_nfct.h +++ b/drivers/include/nrfx_nfct.h @@ -35,7 +35,7 @@ #define NRFX_NFCT_H__ #include -#include +#include #ifdef __cplusplus extern "C" { @@ -179,6 +179,7 @@ typedef struct { uint32_t rxtx_int_mask; ///< Mask for enabling RX/TX events. Indicate which events must be forwarded to the upper layer by using @ref nrfx_nfct_evt_id_t. By default, no events are enabled. */ nrfx_nfct_handler_t cb; ///< Callback. + uint8_t irq_priority; ///< Interrupt priority. } nrfx_nfct_config_t; /** @@ -188,6 +189,7 @@ typedef struct * * @retval NRFX_SUCCESS The NFCT driver was initialized successfully. * @retval NRFX_ERROR_INVALID_STATE The NFCT driver is already initialized. + * @retval NRFX_ERROR_FORBIDDEN The NFCT antenna pads are not configured as antenna pins. */ nrfx_err_t nrfx_nfct_init(nrfx_nfct_config_t const * p_config); @@ -225,8 +227,11 @@ bool nrfx_nfct_field_check(void); * @brief Function for preparing the NFCT driver for receiving an NFC frame. * * @param[in] p_rx_data Pointer to the RX buffer. + * + * @retval NRFX_SUCCESS The operation was successful. + * @retval NRFX_ERROR_INVALID_ADDR Data buffer does not point to memory region reachable by EasyDMA. */ -void nrfx_nfct_rx(nrfx_nfct_data_desc_t const * p_rx_data); +nrfx_err_t nrfx_nfct_rx(nrfx_nfct_data_desc_t const * p_rx_data); /** * @brief Function for transmitting an NFC frame. @@ -237,6 +242,8 @@ void nrfx_nfct_rx(nrfx_nfct_data_desc_t const * p_rx_data); * @retval NRFX_SUCCESS The operation was successful. * @retval NRFX_ERROR_INVALID_LENGTH The TX buffer size is invalid. * @retval NRFX_ERROR_BUSY Driver is already transferring. + * @retval NRFX_ERROR_INVALID_ADDR Data buffer does not point to memory region reachable by + * EasyDMA. */ nrfx_err_t nrfx_nfct_tx(nrfx_nfct_data_desc_t const * p_tx_data, nrf_nfct_frame_delay_mode_t delay_mode); @@ -251,6 +258,8 @@ nrfx_err_t nrfx_nfct_tx(nrfx_nfct_data_desc_t const * p_tx_data, * @retval NRFX_SUCCESS The operation was successful. * @retval NRFX_ERROR_INVALID_LENGTH The TX buffer size is invalid. * @retval NRFX_ERROR_BUSY Driver is already transferring. + * @retval NRFX_ERROR_INVALID_ADDR Data buffer does not point to memory region reachable by + * EasyDMA. */ nrfx_err_t nrfx_nfct_bits_tx(nrfx_nfct_data_desc_t const * p_tx_data, nrf_nfct_frame_delay_mode_t delay_mode); diff --git a/drivers/include/nrfx_nvmc.h b/drivers/include/nrfx_nvmc.h index daff15029..222e8cd82 100644 --- a/drivers/include/nrfx_nvmc.h +++ b/drivers/include/nrfx_nvmc.h @@ -328,7 +328,7 @@ NRFX_STATIC_INLINE bool nrfx_nvmc_write_done_check(void) NRFX_STATIC_INLINE uint32_t nrfx_nvmc_uicr_word_read(uint32_t const volatile *address) { - uint32_t value = *address; + uint32_t value = nrf_nvmc_word_read((uint32_t)address); #if NRF91_ERRATA_7_ENABLE_WORKAROUND __DSB(); diff --git a/drivers/include/nrfx_saadc.h b/drivers/include/nrfx_saadc.h index 0114be5d6..be1c7fdcd 100644 --- a/drivers/include/nrfx_saadc.h +++ b/drivers/include/nrfx_saadc.h @@ -79,8 +79,10 @@ extern "C" { { \ .channel_config = \ { \ - .resistor_p = NRF_SAADC_RESISTOR_DISABLED, \ - .resistor_n = NRF_SAADC_RESISTOR_DISABLED, \ + NRFX_COND_CODE_1(NRF_SAADC_HAS_CH_CONFIG_RES, \ + (.resistor_p = NRF_SAADC_RESISTOR_DISABLED, \ + .resistor_n = NRF_SAADC_RESISTOR_DISABLED,), \ + ()) \ .gain = NRF_SAADC_GAIN1, \ .reference = NRF_SAADC_REFERENCE_INTERNAL, \ .acq_time = NRFX_SAADC_DEFAULT_ACQTIME, \ @@ -115,8 +117,10 @@ extern "C" { { \ .channel_config = \ { \ - .resistor_p = NRF_SAADC_RESISTOR_DISABLED, \ - .resistor_n = NRF_SAADC_RESISTOR_DISABLED, \ + NRFX_COND_CODE_1(NRF_SAADC_HAS_CH_CONFIG_RES, \ + (.resistor_p = NRF_SAADC_RESISTOR_DISABLED, \ + .resistor_n = NRF_SAADC_RESISTOR_DISABLED,), \ + ()) \ .gain = NRF_SAADC_GAIN1, \ .reference = NRF_SAADC_REFERENCE_INTERNAL, \ .acq_time = NRFX_SAADC_DEFAULT_ACQTIME, \ diff --git a/drivers/include/nrfx_spim.h b/drivers/include/nrfx_spim.h index 8b93bebf6..75e8f5d9d 100644 --- a/drivers/include/nrfx_spim.h +++ b/drivers/include/nrfx_spim.h @@ -311,13 +311,17 @@ void nrfx_spim_uninit(nrfx_spim_t const * p_instance); * flag if the transfer is triggered externally by PPI. Use * @ref nrfx_spim_start_task_address_get to get the address of the start task. * Chip select must be configured to @ref NRF_SPIM_PIN_NOT_CONNECTED and managed outside the driver. + * If you do not expect more transfers, you should call @ref nrfx_spim_abort to inform the driver + * that the peripheral can be put into a low power state. * - @ref NRFX_SPIM_FLAG_NO_XFER_EVT_HANDLER - No user event handler after transfer * completion. This also means no interrupt at the end of the transfer. * If @ref NRFX_SPIM_FLAG_NO_XFER_EVT_HANDLER is used, the driver does not set the instance into * busy state, so you must ensure that the next transfers are set up when SPIM is not active. + * Additionally, you should call @ref nrfx_spim_abort to inform the driver that no more transfers will occur. * @ref nrfx_spim_end_event_address_get function can be used to detect end of transfer. Option can * be used together with @ref NRFX_SPIM_FLAG_REPEATED_XFER to prepare a sequence of SPI transfers - * without interruptions. + * without interruptions. If you do not expect more transfers, you should call @ref nrfx_spim_abort + * to inform the driver that the peripheral can be put into a low power state. * - @ref NRFX_SPIM_FLAG_REPEATED_XFER - Prepare for repeated transfers. You can set * up a number of transfers that will be triggered externally (for example by PPI). An example is * a TXRX transfer with the options @ref NRFX_SPIM_FLAG_RX_POSTINC, @@ -327,7 +331,8 @@ void nrfx_spim_uninit(nrfx_spim_t const * p_instance); * @ref nrfx_spim_end_event_address_get can be used to get the address of the END event, which can * be used to count the number of transfers. If @ref NRFX_SPIM_FLAG_REPEATED_XFER is used, * the driver does not set the instance into busy state, so you must ensure that the next - * transfers are set up when SPIM is not active. + * transfers are set up when SPIM is not active. If you do not expect more transfers, you should call + * @ref nrfx_spim_abort to inform the driver that the peripheral can be put into a low power state. * * @note Peripherals using EasyDMA (including SPIM) require the transfer buffers * to be placed in the Data RAM region. If this condition is not met, @@ -409,6 +414,12 @@ NRFX_STATIC_INLINE uint32_t nrfx_spim_end_event_address_get(nrfx_spim_t const * /** * @brief Function for aborting ongoing transfer. * + * @note You should call the function if the first transfer has been started with one or more + * of the following options: @ref NRFX_SPIM_FLAG_NO_XFER_EVT_HANDLER, + * @ref NRFX_SPIM_FLAG_HOLD_XFER, and @ref NRFX_SPIM_FLAG_REPEATED_XFER. When you do not + * expect more transfers, use this function so that the driver can put the peripheral into + * a low power state. + * * @param[in] p_instance Pointer to the driver instance structure. */ void nrfx_spim_abort(nrfx_spim_t const * p_instance); diff --git a/drivers/nrfx_common.h b/drivers/nrfx_common.h index 70f9d466f..ae58dad52 100644 --- a/drivers/nrfx_common.h +++ b/drivers/nrfx_common.h @@ -37,6 +37,7 @@ #include #include #include +#include #include #include @@ -405,6 +406,20 @@ extern "C" { */ #define NRFX_MAX(a, b) ((a) > (b) ? (a) : (b)) +/** + * @brief Macro for checking if a given value is in a given range. + * + * @note @p val is evaluated twice. + * + * @param[in] val A value to be checked. + * @param[in] min The lower bound (inclusive). + * @param[in] max The upper bound (inclusive). + * + * @retval true The value is in the given range. + * @retval false The value is out of the given range. + */ +#define NRFX_IN_RANGE(val, min, max) ((val) >= (min) && (val) <= (max)) + /** * @brief Macro for performing rounded integer division (as opposed to * truncating the result). diff --git a/drivers/nrfx_utils_internal.h b/drivers/nrfx_utils_internal.h index 4c742b9ba..cc1a90739 100644 --- a/drivers/nrfx_utils_internal.h +++ b/drivers/nrfx_utils_internal.h @@ -235,9 +235,9 @@ void NRFX_CONCAT(nrfx_, periph_name_small, _, prefix, i, _irq_handler)(void) \ ) /** - * @brief Macro for generating else if statement code blocks that assignes token \\\\ + * @brief Macro for generating else if statement code blocks that assignes token \\\\ * to the variable \ if \ points to the instance NRF_\\\. - * + * * @param[in] periph_name Peripheral name, e.g. SPIM. * @param[in] prefix Prefix appended to the index. * @param[in] i Index. diff --git a/drivers/src/nrfx_clock.c b/drivers/src/nrfx_clock.c index 32d0320ac..a30d92169 100644 --- a/drivers/src/nrfx_clock.c +++ b/drivers/src/nrfx_clock.c @@ -373,11 +373,7 @@ void nrfx_clock_start(nrf_clock_domain_t domain) else if (nrf_clock_start_task_check(NRF_CLOCK, NRF_CLOCK_DOMAIN_LFCLK)) { // LF clock is not active yet but was started already. Inspect its source. -#if NRF_CLOCK_HAS_XO - lfclksrc = nrf_clock_lf_actv_src_get(NRF_CLOCK); -#else lfclksrc = nrf_clock_lf_srccopy_get(NRF_CLOCK); -#endif if (clock_lfclksrc_tweak(&lfclksrc)) { // LF clock was started already and the configured source diff --git a/drivers/src/nrfx_gpiote.c b/drivers/src/nrfx_gpiote.c index 733495f3c..fa9ebbf61 100644 --- a/drivers/src/nrfx_gpiote.c +++ b/drivers/src/nrfx_gpiote.c @@ -42,15 +42,18 @@ #define NRFX_LOG_MODULE GPIOTE #include -#if (GPIO_COUNT == 1) -#define MAX_PIN_NUMBER 32 -#elif (GPIO_COUNT == 2) -#define MAX_PIN_NUMBER (32 + P1_PIN_NUM) -#elif (GPIO_COUNT > 2) -#define MAX_PIN_NUMBER (32 * GPIO_COUNT) -#else -#error "Not supported." -#endif +/* Macro returning number of pins in the port */ +#define GPIO_PIN_NUM(periph, prefix, i, _) NRFX_CONCAT(periph, prefix, i, _PIN_NUM) + +/* Macro for calculating total number of pins. */ +#define MAX_PIN_NUMBER NRFX_FOREACH_PRESENT(P, GPIO_PIN_NUM, (+), (0), _) + +/* Macro returns true if port has 32 pins. */ +#define GPIO_IS_FULL_PORT(periph, prefix, i, _) \ + (NRFX_CONCAT(periph, prefix, i, _PIN_NUM) == 32) + +/* Macro return true if all ports has 32 pins. In that case pin numbers are continuous. */ +#define FULL_PORTS_PRESENT (NRFX_FOREACH_PRESENT(P, GPIO_IS_FULL_PORT, (&&), (1), _)) /* Use legacy configuration if new is not present. That will lead to slight * increase of RAM usage since number of slots will exceed application need. @@ -176,6 +179,43 @@ static gpiote_control_block_t m_cb = { .available_channels_mask = NRFX_GPIOTE_APP_CHANNELS_MASK }; +#if defined(NRF_GPIO_LATCH_PRESENT) || (!FULL_PORTS_PRESENT) +static const uint8_t ports[GPIO_COUNT] = GPIO_PORT_NUM_LIST; +#endif + +#define GPIO_PORT_OFFSET(i, _) \ + NRFX_COND_CODE_1(NRFX_INSTANCE_PRESENT(NRFX_CONCAT(P, i)),(NRFX_CONCAT(P, i, _PIN_NUM)), (0)) + +static uint8_t get_pin_idx(nrfx_gpiote_pin_t pin) +{ +#if FULL_PORTS_PRESENT + // If all ports have 32 pins then array ordering matches pin ordering. + return pin; +#else + // Possible instances must be explicitely listed as NRFX_LISTIFY cannot be nested. + static const uint8_t port_offset[] = { + 0, + NRFX_LISTIFY(1, GPIO_PORT_OFFSET, (+), _), + NRFX_LISTIFY(2, GPIO_PORT_OFFSET, (+), _), + NRFX_LISTIFY(3, GPIO_PORT_OFFSET, (+), _), + NRFX_LISTIFY(4, GPIO_PORT_OFFSET, (+), _), + NRFX_LISTIFY(5, GPIO_PORT_OFFSET, (+), _), + NRFX_LISTIFY(6, GPIO_PORT_OFFSET, (+), _), + NRFX_LISTIFY(7, GPIO_PORT_OFFSET, (+), _), + NRFX_LISTIFY(8, GPIO_PORT_OFFSET, (+), _), + NRFX_LISTIFY(9, GPIO_PORT_OFFSET, (+), _), + NRFX_LISTIFY(10, GPIO_PORT_OFFSET, (+), _), + NRFX_LISTIFY(11, GPIO_PORT_OFFSET, (+), _), + NRFX_LISTIFY(12, GPIO_PORT_OFFSET, (+), _), + NRFX_LISTIFY(13, GPIO_PORT_OFFSET, (+), _), + NRFX_LISTIFY(14, GPIO_PORT_OFFSET, (+), _), + NRFX_LISTIFY(15, GPIO_PORT_OFFSET, (+), _), + }; + + return port_offset[pin >> 5] + (pin & 0x1F); +#endif +} + /** @brief Checks if pin is in use by the driver. * * @param[in] pin Absolute pin. @@ -184,7 +224,7 @@ static gpiote_control_block_t m_cb = { */ static bool pin_in_use(uint32_t pin) { - return m_cb.pin_flags[pin] & PIN_FLAG_IN_USE; + return m_cb.pin_flags[get_pin_idx(pin)] & PIN_FLAG_IN_USE; } /** @brief Check if Task/Event is used. @@ -197,7 +237,7 @@ static bool pin_in_use(uint32_t pin) */ static bool pin_in_use_by_te(uint32_t pin) { - return m_cb.pin_flags[pin] & PIN_FLAG_TE_USED; + return m_cb.pin_flags[get_pin_idx(pin)] & PIN_FLAG_TE_USED; } /** @brief Check if pin has trigger. @@ -208,7 +248,7 @@ static bool pin_in_use_by_te(uint32_t pin) */ static bool pin_has_trigger(uint32_t pin) { - return PIN_FLAG_TRIG_MODE_GET(m_cb.pin_flags[pin]) != NRFX_GPIOTE_TRIGGER_NONE; + return PIN_FLAG_TRIG_MODE_GET(m_cb.pin_flags[get_pin_idx(pin)]) != NRFX_GPIOTE_TRIGGER_NONE; } /** @brief Check if pin is output. @@ -221,7 +261,7 @@ static bool pin_has_trigger(uint32_t pin) */ static bool pin_is_output(uint32_t pin) { - return PIN_FLAG_IS_OUTPUT(m_cb.pin_flags[pin]); + return PIN_FLAG_IS_OUTPUT(m_cb.pin_flags[get_pin_idx(pin)]); } /** @brief Check if pin is output controlled by GPIOTE task. @@ -261,7 +301,7 @@ static nrf_gpiote_polarity_t gpiote_trigger_to_polarity(nrfx_gpiote_trigger_t tr /* Returns gpiote TE channel associated with the pin */ static uint8_t pin_te_get(nrfx_gpiote_pin_t pin) { - return PIN_GET_TE_ID(m_cb.pin_flags[pin]); + return PIN_GET_TE_ID(m_cb.pin_flags[get_pin_idx(pin)]); } static bool is_level(nrfx_gpiote_trigger_t trigger) @@ -285,14 +325,15 @@ static bool handler_in_use(int32_t handler_id) * pair is not used by other pin. */ static void release_handler(nrfx_gpiote_pin_t pin) { - int32_t handler_id = PIN_GET_HANDLER_ID(m_cb.pin_flags[pin]); + uint8_t idx = get_pin_idx(pin); + int32_t handler_id = PIN_GET_HANDLER_ID(m_cb.pin_flags[idx]); if (handler_id == PIN_FLAG_NO_HANDLER) { return; } - m_cb.pin_flags[pin] &= ~PIN_HANDLER_MASK; + m_cb.pin_flags[idx] &= ~PIN_HANDLER_MASK; /* Check if other pin is using same handler and release handler only if handler * is not used by others. @@ -324,7 +365,7 @@ static void pin_handler_trigger_uninit(nrfx_gpiote_pin_t pin) } release_handler(pin); - m_cb.pin_flags[pin] = PIN_FLAG_NOT_USED; + m_cb.pin_flags[get_pin_idx(pin)] = PIN_FLAG_NOT_USED; } nrfx_err_t nrfx_gpiote_pin_uninit(nrfx_gpiote_pin_t pin) @@ -384,14 +425,14 @@ static nrfx_err_t pin_handler_set(nrfx_gpiote_pin_t pin, m_cb.handlers[handler_id].handler = handler; m_cb.handlers[handler_id].p_context = p_context; - m_cb.pin_flags[pin] |= PIN_FLAG_HANDLER(handler_id); + m_cb.pin_flags[get_pin_idx(pin)] |= PIN_FLAG_HANDLER(handler_id); return NRFX_SUCCESS; } static inline nrf_gpio_pin_sense_t get_initial_sense(nrfx_gpiote_pin_t pin) { - nrfx_gpiote_trigger_t trigger = PIN_FLAG_TRIG_MODE_GET(m_cb.pin_flags[pin]); + nrfx_gpiote_trigger_t trigger = PIN_FLAG_TRIG_MODE_GET(m_cb.pin_flags[get_pin_idx(pin)]); nrf_gpio_pin_sense_t sense; if (trigger == NRFX_GPIOTE_TRIGGER_LOW) @@ -417,6 +458,7 @@ nrfx_err_t nrfx_gpiote_input_configure(nrfx_gpiote_pin_t pin, nrfx_gpiote_handler_config_t const * p_handler_config) { nrfx_err_t err; + uint8_t idx = get_pin_idx(pin); if (p_input_config) { @@ -430,8 +472,8 @@ nrfx_err_t nrfx_gpiote_input_configure(nrfx_gpiote_pin_t pin, nrfy_gpio_reconfigure(pin, &dir, &input_connect, &p_input_config->pull, NULL, NULL); - m_cb.pin_flags[pin] &= ~PIN_FLAG_OUTPUT; - m_cb.pin_flags[pin] |= PIN_FLAG_IN_USE; + m_cb.pin_flags[idx] &= ~PIN_FLAG_OUTPUT; + m_cb.pin_flags[idx] |= PIN_FLAG_IN_USE; } if (p_trigger_config) @@ -448,7 +490,7 @@ nrfx_err_t nrfx_gpiote_input_configure(nrfx_gpiote_pin_t pin, } else { - m_cb.pin_flags[pin] &= ~(PIN_TE_ID_MASK | PIN_FLAG_TE_USED); + m_cb.pin_flags[idx] &= ~(PIN_TE_ID_MASK | PIN_FLAG_TE_USED); if (use_evt) { bool edge = trigger <= NRFX_GPIOTE_TRIGGER_TOGGLE; @@ -473,7 +515,7 @@ nrfx_err_t nrfx_gpiote_input_configure(nrfx_gpiote_pin_t pin, nrfy_gpiote_event_disable(NRF_GPIOTE, ch); nrfy_gpiote_event_configure(NRF_GPIOTE, ch, pin, polarity); - m_cb.pin_flags[pin] |= PIN_FLAG_TE_ID(ch); + m_cb.pin_flags[idx] |= PIN_FLAG_TE_ID(ch); } } } @@ -487,8 +529,8 @@ nrfx_err_t nrfx_gpiote_input_configure(nrfx_gpiote_pin_t pin, nrf_bitmask_bit_set(pin, (uint8_t *)m_cb.port_pins); } #endif - m_cb.pin_flags[pin] &= ~PIN_FLAG_TRIG_MODE_MASK; - m_cb.pin_flags[pin] |= PIN_FLAG_TRIG_MODE_SET(trigger); + m_cb.pin_flags[idx] &= ~PIN_FLAG_TRIG_MODE_MASK; + m_cb.pin_flags[idx] |= PIN_FLAG_TRIG_MODE_SET(trigger); } if (p_handler_config) @@ -507,6 +549,8 @@ nrfx_err_t nrfx_gpiote_output_configure(nrfx_gpiote_pin_t pin, nrfx_gpiote_output_config_t const * p_config, nrfx_gpiote_task_config_t const * p_task_config) { + uint8_t idx = get_pin_idx(pin); + if (p_config) { /* Cannot configure pin to output if pin was using TE event. */ @@ -527,7 +571,7 @@ nrfx_err_t nrfx_gpiote_output_configure(nrfx_gpiote_pin_t pin, nrfy_gpio_reconfigure(pin, &dir, &p_config->input_connect, &p_config->pull, &p_config->drive, NULL); - m_cb.pin_flags[pin] |= PIN_FLAG_IN_USE | PIN_FLAG_OUTPUT; + m_cb.pin_flags[idx] |= PIN_FLAG_IN_USE | PIN_FLAG_OUTPUT; } if (p_task_config) @@ -540,13 +584,13 @@ nrfx_err_t nrfx_gpiote_output_configure(nrfx_gpiote_pin_t pin, uint32_t ch = p_task_config->task_ch; nrfy_gpiote_te_default(NRF_GPIOTE, ch); - m_cb.pin_flags[pin] &= ~(PIN_FLAG_TE_USED | PIN_TE_ID_MASK); + m_cb.pin_flags[idx] &= ~(PIN_FLAG_TE_USED | PIN_TE_ID_MASK); if (p_task_config->polarity != NRF_GPIOTE_POLARITY_NONE) { nrfy_gpiote_task_configure(NRF_GPIOTE, ch, pin, p_task_config->polarity, p_task_config->init_val); - m_cb.pin_flags[pin] |= PIN_FLAG_TE_ID(ch); + m_cb.pin_flags[idx] |= PIN_FLAG_TE_ID(ch); } } @@ -565,7 +609,7 @@ nrfx_err_t nrfx_gpiote_channel_get(nrfx_gpiote_pin_t pin, uint8_t *p_channel) if (pin_in_use_by_te(pin)) { - *p_channel = PIN_GET_TE_ID(m_cb.pin_flags[pin]); + *p_channel = PIN_GET_TE_ID(m_cb.pin_flags[get_pin_idx(pin)]); return NRFX_SUCCESS; } else @@ -577,7 +621,7 @@ nrfx_err_t nrfx_gpiote_channel_get(nrfx_gpiote_pin_t pin, uint8_t *p_channel) /* Return handler associated with given pin or null. */ static nrfx_gpiote_handler_config_t const * channel_handler_get(nrfx_gpiote_pin_t pin) { - int32_t handler_id = PIN_GET_HANDLER_ID(m_cb.pin_flags[pin]); + int32_t handler_id = PIN_GET_HANDLER_ID(m_cb.pin_flags[get_pin_idx(pin)]); if (handler_id == PIN_FLAG_NO_HANDLER) { @@ -618,20 +662,42 @@ bool nrfx_gpiote_is_init(void) return (m_cb.state != NRFX_DRV_STATE_UNINITIALIZED) ? true : false; } +static void pin_uninit(uint32_t pin) +{ + if (nrfy_gpio_pin_present_check(pin) && pin_in_use(pin)) + { + nrfx_gpiote_pin_uninit(pin); + } +} void nrfx_gpiote_uninit(void) { NRFX_ASSERT(m_cb.state != NRFX_DRV_STATE_UNINITIALIZED); - uint32_t i; +#if FULL_PORTS_PRESENT + // Simple iteration for simple case to save memory + for (size_t i = 0; i < MAX_PIN_NUMBER; i++) + { + pin_uninit(i); + } +#else +#define _PORT_LEN(periph, prefix, i, _) NRFX_CONCAT(periph, prefix, i, _PIN_NUM), + static const uint8_t port_lens[] = + { + NRFX_FOREACH_PRESENT(P, _PORT_LEN, (), (), _) + }; - for (i = 0; i < MAX_PIN_NUMBER; i++) + // Iterate over all pins in all ports. + for (size_t i = 0; i < NRFX_ARRAY_SIZE(ports); i++) { - if (nrfy_gpio_pin_present_check(i) && pin_in_use(i)) + for (size_t j = 0; j < port_lens[i]; j++) { - nrfx_gpiote_pin_uninit(i); + pin_uninit(32 * ports[i] + j); } } +#undef _PORT_LEN +#endif + m_cb.state = NRFX_DRV_STATE_UNINITIALIZED; NRFX_LOG_INFO("Uninitialized."); } @@ -940,19 +1006,20 @@ static void port_event_handle(void) uint32_t pin = NRF_CTZ(latch[i]); /* Convert to absolute value. */ - pin += 32 * i; + uint32_t abs_pin = NRF_PIN_PORT_TO_PIN_NUMBER(pin, ports[i]); nrf_gpio_pin_sense_t sense; - nrfx_gpiote_trigger_t trigger = PIN_FLAG_TRIG_MODE_GET(m_cb.pin_flags[pin]); + nrfx_gpiote_trigger_t trigger = + PIN_FLAG_TRIG_MODE_GET(m_cb.pin_flags[get_pin_idx(abs_pin)]); - nrf_bitmask_bit_clear(pin, latch); - sense = nrfy_gpio_pin_sense_get(pin); + nrf_bitmask_bit_clear(pin, &latch[i]); + sense = nrfy_gpio_pin_sense_get(abs_pin); - next_sense_cond_call_handler(pin, trigger, sense); + next_sense_cond_call_handler(abs_pin, trigger, sense); /* Try to clear LATCH bit corresponding to currently processed pin. * This may not succeed if the pin's state changed during the interrupt processing * and now it matches the new sense configuration. In such case, * the pin will be processed again in another iteration of the outer loop. */ - nrfy_gpio_pin_latch_clear(pin); + nrfy_gpio_pin_latch_clear(abs_pin); } } @@ -1020,7 +1087,7 @@ static void port_event_handle(void) /* Absolute */ pin = rel_pin + 32 * i; - trigger = PIN_FLAG_TRIG_MODE_GET(m_cb.pin_flags[pin]); + trigger = PIN_FLAG_TRIG_MODE_GET(m_cb.pin_flags[get_pin_idx(pin)]); sense = nrfy_gpio_pin_sense_get(pin); pin_state = nrf_bitmask_bit_is_set(pin, input); @@ -1054,7 +1121,7 @@ static void port_event_handle(void) pin = rel_pin + 32 * i; if (nrfy_gpio_pin_sense_get(pin) != NRF_GPIO_PIN_NOSENSE) { - trigger = PIN_FLAG_TRIG_MODE_GET(m_cb.pin_flags[pin]); + trigger = PIN_FLAG_TRIG_MODE_GET(m_cb.pin_flags[get_pin_idx(pin)]); if (trigger == NRFX_GPIOTE_TRIGGER_HIGH) { input[i] &= ~NRFX_BIT(rel_pin); diff --git a/drivers/src/nrfx_nfct.c b/drivers/src/nrfx_nfct.c index 67c5fe515..3dfe89e34 100644 --- a/drivers/src/nrfx_nfct.c +++ b/drivers/src/nrfx_nfct.c @@ -36,6 +36,7 @@ #if NRFX_CHECK(NRFX_NFCT_ENABLED) #include +#include #define NRFX_LOG_MODULE NFCT #include @@ -119,9 +120,9 @@ static nrfx_nfct_timer_workaround_t m_timer_workaround = #define NRFX_NFCT_BITS_TO_BYTES(_bits) ((_bits) >> 3) /* Macro for checking whether the NFCT interrupt is active. */ -#define NRFX_NFCT_EVT_ACTIVE(_name) \ - (nrf_nfct_event_check(NRF_NFCT, NRFX_CONCAT_2(NRF_NFCT_EVENT_, _name)) && \ - nrf_nfct_int_enable_check(NRF_NFCT, NRFX_CONCAT_3(NRF_NFCT_INT_, _name, _MASK))) +#define NRFX_NFCT_EVT_ACTIVE(_name, _mask) \ + (((_mask) & NRFY_EVENT_TO_INT_BITMASK(NRFX_CONCAT_2(NRF_NFCT_EVENT_, _name))) && \ + nrfy_nfct_int_enable_check(NRF_NFCT, NRFX_CONCAT_3(NRF_NFCT_INT_, _name, _MASK))) /* Macro for callback execution. */ #define NRFX_NFCT_CB_HANDLE(_cb, _evt) \ @@ -153,35 +154,57 @@ static nrfx_nfct_control_block_t m_nfct_cb; /** * @brief Common part of the setup used for the NFCT initialization and reinitialization. */ -static void nrfx_nfct_hw_init_setup(void) +static void nfct_hw_init_setup(void) { // Use Window Grid frame delay mode. - nrf_nfct_frame_delay_mode_set(NRF_NFCT, NRF_NFCT_FRAME_DELAY_MODE_WINDOWGRID); + nrfy_nfct_frame_delay_mode_set(NRF_NFCT, NRF_NFCT_FRAME_DELAY_MODE_WINDOWGRID); /* Begin: Workaround for anomaly 25 */ /* Workaround for wrong SENSRES values require using SDD00001, but here SDD00100 is used because it is required to operate with Windows Phone */ - nrf_nfct_sensres_bit_frame_sdd_set(NRF_NFCT, NRF_NFCT_SENSRES_BIT_FRAME_SDD_00100); + nrfy_nfct_sensres_bit_frame_sdd_set(NRF_NFCT, NRF_NFCT_SENSRES_BIT_FRAME_SDD_00100); /* End: Workaround for anomaly 25 */ } -static void nrfx_nfct_frame_delay_max_set(bool default_delay) +static void nfct_frame_delay_max_set(bool default_delay) { if (default_delay) { - nrf_nfct_frame_delay_max_set(NRF_NFCT, NFCT_FRAMEDELAYMAX_DEFAULT); + nrfy_nfct_frame_delay_max_set(NRF_NFCT, NFCT_FRAMEDELAYMAX_DEFAULT); } else { - nrf_nfct_frame_delay_max_set(NRF_NFCT, m_nfct_cb.frame_delay_max); + nrfy_nfct_frame_delay_max_set(NRF_NFCT, m_nfct_cb.frame_delay_max); } } +static void nfct_trims_apply(void) +{ +#if NRFY_NFCT_HAS_BIAS_CONFIG_TRIM_REG && defined(FICR_TRIM_GLOBAL_NFCT_BIASCFG_VALUE_Msk) + nrf_nfct_bias_config_t bias_cfg; + + bias_cfg.trim_ibpsr = (NRF_FICR->TRIM.GLOBAL.NFCT.BIASCFG & NFCT_BIASCFG_TRIMIBPSR_Msk) + >> NFCT_BIASCFG_TRIMIBPSR_Pos; + + bias_cfg.coarse_ibpsr = (NRF_FICR->TRIM.GLOBAL.NFCT.BIASCFG & NFCT_BIASCFG_COARSEIBPSR_Msk) + >> NFCT_BIASCFG_COARSEIBPSR_Pos; + + bias_cfg.reference_volatge = (NRF_FICR->TRIM.GLOBAL.NFCT.BIASCFG & + NFCT_BIASCFG_REFERENCEVOLTAGE_Msk) + >> NFCT_BIASCFG_REFERENCEVOLTAGE_Pos; + + bias_cfg.spare = (NRF_FICR->TRIM.GLOBAL.NFCT.BIASCFG & NFCT_BIASCFG_SPARE_Msk) + >> NFCT_BIASCFG_SPARE_Pos; + + nrfy_nfct_bias_config_set(NRF_NFCT, &bias_cfg); +#endif +} + /** @brief Function for evaluating and handling the NFC field events. * * @param[in] field_state Current field state. */ -static void nrfx_nfct_field_event_handler(volatile nrfx_nfct_field_state_t field_state) +static void nfct_field_event_handler(volatile nrfx_nfct_field_state_t field_state) { nrfx_nfct_evt_t nfct_evt; @@ -231,13 +254,13 @@ static void nrfx_nfct_field_event_handler(volatile nrfx_nfct_field_state_t field case NRFX_NFC_FIELD_STATE_OFF: if (m_nfct_cb.field_on) { - nrf_nfct_task_trigger(NRF_NFCT, NRF_NFCT_TASK_SENSE); - nrf_nfct_int_disable(NRF_NFCT, NRFX_NFCT_RX_INT_MASK | NRFX_NFCT_TX_INT_MASK); + nrfy_nfct_task_trigger(NRF_NFCT, NRF_NFCT_TASK_SENSE); + nrfy_nfct_int_disable(NRF_NFCT, NRFX_NFCT_RX_INT_MASK | NRFX_NFCT_TX_INT_MASK); m_nfct_cb.field_on = false; nfct_evt.evt_id = NRFX_NFCT_EVT_FIELD_LOST; /* Begin: Workaround for anomaly 218 */ - nrfx_nfct_frame_delay_max_set(true); + nfct_frame_delay_max_set(true); /* End: Workaround for anomaly 218 */ NRFX_NFCT_CB_HANDLE(m_nfct_cb.config.cb, nfct_evt); @@ -252,7 +275,7 @@ static void nrfx_nfct_field_event_handler(volatile nrfx_nfct_field_state_t field #if NRFX_CHECK(NFCT_WORKAROUND_USES_TIMER) #if NRFX_CHECK(USE_WORKAROUND_FOR_ANOMALY_190) -static void nrfx_nfct_activate_check(void) +static void nfct_activate_check(void) { static bool is_field_validation_pending = false; @@ -262,13 +285,13 @@ static void nrfx_nfct_activate_check(void) m_timer_workaround.fieldevents_filter_active = false; // Check the field status and take action if field is lost. - nrfx_nfct_field_event_handler(NRFX_NFC_FIELD_STATE_UNKNOWN); + nfct_field_event_handler(NRFX_NFC_FIELD_STATE_UNKNOWN); return; } if ((m_timer_workaround.is_hfclk_on) && (m_timer_workaround.is_delayed)) { - nrf_nfct_task_trigger(NRF_NFCT, NRF_NFCT_TASK_ACTIVATE); + nrfy_nfct_task_trigger(NRF_NFCT, NRF_NFCT_TASK_ACTIVATE); is_field_validation_pending = true; // Start the timer second time to validate whether the tag has locked to the field. @@ -280,21 +303,12 @@ static void nrfx_nfct_activate_check(void) #if NRFX_CHECK(USE_WORKAROUND_FOR_ANOMALY_79) /* Begin: Workaround for anomaly 116 */ -static inline void nrfx_nfct_reset(void) +static inline void nfct_reset(void) { - uint32_t fdmax; - uint32_t fdmin; - uint32_t int_enabled; - uint8_t nfcid1[NRF_NFCT_SENSRES_NFCID1_SIZE_TRIPLE]; - nrf_nfct_sensres_nfcid1_size_t nfcid1_size; - nrf_nfct_selres_protocol_t protocol; + nrfy_nfct_parameters_t nfct_params; // Save parameter settings before the reset of the NFCT peripheral. - fdmax = nrf_nfct_frame_delay_max_get(NRF_NFCT); - fdmin = nrf_nfct_frame_delay_min_get(NRF_NFCT); - nfcid1_size = nrf_nfct_nfcid1_get(NRF_NFCT, nfcid1); - protocol = nrf_nfct_selres_protocol_get(NRF_NFCT); - int_enabled = nrf_nfct_int_enable_get(NRF_NFCT); + nrfy_nfct_parameters_save(NRF_NFCT, &nfct_params); // Reset the NFCT peripheral. *(volatile uint32_t *)0x40005FFC = 0; @@ -302,25 +316,22 @@ static inline void nrfx_nfct_reset(void) *(volatile uint32_t *)0x40005FFC = 1; // Restore parameter settings after the reset of the NFCT peripheral. - nrf_nfct_frame_delay_max_set(NRF_NFCT, fdmax); - nrf_nfct_frame_delay_min_set(NRF_NFCT, fdmin); - nrf_nfct_nfcid1_set(NRF_NFCT, nfcid1, nfcid1_size); - nrf_nfct_selres_protocol_set(NRF_NFCT, protocol); + nrfy_nfct_parameters_restore(NRF_NFCT, &nfct_params); // Restore general HW configuration. - nrfx_nfct_hw_init_setup(); + nfct_hw_init_setup(); // Restore interrupts. - nrf_nfct_int_enable(NRF_NFCT, int_enabled); + nrfy_nfct_int_enable(NRF_NFCT, nfct_params.int_enabled); // Disable interrupts associated with data exchange. - nrf_nfct_int_disable(NRF_NFCT, NRFX_NFCT_RX_INT_MASK | NRFX_NFCT_TX_INT_MASK); + nrfy_nfct_int_disable(NRF_NFCT, NRFX_NFCT_RX_INT_MASK | NRFX_NFCT_TX_INT_MASK); NRFX_LOG_INFO("Reinitialize"); } /* End: Workaround for anomaly 116 */ -static void nrfx_nfct_field_poll(void) +static void nfct_field_poll(void) { if (!nrfx_nfct_field_check()) { @@ -334,11 +345,11 @@ static void nrfx_nfct_field_poll(void) nrfx_timer_disable(&m_timer_workaround.timer); m_nfct_cb.field_on = false; - nrfx_nfct_frame_delay_max_set(true); + nfct_frame_delay_max_set(true); /* Begin: Workaround for anomaly 116 */ /* resume the NFCT to initialized state */ - nrfx_nfct_reset(); + nfct_reset(); /* End: Workaround for anomaly 116 */ NRFX_NFCT_CB_HANDLE(m_nfct_cb.config.cb, nfct_evt); @@ -350,7 +361,7 @@ static void nrfx_nfct_field_poll(void) } #endif // NRFX_CHECK(USE_WORKAROUND_FOR_ANOMALY_79) -static void nrfx_nfct_field_timer_handler(nrf_timer_event_t event_type, void * p_context) +static void nfct_field_timer_handler(nrf_timer_event_t event_type, void * p_context) { (void)p_context; @@ -363,21 +374,21 @@ static void nrfx_nfct_field_timer_handler(nrf_timer_event_t event_type, void * p m_timer_workaround.is_delayed = true; nrfx_timer_disable(&m_timer_workaround.timer); - nrfx_nfct_activate_check(); + nfct_activate_check(); #elif NRFX_CHECK(USE_WORKAROUND_FOR_ANOMALY_79) - nrfx_nfct_field_poll(); + nfct_field_poll(); #endif // NRFX_CHECK(USE_WORKAROUND_FOR_ANOMALY_190) } -static inline nrfx_err_t nrfx_nfct_field_timer_config(void) +static inline nrfx_err_t nfct_field_timer_config(uint8_t irq_priority) { nrfx_err_t err_code; nrfx_timer_config_t timer_cfg = NRFX_TIMER_DEFAULT_CONFIG(FIELD_TIMER_FREQUENCY_HZ); - timer_cfg.interrupt_priority = NRFX_NFCT_DEFAULT_CONFIG_IRQ_PRIORITY; + timer_cfg.interrupt_priority = irq_priority; err_code = nrfx_timer_init(&m_timer_workaround.timer, &timer_cfg, - nrfx_nfct_field_timer_handler); + nfct_field_timer_handler); if (err_code != NRFX_SUCCESS) { return err_code; @@ -394,7 +405,7 @@ static inline nrfx_err_t nrfx_nfct_field_timer_config(void) #endif // NRFX_CHECK(NFCT_WORKAROUND_USES_TIMER) static inline -nrf_nfct_sensres_nfcid1_size_t nrf_nfct_nfcid1_size_to_sensres_size(uint8_t nfcid1_size) +nrf_nfct_sensres_nfcid1_size_t nfct_nfcid1_size_to_sensres_size(uint8_t nfcid1_size) { switch (nfcid1_size) { @@ -414,7 +425,22 @@ nrf_nfct_sensres_nfcid1_size_t nrf_nfct_nfcid1_size_to_sensres_size(uint8_t nfci static inline void nrfx_nfct_rxtx_int_enable(uint32_t rxtx_int_mask) { - nrf_nfct_int_enable(NRF_NFCT, rxtx_int_mask & m_nfct_cb.config.rxtx_int_mask); + nrfy_nfct_int_enable(NRF_NFCT, rxtx_int_mask & m_nfct_cb.config.rxtx_int_mask); +} + +static void nfct_stop_tx(void) +{ +#if NRF_NFCT_HAS_STOPTX_TASK + nrfy_nfct_task_trigger(NRF_NFCT, NRF_NFCT_TASK_STOPTX); +#else +#if defined(NRF52_SERIES) + *(volatile uint32_t *)0x40005010 = 0x01; +#elif defined(NRF5340_XXAA_APPLICATION) && defined(NRF_TRUSTZONE_NONSECURE) + *(volatile uint32_t *)0x4002D010 = 0x01; +#elif defined(NRF5340_XXAA_APPLICATION) + *(volatile uint32_t *)0x5002D010 = 0x01; +#endif +#endif // NRF_NFCT_HAS_STOPTX_TASK } nrfx_err_t nrfx_nfct_init(nrfx_nfct_config_t const * p_config) @@ -428,17 +454,26 @@ nrfx_err_t nrfx_nfct_init(nrfx_nfct_config_t const * p_config) return NRFX_ERROR_INVALID_STATE; } + nfct_trims_apply(); + +#if NRFY_NFCT_HAS_PAD_CONFIG_REG + /* Make sure that NFC pads are configured as NFCT antenna pins. */ + if (!nrfy_nfct_pad_config_enable_check(NRF_NFCT)) + { + NRFX_LOG_ERROR("NFCT pads are not configured as NFCT antenna pins"); + return NRFX_ERROR_FORBIDDEN; + } +#endif + m_nfct_cb.config = *p_config; - nrfx_nfct_hw_init_setup(); + nfct_hw_init_setup(); - NRFX_IRQ_PENDING_CLEAR(NFCT_IRQn); - NRFX_IRQ_PRIORITY_SET(NFCT_IRQn, NRFX_NFCT_DEFAULT_CONFIG_IRQ_PRIORITY); - NRFX_IRQ_ENABLE(NFCT_IRQn); + nrfy_nfct_int_init(NRF_NFCT, 0, p_config->irq_priority, false); #if NRFX_CHECK(NFCT_WORKAROUND_USES_TIMER) /* Initialize Timer module as the workaround for NFCT HW issues. */ - err_code = nrfx_nfct_field_timer_config(); -#endif // NRFX_CHECK(NFCT_WORKAROUND_USES_TIMER) + err_code = nfct_field_timer_config(p_config->irq_priority); +#endif m_nfct_cb.state = NRFX_DRV_STATE_INITIALIZED; m_nfct_cb.frame_delay_max = NFCT_FRAMEDELAYMAX_DEFAULT; @@ -452,43 +487,41 @@ void nrfx_nfct_uninit(void) { nrfx_nfct_disable(); - NRFX_IRQ_DISABLE(NFCT_IRQn); - NRFX_IRQ_PENDING_CLEAR(NFCT_IRQn); + nrfy_nfct_int_uninit(NRF_NFCT); #if NRFX_CHECK(NFCT_WORKAROUND_USES_TIMER) /* De-initialize Timer module as the workaround for NFCT HW issues. */ nrfx_timer_uninit(&m_timer_workaround.timer); -#endif // NRFX_CHECK(NFCT_WORKAROUND_USES_TIMER) +#endif m_nfct_cb.state = NRFX_DRV_STATE_UNINITIALIZED; } void nrfx_nfct_enable(void) { - nrf_nfct_error_status_clear(NRF_NFCT, NRFX_NFCT_ERROR_STATUS_ALL_MASK); - nrf_nfct_task_trigger(NRF_NFCT, NRF_NFCT_TASK_SENSE); + nrfy_nfct_error_status_clear(NRF_NFCT, NRFX_NFCT_ERROR_STATUS_ALL_MASK); + nrfy_nfct_task_trigger(NRF_NFCT, NRF_NFCT_TASK_SENSE); - nrf_nfct_int_enable(NRF_NFCT, NRF_NFCT_INT_FIELDDETECTED_MASK | - NRF_NFCT_INT_ERROR_MASK | - NRF_NFCT_INT_SELECTED_MASK); -#if !NRFX_CHECK(USE_WORKAROUND_FOR_ANOMALY_79) - nrf_nfct_int_enable(NRF_NFCT, NRF_NFCT_INT_FIELDLOST_MASK); -#endif // !NRFX_CHECK(USE_WORKAROUND_FOR_ANOMALY_79) + nrfy_nfct_int_enable(NRF_NFCT, NRF_NFCT_INT_FIELDDETECTED_MASK | + NRF_NFCT_INT_ERROR_MASK | + NRF_NFCT_INT_SELECTED_MASK | + (NRFX_IS_ENABLED(USE_WORKAROUND_FOR_ANOMALY_79) ? + 0 : NRF_NFCT_INT_FIELDLOST_MASK)); NRFX_LOG_INFO("Start"); } void nrfx_nfct_disable(void) { - nrf_nfct_int_disable(NRF_NFCT, NRF_NFCT_DISABLE_ALL_INT); - nrf_nfct_task_trigger(NRF_NFCT, NRF_NFCT_TASK_DISABLE); + nrfy_nfct_int_disable(NRF_NFCT, NRF_NFCT_DISABLE_ALL_INT); + nrfy_nfct_task_trigger(NRF_NFCT, NRF_NFCT_TASK_DISABLE); NRFX_LOG_INFO("Stop"); } bool nrfx_nfct_field_check(void) { - uint32_t const field_state = nrf_nfct_field_status_get(NRF_NFCT); + uint32_t const field_state = nrfy_nfct_field_status_get(NRF_NFCT); if (((field_state & NRF_NFCT_FIELD_STATE_PRESENT_MASK) == 0) && ((field_state & NRF_NFCT_FIELD_STATE_LOCK_MASK) == 0)) @@ -500,14 +533,29 @@ bool nrfx_nfct_field_check(void) return true; } -void nrfx_nfct_rx(nrfx_nfct_data_desc_t const * p_tx_data) +nrfx_err_t nrfx_nfct_rx(nrfx_nfct_data_desc_t const * p_rx_data) { - NRFX_ASSERT(p_tx_data); + nrfx_err_t err; - nrf_nfct_rxtx_buffer_set(NRF_NFCT, (uint8_t *) p_tx_data->p_data, p_tx_data->data_size); + NRFX_ASSERT(p_rx_data); + + // EasyDMA requires that transfer buffers are placed in DataRAM, + // signal error if they are not. + if (!nrf_dma_accessible_check(NRF_NFCT, p_rx_data->p_data)) + { + err = NRFX_ERROR_INVALID_ADDR; + NRFX_LOG_WARNING("Function: %s, error code: %s.", + __func__, + NRFX_LOG_ERROR_STRING_GET(err)); + return err; + } + + nrfy_nfct_rxtx_buffer_set(NRF_NFCT, (uint8_t *)p_rx_data->p_data, p_rx_data->data_size, true); nrfx_nfct_rxtx_int_enable(NRFX_NFCT_RX_INT_MASK); - nrf_nfct_task_trigger(NRF_NFCT, NRF_NFCT_TASK_ENABLERXDATA); + nrfy_nfct_task_trigger(NRF_NFCT, NRF_NFCT_TASK_ENABLERXDATA); + + return NRFX_SUCCESS; } nrfx_err_t nrfx_nfct_tx(nrfx_nfct_data_desc_t const * p_tx_data, @@ -523,30 +571,40 @@ nrfx_err_t nrfx_nfct_tx(nrfx_nfct_data_desc_t const * p_tx_data, return NRFX_ERROR_INVALID_LENGTH; } + // EasyDMA requires that transfer buffers are placed in DataRAM, + // signal error if they are not. + if (!nrf_dma_accessible_check(NRF_NFCT, p_tx_data->p_data)) + { + err = NRFX_ERROR_INVALID_ADDR; + NRFX_LOG_WARNING("Function: %s, error code: %s.", + __func__, + NRFX_LOG_ERROR_STRING_GET(err)); + return err; + } + NRFX_CRITICAL_SECTION_ENTER(); /* In case when NFC frame transmission has already started, it returns an error. */ - if (NRFX_NFCT_EVT_ACTIVE(TXFRAMESTART)) + if (nrfy_nfct_event_check(NRF_NFCT, NRF_NFCT_EVENT_TXFRAMESTART) && + nrfy_nfct_int_enable_check(NRF_NFCT, NRF_NFCT_INT_TXFRAMESTART_MASK)) { err = NRFX_ERROR_BUSY; } else { /* In case when Tx operation was scheduled with delay, stop scheduled Tx operation. */ -#if defined(NRF52_SERIES) - *(volatile uint32_t *)0x40005010 = 0x01; -#elif defined(NRF5340_XXAA_APPLICATION) && defined(NRF_TRUSTZONE_NONSECURE) - *(volatile uint32_t *)0x4002D010 = 0x01; -#elif defined(NRF5340_XXAA_APPLICATION) - *(volatile uint32_t *)0x5002D010 = 0x01; -#endif - nrf_nfct_rxtx_buffer_set(NRF_NFCT, (uint8_t *) p_tx_data->p_data, p_tx_data->data_size); - nrf_nfct_tx_bits_set(NRF_NFCT, NRFX_NFCT_BYTES_TO_BITS(p_tx_data->data_size)); - nrf_nfct_frame_delay_mode_set(NRF_NFCT, (nrf_nfct_frame_delay_mode_t) delay_mode); - nrfx_nfct_frame_delay_max_set(false); + nfct_stop_tx(); + + nrfy_nfct_rxtx_buffer_set(NRF_NFCT, + (uint8_t *)p_tx_data->p_data, + p_tx_data->data_size, + false); + nrfy_nfct_tx_bits_set(NRF_NFCT, NRFX_NFCT_BYTES_TO_BITS(p_tx_data->data_size)); + nrfy_nfct_frame_delay_mode_set(NRF_NFCT, (nrf_nfct_frame_delay_mode_t) delay_mode); + nfct_frame_delay_max_set(false); nrfx_nfct_rxtx_int_enable(NRFX_NFCT_TX_INT_MASK); - nrf_nfct_task_trigger(NRF_NFCT, NRF_NFCT_TASK_STARTTX); + nrfy_nfct_task_trigger(NRF_NFCT, NRF_NFCT_TASK_STARTTX); } NRFX_CRITICAL_SECTION_EXIT(); @@ -572,6 +630,17 @@ nrfx_err_t nrfx_nfct_bits_tx(nrfx_nfct_data_desc_t const * p_tx_data, return NRFX_ERROR_INVALID_LENGTH; } + // EasyDMA requires that transfer buffers are placed in DataRAM, + // signal error if they are not. + if (!nrf_dma_accessible_check(NRF_NFCT, p_tx_data->p_data)) + { + err = NRFX_ERROR_INVALID_ADDR; + NRFX_LOG_WARNING("Function: %s, error code: %s.", + __func__, + NRFX_LOG_ERROR_STRING_GET(err)); + return err; + } + /* Get buffer length, add additional byte if bits go beyond last whole byte */ uint32_t buffer_length = NRFX_NFCT_BITS_TO_BYTES(p_tx_data->data_size); if (p_tx_data->data_size & NFCT_TXD_AMOUNT_TXDATABITS_Msk) @@ -582,27 +651,23 @@ nrfx_err_t nrfx_nfct_bits_tx(nrfx_nfct_data_desc_t const * p_tx_data, NRFX_CRITICAL_SECTION_ENTER(); /* In case when NFC frame transmission has already started, it returns an error. */ - if (NRFX_NFCT_EVT_ACTIVE(TXFRAMESTART)) + if (nrfy_nfct_event_check(NRF_NFCT, NRF_NFCT_EVENT_TXFRAMESTART) && + nrfy_nfct_int_enable_check(NRF_NFCT, NRF_NFCT_INT_TXFRAMESTART_MASK)) { err = NRFX_ERROR_BUSY; } else { /* In case when Tx operation was scheduled with delay, stop scheduled Tx operation. */ -#if defined(NRF52_SERIES) - *(volatile uint32_t *)0x40005010 = 0x01; -#elif defined(NRF5340_XXAA_APPLICATION) && defined(NRF_TRUSTZONE_NONSECURE) - *(volatile uint32_t *)0x4002D010 = 0x01; -#elif defined(NRF5340_XXAA_APPLICATION) - *(volatile uint32_t *)0x5002D010 = 0x01; -#endif - nrf_nfct_rxtx_buffer_set(NRF_NFCT, (uint8_t *) p_tx_data->p_data, buffer_length); - nrf_nfct_tx_bits_set(NRF_NFCT, p_tx_data->data_size); - nrf_nfct_frame_delay_mode_set(NRF_NFCT, (nrf_nfct_frame_delay_mode_t) delay_mode); - nrfx_nfct_frame_delay_max_set(false); + nfct_stop_tx(); + + nrfy_nfct_rxtx_buffer_set(NRF_NFCT, (uint8_t *)p_tx_data->p_data, buffer_length, false); + nrfy_nfct_tx_bits_set(NRF_NFCT, p_tx_data->data_size); + nrfy_nfct_frame_delay_mode_set(NRF_NFCT, (nrf_nfct_frame_delay_mode_t) delay_mode); + nfct_frame_delay_max_set(false); nrfx_nfct_rxtx_int_enable(NRFX_NFCT_TX_INT_MASK); - nrf_nfct_task_trigger(NRF_NFCT, NRF_NFCT_TASK_STARTTX); + nrfy_nfct_task_trigger(NRF_NFCT, NRF_NFCT_TASK_STARTTX); } NRFX_CRITICAL_SECTION_EXIT(); @@ -622,11 +687,11 @@ void nrfx_nfct_state_force(nrfx_nfct_state_t state) { m_timer_workaround.is_hfclk_on = true; /* NFCT will be activated based on additional conditions */ - nrfx_nfct_activate_check(); + nfct_activate_check(); return; } #endif // NRFX_CHECK(USE_WORKAROUND_FOR_ANOMALY_190) - nrf_nfct_task_trigger(NRF_NFCT, (nrf_nfct_task_t) state); + nrfy_nfct_task_trigger(NRF_NFCT, (nrf_nfct_task_t) state); } void nrfx_nfct_init_substate_force(nrfx_nfct_active_state_t sub_state) @@ -636,27 +701,27 @@ void nrfx_nfct_init_substate_force(nrfx_nfct_active_state_t sub_state) #if defined(NRF52832_XXAA) || defined(NRF52832_XXAB) if (((*(uint32_t volatile *)(0x40005420)) & 0x1UL) == (1UL)) #else - if (nrf_nfct_sleep_state_get(NRF_NFCT) == NRF_NFCT_SLEEP_STATE_SLEEP_A) + if (nrfy_nfct_sleep_state_get(NRF_NFCT) == NRF_NFCT_SLEEP_STATE_SLEEP_A) #endif //defined(NRF52832_XXAA) || defined(NRF52832_XXAB) { // Default state is SLEEP_A - nrf_nfct_task_trigger(NRF_NFCT, NRF_NFCT_TASK_GOSLEEP); + nrfy_nfct_task_trigger(NRF_NFCT, NRF_NFCT_TASK_GOSLEEP); } else { // Default state is IDLE - nrf_nfct_task_trigger(NRF_NFCT, NRF_NFCT_TASK_GOIDLE); + nrfy_nfct_task_trigger(NRF_NFCT, NRF_NFCT_TASK_GOIDLE); } } else { - nrf_nfct_task_trigger(NRF_NFCT, (nrf_nfct_task_t) sub_state); + nrfy_nfct_task_trigger(NRF_NFCT, (nrf_nfct_task_t) sub_state); } - nrfx_nfct_frame_delay_max_set(true); + nfct_frame_delay_max_set(true); /* Disable TX/RX here (will be enabled at SELECTED) */ - nrf_nfct_int_disable(NRF_NFCT, NRFX_NFCT_RX_INT_MASK | NRFX_NFCT_TX_INT_MASK); + nrfy_nfct_int_disable(NRF_NFCT, NRFX_NFCT_RX_INT_MASK | NRFX_NFCT_TX_INT_MASK); } nrfx_err_t nrfx_nfct_parameter_set(nrfx_nfct_param_t const * p_param) @@ -694,7 +759,7 @@ nrfx_err_t nrfx_nfct_parameter_set(nrfx_nfct_param_t const * p_param) } m_nfct_cb.frame_delay_min = delay_min; - nrf_nfct_frame_delay_min_set(NRF_NFCT, m_nfct_cb.frame_delay_min); + nrfy_nfct_frame_delay_min_set(NRF_NFCT, m_nfct_cb.frame_delay_min); break; } @@ -704,7 +769,7 @@ nrfx_err_t nrfx_nfct_parameter_set(nrfx_nfct_param_t const * p_param) return NRFX_ERROR_INVALID_PARAM; } - nrf_nfct_selres_protocol_set(NRF_NFCT, + nrfy_nfct_selres_protocol_set(NRF_NFCT, (nrf_nfct_selres_protocol_t) p_param->data.sel_res_protocol); break; @@ -712,8 +777,8 @@ nrfx_err_t nrfx_nfct_parameter_set(nrfx_nfct_param_t const * p_param) { nrf_nfct_sensres_nfcid1_size_t id_size_mask; - id_size_mask = nrf_nfct_nfcid1_size_to_sensres_size(p_param->data.nfcid1.id_size); - nrf_nfct_nfcid1_set(NRF_NFCT, p_param->data.nfcid1.p_id, id_size_mask); + id_size_mask = nfct_nfcid1_size_to_sensres_size(p_param->data.nfcid1.id_size); + nrfy_nfct_nfcid1_set(NRF_NFCT, p_param->data.nfcid1.p_id, id_size_mask); break; } @@ -727,6 +792,8 @@ nrfx_err_t nrfx_nfct_parameter_set(nrfx_nfct_param_t const * p_param) nrfx_err_t nrfx_nfct_nfcid1_default_bytes_get(uint8_t * const p_nfcid1_buff, uint32_t nfcid1_buff_len) { + uint32_t tag_header[3]; + if ((nfcid1_buff_len != NRFX_NFCT_NFCID1_SINGLE_SIZE) && (nfcid1_buff_len != NRFX_NFCT_NFCID1_DOUBLE_SIZE) && (nfcid1_buff_len != NRFX_NFCT_NFCID1_TRIPLE_SIZE)) @@ -734,32 +801,34 @@ nrfx_err_t nrfx_nfct_nfcid1_default_bytes_get(uint8_t * const p_nfcid1_buff, return NRFX_ERROR_INVALID_LENGTH; } -#if defined(FICR_NFC_TAGHEADER0_MFGID_Msk) && !defined(NRF_TRUSTZONE_NONSECURE) - uint32_t nfc_tag_header0 = NRF_FICR->NFC.TAGHEADER0; - uint32_t nfc_tag_header1 = NRF_FICR->NFC.TAGHEADER1; - uint32_t nfc_tag_header2 = NRF_FICR->NFC.TAGHEADER2; +#if (NRF_FICR_HAS_NFC_TAGHEADER || NRF_FICR_HAS_NFC_TAGHEADER_ARRAY) && \ + !defined(NRF_TRUSTZONE_NONSECURE) + tag_header[0] = nrf_ficr_nfc_tagheader_get(NRF_FICR, 0); + tag_header[1] = nrf_ficr_nfc_tagheader_get(NRF_FICR, 1); + tag_header[2] = nrf_ficr_nfc_tagheader_get(NRF_FICR, 2); #else - uint32_t nfc_tag_header0 = 0x5F; - uint32_t nfc_tag_header1 = 0; - uint32_t nfc_tag_header2 = 0; + /* IC manufacturer ID byte, set to Nordic Semiconductor value. */ + tag_header[0] = 0x5F; + tag_header[1] = 0; + tag_header[2] = 0; #endif - p_nfcid1_buff[0] = (uint8_t) (nfc_tag_header0 >> 0); - p_nfcid1_buff[1] = (uint8_t) (nfc_tag_header0 >> 8); - p_nfcid1_buff[2] = (uint8_t) (nfc_tag_header0 >> 16); - p_nfcid1_buff[3] = (uint8_t) (nfc_tag_header1 >> 0); + p_nfcid1_buff[0] = (uint8_t) (tag_header[0] >> 0); + p_nfcid1_buff[1] = (uint8_t) (tag_header[0] >> 8); + p_nfcid1_buff[2] = (uint8_t) (tag_header[0] >> 16); + p_nfcid1_buff[3] = (uint8_t) (tag_header[1] >> 0); if (nfcid1_buff_len != NRFX_NFCT_NFCID1_SINGLE_SIZE) { - p_nfcid1_buff[4] = (uint8_t) (nfc_tag_header1 >> 8); - p_nfcid1_buff[5] = (uint8_t) (nfc_tag_header1 >> 16); - p_nfcid1_buff[6] = (uint8_t) (nfc_tag_header1 >> 24); + p_nfcid1_buff[4] = (uint8_t) (tag_header[1] >> 8); + p_nfcid1_buff[5] = (uint8_t) (tag_header[1] >> 16); + p_nfcid1_buff[6] = (uint8_t) (tag_header[1] >> 24); if (nfcid1_buff_len == NRFX_NFCT_NFCID1_TRIPLE_SIZE) { - p_nfcid1_buff[7] = (uint8_t) (nfc_tag_header2 >> 0); - p_nfcid1_buff[8] = (uint8_t) (nfc_tag_header2 >> 8); - p_nfcid1_buff[9] = (uint8_t) (nfc_tag_header2 >> 16); + p_nfcid1_buff[7] = (uint8_t) (tag_header[2] >> 0); + p_nfcid1_buff[8] = (uint8_t) (tag_header[2] >> 8); + p_nfcid1_buff[9] = (uint8_t) (tag_header[2] >> 16); } /* Begin: Workaround for anomaly 181. */ /* Workaround for wrong value in NFCID1. Value 0x88 cannot be used as byte 3 @@ -779,7 +848,7 @@ void nrfx_nfct_autocolres_enable(void) #if defined(NRF52832_XXAA) || defined(NRF52832_XXAB) (*(uint32_t *)(0x4000559C)) &= (~(0x1UL)); #else - nrf_nfct_autocolres_enable(NRF_NFCT); + nrfy_nfct_autocolres_enable(NRF_NFCT); #endif //defined(NRF52832_XXAA) || defined(NRF52832_XXAB) } @@ -788,26 +857,36 @@ void nrfx_nfct_autocolres_disable(void) #if defined(NRF52832_XXAA) || defined(NRF52832_XXAB) (*(uint32_t *)(0x4000559C)) |= (0x1UL); #else - nrf_nfct_autocolres_disable(NRF_NFCT); + nrfy_nfct_autocolres_disable(NRF_NFCT); #endif //defined(NRF52832_XXAA) || defined(NRF52832_XXAB) } void nrfx_nfct_irq_handler(void) { nrfx_nfct_field_state_t current_field = NRFX_NFC_FIELD_STATE_NONE; - - if (NRFX_NFCT_EVT_ACTIVE(FIELDDETECTED)) + uint32_t evt_mask = nrfy_nfct_events_process(NRF_NFCT, + NRFY_EVENT_TO_INT_BITMASK(NRF_NFCT_EVENT_FIELDDETECTED) | + (NRFX_IS_ENABLED(USE_WORKAROUND_FOR_ANOMALY_79) ? 0 : + NRFY_EVENT_TO_INT_BITMASK(NRF_NFCT_EVENT_FIELDLOST)) | + NRFY_EVENT_TO_INT_BITMASK(NRF_NFCT_EVENT_FIELDLOST) | + NRFY_EVENT_TO_INT_BITMASK(NRF_NFCT_EVENT_RXFRAMESTART) | + NRFY_EVENT_TO_INT_BITMASK(NRF_NFCT_EVENT_RXFRAMEEND) | + NRFY_EVENT_TO_INT_BITMASK(NRF_NFCT_EVENT_RXERROR) | + NRFY_EVENT_TO_INT_BITMASK(NRF_NFCT_EVENT_SELECTED) | + NRFY_EVENT_TO_INT_BITMASK(NRF_NFCT_EVENT_ERROR) | + NRFY_EVENT_TO_INT_BITMASK(NRF_NFCT_EVENT_TXFRAMESTART) | + NRFY_EVENT_TO_INT_BITMASK(NRF_NFCT_EVENT_TXFRAMEEND)); + + if (NRFX_NFCT_EVT_ACTIVE(FIELDDETECTED, evt_mask)) { - nrf_nfct_event_clear(NRF_NFCT, NRF_NFCT_EVENT_FIELDDETECTED); current_field = NRFX_NFC_FIELD_STATE_ON; NRFX_LOG_DEBUG("Field detected"); } #if !NRFX_CHECK(USE_WORKAROUND_FOR_ANOMALY_79) - if (NRFX_NFCT_EVT_ACTIVE(FIELDLOST)) + if (NRFX_NFCT_EVT_ACTIVE(FIELDLOST, evt_mask)) { - nrf_nfct_event_clear(NRF_NFCT, NRF_NFCT_EVENT_FIELDLOST); current_field = (current_field == NRFX_NFC_FIELD_STATE_NONE) ? NRFX_NFC_FIELD_STATE_OFF : NRFX_NFC_FIELD_STATE_UNKNOWN; @@ -818,13 +897,11 @@ void nrfx_nfct_irq_handler(void) /* Perform actions if any FIELD event is active */ if (current_field != NRFX_NFC_FIELD_STATE_NONE) { - nrfx_nfct_field_event_handler(current_field); + nfct_field_event_handler(current_field); } - if (NRFX_NFCT_EVT_ACTIVE(RXFRAMESTART)) + if (NRFX_NFCT_EVT_ACTIVE(RXFRAMESTART, evt_mask)) { - nrf_nfct_event_clear(NRF_NFCT, NRF_NFCT_EVENT_RXFRAMESTART); - nrfx_nfct_evt_t nfct_evt = { .evt_id = NRFX_NFCT_EVT_RX_FRAMESTART @@ -833,10 +910,8 @@ void nrfx_nfct_irq_handler(void) NRFX_NFCT_CB_HANDLE(m_nfct_cb.config.cb, nfct_evt); } - if (NRFX_NFCT_EVT_ACTIVE(RXFRAMEEND)) + if (NRFX_NFCT_EVT_ACTIVE(RXFRAMEEND, evt_mask)) { - nrf_nfct_event_clear(NRF_NFCT, NRF_NFCT_EVENT_RXFRAMEEND); - nrfx_nfct_evt_t nfct_evt = { .evt_id = NRFX_NFCT_EVT_RX_FRAMEEND @@ -844,20 +919,19 @@ void nrfx_nfct_irq_handler(void) /* Take into account only the number of whole bytes. */ nfct_evt.params.rx_frameend.rx_status = 0; - nfct_evt.params.rx_frameend.rx_data.p_data = nrf_nfct_rxtx_buffer_get(NRF_NFCT); + nfct_evt.params.rx_frameend.rx_data.p_data = nrfy_nfct_rxtx_buffer_get(NRF_NFCT); nfct_evt.params.rx_frameend.rx_data.data_size = - NRFX_NFCT_BITS_TO_BYTES(nrf_nfct_rx_bits_get(NRF_NFCT, true)); + NRFX_NFCT_BITS_TO_BYTES(nrfy_nfct_rx_bits_get(NRF_NFCT, true)); - if (NRFX_NFCT_EVT_ACTIVE(RXERROR)) + if (NRFX_NFCT_EVT_ACTIVE(RXERROR, evt_mask)) { nfct_evt.params.rx_frameend.rx_status = - (nrf_nfct_rx_frame_status_get(NRF_NFCT) & NRFX_NFCT_FRAME_STATUS_RX_ALL_MASK); - nrf_nfct_event_clear(NRF_NFCT, NRF_NFCT_EVENT_RXERROR); + (nrfy_nfct_rx_frame_status_get(NRF_NFCT) & NRFX_NFCT_FRAME_STATUS_RX_ALL_MASK); NRFX_LOG_DEBUG("Rx error (0x%x)", (unsigned int) nfct_evt.params.rx_frameend.rx_status); /* Clear rx frame status */ - nrf_nfct_rx_frame_status_clear(NRF_NFCT, NRFX_NFCT_FRAME_STATUS_RX_ALL_MASK); + nrfy_nfct_rx_frame_status_clear(NRF_NFCT, NRFX_NFCT_FRAME_STATUS_RX_ALL_MASK); } NRFX_NFCT_CB_HANDLE(m_nfct_cb.config.cb, nfct_evt); @@ -865,21 +939,20 @@ void nrfx_nfct_irq_handler(void) NRFX_LOG_DEBUG("Rx fend"); } - if (NRFX_NFCT_EVT_ACTIVE(SELECTED)) + if (NRFX_NFCT_EVT_ACTIVE(SELECTED, evt_mask)) { - nrf_nfct_event_clear(NRF_NFCT, NRF_NFCT_EVENT_SELECTED); /* Clear also RX END and RXERROR events because SW does not take care of commands that were received before selecting the tag. */ - nrf_nfct_event_clear(NRF_NFCT, NRF_NFCT_EVENT_RXFRAMEEND); - nrf_nfct_event_clear(NRF_NFCT, NRF_NFCT_EVENT_RXERROR); - nrf_nfct_event_clear(NRF_NFCT, NRF_NFCT_EVENT_TXFRAMESTART); - nrf_nfct_event_clear(NRF_NFCT, NRF_NFCT_EVENT_TXFRAMEEND); + nrfy_nfct_event_clear(NRF_NFCT, NRF_NFCT_EVENT_RXFRAMEEND); + nrfy_nfct_event_clear(NRF_NFCT, NRF_NFCT_EVENT_RXERROR); + nrfy_nfct_event_clear(NRF_NFCT, NRF_NFCT_EVENT_TXFRAMESTART); + nrfy_nfct_event_clear(NRF_NFCT, NRF_NFCT_EVENT_TXFRAMEEND); - nrfx_nfct_frame_delay_max_set(false); + nfct_frame_delay_max_set(false); /* At this point any previous error status can be ignored. */ - nrf_nfct_rx_frame_status_clear(NRF_NFCT, NRFX_NFCT_FRAME_STATUS_RX_ALL_MASK); - nrf_nfct_error_status_clear(NRF_NFCT, NRFX_NFCT_ERROR_STATUS_ALL_MASK); + nrfy_nfct_rx_frame_status_clear(NRF_NFCT, NRFX_NFCT_FRAME_STATUS_RX_ALL_MASK); + nrfy_nfct_error_status_clear(NRF_NFCT, NRFX_NFCT_ERROR_STATUS_ALL_MASK); nrfx_nfct_evt_t nfct_evt = { @@ -890,10 +963,9 @@ void nrfx_nfct_irq_handler(void) NRFX_LOG_DEBUG("Selected"); } - if (NRFX_NFCT_EVT_ACTIVE(ERROR)) + if (NRFX_NFCT_EVT_ACTIVE(ERROR, evt_mask)) { - uint32_t err_status = nrf_nfct_error_status_get(NRF_NFCT); - nrf_nfct_event_clear(NRF_NFCT, NRF_NFCT_EVENT_ERROR); + uint32_t err_status = nrfy_nfct_error_status_get(NRF_NFCT); nrfx_nfct_evt_t nfct_evt = { @@ -903,7 +975,7 @@ void nrfx_nfct_irq_handler(void) /* Clear FRAMEDELAYTIMEOUT error (expected HW behaviour) when SLP_REQ command was received. */ if (err_status & NRF_NFCT_ERROR_FRAMEDELAYTIMEOUT_MASK) { - nrf_nfct_error_status_clear(NRF_NFCT, NRF_NFCT_ERROR_FRAMEDELAYTIMEOUT_MASK); + nrfy_nfct_error_status_clear(NRF_NFCT, NRF_NFCT_ERROR_FRAMEDELAYTIMEOUT_MASK); nfct_evt.params.error.reason = NRFX_NFCT_ERROR_FRAMEDELAYTIMEOUT; NRFX_NFCT_CB_HANDLE(m_nfct_cb.config.cb, nfct_evt); @@ -917,37 +989,33 @@ void nrfx_nfct_irq_handler(void) } /* Clear error status. */ - nrf_nfct_error_status_clear(NRF_NFCT, NRFX_NFCT_ERROR_STATUS_ALL_MASK); + nrfy_nfct_error_status_clear(NRF_NFCT, NRFX_NFCT_ERROR_STATUS_ALL_MASK); } - if (NRFX_NFCT_EVT_ACTIVE(TXFRAMESTART)) + if (NRFX_NFCT_EVT_ACTIVE(TXFRAMESTART, evt_mask)) { - nrf_nfct_event_clear(NRF_NFCT, NRF_NFCT_EVENT_TXFRAMESTART); - if (m_nfct_cb.config.cb != NULL) { nrfx_nfct_evt_t nfct_evt; nfct_evt.evt_id = NRFX_NFCT_EVT_TX_FRAMESTART; - nfct_evt.params.tx_framestart.tx_data.p_data = nrf_nfct_rxtx_buffer_get(NRF_NFCT); + nfct_evt.params.tx_framestart.tx_data.p_data = nrfy_nfct_rxtx_buffer_get(NRF_NFCT); nfct_evt.params.tx_framestart.tx_data.data_size = - NRFX_NFCT_BITS_TO_BYTES(nrf_nfct_tx_bits_get(NRF_NFCT)); + NRFX_NFCT_BITS_TO_BYTES(nrfy_nfct_tx_bits_get(NRF_NFCT)); m_nfct_cb.config.cb(&nfct_evt); } } - if (NRFX_NFCT_EVT_ACTIVE(TXFRAMEEND)) + if (NRFX_NFCT_EVT_ACTIVE(TXFRAMEEND, evt_mask)) { - nrf_nfct_event_clear(NRF_NFCT, NRF_NFCT_EVENT_TXFRAMEEND); - nrfx_nfct_evt_t nfct_evt = { .evt_id = NRFX_NFCT_EVT_TX_FRAMEEND }; /* Ignore any frame transmission until a new TX is scheduled by nrfx_nfct_tx() */ - nrf_nfct_int_disable(NRF_NFCT, NRFX_NFCT_TX_INT_MASK); + nrfy_nfct_int_disable(NRF_NFCT, NRFX_NFCT_TX_INT_MASK); NRFX_NFCT_CB_HANDLE(m_nfct_cb.config.cb, nfct_evt); diff --git a/drivers/src/nrfx_nvmc.c b/drivers/src/nrfx_nvmc.c index 44f39e263..799633fb6 100644 --- a/drivers/src/nrfx_nvmc.c +++ b/drivers/src/nrfx_nvmc.c @@ -246,7 +246,7 @@ static void nvmc_word_write(uint32_t addr, uint32_t value) {} #endif - *(volatile uint32_t *)addr = value; + nrf_nvmc_word_write(addr, value); __DMB(); } @@ -350,7 +350,7 @@ bool nrfx_nvmc_byte_writable_check(uint32_t addr, uint8_t val_to_check) { NRFX_ASSERT(is_valid_address(addr, true)); - uint8_t val_on_addr = *(uint8_t const *)addr; + uint8_t val_on_addr = nrf_nvmc_byte_read(addr); return (val_to_check & val_on_addr) == val_to_check; } @@ -363,7 +363,7 @@ bool nrfx_nvmc_halfword_writable_check(uint32_t addr, uint16_t val_to_check) if ((addr - NVMC_FLASH_BASE_ADDRESS) < flash_total_size_get()) { - val_on_addr = *(uint16_t const *)addr; + val_on_addr = nrf_nvmc_halfword_read(addr); } else { @@ -377,7 +377,7 @@ bool nrfx_nvmc_word_writable_check(uint32_t addr, uint32_t val_to_check) NRFX_ASSERT(is_valid_address(addr, true)); NRFX_ASSERT(nrfx_is_word_aligned((void const *)addr)); - uint32_t val_on_addr = *(uint32_t const *)addr; + uint32_t val_on_addr = nrf_nvmc_word_read(addr); return (val_to_check & val_on_addr) == val_to_check; } @@ -492,7 +492,7 @@ uint16_t nrfx_nvmc_otp_halfword_read(uint32_t addr) NRFX_ASSERT(is_halfword_aligned(addr)); uint32_t aligned_addr = addr & ~(0x03UL); - uint32_t val32 = *(const uint32_t *)aligned_addr; + uint32_t val32 = nrf_nvmc_word_read(aligned_addr); return (nrfx_is_word_aligned((void const *)addr) ? (uint16_t)(val32) : (uint16_t)(val32 >> 16)); diff --git a/drivers/src/nrfx_pwm.c b/drivers/src/nrfx_pwm.c index 399a9fce1..5340dab18 100644 --- a/drivers/src/nrfx_pwm.c +++ b/drivers/src/nrfx_pwm.c @@ -167,6 +167,22 @@ static void pwm_configure(nrfx_pwm_t const * p_instance, nrfx_pwm_config_t const #endif } +static bool pwm_stopped_check(nrfx_pwm_t const * p_instance) +{ + pwm_control_block_t * p_cb = &m_cb[p_instance->instance_id]; + + if (p_cb->handler) + { + return (p_cb->state == NRFX_DRV_STATE_POWERED_ON ? false : true); + } + else + { + return ((p_cb->state != NRFX_DRV_STATE_POWERED_ON) || + (nrfy_pwm_events_process(p_instance->p_reg, + NRFY_EVENT_TO_INT_BITMASK(NRF_PWM_EVENT_STOPPED)))); + } +} + nrfx_err_t nrfx_pwm_init(nrfx_pwm_t const * p_instance, nrfx_pwm_config_t const * p_config, nrfx_pwm_handler_t handler, @@ -290,9 +306,6 @@ static uint32_t start_playback(nrfx_pwm_t const * p_instance, NRF_PWM_INT_SEQEND0_MASK | NRF_PWM_INT_SEQEND1_MASK); } #endif - - nrfy_pwm_event_clear(p_instance->p_reg, NRF_PWM_EVENT_STOPPED); - if (flags & NRFX_PWM_FLAG_START_VIA_TASK) { uint32_t starting_task_address = @@ -423,15 +436,12 @@ bool nrfx_pwm_stop(nrfx_pwm_t const * p_instance, bool wait_until_stopped) if (wait_until_stopped) { - // Either status was already correct or new STOPPED event will appear. - while (!(nrfx_pwm_stopped_check(p_instance) || - nrfy_pwm_events_process(p_instance->p_reg, - NRFY_EVENT_TO_INT_BITMASK(NRF_PWM_EVENT_STOPPED)))) + while (!pwm_stopped_check(p_instance)) {} p_cb->state = NRFX_DRV_STATE_INITIALIZED; } - ret_val = nrfx_pwm_stopped_check(p_instance); + ret_val = pwm_stopped_check(p_instance); NRFX_LOG_INFO("%s returned %d.", __func__, ret_val); return ret_val; @@ -439,15 +449,9 @@ bool nrfx_pwm_stop(nrfx_pwm_t const * p_instance, bool wait_until_stopped) bool nrfx_pwm_stopped_check(nrfx_pwm_t const * p_instance) { - pwm_control_block_t * p_cb = &m_cb[p_instance->instance_id]; - NRFX_ASSERT(p_cb->state != NRFX_DRV_STATE_UNINITIALIZED); + NRFX_ASSERT(m_cb[p_instance->instance_id].state != NRFX_DRV_STATE_UNINITIALIZED); - bool ret_val = false; - - if (p_cb->state != NRFX_DRV_STATE_POWERED_ON) - { - ret_val = true; - } + bool ret_val = pwm_stopped_check(p_instance); NRFX_LOG_INFO("%s returned %d.", __func__, ret_val); return ret_val; diff --git a/drivers/src/nrfx_qdec.c b/drivers/src/nrfx_qdec.c index e89149c7b..c61ca609f 100644 --- a/drivers/src/nrfx_qdec.c +++ b/drivers/src/nrfx_qdec.c @@ -92,13 +92,13 @@ static void qdec_configure(nrfx_qdec_t const * p_instance, }; nrfy_qdec_periph_configure(p_instance->p_reg, &nrfy_config); - nrfy_qdec_shorts_enable(p_instance->p_reg, NRF_QDEC_SHORT_REPORTRDY_READCLRACC_MASK); uint32_t int_mask = NRF_QDEC_INT_ACCOF_MASK; if (p_config->reportper_inten) { int_mask |= NRF_QDEC_INT_REPORTRDY_MASK; + nrfy_qdec_shorts_enable(p_instance->p_reg, NRF_QDEC_SHORT_REPORTRDY_READCLRACC_MASK); } if (p_config->sample_inten) { diff --git a/drivers/src/nrfx_spim.c b/drivers/src/nrfx_spim.c index c92006ea0..0f42ee415 100644 --- a/drivers/src/nrfx_spim.c +++ b/drivers/src/nrfx_spim.c @@ -207,6 +207,7 @@ static void spim_abort(NRF_SPIM_Type * p_spim, spim_control_block_t * p_cb) NRFX_LOG_ERROR("Failed to stop instance with base address: %p.", (void *)p_spim); } p_cb->transfer_in_progress = false; + nrfy_spim_disable(p_spim); } static void pin_init(uint32_t pin, @@ -545,7 +546,6 @@ nrfx_err_t nrfx_spim_init(nrfx_spim_t const * p_instance, return err_code; } spim_configure(p_instance, p_config); - nrfy_spim_enable(p_instance->p_reg); } p_cb->transfer_in_progress = false; @@ -576,9 +576,7 @@ nrfx_err_t nrfx_spim_reconfigure(nrfx_spim_t const * p_instance, return err_code; } - nrfy_spim_disable(p_instance->p_reg); spim_configure(p_instance, p_config); - nrfy_spim_enable(p_instance->p_reg); return NRFX_SUCCESS; } @@ -602,14 +600,9 @@ void nrfx_spim_uninit(nrfx_spim_t const * p_instance) if (p_cb->handler) { nrfy_spim_int_disable(p_instance->p_reg, NRF_SPIM_ALL_INTS_MASK); - if (p_cb->transfer_in_progress) - { - // Ensure that SPI is not performing any transfer. - spim_abort(p_instance->p_reg, p_cb); - } + spim_abort(p_instance->p_reg, p_cb); } - nrfy_spim_disable(p_instance->p_reg); nrfy_spim_pins_t pins; nrfy_spim_pins_get(p_instance->p_reg, &pins); @@ -688,14 +681,17 @@ static void set_ss_pin_state(spim_control_block_t * p_cb, bool active) } } -static void finish_transfer(spim_control_block_t * p_cb) +static void finish_transfer(NRF_SPIM_Type * p_spim, spim_control_block_t * p_cb) { // If Slave Select signal is used, this is the time to deactivate it. set_ss_pin_state(p_cb, false); // By clearing this flag before calling the handler we allow subsequent // transfers to be started directly from the handler function. - p_cb->transfer_in_progress = false; + if (p_cb->transfer_in_progress) + { + spim_abort(p_spim, p_cb); + } p_cb->evt.type = NRFX_SPIM_EVENT_DONE; p_cb->handler(&p_cb->evt, p_cb->p_context); @@ -709,8 +705,10 @@ static nrfx_err_t spim_xfer(NRF_SPIM_Type * p_spim, nrfx_err_t err_code; // EasyDMA requires that transfer buffers are placed in Data RAM region; // signal error if they are not. - if ((p_xfer_desc->p_tx_buffer != NULL && !nrfx_is_in_ram(p_xfer_desc->p_tx_buffer)) || - (p_xfer_desc->p_rx_buffer != NULL && !nrfx_is_in_ram(p_xfer_desc->p_rx_buffer))) + if ((p_xfer_desc->p_tx_buffer != NULL && + !nrf_dma_accessible_check(p_spim, p_xfer_desc->p_tx_buffer)) || + (p_xfer_desc->p_rx_buffer != NULL && + !nrf_dma_accessible_check(p_spim, p_xfer_desc->p_rx_buffer))) { p_cb->transfer_in_progress = false; err_code = NRFX_ERROR_INVALID_ADDR; @@ -736,6 +734,7 @@ static nrfx_err_t spim_xfer(NRF_SPIM_Type * p_spim, #if NRFX_CHECK(NRFX_SPIM_NRF52_ANOMALY_109_WORKAROUND_ENABLED) if (flags & NRFX_SPIM_FLAG_HOLD_XFER) { + nrfy_spim_event_clear(p_spim, NRF_SPIM_EVENT_STARTED); xfer_desc.tx_length = 0; xfer_desc.rx_length = 0; nrfy_spim_int_enable(p_spim, NRF_SPIM_INT_STARTED_MASK); @@ -744,6 +743,7 @@ static nrfx_err_t spim_xfer(NRF_SPIM_Type * p_spim, nrfy_spim_buffers_set(p_spim, &xfer_desc); nrfy_spim_event_clear(p_spim, NRF_SPIM_EVENT_END); + nrfy_spim_enable(p_spim); if (!(flags & NRFX_SPIM_FLAG_HOLD_XFER)) { @@ -759,6 +759,10 @@ static nrfx_err_t spim_xfer(NRF_SPIM_Type * p_spim, } #endif set_ss_pin_state(p_cb, false); + if (!(flags & NRFX_SPIM_FLAG_HOLD_XFER)) + { + spim_abort(p_spim, p_cb); + } } else { @@ -837,17 +841,14 @@ void nrfx_spim_abort(nrfx_spim_t const * p_instance) static void irq_handler(NRF_SPIM_Type * p_spim, spim_control_block_t * p_cb) { - uint32_t evt_mask = nrfy_spim_events_process(p_spim, -#if NRFX_CHECK(NRFX_SPIM_NRF52_ANOMALY_109_WORKAROUND_ENABLED) - NRFY_EVENT_TO_INT_BITMASK(NRF_SPIM_EVENT_STARTED) | -#endif - NRFY_EVENT_TO_INT_BITMASK(NRF_SPIM_EVENT_END), - &p_cb->evt.xfer_desc); - #if NRFX_CHECK(NRFX_SPIM_NRF52_ANOMALY_109_WORKAROUND_ENABLED) - if (evt_mask & NRFY_EVENT_TO_INT_BITMASK(NRF_SPIM_EVENT_STARTED)) + if (nrfy_spim_int_enable_check(p_spim, NRF_SPIM_INT_STARTED_MASK) && + nrfy_spim_event_check(p_spim, NRF_SPIM_EVENT_STARTED)) { /* Handle first, zero-length, auxiliary transmission. */ + nrfy_spim_event_clear(p_spim, NRF_SPIM_EVENT_STARTED); + nrfy_spim_event_clear(p_spim, NRF_SPIM_EVENT_END); + NRFX_ASSERT(nrfy_spim_tx_maxcnt_get(p_spim) == 0); NRFX_ASSERT(nrfy_spim_rx_maxcnt_get(p_spim) == 0); @@ -861,7 +862,9 @@ static void irq_handler(NRF_SPIM_Type * p_spim, spim_control_block_t * p_cb) } #endif - if (evt_mask & NRFY_EVENT_TO_INT_BITMASK(NRF_SPIM_EVENT_END)) + if (nrfy_spim_events_process(p_spim, + NRFY_EVENT_TO_INT_BITMASK(NRF_SPIM_EVENT_END), + &p_cb->evt.xfer_desc)) { #if NRFX_CHECK(NRFX_SPIM3_NRF52840_ANOMALY_198_WORKAROUND_ENABLED) if (p_spim == NRF_SPIM3) @@ -871,7 +874,7 @@ static void irq_handler(NRF_SPIM_Type * p_spim, spim_control_block_t * p_cb) #endif NRFX_ASSERT(p_cb->handler); NRFX_LOG_DEBUG("Event: NRF_SPIM_EVENT_END."); - finish_transfer(p_cb); + finish_transfer(p_spim, p_cb); } } diff --git a/drivers/src/nrfx_spis.c b/drivers/src/nrfx_spis.c index 257726c59..df84b653b 100644 --- a/drivers/src/nrfx_spis.c +++ b/drivers/src/nrfx_spis.c @@ -95,98 +95,52 @@ typedef struct volatile nrfx_spis_state_t spi_state; //!< SPI slave state. void * p_context; //!< Context set on initialization. bool skip_gpio_cfg; +#if defined(USE_DMA_ISSUE_WORKAROUND) + uint32_t csn_pin; + uint8_t gpiote_ch; +#endif } spis_cb_t; static spis_cb_t m_cb[NRFX_SPIS_ENABLED_COUNT]; -static nrfx_err_t pins_configure(nrfx_spis_config_t const * p_config) +static void pins_configure(nrfx_spis_config_t const * p_config) { - if (!p_config->skip_gpio_cfg) + nrf_gpio_cfg(p_config->sck_pin, + NRF_GPIO_PIN_DIR_INPUT, + NRF_GPIO_PIN_INPUT_CONNECT, + NRF_GPIO_PIN_NOPULL, + NRF_GPIO_PIN_S0S1, + NRF_GPIO_PIN_NOSENSE); +#if NRF_GPIO_HAS_CLOCKPIN + nrfy_gpio_pin_clock_set(p_config->sck_pin, true); +#endif + + if (p_config->mosi_pin != NRF_SPIS_PIN_NOT_CONNECTED) { - nrf_gpio_cfg(p_config->sck_pin, + nrf_gpio_cfg(p_config->mosi_pin, NRF_GPIO_PIN_DIR_INPUT, NRF_GPIO_PIN_INPUT_CONNECT, NRF_GPIO_PIN_NOPULL, NRF_GPIO_PIN_S0S1, NRF_GPIO_PIN_NOSENSE); -#if NRF_GPIO_HAS_CLOCKPIN - nrfy_gpio_pin_clock_set(p_config->sck_pin, true); -#endif - - if (p_config->mosi_pin != NRF_SPIS_PIN_NOT_CONNECTED) - { - nrf_gpio_cfg(p_config->mosi_pin, - NRF_GPIO_PIN_DIR_INPUT, - NRF_GPIO_PIN_INPUT_CONNECT, - NRF_GPIO_PIN_NOPULL, - NRF_GPIO_PIN_S0S1, - NRF_GPIO_PIN_NOSENSE); - } - - if (p_config->miso_pin != NRF_SPIS_PIN_NOT_CONNECTED) - { - nrf_gpio_cfg(p_config->miso_pin, - NRF_GPIO_PIN_DIR_INPUT, - NRF_GPIO_PIN_INPUT_CONNECT, - NRF_GPIO_PIN_NOPULL, - p_config->miso_drive, - NRF_GPIO_PIN_NOSENSE); - } + } - nrf_gpio_cfg(p_config->csn_pin, + if (p_config->miso_pin != NRF_SPIS_PIN_NOT_CONNECTED) + { + nrf_gpio_cfg(p_config->miso_pin, NRF_GPIO_PIN_DIR_INPUT, NRF_GPIO_PIN_INPUT_CONNECT, - p_config->csn_pullup, - NRF_GPIO_PIN_S0S1, + NRF_GPIO_PIN_NOPULL, + p_config->miso_drive, NRF_GPIO_PIN_NOSENSE); - -#if defined(USE_DMA_ISSUE_WORKAROUND) - // Configure a GPIOTE channel to generate interrupts on each falling edge - // on the CSN line. Handling of these interrupts will make the CPU active, - // and thus will protect the DMA transfers started by SPIS right after it - // is selected for communication. - // [the GPIOTE driver may be already initialized at this point (by this - // driver when another SPIS instance is used, or by an application code), - // so just ignore the returned value] - (void)nrfx_gpiote_init(NRFX_GPIOTE_DEFAULT_CONFIG_IRQ_PRIORITY); - - uint8_t ch; - nrfx_err_t err_code; - - err_code = nrfx_gpiote_channel_alloc(&ch); - if (err_code != NRFX_SUCCESS) - { - NRFX_LOG_ERROR("Function: %s, error code: %s.", - __func__, - NRFX_LOG_ERROR_STRING_GET(err_code)); - return err_code; - } - - nrfx_gpiote_trigger_config_t trigger_config = { - .trigger = NRFX_GPIOTE_TRIGGER_HITOLO, - .p_in_channel = &ch - }; - nrfx_gpiote_handler_config_t handler_config = { - .handler = csn_event_handler - }; - - err_code = nrfx_gpiote_input_configure(p_config->csn_pin, - NULL, - &trigger_config, - &handler_config); - if (err_code != NRFX_SUCCESS) - { - NRFX_LOG_ERROR("Function: %s, error code: %s.", - __func__, - NRFX_LOG_ERROR_STRING_GET(err_code)); - return err_code; - } - - nrfx_gpiote_trigger_enable(p_config->csn_pin, true); -#endif } - return NRFX_SUCCESS; + nrf_gpio_cfg(p_config->csn_pin, + NRF_GPIO_PIN_DIR_INPUT, + NRF_GPIO_PIN_INPUT_CONNECT, + p_config->csn_pullup, + NRF_GPIO_PIN_S0S1, + NRF_GPIO_PIN_NOSENSE); } static bool spis_configure(nrfx_spis_t const * p_instance, @@ -198,9 +152,9 @@ static bool spis_configure(nrfx_spis_t const * p_instance, return false; } - if (pins_configure(p_config) != NRFX_SUCCESS) + if (!p_config->skip_gpio_cfg) { - return false; + pins_configure(p_config); } if (!p_config->skip_psel_cfg) @@ -212,6 +166,49 @@ static bool spis_configure(nrfx_spis_t const * p_instance, p_config->csn_pin); } +#if defined(USE_DMA_ISSUE_WORKAROUND) + spis_cb_t * p_cb = &m_cb[p_instance->drv_inst_idx]; + + // If the GPIOTE channel was already used with a CSN pin, deinitialize it + // first as that pin number may be different now. + if (p_cb->csn_pin != NRF_SPIS_PIN_NOT_CONNECTED) + { + nrfx_gpiote_pin_uninit(p_cb->csn_pin); + p_cb->csn_pin = NRF_SPIS_PIN_NOT_CONNECTED; + } + + // Get the CSN pin number from the PSEL register in the peripheral + // as in p_config that pin number may be omitted. + uint32_t csn_pin = nrf_spis_csn_pin_get(p_spis); + + // Configure a GPIOTE channel to generate interrupts on each falling edge + // on the CSN line. Handling of these interrupts will make the CPU active + // and thus will protect the DMA transfers started by SPIS right after it + // is selected for communication. + nrfx_gpiote_trigger_config_t trigger_config = { + .trigger = NRFX_GPIOTE_TRIGGER_HITOLO, + .p_in_channel = &p_cb->gpiote_ch + }; + nrfx_gpiote_handler_config_t handler_config = { + .handler = csn_event_handler + }; + nrfx_err_t err_code = nrfx_gpiote_input_configure(csn_pin, + NULL, + &trigger_config, + &handler_config); + if (err_code != NRFX_SUCCESS) + { + NRFX_LOG_ERROR("Function: %s, error code: %s.", + __func__, + NRFX_LOG_ERROR_STRING_GET(err_code)); + return false; + } + + nrfx_gpiote_trigger_enable(csn_pin, true); + + p_cb->csn_pin = csn_pin; +#endif + // Configure SPI mode. nrf_spis_configure(p_spis, p_config->mode, p_config->bit_order); @@ -271,12 +268,35 @@ nrfx_err_t nrfx_spis_init(nrfx_spis_t const * p_instance, p_cb->handler = event_handler; p_cb->p_context = p_context; +#if defined(USE_DMA_ISSUE_WORKAROUND) + p_cb->csn_pin = NRF_SPIS_PIN_NOT_CONNECTED; + + // Allocate a GPIOTE channel that will be used to handle the anomaly 109 + // (the GPIOTE driver may be already initialized at this point, by this + // driver when another SPIS instance is used or by an application code, + // so just ignore the returned value here). + (void)nrfx_gpiote_init(NRFX_GPIOTE_DEFAULT_CONFIG_IRQ_PRIORITY); + + err_code = nrfx_gpiote_channel_alloc(&p_cb->gpiote_ch); + if (err_code != NRFX_SUCCESS) + { + err_code = NRFX_ERROR_INTERNAL; + NRFX_LOG_ERROR("Function: %s, error code: %s.", + __func__, + NRFX_LOG_ERROR_STRING_GET(err_code)); + return err_code; + } +#endif + if (p_config) { p_cb->skip_gpio_cfg = p_config->skip_gpio_cfg; if (!spis_configure(p_instance, p_config)) { +#if defined(USE_DMA_ISSUE_WORKAROUND) + nrfx_gpiote_channel_free(p_cb->gpiote_ch); +#endif err_code = NRFX_ERROR_INVALID_PARAM; NRFX_LOG_WARNING("Function: %s, error code: %s.", __func__, @@ -333,6 +353,14 @@ void nrfx_spis_uninit(nrfx_spis_t const * p_instance) NRF_SPIS_Type * p_spis = p_instance->p_reg; +#if defined(USE_DMA_ISSUE_WORKAROUND) + if (p_cb->csn_pin != NRF_SPIS_PIN_NOT_CONNECTED) + { + nrfx_gpiote_pin_uninit(p_cb->csn_pin); + } + nrfx_gpiote_channel_free(p_cb->gpiote_ch); +#endif + #define DISABLE_ALL 0xFFFFFFFF nrf_spis_disable(p_spis); NRFX_IRQ_DISABLE(nrfx_get_irq_number(p_instance->p_reg)); diff --git a/drivers/src/nrfx_temp.c b/drivers/src/nrfx_temp.c index 4cd1edbaa..f1500aa8f 100644 --- a/drivers/src/nrfx_temp.c +++ b/drivers/src/nrfx_temp.c @@ -68,6 +68,10 @@ nrfx_err_t nrfx_temp_init(nrfx_temp_config_t const * p_config, nrfx_temp_data_ha *(uint32_t volatile *)0x4000C504 = 0; #endif +#if NRFY_TEMP_HAS_CALIBRATION && defined(FICR_TRIM_GLOBAL_TEMP_CALIB_VALUE_Msk) + nrfy_temp_calibration_coeff_set(NRF_TEMP, NRF_FICR->TRIM.GLOBAL.TEMP.CALIB); +#endif + m_data_handler = handler; if (m_data_handler) diff --git a/drivers/src/nrfx_wdt.c b/drivers/src/nrfx_wdt.c index 21c78d54f..ff00ee72a 100644 --- a/drivers/src/nrfx_wdt.c +++ b/drivers/src/nrfx_wdt.c @@ -123,7 +123,7 @@ nrfx_err_t nrfx_wdt_reconfigure(nrfx_wdt_t const * p_instance, NRFX_ASSERT(p_config); wdt_control_block_t * p_cb = &m_cb[p_instance->drv_inst_idx]; - if (p_cb->state == NRFX_DRV_STATE_INITIALIZED) + if (p_cb->state == NRFX_DRV_STATE_UNINITIALIZED) { return NRFX_ERROR_INVALID_STATE; } diff --git a/drivers/src/prs/nrfx_prs.h b/drivers/src/prs/nrfx_prs.h index e094fef41..493f85857 100644 --- a/drivers/src/prs/nrfx_prs.h +++ b/drivers/src/prs/nrfx_prs.h @@ -148,16 +148,20 @@ void nrfx_prs_release(void const * p_base_addr); /** @} */ -void nrfx_prs_box_0_irq_handler(void); -void nrfx_prs_box_1_irq_handler(void); -void nrfx_prs_box_2_irq_handler(void); -void nrfx_prs_box_3_irq_handler(void); -void nrfx_prs_box_4_irq_handler(void); -void nrfx_prs_box_5_irq_handler(void); -void nrfx_prs_box_6_irq_handler(void); -void nrfx_prs_box_7_irq_handler(void); -void nrfx_prs_box_8_irq_handler(void); - +/* + * Declare interrupt handlers for all enabled driver instances in the following format: + * nrfx_\_\_irq_handler (for example, nrfx_prs_box_0_irq_handler). + * + * A specific interrupt handler for the driver instance can be retrieved by using + * the NRFX_PRS_BOX_INST_HANDLER_GET macro. + * + * Here is a sample of using the NRFX_PRS_BOX_INST_HANDLER_GET macro to directly map + * an interrupt handler in a Zephyr application: + * + * IRQ_DIRECT_CONNECT(NRFX_IRQ_NUMBER_GET(NRF_PRS_BOX_INST_GET(\)), \, + * NRFX_PRS_BOX_INST_HANDLER_GET(\), 0); + */ +NRFX_INSTANCE_IRQ_HANDLERS_DECLARE(PRS_BOX_, prs_box) #ifdef __cplusplus } diff --git a/hal/nrf_cache.h b/hal/nrf_cache.h index 7977625b2..f4e784e90 100644 --- a/hal/nrf_cache.h +++ b/hal/nrf_cache.h @@ -107,30 +107,33 @@ extern "C" { #if defined(CACHEINFO_SET_WAY_D0_Msk) || defined(__NRFX_DOXYGEN__) /** @brief Symbol indicating whether dirtiness check functionality for cache is supported. */ -#define NRF_CACHE_HAS_DU_DIRTY 1 +#define NRF_CACHE_HAS_CACHEINFO_DU_DIRTY 1 #else -#define NRF_CACHE_HAS_DU_DIRTY 0 +#define NRF_CACHE_HAS_CACHEINFO_DU_DIRTY 0 #endif #if defined(CACHEINFO_SET_WAY_DUV0_Msk) || defined(CACHEINFO_SET_WAY_INFO_DUV0_Msk) || defined(__NRFX_DOXYGEN__) /** @brief Symbol indicating whether data unit validation functionality for cache is supported. */ -#define NRF_CACHE_HAS_DU_VALIDATION 1 +#define NRF_CACHE_HAS_CACHEINFO_DU_VALIDATION 1 #else -#define NRF_CACHE_HAS_DU_VALIDATION 0 +#define NRF_CACHE_HAS_CACHEINFO_DU_VALIDATION 0 #endif #if defined(CACHEINFO_SET_WAY_INFO_DUV0_Msk) || defined(__NRFX_DOXYGEN__) -/** @brief Symbol indicating whether data unit validation functionality for cache is supported. */ -#define NRF_CACHE_HAS_SET_WAY_INFO 1 +/** @brief Symbol indicating whether cache info has INFO register. */ +#define NRF_CACHE_HAS_CACHEINFO_SET_WAY_INFO 1 #else -#define NRF_CACHE_HAS_SET_WAY_INFO 0 +#define NRF_CACHE_HAS_CACHEINFO_SET_WAY_INFO 0 #endif #if NRF_CACHE_HAS_CACHEDATA /** @brief Max number of words in CACHEDATA data units. */ -#define NRF_CACHEDATA_DATA_WORDS_MAX CACHEDATA_SET_WAY_DU_DATA_MaxCount +#define NRF_CACHEDATA_DATA_WORDS_IN_UNIT_MAX CACHEDATA_SET_WAY_DU_DATA_MaxCount /** @brief Max number of CACHEDATA data units. */ #define NRF_CACHEDATA_DATA_UNITS_MAX CACHEDATA_SET_WAY_DU_MaxCount +/** @brief Max number of CACHEDATA words. */ +#define NRF_CACHEDATA_WORD_INDEX_MAX \ + (NRF_CACHEDATA_DATA_WORDS_IN_UNIT_MAX * NRF_CACHEDATA_DATA_UNITS_MAX) /** @brief Max number of CACHEDATA ways. */ #define NRF_CACHEDATA_WAY_INDEX_MAX CACHEDATA_SET_WAY_MaxCount /** @brief Max number of CACHEDATA sets. */ @@ -138,6 +141,13 @@ extern "C" { #endif #if NRF_CACHE_HAS_CACHEINFO +/** @brief Max number of words in CACHEINFO data units. */ +#define NRF_CACHEINFO_DATA_WORDS_IN_UNIT_MAX CACHEDATA_SET_WAY_DU_DATA_MaxCount +/** @brief Max number of CACHEINFO data units. */ +#define NRF_CACHEINFO_DATA_UNITS_MAX CACHEDATA_SET_WAY_DU_MaxCount +/** @brief Max number of CACHEINFO words. */ +#define NRF_CACHEINFO_WORD_INDEX_MAX \ + (NRF_CACHEINFO_DATA_WORDS_IN_UNIT_MAX * NRF_CACHEINFO_DATA_UNITS_MAX) /** @brief Max number of CACHEINFO ways. */ #define NRF_CACHEINFO_WAY_INDEX_MAX CACHEINFO_SET_WAY_MaxCount /** @brief Max number of CACHEINFO sets. */ @@ -187,22 +197,6 @@ typedef enum } nrf_cache_ramsize_t; #endif -/** @brief Structure describing location of the data stored in cache depending on a cache set and way. */ -typedef struct -{ - uint32_t set; ///< Cache set containing data to get. - uint8_t way; ///< Cache way containing data to get. -} nrf_cache_set_way_loc_t; - -/** @brief Structure describing location of the data stored in cache depending on data unit and word. */ -typedef struct -{ -#if NRF_CACHE_HAS_CACHEDATA_DU - uint8_t du; ///< Data unit that containing data to get. -#endif - uint8_t word; ///< Index of a specific data word. -} nrf_cache_du_word_loc_t; - /** * @brief Function for enabling the CACHE peripheral. * @@ -400,15 +394,17 @@ NRF_STATIC_INLINE void nrf_cache_update_lock_set(NRF_CACHE_Type * p_reg, bool en * * @note When operating in the RAM mode, the cache data is accessible as a general purpose RAM. * - * @param[in] p_reg Pointer to the structure of registers of the peripheral. - * @param[in] p_set_way Pointer to the structure of location parameters depending on a cache set and way. - * @param[in] p_du_word Pointer to the structure of location parameters depending on data unit and word. + * @param[in] p_reg Pointer to the structure of registers of the peripheral. + * @param[in] set Set that contains the data to get. + * @param[in] way Way that contains the data to get. + * @param[in] word Data word index to get. * * @return 32-bit data word. */ -NRF_STATIC_INLINE uint32_t nrf_cache_data_get(NRF_CACHEDATA_Type const * p_reg, - nrf_cache_set_way_loc_t const * p_set_way, - nrf_cache_du_word_loc_t const * p_du_word); +NRF_STATIC_INLINE uint32_t nrf_cache_data_get(NRF_CACHEDATA_Type const * p_reg, + uint32_t set, + uint8_t way, + uint8_t word); #endif #if NRF_CACHE_HAS_CACHEINFO @@ -417,25 +413,29 @@ NRF_STATIC_INLINE uint32_t nrf_cache_data_get(NRF_CACHEDATA_Type const * p_ * * The tag is used to check if an entry in the cache matches the address that is being fetched. * - * @param[in] p_reg Pointer to the structure of registers of the peripheral. - * @param[in] p_set_way Pointer to the structure of location parameters depending on a cache set and way. + * @param[in] p_reg Pointer to the structure of registers of the peripheral. + * @param[in] set Set that contains the tag to get. + * @param[in] way Way that contains the tag to get. * * @return Tag value. */ -NRF_STATIC_INLINE uint32_t nrf_cache_tag_get(NRF_CACHEINFO_Type const * p_reg, - nrf_cache_set_way_loc_t const * p_set_way); +NRF_STATIC_INLINE uint32_t nrf_cache_tag_get(NRF_CACHEINFO_Type const * p_reg, + uint32_t set, + uint8_t way); /** * @brief Function for checking the validity of a cache line associated with the specified set and way. * - * @param[in] p_reg Pointer to the structure of registers of the peripheral. - * @param[in] p_set_way Pointer to the structure of location parameters depending on a cache set and way. + * @param[in] p_reg Pointer to the structure of registers of the peripheral. + * @param[in] set Set that contains the cache line to check. + * @param[in] way Way that contains the cache line to check. * * @retval true Cache line is valid. * @retval false Cache line is invalid. */ -NRF_STATIC_INLINE bool nrf_cache_line_validity_check(NRF_CACHEINFO_Type const * p_reg, - nrf_cache_set_way_loc_t const * p_set_way); +NRF_STATIC_INLINE bool nrf_cache_line_validity_check(NRF_CACHEINFO_Type const * p_reg, + uint32_t set, + uint8_t way); /** * @brief Function for getting the most recently used way in the specified set. @@ -450,36 +450,40 @@ NRF_STATIC_INLINE bool nrf_cache_line_validity_check(NRF_CACHEINFO_Type const * NRF_STATIC_INLINE uint8_t nrf_cache_mru_get(NRF_CACHEINFO_Type const * p_reg, uint32_t set); #endif -#if NRF_CACHE_HAS_DU_VALIDATION +#if NRF_CACHE_HAS_CACHEINFO_DU_VALIDATION /** - * @brief Function for checking the validity of a data unit associated with the specified set and way. + * @brief Function for checking the validity of a data unit associated with the specified set, way and word. * - * @param[in] p_reg Pointer to the structure of registers of the peripheral. - * @param[in] p_set_way Pointer to the structure of location parameters depending on a cache set and way. - * @param[in] p_du_word Pointer to the structure of location parameters depending on data unit and word. + * @param[in] p_reg Pointer to the structure of registers of the peripheral. + * @param[in] set Set that contains the data unit to check. + * @param[in] way Way that contains the data unit to check. + * @param[in] word Data word index. * * @retval true Data unit is valid. * @retval false Data unit is invalid. */ -NRF_STATIC_INLINE bool nrf_cache_data_unit_validity_check(NRF_CACHEINFO_Type const * p_reg, - nrf_cache_set_way_loc_t const * p_set_way, - nrf_cache_du_word_loc_t const * p_du_word); +NRF_STATIC_INLINE bool nrf_cache_data_unit_validity_check(NRF_CACHEINFO_Type const * p_reg, + uint32_t set, + uint8_t way, + uint8_t word); #endif -#if NRF_CACHE_HAS_DU_DIRTY +#if NRF_CACHE_HAS_CACHEINFO_DU_DIRTY /** - * @brief Function for checking the dirtiness of a data unit associated with the specified set and way. + * @brief Function for checking the dirtiness of a data unit associated with the specified set, way and word. * - * @param[in] p_reg Pointer to the structure of registers of the peripheral. - * @param[in] p_set_way Pointer to the structure of location parameters depending on a cache set and way. - * @param[in] p_du_word Pointer to the structure of location parameters depending on data unit and word. + * @param[in] p_reg Pointer to the structure of registers of the peripheral. + * @param[in] set Set that contains the data unit to check. + * @param[in] way Way that contains the data unit to check. + * @param[in] word Data word index. * * @retval true Data unit is dirty. * @retval false Data unit is clean. */ -NRF_STATIC_INLINE bool nrf_cache_is_data_unit_dirty_check(NRF_CACHEINFO_Type const * p_reg, - nrf_cache_set_way_loc_t const * p_set_way, - nrf_cache_du_word_loc_t const * p_du_word); +NRF_STATIC_INLINE bool nrf_cache_is_data_unit_dirty_check(NRF_CACHEINFO_Type const * p_reg, + uint32_t set, + uint8_t way, + uint8_t word); #endif #if NRF_CACHE_HAS_TASKS @@ -672,20 +676,23 @@ NRF_STATIC_INLINE void nrf_cache_update_lock_set(NRF_CACHE_Type * p_reg, bool en } #if NRF_CACHE_HAS_CACHEDATA -NRF_STATIC_INLINE uint32_t nrf_cache_data_get(NRF_CACHEDATA_Type const * p_reg, - nrf_cache_set_way_loc_t const * p_set_way, - nrf_cache_du_word_loc_t const * p_du_word) +NRF_STATIC_INLINE uint32_t nrf_cache_data_get(NRF_CACHEDATA_Type const * p_reg, + uint32_t set, + uint8_t way, + uint8_t word) { #if NRF_CACHE_HAS_CACHEDATA_DU - NRFX_ASSERT(p_du_word->word < NRF_CACHEDATA_DATA_WORDS_MAX); - NRFX_ASSERT(p_du_word->du < NRF_CACHEDATA_DATA_UNITS_MAX); - NRFX_ASSERT(p_set_way->way < NRF_CACHEDATA_WAY_INDEX_MAX); - NRFX_ASSERT(p_set_way->set < NRF_CACHEDATA_SET_INDEX_MAX); + NRFX_ASSERT(word < NRF_CACHEDATA_WORD_INDEX_MAX); + NRFX_ASSERT(way < NRF_CACHEDATA_WAY_INDEX_MAX); + NRFX_ASSERT(set < NRF_CACHEDATA_SET_INDEX_MAX); - return p_reg->SET[p_set_way->set].WAY[p_set_way->way].DU[p_du_word->du].DATA[p_du_word->word]; + uint8_t du = (word / NRF_CACHEDATA_DATA_WORDS_IN_UNIT_MAX); + uint8_t data = (word - (du * NRF_CACHEDATA_DATA_WORDS_IN_UNIT_MAX)); + + return p_reg->SET[set].WAY[way].DU[du].DATA[data]; #else - volatile CACHEDATA_SET_WAY_Type const * reg = &p_reg->SET[p_set_way->set].WAY[p_set_way->way]; - switch (p_du_word->word) + volatile CACHEDATA_SET_WAY_Type const * reg = &p_reg->SET[set].WAY[way]; + switch (word) { case 0: return reg->DATA0; case 1: return reg->DATA1; @@ -700,28 +707,30 @@ NRF_STATIC_INLINE uint32_t nrf_cache_data_get(NRF_CACHEDATA_Type const * p_ #endif #if NRF_CACHE_HAS_CACHEINFO -NRF_STATIC_INLINE uint32_t nrf_cache_tag_get(NRF_CACHEINFO_Type const * p_reg, - nrf_cache_set_way_loc_t const * p_set_way) +NRF_STATIC_INLINE uint32_t nrf_cache_tag_get(NRF_CACHEINFO_Type const * p_reg, + uint32_t set, + uint8_t way) { #if defined(CACHEINFO_SET_WAY_INFO_TAG_Msk) - NRFX_ASSERT(p_set_way->way < NRF_CACHEINFO_WAY_INDEX_MAX); - NRFX_ASSERT(p_set_way->set < NRF_CACHEINFO_SET_INDEX_MAX); - return (p_reg->SET[p_set_way->set].WAY[p_set_way->way].INFO & CACHEINFO_SET_WAY_INFO_TAG_Msk); + NRFX_ASSERT(way < NRF_CACHEINFO_WAY_INDEX_MAX); + NRFX_ASSERT(set < NRF_CACHEINFO_SET_INDEX_MAX); + return (p_reg->SET[set].WAY[way].INFO & CACHEINFO_SET_WAY_INFO_TAG_Msk); #else - return (p_reg->SET[p_set_way->set].WAY[p_set_way->way] & CACHEINFO_SET_WAY_TAG_Msk); + return (p_reg->SET[set].WAY[way] & CACHEINFO_SET_WAY_TAG_Msk); #endif } -NRF_STATIC_INLINE bool nrf_cache_line_validity_check(NRF_CACHEINFO_Type const * p_reg, - nrf_cache_set_way_loc_t const * p_set_way) +NRF_STATIC_INLINE bool nrf_cache_line_validity_check(NRF_CACHEINFO_Type const * p_reg, + uint32_t set, + uint8_t way) { #if defined(CACHEINFO_SET_WAY_INFO_V_Msk) - NRFX_ASSERT(p_set_way->way < NRF_CACHEINFO_WAY_INDEX_MAX); - NRFX_ASSERT(p_set_way->set < NRF_CACHEINFO_SET_INDEX_MAX); - return (p_reg->SET[p_set_way->set].WAY[p_set_way->way].INFO & CACHEINFO_SET_WAY_INFO_V_Msk) == + NRFX_ASSERT(way < NRF_CACHEINFO_WAY_INDEX_MAX); + NRFX_ASSERT(set < NRF_CACHEINFO_SET_INDEX_MAX); + return (p_reg->SET[set].WAY[way].INFO & CACHEINFO_SET_WAY_INFO_V_Msk) == (CACHEINFO_SET_WAY_INFO_V_Valid << CACHEINFO_SET_WAY_INFO_V_Pos); #else - return (p_reg->SET[p_set_way->set].WAY[p_set_way->way] & CACHEINFO_SET_WAY_V_Msk) == + return (p_reg->SET[set].WAY[way] & CACHEINFO_SET_WAY_V_Msk) == (CACHEINFO_SET_WAY_V_Valid << CACHEINFO_SET_WAY_V_Pos); #endif } @@ -737,45 +746,48 @@ NRF_STATIC_INLINE uint8_t nrf_cache_mru_get(NRF_CACHEINFO_Type const * p_reg, ui #endif } -#if NRF_CACHE_HAS_DU_VALIDATION -NRF_STATIC_INLINE bool nrf_cache_data_unit_validity_check(NRF_CACHEINFO_Type const * p_reg, - nrf_cache_set_way_loc_t const * p_set_way, - nrf_cache_du_word_loc_t const * p_du_word) +#if NRF_CACHE_HAS_CACHEINFO_DU_VALIDATION +NRF_STATIC_INLINE bool nrf_cache_data_unit_validity_check(NRF_CACHEINFO_Type const * p_reg, + uint32_t set, + uint8_t way, + uint8_t word) { - (void)p_du_word->word; - NRFX_ASSERT(p_set_way->way < NRF_CACHEINFO_WAY_INDEX_MAX); - NRFX_ASSERT(p_set_way->set < NRF_CACHEINFO_SET_INDEX_MAX); - switch (p_du_word->du) + NRFX_ASSERT(word < NRF_CACHEINFO_WORD_INDEX_MAX); + NRFX_ASSERT(way < NRF_CACHEINFO_WAY_INDEX_MAX); + NRFX_ASSERT(set < NRF_CACHEINFO_SET_INDEX_MAX); + + uint8_t du = (word / NRF_CACHEINFO_DATA_WORDS_IN_UNIT_MAX); + switch (du) { -#if NRF_CACHE_HAS_SET_WAY_INFO +#if NRF_CACHE_HAS_CACHEINFO_SET_WAY_INFO case 0: - return (p_reg->SET[p_set_way->set].WAY[p_set_way->way].INFO & + return (p_reg->SET[set].WAY[way].INFO & CACHEINFO_SET_WAY_INFO_DUV0_Msk) == (CACHEINFO_SET_WAY_INFO_DUV0_Valid << CACHEINFO_SET_WAY_INFO_DUV0_Pos); case 1: - return (p_reg->SET[p_set_way->set].WAY[p_set_way->way].INFO & + return (p_reg->SET[set].WAY[way].INFO & CACHEINFO_SET_WAY_INFO_DUV1_Msk) == (CACHEINFO_SET_WAY_INFO_DUV1_Valid << CACHEINFO_SET_WAY_INFO_DUV1_Pos); case 2: - return (p_reg->SET[p_set_way->set].WAY[p_set_way->way].INFO & + return (p_reg->SET[set].WAY[way].INFO & CACHEINFO_SET_WAY_INFO_DUV2_Msk) == (CACHEINFO_SET_WAY_INFO_DUV2_Valid << CACHEINFO_SET_WAY_INFO_DUV2_Pos); case 3: - return (p_reg->SET[p_set_way->set].WAY[p_set_way->way].INFO & + return (p_reg->SET[set].WAY[way].INFO & CACHEINFO_SET_WAY_INFO_DUV3_Msk) == (CACHEINFO_SET_WAY_INFO_DUV3_Valid << CACHEINFO_SET_WAY_INFO_DUV3_Pos); #else case 0: - return (p_reg->SET[p_set_way->set].WAY[p_set_way->way] & CACHEINFO_SET_WAY_DUV0_Msk) == + return (p_reg->SET[set].WAY[way] & CACHEINFO_SET_WAY_DUV0_Msk) == (CACHEINFO_SET_WAY_DUV0_Valid << CACHEINFO_SET_WAY_DUV0_Pos); case 1: - return (p_reg->SET[p_set_way->set].WAY[p_set_way->way] & CACHEINFO_SET_WAY_DUV1_Msk) == + return (p_reg->SET[set].WAY[way] & CACHEINFO_SET_WAY_DUV1_Msk) == (CACHEINFO_SET_WAY_DUV1_Valid << CACHEINFO_SET_WAY_DUV1_Pos); case 2: - return (p_reg->SET[p_set_way->set].WAY[p_set_way->way] & CACHEINFO_SET_WAY_DUV2_Msk) == + return (p_reg->SET[set].WAY[way] & CACHEINFO_SET_WAY_DUV2_Msk) == (CACHEINFO_SET_WAY_DUV2_Valid << CACHEINFO_SET_WAY_DUV2_Pos); case 3: - return (p_reg->SET[p_set_way->set].WAY[p_set_way->way] & CACHEINFO_SET_WAY_DUV3_Msk) == + return (p_reg->SET[set].WAY[way] & CACHEINFO_SET_WAY_DUV3_Msk) == (CACHEINFO_SET_WAY_DUV3_Valid << CACHEINFO_SET_WAY_DUV3_Pos); #endif default: @@ -783,23 +795,30 @@ NRF_STATIC_INLINE bool nrf_cache_data_unit_validity_check(NRF_CACHEINFO_Type con return false; } } -#endif // NRF_CACHE_HAS_DU_VALIDATION +#endif // NRF_CACHE_HAS_CACHEINFO_DU_VALIDATION -#if NRF_CACHE_HAS_DU_DIRTY -NRF_STATIC_INLINE bool nrf_cache_is_data_unit_dirty_check(NRF_CACHEINFO_Type const * p_reg, - nrf_cache_set_way_loc_t const * p_set_way, - nrf_cache_du_word_loc_t const * p_du_word) +#if NRF_CACHE_HAS_CACHEINFO_DU_DIRTY +NRF_STATIC_INLINE bool nrf_cache_is_data_unit_dirty_check(NRF_CACHEINFO_Type const * p_reg, + uint32_t set, + uint8_t way, + uint8_t word) { - (void)p_du_word->word; - NRFX_ASSERT(p_set_way->way < NRF_CACHEINFO_WAY_INDEX_MAX); - NRFX_ASSERT(p_set_way->set < NRF_CACHEINFO_SET_INDEX_MAX); - switch (p_du_word->du) + NRFX_ASSERT(word < NRF_CACHEINFO_WORD_INDEX_MAX); + NRFX_ASSERT(way < NRF_CACHEINFO_WAY_INDEX_MAX); + NRFX_ASSERT(set < NRF_CACHEINFO_SET_INDEX_MAX); + + uint8_t du = (word / NRF_CACHEINFO_DATA_WORDS_IN_UNIT_MAX); + switch (du) { case 0: - return (p_reg->SET[p_set_way->set].WAY[p_set_way->way] & CACHEINFO_SET_WAY_D0_Msk) == - (CACHEINFO_SET_WAY_D0_Dirty << CACHEINFO_SET_WAY_D0_Pos); + /* FALLTHROUGH */ case 1: - return (p_reg->SET[p_set_way->set].WAY[p_set_way->way] & CACHEINFO_SET_WAY_D1_Msk) == + return (p_reg->SET[set].WAY[way] & CACHEINFO_SET_WAY_D0_Msk) == + (CACHEINFO_SET_WAY_D0_Dirty << CACHEINFO_SET_WAY_D0_Pos); + case 2: + /* FALLTHROUGH */ + case 3: + return (p_reg->SET[set].WAY[way] & CACHEINFO_SET_WAY_D1_Msk) == (CACHEINFO_SET_WAY_D1_Dirty << CACHEINFO_SET_WAY_D1_Pos); default: NRFX_ASSERT(false); diff --git a/hal/nrf_clock.h b/hal/nrf_clock.h index 4ac0b306a..40f371969 100644 --- a/hal/nrf_clock.h +++ b/hal/nrf_clock.h @@ -94,11 +94,19 @@ extern "C" { #define NRF_CLOCK_HAS_HFCLK_DIV 0 #endif -#if defined(CLOCK_LFCLKALWAYSRUN_ALWAYSRUN_Msk) || defined(__NRFX_DOXYGEN__) -/** @brief Symbol indicating whether the ALWAYSRUN register is present. */ -#define NRF_CLOCK_HAS_ALWAYSRUN 1 +#if defined(CLOCK_LFCLKALWAYSRUN_ALWAYSRUN_Msk) || defined(CLOCK_LFCLK_ALWAYSRUN_ALWAYSRUN_Msk) || \ + defined(__NRFX_DOXYGEN__) +/** @brief Symbol indicating whether the ALWAYSRUN register is present for LFCLK. */ +#define NRF_CLOCK_HAS_LFCLK_ALWAYSRUN 1 #else -#define NRF_CLOCK_HAS_ALWAYSRUN 0 +#define NRF_CLOCK_HAS_LFCLK_ALWAYSRUN 0 +#endif + +#if defined(CLOCK_HFCLKALWAYSRUN_ALWAYSRUN_Msk) || defined(__NRFX_DOXYGEN__) +/** @brief Symbol indicating whether the ALWAYSRUN register is present for HFCLK. */ +#define NRF_CLOCK_HAS_HFCLK_ALWAYSRUN 1 +#else +#define NRF_CLOCK_HAS_HFCLK_ALWAYSRUN 0 #endif #if defined(CLOCK_HFCLKSRC_SRC_Msk) || defined(__NRFX_DOXYGEN__) @@ -129,39 +137,48 @@ extern "C" { #define NRF_CLOCK_HAS_LFCLK_TYPE 0 #endif -#if defined(CLOCK_LFCLKSRCCOPY_SRC_Msk) || defined(__NRFX_DOXYGEN__) -/** @brief Symbol indicating whether the CLOCK has LFCLKSRCCOPY register. */ -#define NRF_CLOCK_HAS_LFCLKSRCCOPY 1 -#else -#define NRF_CLOCK_HAS_LFCLKSRCCOPY 0 -#endif - #if NRF_CLOCK_HAS_LFCLK_TYPE #define NRF_CLOCK_LFCLKRUN_STATUS_NotTriggered CLOCK_LFCLK_RUN_STATUS_NotTriggered /**< Task LFCLKSTART/HFCLKSTART has not been triggered definiton. */ #define NRF_CLOCK_LFCLKRUN_STATUS_Triggered CLOCK_LFCLK_RUN_STATUS_Triggered /**< Task LFCLKSTART/HFCLKSTART has been triggered. */ #define NRF_CLOCK_INTENSET_LFCLKSTARTED_Msk CLOCK_INTENSET_LFCLKSTARTED_Msk /**< Interrupt on LFCLKSTARTED event mask definition. */ +#define NRF_LFCLKSRCCOPY LFCLK.SRCCOPY /**< LF clock SRCCOPY register definition. */ #define NRF_LFCLKRUN LFCLK.RUN /**< LF clock RUN register definition. */ #define NRF_LFCLKSTAT LFCLK.STAT /**< LF clock STAT register definition. */ #define NRF_LFCLKSRC LFCLK.SRC /**< LF clock SRC register definition. */ +#define NRF_LFCLKALWAYSRUN LFCLK.ALWAYSRUN /**< LF clock ALWAYSRUN register definition. */ +#define NRF_CLOCK_LFCLKSRCCOPY_SRC_Msk CLOCK_LFCLK_SRCCOPY_SRC_Msk /**< LF clock SRCCOPY status mask definition. */ +#define NRF_CLOCK_LFCLKSRCCOPY_SRC_Pos CLOCK_LFCLK_SRCCOPY_SRC_Pos /**< LF clock SRCCOPY status position definition. */ #define NRF_CLOCK_LFCLKRUN_STATUS_Msk CLOCK_LFCLK_RUN_STATUS_Msk /**< LF clock RUN status mask definition. */ #define NRF_CLOCK_LFCLKRUN_STATUS_Pos CLOCK_LFCLK_RUN_STATUS_Pos /**< LF clock RUN status position definition. */ #define NRF_CLOCK_LFCLKSTAT_SRC_Msk CLOCK_LFCLK_STAT_SRC_Msk /**< LF clock STAT source mask definition. */ #define NRF_CLOCK_LFCLKSTAT_SRC_Pos CLOCK_LFCLK_STAT_SRC_Pos /**< LF clock STAT source position definition. */ #define NRF_CLOCK_LFCLKSTAT_STATE_Msk CLOCK_LFCLK_STAT_STATE_Msk /**< LF clock STAT state mask definition. */ #define NRF_CLOCK_LFCLKSTAT_STATE_Pos CLOCK_LFCLK_STAT_STATE_Pos /**< LF clock STAT state position definition. */ +#define NRF_CLOCK_LFCLKSTAT_ALWAYSRUNNING_Msk CLOCK_LFCLK_STAT_ALWAYSRUNNING_Msk /**< LF clock STAT alwaysrunning position definition. */ +#define NRF_CLOCK_LFCLKSTAT_ALWAYSRUNNING_Pos CLOCK_LFCLK_STAT_ALWAYSRUNNING_Pos /**< LF clock STAT alwaysrunning mask definition. */ +#define NRF_CLOCK_LFCLKALWAYSRUN_ALWAYSRUN_Msk CLOCK_LFCLK_ALWAYSRUN_ALWAYSRUN_Msk /**< LF clock ALWAYSRUN position definition. */ +#define NRF_CLOCK_LFCLKALWAYSRUN_ALWAYSRUN_Pos CLOCK_LFCLK_ALWAYSRUN_ALWAYSRUN_Pos /**< LF clock ALWAYSRUN mask definition. */ #else #define NRF_CLOCK_LFCLKRUN_STATUS_NotTriggered CLOCK_LFCLKRUN_STATUS_NotTriggered #define NRF_CLOCK_LFCLKRUN_STATUS_Triggered CLOCK_LFCLKRUN_STATUS_Triggered #define NRF_CLOCK_INTENSET_LFCLKSTARTED_Msk CLOCK_INTENSET_LFCLKSTARTED_Msk +#define NRF_LFCLKSRCCOPY LFCLKSRCCOPY #define NRF_LFCLKRUN LFCLKRUN #define NRF_LFCLKSTAT LFCLKSTAT #define NRF_LFCLKSRC LFCLKSRC +#define NRF_LFCLKALWAYSRUN LFCLKALWAYSRUN +#define NRF_CLOCK_LFCLKSRCCOPY_SRC_Msk CLOCK_LFCLKSRCCOPY_SRC_Msk +#define NRF_CLOCK_LFCLKSRCCOPY_SRC_Pos CLOCK_LFCLKSRCCOPY_SRC_Pos #define NRF_CLOCK_LFCLKRUN_STATUS_Msk CLOCK_LFCLKRUN_STATUS_Msk #define NRF_CLOCK_LFCLKRUN_STATUS_Pos CLOCK_LFCLKRUN_STATUS_Pos #define NRF_CLOCK_LFCLKSTAT_SRC_Msk CLOCK_LFCLKSTAT_SRC_Msk #define NRF_CLOCK_LFCLKSTAT_SRC_Pos CLOCK_LFCLKSTAT_SRC_Pos #define NRF_CLOCK_LFCLKSTAT_STATE_Msk CLOCK_LFCLKSTAT_STATE_Msk #define NRF_CLOCK_LFCLKSTAT_STATE_Pos CLOCK_LFCLKSTAT_STATE_Pos +#define NRF_CLOCK_LFCLKSTAT_ALWAYSRUNNING_Msk CLOCK_LFCLKSTAT_ALWAYSRUNNING_Msk +#define NRF_CLOCK_LFCLKSTAT_ALWAYSRUNNING_Pos CLOCK_LFCLKSTAT_ALWAYSRUNNING_Pos +#define NRF_CLOCK_LFCLKALWAYSRUN_ALWAYSRUN_Msk CLOCK_LFCLKALWAYSRUN_ALWAYSRUN_Msk +#define NRF_CLOCK_LFCLKALWAYSRUN_ALWAYSRUN_Pos CLOCK_LFCLKALWAYSRUN_ALWAYSRUN_Pos #endif #if NRF_CLOCK_HAS_XO @@ -173,12 +190,10 @@ extern "C" { #define NRF_HFCLKSTAT XO.STAT /**< HF clock STAT register definition. */ #define NRF_CLOCK_HFCLKRUN_STATUS_Msk CLOCK_XO_RUN_STATUS_Msk /**< HF clock RUN status mask definition. */ #define NRF_CLOCK_HFCLKRUN_STATUS_Pos CLOCK_XO_RUN_STATUS_Pos /**< HF clock RUN status position definition. */ -#define NRF_CLOCK_HFCLKSTAT_SRC_Msk CLOCK_XO_STAT_SRC_Msk /**< HF clock STAT source mask definition. */ -#define NRF_CLOCK_HFCLKSTAT_SRC_Pos CLOCK_XO_STAT_SRC_Pos /**< HF clock STAT source position definition. */ #define NRF_CLOCK_HFCLKSTAT_STATE_Msk CLOCK_XO_STAT_STATE_Msk /**< HF clock STAT state mask definition. */ #define NRF_CLOCK_HFCLKSTAT_STATE_Pos CLOCK_XO_STAT_STATE_Pos /**< HF clock STAT state position definition. */ #else -#define NRF_CLOCK_INTENSET_HFCLKSTARTED_Msk CLOCK_INTENSET_HFCLKSTARTED_Msk +#define NRF_CLOCK_INTENSET_HFCLKSTARTED_Msk CLOCK_INTENSET_HFCLKSTARTED_Msk #define NRF_TASKS_HFCLKSTART TASKS_HFCLKSTART #define NRF_TASKS_HFCLKSTOP TASKS_HFCLKSTOP #define NRF_EVENTS_HFCLKSTARTED EVENTS_HFCLKSTARTED @@ -186,8 +201,6 @@ extern "C" { #define NRF_HFCLKSTAT HFCLKSTAT #define NRF_CLOCK_HFCLKRUN_STATUS_Msk CLOCK_HFCLKRUN_STATUS_Msk #define NRF_CLOCK_HFCLKRUN_STATUS_Pos CLOCK_HFCLKRUN_STATUS_Pos -#define NRF_CLOCK_HFCLKSTAT_SRC_Msk CLOCK_HFCLKSTAT_SRC_Msk -#define NRF_CLOCK_HFCLKSTAT_SRC_Pos CLOCK_HFCLKSTAT_SRC_Pos #define NRF_CLOCK_HFCLKSTAT_STATE_Msk CLOCK_HFCLKSTAT_STATE_Msk #define NRF_CLOCK_HFCLKSTAT_STATE_Pos CLOCK_HFCLKSTAT_STATE_Pos #endif @@ -547,7 +560,6 @@ NRF_STATIC_INLINE nrf_clock_lfclk_t nrf_clock_lf_src_get(NRF_CLOCK_Type const * */ NRF_STATIC_INLINE nrf_clock_lfclk_t nrf_clock_lf_actv_src_get(NRF_CLOCK_Type const * p_reg); -#if NRF_CLOCK_HAS_LFCLKSRCCOPY /** * @brief Function for retrieving the clock source for the LFCLK clock when * the task LKCLKSTART is triggered. @@ -562,7 +574,6 @@ NRF_STATIC_INLINE nrf_clock_lfclk_t nrf_clock_lf_actv_src_get(NRF_CLOCK_Type con * the HFCLK is running and generating the LFCLK clock. */ NRF_STATIC_INLINE nrf_clock_lfclk_t nrf_clock_lf_srccopy_get(NRF_CLOCK_Type const * p_reg); -#endif /** * @brief Function for retrieving the state of the LFCLK clock. @@ -744,7 +755,8 @@ NRF_STATIC_INLINE void nrf_clock_hfclk192m_src_set(NRF_CLOCK_Type * p_reg, NRF_STATIC_INLINE nrf_clock_hfclk_t nrf_clock_hfclk192m_src_get(NRF_CLOCK_Type const * p_reg); #endif // NRF_CLOCK_HAS_HFCLK192M -#if NRF_CLOCK_HAS_ALWAYSRUN +#if (NRF_CLOCK_HAS_LFCLK_ALWAYSRUN || NRF_CLOCK_HAS_HFCLK_ALWAYSRUN || NRF_CLOCK_HAS_HFCLK192M || \ + NRF_CLOCK_HAS_HFCLKAUDIO) /** * @brief Function for setting the clock domain to always run. * @@ -777,7 +789,8 @@ NRF_STATIC_INLINE bool nrf_clock_alwaysrun_get(NRF_CLOCK_Type const * p_reg, */ NRF_STATIC_INLINE bool nrf_clock_alwaysrun_active_get(NRF_CLOCK_Type const * p_reg, nrf_clock_domain_t domain); -#endif +#endif /* (NRF_CLOCK_HAS_LFCLK_ALWAYSRUN || NRF_CLOCK_HAS_HFCLK_ALWAYSRUN || + NRF_CLOCK_HAS_HFCLK192M || NRF_CLOCK_HAS_HFCLKAUDIO) */ #if defined(DPPI_PRESENT) || defined(__NRFX_DOXYGEN__) /** @@ -933,8 +946,8 @@ NRF_STATIC_INLINE bool nrf_clock_is_running(NRF_CLOCK_Type const * p_reg, NRF_CLOCK_HFCLK_LOW_ACCURACY; #else (*(nrf_clock_hfclk_t *)p_clk_src) = - (nrf_clock_hfclk_t)((p_reg->NRF_HFCLKSTAT & NRF_CLOCK_HFCLKSTAT_SRC_Msk) - >> NRF_CLOCK_HFCLKSTAT_SRC_Pos); + (nrf_clock_hfclk_t)((p_reg->NRF_HFCLKSTAT & CLOCK_HFCLKSTAT_SRC_Msk) + >> CLOCK_HFCLKSTAT_SRC_Pos); #endif } break; @@ -982,13 +995,11 @@ NRF_STATIC_INLINE nrf_clock_lfclk_t nrf_clock_lf_actv_src_get(NRF_CLOCK_Type con return clk_src; } -#if NRF_CLOCK_HAS_LFCLKSRCCOPY NRF_STATIC_INLINE nrf_clock_lfclk_t nrf_clock_lf_srccopy_get(NRF_CLOCK_Type const * p_reg) { - return (nrf_clock_lfclk_t)((p_reg->LFCLKSRCCOPY & CLOCK_LFCLKSRCCOPY_SRC_Msk) - >> CLOCK_LFCLKSRCCOPY_SRC_Pos); + return (nrf_clock_lfclk_t)((p_reg->NRF_LFCLKSRCCOPY & NRF_CLOCK_LFCLKSRCCOPY_SRC_Msk) + >> NRF_CLOCK_LFCLKSRCCOPY_SRC_Pos); } -#endif NRF_STATIC_INLINE bool nrf_clock_lf_is_running(NRF_CLOCK_Type const * p_reg) { @@ -1100,23 +1111,28 @@ NRF_STATIC_INLINE void nrf_clock_cal_timer_timeout_set(NRF_CLOCK_Type * p_reg, u } #endif -#if NRF_CLOCK_HAS_ALWAYSRUN +#if (NRF_CLOCK_HAS_LFCLK_ALWAYSRUN || NRF_CLOCK_HAS_HFCLK_ALWAYSRUN || NRF_CLOCK_HAS_HFCLK192M || \ + NRF_CLOCK_HAS_HFCLKAUDIO) NRF_STATIC_INLINE void nrf_clock_alwaysrun_set(NRF_CLOCK_Type * p_reg, nrf_clock_domain_t domain, bool alwaysrun) { switch (domain) { +#if NRF_CLOCK_HAS_LFCLK_ALWAYSRUN case NRF_CLOCK_DOMAIN_LFCLK: - p_reg->LFCLKALWAYSRUN = - ((alwaysrun << CLOCK_LFCLKALWAYSRUN_ALWAYSRUN_Pos) - & CLOCK_LFCLKALWAYSRUN_ALWAYSRUN_Msk); + p_reg->NRF_LFCLKALWAYSRUN = + ((alwaysrun << NRF_CLOCK_LFCLKALWAYSRUN_ALWAYSRUN_Pos) + & NRF_CLOCK_LFCLKALWAYSRUN_ALWAYSRUN_Msk); break; +#endif +#if NRF_CLOCK_HAS_HFCLK_ALWAYSRUN case NRF_CLOCK_DOMAIN_HFCLK: p_reg->HFCLKALWAYSRUN = ((alwaysrun << CLOCK_HFCLKALWAYSRUN_ALWAYSRUN_Pos) & CLOCK_HFCLKALWAYSRUN_ALWAYSRUN_Msk); break; +#endif #if NRF_CLOCK_HAS_HFCLK192M case NRF_CLOCK_DOMAIN_HFCLK192M: p_reg->HFCLK192MALWAYSRUN = @@ -1142,12 +1158,16 @@ NRF_STATIC_INLINE bool nrf_clock_alwaysrun_get(NRF_CLOCK_Type const * p_reg, { switch (domain) { +#if NRF_CLOCK_HAS_LFCLK_ALWAYSRUN case NRF_CLOCK_DOMAIN_LFCLK: - return ((p_reg->LFCLKALWAYSRUN & CLOCK_LFCLKALWAYSRUN_ALWAYSRUN_Msk) - >> CLOCK_LFCLKALWAYSRUN_ALWAYSRUN_Pos); + return ((p_reg->NRF_LFCLKALWAYSRUN & NRF_CLOCK_LFCLKALWAYSRUN_ALWAYSRUN_Msk) + >> NRF_CLOCK_LFCLKALWAYSRUN_ALWAYSRUN_Pos); +#endif +#if NRF_CLOCK_HAS_HFCLK_ALWAYSRUN case NRF_CLOCK_DOMAIN_HFCLK: return ((p_reg->HFCLKALWAYSRUN & CLOCK_HFCLKALWAYSRUN_ALWAYSRUN_Msk) >> CLOCK_HFCLKALWAYSRUN_ALWAYSRUN_Pos); +#endif #if NRF_CLOCK_HAS_HFCLK192M case NRF_CLOCK_DOMAIN_HFCLK192M: return ((p_reg->HFCLK192MALWAYSRUN & CLOCK_HFCLK192MALWAYSRUN_ALWAYSRUN_Msk) @@ -1169,12 +1189,16 @@ NRF_STATIC_INLINE bool nrf_clock_alwaysrun_active_get(NRF_CLOCK_Type const * p_r { switch (domain) { +#if NRF_CLOCK_HAS_LFCLK_ALWAYSRUN case NRF_CLOCK_DOMAIN_LFCLK: - return ((p_reg->LFCLKSTAT & CLOCK_LFCLKSTAT_ALWAYSRUNNING_Msk) - >> CLOCK_LFCLKSTAT_ALWAYSRUNNING_Pos); + return ((p_reg->NRF_LFCLKSTAT & NRF_CLOCK_LFCLKSTAT_ALWAYSRUNNING_Msk) + >> NRF_CLOCK_LFCLKSTAT_ALWAYSRUNNING_Pos); +#endif +#if NRF_CLOCK_HAS_HFCLK_ALWAYSRUN case NRF_CLOCK_DOMAIN_HFCLK: return ((p_reg->HFCLKSTAT & CLOCK_HFCLKSTAT_ALWAYSRUNNING_Msk) >> CLOCK_HFCLKSTAT_ALWAYSRUNNING_Pos); +#endif #if NRF_CLOCK_HAS_HFCLK192M case NRF_CLOCK_DOMAIN_HFCLK192M: return ((p_reg->HFCLK192MSTAT & CLOCK_HFCLK192MSTAT_ALWAYSRUNNING_Msk) @@ -1190,7 +1214,8 @@ NRF_STATIC_INLINE bool nrf_clock_alwaysrun_active_get(NRF_CLOCK_Type const * p_r return false; } } -#endif // NRF_CLOCK_HAS_ALWAYSRUN +#endif /* (NRF_CLOCK_HAS_LFCLK_ALWAYSRUN || NRF_CLOCK_HAS_HFCLK_ALWAYSRUN || + NRF_CLOCK_HAS_HFCLK192M || NRF_CLOCK_HAS_HFCLKAUDIO) */ #if defined(DPPI_PRESENT) NRF_STATIC_INLINE void nrf_clock_subscribe_set(NRF_CLOCK_Type * p_reg, diff --git a/hal/nrf_common.h b/hal/nrf_common.h index b3eecf587..133086e4f 100644 --- a/hal/nrf_common.h +++ b/hal/nrf_common.h @@ -58,9 +58,24 @@ extern "C" { #define RISCV_FENCE(p, s) __asm__ __volatile__ ("fence " #p "," #s : : : "memory") #endif +#if defined(DPPI_PRESENT) #ifndef NRF_SUBSCRIBE_PUBLISH_ENABLE #define NRF_SUBSCRIBE_PUBLISH_ENABLE (0x01UL << 31UL) #endif +#if defined(NRF_RADIO) +#define NRF_SUBSCRIBE_PUBLISH_OFFSET_RADIO \ + (NRFX_OFFSETOF(NRF_RADIO_Type, SUBSCRIBE_TXEN) - NRFX_OFFSETOF(NRF_RADIO_Type, TASKS_TXEN)) +#define NRF_SUBSCRIBE_PUBLISH_OFFSET(task_or_event) \ + ((NRFX_IN_RANGE(task_or_event, (uint32_t)NRF_RADIO, \ + (uint32_t)NRF_RADIO + NRF_SUBSCRIBE_PUBLISH_OFFSET_RADIO)) ? \ + (NRF_SUBSCRIBE_PUBLISH_OFFSET_RADIO) : \ + (0x80uL)) +#else +#define NRF_SUBSCRIBE_PUBLISH_OFFSET(task_or_event) 0x80uL +#endif // defined(NRF_RADIO) +#endif // defined(DPPI_PRESENT) + + #if defined(NRFX_CLZ) #define NRF_CLZ(value) NRFX_CLZ(value) diff --git a/hal/nrf_dppi.h b/hal/nrf_dppi.h index e78bc7491..a3b7e4512 100644 --- a/hal/nrf_dppi.h +++ b/hal/nrf_dppi.h @@ -83,9 +83,9 @@ extern "C" { * register is to be set. * @param[in] dppi_chan DPPIC channel number. */ -#define NRF_DPPI_ENDPOINT_SETUP(task_or_event, dppi_chan) \ - (*((volatile uint32_t *)(task_or_event + 0x80uL)) = \ - ((uint32_t)dppi_chan | NRF_SUBSCRIBE_PUBLISH_ENABLE)) +#define NRF_DPPI_ENDPOINT_SETUP(task_or_event, dppi_chan) \ + (*((volatile uint32_t *)(task_or_event + NRF_SUBSCRIBE_PUBLISH_OFFSET(task_or_event))) = \ + ((uint32_t)dppi_chan | NRF_SUBSCRIBE_PUBLISH_ENABLE)) /** * @brief Macro for clearing publish/subscribe register corresponding to specified event/task. @@ -94,7 +94,7 @@ extern "C" { * register is to be cleared. */ #define NRF_DPPI_ENDPOINT_CLEAR(task_or_event) \ - (*((volatile uint32_t *)(task_or_event + 0x80uL)) = 0) + (*((volatile uint32_t *)(task_or_event + NRF_SUBSCRIBE_PUBLISH_OFFSET(task_or_event))) = 0) /** @brief DPPI channel groups. */ typedef enum diff --git a/hal/nrf_ficr.h b/hal/nrf_ficr.h index ac7a8d82e..eef63b2a1 100644 --- a/hal/nrf_ficr.h +++ b/hal/nrf_ficr.h @@ -48,6 +48,63 @@ extern "C" { * the Factory Information Configuration Registers (FICR). */ +#if defined(FICR_CODEPAGESIZE_CODEPAGESIZE_Msk) || defined(NRF51) || defined(__NRFX_DOXYGEN__) +/** @brief Symbol indicating whether FICR CODEPAGESIZE register is present. */ +#define NRF_FICR_HAS_CODE_PAGE_SIZE 1 +#else +#define NRF_FICR_HAS_CODE_PAGE_SIZE 0 +#endif + +#if defined(FICR_INFO_CODEPAGESIZE_CODEPAGESIZE_Msk) || defined(__NRFX_DOXYGEN__) +/** @brief Symbol indicating whether FICR INFO.CODEPAGESIZE register is present. */ +#define NRF_FICR_HAS_INFO_CODE_PAGE_SIZE 1 +#else +#define NRF_FICR_HAS_INFO_CODE_PAGE_SIZE 0 +#endif + +#if defined(FICR_CODESIZE_CODESIZE_Msk) || defined(NRF51) || defined(__NRFX_DOXYGEN__) +/** @brief Symbol indicating whether FICR CODESIZE register is present. */ +#define NRF_FICR_HAS_CODE_SIZE 1 +#else +#define NRF_FICR_HAS_CODE_SIZE 0 +#endif + +#if defined(FICR_INFO_CODESIZE_CODESIZE_Msk) || defined(__NRFX_DOXYGEN__) +/** @brief Symbol indicating whether FICR INFO.CODESIZE register is present. */ +#define NRF_FICR_HAS_INFO_CODE_SIZE 1 +#else +#define NRF_FICR_HAS_INFO_CODE_SIZE 0 +#endif + +#if defined(FICR_DEVICEID_DEVICEID_Msk) || defined(NRF51) || defined(__NRFX_DOXYGEN__) +/** @brief Symbol indicating whether FICR DEVICEID[n] registers are present. */ +#define NRF_FICR_HAS_DEVICE_ID 1 +#else +#define NRF_FICR_HAS_DEVICE_ID 0 +#endif + +#if defined(FICR_INFO_DEVICEID_DEVICEID_Msk) || defined(__NRFX_DOXYGEN__) +/** @brief Symbol indicating whether FICR INFO.DEVICEID[n] registers are present. */ +#define NRF_FICR_HAS_INFO_DEVICE_ID 1 +#else +#define NRF_FICR_HAS_INFO_DEVICE_ID 0 +#endif + +#if defined(FICR_NFC_TAGHEADER0_MFGID_Msk) || defined(__NRFX_DOXYGEN__) +/** @brief Symbol indicating whether FICR NFC.TAGHEADERn registers are present. */ +#define NRF_FICR_HAS_NFC_TAGHEADER 1 +#else +#define NRF_FICR_HAS_NFC_TAGHEADER 0 +#endif + +#if defined(FICR_NFC_TAGHEADER_UD0_Msk) || defined(__NRFX_DOXYGEN__) +/** @brief Symbol indicating whether FICR NFC registers have tagheader array layout. */ +#define NRF_FICR_HAS_NFC_TAGHEADER_ARRAY 1 +#else +#define NRF_FICR_HAS_NFC_TAGHEADER_ARRAY 0 +#endif + +#if NRF_FICR_HAS_CODE_PAGE_SIZE || NRF_FICR_HAS_INFO_CODE_PAGE_SIZE /** * @brief Function for getting the size of the code memory page. * @@ -56,7 +113,9 @@ extern "C" { * @return Code memory page size in bytes. */ NRF_STATIC_INLINE uint32_t nrf_ficr_codepagesize_get(NRF_FICR_Type const * p_reg); +#endif +#if NRF_FICR_HAS_CODE_SIZE || NRF_FICR_HAS_INFO_CODE_SIZE /** * @brief Function for getting the size of the code memory rendered as number of pages. * @@ -65,7 +124,9 @@ NRF_STATIC_INLINE uint32_t nrf_ficr_codepagesize_get(NRF_FICR_Type const * p_reg * @return Code memory size rendered as number of pages. */ NRF_STATIC_INLINE uint32_t nrf_ficr_codesize_get(NRF_FICR_Type const * p_reg); +#endif +#if NRF_FICR_HAS_DEVICE_ID || NRF_FICR_HAS_INFO_DEVICE_ID /** * @brief Function for getting the unique device identifier. * @@ -75,8 +136,9 @@ NRF_STATIC_INLINE uint32_t nrf_ficr_codesize_get(NRF_FICR_Type const * p_reg); * @return Unique device identifier. */ NRF_STATIC_INLINE uint32_t nrf_ficr_deviceid_get(NRF_FICR_Type const * p_reg, uint32_t reg_id); +#endif -#if defined(FICR_NFC_TAGHEADER0_MFGID_Msk) || defined(__NRFX_DOXYGEN__) +#if NRF_FICR_HAS_NFC_TAGHEADER || NRF_FICR_HAS_NFC_TAGHEADER_ARRAY /** * @brief Function for getting the default header values for the NFC tag. * @@ -87,41 +149,61 @@ NRF_STATIC_INLINE uint32_t nrf_ficr_deviceid_get(NRF_FICR_Type const * p_reg, ui */ NRF_STATIC_INLINE uint32_t nrf_ficr_nfc_tagheader_get(NRF_FICR_Type const * p_reg, uint32_t tagheader_id); -#endif // defined(FICR_NFC_TAGHEADER0_MFGID_Msk) || defined(__NRFX_DOXYGEN__) +#endif #ifndef NRF_DECLARE_ONLY +#if NRF_FICR_HAS_CODE_PAGE_SIZE || NRF_FICR_HAS_INFO_CODE_PAGE_SIZE NRF_STATIC_INLINE uint32_t nrf_ficr_codepagesize_get(NRF_FICR_Type const * p_reg) { -#if defined(FICR_INFO_CODEPAGESIZE_CODEPAGESIZE_Msk) +#if NRF_FICR_HAS_INFO_CODE_PAGE_SIZE return p_reg->INFO.CODEPAGESIZE; #else return p_reg->CODEPAGESIZE; #endif } +#endif +#if NRF_FICR_HAS_CODE_SIZE || NRF_FICR_HAS_INFO_CODE_SIZE NRF_STATIC_INLINE uint32_t nrf_ficr_codesize_get(NRF_FICR_Type const * p_reg) { -#if defined(FICR_INFO_CODESIZE_CODESIZE_Msk) +#if NRF_FICR_HAS_INFO_CODE_SIZE return p_reg->INFO.CODESIZE; #else return p_reg->CODESIZE; #endif } +#endif +#if NRF_FICR_HAS_DEVICE_ID || NRF_FICR_HAS_INFO_DEVICE_ID NRF_STATIC_INLINE uint32_t nrf_ficr_deviceid_get(NRF_FICR_Type const * p_reg, uint32_t reg_id) { -#if defined(FICR_INFO_DEVICEID_DEVICEID_Msk) +#if NRF_FICR_HAS_INFO_DEVICE_ID return p_reg->INFO.DEVICEID[reg_id]; #else return p_reg->DEVICEID[reg_id]; #endif } +#endif -#if defined(FICR_NFC_TAGHEADER0_MFGID_Msk) +#if NRF_FICR_HAS_NFC_TAGHEADER || NRF_FICR_HAS_NFC_TAGHEADER_ARRAY NRF_STATIC_INLINE uint32_t nrf_ficr_nfc_tagheader_get(NRF_FICR_Type const * p_reg, uint32_t tagheader_id) { +#if NRF_FICR_HAS_NFC_TAGHEADER_ARRAY + switch(tagheader_id) { + case 0: + return p_reg->NFC.TAGHEADER[0]; + case 1: + return p_reg->NFC.TAGHEADER[1]; + case 2: + return p_reg->NFC.TAGHEADER[2]; + case 3: + return p_reg->NFC.TAGHEADER[3]; + default: + return 0; + } +#else switch(tagheader_id) { case 0: return p_reg->NFC.TAGHEADER0; @@ -134,8 +216,9 @@ NRF_STATIC_INLINE uint32_t nrf_ficr_nfc_tagheader_get(NRF_FICR_Type const * p_re default: return 0; } +#endif } -#endif // defined(FICR_NFC_TAGHEADER0_MFGID_Msk) +#endif #endif // NRF_DECLARE_ONLY diff --git a/hal/nrf_gpio.h b/hal/nrf_gpio.h index 8506c7372..f572b9516 100644 --- a/hal/nrf_gpio.h +++ b/hal/nrf_gpio.h @@ -44,13 +44,13 @@ extern "C" { #define NRF_P0 NRF_GPIO #endif -#if (GPIO_COUNT == 1) -#define NUMBER_OF_PINS (P0_PIN_NUM) -#define GPIO_REG_LIST {NRF_P0} -#elif (GPIO_COUNT == 2) -#define NUMBER_OF_PINS (P0_PIN_NUM + P1_PIN_NUM) -#define GPIO_REG_LIST {NRF_P0, NRF_P1} -#endif +#define GPIO_PORT_NUM(periph_name, prefix, i, _) i, +#define GPIO_REG(periph_name, prefix, i, _) NRFX_CONCAT(NRF_, periph_name, prefix, i), +#define GPIO_NUM_OF_PINS(periph_name, prefix, i, _) NRFX_CONCAT(periph_name, prefix, i, _PIN_NUM) + +#define GPIO_PORT_NUM_LIST {NRFX_FOREACH_PRESENT(P, GPIO_PORT_NUM, (), (), _)} +#define GPIO_REG_LIST {NRFX_FOREACH_PRESENT(P, GPIO_REG, (), (), _)} +#define NUMBER_OF_PINS {NRFX_FOREACH_PRESENT(P, GPIO_NUM_OF_PINS, (+), (0), _)} #if !defined(GPIO_REG_LIST) #error "Not supported." @@ -141,7 +141,7 @@ extern "C" { #define NRF_GPIO_HAS_PORT_IMPEDANCE 0 #endif -#if defined(GPIO_RETAIN_APPLICAION_Msk) || defined(__NRFX_DOXYGEN__) +#if defined(GPIO_RETAIN_ResetValue) || defined(__NRFX_DOXYGEN__) /** @brief Presence of register retention. */ #define NRF_GPIO_HAS_RETENTION 1 #else @@ -1299,7 +1299,7 @@ NRF_STATIC_INLINE bool nrf_gpio_pin_present_check(uint32_t pin_number) NRF_INTERNAL_GPIO_PORT_MASK_SET(mask); default: - NRFX_ASSERT(0); + return false; } #ifdef P0_FEATURE_PINS_PRESENT diff --git a/hal/nrf_nfct.h b/hal/nrf_nfct.h index 5d396b01f..836d86d3b 100644 --- a/hal/nrf_nfct.h +++ b/hal/nrf_nfct.h @@ -65,6 +65,63 @@ extern "C" { #define NRF_NFCID1_HAS_NEW_LAYOUT 0 #endif +#if defined(NFCT_TASKS_STOPTX_TASKS_STOPTX_Msk) || defined(__NRFX_DOXYGEN__) +/** @brief Symbol indicating whether NFCT STOPTX event is present. */ +#define NRF_NFCT_HAS_STOPTX_TASK 1 +#else +#define NRF_NFCT_HAS_STOPTX_TASK 0 +#endif + +#if defined(NFCT_MODULATIONPSEL_PIN_Msk) || defined(__NRFX_DOXYGEN__) +/** @brief Symbol indicating whether pin select for modulation control register is present. */ +#define NRF_NFCT_HAS_MODULATION_PSEL_REG 1 +#else +#define NRF_NFCT_HAS_MODULATION_PSEL_REG 0 +#endif + +#if defined(NFCT_MODULATIONCTRL_MODULATIONCTRL_Msk) || defined(__NRFX_DOXYGEN__) +/** @brief Symbol indicating whether modulation output select register is present. */ +#define NRF_NFCT_HAS_MODULATION_CTRL_REG 1 +#else +#define NRF_NFCT_HAS_MODULATION_CTRL_REG 0 +#endif + +#if defined(NFCT_NFCTAGSTATE_NFCTAGSTATE_Msk) || defined(__NRFX_DOXYGEN__) +/** @brief Symbol indicating whether current operating state of NFC tag register is present. */ +#define NRF_NFCT_HAS_TAG_STATE_REG 1 +#else +#define NRF_NFCT_HAS_TAG_STATE_REG 0 +#endif + +#if defined(NFCT_SLEEPSTATE_SLEEPSTATE_Msk) || defined(__NRFX_DOXYGEN__) +/** @brief Symbol indicating whether sleep state during automatic collision resolution is present. */ +#define NRF_NFCT_HAS_SLEEP_STATE_REG 1 +#else +#define NRF_NFCT_HAS_SLEEP_STATE_REG 0 +#endif + +#if defined (NFCT_AUTOCOLRESCONFIG_MODE_Msk) || defined(__NRFX_DOXYGEN__) +/** @brief Symbol indicating whether automatic collision resolution control register is present. */ +#define NRF_NFCT_HAS_AUTOCOLRES_CONFIG_REG 1 +#else +#define NRF_NFCT_HAS_AUTOCOLRES_CONFIG_REG 0 +#endif + +#if defined(NFCT_PADCONFIG_ENABLE_Msk) || defined(__NRFX_DOXYGEN__) +/** @brief Symbol indicating whether NFC pad configuration register is present. */ +#define NRF_NFCT_HAS_PAD_CONFIG_REG 1 +#else +#define NRF_NFCT_HAS_PAD_CONFIG_REG 0 +#endif + +#if defined(NFCT_BIASCFG_TRIMIBPSR_Msk) || defined(NFCT_BIASCFG_COARSEIBPSR_Msk) || \ + defined(NFCT_BIASCFG_REFERENCEVOLTAGE_Msk) || defined(NFCT_BIASCFG_SPARE_Msk) || \ + defined(__NRFX_DOXYGEN__) +/** @brief Symbol indicating whether NFC bias configuration trim register is present. */ +#define NRF_NFCT_HAS_BIAS_CONFIG_TRIM_REG 1 +#else +#define NRF_NFCT_HAS_BIAS_CONFIG_TRIM_REG 0 +#endif /** @brief NFCT tasks. */ typedef enum { @@ -72,6 +129,9 @@ typedef enum NRF_NFCT_TASK_DISABLE = offsetof(NRF_NFCT_Type, TASKS_DISABLE), /**< Disable the NFCT peripheral. */ NRF_NFCT_TASK_SENSE = offsetof(NRF_NFCT_Type, TASKS_SENSE), /**< Enable the NFC sense field mode, change state to sense mode. */ NRF_NFCT_TASK_STARTTX = offsetof(NRF_NFCT_Type, TASKS_STARTTX), /**< Start the transmission of an outgoing frame, change state to transmit. */ +#if NRF_NFCT_HAS_STOPTX_TASK + NRF_NFCT_TASK_STOPTX = offsetof(NRF_NFCT_Type, TASKS_STOPTX), /**< Stop an issued transmission of a frame. */ +#endif NRF_NFCT_TASK_ENABLERXDATA = offsetof(NRF_NFCT_Type, TASKS_ENABLERXDATA), /**< Initialize EasyDMA for receive. */ NRF_NFCT_TASK_GOIDLE = offsetof(NRF_NFCT_Type, TASKS_GOIDLE), /**< Force state machine to the IDLE state. */ NRF_NFCT_TASK_GOSLEEP = offsetof(NRF_NFCT_Type, TASKS_GOSLEEP), /**< Force state machine to the SLEEP_A state. */ @@ -104,7 +164,7 @@ typedef enum NRF_NFCT_SHORT_FIELDLOST_SENSE_MASK = NFCT_SHORTS_FIELDLOST_SENSE_Msk, /**< Shortcut between the FIELDLOST event and the SENSE task. */ #if defined(NFCT_SHORTS_TXFRAMEEND_ENABLERXDATA_Msk) || defined(__NRFX_DOXYGEN__) NRF_NFCT_SHORT_TXFRAMEEND_ENABLERXDATA_MASK = NFCT_SHORTS_TXFRAMEEND_ENABLERXDATA_Msk, /**< Shortcut between the TXFRAMEEND event and the ENABLERXDATA task. */ -#endif // defined(NFCT_SHORTS_TXFRAMEEND_ENABLERXDATA_Msk) || defined(__NRFX_DOXYGEN__) +#endif } nrf_nfct_short_mask_t; /** @brief NFCT interrupts. */ @@ -133,10 +193,10 @@ typedef enum NRF_NFCT_ERROR_FRAMEDELAYTIMEOUT_MASK = NFCT_ERRORSTATUS_FRAMEDELAYTIMEOUT_Msk, /**< Timeout of the Frame Delay Timer (no frame transmission started in the FDT window). */ #if defined(NFCT_ERRORSTATUS_NFCFIELDTOOSTRONG_Msk) || defined(__NRFX_DOXYGEN__) NRF_NFCT_ERROR_NFCFIELDTOOSTRONG_MASK = NFCT_ERRORSTATUS_NFCFIELDTOOSTRONG_Msk, /**< Field level is too high at maximum load resistance. */ -#endif // defined(NFCT_ERRORSTATUS_NFCFIELDTOOSTRONG_Msk) || defined(__NRFX_DOXYGEN__) +#endif #if defined(NFCT_ERRORSTATUS_NFCFIELDTOOWEAK_Msk) || defined(__NRFX_DOXYGEN__) NRF_NFCT_ERROR_NFCFIELDTOOWEAK_MASK = NFCT_ERRORSTATUS_NFCFIELDTOOWEAK_Msk, /**< Field level is too low at minimum load resistance. */ -#endif // defined(NFCT_ERRORSTATUS_NFCFIELDTOOWEAK_Msk) || defined(__NRFX_DOXYGEN__) +#endif } nrf_nfct_error_status_t; /** @brief NFC received frame status bit masks. */ @@ -147,7 +207,7 @@ typedef enum NRF_NFCT_RX_FRAME_STATUS_OVERRUN_MASK = NFCT_FRAMESTATUS_RX_OVERRUN_Msk, /**< Overrun status mask. */ } nrf_nfct_rx_frame_status_t; -#if defined(NFCT_NFCTAGSTATE_NFCTAGSTATE_Msk) || defined(__NRFX_DOXYGEN__) +#if NRF_NFCT_HAS_TAG_STATE_REG /** @brief NFC tag state. */ typedef enum { @@ -158,9 +218,9 @@ typedef enum NRF_NFCT_TAG_STATE_FRAME_DELAY = NFCT_NFCTAGSTATE_NFCTAGSTATE_FrameDelay, /**< Counting Frame Delay Time since the last symbol of the last received frame. */ NRF_NFCT_TAG_STATE_TRANSMIT = NFCT_NFCTAGSTATE_NFCTAGSTATE_Transmit /**< Transmitting data. */ } nrf_nfct_tag_state_t; -#endif // defined(NFCT_NFCTAGSTATE_NFCTAGSTATE_Msk) || defined(__NRFX_DOXYGEN__) +#endif // NRF_NFCT_HAS_TAG_STATE_REG -#if defined (NFCT_SLEEPSTATE_SLEEPSTATE_Msk) || defined(__NRFX_DOXYGEN__) +#if NRF_NFCT_HAS_SLEEP_STATE_REG /** * @brief NFC tag sleep state. * @@ -172,7 +232,7 @@ typedef enum NRF_NFCT_SLEEP_STATE_IDLE = NFCT_SLEEPSTATE_SLEEPSTATE_Idle, /**< 'IDLE' state. */ NRF_NFCT_SLEEP_STATE_SLEEP_A = NFCT_SLEEPSTATE_SLEEPSTATE_SleepA /**< 'SLEEP_A' state. */ } nrf_nfct_sleep_state_t; -#endif // defined (NFCT_SLEEPSTATE_SLEEPSTATE_Msk) || defined(__NRFX_DOXYGEN__) +#endif // NRF_NFCT_HAS_SLEEP_STATE_REG /** @brief NFC field state bit masks. */ typedef enum @@ -223,6 +283,15 @@ typedef enum NFCT_SENSRES_NFCIDSIZE_Msk /**< Default size. Use this option to leave NFCID1 size unchanged. */ } nrf_nfct_sensres_nfcid1_size_t; +/** @brief Bias trim configuration. */ +typedef struct +{ + uint8_t trim_ibpsr; /**< Fine trim IBPSR 4 µA bias current. */ + uint8_t coarse_ibpsr; /**< Coarse trim IBPSR 4 µA. */ + uint8_t reference_volatge; /**< Reference voltage level. */ + uint8_t spare; /**< Spare. */ +} nrf_nfct_bias_config_t; + /** * @brief 'Bit frame SDD' NFC field configuration for the SENS_RES frame according to the NFC * Forum Digital Protocol Technical Specification. @@ -267,7 +336,7 @@ typedef enum NRF_NFCT_SELRES_PROTOCOL_NFCDEP_T4AT = 3, /**< NFC-DEP Protocol and Type 4A Tag platform). */ } nrf_nfct_selres_protocol_t; -#if defined(NFCT_MODULATIONCTRL_MODULATIONCTRL_Msk) || defined(__NRFX_DOXYGEN__) +#if NRF_NFCT_HAS_MODULATION_CTRL_REG /** @brief Modulation output configuration. */ typedef enum { @@ -276,7 +345,7 @@ typedef enum NRF_NFCT_MODULATION_CTRL_GPIO = NFCT_MODULATIONCTRL_MODULATIONCTRL_ModToGpio, /**< Transmit output digital modulation signal to a GPIO pin. */ NRF_NFCT_MODULATION_CTRL_INTERNAL_GPIO = NFCT_MODULATIONCTRL_MODULATIONCTRL_InternalAndModToGpio /**< Use internal modulator and transmit output digital modulation signal to a GPIO pin. */ } nrf_nfct_modulation_ctrl_t; -#endif // defined(NFCT_MODULATIONCTRL_MODULATIONCTRL_Msk) || defined(__NRFX_DOXYGEN__) +#endif // NRF_NFCT_HAS_MODULATION_CTRL_REG /** * @brief Function for activating a specific NFCT task. @@ -395,8 +464,7 @@ NRF_STATIC_INLINE uint32_t nrf_nfct_int_enable_get(NRF_NFCT_Type const * p_reg); */ NRF_STATIC_INLINE void nrf_nfct_int_disable(NRF_NFCT_Type * p_reg, uint32_t mask); -#if defined(NFCT_MODULATIONPSEL_PIN_Msk) || defined(__NRFX_DOXYGEN__) - +#if NRF_NFCT_HAS_MODULATION_PSEL_REG /** * @brief Function for configuring the NFCT modulation control pin. * @@ -416,9 +484,9 @@ NRF_STATIC_INLINE void nrf_nfct_mod_ctrl_pin_set(NRF_NFCT_Type * p_reg, uint32_t * @return Modulation control pin selection. */ NRF_STATIC_INLINE uint32_t nrf_nfct_mod_ctrl_pin_get(NRF_NFCT_Type const * p_reg); -#endif // defined(NFCT_MODULATIONPSEL_PIN_Msk) || defined(__NRFX_DOXYGEN__) +#endif // NRF_NFCT_HAS_MODULATION_PSEL_REG -#if defined(NFCT_MODULATIONCTRL_MODULATIONCTRL_Msk) || defined(__NRFX_DOXYGEN__) +#if NRF_NFCT_HAS_MODULATION_CTRL_REG /** * @brief Function for setting the modulation output. It enables the * output to a GPIO pin which can be connected to a second external. @@ -438,7 +506,7 @@ NRF_STATIC_INLINE void nrf_nfct_modulation_output_set(NRF_NFCT_Type * */ NRF_STATIC_INLINE nrf_nfct_modulation_ctrl_t nrf_nfct_modulation_output_get(NRF_NFCT_Type const * p_reg); -#endif // defined(NFCT_MODULATIONCTRL_MODULATIONCTRL_Msk) || defined(__NRFX_DOXYGEN__) +#endif // NRF_NFCT_HAS_MODULATION_CTRL_REG /** * @brief Function for getting the NFCT error status. @@ -476,7 +544,7 @@ NRF_STATIC_INLINE uint32_t nrf_nfct_rx_frame_status_get(NRF_NFCT_Type const * p_ NRF_STATIC_INLINE void nrf_nfct_rx_frame_status_clear(NRF_NFCT_Type * p_reg, uint32_t framestatus_flags); -#if defined(NFCT_NFCTAGSTATE_NFCTAGSTATE_Msk) || defined(__NRFX_DOXYGEN__) +#if NRF_NFCT_HAS_TAG_STATE_REG /** * @brief Function for getting the NFC tag state. * @@ -491,9 +559,9 @@ NRF_STATIC_INLINE void nrf_nfct_rx_frame_status_clear(NRF_NFCT_Type * p_reg, * @retval NRF_NFCT_TAG_STATE_TRANSMIT NFC tag is transmitting data. */ NRF_STATIC_INLINE nrf_nfct_tag_state_t nrf_nfct_tag_state_get(NRF_NFCT_Type const * p_reg); -#endif // defined(NFCT_NFCTAGSTATE_NFCTAGSTATE_Msk) || defined(__NRFX_DOXYGEN__) +#endif // NRF_NFCT_HAS_TAG_STATE_REG -#if defined (NFCT_SLEEPSTATE_SLEEPSTATE_Msk) || defined(__NRFX_DOXYGEN__) +#if NRF_NFCT_HAS_SLEEP_STATE_REG /** * @brief Function for getting the NFC tag sleep state during the automatic collision resolution. * @@ -507,7 +575,7 @@ NRF_STATIC_INLINE nrf_nfct_tag_state_t nrf_nfct_tag_state_get(NRF_NFCT_Type cons * collision resolution started. */ NRF_STATIC_INLINE nrf_nfct_sleep_state_t nrf_nfct_sleep_state_get(NRF_NFCT_Type const * p_reg); -#endif // defined (NFCT_SLEEPSTATE_SLEEPSTATE_Msk) || defined(__NRFX_DOXYGEN__) +#endif // NRF_NFCT_HAS_SLEEP_STATE_REG /** * @brief Function for getting the status of the external NFC field detection. @@ -734,7 +802,7 @@ NRF_STATIC_INLINE void nrf_nfct_nfcid1_set(NRF_NFCT_Type * p_reg, uint8_t const * p_nfcid1_buf, nrf_nfct_sensres_nfcid1_size_t nfcid1_size); -#if defined (NFCT_AUTOCOLRESCONFIG_MODE_Msk) || defined(__NRFX_DOXYGEN__) +#if NRF_NFCT_HAS_AUTOCOLRES_CONFIG_REG /** * @brief Function for getting the setting for the automatic collision resolution. * @@ -767,7 +835,7 @@ NRF_STATIC_INLINE void nrf_nfct_autocolres_enable(NRF_NFCT_Type * p_reg); * Digital Protocol Technical Specification 2.0, section 6. */ NRF_STATIC_INLINE void nrf_nfct_autocolres_disable(NRF_NFCT_Type * p_reg); -#endif // defined (NFCT_AUTOCOLRESCONFIG_MODE_Msk) || defined(__NRFX_DOXYGEN__) +#endif // NRF_NFCT_HAS_AUTOCOLRES_CONFIG_REG /** * @brief Function for getting the NFCID1 size from the SENS_RES frame configuration. @@ -902,6 +970,54 @@ NRF_STATIC_INLINE uint32_t nrf_nfct_selres_get(NRF_NFCT_Type const * p_reg); */ NRF_STATIC_INLINE void nrf_nfct_selres_set(NRF_NFCT_Type * p_reg, uint32_t selres); +#if NRF_NFCT_HAS_PAD_CONFIG_REG +/** + * @brief Function for enabling or disabling the NFC pad configuration. + * + * @details When the NFC pads are enabled, they are configured as the NFC + * antenna pins, and the NFC pins protection mechanism is enabled. + * When the NFC pads are disabled, they are configured as GPIO pins. + * + * @param[in] p_reg Pointer to the structure of registers of the peripheral. + * @param[in] enable True if the NFC pads are to be enabled, false otherwise. + */ +NRF_STATIC_INLINE void nrf_nfct_pad_config_enable_set(NRF_NFCT_Type * p_reg, bool enable); + +/** + * @brief Function for checking the NFC pads configuration. + * + * @details When the NFC pads are enabled, they are configured as the NFC + * antenna pins, and the NFC pins protection mechanism is enabled. + * When the NFC pads are disabled, they are configured as GPIO pins. + * + * @param[in] p_reg Pointer to the structure of registers of the peripheral. + * + * @retval true NFC pads are enabled. + * @retval false NFC pads are disabled. + */ +NRF_STATIC_INLINE bool nrf_nfct_pad_config_enable_check(NRF_NFCT_Type const * p_reg); +#endif // NRF_NFCT_HAS_PAD_CONFIG_REG + +#if NRF_NFCT_HAS_BIAS_CONFIG_TRIM_REG +/** + * @brief Function for setting the bias configuration. + * + * @param[in] p_reg Pointer to the structure of registers of the peripheral. + * @param[in] p_bias_config Pointer to the structure of bias configuration parameters. + */ +NRF_STATIC_INLINE void nrf_nfct_bias_config_set(NRF_NFCT_Type * p_reg, + nrf_nfct_bias_config_t const * p_bias_config); + +/** + * @brief Function for getting the bias configuration. + * + * @param[in] p_reg Pointer to the structure of registers of the peripheral. + * @param[in] p_bias_config Pointer to the structure to be filled with bias configuration parameters. + */ +NRF_STATIC_INLINE void nrf_nfct_bias_config_get(NRF_NFCT_Type const * p_reg, + nrf_nfct_bias_config_t * p_bias_config); +#endif // NRF_NFCT_HAS_BIAS_CONFIG_TRIM_REG + #ifndef NRF_DECLARE_ONLY NRF_STATIC_INLINE void nrf_nfct_task_trigger(NRF_NFCT_Type * p_reg, nrf_nfct_task_t task) { @@ -971,7 +1087,7 @@ NRF_STATIC_INLINE void nrf_nfct_int_disable(NRF_NFCT_Type * p_reg, uint32_t mask p_reg->INTENCLR = mask; } -#if defined(NFCT_MODULATIONPSEL_PIN_Msk) +#if NRF_NFCT_HAS_MODULATION_PSEL_REG NRF_STATIC_INLINE void nrf_nfct_mod_ctrl_pin_set(NRF_NFCT_Type * p_reg, uint32_t mod_ctrl_pin) { p_reg->MODULATIONPSEL = mod_ctrl_pin; @@ -981,9 +1097,9 @@ NRF_STATIC_INLINE uint32_t nrf_nfct_mod_ctrl_pin_get(NRF_NFCT_Type const * p_reg { return p_reg->MODULATIONPSEL; } -#endif // (NFCT_MODULATIONPSEL_PIN_Msk) +#endif // NRF_NFCT_HAS_MODULATION_PSEL_REG -#if defined(NFCT_MODULATIONCTRL_MODULATIONCTRL_Msk) +#if NRF_NFCT_HAS_MODULATION_CTRL_REG NRF_STATIC_INLINE void nrf_nfct_modulation_output_set(NRF_NFCT_Type * p_reg, nrf_nfct_modulation_ctrl_t mod_ctrl) { @@ -996,7 +1112,7 @@ nrf_nfct_modulation_ctrl_t nrf_nfct_modulation_output_get(NRF_NFCT_Type const * return (nrf_nfct_modulation_ctrl_t)(p_reg->MODULATIONCTRL & NFCT_MODULATIONCTRL_MODULATIONCTRL_Msk); } -#endif // defined(NFCT_MODULATIONCTRL_MODULATIONCTRL_Msk) +#endif // NRF_NFCT_HAS_MODULATION_CTRL_REG NRF_STATIC_INLINE uint32_t nrf_nfct_error_status_get(NRF_NFCT_Type const * p_reg) { @@ -1019,21 +1135,21 @@ NRF_STATIC_INLINE void nrf_nfct_rx_frame_status_clear(NRF_NFCT_Type * p_reg, p_reg->FRAMESTATUS.RX = framestatus_flags; } -#if defined(NFCT_NFCTAGSTATE_NFCTAGSTATE_Msk) || defined(__NRFX_DOXYGEN__) +#if NRF_NFCT_HAS_TAG_STATE_REG NRF_STATIC_INLINE nrf_nfct_tag_state_t nrf_nfct_tag_state_get(NRF_NFCT_Type const * p_reg) { return (nrf_nfct_tag_state_t)((p_reg->NFCTAGSTATE & NFCT_NFCTAGSTATE_NFCTAGSTATE_Msk) >> NFCT_NFCTAGSTATE_NFCTAGSTATE_Pos); } -#endif // defined(NFCT_NFCTAGSTATE_NFCTAGSTATE_Msk) || defined(__NRFX_DOXYGEN__) +#endif // NRF_NFCT_HAS_TAG_STATE_REG -#if defined (NFCT_SLEEPSTATE_SLEEPSTATE_Msk) || defined(__NRFX_DOXYGEN__) +#if NRF_NFCT_HAS_SLEEP_STATE_REG NRF_STATIC_INLINE nrf_nfct_sleep_state_t nrf_nfct_sleep_state_get(NRF_NFCT_Type const * p_reg) { return (nrf_nfct_sleep_state_t)((p_reg->SLEEPSTATE & NFCT_SLEEPSTATE_SLEEPSTATE_Msk) >> NFCT_SLEEPSTATE_SLEEPSTATE_Pos); } -#endif // defined (NFCT_SLEEPSTATE_SLEEPSTATE_Msk) || defined(__NRFX_DOXYGEN__) +#endif // NRF_NFCT_HAS_SLEEP_STATE_REG NRF_STATIC_INLINE uint8_t nrf_nfct_field_status_get(NRF_NFCT_Type const * p_reg) { @@ -1228,7 +1344,7 @@ NRF_STATIC_INLINE void nrf_nfct_nfcid1_set(NRF_NFCT_Type * p_reg, (uint32_t)size); } -#if defined (NFCT_AUTOCOLRESCONFIG_MODE_Msk) || defined(__NRFX_DOXYGEN__) +#if NRF_NFCT_HAS_AUTOCOLRES_CONFIG_REG NRF_STATIC_INLINE bool nrf_nfct_autocolres_is_enabled(NRF_NFCT_Type const * p_reg) { return (p_reg->AUTOCOLRESCONFIG & NFCT_AUTOCOLRESCONFIG_MODE_Msk) == @@ -1248,7 +1364,7 @@ NRF_STATIC_INLINE void nrf_nfct_autocolres_disable(NRF_NFCT_Type * p_reg) (p_reg->AUTOCOLRESCONFIG & ~NFCT_AUTOCOLRESCONFIG_MODE_Msk) | (NFCT_AUTOCOLRESCONFIG_MODE_Disabled << NFCT_AUTOCOLRESCONFIG_MODE_Pos); } -#endif // defined (NFCT_AUTOCOLRESCONFIG_MODE_Msk) || defined(__NRFX_DOXYGEN__) +#endif // NRF_NFCT_HAS_AUTOCOLRES_CONFIG_REG NRF_STATIC_INLINE nrf_nfct_sensres_nfcid1_size_t nrf_nfct_sensres_nfcid1_size_get(NRF_NFCT_Type const * p_reg) @@ -1270,7 +1386,7 @@ nrf_nfct_sensres_bit_frame_sdd_t nrf_nfct_sensres_bit_frame_sdd_get(NRF_NFCT_Typ } NRF_STATIC_INLINE -void nrf_nfct_sensres_bit_frame_sdd_set(NRF_NFCT_Type * p_reg, +void nrf_nfct_sensres_bit_frame_sdd_set(NRF_NFCT_Type * p_reg, nrf_nfct_sensres_bit_frame_sdd_t bit_frame_sdd) { p_reg->SENSRES = ((p_reg->SENSRES & ~(NFCT_SENSRES_BITFRAMESDD_Msk)) | (uint32_t)bit_frame_sdd); @@ -1283,7 +1399,7 @@ nrf_nfct_sensres_platform_config_t nrf_nfct_sensres_platform_config_get(NRF_NFCT } NRF_STATIC_INLINE -void nrf_nfct_sensres_platform_config_set(NRF_NFCT_Type * p_reg, +void nrf_nfct_sensres_platform_config_set(NRF_NFCT_Type * p_reg, nrf_nfct_sensres_platform_config_t platform_config) { p_reg->SENSRES = ((p_reg->SENSRES & ~(NFCT_SENSRES_PLATFCONFIG_Msk)) | @@ -1318,6 +1434,61 @@ NRF_STATIC_INLINE void nrf_nfct_selres_set(NRF_NFCT_Type * p_reg, uint32_t selre { p_reg->SELRES = (p_reg->SELRES & NFCT_SELRES_CASCADE_Msk) | (selres & ~NFCT_SELRES_CASCADE_Msk); } + +#if NRF_NFCT_HAS_PAD_CONFIG_REG +NRF_STATIC_INLINE void nrf_nfct_pad_config_enable_set(NRF_NFCT_Type * p_reg, bool enable) +{ + p_reg->PADCONFIG = (enable ? + NFCT_PADCONFIG_ENABLE_Enabled : + NFCT_PADCONFIG_ENABLE_Disabled) << + NFCT_PADCONFIG_ENABLE_Pos; +} + +NRF_STATIC_INLINE bool nrf_nfct_pad_config_enable_check(NRF_NFCT_Type const * p_reg) +{ + return (bool)(((p_reg->PADCONFIG & NFCT_PADCONFIG_ENABLE_Msk) >> NFCT_PADCONFIG_ENABLE_Pos)); +} +#endif // NRF_NFCT_HAS_PAD_CONFIG_REG + +#if NRF_NFCT_HAS_BIAS_CONFIG_TRIM_REG +NRF_STATIC_INLINE void nrf_nfct_bias_config_set(NRF_NFCT_Type * p_reg, + nrf_nfct_bias_config_t const * p_bias_config) +{ + NRFX_ASSERT(p_bias_config != NULL); + + p_reg->BIASCFG = (((p_bias_config->trim_ibpsr << + NFCT_BIASCFG_TRIMIBPSR_Pos) & + NFCT_BIASCFG_TRIMIBPSR_Msk) | + ((p_bias_config->coarse_ibpsr << + NFCT_BIASCFG_COARSEIBPSR_Pos) & + NFCT_BIASCFG_COARSEIBPSR_Msk) | + ((p_bias_config->reference_volatge << + NFCT_BIASCFG_REFERENCEVOLTAGE_Pos) & + NFCT_BIASCFG_REFERENCEVOLTAGE_Msk) | + ((p_bias_config->spare << + NFCT_BIASCFG_SPARE_Pos) & + NFCT_BIASCFG_SPARE_Msk)); +} + +NRF_STATIC_INLINE void nrf_nfct_bias_config_get(NRF_NFCT_Type const * p_reg, + nrf_nfct_bias_config_t * p_bias_config) +{ + NRFX_ASSERT(p_bias_config != NULL); + + p_bias_config->trim_ibpsr = (p_reg->BIASCFG & NFCT_BIASCFG_TRIMIBPSR_Msk) + >> NFCT_BIASCFG_TRIMIBPSR_Pos; + + p_bias_config->coarse_ibpsr = (p_reg->BIASCFG & NFCT_BIASCFG_COARSEIBPSR_Msk) + >> NFCT_BIASCFG_COARSEIBPSR_Pos; + + p_bias_config->reference_volatge = (p_reg->BIASCFG & NFCT_BIASCFG_REFERENCEVOLTAGE_Msk) + >> NFCT_BIASCFG_REFERENCEVOLTAGE_Pos; + + p_bias_config->spare = (p_reg->BIASCFG & NFCT_BIASCFG_SPARE_Msk) + >> NFCT_BIASCFG_SPARE_Pos; +} +#endif // NRF_NFCT_HAS_BIAS_CONFIG_TRIM_REG + #endif /* NRF_DECLARE_ONLY */ /** @} */ diff --git a/hal/nrf_nvmc.h b/hal/nrf_nvmc.h index 78904c68a..b3c8d9830 100644 --- a/hal/nrf_nvmc.h +++ b/hal/nrf_nvmc.h @@ -133,6 +133,79 @@ NRF_STATIC_INLINE void nrf_nvmc_nonsecure_mode_set(NRF_NVMC_Type * p_reg, nrf_nvmc_ns_mode_t mode); #endif +/** + * @brief Function for writing a 32-bit word to flash. + * + * @note Before calling this function, the caller must ensure that: + * - the @p address is word-aligned, + * - write mode is enabled, using @ref nrf_nvmc_mode_set, + * - the NVMC is ready to accept another write, using + * @ref nrf_nvmc_ready_check or @ref nrf_nvmc_write_ready_check, + * - read-only mode is enabled as soon as writing is no longer needed, + * using @ref nrf_nvmc_mode_set. + * + * @warning It is recommended to use @ref nrfx_nvmc_word_write function instead. + * + * Using this function when accessing the flash gives the possibility + * to run the code in an environment where the flash is simulated. + * + * @param[in] address Address of the word to write. + * @param[in] value Value to write. + */ +NRF_STATIC_INLINE void nrf_nvmc_word_write(uint32_t address, + uint32_t value); + +/** + * @brief Function for reading a byte from the flash. + * + * Using this function when accessing the flash gives the possibility + * to run the code in an environment where the flash is simulated. + * + * @param[in] address Address of the byte to read. + * + * @return Value read from flash. + */ +NRF_STATIC_INLINE uint8_t nrf_nvmc_byte_read(uint32_t address); + +/** + * @brief Function for reading a 16-bit halfword from the flash. + * + * Using this function when accessing the flash gives the possibility + * to run the code in an environment where the flash is simulated. + * + * @param[in] address Address of the halfword to read. + * + * @return Value read from flash. + */ +NRF_STATIC_INLINE uint16_t nrf_nvmc_halfword_read(uint32_t address); + +/** + * @brief Function for reading a 32-bit word from the flash. + * + * Using this function when accessing the flash gives the possibility + * to run the code in an environment where the flash is simulated. + * + * @param[in] address Address of the word to read. + * + * @return Value read from flash. + */ +NRF_STATIC_INLINE uint32_t nrf_nvmc_word_read(uint32_t address); + +/** + * @brief Function for reading a given number of bytes from the flash into the specified buffer. + * + * Using this function when accessing the flash gives the possibility + * to run the code in an environment where the flash is simulated. + * + * @param[in] dst Pointer to the buffer to store the data. + * @param[in] address Address of the first byte to read. + * @param[in] num_bytes Number of bytes to read. + * + */ +NRF_STATIC_INLINE void nrf_nvmc_buffer_read(void * dst, + uint32_t address, + uint32_t num_bytes); + /** * @brief Function for starting a single page erase in the Flash memory. * @@ -282,6 +355,34 @@ NRF_STATIC_INLINE void nrf_nvmc_nonsecure_mode_set(NRF_NVMC_Type * p_reg, } #endif +NRF_STATIC_INLINE void nrf_nvmc_word_write(uint32_t address, + uint32_t value) +{ + *(volatile uint32_t *)address = value; +} + +NRF_STATIC_INLINE uint8_t nrf_nvmc_byte_read(uint32_t address) +{ + return *(volatile uint8_t *)address; +} + +NRF_STATIC_INLINE uint16_t nrf_nvmc_halfword_read(uint32_t address) +{ + return *(volatile uint16_t *)address; +} + +NRF_STATIC_INLINE uint32_t nrf_nvmc_word_read(uint32_t address) +{ + return *(volatile uint32_t *)address; +} + +NRF_STATIC_INLINE void nrf_nvmc_buffer_read(void * dst, + uint32_t address, + uint32_t num_bytes) +{ + memcpy(dst, (void *)address, num_bytes); +} + NRF_STATIC_INLINE void nrf_nvmc_page_erase_start(NRF_NVMC_Type * p_reg, uint32_t page_addr) { diff --git a/hal/nrf_power.h b/hal/nrf_power.h index 0aaff79c2..ec9338a0c 100644 --- a/hal/nrf_power.h +++ b/hal/nrf_power.h @@ -48,6 +48,20 @@ extern "C" { * @brief Hardware access layer for managing the POWER peripheral. */ +#if defined(POWER_TASKS_CONSTLAT_TASKS_CONSTLAT_Msk) || defined(NRF51) || defined(__NRFX_DOXYGEN__) +/** @brief Symbol indicating whether Constant Latency mode is present. */ +#define NRF_POWER_HAS_CONST_LATENCY 1 +#else +#define NRF_POWER_HAS_CONST_LATENCY 0 +#endif + +#if defined(POWER_TASKS_LOWPWR_TASKS_LOWPWR_Msk) || defined(NRF51) || defined(__NRFX_DOXYGEN__) +/** @brief Symbol indicating whether Low-Power mode is present. */ +#define NRF_POWER_HAS_LOW_POWER 1 +#else +#define NRF_POWER_HAS_LOW_POWER 0 +#endif + #if defined(POWER_INTENSET_SLEEPENTER_Msk) || defined(__NRFX_DOXYGEN__) /** @brief Symbol indicating whether sleep events are present. */ #define NRF_POWER_HAS_SLEEPEVT 1 @@ -111,6 +125,13 @@ extern "C" { #define NRF_POWER_HAS_MAINREGSTATUS 0 #endif +#if defined(POWER_GPREGRET_GPREGRET_Msk) || defined(__NRFX_DOXYGEN__) +/** @brief Symbol indicating whether GPREGRET register is present. */ +#define NRF_POWER_HAS_GPREGRET 1 +#else +#define NRF_POWER_HAS_GPREGRET 0 +#endif + #if (!defined(POWER_GPREGRET2_GPREGRET_Msk) && !defined(NRF51)) || defined(__NRFX_DOXYGEN__) /** @brief Symbol indicating whether GPREGRET register is treated as an array. */ #define NRF_POWER_HAS_GPREGRET_ARRAY 1 @@ -118,27 +139,104 @@ extern "C" { #define NRF_POWER_HAS_GPREGRET_ARRAY 0 #endif +#if defined(POWER_TASKS_SEMAPHORE_ACQUIRE_ACQUIRE_Msk) || defined(__NRFX_DOXYGEN__) +/** @brief Symbol indicating whether semaphore for regulator voltage scaling procedure is present. */ +#define NRF_POWER_HAS_SEMAPHORE 1 +#else +#define NRF_POWER_HAS_SEMAPHORE 0 +#endif + +#if (defined(POWER_TASKS_REGUPDATE_TASKS_REGUPDATE_Msk) && \ + defined(POWER_EVENTS_REGUPDATED_EVENTS_REGUPDATED_Msk)) || defined(__NRFX_DOXYGEN__) +/** @brief Symbol indicating whether task and event responsible for updating voltage regulators configuration are present. */ +#define NRF_POWER_HAS_VREG_UPDATE_TASK_EVENT 1 +#else +#define NRF_POWER_HAS_VREG_UPDATE_TASK_EVENT 0 +#endif + +#if defined(POWER_REGCONFIG_VREG1V8_Msk) || defined(__NRFX_DOXYGEN__) +/** @brief Symbol indicating whether voltage regulators are configurable. */ +#define NRF_POWER_HAS_VREG_CONFIG 1 +#else +#define NRF_POWER_HAS_VREG_CONFIG 0 +#endif + +#if defined(POWER_EVENTS_ABBLOCK_EVENTS_ABBLOCK_Msk) || defined(__NRFX_DOXYGEN__) +/** @brief Symbol indicating whether the Adaptive Body Biasing (ABB) domains are present. */ +#define NRF_POWER_HAS_ABB 1 +#else +#define NRF_POWER_HAS_ABB 0 +#endif + +#if defined(POWER_BLOCKULPMODE_BLOCK_Msk) || defined(__NRFX_DOXYGEN__) +/** @brief Symbol indicating whether the power block modes are present. */ +#define NRF_POWER_HAS_BLOCK_MODES 1 +#else +#define NRF_POWER_HAS_BLOCK_MODES 0 +#endif + +#if defined(POWER_BILSENABLE_ENABLE_Msk) || defined(__NRFX_DOXYGEN__) +/** @brief Symbol indicating whether the Built-in Leakage Sensors (BILS) are present. */ +#define NRF_POWER_HAS_BILS 1 +#else +#define NRF_POWER_HAS_BILS 0 +#endif + +#if defined(POWER_PMICENABLE_ENABLE_Msk) || defined(__NRFX_DOXYGEN__) +/** @brief Symbol indicating whether the Power Management IC (PMIC) is present. */ +#define NRF_POWER_HAS_PMIC 1 +#else +#define NRF_POWER_HAS_PMIC 0 +#endif + +#if NRF_POWER_HAS_ABB +/** @brief Symbol specifying the maximum number of available @p ABB_LOCK events. */ +#define NRF_POWER_EVENTS_ABB_LOCK_COUNT POWER_EVENTS_ABBLOCK_MaxCount +#endif + /** @brief POWER tasks. */ typedef enum { - NRF_POWER_TASK_CONSTLAT = offsetof(NRF_POWER_Type, TASKS_CONSTLAT), /**< Enable constant latency mode. */ - NRF_POWER_TASK_LOWPWR = offsetof(NRF_POWER_Type, TASKS_LOWPWR ), /**< Enable low-power mode (variable latency). */ +#if NRF_POWER_HAS_CONST_LATENCY + NRF_POWER_TASK_CONSTLAT = offsetof(NRF_POWER_Type, TASKS_CONSTLAT), ///< Enable constant latency mode. +#endif +#if NRF_POWER_HAS_LOW_POWER + NRF_POWER_TASK_LOWPWR = offsetof(NRF_POWER_Type, TASKS_LOWPWR), ///< Enable low-power mode (variable latency). +#endif +#if NRF_POWER_HAS_SEMAPHORE + NRF_POWER_TASK_SEMAPHORE_ACQUIRE = offsetof(NRF_POWER_Type, TASKS_SEMAPHORE.ACQUIRE), ///< Acquire the semaphore for regulator voltage scaling procedure. + NRF_POWER_TASK_SEMAPHORE_RELEASE = offsetof(NRF_POWER_Type, TASKS_SEMAPHORE.RELEASE), ///< Release the semaphore for regulator voltage scaling procedure. +#endif +#if NRF_POWER_HAS_VREG_UPDATE_TASK_EVENT + NRF_POWER_TASK_REGULATOR_UPDATE = offsetof(NRF_POWER_Type, TASKS_REGUPDATE), ///< Update the regulator configuration. +#endif } nrf_power_task_t; /** @brief POWER events. */ typedef enum { #if NRF_POWER_HAS_POFWARN - NRF_POWER_EVENT_POFWARN = offsetof(NRF_POWER_Type, EVENTS_POFWARN ), /**< Power failure warning. */ + NRF_POWER_EVENT_POFWARN = offsetof(NRF_POWER_Type, EVENTS_POFWARN), ///< Power failure warning. #endif #if NRF_POWER_HAS_SLEEPEVT - NRF_POWER_EVENT_SLEEPENTER = offsetof(NRF_POWER_Type, EVENTS_SLEEPENTER ), /**< CPU entered WFI/WFE sleep. */ - NRF_POWER_EVENT_SLEEPEXIT = offsetof(NRF_POWER_Type, EVENTS_SLEEPEXIT ), /**< CPU exited WFI/WFE sleep. */ + NRF_POWER_EVENT_SLEEPENTER = offsetof(NRF_POWER_Type, EVENTS_SLEEPENTER), ///< CPU entered WFI/WFE sleep mode. + NRF_POWER_EVENT_SLEEPEXIT = offsetof(NRF_POWER_Type, EVENTS_SLEEPEXIT), ///< CPU exited WFI/WFE sleep mode. #endif #if NRF_POWER_HAS_USBREG - NRF_POWER_EVENT_USBDETECTED = offsetof(NRF_POWER_Type, EVENTS_USBDETECTED), /**< Voltage supply detected on VBUS. */ - NRF_POWER_EVENT_USBREMOVED = offsetof(NRF_POWER_Type, EVENTS_USBREMOVED ), /**< Voltage supply removed from VBUS. */ - NRF_POWER_EVENT_USBPWRRDY = offsetof(NRF_POWER_Type, EVENTS_USBPWRRDY ), /**< USB 3.3 V supply ready. */ + NRF_POWER_EVENT_USBDETECTED = offsetof(NRF_POWER_Type, EVENTS_USBDETECTED), ///< Voltage supply detected on VBUS. + NRF_POWER_EVENT_USBREMOVED = offsetof(NRF_POWER_Type, EVENTS_USBREMOVED), ///< Voltage supply removed from VBUS. + NRF_POWER_EVENT_USBPWRRDY = offsetof(NRF_POWER_Type, EVENTS_USBPWRRDY), ///< USB 3.3 V supply ready. +#endif +#if NRF_POWER_HAS_SEMAPHORE + NRF_POWER_EVENT_SEMAPHORE_ACQUIRED = offsetof(NRF_POWER_Type, EVENTS_SEMAPHORE.ACQUIRED), ///< Acquired the semaphore for regulator voltage scaling procedure. + NRF_POWER_EVENT_SEMAPHORE_RELEASED = offsetof(NRF_POWER_Type, EVENTS_SEMAPHORE.RELEASED), ///< Released the semaphore for regulator voltage scaling procedure. +#endif +#if NRF_POWER_HAS_VREG_UPDATE_TASK_EVENT + NRF_POWER_EVENT_REGULATOR_UPDATED = offsetof(NRF_POWER_Type, EVENTS_REGUPDATED), ///< Updated the regulator configuration. +#endif +#if NRF_POWER_HAS_ABB + NRF_POWER_EVENT_ABB_LOCK_0 = offsetof(NRF_POWER_Type, EVENTS_ABBLOCK[0]), ///< ABB lock for the ABB domain 0. + NRF_POWER_EVENT_ABB_LOCK_1 = offsetof(NRF_POWER_Type, EVENTS_ABBLOCK[1]), ///< ABB lock for the ABB domain 1. #endif } nrf_power_event_t; @@ -146,16 +244,27 @@ typedef enum typedef enum { #if NRF_POWER_HAS_POFWARN - NRF_POWER_INT_POFWARN_MASK = POWER_INTENSET_POFWARN_Msk , /**< Write '1' to Enable interrupt for POFWARN event. */ + NRF_POWER_INT_POFWARN_MASK = POWER_INTENSET_POFWARN_Msk, ///< Write '1' to enable interrupt for POFWARN event. #endif #if NRF_POWER_HAS_SLEEPEVT - NRF_POWER_INT_SLEEPENTER_MASK = POWER_INTENSET_SLEEPENTER_Msk , /**< Write '1' to Enable interrupt for SLEEPENTER event. */ - NRF_POWER_INT_SLEEPEXIT_MASK = POWER_INTENSET_SLEEPEXIT_Msk , /**< Write '1' to Enable interrupt for SLEEPEXIT event. */ + NRF_POWER_INT_SLEEPENTER_MASK = POWER_INTENSET_SLEEPENTER_Msk, ///< Write '1' to enable interrupt for SLEEPENTER event. + NRF_POWER_INT_SLEEPEXIT_MASK = POWER_INTENSET_SLEEPEXIT_Msk, ///< Write '1' to enable interrupt for SLEEPEXIT event. #endif #if NRF_POWER_HAS_USBREG - NRF_POWER_INT_USBDETECTED_MASK = POWER_INTENSET_USBDETECTED_Msk, /**< Write '1' to Enable interrupt for USBDETECTED event. */ - NRF_POWER_INT_USBREMOVED_MASK = POWER_INTENSET_USBREMOVED_Msk , /**< Write '1' to Enable interrupt for USBREMOVED event. */ - NRF_POWER_INT_USBPWRRDY_MASK = POWER_INTENSET_USBPWRRDY_Msk , /**< Write '1' to Enable interrupt for USBPWRRDY event. */ + NRF_POWER_INT_USBDETECTED_MASK = POWER_INTENSET_USBDETECTED_Msk, ///< Write '1' to enable interrupt for USBDETECTED event. + NRF_POWER_INT_USBREMOVED_MASK = POWER_INTENSET_USBREMOVED_Msk, ///< Write '1' to enable interrupt for USBREMOVED event. + NRF_POWER_INT_USBPWRRDY_MASK = POWER_INTENSET_USBPWRRDY_Msk, ///< Write '1' to enable interrupt for USBPWRRDY event. +#endif +#if NRF_POWER_HAS_SEMAPHORE + NRF_POWER_INT_SEMAPHORE_ACQUIRED = POWER_INTEN_SEMAPHOREACQUIRED_Msk, ///< Write '1' to enable interrupt for SEMAPHORE_ACQUIRED event. + NRF_POWER_INT_SEMAPHORE_RELEASED = POWER_INTEN_SEMAPHORERELEASED_Msk, ///< Write '1' to enable interrupt for SEMAPHORE_RELEASED event. +#endif +#if NRF_POWER_HAS_VREG_UPDATE_TASK_EVENT + NRF_POWER_INT_REGULATOR_UPDATED = POWER_INTEN_REGUPDATED_Msk, ///< Write '1' to enable interrupt for REGULATOR_UPDATED event. +#endif +#if NRF_POWER_HAS_ABB + NRF_POWER_INT_ABB_LOCK_0 = POWER_INTEN_ABBLOCK0_Msk, ///< Write '1' to enable interrupt for ABB_LOCK_0 event. + NRF_POWER_INT_ABB_LOCK_1 = POWER_INTEN_ABBLOCK1_Msk, ///< Write '1' to enable interrupt for ABB_LOCK_1 event. #endif } nrf_power_int_mask_t; @@ -189,8 +298,8 @@ typedef enum */ typedef enum { - NRF_POWER_USBREGSTATUS_VBUSDETECT_MASK = POWER_USBREGSTATUS_VBUSDETECT_Msk, /**< USB detected or removed. */ - NRF_POWER_USBREGSTATUS_OUTPUTRDY_MASK = POWER_USBREGSTATUS_OUTPUTRDY_Msk /**< USB 3.3 V supply ready. */ + NRF_POWER_USBREGSTATUS_VBUSDETECT_MASK = POWER_USBREGSTATUS_VBUSDETECT_Msk, ///< USB detected or removed. + NRF_POWER_USBREGSTATUS_OUTPUTRDY_MASK = POWER_USBREGSTATUS_OUTPUTRDY_Msk ///< USB 3.3 V supply ready. } nrf_power_usbregstatus_mask_t; #endif // NRF_POWER_HAS_USBREG @@ -273,19 +382,19 @@ typedef enum /** @brief Power failure comparator thresholds. */ typedef enum { - NRF_POWER_POFTHR_V21 = POWER_POFCON_THRESHOLD_V21, /**< Set threshold to 2.1 V. */ - NRF_POWER_POFTHR_V23 = POWER_POFCON_THRESHOLD_V23, /**< Set threshold to 2.3 V. */ - NRF_POWER_POFTHR_V25 = POWER_POFCON_THRESHOLD_V25, /**< Set threshold to 2.5 V. */ - NRF_POWER_POFTHR_V27 = POWER_POFCON_THRESHOLD_V27, /**< Set threshold to 2.7 V. */ + NRF_POWER_POFTHR_V21 = POWER_POFCON_THRESHOLD_V21, ///< Set threshold to 2.1 V. + NRF_POWER_POFTHR_V23 = POWER_POFCON_THRESHOLD_V23, ///< Set threshold to 2.3 V. + NRF_POWER_POFTHR_V25 = POWER_POFCON_THRESHOLD_V25, ///< Set threshold to 2.5 V. + NRF_POWER_POFTHR_V27 = POWER_POFCON_THRESHOLD_V27, ///< Set threshold to 2.7 V. #if defined(POWER_POFCON_THRESHOLD_V17) || defined(__NRFX_DOXYGEN__) - NRF_POWER_POFTHR_V17 = POWER_POFCON_THRESHOLD_V17, /**< Set threshold to 1.7 V. */ - NRF_POWER_POFTHR_V18 = POWER_POFCON_THRESHOLD_V18, /**< Set threshold to 1.8 V. */ - NRF_POWER_POFTHR_V19 = POWER_POFCON_THRESHOLD_V19, /**< Set threshold to 1.9 V. */ - NRF_POWER_POFTHR_V20 = POWER_POFCON_THRESHOLD_V20, /**< Set threshold to 2.0 V. */ - NRF_POWER_POFTHR_V22 = POWER_POFCON_THRESHOLD_V22, /**< Set threshold to 2.2 V. */ - NRF_POWER_POFTHR_V24 = POWER_POFCON_THRESHOLD_V24, /**< Set threshold to 2.4 V. */ - NRF_POWER_POFTHR_V26 = POWER_POFCON_THRESHOLD_V26, /**< Set threshold to 2.6 V. */ - NRF_POWER_POFTHR_V28 = POWER_POFCON_THRESHOLD_V28, /**< Set threshold to 2.8 V. */ + NRF_POWER_POFTHR_V17 = POWER_POFCON_THRESHOLD_V17, ///< Set threshold to 1.7 V. + NRF_POWER_POFTHR_V18 = POWER_POFCON_THRESHOLD_V18, ///< Set threshold to 1.8 V. + NRF_POWER_POFTHR_V19 = POWER_POFCON_THRESHOLD_V19, ///< Set threshold to 1.9 V. + NRF_POWER_POFTHR_V20 = POWER_POFCON_THRESHOLD_V20, ///< Set threshold to 2.0 V. + NRF_POWER_POFTHR_V22 = POWER_POFCON_THRESHOLD_V22, ///< Set threshold to 2.2 V. + NRF_POWER_POFTHR_V24 = POWER_POFCON_THRESHOLD_V24, ///< Set threshold to 2.4 V. + NRF_POWER_POFTHR_V26 = POWER_POFCON_THRESHOLD_V26, ///< Set threshold to 2.6 V. + NRF_POWER_POFTHR_V28 = POWER_POFCON_THRESHOLD_V28, ///< Set threshold to 2.8 V. #endif // defined(POWER_POFCON_THRESHOLD_V17) || defined(__NRFX_DOXYGEN__) } nrf_power_pof_thr_t; #endif // NRF_POWER_HAS_POFCON @@ -294,22 +403,22 @@ typedef enum /** @brief Power failure comparator thresholds for VDDH. */ typedef enum { - NRF_POWER_POFTHRVDDH_V27 = POWER_POFCON_THRESHOLDVDDH_V27, /**< Set threshold to 2.7 V. */ - NRF_POWER_POFTHRVDDH_V28 = POWER_POFCON_THRESHOLDVDDH_V28, /**< Set threshold to 2.8 V. */ - NRF_POWER_POFTHRVDDH_V29 = POWER_POFCON_THRESHOLDVDDH_V29, /**< Set threshold to 2.9 V. */ - NRF_POWER_POFTHRVDDH_V30 = POWER_POFCON_THRESHOLDVDDH_V30, /**< Set threshold to 3.0 V. */ - NRF_POWER_POFTHRVDDH_V31 = POWER_POFCON_THRESHOLDVDDH_V31, /**< Set threshold to 3.1 V. */ - NRF_POWER_POFTHRVDDH_V32 = POWER_POFCON_THRESHOLDVDDH_V32, /**< Set threshold to 3.2 V. */ - NRF_POWER_POFTHRVDDH_V33 = POWER_POFCON_THRESHOLDVDDH_V33, /**< Set threshold to 3.3 V. */ - NRF_POWER_POFTHRVDDH_V34 = POWER_POFCON_THRESHOLDVDDH_V34, /**< Set threshold to 3.4 V. */ - NRF_POWER_POFTHRVDDH_V35 = POWER_POFCON_THRESHOLDVDDH_V35, /**< Set threshold to 3.5 V. */ - NRF_POWER_POFTHRVDDH_V36 = POWER_POFCON_THRESHOLDVDDH_V36, /**< Set threshold to 3.6 V. */ - NRF_POWER_POFTHRVDDH_V37 = POWER_POFCON_THRESHOLDVDDH_V37, /**< Set threshold to 3.7 V. */ - NRF_POWER_POFTHRVDDH_V38 = POWER_POFCON_THRESHOLDVDDH_V38, /**< Set threshold to 3.8 V. */ - NRF_POWER_POFTHRVDDH_V39 = POWER_POFCON_THRESHOLDVDDH_V39, /**< Set threshold to 3.9 V. */ - NRF_POWER_POFTHRVDDH_V40 = POWER_POFCON_THRESHOLDVDDH_V40, /**< Set threshold to 4.0 V. */ - NRF_POWER_POFTHRVDDH_V41 = POWER_POFCON_THRESHOLDVDDH_V41, /**< Set threshold to 4.1 V. */ - NRF_POWER_POFTHRVDDH_V42 = POWER_POFCON_THRESHOLDVDDH_V42, /**< Set threshold to 4.2 V. */ + NRF_POWER_POFTHRVDDH_V27 = POWER_POFCON_THRESHOLDVDDH_V27, ///< Set threshold to 2.7 V. + NRF_POWER_POFTHRVDDH_V28 = POWER_POFCON_THRESHOLDVDDH_V28, ///< Set threshold to 2.8 V. + NRF_POWER_POFTHRVDDH_V29 = POWER_POFCON_THRESHOLDVDDH_V29, ///< Set threshold to 2.9 V. + NRF_POWER_POFTHRVDDH_V30 = POWER_POFCON_THRESHOLDVDDH_V30, ///< Set threshold to 3.0 V. + NRF_POWER_POFTHRVDDH_V31 = POWER_POFCON_THRESHOLDVDDH_V31, ///< Set threshold to 3.1 V. + NRF_POWER_POFTHRVDDH_V32 = POWER_POFCON_THRESHOLDVDDH_V32, ///< Set threshold to 3.2 V. + NRF_POWER_POFTHRVDDH_V33 = POWER_POFCON_THRESHOLDVDDH_V33, ///< Set threshold to 3.3 V. + NRF_POWER_POFTHRVDDH_V34 = POWER_POFCON_THRESHOLDVDDH_V34, ///< Set threshold to 3.4 V. + NRF_POWER_POFTHRVDDH_V35 = POWER_POFCON_THRESHOLDVDDH_V35, ///< Set threshold to 3.5 V. + NRF_POWER_POFTHRVDDH_V36 = POWER_POFCON_THRESHOLDVDDH_V36, ///< Set threshold to 3.6 V. + NRF_POWER_POFTHRVDDH_V37 = POWER_POFCON_THRESHOLDVDDH_V37, ///< Set threshold to 3.7 V. + NRF_POWER_POFTHRVDDH_V38 = POWER_POFCON_THRESHOLDVDDH_V38, ///< Set threshold to 3.8 V. + NRF_POWER_POFTHRVDDH_V39 = POWER_POFCON_THRESHOLDVDDH_V39, ///< Set threshold to 3.9 V. + NRF_POWER_POFTHRVDDH_V40 = POWER_POFCON_THRESHOLDVDDH_V40, ///< Set threshold to 4.0 V. + NRF_POWER_POFTHRVDDH_V41 = POWER_POFCON_THRESHOLDVDDH_V41, ///< Set threshold to 4.1 V. + NRF_POWER_POFTHRVDDH_V42 = POWER_POFCON_THRESHOLDVDDH_V42, ///< Set threshold to 4.2 V. } nrf_power_pof_thrvddh_t; #endif // NRF_POWER_HAS_POFCON_VDDH @@ -408,6 +517,48 @@ typedef enum } nrf_power_rampower_mask_t; #endif // defined(POWER_RAM_POWER_S0POWER_Msk) || defined(__NRFX_DOXYGEN__) +#if NRF_POWER_HAS_VREG_CONFIG +/** @brief POWER voltage regulators bit masks. */ +typedef enum +{ + NRF_POWER_VREG_1V8_MASK = POWER_REGCONFIG_VREG1V8_Msk, ///< 1.8 V regulator. + NRF_POWER_VREG_1V0_MASK = POWER_REGCONFIG_VREG1V0_Msk, ///< 1.0 V regulator. + NRF_POWER_VREG_0V8_MASK = POWER_REGCONFIG_VREG0V8_Msk, ///< 0.8 V regulator. + NRF_POWER_VREG_VS_MASK = POWER_REGCONFIG_VREGVS_Msk, ///< Voltage scaled regulator. + NRF_POWER_VREG_MAIN1V8_MASK = POWER_REGCONFIG_VREGMAIN1V8_Msk, ///< 1.8 V rail at VREGMAIN regulator. + NRF_POWER_VREG_MAIN1V0_MASK = POWER_REGCONFIG_VREGMAIN1V0_Msk, ///< 1.0 V rail at VREGMAIN regulator. + NRF_POWER_VREG_MAINVS_MASK = POWER_REGCONFIG_VREGMAINVS_Msk, ///< Voltage scaled rail at VREGMAIN regulator. + NRF_POWER_VREG_FORCE_MASK = POWER_REGCONFIG_FORCE_Msk, ///< Force the regulator enable configuration. +} nrf_power_vreg_mask_t; +#endif // NRF_POWER_HAS_VREG_CONFIG + +#if NRF_POWER_HAS_ABB +/** @brief POWER operating points for ABB domain. */ +typedef enum +{ + NRF_POWER_OP_POINT_0V4 = POWER_ABB_OPPOINT_OPPOINT_OpPoint0V4, ///< Operating point 0.4 V. + NRF_POWER_OP_POINT_0V5 = POWER_ABB_OPPOINT_OPPOINT_OpPoint0V5, ///< Operating point 0.5 V. + NRF_POWER_OP_POINT_0V6 = POWER_ABB_OPPOINT_OPPOINT_OpPoint0V6, ///< Operating point 0.6 V. + NRF_POWER_OP_POINT_0V8 = POWER_ABB_OPPOINT_OPPOINT_OpPoint0V8, ///< Operating point 0.8 V. +} nrf_power_op_point_t; + +/** @brief POWER operating points for ABB domain. */ +typedef enum +{ + NRF_POWER_OVERRIDE_VALUE_POWER_DOWN = POWER_ABB_OPPOINT_ABBPWROVERRIDEVAL_PowerDown, ///< ABB analog macro powered down. + NRF_POWER_OVERRIDE_VALUE_POWER_UP = POWER_ABB_OPPOINT_ABBPWROVERRIDEVAL_PowerUp, ///< ABB analog macro powered up. +} nrf_power_override_value_t; + +/** @brief POWER operating point for ABB domain structure. */ +typedef struct +{ + nrf_power_op_point_t op_point; ///< ABB operating point. + nrf_power_override_value_t override_value; ///< Override value of ABB analog macro powerup signal. + /**< Value is applied only if @p override_enable is enabled. */ + bool override_enable; ///< True if the override of ABB analog macro signal is to be applied, false otherwise. +} nrf_power_abb_config_t; +#endif // NRF_POWER_HAS_ABB + /** * @brief Function for activating a specific POWER task. * @@ -476,6 +627,7 @@ NRF_STATIC_INLINE uint32_t nrf_power_event_address_get(NRF_POWER_Type const * p_ * * @param[in] p_reg Pointer to the structure of registers of the peripheral. * @param[in] mask Mask of interrupts to be enabled. + * Use @ref nrf_power_int_mask_t values for bit masking. */ NRF_STATIC_INLINE void nrf_power_int_enable(NRF_POWER_Type * p_reg, uint32_t mask); @@ -484,6 +636,7 @@ NRF_STATIC_INLINE void nrf_power_int_enable(NRF_POWER_Type * p_reg, uint32_t mas * * @param[in] p_reg Pointer to the structure of registers of the peripheral. * @param[in] mask Mask of interrupts to be checked. + * Use @ref nrf_power_int_mask_t values for bit masking. * * @return Mask of enabled interrupts. */ @@ -503,6 +656,7 @@ NRF_STATIC_INLINE uint32_t nrf_power_int_enable_get(NRF_POWER_Type const * p_reg * * @param[in] p_reg Pointer to the structure of registers of the peripheral. * @param[in] mask Mask of interrupts to be disabled. + * Use @ref nrf_power_int_mask_t values for bit masking. */ NRF_STATIC_INLINE void nrf_power_int_disable(NRF_POWER_Type * p_reg, uint32_t mask); @@ -623,7 +777,7 @@ NRF_STATIC_INLINE void nrf_power_system_off(NRF_POWER_Type * p_reg); * * @param[in] p_reg Pointer to the structure of registers of the peripheral. * @param[in] enable True if the power failure comparator is to be enabled, false otherwise. - * @param[in] thr voltage threshold value. + * @param[in] thr Voltage threshold value. */ NRF_STATIC_INLINE void nrf_power_pofcon_set(NRF_POWER_Type * p_reg, bool enable, @@ -663,6 +817,7 @@ NRF_STATIC_INLINE void nrf_power_pofcon_vddh_set(NRF_POWER_Type * p_reg, NRF_STATIC_INLINE nrf_power_pof_thrvddh_t nrf_power_pofcon_vddh_get(NRF_POWER_Type const * p_reg); #endif // NRF_POWER_HAS_POFCON_VDDH +#if NRF_POWER_HAS_GPREGRET /** * @brief Function for setting the general purpose retention register. * @@ -723,13 +878,14 @@ NRF_STATIC_INLINE uint8_t nrf_power_gpregret_ext_get(NRF_POWER_Type const * p_re NRF_STATIC_INLINE void nrf_power_gpregret_ext_set(NRF_POWER_Type * p_reg, uint8_t reg_num, uint8_t val); +#endif // NRF_POWER_HAS_GPREGRET #if NRF_POWER_HAS_DCDCEN /** * @brief Enable or disable DCDC converter * * @note If the device consist of high voltage power input (VDDH), this setting - * will relate to the converter on low voltage side (1.3 V output). + * will relate to the converter on low voltage side (1.3 V output). * * @param[in] p_reg Pointer to the structure of registers of the peripheral. * @param[in] enable True if DCDC converter is to be enabled, false otherwise. @@ -740,7 +896,7 @@ NRF_STATIC_INLINE void nrf_power_dcdcen_set(NRF_POWER_Type * p_reg, bool enable) * @brief Function for getting the state of the DCDC converter. * * @note If the device consist of high voltage power input (VDDH), this setting - * will relate to the converter on low voltage side (1.3 V output). + * will relate to the converter on low voltage side (1.3 V output). * * @param[in] p_reg Pointer to the structure of registers of the peripheral. * @@ -870,6 +1026,197 @@ NRF_STATIC_INLINE bool nrf_power_usbregstatus_vbusdet_get(NRF_POWER_Type const * NRF_STATIC_INLINE bool nrf_power_usbregstatus_outrdy_get(NRF_POWER_Type const * p_reg); #endif // NRF_POWER_HAS_USBREG +#if NRF_POWER_HAS_ABB +/** + * @brief Function for checking whether the specified ABB domain is busy. + * + * @param[in] p_reg Pointer to the structure of registers of the peripheral. + * @param[in] domain_idx Index of ABB domain. + * + * @retval true The ABB is busy with applying the new operating point. + * @retval false The ABB is ready to accept the new operating point. + */ +NRF_STATIC_INLINE bool nrf_power_abb_busy_check(NRF_POWER_Type const * p_reg, uint8_t domain_idx); + +/** + * @brief Function for setting configuration of the operating point for the specified ABB domain. + * + * @param[in] p_reg Pointer to the structure of registers of the peripheral. + * @param[in] domain_idx Index of ABB domain. + * @param[in] p_config Pointer to the structure with configuration to be set. + */ +NRF_STATIC_INLINE void nrf_power_abb_config_set(NRF_POWER_Type * p_reg, + uint8_t domain_idx, + nrf_power_abb_config_t const * p_config); + +/** + * @brief Function for getting configuration of the operating point for the specified ABB domain. + * + * @param[in] p_reg Pointer to the structure of registers of the peripheral. + * @param[in] domain_idx Index of ABB domain. + * @param[in] p_config Pointer to the structure with configuration to be set. + */ +NRF_STATIC_INLINE void nrf_power_abb_config_get(NRF_POWER_Type const * p_reg, + uint8_t domain_idx, + nrf_power_abb_config_t * p_config); + +/** + * @brief Function for setting the force lock for the specified ABB domain. + * + * @param[in] p_reg Pointer to the structure of registers of the peripheral. + * @param[in] domain_idx Index of ABB domain. + * @param[in] enable True if force lock is to be enabled, false otherwise. + */ +NRF_STATIC_INLINE void nrf_power_abb_force_lock_set(NRF_POWER_Type * p_reg, + uint8_t domain_idx, + bool enable); + +/** + * @brief Function for checking if the force lock for the specified ABB domain is enabled. + * + * @param[in] p_reg Pointer to the structure of registers of the peripheral. + * @param[in] domain_idx Index of ABB domain whose status is checked. + * + * @retval true Force lock is enabled. + * @retval false Force lock is disabled. + */ +NRF_STATIC_INLINE bool nrf_power_abb_force_lock_check(NRF_POWER_Type const * p_reg, + uint8_t domain_idx); +#endif // NRF_POWER_HAS_ABB + +#if NRF_POWER_HAS_VREG_CONFIG +/** + * @brief Function for enabling specified voltage regulator. + * + * @param[in] p_reg Pointer to the structure of registers of the peripheral. + * @param[in] mask Mask of voltage regulators to be enabled. + * Use @ref nrf_power_vreg_mask_t values for bit masking. + */ +NRF_STATIC_INLINE void nrf_power_vreg_enable(NRF_POWER_Type * p_reg, uint32_t mask); + +/** + * @brief Function for disabling specified voltage regulator. + * + * @param[in] p_reg Pointer to the structure of registers of the peripheral. + * @param[in] mask Mask of voltage regulators to be disabled. + * Use @ref nrf_power_vreg_mask_t values for bit masking. + */ +NRF_STATIC_INLINE void nrf_power_vreg_disable(NRF_POWER_Type * p_reg, uint32_t mask); + +/** + * @brief Function for checking if the specified voltage regulator is enabled. + * + * @param[in] p_reg Pointer to the structure of registers of the peripheral. + * @param[in] mask Mask of voltage regulator to be checked. + * Use @ref nrf_power_vreg_mask_t values for bit masking. + * + * @return Mask of enabled voltage regulators. + */ +NRF_STATIC_INLINE uint32_t nrf_power_vreg_enable_check(NRF_POWER_Type const * p_reg, uint32_t mask); +#endif // NRF_POWER_HAS_VREG_CONFIG + +#if NRF_POWER_HAS_BLOCK_MODES +/** + * @brief Function for setting the Ultra Low Power (ULP) mode. + * + * @note Going into ULP mode is allowed only if this mode is enabled - otherwise it is blocked. + * If the ULV mode is blocked, the ULP mode is also blocked. + * + * @param[in] p_reg Pointer to the structure of registers of the peripheral. + * @param[in] enable True if ULP mode is to be enabled, false otherwise. + */ +NRF_STATIC_INLINE void nrf_power_ulp_mode_set(NRF_POWER_Type * p_reg, bool enable); + +/** + * @brief Function for checking if the ULP mode is enabled. + * + * @note Going into ULP mode is allowed only if this mode is enabled - otherwise it is blocked. + * If the ULV mode is blocked, the ULP mode is also blocked. + * + * @param[in] p_reg Pointer to the structure of registers of the peripheral. + * + * @retval true ULP mode is enabled. + * @retval false ULP mode is disabled. + */ +NRF_STATIC_INLINE bool nrf_power_ulp_mode_check(NRF_POWER_Type const * p_reg); + +/** + * @brief Function for setting the Ultra Low Voltage (ULV) mode. + * + * @note Going into ULP mode is allowed only if this mode is enabled - otherwise it is blocked. + * If the ULV mode is blocked, the ULP mode is also blocked. + * + * @param[in] p_reg Pointer to the structure of registers of the peripheral. + * @param[in] enable True if ULV mode is to be enabled, false otherwise. + */ +NRF_STATIC_INLINE void nrf_power_ulv_mode_set(NRF_POWER_Type * p_reg, bool enable); + +/** + * @brief Function for checking if the ULV mode is enabled. + * + * @note Going into ULP mode is allowed only if this mode is enabled - otherwise it is blocked. + * If the ULV mode is blocked, the ULP mode is also blocked. + * + * @param[in] p_reg Pointer to the structure of registers of the peripheral. + * + * @retval true ULV mode is enabled. + * @retval false ULV mode is disabled. + */ +NRF_STATIC_INLINE bool nrf_power_ulv_mode_check(NRF_POWER_Type const * p_reg); +#endif // NRF_POWER_HAS_BLOCK_MODES + +#if NRF_POWER_HAS_SEMAPHORE +/** + * @brief Function for getting the POWER semaphore status. + * + * @param[in] p_reg Pointer to the structure of registers of the peripheral. + * + * @retval true Semaphore is acquired. + * @retval false Semaphore is released. + */ +NRF_STATIC_INLINE bool nrf_power_sem_status_get(NRF_POWER_Type const * p_reg); +#endif // NRF_POWER_HAS_SEMAPHORE + +#if NRF_POWER_HAS_BILS +/** + * @brief Function for setting BILS instances. + * + * @param[in] p_reg Pointer to the structure of registers of the peripheral. + * @param[in] enable True if all configured BILS instances are to be enabled, false otherwise. + */ +NRF_STATIC_INLINE void nrf_power_bils_set(NRF_POWER_Type * p_reg, bool enable); + +/** + * @brief Function for checking if BILS instances are enabled. + * + * @param[in] p_reg Pointer to the structure of registers of the peripheral. + * + * @retval true All configured BILS instances are enabled. + * @retval false All BILS instances are disabled. + */ +NRF_STATIC_INLINE bool nrf_power_bils_check(NRF_POWER_Type const * p_reg); +#endif // NRF_POWER_HAS_BILS + +#if NRF_POWER_HAS_PMIC +/** + * @brief Function for setting the PMIC interface. + * + * @param[in] p_reg Pointer to the structure of registers of the peripheral. + * @param[in] enable True if PMIC interface is to be enabled, false otherwise. + */ +NRF_STATIC_INLINE void nrf_power_pmic_set(NRF_POWER_Type * p_reg, bool enable); + +/** + * @brief Function for checking if the PMIC interface is enabled. + * + * @param[in] p_reg Pointer to the structure of registers of the peripheral. + * + * @retval true PMIC interface is enabled. + * @retval false PMIC interface is disabled. + */ +NRF_STATIC_INLINE bool nrf_power_pmic_check(NRF_POWER_Type const * p_reg); +#endif // NRF_POWER_HAS_PMIC + #ifndef NRF_DECLARE_ONLY NRF_STATIC_INLINE void nrf_power_task_trigger(NRF_POWER_Type * p_reg, nrf_power_task_t task) @@ -1055,6 +1402,7 @@ NRF_STATIC_INLINE nrf_power_pof_thrvddh_t nrf_power_pofcon_vddh_get(NRF_POWER_Ty } #endif // NRF_POWER_HAS_POFCON_VDDH +#if NRF_POWER_HAS_GPREGRET NRF_STATIC_INLINE void nrf_power_gpregret_set(NRF_POWER_Type * p_reg, uint8_t val) { volatile uint32_t * p_gpregret; @@ -1116,6 +1464,7 @@ NRF_STATIC_INLINE uint8_t nrf_power_gpregret2_get(NRF_POWER_Type const * p_reg) return (uint8_t)p_reg->GPREGRET2; } #endif +#endif // NRF_POWER_HAS_GPREGRET #if NRF_POWER_HAS_DCDCEN NRF_STATIC_INLINE void nrf_power_dcdcen_set(NRF_POWER_Type * p_reg, bool enable) @@ -1200,6 +1549,149 @@ NRF_STATIC_INLINE bool nrf_power_usbregstatus_outrdy_get(NRF_POWER_Type const * } #endif // NRF_POWER_HAS_USBREG +#if NRF_POWER_HAS_ABB +NRF_STATIC_INLINE bool nrf_power_abb_busy_check(NRF_POWER_Type const * p_reg, uint8_t domain_idx) +{ + return ((p_reg->ABB[domain_idx].STATUS & POWER_ABB_STATUS_STATUS_Msk) == + (POWER_ABB_STATUS_STATUS_Busy << POWER_ABB_STATUS_STATUS_Pos)); +} + +NRF_STATIC_INLINE void nrf_power_abb_config_set(NRF_POWER_Type * p_reg, + uint8_t domain_idx, + nrf_power_abb_config_t const * p_config) +{ + p_reg->ABB[domain_idx].OPPOINT = ((p_config->op_point << + POWER_ABB_OPPOINT_OPPOINT_Pos) & + POWER_ABB_OPPOINT_OPPOINT_Msk) | + ((p_config->override_value << + POWER_ABB_OPPOINT_ABBPWROVERRIDEVAL_Pos) & + POWER_ABB_OPPOINT_ABBPWROVERRIDEVAL_Msk) | + ((p_config->override_enable ? + POWER_ABB_OPPOINT_ABBPWROVERRIDEEN_Enabled : + POWER_ABB_OPPOINT_ABBPWROVERRIDEEN_Disabled) << + POWER_ABB_OPPOINT_ABBPWROVERRIDEEN_Pos); +} + +NRF_STATIC_INLINE void nrf_power_abb_config_get(NRF_POWER_Type const * p_reg, + uint8_t domain_idx, + nrf_power_abb_config_t * p_config) +{ + p_config->op_point = (nrf_power_op_point_t)((p_reg->ABB[domain_idx].OPPOINT & + POWER_ABB_OPPOINT_OPPOINT_Msk) >> + POWER_ABB_OPPOINT_OPPOINT_Pos); + + p_config->override_value = (nrf_power_override_value_t) + ((p_reg->ABB[domain_idx].OPPOINT & + POWER_ABB_OPPOINT_ABBPWROVERRIDEVAL_Msk) >> + POWER_ABB_OPPOINT_ABBPWROVERRIDEVAL_Pos); + + p_config->override_enable = ((p_reg->ABB[domain_idx].OPPOINT & + POWER_ABB_OPPOINT_ABBPWROVERRIDEEN_Msk) == + (POWER_ABB_OPPOINT_ABBPWROVERRIDEEN_Enabled << + POWER_ABB_OPPOINT_ABBPWROVERRIDEEN_Pos)); +} + +NRF_STATIC_INLINE void nrf_power_abb_force_lock_set(NRF_POWER_Type * p_reg, + uint8_t domain_idx, + bool enable) +{ + p_reg->ABB[domain_idx].FORCELOCK = ((enable ? + POWER_ABB_FORCELOCK_ENABLE_Enabled : + POWER_ABB_FORCELOCK_ENABLE_Disabled) << + POWER_ABB_FORCELOCK_ENABLE_Pos); +} + +NRF_STATIC_INLINE bool nrf_power_abb_force_lock_check(NRF_POWER_Type const * p_reg, + uint8_t domain_idx) +{ + return (p_reg->ABB[domain_idx].FORCELOCK & POWER_ABB_FORCELOCK_ENABLE_Msk) == + (POWER_ABB_FORCELOCK_ENABLE_Enabled << POWER_ABB_FORCELOCK_ENABLE_Pos); +} +#endif // NRF_POWER_HAS_ABB + +#if NRF_POWER_HAS_VREG_CONFIG +NRF_STATIC_INLINE void nrf_power_vreg_enable(NRF_POWER_Type * p_reg, uint32_t mask) +{ + p_reg->REGCONFIG = mask; +} + +NRF_STATIC_INLINE void nrf_power_vreg_disable(NRF_POWER_Type * p_reg, uint32_t mask) +{ + p_reg->REGCONFIG = ~mask; +} + +NRF_STATIC_INLINE uint32_t nrf_power_vreg_enable_check(NRF_POWER_Type const * p_reg, uint32_t mask) +{ + return p_reg->REGCONFIG & mask; +} +#endif // NRF_POWER_HAS_VREG_CONFIG + +#if NRF_POWER_HAS_BLOCK_MODES +NRF_STATIC_INLINE void nrf_power_ulp_mode_set(NRF_POWER_Type * p_reg, bool enable) +{ + p_reg->BLOCKULPMODE = (enable ? POWER_BLOCKULPMODE_BLOCK_Allowed : + POWER_BLOCKULPMODE_BLOCK_Blocked) << + POWER_BLOCKULPMODE_BLOCK_Pos; +} + +NRF_STATIC_INLINE bool nrf_power_ulp_mode_check(NRF_POWER_Type const * p_reg) +{ + return (p_reg->BLOCKULPMODE & POWER_BLOCKULPMODE_BLOCK_Msk) == + (POWER_BLOCKULPMODE_BLOCK_Allowed << POWER_BLOCKULPMODE_BLOCK_Pos); +} + +NRF_STATIC_INLINE void nrf_power_ulv_mode_set(NRF_POWER_Type * p_reg, bool enable) +{ + p_reg->BLOCKULVMODE = (enable ? POWER_BLOCKULVMODE_BLOCK_Allowed : + POWER_BLOCKULVMODE_BLOCK_Blocked) << + POWER_BLOCKULVMODE_BLOCK_Pos; +} + +NRF_STATIC_INLINE bool nrf_power_ulv_mode_check(NRF_POWER_Type const * p_reg) +{ + return (p_reg->BLOCKULVMODE & POWER_BLOCKULVMODE_BLOCK_Msk) == + (POWER_BLOCKULVMODE_BLOCK_Allowed << POWER_BLOCKULVMODE_BLOCK_Pos); +} +#endif // NRF_POWER_HAS_BLOCK_MODES + +#if NRF_POWER_HAS_SEMAPHORE +NRF_STATIC_INLINE bool nrf_power_sem_status_get(NRF_POWER_Type const * p_reg) +{ + return (p_reg->SEMAPHORESTATUS & POWER_SEMAPHORESTATUS_STATUS_Msk) == + (POWER_SEMAPHORESTATUS_STATUS_Acquired << POWER_SEMAPHORESTATUS_STATUS_Pos); +} +#endif // NRF_POWER_HAS_SEMAPHORE + +#if NRF_POWER_HAS_BILS +NRF_STATIC_INLINE void nrf_power_bils_set(NRF_POWER_Type * p_reg, bool enable) +{ + p_reg->BILSENABLE = (enable ? POWER_BILSENABLE_ENABLE_Enabled : + POWER_BILSENABLE_ENABLE_Disabled) << + POWER_BILSENABLE_ENABLE_Pos; +} + +NRF_STATIC_INLINE bool nrf_power_bils_check(NRF_POWER_Type const * p_reg) +{ + return (p_reg->BILSENABLE & POWER_BILSENABLE_ENABLE_Msk) == + (POWER_BILSENABLE_ENABLE_Enabled << POWER_BILSENABLE_ENABLE_Pos); +} +#endif // NRF_POWER_HAS_BILS + +#if NRF_POWER_HAS_PMIC +NRF_STATIC_INLINE void nrf_power_pmic_set(NRF_POWER_Type * p_reg, bool enable) +{ + p_reg->PMICENABLE = (enable ? POWER_PMICENABLE_ENABLE_Enabled : + POWER_PMICENABLE_ENABLE_Disabled) << + POWER_PMICENABLE_ENABLE_Pos; +} + +NRF_STATIC_INLINE bool nrf_power_pmic_check(NRF_POWER_Type const * p_reg) +{ + return (p_reg->PMICENABLE & POWER_PMICENABLE_ENABLE_Msk) == + (POWER_PMICENABLE_ENABLE_Enabled << POWER_PMICENABLE_ENABLE_Pos); +} +#endif // NRF_POWER_HAS_PMIC + #endif // NRF_DECLARE_ONLY /** @} */ diff --git a/hal/nrf_pwm.h b/hal/nrf_pwm.h index 658d86fdb..64d107780 100644 --- a/hal/nrf_pwm.h +++ b/hal/nrf_pwm.h @@ -69,6 +69,13 @@ extern "C" { #define NRF_PWM_HAS_DMA_TASKS_EVENTS 0 #endif +#if defined(PWM_SEQ_CNT_CNT_Msk) || defined(__NRFX_DOXYGEN__) +/** @brief Symbol indicating whether setting the number of duty cycle values for a sequence is available. */ +#define NRF_PWM_HAS_SEQ_CNT 1 +#else +#define NRF_PWM_HAS_SEQ_CNT 0 +#endif + /** * @brief Macro getting pointer to the structure of registers of the PWM peripheral. * @@ -92,7 +99,7 @@ extern "C" { * @brief Helper macro for calculating the number of 16-bit values in the specified * array of duty cycle values. */ -#define NRF_PWM_VALUES_LENGTH(array) (sizeof(array) / sizeof(uint16_t)) +#define NRF_PWM_VALUES_LENGTH(array) (sizeof(array) / 2UL) /** @brief PWM tasks. */ @@ -513,6 +520,7 @@ NRF_STATIC_INLINE void nrf_pwm_seq_ptr_set(NRF_PWM_Type * p_reg, uint8_t seq_id, uint16_t const * p_values); +#if NRF_PWM_HAS_SEQ_CNT /** * @brief Function for modifying the total number of duty cycle values * in the specified sequence. @@ -524,6 +532,7 @@ NRF_STATIC_INLINE void nrf_pwm_seq_ptr_set(NRF_PWM_Type * p_reg, NRF_STATIC_INLINE void nrf_pwm_seq_cnt_set(NRF_PWM_Type * p_reg, uint8_t seq_id, uint16_t length); +#endif /** * @brief Function for modifying the additional number of PWM periods spent @@ -735,7 +744,9 @@ NRF_STATIC_INLINE void nrf_pwm_sequence_set(NRF_PWM_Type * p_reg, NRFX_ASSERT(p_seq != NULL); nrf_pwm_seq_ptr_set( p_reg, seq_id, p_seq->values.p_raw); +#if NRF_PWM_HAS_SEQ_CNT nrf_pwm_seq_cnt_set( p_reg, seq_id, p_seq->length); +#endif nrf_pwm_seq_refresh_set( p_reg, seq_id, p_seq->repeats); nrf_pwm_seq_end_delay_set(p_reg, seq_id, p_seq->end_delay); } @@ -753,6 +764,7 @@ NRF_STATIC_INLINE void nrf_pwm_seq_ptr_set(NRF_PWM_Type * p_reg, #endif } +#if NRF_PWM_HAS_SEQ_CNT NRF_STATIC_INLINE void nrf_pwm_seq_cnt_set(NRF_PWM_Type * p_reg, uint8_t seq_id, uint16_t length) @@ -762,6 +774,7 @@ NRF_STATIC_INLINE void nrf_pwm_seq_cnt_set(NRF_PWM_Type * p_reg, NRFX_ASSERT(length <= PWM_SEQ_CNT_CNT_Msk); p_reg->SEQ[seq_id].CNT = length; } +#endif NRF_STATIC_INLINE void nrf_pwm_seq_refresh_set(NRF_PWM_Type * p_reg, uint8_t seq_id, diff --git a/hal/nrf_radio.h b/hal/nrf_radio.h index d6bd831c0..f711c5862 100644 --- a/hal/nrf_radio.h +++ b/hal/nrf_radio.h @@ -49,8 +49,7 @@ extern "C" { #if defined(DPPI_PRESENT) || defined(__NRFX_DOXYGEN__) /** @brief Symbol specifying offset between address of TASK/EVENT register and address of associated SUBSCRIBE/PUBLISH register. */ -#define NRF_RADIO_DPPI_OFFSET \ - (NRFX_OFFSETOF(NRF_RADIO_Type, SUBSCRIBE_TXEN) - NRFX_OFFSETOF(NRF_RADIO_Type, TASKS_TXEN)) +#define NRF_RADIO_DPPI_OFFSET NRF_SUBSCRIBE_PUBLISH_OFFSET_RADIO #endif // defined(DPPI_PRESENT) || defined(__NRFX_DOXYGEN__) /** @brief RADIO tasks. */ @@ -436,7 +435,9 @@ typedef enum NRF_RADIO_TXPOWER_NEG12DBM = RADIO_TXPOWER_TXPOWER_Neg12dBm, /**< -12 dBm. */ NRF_RADIO_TXPOWER_NEG16DBM = RADIO_TXPOWER_TXPOWER_Neg16dBm, /**< -16 dBm. */ NRF_RADIO_TXPOWER_NEG20DBM = RADIO_TXPOWER_TXPOWER_Neg20dBm, /**< -20 dBm. */ +#if defined(RADIO_TXPOWER_TXPOWER_Neg30dBm) || defined(__NRFX_DOXYGEN__) NRF_RADIO_TXPOWER_NEG30DBM = RADIO_TXPOWER_TXPOWER_Neg30dBm, /**< -30 dBm. */ +#endif #if defined(RADIO_TXPOWER_TXPOWER_Neg40dBm) || defined(__NRFX_DOXYGEN__) NRF_RADIO_TXPOWER_NEG40DBM = RADIO_TXPOWER_TXPOWER_Neg40dBm, /**< -40 dBm. */ #endif diff --git a/hal/nrf_saadc.h b/hal/nrf_saadc.h index 6b928cd23..0e5bdb73d 100644 --- a/hal/nrf_saadc.h +++ b/hal/nrf_saadc.h @@ -90,12 +90,18 @@ extern "C" { #define NRF_SAADC_HAS_DMA_REG 0 #endif -#if (defined(SAADC_TASKS_DMA_START_START_Msk) && defined(SAADC_EVENTS_DMA_END_END_Msk)) || \ - defined(__NRFX_DOXYGEN__) -/** @brief Symbol indicating whether SAADC DMA tasks and events are present. */ -#define NRF_SAADC_HAS_DMA_TASKS_EVENTS 1 +#if defined(SAADC_EVENTS_DMA_END_END_Msk) || defined(__NRFX_DOXYGEN__) +/** @brief Symbol indicating whether SAADC DMA events are present. */ +#define NRF_SAADC_HAS_DMA_EVENTS 1 #else -#define NRF_SAADC_HAS_DMA_TASKS_EVENTS 0 +#define NRF_SAADC_HAS_DMA_EVENTS 0 +#endif + +#if defined(SAADC_CH_CONFIG_RESP_Msk) || defined(__NRFX_DOXYGEN__) +/** @brief Symbol indicating whether SAADC channel resistor control is present. */ +#define NRF_SAADC_HAS_CH_CONFIG_RES 1 +#else +#define NRF_SAADC_HAS_CH_CONFIG_RES 0 #endif #if !NRF_SAADC_HAS_ACQTIME_ENUM @@ -185,6 +191,7 @@ typedef enum NRF_SAADC_OVERSAMPLE_256X = SAADC_OVERSAMPLE_OVERSAMPLE_Over256x ///< Oversample 256x. } nrf_saadc_oversample_t; +#if NRF_SAADC_HAS_CH_CONFIG_RES /** @brief Analog-to-digital converter channel resistor control. */ typedef enum { @@ -198,6 +205,7 @@ typedef enum NRF_SAADC_RESISTOR_VDD1_2 = SAADC_CH_CONFIG_RESP_VDDAO1V8div2, ///< Set input at VDD/2. #endif } nrf_saadc_resistor_t; +#endif /** @brief Gain factor of the analog-to-digital converter input. */ typedef enum @@ -271,13 +279,8 @@ typedef enum /** @brief Analog-to-digital converter tasks. */ typedef enum { -#if NRF_SAADC_HAS_DMA_TASKS_EVENTS - NRF_SAADC_TASK_START = offsetof(NRF_SAADC_Type, TASKS_DMA.START), ///< Start the ADC and prepare the result buffer in RAM. - NRF_SAADC_TASK_STOP = offsetof(NRF_SAADC_Type, TASKS_DMA.STOP), ///< Stop the ADC and terminate any ongoing conversion. -#else NRF_SAADC_TASK_START = offsetof(NRF_SAADC_Type, TASKS_START), ///< Start the ADC and prepare the result buffer in RAM. NRF_SAADC_TASK_STOP = offsetof(NRF_SAADC_Type, TASKS_STOP), ///< Stop the ADC and terminate any ongoing conversion. -#endif NRF_SAADC_TASK_SAMPLE = offsetof(NRF_SAADC_Type, TASKS_SAMPLE), ///< Take one ADC sample. If scan is enabled, all channels are sampled. NRF_SAADC_TASK_CALIBRATEOFFSET = offsetof(NRF_SAADC_Type, TASKS_CALIBRATEOFFSET), ///< Starts offset auto-calibration. } nrf_saadc_task_t; @@ -286,7 +289,7 @@ typedef enum typedef enum { NRF_SAADC_EVENT_STARTED = offsetof(NRF_SAADC_Type, EVENTS_STARTED), ///< The ADC has started. -#if NRF_SAADC_HAS_DMA_TASKS_EVENTS +#if NRF_SAADC_HAS_DMA_EVENTS NRF_SAADC_EVENT_END = offsetof(NRF_SAADC_Type, EVENTS_DMA.END), ///< The ADC has filled up the result buffer. #else NRF_SAADC_EVENT_END = offsetof(NRF_SAADC_Type, EVENTS_END), ///< The ADC has filled up the result buffer. @@ -317,7 +320,7 @@ typedef enum typedef enum { NRF_SAADC_INT_STARTED = SAADC_INTENSET_STARTED_Msk, ///< Interrupt on EVENTS_STARTED event. -#if NRF_SAADC_HAS_DMA_TASKS_EVENTS +#if NRF_SAADC_HAS_DMA_EVENTS NRF_SAADC_INT_END = SAADC_INTENSET_DMAEND_Msk, ///< Interrupt on EVENTS_END event. #else NRF_SAADC_INT_END = SAADC_INTENSET_END_Msk, ///< Interrupt on EVENTS_END event. @@ -367,8 +370,10 @@ typedef struct /** @brief Analog-to-digital converter channel configuration structure. */ typedef struct { +#if NRF_SAADC_HAS_CH_CONFIG_RES nrf_saadc_resistor_t resistor_p; ///< Resistor value on positive input. nrf_saadc_resistor_t resistor_n; ///< Resistor value on negative input. +#endif nrf_saadc_gain_t gain; ///< Gain control value. nrf_saadc_reference_t reference; ///< Reference control value. nrf_saadc_acqtime_t acq_time; ///< Acquisition time. @@ -1073,11 +1078,13 @@ NRF_STATIC_INLINE void nrf_saadc_channel_init(NRF_SAADC_Type * NRFX_ASSERT(config->conv_time <= NRF_SAADC_CONVTIME_MAX); #endif p_reg->CH[channel].CONFIG = - ((config->resistor_p << SAADC_CH_CONFIG_RESP_Pos) & SAADC_CH_CONFIG_RESP_Msk) - | ((config->resistor_n << SAADC_CH_CONFIG_RESN_Pos) & SAADC_CH_CONFIG_RESN_Msk) - | ((config->gain << SAADC_CH_CONFIG_GAIN_Pos) & SAADC_CH_CONFIG_GAIN_Msk) + ((config->gain << SAADC_CH_CONFIG_GAIN_Pos) & SAADC_CH_CONFIG_GAIN_Msk) | ((config->reference << SAADC_CH_CONFIG_REFSEL_Pos) & SAADC_CH_CONFIG_REFSEL_Msk) | ((config->acq_time << SAADC_CH_CONFIG_TACQ_Pos) & SAADC_CH_CONFIG_TACQ_Msk) +#if NRF_SAADC_HAS_CH_CONTROL_RES + | ((config->resistor_p << SAADC_CH_CONFIG_RESP_Pos) & SAADC_CH_CONFIG_RESP_Msk) + | ((config->resistor_n << SAADC_CH_CONFIG_RESN_Pos) & SAADC_CH_CONFIG_RESN_Msk) +#endif #if NRF_SAADC_HAS_CONVTIME | ((config->conv_time << SAADC_CH_CONFIG_TCONV_Pos) & SAADC_CH_CONFIG_TCONV_Msk) #endif diff --git a/hal/nrf_spim.h b/hal/nrf_spim.h index a1b5bbb7f..1d4e49fc0 100644 --- a/hal/nrf_spim.h +++ b/hal/nrf_spim.h @@ -259,8 +259,7 @@ extern "C" { ((uint32_t)frequency == (uint32_t)NRFX_MHZ_TO_HZ(4)) || \ ((uint32_t)frequency == (uint32_t)NRFX_MHZ_TO_HZ(8)) || \ (((uint32_t)frequency == (uint32_t)NRFX_MHZ_TO_HZ(16)) && (NRF_SPIM_HAS_16_MHZ_FREQ)) || \ - (((uint32_t)frequency == (uint32_t)NRFX_MHZ_TO_HZ(32)) && (NRF_SPIM_HAS_32_MHZ_FREQ)) )), \ - "The specified frequency cannot be achieved with the given SPIM instance.") + (((uint32_t)frequency == (uint32_t)NRFX_MHZ_TO_HZ(32)) && (NRF_SPIM_HAS_32_MHZ_FREQ))))) /** @brief SPIM tasks. */ typedef enum @@ -312,7 +311,7 @@ typedef enum NRF_SPIM_SHORT_RXMATCH0_ENABLERXMATCH1_MASK = SPIM_SHORTS_DMA_RX_MATCH0_DMA_RX_ENABLEMATCH1_Msk, ///< Shortcut between DMA.RX.MATCH0 event and DMA.RX.ENABLEMATCH1 task. NRF_SPIM_SHORT_RXMATCH1_ENABLERXMATCH2_MASK = SPIM_SHORTS_DMA_RX_MATCH1_DMA_RX_ENABLEMATCH2_Msk, ///< Shortcut between DMA.RX.MATCH1 event and DMA.RX.ENABLEMATCH2 task. NRF_SPIM_SHORT_RXMATCH2_ENABLERXMATCH3_MASK = SPIM_SHORTS_DMA_RX_MATCH2_DMA_RX_ENABLEMATCH3_Msk, ///< Shortcut between DMA.RX.MATCH2 event and DMA.RX.ENABLEMATCH3 task. - NRF_SPIM_SHORT_RXMATCH3_ENABLERXMATCH4_MASK = SPIM_SHORTS_DMA_RX_MATCH3_DMA_RX_ENABLEMATCH4_Msk, ///< Shortcut between DMA.RX.MATCH3 event and DMA.RX.ENABLEMATCH4 task. + NRF_SPIM_SHORT_RXMATCH3_ENABLERXMATCH0_MASK = SPIM_SHORTS_DMA_RX_MATCH3_DMA_RX_ENABLEMATCH0_Msk, ///< Shortcut between DMA.RX.MATCH3 event and DMA.RX.ENABLEMATCH4 task. NRF_SPIM_SHORT_RXMATCH0_DISABLERXMATCH0_MASK = SPIM_SHORTS_DMA_RX_MATCH0_DMA_RX_DISABLEMATCH0_Msk, ///< Shortcut between DMA.RX.MATCH0 event and DMA.RX.DISABLEMATCH0 task. NRF_SPIM_SHORT_RXMATCH1_DISABLERXMATCH1_MASK = SPIM_SHORTS_DMA_RX_MATCH1_DMA_RX_DISABLEMATCH1_Msk, ///< Shortcut between DMA.RX.MATCH1 event and DMA.RX.DISABLEMATCH1 task. NRF_SPIM_SHORT_RXMATCH2_DISABLERXMATCH2_MASK = SPIM_SHORTS_DMA_RX_MATCH2_DMA_RX_DISABLEMATCH2_Msk, ///< Shortcut between DMA.RX.MATCH2 event and DMA.RX.DISABLEMATCH2 task. @@ -323,7 +322,7 @@ typedef enum | SPIM_SHORTS_DMA_RX_MATCH0_DMA_RX_ENABLEMATCH1_Msk | SPIM_SHORTS_DMA_RX_MATCH1_DMA_RX_ENABLEMATCH2_Msk | SPIM_SHORTS_DMA_RX_MATCH2_DMA_RX_ENABLEMATCH3_Msk - | SPIM_SHORTS_DMA_RX_MATCH3_DMA_RX_ENABLEMATCH4_Msk + | SPIM_SHORTS_DMA_RX_MATCH3_DMA_RX_ENABLEMATCH0_Msk | SPIM_SHORTS_DMA_RX_MATCH0_DMA_RX_DISABLEMATCH0_Msk | SPIM_SHORTS_DMA_RX_MATCH1_DMA_RX_DISABLEMATCH1_Msk | SPIM_SHORTS_DMA_RX_MATCH2_DMA_RX_DISABLEMATCH2_Msk diff --git a/hal/nrf_spu.h b/hal/nrf_spu.h index 6d56a7711..983c91c99 100644 --- a/hal/nrf_spu.h +++ b/hal/nrf_spu.h @@ -61,6 +61,14 @@ extern "C" { #define NRF_SPU_HAS_MEMORY 0 #endif +#if defined(SPU_FEATURE_BELLS_DOMAIN_MaxCount) || defined(SPU_FEATURE_BELLS_PROCESSOR_MaxCount) \ + || defined(__NRFX_DOXYGEN__) +/** @brief Symbol indicating whether SPU has registers related to BELLS. */ +#define NRF_SPU_HAS_BELLS 1 +#else +#define NRF_SPU_HAS_BELLS 0 +#endif + #if defined(SPU_FEATURE_BELLS_DOMAIN_MaxCount) || defined(__NRFX_DOXYGEN__) /** @brief Symbol indicating whether SPU uses DOMAIN register name. */ #define NRF_SPU_HAS_DOMAIN 1 @@ -68,16 +76,25 @@ extern "C" { #define NRF_SPU_HAS_DOMAIN 0 #endif +#if defined(SPU_FEATURE_IPCT_CH_MaxCount) || defined(__NRFX_DOXYGEN__) +/** @brief Symbol indicating whether SPU has registers related to IPCT. */ +#define NRF_SPU_HAS_IPCT 1 +#else +#define NRF_SPU_HAS_IPCT 0 +#endif + #if NRF_SPU_HAS_OWNERSHIP /** @brief Number of peripherals. */ #define NRF_SPU_PERIPH_COUNT SPU_PERIPH_MaxCount +#if NRF_SPU_HAS_IPCT /** @brief Number of IPCT channels. */ #define NRF_SPU_FEATURE_IPCT_CHANNEL_COUNT SPU_FEATURE_IPCT_CH_MaxCount /** @brief Number of IPCT interrupts. */ #define NRF_SPU_FEATURE_IPCT_INTERRUPT_COUNT SPU_FEATURE_IPCT_INTERRUPT_MaxCount +#endif /** @brief Number of DPPI channels. */ #define NRF_SPU_FEATURE_DPPI_CHANNEL_COUNT SPU_FEATURE_DPPIC_CH_MaxCount @@ -189,8 +206,10 @@ typedef enum /** @brief SPU features. */ typedef enum { +#if NRF_SPU_HAS_IPCT NRF_SPU_FEATURE_IPCT_CHANNEL, /**< IPCT channel. */ NRF_SPU_FEATURE_IPCT_INTERRUPT, /**< IPCT interrupt. */ +#endif NRF_SPU_FEATURE_DPPI_CHANNEL, /**< DPPI channel. */ NRF_SPU_FEATURE_DPPI_CHANNEL_GROUP, /**< DPPI channel group. */ NRF_SPU_FEATURE_GPIOTE_CHANNEL, /**< GPIOTE channel. */ @@ -199,6 +218,7 @@ typedef enum NRF_SPU_FEATURE_GRTC_CC, /**< GRTC compare channel. */ NRF_SPU_FEATURE_GRTC_SYSCOUNTER, /**< GRTC SYSCOUNTER. */ NRF_SPU_FEATURE_GRTC_INTERRUPT, /**< GRTC interrupt. */ +#if NRF_SPU_HAS_BELLS #if NRF_SPU_HAS_DOMAIN NRF_SPU_FEATURE_BELLS_BELL, /**< BELLS bell pair. */ #else @@ -206,6 +226,7 @@ typedef enum NRF_SPU_FEATURE_BELLS_EVENTS, /**< BELLS events pair. */ NRF_SPU_FEATURE_BELLS_INTERRUPT, /**< BELLS interrupt pair. */ #endif +#endif } nrf_spu_feature_t; #endif @@ -1059,6 +1080,7 @@ NRF_STATIC_INLINE bool nrf_spu_feature_secattr_get(NRF_SPU_Type const * p_reg, { switch (feature) { +#if NRF_SPU_HAS_IPCT case NRF_SPU_FEATURE_IPCT_CHANNEL: NRFX_ASSERT(index < NRF_SPU_FEATURE_IPCT_CHANNEL_COUNT); return (p_reg->FEATURE.IPCT.CH[index] @@ -1070,6 +1092,7 @@ NRF_STATIC_INLINE bool nrf_spu_feature_secattr_get(NRF_SPU_Type const * p_reg, return (p_reg->FEATURE.IPCT.INTERRUPT[index] & SPU_FEATURE_IPCT_INTERRUPT_SECATTR_Msk) >> SPU_FEATURE_IPCT_INTERRUPT_SECATTR_Pos; +#endif // NRF_SPU_HAS_IPCT case NRF_SPU_FEATURE_DPPI_CHANNEL: NRFX_ASSERT(index < NRF_SPU_FEATURE_DPPI_CHANNEL_COUNT); @@ -1121,6 +1144,7 @@ NRF_STATIC_INLINE bool nrf_spu_feature_secattr_get(NRF_SPU_Type const * p_reg, & SPU_FEATURE_GRTC_INTERRUPT_SECATTR_Msk) >> SPU_FEATURE_GRTC_INTERRUPT_SECATTR_Pos; +#if NRF_SPU_HAS_BELLS #if NRF_SPU_HAS_DOMAIN case NRF_SPU_FEATURE_BELLS_BELL: NRFX_ASSERT(index < NRF_SPU_FEATURE_BELL_BELL_COUNT); @@ -1145,7 +1169,8 @@ NRF_STATIC_INLINE bool nrf_spu_feature_secattr_get(NRF_SPU_Type const * p_reg, return (p_reg->FEATURE.BELLS.PROCESSOR[index].INTERRUPT[subindex] & SPU_FEATURE_BELLS_PROCESSOR_INTERRUPT_SECATTR_Msk) >> SPU_FEATURE_BELLS_PROCESSOR_INTERRUPT_SECATTR_Pos; -#endif +#endif // NRF_SPU_HAS_DOMAIN +#endif // NRF_SPU_HAS_BELLS default: NRFX_ASSERT(0); @@ -1160,6 +1185,7 @@ NRF_STATIC_INLINE bool nrf_spu_feature_lock_get(NRF_SPU_Type const * p_reg, { switch (feature) { +#if NRF_SPU_HAS_IPCT case NRF_SPU_FEATURE_IPCT_CHANNEL: NRFX_ASSERT(index < NRF_SPU_FEATURE_IPCT_CHANNEL_COUNT); return (p_reg->FEATURE.IPCT.CH[index] @@ -1171,6 +1197,7 @@ NRF_STATIC_INLINE bool nrf_spu_feature_lock_get(NRF_SPU_Type const * p_reg, return (p_reg->FEATURE.IPCT.INTERRUPT[index] & SPU_FEATURE_IPCT_INTERRUPT_LOCK_Msk) >> SPU_FEATURE_IPCT_INTERRUPT_LOCK_Pos; +#endif // NRF_SPU_HAS_IPCT case NRF_SPU_FEATURE_DPPI_CHANNEL: NRFX_ASSERT(index < NRF_SPU_FEATURE_DPPI_CHANNEL_COUNT); @@ -1222,6 +1249,7 @@ NRF_STATIC_INLINE bool nrf_spu_feature_lock_get(NRF_SPU_Type const * p_reg, & SPU_FEATURE_GRTC_INTERRUPT_LOCK_Msk) >> SPU_FEATURE_GRTC_INTERRUPT_LOCK_Pos; +#if NRF_SPU_HAS_BELLS #if NRF_SPU_HAS_DOMAIN case NRF_SPU_FEATURE_BELLS_BELL: NRFX_ASSERT(index < NRF_SPU_FEATURE_BELL_BELL_COUNT); @@ -1246,7 +1274,8 @@ NRF_STATIC_INLINE bool nrf_spu_feature_lock_get(NRF_SPU_Type const * p_reg, return (p_reg->FEATURE.BELLS.PROCESSOR[index].INTERRUPT[subindex] & SPU_FEATURE_BELLS_PROCESSOR_INTERRUPT_LOCK_Msk) >> SPU_FEATURE_BELLS_PROCESSOR_INTERRUPT_LOCK_Pos; -#endif +#endif // NRF_SPU_HAS_DOMAIN +#endif // NRF_SPU_HAS_BELLS default: NRFX_ASSERT(0); return false; @@ -1260,6 +1289,7 @@ NRF_STATIC_INLINE bool nrf_spu_feature_block_get(NRF_SPU_Type const * p_reg, { switch (feature) { +#if NRF_SPU_HAS_IPCT case NRF_SPU_FEATURE_IPCT_CHANNEL: NRFX_ASSERT(index < NRF_SPU_FEATURE_IPCT_CHANNEL_COUNT); return (p_reg->FEATURE.IPCT.CH[index] @@ -1271,6 +1301,7 @@ NRF_STATIC_INLINE bool nrf_spu_feature_block_get(NRF_SPU_Type const * p_reg, return (p_reg->FEATURE.IPCT.INTERRUPT[index] & SPU_FEATURE_IPCT_INTERRUPT_BLOCK_Msk) >> SPU_FEATURE_IPCT_INTERRUPT_BLOCK_Pos; +#endif // NRF_SPU_HAS_IPCT case NRF_SPU_FEATURE_DPPI_CHANNEL: NRFX_ASSERT(index < NRF_SPU_FEATURE_DPPI_CHANNEL_COUNT); @@ -1322,6 +1353,7 @@ NRF_STATIC_INLINE bool nrf_spu_feature_block_get(NRF_SPU_Type const * p_reg, & SPU_FEATURE_GRTC_INTERRUPT_BLOCK_Msk) >> SPU_FEATURE_GRTC_INTERRUPT_BLOCK_Pos; +#if NRF_SPU_HAS_BELLS #if NRF_SPU_HAS_DOMAIN case NRF_SPU_FEATURE_BELLS_BELL: NRFX_ASSERT(index < NRF_SPU_FEATURE_BELL_BELL_COUNT); @@ -1346,7 +1378,8 @@ NRF_STATIC_INLINE bool nrf_spu_feature_block_get(NRF_SPU_Type const * p_reg, return (p_reg->FEATURE.BELLS.PROCESSOR[index].INTERRUPT[subindex] & SPU_FEATURE_BELLS_PROCESSOR_INTERRUPT_BLOCK_Msk) >> SPU_FEATURE_BELLS_PROCESSOR_INTERRUPT_BLOCK_Pos; -#endif +#endif // NRF_SPU_HAS_DOMAIN +#endif // NRF_SPU_HAS_BELLS default: NRFX_ASSERT(0); return false; @@ -1360,6 +1393,7 @@ NRF_STATIC_INLINE nrf_owner_t nrf_spu_feature_ownerid_get(NRF_SPU_Type const * p { switch (feature) { +#if NRF_SPU_HAS_IPCT case NRF_SPU_FEATURE_IPCT_CHANNEL: NRFX_ASSERT(index < NRF_SPU_FEATURE_IPCT_CHANNEL_COUNT); return (nrf_owner_t)((p_reg->FEATURE.IPCT.CH[index] @@ -1371,6 +1405,7 @@ NRF_STATIC_INLINE nrf_owner_t nrf_spu_feature_ownerid_get(NRF_SPU_Type const * p return (nrf_owner_t)((p_reg->FEATURE.IPCT.INTERRUPT[index] & SPU_FEATURE_IPCT_INTERRUPT_OWNERID_Msk) >> SPU_FEATURE_IPCT_INTERRUPT_OWNERID_Pos); +#endif // NRF_SPU_HAS_IPCT case NRF_SPU_FEATURE_DPPI_CHANNEL: NRFX_ASSERT(index < NRF_SPU_FEATURE_DPPI_CHANNEL_COUNT); @@ -1422,6 +1457,7 @@ NRF_STATIC_INLINE nrf_owner_t nrf_spu_feature_ownerid_get(NRF_SPU_Type const * p & SPU_FEATURE_GRTC_INTERRUPT_OWNERID_Msk) >> SPU_FEATURE_GRTC_INTERRUPT_OWNERID_Pos); +#if NRF_SPU_HAS_BELLS #if NRF_SPU_HAS_DOMAIN case NRF_SPU_FEATURE_BELLS_BELL: NRFX_ASSERT(index < NRF_SPU_FEATURE_BELL_BELL_COUNT); @@ -1446,7 +1482,8 @@ NRF_STATIC_INLINE nrf_owner_t nrf_spu_feature_ownerid_get(NRF_SPU_Type const * p return (nrf_owner_t)((p_reg->FEATURE.BELLS.PROCESSOR[index].INTERRUPT[subindex] & SPU_FEATURE_BELLS_PROCESSOR_INTERRUPT_OWNERID_Msk) >> SPU_FEATURE_BELLS_PROCESSOR_INTERRUPT_OWNERID_Pos); -#endif +#endif // NRF_SPU_HAS_DOMAIN +#endif // NRF_SPU_HAS_BELLS default: NRFX_ASSERT(0); return (nrf_owner_t)0; @@ -1461,6 +1498,7 @@ NRF_STATIC_INLINE void nrf_spu_feature_secattr_set(NRF_SPU_Type * p_reg, { switch (feature) { +#if NRF_SPU_HAS_IPCT case NRF_SPU_FEATURE_IPCT_CHANNEL: NRFX_ASSERT(index < NRF_SPU_FEATURE_IPCT_CHANNEL_COUNT); p_reg->FEATURE.IPCT.CH[index] = @@ -1482,6 +1520,7 @@ NRF_STATIC_INLINE void nrf_spu_feature_secattr_set(NRF_SPU_Type * p_reg, SPU_FEATURE_IPCT_INTERRUPT_SECATTR_NonSecure) << SPU_FEATURE_IPCT_INTERRUPT_SECATTR_Pos)); break; +#endif // NRF_SPU_HAS_IPCT case NRF_SPU_FEATURE_DPPI_CHANNEL: NRFX_ASSERT(index < NRF_SPU_FEATURE_DPPI_CHANNEL_COUNT); @@ -1573,6 +1612,7 @@ NRF_STATIC_INLINE void nrf_spu_feature_secattr_set(NRF_SPU_Type * p_reg, << SPU_FEATURE_GRTC_INTERRUPT_SECATTR_Pos)); break; +#if NRF_SPU_HAS_BELLS #if NRF_SPU_HAS_DOMAIN case NRF_SPU_FEATURE_BELLS_BELL: NRFX_ASSERT(index < NRF_SPU_FEATURE_BELL_BELL_COUNT); @@ -1617,7 +1657,8 @@ NRF_STATIC_INLINE void nrf_spu_feature_secattr_set(NRF_SPU_Type * p_reg, SPU_FEATURE_BELLS_PROCESSOR_INTERRUPT_SECATTR_NonSecure) << SPU_FEATURE_BELLS_PROCESSOR_INTERRUPT_SECATTR_Pos)); break; -#endif +#endif // NRF_SPU_HAS_DOMAIN +#endif // NRF_SPU_HAS_BELLS default: NRFX_ASSERT(0); @@ -1632,6 +1673,7 @@ NRF_STATIC_INLINE void nrf_spu_feature_lock_enable(NRF_SPU_Type * p_reg, { switch (feature) { +#if NRF_SPU_HAS_IPCT case NRF_SPU_FEATURE_IPCT_CHANNEL: NRFX_ASSERT(index < NRF_SPU_FEATURE_IPCT_CHANNEL_COUNT); p_reg->FEATURE.IPCT.CH[index] = @@ -1649,6 +1691,7 @@ NRF_STATIC_INLINE void nrf_spu_feature_lock_enable(NRF_SPU_Type * p_reg, (SPU_FEATURE_IPCT_INTERRUPT_LOCK_Locked << SPU_FEATURE_IPCT_INTERRUPT_LOCK_Pos)); break; +#endif // NRF_SPU_HAS_IPCT case NRF_SPU_FEATURE_DPPI_CHANNEL: NRFX_ASSERT(index < NRF_SPU_FEATURE_DPPI_CHANNEL_COUNT); @@ -1724,6 +1767,7 @@ NRF_STATIC_INLINE void nrf_spu_feature_lock_enable(NRF_SPU_Type * p_reg, << SPU_FEATURE_GRTC_INTERRUPT_LOCK_Pos)); break; +#if NRF_SPU_HAS_BELLS #if NRF_SPU_HAS_DOMAIN case NRF_SPU_FEATURE_BELLS_BELL: NRFX_ASSERT(index < NRF_SPU_FEATURE_BELL_BELL_COUNT); @@ -1760,7 +1804,8 @@ NRF_STATIC_INLINE void nrf_spu_feature_lock_enable(NRF_SPU_Type * p_reg, (SPU_FEATURE_BELLS_PROCESSOR_INTERRUPT_LOCK_Locked << SPU_FEATURE_BELLS_PROCESSOR_INTERRUPT_LOCK_Pos)); break; -#endif +#endif // NRF_SPU_HAS_DOMAIN +#endif // NRF_SPU_HAS_BELLS default: NRFX_ASSERT(0); @@ -1775,6 +1820,7 @@ NRF_STATIC_INLINE void nrf_spu_feature_block_enable(NRF_SPU_Type * p_reg, { switch (feature) { +#if NRF_SPU_HAS_IPCT case NRF_SPU_FEATURE_IPCT_CHANNEL: NRFX_ASSERT(index < NRF_SPU_FEATURE_IPCT_CHANNEL_COUNT); p_reg->FEATURE.IPCT.CH[index] = @@ -1792,6 +1838,7 @@ NRF_STATIC_INLINE void nrf_spu_feature_block_enable(NRF_SPU_Type * p_reg, (SPU_FEATURE_IPCT_INTERRUPT_BLOCK_Blocked << SPU_FEATURE_IPCT_INTERRUPT_BLOCK_Pos)); break; +#endif // NRF_SPU_HAS_IPCT case NRF_SPU_FEATURE_DPPI_CHANNEL: NRFX_ASSERT(index < NRF_SPU_FEATURE_DPPI_CHANNEL_COUNT); @@ -1867,6 +1914,7 @@ NRF_STATIC_INLINE void nrf_spu_feature_block_enable(NRF_SPU_Type * p_reg, << SPU_FEATURE_GRTC_INTERRUPT_BLOCK_Pos)); break; +#if NRF_SPU_HAS_BELLS #if NRF_SPU_HAS_DOMAIN case NRF_SPU_FEATURE_BELLS_BELL: NRFX_ASSERT(index < NRF_SPU_FEATURE_BELL_BELL_COUNT); @@ -1903,7 +1951,8 @@ NRF_STATIC_INLINE void nrf_spu_feature_block_enable(NRF_SPU_Type * p_reg, (SPU_FEATURE_BELLS_PROCESSOR_INTERRUPT_BLOCK_Blocked << SPU_FEATURE_BELLS_PROCESSOR_INTERRUPT_BLOCK_Pos)); break; -#endif +#endif // NRF_SPU_HAS_DOMAIN +#endif // NRF_SPU_HAS_BELLS default: NRFX_ASSERT(0); @@ -1919,6 +1968,7 @@ NRF_STATIC_INLINE void nrf_spu_feature_ownerid_set(NRF_SPU_Type * p_reg, { switch (feature) { +#if NRF_SPU_HAS_IPCT case NRF_SPU_FEATURE_IPCT_CHANNEL: NRFX_ASSERT(index < NRF_SPU_FEATURE_IPCT_CHANNEL_COUNT); p_reg->FEATURE.IPCT.CH[index] = @@ -1938,6 +1988,7 @@ NRF_STATIC_INLINE void nrf_spu_feature_ownerid_set(NRF_SPU_Type * p_reg, << SPU_FEATURE_IPCT_INTERRUPT_OWNERID_Pos) & SPU_FEATURE_IPCT_INTERRUPT_OWNERID_Msk)); break; +#endif // NRF_SPU_HAS_IPCT case NRF_SPU_FEATURE_DPPI_CHANNEL: NRFX_ASSERT(index < NRF_SPU_FEATURE_DPPI_CHANNEL_COUNT); @@ -2021,6 +2072,7 @@ NRF_STATIC_INLINE void nrf_spu_feature_ownerid_set(NRF_SPU_Type * p_reg, SPU_FEATURE_GRTC_INTERRUPT_OWNERID_Msk)); break; +#if NRF_SPU_HAS_BELLS #if NRF_SPU_HAS_DOMAIN case NRF_SPU_FEATURE_BELLS_BELL: NRFX_ASSERT(index < NRF_SPU_FEATURE_BELL_BELL_COUNT); @@ -2061,7 +2113,8 @@ NRF_STATIC_INLINE void nrf_spu_feature_ownerid_set(NRF_SPU_Type * p_reg, << SPU_FEATURE_BELLS_PROCESSOR_INTERRUPT_OWNERID_Pos) & SPU_FEATURE_BELLS_PROCESSOR_INTERRUPT_OWNERID_Msk)); break; -#endif +#endif // NRF_SPU_HAS_DOMAIN +#endif // NRF_SPU_HAS_BELLS default: NRFX_ASSERT(0); diff --git a/hal/nrf_temp.h b/hal/nrf_temp.h index 9c238f400..2ead00958 100644 --- a/hal/nrf_temp.h +++ b/hal/nrf_temp.h @@ -47,6 +47,13 @@ extern "C" { * @brief Hardware access layer for managing the Temperature sensor (TEMP). */ +#if defined(TEMP_CALIB_CALIB_Msk) || defined(__NRFX_DOXYGEN__) +/** @brief Symbol indicating whether the calibration of temperature measurement is present. */ +#define NRF_TEMP_HAS_CALIBRATION 1 +#else +#define NRF_TEMP_HAS_CALIBRATION 0 +#endif + /** @brief TEMP tasks. */ typedef enum { @@ -152,6 +159,25 @@ NRF_STATIC_INLINE bool nrf_temp_event_check(NRF_TEMP_Type const * p_reg, nrf_tem */ NRF_STATIC_INLINE int32_t nrf_temp_result_get(NRF_TEMP_Type const * p_reg); +#if NRF_TEMP_HAS_CALIBRATION +/** + * @brief Function for setting the calibration coefficient for the temperature measurement. + * + * @param[in] p_reg Pointer to the structure of registers of the peripheral. + * @param[in] coeff Calibration coefficient. + */ +NRF_STATIC_INLINE void nrf_temp_calibration_coeff_set(NRF_TEMP_Type * p_reg, uint32_t coeff); + +/** + * @brief Function for getting the calibration coefficient for the temperature measurement. + * + * @param[in] p_reg Pointer to the structure of registers of the peripheral. + * + * @return Calibration coefficient. + */ +NRF_STATIC_INLINE uint32_t nrf_temp_calibration_coeff_get(NRF_TEMP_Type const * p_reg); +#endif + #ifndef NRF_DECLARE_ONLY NRF_STATIC_INLINE void nrf_temp_int_enable(NRF_TEMP_Type * p_reg, uint32_t mask) @@ -212,6 +238,18 @@ NRF_STATIC_INLINE int32_t nrf_temp_result_get(NRF_TEMP_Type const * p_reg) return raw_measurement; } +#if NRF_TEMP_HAS_CALIBRATION +NRF_STATIC_INLINE void nrf_temp_calibration_coeff_set(NRF_TEMP_Type * p_reg, uint32_t coeff) +{ + p_reg->CALIB = coeff; +} + +NRF_STATIC_INLINE uint32_t nrf_temp_calibration_coeff_get(NRF_TEMP_Type const * p_reg) +{ + return p_reg->CALIB; +} +#endif + #endif // NRF_DECLARE_ONLY /** @} */ diff --git a/hal/nrf_timer.h b/hal/nrf_timer.h index 10b77832f..2a74108f1 100644 --- a/hal/nrf_timer.h +++ b/hal/nrf_timer.h @@ -231,8 +231,7 @@ extern "C" { (NRF_TIMER_BASE_FREQUENCY_GET(p_reg) == frequency) || \ ((NRF_TIMER_BASE_FREQUENCY_GET(p_reg) % frequency == 0) && \ NRFX_IS_POWER_OF_TWO(NRF_TIMER_BASE_FREQUENCY_GET(p_reg) / (uint32_t)frequency) && \ - ((NRF_TIMER_BASE_FREQUENCY_GET(p_reg) / frequency) <= (1 << NRF_TIMER_PRESCALER_MAX))), \ - "Specified frequency can not be achived with given TIMER instance.") + ((NRF_TIMER_BASE_FREQUENCY_GET(p_reg) / frequency) <= (1 << NRF_TIMER_PRESCALER_MAX)))) /** * @brief Macro for getting the number of capture/compare channels available diff --git a/hal/nrf_twim.h b/hal/nrf_twim.h index 3063cdd0d..fbfbc66e2 100644 --- a/hal/nrf_twim.h +++ b/hal/nrf_twim.h @@ -147,8 +147,8 @@ typedef enum #if NRF_TWIM_HAS_DMA_TASKS_EVENTS NRF_TWIM_SHORT_RXMATCH0_ENABLERXMATCH1_MASK = TWIM_SHORTS_DMA_RX_MATCH0_DMA_RX_ENABLEMATCH1_Msk, ///< Shortcut between DMA.RX.MATCH0 event and DMA.RX.ENABLEMATCH1 task. NRF_TWIM_SHORT_RXMATCH1_ENABLERXMATCH2_MASK = TWIM_SHORTS_DMA_RX_MATCH1_DMA_RX_ENABLEMATCH2_Msk, ///< Shortcut between DMA.RX.MATCH1 event and DMA.RX.ENABLEMATCH2 task. - NRF_TWIM_SHORT_RXMATCH2_ENABLERXMATCH0_MASK = TWIM_SHORTS_DMA_RX_MATCH2_DMA_RX_ENABLEMATCH0_Msk, ///< Shortcut between DMA.RX.MATCH2 event and DMA.RX.ENABLEMATCH0 task. - NRF_TWIM_SHORT_RXMATCH3_ENABLERXMATCH1_MASK = TWIM_SHORTS_DMA_RX_MATCH3_DMA_RX_ENABLEMATCH1_Msk, ///< Shortcut between DMA.RX.MATCH3 event and DMA.RX.ENABLEMATCH1 task. + NRF_TWIM_SHORT_RXMATCH2_ENABLERXMATCH3_MASK = TWIM_SHORTS_DMA_RX_MATCH2_DMA_RX_ENABLEMATCH3_Msk, ///< Shortcut between DMA.RX.MATCH2 event and DMA.RX.ENABLEMATCH0 task. + NRF_TWIM_SHORT_RXMATCH3_ENABLERXMATCH0_MASK = TWIM_SHORTS_DMA_RX_MATCH3_DMA_RX_ENABLEMATCH0_Msk, ///< Shortcut between DMA.RX.MATCH3 event and DMA.RX.ENABLEMATCH1 task. NRF_TWIM_SHORT_RXMATCH0_DISABLERXMATCH0_MASK = TWIM_SHORTS_DMA_RX_MATCH0_DMA_RX_DISABLEMATCH0_Msk, ///< Shortcut between DMA.RX.MATCH0 event and DMA.RX.DISABLEMATCH0 task. NRF_TWIM_SHORT_RXMATCH1_DISABLERXMATCH1_MASK = TWIM_SHORTS_DMA_RX_MATCH1_DMA_RX_DISABLEMATCH1_Msk, ///< Shortcut between DMA.RX.MATCH1 event and DMA.RX.DISABLEMATCH1 task. NRF_TWIM_SHORT_RXMATCH2_DISABLERXMATCH2_MASK = TWIM_SHORTS_DMA_RX_MATCH2_DMA_RX_DISABLEMATCH2_Msk, ///< Shortcut between DMA.RX.MATCH2 event and DMA.RX.DISABLEMATCH2 task. @@ -162,8 +162,8 @@ typedef enum #if NRF_TWIM_HAS_DMA_TASKS_EVENTS TWIM_SHORTS_DMA_RX_MATCH0_DMA_RX_ENABLEMATCH1_Msk | TWIM_SHORTS_DMA_RX_MATCH1_DMA_RX_ENABLEMATCH2_Msk | - TWIM_SHORTS_DMA_RX_MATCH2_DMA_RX_ENABLEMATCH0_Msk | - TWIM_SHORTS_DMA_RX_MATCH3_DMA_RX_ENABLEMATCH1_Msk | + TWIM_SHORTS_DMA_RX_MATCH2_DMA_RX_ENABLEMATCH3_Msk | + TWIM_SHORTS_DMA_RX_MATCH3_DMA_RX_ENABLEMATCH0_Msk | TWIM_SHORTS_DMA_RX_MATCH0_DMA_RX_DISABLEMATCH0_Msk | TWIM_SHORTS_DMA_RX_MATCH1_DMA_RX_DISABLEMATCH1_Msk | TWIM_SHORTS_DMA_RX_MATCH2_DMA_RX_DISABLEMATCH2_Msk | diff --git a/haly/nrfy_dppi.h b/haly/nrfy_dppi.h index 09f14eb2f..0f8abb270 100644 --- a/haly/nrfy_dppi.h +++ b/haly/nrfy_dppi.h @@ -154,7 +154,7 @@ NRFY_STATIC_INLINE void nrfy_dppi_channels_include_in_group(NRF_DPPIC_Type * } /** @refhal{nrf_dppi_channels_remove_from_group} */ -NRFY_STATIC_INLINE +NRFY_STATIC_INLINE void nrfy_dppi_channels_remove_from_group(NRF_DPPIC_Type * p_reg, uint32_t channel_mask, nrf_dppi_channel_group_t channel_group) diff --git a/haly/nrfy_nfct.h b/haly/nrfy_nfct.h new file mode 100644 index 000000000..c96cecc29 --- /dev/null +++ b/haly/nrfy_nfct.h @@ -0,0 +1,836 @@ +/* + * Copyright (c) 2023, Nordic Semiconductor ASA + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef NRFY_NFCT_H__ +#define NRFY_NFCT_H__ + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +NRFY_STATIC_INLINE void __nrfy_internal_nfct_event_enabled_clear(NRF_NFCT_Type * p_reg, + uint32_t mask, + nrf_nfct_event_t event); + +NRFY_STATIC_INLINE bool __nrfy_internal_nfct_event_handle(NRF_NFCT_Type * p_reg, + uint32_t mask, + nrf_nfct_event_t event, + uint32_t * p_evt_mask); + +NRFY_STATIC_INLINE uint32_t __nrfy_internal_nfct_events_process(NRF_NFCT_Type * p_reg, + uint32_t mask); + +/** + * @defgroup nrfy_nfct NFCT HALY + * @{ + * @ingroup nrf_nfct + * @brief Hardware access layer with cache and barrier support for managing the NFCT peripheral. + */ + +#if NRF_NFCT_HAS_MODULATION_PSEL_REG || defined(__NRFX_DOXYGEN__) +/** @refhal{NRF_NFCT_HAS_MODULATION_PSEL_REG} */ +#define NRFY_NFCT_HAS_MODULATION_PSEL_REG 1 +#else +#define NRFY_NFCT_HAS_MODULATION_PSEL_REG 0 +#endif + +#if NRF_NFCT_HAS_MODULATION_CTRL_REG || defined(__NRFX_DOXYGEN__) +/** @refhal{NRF_NFCT_HAS_MODULATION_CTRL_REG} */ +#define NRFY_NFCT_HAS_MODULATION_CTRL_REG 1 +#else +#define NRFY_NFCT_HAS_MODULATION_CTRL_REG 0 +#endif + +#if NRF_NFCT_HAS_TAG_STATE_REG || defined(__NRFX_DOXYGEN__) +/** @refhal{NRF_NFCT_HAS_TAG_STATE_REG} */ +#define NRFY_NFCT_HAS_TAG_STATE_REG 1 +#else +#define NRFY_NFCT_HAS_TAG_STATE_REG 0 +#endif + +#if NRF_NFCT_HAS_SLEEP_STATE_REG || defined(__NRFX_DOXYGEN__) +/** @refhal{NRF_NFCT_HAS_SLEEP_STATE_REG} */ +#define NRFY_NFCT_HAS_SLEEP_STATE_REG 1 +#else +#define NRFY_NFCT_HAS_SLEEP_STATE_REG 0 +#endif + +#if NRF_NFCT_HAS_AUTOCOLRES_CONFIG_REG || defined(__NRFX_DOXYGEN__) +/** @refhal{NRF_NFCT_HAS_AUTOCOLRES_CONFIG_REG} */ +#define NRFY_NFCT_HAS_AUTOCOLRES_CONFIG_REG 1 +#else +#define NRFY_NFCT_HAS_AUTOCOLRES_CONFIG_REG 0 +#endif + +#if NRF_NFCT_HAS_PAD_CONFIG_REG || defined(__NRFX_DOXYGEN__) +/** @refhal{NRF_NFCT_HAS_PAD_CONFIG_REG} */ +#define NRFY_NFCT_HAS_PAD_CONFIG_REG 1 +#else +#define NRFY_NFCT_HAS_PAD_CONFIG_REG 0 +#endif + +#if NRF_NFCT_HAS_BIAS_CONFIG_TRIM_REG || defined(__NRFX_DOXYGEN__) +/** @refhal{NRF_NFCT_HAS_BIAS_CONFIG_TRIM_REG} */ +#define NRFY_NFCT_HAS_BIAS_CONFIG_TRIM_REG 1 +#else +#define NRFY_NFCT_HAS_BIAS_CONFIG_TRIM_REG 0 +#endif + +/** @brief NFCT parameters storage structure. */ +typedef struct +{ + uint32_t fdmax; ///< Frame delay max value. + uint32_t fdmin; ///< Frame delay min value. + uint32_t int_enabled; ///< Interrupts status. + uint8_t nfcid1[NRF_NFCT_SENSRES_NFCID1_SIZE_TRIPLE]; ///< NFCID1 value. + nrf_nfct_sensres_nfcid1_size_t nfcid1_size; ///< NFCID1 size. + nrf_nfct_selres_protocol_t protocol; ///< NFC protocol type. +} nrfy_nfct_parameters_t; + +/** + * @brief Function for initializing the specified NFCT interrupts. + * + * @param[in] p_reg Pointer to the structure of registers of the peripheral. + * @param[in] mask Mask of interrupts to be initialized. + * @param[in] irq_priority Interrupts priority. + * @param[in] enable True if interrupts associated with the event mask are to be enabled, + * false otherwise. + */ +NRFY_STATIC_INLINE void nrfy_nfct_int_init(NRF_NFCT_Type * p_reg, + uint32_t mask, + uint8_t irq_priority, + bool enable) +{ + IRQn_Type nfct_irq = nrfx_get_irq_number(p_reg); + + __nrfy_internal_nfct_event_enabled_clear(p_reg, mask, NRF_NFCT_EVENT_READY); + __nrfy_internal_nfct_event_enabled_clear(p_reg, mask, NRF_NFCT_EVENT_FIELDDETECTED); + __nrfy_internal_nfct_event_enabled_clear(p_reg, mask, NRF_NFCT_EVENT_FIELDLOST); + __nrfy_internal_nfct_event_enabled_clear(p_reg, mask, NRF_NFCT_EVENT_TXFRAMESTART); + __nrfy_internal_nfct_event_enabled_clear(p_reg, mask, NRF_NFCT_EVENT_TXFRAMEEND); + __nrfy_internal_nfct_event_enabled_clear(p_reg, mask, NRF_NFCT_EVENT_RXFRAMESTART); + __nrfy_internal_nfct_event_enabled_clear(p_reg, mask, NRF_NFCT_EVENT_RXFRAMEEND); + __nrfy_internal_nfct_event_enabled_clear(p_reg, mask, NRF_NFCT_EVENT_ERROR); + __nrfy_internal_nfct_event_enabled_clear(p_reg, mask, NRF_NFCT_EVENT_RXERROR); + __nrfy_internal_nfct_event_enabled_clear(p_reg, mask, NRF_NFCT_EVENT_ENDRX); + __nrfy_internal_nfct_event_enabled_clear(p_reg, mask, NRF_NFCT_EVENT_ENDTX); + __nrfy_internal_nfct_event_enabled_clear(p_reg, mask, NRF_NFCT_EVENT_AUTOCOLRESSTARTED); + __nrfy_internal_nfct_event_enabled_clear(p_reg, mask, NRF_NFCT_EVENT_COLLISION); + __nrfy_internal_nfct_event_enabled_clear(p_reg, mask, NRF_NFCT_EVENT_SELECTED); + __nrfy_internal_nfct_event_enabled_clear(p_reg, mask, NRF_NFCT_EVENT_STARTED); + nrf_barrier_w(); + + NRFY_IRQ_PENDING_CLEAR(nfct_irq); + nrf_barrier_w(); + + NRFY_IRQ_PRIORITY_SET(nfct_irq, irq_priority); + NRFY_IRQ_ENABLE(nfct_irq); + + if (enable) + { + nrf_nfct_int_enable(p_reg, mask); + } + + nrf_barrier_w(); +} + +/** + * @brief Function for un-initializing the NFCT interrupts. + * + * @param[in] p_reg Pointer to the structure of registers of the peripheral. + */ +NRFY_STATIC_INLINE void nrfy_nfct_int_uninit(NRF_NFCT_Type * p_reg) +{ + IRQn_Type nfct_irq = nrfx_get_irq_number(p_reg); + + NRFY_IRQ_DISABLE(nfct_irq); + nrf_barrier_w(); + NRFY_IRQ_PENDING_CLEAR(nfct_irq); + nrf_barrier_w(); +} + +/** + * @brief Function for processing the specified NFCT events. + * + * @param[in] p_reg Pointer to the structure of registers of the peripheral. + * @param[in] mask Mask of the events to be processed, created by the + * @ref NRFY_EVENT_TO_INT_BITMASK(). + * + * @return Mask of the events that were generated and processed. + * To be checked against the result of the @ref NRFY_EVENT_TO_INT_BITMASK(). +*/ +NRFY_STATIC_INLINE uint32_t nrfy_nfct_events_process(NRF_NFCT_Type * p_reg, uint32_t mask) +{ + uint32_t evt_mask = __nrfy_internal_nfct_events_process(p_reg, mask); + nrf_barrier_w(); + return evt_mask; +} + +/** + * @brief Function for saving NFCT parameters before peripheral reset. + * + * @param[in] p_reg Pointer to the structure of registers of the peripheral. + * @param[in] p_params Pointer to the structure where the parameters will be saved. +*/ +NRFY_STATIC_INLINE void nrfy_nfct_parameters_save(NRF_NFCT_Type const * p_reg, + nrfy_nfct_parameters_t * p_params) +{ + nrf_barrier_rw(); + p_params->fdmax = nrf_nfct_frame_delay_max_get(p_reg); + p_params->fdmin = nrf_nfct_frame_delay_min_get(p_reg); + p_params->nfcid1_size = nrf_nfct_nfcid1_get(p_reg, p_params->nfcid1); + p_params->protocol = nrf_nfct_selres_protocol_get(p_reg); + p_params->int_enabled = nrf_nfct_int_enable_get(p_reg); + nrf_barrier_r(); +} + +/** + * @brief Function for restoring NFCT parameters after peripheral reset. The parameters are + * written back to the peripheral registers. + * + * @param[in] p_reg Pointer to the structure of registers of the peripheral. + * @param[in] p_params Pointer to the structure holding peripheral parameters to be restored. + */ +NRFY_STATIC_INLINE void nrfy_nfct_parameters_restore(NRF_NFCT_Type * p_reg, + nrfy_nfct_parameters_t const * p_params) +{ + nrf_nfct_frame_delay_max_set(p_reg, p_params->fdmax); + nrf_nfct_frame_delay_min_set(p_reg, p_params->fdmin); + nrf_nfct_nfcid1_set(p_reg, p_params->nfcid1, p_params->nfcid1_size); + nrf_nfct_selres_protocol_set(p_reg, p_params->protocol); + + nrf_barrier_w(); +} + +/** + * @brief Function for setting the the NFCT RX/TX buffer (address and maximum length). + * + * @note Buffer for the NFC RX/TX data is used by EasyDMA and must be located in RAM. + * + * @param[in] p_reg Pointer to the structure of registers of the peripheral. + * @param[in] p_rxtx_buf Pointer to the receive or transmit buffer. + * @param[in] max_txrx_len Maximum receive or transmit length in bytes + * (size of the RAM buffer for EasyDMA). + * @param[in] rx True if buffer is set for the frame reception, false if buffer is set for + * the frame transmission. + */ +NRFY_STATIC_INLINE void nrfy_nfct_rxtx_buffer_set(NRF_NFCT_Type * p_reg, + uint8_t * p_rxtx_buf, + uint16_t max_txrx_len, + bool rx) +{ + if (p_rxtx_buf && !rx) + { + NRFY_CACHE_WB(p_rxtx_buf, max_txrx_len); + } + + nrf_nfct_rxtx_buffer_set(p_reg, p_rxtx_buf, max_txrx_len); + nrf_barrier_w(); +} + +/** @refhal{nrf_nfct_task_trigger} */ +NRFY_STATIC_INLINE void nrfy_nfct_task_trigger(NRF_NFCT_Type * p_reg, nrf_nfct_task_t task) +{ + nrf_nfct_task_trigger(p_reg, task); + nrf_barrier_w(); +} + +/** @refhal{nrf_nfct_task_address_get} */ +NRFY_STATIC_INLINE uint32_t nrfy_nfct_task_address_get(NRF_NFCT_Type const * p_reg, + nrf_nfct_task_t task) +{ + return nrf_nfct_task_address_get(p_reg, task); +} + +/** @refhal{nrf_nfct_event_clear} */ +NRFY_STATIC_INLINE void nrfy_nfct_event_clear(NRF_NFCT_Type * p_reg, nrf_nfct_event_t event) +{ + nrf_nfct_event_clear(p_reg, event); + nrf_barrier_w(); +} + +/** @refhal{nrf_nfct_event_check} */ +NRFY_STATIC_INLINE bool nrfy_nfct_event_check(NRF_NFCT_Type const * p_reg, nrf_nfct_event_t event) +{ + nrf_barrier_rw(); + bool check = nrf_nfct_event_check(p_reg, event); + nrf_barrier_r(); + return check; +} + +/** @refhal{nrf_nfct_shorts_enable} */ +NRFY_STATIC_INLINE void nrfy_nfct_shorts_enable(NRF_NFCT_Type * p_reg, uint32_t short_mask) +{ + nrf_nfct_shorts_enable(p_reg, short_mask); + nrf_barrier_w(); +} + +/** @refhal{nrf_nfct_shorts_disable} */ +NRFY_STATIC_INLINE void nrfy_nfct_shorts_disable(NRF_NFCT_Type * p_reg, uint32_t short_mask) +{ + nrf_nfct_shorts_disable(p_reg, short_mask); + nrf_barrier_w(); +} + +/** @refhal{nrf_nfct_shorts_get} */ +NRFY_STATIC_INLINE uint32_t nrfy_nfct_shorts_get(NRF_NFCT_Type const * p_reg) +{ + nrf_barrier_rw(); + uint32_t shorts = nrf_nfct_shorts_get(p_reg); + nrf_barrier_r(); + return shorts; +} + +/** @refhal{nrf_nfct_shorts_set} */ +NRFY_STATIC_INLINE void nrfy_nfct_shorts_set(NRF_NFCT_Type * p_reg, uint32_t short_mask) +{ + nrf_nfct_shorts_set(p_reg, short_mask); + nrf_barrier_w(); +} + +/** @refhal{nrf_nfct_int_enable} */ +NRFY_STATIC_INLINE void nrfy_nfct_int_enable(NRF_NFCT_Type * p_reg, uint32_t mask) +{ + nrf_nfct_int_enable(p_reg, mask); + nrf_barrier_w(); +} + +/** @refhal{nrf_nfct_int_enable_check} */ +NRFY_STATIC_INLINE uint32_t nrfy_nfct_int_enable_check(NRF_NFCT_Type const * p_reg, uint32_t mask) +{ + nrf_barrier_rw(); + uint32_t check = nrf_nfct_int_enable_check(p_reg, mask); + nrf_barrier_r(); + return check; +} + +/** @refhal{nrf_nfct_int_enable_get} */ +NRFY_STATIC_INLINE uint32_t nrfy_nfct_int_enable_get(NRF_NFCT_Type const * p_reg) +{ + nrf_barrier_rw(); + uint32_t check = nrf_nfct_int_enable_get(p_reg); + nrf_barrier_w(); + return check; +} + +/** @refhal{nrf_nfct_int_disable} */ +NRFY_STATIC_INLINE void nrfy_nfct_int_disable(NRF_NFCT_Type * p_reg, uint32_t mask) +{ + nrf_nfct_int_disable(p_reg, mask); + nrf_barrier_w(); +} + +#if NRFY_NFCT_HAS_MODULATION_PSEL_REG +/** @refhal{nrf_nfct_mod_ctrl_pin_set} */ +NRFY_STATIC_INLINE void nrfy_nfct_mod_ctrl_pin_set(NRF_NFCT_Type * p_reg, uint32_t mod_ctrl_pin) +{ + nrf_nfct_mod_ctrl_pin_set(p_reg, mod_ctrl_pin); + nrf_barrier_w(); +} + +/** @refhal{nrf_nfct_mod_ctrl_pin_get} */ +NRFY_STATIC_INLINE uint32_t nrfy_nfct_mod_ctrl_pin_get(NRF_NFCT_Type const * p_reg) +{ + nrf_barrier_rw(); + uint32_t pins = nrf_nfct_mod_ctrl_pin_get(p_reg); + nrf_barrier_r(); + return pins; +} +#endif // NRFY_NFCT_HAS_MODULATION_PSEL_REG + +/** @refhal{nrf_nfct_modulation_output_set} */ +#if NRFY_NFCT_HAS_MODULATION_CTRL_REG +NRFY_STATIC_INLINE void nrfy_nfct_modulation_output_set(NRF_NFCT_Type * p_reg, + nrf_nfct_modulation_ctrl_t mod_ctrl) +{ + nrf_nfct_modulation_output_set(p_reg, mod_ctrl); + nrf_barrier_w(); +} + +/** @refhal{nrf_nfct_modulation_output_get} */ +NRFY_STATIC_INLINE +nrf_nfct_modulation_ctrl_t nrfy_nfct_modulation_output_get(NRF_NFCT_Type const * p_reg) +{ + nrf_barrier_rw(); + nrf_nfct_modulation_ctrl_t modulation_ctrl = nrf_nfct_modulation_output_get(p_reg); + nrf_barrier_r(); + return modulation_ctrl; +} +#endif // NRFY_NFCT_HAS_MODULATION_CTRL_REG + +/** @refhal{nrf_nfct_error_status_get} */ +NRFY_STATIC_INLINE uint32_t nrfy_nfct_error_status_get(NRF_NFCT_Type const * p_reg) +{ + nrf_barrier_rw(); + uint32_t error_status = nrf_nfct_error_status_get(p_reg); + nrf_barrier_r(); + return error_status; +} + +/** @refhal{nrf_nfct_error_status_clear} */ +NRFY_STATIC_INLINE void nrfy_nfct_error_status_clear(NRF_NFCT_Type * p_reg, uint32_t error_flag) +{ + nrf_nfct_error_status_clear(p_reg, error_flag); + nrf_barrier_w(); +} + +/** @refhal{nrf_nfct_rx_frame_status_get} */ +NRFY_STATIC_INLINE uint32_t nrfy_nfct_rx_frame_status_get(NRF_NFCT_Type const * p_reg) +{ + nrf_barrier_rw(); + uint32_t frame_status = nrf_nfct_rx_frame_status_get(p_reg); + nrf_barrier_r(); + return frame_status; +} + +/** @refhal{nrf_nfct_rx_frame_status_clear} */ +NRFY_STATIC_INLINE void nrfy_nfct_rx_frame_status_clear(NRF_NFCT_Type * p_reg, + uint32_t framestatus_flags) +{ + nrf_nfct_rx_frame_status_clear(p_reg, framestatus_flags); + nrf_barrier_w(); +} + +#if NRFY_NFCT_HAS_TAG_STATE_REG +/** @refhal{nrf_nfct_tag_state_get} */ +NRFY_STATIC_INLINE nrf_nfct_tag_state_t nrfy_nfct_tag_state_get(NRF_NFCT_Type const * p_reg) +{ + nrf_barrier_r(); + nrf_nfct_tag_state_t tag_state = nrf_nfct_tag_state_get(p_reg); + nrf_barrier_r(); + return tag_state; +} +#endif // NRFY_NFCT_HAS_TAG_STATE_REG + +#if NRFY_NFCT_HAS_SLEEP_STATE_REG +/** @refhal{nrf_nfct_sleep_state_get} */ +NRFY_STATIC_INLINE nrf_nfct_sleep_state_t nrfy_nfct_sleep_state_get(NRF_NFCT_Type const * p_reg) +{ + nrf_barrier_r(); + nrf_nfct_sleep_state_t sleep_state = nrf_nfct_sleep_state_get(p_reg); + nrf_barrier_r(); + return sleep_state; +} +#endif // NRFY_NFCT_HAS_SLEEP_STATE_REG + +/** @refhal{nrf_nfct_field_status_get} */ +NRFY_STATIC_INLINE uint8_t nrfy_nfct_field_status_get(NRF_NFCT_Type const * p_reg) +{ + nrf_barrier_r(); + uint8_t status = nrf_nfct_field_status_get(p_reg); + nrf_barrier_r(); + return status; +} + +/** @refhal{nrf_nfct_frame_delay_min_get} */ +NRFY_STATIC_INLINE uint16_t nrfy_nfct_frame_delay_min_get(NRF_NFCT_Type const * p_reg) +{ + nrf_barrier_rw(); + uint16_t frame_delay_min = nrf_nfct_frame_delay_min_get(p_reg); + nrf_barrier_r(); + return frame_delay_min; +} + +/** @refhal{nrf_nfct_frame_delay_min_set} */ +NRFY_STATIC_INLINE void nrfy_nfct_frame_delay_min_set(NRF_NFCT_Type * p_reg, + uint16_t frame_delay_min) +{ + nrf_nfct_frame_delay_min_set(p_reg, frame_delay_min); + nrf_barrier_w(); +} + +/** @refhal{nrf_nfct_frame_delay_max_get} */ +NRFY_STATIC_INLINE uint32_t nrfy_nfct_frame_delay_max_get(NRF_NFCT_Type const * p_reg) +{ + nrf_barrier_rw(); + uint32_t frame_delay_max = nrf_nfct_frame_delay_max_get(p_reg); + nrf_barrier_r(); + return frame_delay_max; +} + +/** @refhal{nrf_nfct_frame_delay_max_set} */ +NRFY_STATIC_INLINE void nrfy_nfct_frame_delay_max_set(NRF_NFCT_Type * p_reg, + uint32_t frame_delay_max) +{ + nrf_nfct_frame_delay_max_set(p_reg, frame_delay_max); + nrf_barrier_w(); +} + +/** @refhal{nrf_nfct_frame_delay_mode_get} */ +NRFY_STATIC_INLINE +nrf_nfct_frame_delay_mode_t nrfy_nfct_frame_delay_mode_get(NRF_NFCT_Type const * p_reg) +{ + nrf_barrier_rw(); + nrf_nfct_frame_delay_mode_t frame_delay_mode = nrf_nfct_frame_delay_mode_get(p_reg); + nrf_barrier_r(); + return frame_delay_mode; +} + +/** @refhal{nrf_nfct_frame_delay_mode_set} */ +NRFY_STATIC_INLINE void nrfy_nfct_frame_delay_mode_set(NRF_NFCT_Type * p_reg, + nrf_nfct_frame_delay_mode_t frame_delay_mode) +{ + nrf_nfct_frame_delay_mode_set(p_reg, frame_delay_mode); + nrf_barrier_w(); +} + +/** @refhal{nrf_nfct_rxtx_buffer_get} */ +NRFY_STATIC_INLINE uint8_t * nrfy_nfct_rxtx_buffer_get(NRF_NFCT_Type const * p_reg) +{ + nrf_barrier_rw(); + uint8_t *buffer = nrf_nfct_rxtx_buffer_get(p_reg); + nrf_barrier_r(); + return buffer; +} + +/** @refhal{nrf_nfct_max_rxtx_length_get} */ +NRFY_STATIC_INLINE uint16_t nrfy_nfct_max_rxtx_length_get(NRF_NFCT_Type const * p_reg) +{ + nrf_barrier_rw(); + uint16_t max_length = nrf_nfct_max_rxtx_length_get(p_reg); + nrf_barrier_r(); + return max_length; +} + +/** @refhal{nrf_nfct_tx_frame_config_get} */ +NRFY_STATIC_INLINE uint8_t nrfy_nfct_tx_frame_config_get(NRF_NFCT_Type const * p_reg) +{ + nrf_barrier_rw(); + uint8_t frame_config = nrf_nfct_tx_frame_config_get(p_reg); + nrf_barrier_r(); + return frame_config; +} + +/** @refhal{nrf_nfct_tx_frame_config_set} */ +NRFY_STATIC_INLINE void nrfy_nfct_tx_frame_config_set(NRF_NFCT_Type * p_reg, uint8_t flags) +{ + nrf_nfct_rx_frame_config_set(p_reg, flags); + nrf_barrier_w(); +} + +/** @refhal{nrf_nfct_tx_bits_get} */ +NRFY_STATIC_INLINE uint16_t nrfy_nfct_tx_bits_get(NRF_NFCT_Type const * p_reg) +{ + nrf_barrier_rw(); + uint16_t bits = nrf_nfct_tx_bits_get(p_reg); + nrf_barrier_r(); + return bits; +} + +/** @refhal{nrf_nfct_tx_bits_set} */ +NRFY_STATIC_INLINE void nrfy_nfct_tx_bits_set(NRF_NFCT_Type * p_reg, uint16_t tx_bits) +{ + nrf_nfct_tx_bits_set(p_reg, tx_bits); + nrf_barrier_w(); +} + +/** @refhal{nrf_nfct_rx_frame_config_get} */ +NRFY_STATIC_INLINE uint8_t nrfy_nfct_rx_frame_config_get(NRF_NFCT_Type const * p_reg) +{ + nrf_barrier_rw(); + uint8_t frame_config = nrf_nfct_rx_frame_config_get(p_reg); + nrf_barrier_r(); + return frame_config; +} + +/** @refhal{nrf_nfct_rx_frame_config_set} */ +NRFY_STATIC_INLINE void nrfy_nfct_rx_frame_config_set(NRF_NFCT_Type * p_reg, uint8_t flags) +{ + nrf_nfct_rx_frame_config_set(p_reg, flags); + nrf_barrier_w(); +} + +/** @refhal{nrf_nfct_rx_bits_get} */ +NRFY_STATIC_INLINE uint16_t nrfy_nfct_rx_bits_get(NRF_NFCT_Type const * p_reg, bool crc_excluded) +{ + nrf_barrier_r(); + uint16_t rx_bits = nrf_nfct_rx_bits_get(p_reg, crc_excluded); + nrf_barrier_r(); + return rx_bits; +} + +/** @refhal{nrf_nfct_nfcid1_get} */ +NRFY_STATIC_INLINE +nrf_nfct_sensres_nfcid1_size_t nrfy_nfct_nfcid1_get(NRF_NFCT_Type const * p_reg, + uint8_t * p_nfcid1_buf) +{ + nrf_barrier_rw(); + nrf_nfct_sensres_nfcid1_size_t nfcid1_size = nrf_nfct_nfcid1_get(p_reg, p_nfcid1_buf); + nrf_barrier_rw(); + return nfcid1_size; +} + +/** @refhal{nrf_nfct_nfcid1_set} */ +NRFY_STATIC_INLINE void nrfy_nfct_nfcid1_set(NRF_NFCT_Type * p_reg, + uint8_t const * p_nfcid1_buf, + nrf_nfct_sensres_nfcid1_size_t nfcid1_size) +{ + nrf_nfct_nfcid1_set(p_reg, p_nfcid1_buf, nfcid1_size); + nrf_barrier_w(); +} + +#if NRFY_NFCT_HAS_AUTOCOLRES_CONFIG_REG +/** @refhal{nrf_nfct_autocolres_is_enabled} */ +NRFY_STATIC_INLINE bool nrfy_nfct_autocolres_is_enabled(NRF_NFCT_Type const * p_reg) +{ + nrf_barrier_rw(); + bool enabled = nrf_nfct_autocolres_is_enabled(p_reg); + nrf_barrier_r(); + return enabled; +} + +/** @refhal{nrf_nfct_autocolres_enable} */ +NRFY_STATIC_INLINE void nrfy_nfct_autocolres_enable(NRF_NFCT_Type * p_reg) +{ + nrf_nfct_autocolres_enable(p_reg); + nrf_barrier_w(); +} + +/** @refhal{nrf_nfct_autocolres_disable} */ +NRFY_STATIC_INLINE void nrfy_nfct_autocolres_disable(NRF_NFCT_Type * p_reg) +{ + nrf_nfct_autocolres_disable(p_reg); + nrf_barrier_w(); +} +#endif // NRFY_NFCT_HAS_AUTOCOLRES_CONFIG_REG + +/** @refhal{nrf_nfct_sensres_nfcid1_size_get} */ +NRFY_STATIC_INLINE +nrf_nfct_sensres_nfcid1_size_t nrfy_nfct_sensres_nfcid1_size_get(NRF_NFCT_Type const * p_reg) +{ + nrf_barrier_rw(); + nrf_nfct_sensres_nfcid1_size_t nfcid1_size = nrf_nfct_sensres_nfcid1_size_get(p_reg); + nrf_barrier_r(); + return nfcid1_size; +} + +/** @refhal{nrf_nfct_sensres_nfcid1_size_set} */ +NRFY_STATIC_INLINE +void nrfy_nfct_sensres_nfcid1_size_set(NRF_NFCT_Type * p_reg, + nrf_nfct_sensres_nfcid1_size_t nfcid1_size) +{ + nrf_nfct_sensres_nfcid1_size_set(p_reg, nfcid1_size); + nrf_barrier_w(); +} + +/** @refhal{nrf_nfct_sensres_bit_frame_sdd_get} */ +NRFY_STATIC_INLINE +nrf_nfct_sensres_bit_frame_sdd_t nrfy_nfct_sensres_bit_frame_sdd_get(NRF_NFCT_Type const * p_reg) +{ + nrf_barrier_rw(); + nrf_nfct_sensres_bit_frame_sdd_t frame_sdd = nrf_nfct_sensres_bit_frame_sdd_get(p_reg); + nrf_barrier_r(); + return frame_sdd; +} + +/** @refhal{nrf_nfct_sensres_bit_frame_sdd_set} */ +NRFY_STATIC_INLINE +void nrfy_nfct_sensres_bit_frame_sdd_set(NRF_NFCT_Type * p_reg, + nrf_nfct_sensres_bit_frame_sdd_t bit_frame_sdd) +{ + nrf_nfct_sensres_bit_frame_sdd_set(p_reg, bit_frame_sdd); + nrf_barrier_w(); +} + +/** @refhal{nrf_nfct_sensres_platform_config_get} */ +NRFY_STATIC_INLINE nrf_nfct_sensres_platform_config_t +nrfy_nfct_sensres_platform_config_get(NRF_NFCT_Type const * p_reg) +{ + nrf_barrier_rw(); + nrf_nfct_sensres_platform_config_t config = nrf_nfct_sensres_platform_config_get(p_reg); + nrf_barrier_r(); + return config; +} + +/** @refhal{nrf_nfct_sensres_platform_config_set} */ +NRFY_STATIC_INLINE +void nrfy_nfct_sensres_platform_config_set(NRF_NFCT_Type * p_reg, + nrf_nfct_sensres_platform_config_t platform_config) +{ + nrf_nfct_sensres_platform_config_set(p_reg, platform_config); + nrf_barrier_w(); +} + +/** @refhal{nrf_nfct_selres_cascade_check} */ +NRFY_STATIC_INLINE bool nrfy_nfct_selres_cascade_check(NRF_NFCT_Type const * p_reg) +{ + nrf_barrier_rw(); + bool check = nrf_nfct_selres_cascade_check(p_reg); + nrf_barrier_r(); + return check; +} + +/** @refhal{nrf_nfct_selres_protocol_get} */ +NRFY_STATIC_INLINE +nrf_nfct_selres_protocol_t nrfy_nfct_selres_protocol_get(NRF_NFCT_Type const * p_reg) +{ + nrf_barrier_rw(); + nrf_nfct_selres_protocol_t protocol = nrf_nfct_selres_protocol_get(p_reg); + nrf_barrier_r(); + return protocol; +} + +/** @refhal{nrf_nfct_selres_protocol_set} */ +NRFY_STATIC_INLINE void nrfy_nfct_selres_protocol_set(NRF_NFCT_Type * p_reg, + nrf_nfct_selres_protocol_t sel_res_protocol) +{ + nrf_nfct_selres_protocol_set(p_reg, sel_res_protocol); + nrf_barrier_w(); +} + +/** @refhal{nrf_nfct_selres_get} */ +NRFY_STATIC_INLINE uint32_t nrfy_nfct_selres_get(NRF_NFCT_Type const * p_reg) +{ + nrf_barrier_rw(); + uint32_t selres = nrf_nfct_selres_get(p_reg); + nrf_barrier_r(); + return selres; +} + +/** @refhal{nrf_nfct_selres_set} */ +NRFY_STATIC_INLINE void nrfy_nfct_selres_set(NRF_NFCT_Type * p_reg, uint32_t selres) +{ + nrf_nfct_selres_set(p_reg, selres); + nrf_barrier_w(); +} + +#if NRFY_NFCT_HAS_PAD_CONFIG_REG +/** @refhal{nrf_nfct_pad_config_enable_check} */ +NRFY_STATIC_INLINE bool nrfy_nfct_pad_config_enable_check(NRF_NFCT_Type const * p_reg) +{ + nrf_barrier_rw(); + bool enabled = nrf_nfct_pad_config_enable_check(p_reg); + nrf_barrier_w(); + return enabled; +} + +/** @refhal{nrf_nfct_pad_config_enable_set} */ +NRFY_STATIC_INLINE void nrfy_nfct_pad_config_enable_set(NRF_NFCT_Type * p_reg, bool enable) +{ + nrf_nfct_pad_config_enable_set(p_reg, enable); + nrf_barrier_w(); +} +#endif // NRFY_NFCT_HAS_PAD_CONFIG_REG + +#if NRFY_NFCT_HAS_BIAS_CONFIG_TRIM_REG +/** @refhal{nrf_nfct_bias_config_get} */ +NRFY_STATIC_INLINE void nrfy_nfct_bias_config_get(NRF_NFCT_Type const * p_reg, + nrf_nfct_bias_config_t * p_bias_config) +{ + nrf_barrier_rw(); + nrf_nfct_bias_config_get(p_reg, p_bias_config); + nrf_barrier_r(); +} + +/** @refhal{nrf_nfct_bias_config_set} */ +NRFY_STATIC_INLINE void nrfy_nfct_bias_config_set(NRF_NFCT_Type * p_reg, + nrf_nfct_bias_config_t const * p_bias_config) +{ + nrf_nfct_bias_config_set(p_reg, p_bias_config); + nrf_barrier_w(); +} +#endif // NRFY_NFCT_HAS_BIAS_CONFIG_TRIM_REG + +/** @} */ + +NRFY_STATIC_INLINE void __nrfy_internal_nfct_event_enabled_clear(NRF_NFCT_Type * p_reg, + uint32_t mask, + nrf_nfct_event_t event) +{ + if (mask & NRFY_EVENT_TO_INT_BITMASK(event)) + { + nrf_nfct_event_clear(p_reg, event); + } +} + +NRFY_STATIC_INLINE bool __nrfy_internal_nfct_event_handle(NRF_NFCT_Type * p_reg, + uint32_t mask, + nrf_nfct_event_t event, + uint32_t * p_evt_mask) +{ + if ((mask & NRFY_EVENT_TO_INT_BITMASK(event)) && nrf_nfct_event_check(p_reg, event)) + { + nrf_nfct_event_clear(p_reg, event); + if (p_evt_mask) + { + *p_evt_mask |= NRFY_EVENT_TO_INT_BITMASK(event); + } + return true; + } + + return false; +} + +NRFY_STATIC_INLINE uint32_t __nrfy_internal_nfct_events_process(NRF_NFCT_Type * p_reg, uint32_t mask) +{ + uint32_t evt_mask = 0; + + nrf_barrier_r(); + __nrfy_internal_nfct_event_handle(p_reg, mask, NRF_NFCT_EVENT_READY, &evt_mask); + __nrfy_internal_nfct_event_handle(p_reg, mask, NRF_NFCT_EVENT_FIELDDETECTED, &evt_mask); + __nrfy_internal_nfct_event_handle(p_reg, mask, NRF_NFCT_EVENT_FIELDLOST, &evt_mask); + __nrfy_internal_nfct_event_handle(p_reg, mask, NRF_NFCT_EVENT_TXFRAMESTART, &evt_mask); + __nrfy_internal_nfct_event_handle(p_reg, mask, NRF_NFCT_EVENT_TXFRAMEEND, &evt_mask); + __nrfy_internal_nfct_event_handle(p_reg, mask, NRF_NFCT_EVENT_RXFRAMESTART, &evt_mask); + __nrfy_internal_nfct_event_handle(p_reg, mask, NRF_NFCT_EVENT_RXFRAMEEND, &evt_mask); + __nrfy_internal_nfct_event_handle(p_reg, mask, NRF_NFCT_EVENT_ERROR, &evt_mask); + __nrfy_internal_nfct_event_handle(p_reg, mask, NRF_NFCT_EVENT_RXERROR, &evt_mask); + __nrfy_internal_nfct_event_handle(p_reg, mask, NRF_NFCT_EVENT_ENDRX, &evt_mask); + __nrfy_internal_nfct_event_handle(p_reg, mask, NRF_NFCT_EVENT_ENDTX, &evt_mask); + __nrfy_internal_nfct_event_handle(p_reg, mask, NRF_NFCT_EVENT_AUTOCOLRESSTARTED, &evt_mask); + __nrfy_internal_nfct_event_handle(p_reg, mask, NRF_NFCT_EVENT_COLLISION, &evt_mask); + __nrfy_internal_nfct_event_handle(p_reg, mask, NRF_NFCT_EVENT_SELECTED, &evt_mask); + __nrfy_internal_nfct_event_handle(p_reg, mask, NRF_NFCT_EVENT_STARTED, &evt_mask); + + if (evt_mask & NRFY_EVENT_TO_INT_BITMASK(NRF_NFCT_EVENT_RXFRAMEEND)) + { + uint8_t *buffer = nrf_nfct_rxtx_buffer_get(p_reg); + uint16_t bytes = (nrf_nfct_rx_bits_get(p_reg, true) >> 3U); + + nrf_barrier_rw(); + NRFY_CACHE_INV(buffer, bytes); + } + + nrf_barrier_w(); + + return evt_mask; +} + +#ifdef __cplusplus +} +#endif + +#endif // NRFY_NFCT_H__ diff --git a/haly/nrfy_temp.h b/haly/nrfy_temp.h index e1f54bd44..049661c00 100644 --- a/haly/nrfy_temp.h +++ b/haly/nrfy_temp.h @@ -49,6 +49,13 @@ extern "C" { for managing the Temperature sensor (TEMP). */ +#if NRF_TEMP_HAS_CALIBRATION || defined(__NRFX_DOXYGEN__) +/** @refhal{NRF_TEMP_HAS_CALIBRATION} */ +#define NRFY_TEMP_HAS_CALIBRATION 1 +#else +#define NRFY_TEMP_HAS_CALIBRATION 0 +#endif + /** * @brief Function for initializing the specified TEMP interrupts. * @@ -155,6 +162,24 @@ NRF_STATIC_INLINE int32_t nrfy_temp_result_get(NRF_TEMP_Type const * p_reg) return temperature; } +#if NRFY_TEMP_HAS_CALIBRATION +/** @refhal{nrf_temp_calibration_coeff_set} */ +NRF_STATIC_INLINE void nrfy_temp_calibration_coeff_set(NRF_TEMP_Type * p_reg, uint32_t coeff) +{ + nrf_temp_calibration_coeff_set(p_reg, coeff); + nrf_barrier_w(); +} + +/** @refhal{nrf_temp_calibration_coeff_get} */ +NRF_STATIC_INLINE uint32_t nrfy_temp_calibration_coeff_get(NRF_TEMP_Type const * p_reg) +{ + nrf_barrier_rw(); + uint32_t coeff = nrf_temp_calibration_coeff_get(p_reg); + nrf_barrier_r(); + return coeff; +} +#endif + /** @} */ #ifdef __cplusplus diff --git a/mdk/nrf.h b/mdk/nrf.h index a1174ca0e..89fa9ec49 100644 --- a/mdk/nrf.h +++ b/mdk/nrf.h @@ -37,8 +37,8 @@ POSSIBILITY OF SUCH DAMAGE. /* MDK version */ #define MDK_MAJOR_VERSION 8 -#define MDK_MINOR_VERSION 53 -#define MDK_MICRO_VERSION 1 +#define MDK_MINOR_VERSION 55 +#define MDK_MICRO_VERSION 0 /* Define coprocessor domains */ diff --git a/mdk/nrf51.h b/mdk/nrf51.h index 6cf49d85d..ccef50e19 100644 --- a/mdk/nrf51.h +++ b/mdk/nrf51.h @@ -32,10 +32,10 @@ POSSIBILITY OF SUCH DAMAGE.\n * @file nrf51.h * @brief CMSIS HeaderFile * @version 522 - * @date 04. April 2023 - * @note Generated by SVDConv V3.3.35 on Tuesday, 04.04.2023 11:58:28 + * @date 22. June 2023 + * @note Generated by SVDConv V3.3.35 on Thursday, 22.06.2023 08:53:07 * from File 'nrf51.svd', - * last modified on Tuesday, 04.04.2023 09:57:13 + * last modified on Thursday, 22.06.2023 06:51:53 */ diff --git a/mdk/nrf52.h b/mdk/nrf52.h index 86c537917..26d2d36a4 100644 --- a/mdk/nrf52.h +++ b/mdk/nrf52.h @@ -32,10 +32,10 @@ POSSIBILITY OF SUCH DAMAGE. * @file nrf52.h * @brief CMSIS HeaderFile * @version 1 - * @date 04. April 2023 - * @note Generated by SVDConv V3.3.35 on Tuesday, 04.04.2023 11:58:33 + * @date 22. June 2023 + * @note Generated by SVDConv V3.3.35 on Thursday, 22.06.2023 08:53:14 * from File 'nrf52.svd', - * last modified on Tuesday, 04.04.2023 09:57:13 + * last modified on Thursday, 22.06.2023 06:51:53 */ diff --git a/mdk/nrf52805.h b/mdk/nrf52805.h index 3f8f1d6b6..7a8c94b60 100644 --- a/mdk/nrf52805.h +++ b/mdk/nrf52805.h @@ -32,10 +32,10 @@ POSSIBILITY OF SUCH DAMAGE.\n * @file nrf52805.h * @brief CMSIS HeaderFile * @version 1 - * @date 04. April 2023 - * @note Generated by SVDConv V3.3.35 on Tuesday, 04.04.2023 11:58:28 + * @date 22. June 2023 + * @note Generated by SVDConv V3.3.35 on Thursday, 22.06.2023 08:53:08 * from File 'nrf52805.svd', - * last modified on Tuesday, 04.04.2023 09:57:14 + * last modified on Thursday, 22.06.2023 06:51:53 */ diff --git a/mdk/nrf52810.h b/mdk/nrf52810.h index b15e8b4cb..1a05c2d79 100644 --- a/mdk/nrf52810.h +++ b/mdk/nrf52810.h @@ -32,10 +32,10 @@ POSSIBILITY OF SUCH DAMAGE.\n * @file nrf52810.h * @brief CMSIS HeaderFile * @version 1 - * @date 04. April 2023 - * @note Generated by SVDConv V3.3.35 on Tuesday, 04.04.2023 11:58:29 + * @date 22. June 2023 + * @note Generated by SVDConv V3.3.35 on Thursday, 22.06.2023 08:53:10 * from File 'nrf52810.svd', - * last modified on Tuesday, 04.04.2023 09:57:14 + * last modified on Thursday, 22.06.2023 06:51:53 */ diff --git a/mdk/nrf52811.h b/mdk/nrf52811.h index 56732a95e..bf488d971 100644 --- a/mdk/nrf52811.h +++ b/mdk/nrf52811.h @@ -32,10 +32,10 @@ POSSIBILITY OF SUCH DAMAGE.\n * @file nrf52811.h * @brief CMSIS HeaderFile * @version 1 - * @date 04. April 2023 - * @note Generated by SVDConv V3.3.35 on Tuesday, 04.04.2023 11:58:31 + * @date 22. June 2023 + * @note Generated by SVDConv V3.3.35 on Thursday, 22.06.2023 08:53:11 * from File 'nrf52811.svd', - * last modified on Tuesday, 04.04.2023 09:57:14 + * last modified on Thursday, 22.06.2023 06:51:53 */ diff --git a/mdk/nrf52820.h b/mdk/nrf52820.h index 06ef0755d..76ed69045 100644 --- a/mdk/nrf52820.h +++ b/mdk/nrf52820.h @@ -32,10 +32,10 @@ POSSIBILITY OF SUCH DAMAGE.\n * @file nrf52820.h * @brief CMSIS HeaderFile * @version 1 - * @date 04. April 2023 - * @note Generated by SVDConv V3.3.35 on Tuesday, 04.04.2023 11:58:32 + * @date 22. June 2023 + * @note Generated by SVDConv V3.3.35 on Thursday, 22.06.2023 08:53:12 * from File 'nrf52820.svd', - * last modified on Tuesday, 04.04.2023 09:57:14 + * last modified on Thursday, 22.06.2023 06:51:53 */ diff --git a/mdk/nrf52833.h b/mdk/nrf52833.h index f9c0bcf63..57fe49de9 100644 --- a/mdk/nrf52833.h +++ b/mdk/nrf52833.h @@ -32,10 +32,10 @@ POSSIBILITY OF SUCH DAMAGE.\n * @file nrf52833.h * @brief CMSIS HeaderFile * @version 1 - * @date 04. April 2023 - * @note Generated by SVDConv V3.3.35 on Tuesday, 04.04.2023 11:58:35 + * @date 22. June 2023 + * @note Generated by SVDConv V3.3.35 on Thursday, 22.06.2023 08:53:16 * from File 'nrf52833.svd', - * last modified on Tuesday, 04.04.2023 09:57:14 + * last modified on Thursday, 22.06.2023 06:51:53 */ diff --git a/mdk/nrf52840.h b/mdk/nrf52840.h index ca458c0a1..a16969c21 100644 --- a/mdk/nrf52840.h +++ b/mdk/nrf52840.h @@ -32,10 +32,10 @@ POSSIBILITY OF SUCH DAMAGE.\n * @file nrf52840.h * @brief CMSIS HeaderFile * @version 1 - * @date 04. April 2023 - * @note Generated by SVDConv V3.3.35 on Tuesday, 04.04.2023 11:58:37 + * @date 22. June 2023 + * @note Generated by SVDConv V3.3.35 on Thursday, 22.06.2023 08:53:18 * from File 'nrf52840.svd', - * last modified on Tuesday, 04.04.2023 09:57:14 + * last modified on Thursday, 22.06.2023 06:51:54 */ diff --git a/mdk/nrf52_erratas.h b/mdk/nrf52_erratas.h index 7347c320f..2dfb5b889 100644 --- a/mdk/nrf52_erratas.h +++ b/mdk/nrf52_erratas.h @@ -215,6 +215,7 @@ static bool nrf52_errata_232(void) __UNUSED; static bool nrf52_errata_233(void) __UNUSED; static bool nrf52_errata_236(void) __UNUSED; static bool nrf52_errata_237(void) __UNUSED; +static bool nrf52_errata_241(void) __UNUSED; static bool nrf52_errata_242(void) __UNUSED; static bool nrf52_errata_243(void) __UNUSED; static bool nrf52_errata_244(void) __UNUSED; @@ -12336,6 +12337,176 @@ static bool nrf52_errata_237(void) #endif } +/* ========= Errata 241 ========= */ +#if defined (NRF52805_XXAA) || defined (DEVELOP_IN_NRF52805) \ + || defined (NRF52810_XXAA) || defined (DEVELOP_IN_NRF52810) \ + || defined (NRF52811_XXAA) || defined (DEVELOP_IN_NRF52811) \ + || defined (NRF52820_XXAA) || defined (DEVELOP_IN_NRF52820) \ + || defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832) \ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) \ + || defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833) \ + || defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + #define NRF52_ERRATA_241_PRESENT 1 +#else + #define NRF52_ERRATA_241_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_241_ENABLE_WORKAROUND + #define NRF52_ERRATA_241_ENABLE_WORKAROUND NRF52_ERRATA_241_PRESENT +#endif + +static bool nrf52_errata_241(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + uint32_t var1; + uint32_t var2; + + if (*(uint32_t *)0x10000130ul == 0xFFFFFFFF) + { + var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + } + else + { + var1 = *(uint32_t *)0x10000130ul; + var2 = *(uint32_t *)0x10000134ul; + } + #elif defined (NRF52805_XXAA) || defined (DEVELOP_IN_NRF52805)\ + || defined (NRF52810_XXAA) || defined (DEVELOP_IN_NRF52810)\ + || defined (NRF52811_XXAA) || defined (DEVELOP_IN_NRF52811)\ + || defined (NRF52820_XXAA) || defined (DEVELOP_IN_NRF52820)\ + || defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833)\ + || defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + uint32_t var1 = *(uint32_t *)0x10000130ul; + uint32_t var2 = *(uint32_t *)0x10000134ul; + #endif + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + if (var1 == 0x06) + { + switch(var2) + { + case 0x03ul: + return false; + case 0x04ul: + return false; + case 0x05ul: + return true; + case 0x06ul: + return true; + case 0x07ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + if (var1 == 0x08) + { + switch(var2) + { + case 0x00ul: + return false; + case 0x01ul: + return false; + case 0x02ul: + return true; + case 0x03ul: + return true; + case 0x04ul: + return true; + case 0x05ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52810_XXAA) || defined (DEVELOP_IN_NRF52810) + if (var1 == 0x0A) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + case 0x02ul: + return false; + default: + return false; + } + } + #endif + #if defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833) + if (var1 == 0x0D) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52811_XXAA) || defined (DEVELOP_IN_NRF52811) + if (var1 == 0x0E) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return false; + default: + return false; + } + } + #endif + #if defined (NRF52805_XXAA) || defined (DEVELOP_IN_NRF52805) + if (var1 == 0x0F) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52820_XXAA) || defined (DEVELOP_IN_NRF52820) + if (var1 == 0x10) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + case 0x02ul: + return false; + case 0x03ul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + /* ========= Errata 242 ========= */ #if defined (NRF52805_XXAA) || defined (DEVELOP_IN_NRF52805) \ || defined (NRF52810_XXAA) || defined (DEVELOP_IN_NRF52810) \ diff --git a/mdk/nrf5340_application.h b/mdk/nrf5340_application.h index 4fc1af1e6..4df3121d9 100644 --- a/mdk/nrf5340_application.h +++ b/mdk/nrf5340_application.h @@ -32,10 +32,10 @@ POSSIBILITY OF SUCH DAMAGE. * @file nrf5340_application.h * @brief CMSIS HeaderFile * @version 1 - * @date 04. April 2023 - * @note Generated by SVDConv V3.3.35 on Tuesday, 04.04.2023 11:58:39 + * @date 22. June 2023 + * @note Generated by SVDConv V3.3.35 on Thursday, 22.06.2023 08:53:20 * from File 'nrf5340_application.svd', - * last modified on Tuesday, 04.04.2023 09:57:14 + * last modified on Thursday, 22.06.2023 06:51:54 */ diff --git a/mdk/nrf5340_network.h b/mdk/nrf5340_network.h index e4bc2dcf9..957504833 100644 --- a/mdk/nrf5340_network.h +++ b/mdk/nrf5340_network.h @@ -32,10 +32,10 @@ POSSIBILITY OF SUCH DAMAGE. * @file nrf5340_network.h * @brief CMSIS HeaderFile * @version 1 - * @date 04. April 2023 - * @note Generated by SVDConv V3.3.35 on Tuesday, 04.04.2023 11:58:49 + * @date 22. June 2023 + * @note Generated by SVDConv V3.3.35 on Thursday, 22.06.2023 08:53:31 * from File 'nrf5340_network.svd', - * last modified on Tuesday, 04.04.2023 09:57:14 + * last modified on Thursday, 22.06.2023 06:51:54 */ diff --git a/mdk/nrf53_erratas.h b/mdk/nrf53_erratas.h index e8803dbc1..9ad1038fa 100644 --- a/mdk/nrf53_erratas.h +++ b/mdk/nrf53_erratas.h @@ -142,6 +142,7 @@ static bool nrf53_errata_140(void) __UNUSED; static bool nrf53_errata_152(void) __UNUSED; static bool nrf53_errata_153(void) __UNUSED; static bool nrf53_errata_154(void) __UNUSED; +static bool nrf53_errata_157(void) __UNUSED; static bool nrf53_errata_158(void) __UNUSED; static bool nrf53_errata_160(void) __UNUSED; static bool nrf53_errata_161(void) __UNUSED; @@ -5748,6 +5749,66 @@ static bool nrf53_errata_154(void) #endif } +/* ========= Errata 157 ========= */ +#if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) || \ + defined(NRF_NETWORK) + #define NRF53_ERRATA_157_PRESENT 1 + #else + #define NRF53_ERRATA_157_PRESENT 0 + #endif +#else + #define NRF53_ERRATA_157_PRESENT 0 +#endif + +#ifndef NRF53_ERRATA_157_ENABLE_WORKAROUND + #define NRF53_ERRATA_157_ENABLE_WORKAROUND NRF53_ERRATA_157_PRESENT +#endif + +static bool nrf53_errata_157(void) +{ + #ifndef NRF53_SERIES + return false; + #else + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) + #if defined(NRF_TRUSTZONE_NONSECURE) + uint32_t var1 = *((volatile uint32_t *)((uint32_t)NRF_FICR_NS + 0x00000130ul)); + uint32_t var2 = *((volatile uint32_t *)((uint32_t)NRF_FICR_NS + 0x00000134ul)); + #else + uint32_t var1 = *((volatile uint32_t *)((uint32_t)NRF_FICR_S + 0x00000130ul)); + uint32_t var2 = *((volatile uint32_t *)((uint32_t)NRF_FICR_S + 0x00000134ul)); + #endif + #elif defined(NRF_NETWORK) + uint32_t var1 = *(uint32_t *)0x01FF0130ul; + uint32_t var2 = *(uint32_t *)0x01FF0134ul; + #endif + #endif + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined (NRF_APPLICATION)\ + || defined (NRF_NETWORK) + if (var1 == 0x07) + { + switch(var2) + { + case 0x02ul: + return false; + case 0x03ul: + return false; + case 0x04ul: + return false; + case 0x05ul: + return true; + default: + return true; + } + } + #endif + #endif + return false; + #endif +} + /* ========= Errata 158 ========= */ #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) #if defined(NRF_NETWORK) @@ -5879,13 +5940,22 @@ static bool nrf53_errata_161(void) return false; #else #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) - #if defined(NRF_NETWORK) + #if defined(NRF_APPLICATION) + #if defined(NRF_TRUSTZONE_NONSECURE) + uint32_t var1 = *((volatile uint32_t *)((uint32_t)NRF_FICR_NS + 0x00000130ul)); + uint32_t var2 = *((volatile uint32_t *)((uint32_t)NRF_FICR_NS + 0x00000134ul)); + #else + uint32_t var1 = *((volatile uint32_t *)((uint32_t)NRF_FICR_S + 0x00000130ul)); + uint32_t var2 = *((volatile uint32_t *)((uint32_t)NRF_FICR_S + 0x00000134ul)); + #endif + #elif defined(NRF_NETWORK) uint32_t var1 = *(uint32_t *)0x01FF0130ul; uint32_t var2 = *(uint32_t *)0x01FF0134ul; #endif #endif #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) - #if defined (NRF_NETWORK) + #if defined (NRF_APPLICATION)\ + || defined (NRF_NETWORK) if (var1 == 0x07) { switch(var2) diff --git a/mdk/nrf9120.h b/mdk/nrf9120.h index 6a62070ae..3fe331f1b 100644 --- a/mdk/nrf9120.h +++ b/mdk/nrf9120.h @@ -32,10 +32,10 @@ POSSIBILITY OF SUCH DAMAGE. * @file nrf9120.h * @brief CMSIS HeaderFile * @version 1 - * @date 04. April 2023 - * @note Generated by SVDConv V3.3.35 on Tuesday, 04.04.2023 11:58:51 + * @date 22. June 2023 + * @note Generated by SVDConv V3.3.35 on Thursday, 22.06.2023 08:53:33 * from File 'nrf9120.svd', - * last modified on Tuesday, 04.04.2023 09:57:14 + * last modified on Thursday, 22.06.2023 06:51:54 */ @@ -152,6 +152,31 @@ typedef enum { #endif +/* ======================================== Start of section using anonymous unions ======================================== */ +#if defined (__CC_ARM) + #pragma push + #pragma anon_unions +#elif defined (__ICCARM__) + #pragma language=extended +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wc11-extensions" + #pragma clang diagnostic ignored "-Wreserved-id-macro" + #pragma clang diagnostic ignored "-Wgnu-anonymous-struct" + #pragma clang diagnostic ignored "-Wnested-anon-types" +#elif defined (__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined (__TMS470__) + /* anonymous unions are enabled by default */ +#elif defined (__TASKING__) + #pragma warning 586 +#elif defined (__CSMC__) + /* anonymous unions are enabled by default */ +#else + #warning Not supported compiler type +#endif + + /* =========================================================================================================================== */ /* ================ Device Specific Cluster Section ================ */ /* =========================================================================================================================== */ @@ -712,18 +737,22 @@ typedef struct { * @brief APPROTECT_SECUREAPPROTECT [SECUREAPPROTECT] (Unspecified) */ typedef struct { - __IOM uint32_t DISABLE; /*!< (@ 0x00000000) Software disable SECUREAPPROTECT mechanism */ - __IOM uint32_t FORCEPROTECT; /*!< (@ 0x00000004) Software force SECUREAPPROTECT mechanism */ -} APPROTECT_SECUREAPPROTECT_Type; /*!< Size = 8 (0x8) */ + union { + __IOM uint32_t DISABLE; /*!< (@ 0x00000000) Software disable SECUREAPPROTECT mechanism */ + __IOM uint32_t FORCEPROTECT; /*!< (@ 0x00000000) Software force SECUREAPPROTECT mechanism */ + }; +} APPROTECT_SECUREAPPROTECT_Type; /*!< Size = 4 (0x4) */ /** * @brief APPROTECT_APPROTECT [APPROTECT] (Unspecified) */ typedef struct { - __IOM uint32_t DISABLE; /*!< (@ 0x00000000) Software disable APPROTECT mechanism */ - __IOM uint32_t FORCEPROTECT; /*!< (@ 0x00000004) Software force APPROTECT mechanism */ -} APPROTECT_APPROTECT_Type; /*!< Size = 8 (0x8) */ + union { + __IOM uint32_t DISABLE; /*!< (@ 0x00000000) Software disable APPROTECT mechanism */ + __IOM uint32_t FORCEPROTECT; /*!< (@ 0x00000000) Software force APPROTECT mechanism */ + }; +} APPROTECT_APPROTECT_Type; /*!< Size = 4 (0x4) */ /** @@ -1884,7 +1913,7 @@ typedef struct { /*!< (@ 0x4002A000) IPC_NS Struc /** - * @brief FPU 0 (FPU_NS) + * @brief FPU (FPU_NS) */ typedef struct { /*!< (@ 0x4002C000) FPU_NS Structure */ @@ -1905,9 +1934,9 @@ typedef struct { /*!< (@ 0x4002C000) FPU_NS Struc typedef struct { /*!< (@ 0x40039000) APPROTECT_NS Structure */ __IM uint32_t RESERVED[896]; __IOM APPROTECT_SECUREAPPROTECT_Type SECUREAPPROTECT;/*!< (@ 0x00000E00) Unspecified */ - __IM uint32_t RESERVED1[2]; + __IM uint32_t RESERVED1[3]; __IOM APPROTECT_APPROTECT_Type APPROTECT; /*!< (@ 0x00000E10) Unspecified */ -} NRF_APPROTECT_Type; /*!< Size = 3608 (0xe18) */ +} NRF_APPROTECT_Type; /*!< Size = 3604 (0xe14) */ @@ -2183,7 +2212,6 @@ typedef struct { /*!< (@ 0x40842500) P0_NS Struct #define NRF_IPC_NS_BASE 0x4002A000UL #define NRF_IPC_S_BASE 0x5002A000UL #define NRF_FPU_NS_BASE 0x4002C000UL -#define NRF_FPU_S_BASE 0x5002C000UL #define NRF_GPIOTE1_NS_BASE 0x40031000UL #define NRF_APPROTECT_NS_BASE 0x40039000UL #define NRF_KMU_NS_BASE 0x40039000UL @@ -2305,7 +2333,6 @@ typedef struct { /*!< (@ 0x40842500) P0_NS Struct #define NRF_IPC_NS ((NRF_IPC_Type*) NRF_IPC_NS_BASE) #define NRF_IPC_S ((NRF_IPC_Type*) NRF_IPC_S_BASE) #define NRF_FPU_NS ((NRF_FPU_Type*) NRF_FPU_NS_BASE) -#define NRF_FPU_S ((NRF_FPU_Type*) NRF_FPU_S_BASE) #define NRF_GPIOTE1_NS ((NRF_GPIOTE_Type*) NRF_GPIOTE1_NS_BASE) #define NRF_APPROTECT_NS ((NRF_APPROTECT_Type*) NRF_APPROTECT_NS_BASE) #define NRF_KMU_NS ((NRF_KMU_Type*) NRF_KMU_NS_BASE) @@ -2323,6 +2350,24 @@ typedef struct { /*!< (@ 0x40842500) P0_NS Struct /** @} */ /* End of group Device_Peripheral_declaration */ +/* ========================================= End of section using anonymous unions ========================================= */ +#if defined (__CC_ARM) + #pragma pop +#elif defined (__ICCARM__) + /* leave anonymous unions enabled */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop +#elif defined (__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined (__TMS470__) + /* anonymous unions are enabled by default */ +#elif defined (__TASKING__) + #pragma warning restore +#elif defined (__CSMC__) + /* anonymous unions are enabled by default */ +#endif + + #ifdef __cplusplus } #endif diff --git a/mdk/nrf9120.svd b/mdk/nrf9120.svd index 63f7838ae..83cfe0200 100644 --- a/mdk/nrf9120.svd +++ b/mdk/nrf9120.svd @@ -109,7 +109,7 @@ POSSIBILITY OF SUCH DAMAGE. Description collection: SIP hardware revision, encoded in ASCII, ex B0A or B1A 0x004 read-only - 0x000000FF + 0xFF uint8_t 0x8 @@ -127,7 +127,7 @@ POSSIBILITY OF SUCH DAMAGE. Description collection: SIP VARIANT, encoded in ASCII, ex SIAA, SIBA or SICA 0x008 read-only - 0x000000FF + 0xFF uint8_t 0x8 @@ -178,12 +178,12 @@ POSSIBILITY OF SUCH DAMAGE. N9160 nRF9160 - 0x9160 + 0x00009160 N9120 nRF9120 - 0x9120 + 0x00009120 @@ -242,7 +242,7 @@ POSSIBILITY OF SUCH DAMAGE. CF CFxx - 236 ball wlCSP - 0x2002 + 0x00002002 @@ -264,7 +264,7 @@ POSSIBILITY OF SUCH DAMAGE. K256 256 kByte RAM - 0x100 + 0x00000100 Unspecified @@ -291,7 +291,7 @@ POSSIBILITY OF SUCH DAMAGE. K1024 1 MByte FLASH - 0x400 + 0x00000400 @@ -313,7 +313,7 @@ POSSIBILITY OF SUCH DAMAGE. K4096 4 kByte - 0x1000 + 0x00001000 @@ -335,7 +335,7 @@ POSSIBILITY OF SUCH DAMAGE. P256 256 pages - 256 + 0x00000100 @@ -357,7 +357,7 @@ POSSIBILITY OF SUCH DAMAGE. Die Device is an physical DIE - 0x0000000 + 0x00000000 FPGA @@ -611,12 +611,12 @@ POSSIBILITY OF SUCH DAMAGE. XTAL 32 MHz crystal oscillator - 1 + 0x1 TCXO 32 MHz temperature compensated crystal oscillator (TCXO) - 0 + 0x0 @@ -638,12 +638,12 @@ POSSIBILITY OF SUCH DAMAGE. MinDebounceTime Min debounce time = (0*64 us + 0.5 us) - 0 + 0x00 MaxDebounceTime Max debounce time = (255*64 us + 0.5 us) - 255 + 0xFF @@ -665,12 +665,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled NVM WRITE and NVM ERASE are not blocked in POFWARN condition - 0 + 0x0 Enabled NVM WRITE and NVM ERASE are blocked in POFWARN condition - 1 + 0x1 @@ -692,12 +692,12 @@ POSSIBILITY OF SUCH DAMAGE. ActiveLow PMIC_FPWM output signal is active-low - 0 + 0x0 ActiveHigh PMIC_FPWM output signal is active-high - 1 + 0x1 @@ -831,12 +831,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Disable write to the key value registers - 0 + 0x0 Enabled Enable write to the key value registers - 1 + 0x1 @@ -849,12 +849,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Disable read from key value registers - 0 + 0x0 Enabled Enable read from key value registers - 1 + 0x1 @@ -867,12 +867,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Disable pushing of key value registers over secure APB, but can be read if field READ is Enabled - 0 + 0x0 Enabled Enable pushing of key value registers over secure APB. Register KEYSLOT.CONFIGn.DEST must contain a valid destination address! - 1 + 0x1 @@ -885,12 +885,12 @@ POSSIBILITY OF SUCH DAMAGE. Revoked Key value registers can no longer be read or pushed - 0 + 0x0 Active Key value registers are readable (if enabled) and can be pushed (if enabled) - 1 + 0x1 @@ -946,6 +946,7 @@ POSSIBILITY OF SUCH DAMAGE. Start all trace and debug clocks. 0x000 write-only + 0x00000000 TASKS_CLOCKSTART @@ -956,7 +957,7 @@ POSSIBILITY OF SUCH DAMAGE. Trigger Trigger task - 1 + 0x1 @@ -967,6 +968,7 @@ POSSIBILITY OF SUCH DAMAGE. Stop all trace and debug clocks. 0x004 write-only + 0x00000000 TASKS_CLOCKSTOP @@ -977,7 +979,7 @@ POSSIBILITY OF SUCH DAMAGE. Trigger Trigger task - 1 + 0x1 @@ -988,6 +990,7 @@ POSSIBILITY OF SUCH DAMAGE. Enable debug domain and aquire selected GPIOs 0x500 read-write + 0x00000000 ENABLE @@ -997,12 +1000,12 @@ POSSIBILITY OF SUCH DAMAGE. DISABLED Disable debug domain and release selected GPIOs - 0 + 0x0 ENABLED Enable debug domain and aquire selected GPIOs - 1 + 0x1 @@ -1030,7 +1033,7 @@ POSSIBILITY OF SUCH DAMAGE. Traceclk TRACECLK pin - 21 + 0x15 @@ -1043,12 +1046,12 @@ POSSIBILITY OF SUCH DAMAGE. Disconnected Disconnect - 1 + 0x1 Connected Connect - 0 + 0x0 @@ -1070,7 +1073,7 @@ POSSIBILITY OF SUCH DAMAGE. Tracedata0 TRACEDATA0 pin - 22 + 0x16 @@ -1083,12 +1086,12 @@ POSSIBILITY OF SUCH DAMAGE. Disconnected Disconnect - 1 + 0x1 Connected Connect - 0 + 0x0 @@ -1110,7 +1113,7 @@ POSSIBILITY OF SUCH DAMAGE. Tracedata1 TRACEDATA1 pin - 23 + 0x17 @@ -1123,12 +1126,12 @@ POSSIBILITY OF SUCH DAMAGE. Disconnected Disconnect - 1 + 0x1 Connected Connect - 0 + 0x0 @@ -1150,7 +1153,7 @@ POSSIBILITY OF SUCH DAMAGE. Tracedata2 TRACEDATA2 pin - 24 + 0x18 @@ -1163,12 +1166,12 @@ POSSIBILITY OF SUCH DAMAGE. Disconnected Disconnect - 1 + 0x1 Connected Connect - 0 + 0x0 @@ -1190,7 +1193,7 @@ POSSIBILITY OF SUCH DAMAGE. Tracedata3 TRACEDATA3 pin - 25 + 0x19 @@ -1203,12 +1206,12 @@ POSSIBILITY OF SUCH DAMAGE. Disconnected Disconnect - 1 + 0x1 Connected Connect - 0 + 0x0 @@ -1231,22 +1234,22 @@ POSSIBILITY OF SUCH DAMAGE. 32MHz Trace Port clock is: 32MHz - 0 + 0x0 16MHz Trace Port clock is: 16MHz - 1 + 0x1 8MHz Trace Port clock is: 8MHz - 2 + 0x2 4MHz Trace Port clock is: 4MHz - 3 + 0x3 @@ -1278,6 +1281,7 @@ POSSIBILITY OF SUCH DAMAGE. A security violation has been detected for the RAM memory space 0x100 read-write + 0x00000000 EVENTS_RAMACCERR @@ -1288,12 +1292,12 @@ POSSIBILITY OF SUCH DAMAGE. NotGenerated Event not generated - 0 + 0x0 Generated Event generated - 1 + 0x1 @@ -1304,6 +1308,7 @@ POSSIBILITY OF SUCH DAMAGE. A security violation has been detected for the flash memory space 0x104 read-write + 0x00000000 EVENTS_FLASHACCERR @@ -1314,12 +1319,12 @@ POSSIBILITY OF SUCH DAMAGE. NotGenerated Event not generated - 0 + 0x0 Generated Event generated - 1 + 0x1 @@ -1330,6 +1335,7 @@ POSSIBILITY OF SUCH DAMAGE. A security violation has been detected on one or several peripherals 0x108 read-write + 0x00000000 EVENTS_PERIPHACCERR @@ -1340,12 +1346,12 @@ POSSIBILITY OF SUCH DAMAGE. NotGenerated Event not generated - 0 + 0x0 Generated Event generated - 1 + 0x1 @@ -1356,6 +1362,7 @@ POSSIBILITY OF SUCH DAMAGE. Publish configuration for event RAMACCERR 0x180 read-write + 0x00000000 CHIDX @@ -1371,12 +1378,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Disable publishing - 0 + 0x0 Enabled Enable publishing - 1 + 0x1 @@ -1387,6 +1394,7 @@ POSSIBILITY OF SUCH DAMAGE. Publish configuration for event FLASHACCERR 0x184 read-write + 0x00000000 CHIDX @@ -1402,12 +1410,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Disable publishing - 0 + 0x0 Enabled Enable publishing - 1 + 0x1 @@ -1418,6 +1426,7 @@ POSSIBILITY OF SUCH DAMAGE. Publish configuration for event PERIPHACCERR 0x188 read-write + 0x00000000 CHIDX @@ -1433,12 +1442,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Disable publishing - 0 + 0x0 Enabled Enable publishing - 1 + 0x1 @@ -1449,6 +1458,7 @@ POSSIBILITY OF SUCH DAMAGE. Enable or disable interrupt 0x300 read-write + 0x00000000 RAMACCERR @@ -1459,12 +1469,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Disable - 0 + 0x0 Enabled Enable - 1 + 0x1 @@ -1477,12 +1487,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Disable - 0 + 0x0 Enabled Enable - 1 + 0x1 @@ -1495,12 +1505,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Disable - 0 + 0x0 Enabled Enable - 1 + 0x1 @@ -1511,6 +1521,7 @@ POSSIBILITY OF SUCH DAMAGE. Enable interrupt 0x304 read-write + 0x00000000 RAMACCERR @@ -1522,12 +1533,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -1535,7 +1546,7 @@ POSSIBILITY OF SUCH DAMAGE. Set Enable - 1 + 0x1 @@ -1549,12 +1560,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -1562,7 +1573,7 @@ POSSIBILITY OF SUCH DAMAGE. Set Enable - 1 + 0x1 @@ -1576,12 +1587,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -1589,7 +1600,7 @@ POSSIBILITY OF SUCH DAMAGE. Set Enable - 1 + 0x1 @@ -1600,6 +1611,7 @@ POSSIBILITY OF SUCH DAMAGE. Disable interrupt 0x308 read-write + 0x00000000 RAMACCERR @@ -1611,12 +1623,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -1624,7 +1636,7 @@ POSSIBILITY OF SUCH DAMAGE. Clear Disable - 1 + 0x1 @@ -1638,12 +1650,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -1651,7 +1663,7 @@ POSSIBILITY OF SUCH DAMAGE. Clear Disable - 1 + 0x1 @@ -1665,12 +1677,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -1678,7 +1690,7 @@ POSSIBILITY OF SUCH DAMAGE. Clear Disable - 1 + 0x1 @@ -1700,12 +1712,12 @@ POSSIBILITY OF SUCH DAMAGE. NotAvailable ARM TrustZone support not available - 0 + 0x0 Enabled ARM TrustZone support is available - 1 + 0x1 @@ -1736,17 +1748,17 @@ POSSIBILITY OF SUCH DAMAGE. NonSecure The bus access from this external domain always have the non-secure attribute set - 0 + 0x0 Secure The bus access from this external domain always have the secure attribute set - 1 + 0x1 UserSelectable Non-secure or secure attribute for bus access from this domain is defined by the EXTDOMAIN[n].PERM register - 2 + 0x2 @@ -1759,12 +1771,12 @@ POSSIBILITY OF SUCH DAMAGE. NonSecure Bus accesses from this domain have the non-secure attribute set - 0 + 0x0 Secure Bus accesses from this domain have secure attribute set - 1 + 0x1 @@ -1776,12 +1788,12 @@ POSSIBILITY OF SUCH DAMAGE. Unlocked This register can be updated - 0 + 0x0 Locked The content of this register can't be changed until the next reset - 1 + 0x1 @@ -1812,12 +1824,12 @@ POSSIBILITY OF SUCH DAMAGE. Secure Channel0 has its secure attribute set - 1 + 0x1 NonSecure Channel0 has its non-secure attribute set - 0 + 0x0 @@ -1830,12 +1842,12 @@ POSSIBILITY OF SUCH DAMAGE. Secure Channel1 has its secure attribute set - 1 + 0x1 NonSecure Channel1 has its non-secure attribute set - 0 + 0x0 @@ -1848,12 +1860,12 @@ POSSIBILITY OF SUCH DAMAGE. Secure Channel2 has its secure attribute set - 1 + 0x1 NonSecure Channel2 has its non-secure attribute set - 0 + 0x0 @@ -1866,12 +1878,12 @@ POSSIBILITY OF SUCH DAMAGE. Secure Channel3 has its secure attribute set - 1 + 0x1 NonSecure Channel3 has its non-secure attribute set - 0 + 0x0 @@ -1884,12 +1896,12 @@ POSSIBILITY OF SUCH DAMAGE. Secure Channel4 has its secure attribute set - 1 + 0x1 NonSecure Channel4 has its non-secure attribute set - 0 + 0x0 @@ -1902,12 +1914,12 @@ POSSIBILITY OF SUCH DAMAGE. Secure Channel5 has its secure attribute set - 1 + 0x1 NonSecure Channel5 has its non-secure attribute set - 0 + 0x0 @@ -1920,12 +1932,12 @@ POSSIBILITY OF SUCH DAMAGE. Secure Channel6 has its secure attribute set - 1 + 0x1 NonSecure Channel6 has its non-secure attribute set - 0 + 0x0 @@ -1938,12 +1950,12 @@ POSSIBILITY OF SUCH DAMAGE. Secure Channel7 has its secure attribute set - 1 + 0x1 NonSecure Channel7 has its non-secure attribute set - 0 + 0x0 @@ -1956,12 +1968,12 @@ POSSIBILITY OF SUCH DAMAGE. Secure Channel8 has its secure attribute set - 1 + 0x1 NonSecure Channel8 has its non-secure attribute set - 0 + 0x0 @@ -1974,12 +1986,12 @@ POSSIBILITY OF SUCH DAMAGE. Secure Channel9 has its secure attribute set - 1 + 0x1 NonSecure Channel9 has its non-secure attribute set - 0 + 0x0 @@ -1992,12 +2004,12 @@ POSSIBILITY OF SUCH DAMAGE. Secure Channel10 has its secure attribute set - 1 + 0x1 NonSecure Channel10 has its non-secure attribute set - 0 + 0x0 @@ -2010,12 +2022,12 @@ POSSIBILITY OF SUCH DAMAGE. Secure Channel11 has its secure attribute set - 1 + 0x1 NonSecure Channel11 has its non-secure attribute set - 0 + 0x0 @@ -2028,12 +2040,12 @@ POSSIBILITY OF SUCH DAMAGE. Secure Channel12 has its secure attribute set - 1 + 0x1 NonSecure Channel12 has its non-secure attribute set - 0 + 0x0 @@ -2046,12 +2058,12 @@ POSSIBILITY OF SUCH DAMAGE. Secure Channel13 has its secure attribute set - 1 + 0x1 NonSecure Channel13 has its non-secure attribute set - 0 + 0x0 @@ -2064,12 +2076,12 @@ POSSIBILITY OF SUCH DAMAGE. Secure Channel14 has its secure attribute set - 1 + 0x1 NonSecure Channel14 has its non-secure attribute set - 0 + 0x0 @@ -2082,12 +2094,12 @@ POSSIBILITY OF SUCH DAMAGE. Secure Channel15 has its secure attribute set - 1 + 0x1 NonSecure Channel15 has its non-secure attribute set - 0 + 0x0 @@ -2108,12 +2120,12 @@ POSSIBILITY OF SUCH DAMAGE. Locked DPPI[n].PERM register can't be changed until next reset - 1 + 0x1 Unlocked DPPI[n].PERM register content can be changed - 0 + 0x0 @@ -2144,12 +2156,12 @@ POSSIBILITY OF SUCH DAMAGE. Secure Pin 0 has its secure attribute set - 1 + 0x1 NonSecure Pin 0 has its non-secure attribute set - 0 + 0x0 @@ -2162,12 +2174,12 @@ POSSIBILITY OF SUCH DAMAGE. Secure Pin 1 has its secure attribute set - 1 + 0x1 NonSecure Pin 1 has its non-secure attribute set - 0 + 0x0 @@ -2180,12 +2192,12 @@ POSSIBILITY OF SUCH DAMAGE. Secure Pin 2 has its secure attribute set - 1 + 0x1 NonSecure Pin 2 has its non-secure attribute set - 0 + 0x0 @@ -2198,12 +2210,12 @@ POSSIBILITY OF SUCH DAMAGE. Secure Pin 3 has its secure attribute set - 1 + 0x1 NonSecure Pin 3 has its non-secure attribute set - 0 + 0x0 @@ -2216,12 +2228,12 @@ POSSIBILITY OF SUCH DAMAGE. Secure Pin 4 has its secure attribute set - 1 + 0x1 NonSecure Pin 4 has its non-secure attribute set - 0 + 0x0 @@ -2234,12 +2246,12 @@ POSSIBILITY OF SUCH DAMAGE. Secure Pin 5 has its secure attribute set - 1 + 0x1 NonSecure Pin 5 has its non-secure attribute set - 0 + 0x0 @@ -2252,12 +2264,12 @@ POSSIBILITY OF SUCH DAMAGE. Secure Pin 6 has its secure attribute set - 1 + 0x1 NonSecure Pin 6 has its non-secure attribute set - 0 + 0x0 @@ -2270,12 +2282,12 @@ POSSIBILITY OF SUCH DAMAGE. Secure Pin 7 has its secure attribute set - 1 + 0x1 NonSecure Pin 7 has its non-secure attribute set - 0 + 0x0 @@ -2288,12 +2300,12 @@ POSSIBILITY OF SUCH DAMAGE. Secure Pin 8 has its secure attribute set - 1 + 0x1 NonSecure Pin 8 has its non-secure attribute set - 0 + 0x0 @@ -2306,12 +2318,12 @@ POSSIBILITY OF SUCH DAMAGE. Secure Pin 9 has its secure attribute set - 1 + 0x1 NonSecure Pin 9 has its non-secure attribute set - 0 + 0x0 @@ -2324,12 +2336,12 @@ POSSIBILITY OF SUCH DAMAGE. Secure Pin 10 has its secure attribute set - 1 + 0x1 NonSecure Pin 10 has its non-secure attribute set - 0 + 0x0 @@ -2342,12 +2354,12 @@ POSSIBILITY OF SUCH DAMAGE. Secure Pin 11 has its secure attribute set - 1 + 0x1 NonSecure Pin 11 has its non-secure attribute set - 0 + 0x0 @@ -2360,12 +2372,12 @@ POSSIBILITY OF SUCH DAMAGE. Secure Pin 12 has its secure attribute set - 1 + 0x1 NonSecure Pin 12 has its non-secure attribute set - 0 + 0x0 @@ -2378,12 +2390,12 @@ POSSIBILITY OF SUCH DAMAGE. Secure Pin 13 has its secure attribute set - 1 + 0x1 NonSecure Pin 13 has its non-secure attribute set - 0 + 0x0 @@ -2396,12 +2408,12 @@ POSSIBILITY OF SUCH DAMAGE. Secure Pin 14 has its secure attribute set - 1 + 0x1 NonSecure Pin 14 has its non-secure attribute set - 0 + 0x0 @@ -2414,12 +2426,12 @@ POSSIBILITY OF SUCH DAMAGE. Secure Pin 15 has its secure attribute set - 1 + 0x1 NonSecure Pin 15 has its non-secure attribute set - 0 + 0x0 @@ -2432,12 +2444,12 @@ POSSIBILITY OF SUCH DAMAGE. Secure Pin 16 has its secure attribute set - 1 + 0x1 NonSecure Pin 16 has its non-secure attribute set - 0 + 0x0 @@ -2450,12 +2462,12 @@ POSSIBILITY OF SUCH DAMAGE. Secure Pin 17 has its secure attribute set - 1 + 0x1 NonSecure Pin 17 has its non-secure attribute set - 0 + 0x0 @@ -2468,12 +2480,12 @@ POSSIBILITY OF SUCH DAMAGE. Secure Pin 18 has its secure attribute set - 1 + 0x1 NonSecure Pin 18 has its non-secure attribute set - 0 + 0x0 @@ -2486,12 +2498,12 @@ POSSIBILITY OF SUCH DAMAGE. Secure Pin 19 has its secure attribute set - 1 + 0x1 NonSecure Pin 19 has its non-secure attribute set - 0 + 0x0 @@ -2504,12 +2516,12 @@ POSSIBILITY OF SUCH DAMAGE. Secure Pin 20 has its secure attribute set - 1 + 0x1 NonSecure Pin 20 has its non-secure attribute set - 0 + 0x0 @@ -2522,12 +2534,12 @@ POSSIBILITY OF SUCH DAMAGE. Secure Pin 21 has its secure attribute set - 1 + 0x1 NonSecure Pin 21 has its non-secure attribute set - 0 + 0x0 @@ -2540,12 +2552,12 @@ POSSIBILITY OF SUCH DAMAGE. Secure Pin 22 has its secure attribute set - 1 + 0x1 NonSecure Pin 22 has its non-secure attribute set - 0 + 0x0 @@ -2558,12 +2570,12 @@ POSSIBILITY OF SUCH DAMAGE. Secure Pin 23 has its secure attribute set - 1 + 0x1 NonSecure Pin 23 has its non-secure attribute set - 0 + 0x0 @@ -2576,12 +2588,12 @@ POSSIBILITY OF SUCH DAMAGE. Secure Pin 24 has its secure attribute set - 1 + 0x1 NonSecure Pin 24 has its non-secure attribute set - 0 + 0x0 @@ -2594,12 +2606,12 @@ POSSIBILITY OF SUCH DAMAGE. Secure Pin 25 has its secure attribute set - 1 + 0x1 NonSecure Pin 25 has its non-secure attribute set - 0 + 0x0 @@ -2612,12 +2624,12 @@ POSSIBILITY OF SUCH DAMAGE. Secure Pin 26 has its secure attribute set - 1 + 0x1 NonSecure Pin 26 has its non-secure attribute set - 0 + 0x0 @@ -2630,12 +2642,12 @@ POSSIBILITY OF SUCH DAMAGE. Secure Pin 27 has its secure attribute set - 1 + 0x1 NonSecure Pin 27 has its non-secure attribute set - 0 + 0x0 @@ -2648,12 +2660,12 @@ POSSIBILITY OF SUCH DAMAGE. Secure Pin 28 has its secure attribute set - 1 + 0x1 NonSecure Pin 28 has its non-secure attribute set - 0 + 0x0 @@ -2666,12 +2678,12 @@ POSSIBILITY OF SUCH DAMAGE. Secure Pin 29 has its secure attribute set - 1 + 0x1 NonSecure Pin 29 has its non-secure attribute set - 0 + 0x0 @@ -2684,12 +2696,12 @@ POSSIBILITY OF SUCH DAMAGE. Secure Pin 30 has its secure attribute set - 1 + 0x1 NonSecure Pin 30 has its non-secure attribute set - 0 + 0x0 @@ -2702,12 +2714,12 @@ POSSIBILITY OF SUCH DAMAGE. Secure Pin 31 has its secure attribute set - 1 + 0x1 NonSecure Pin 31 has its non-secure attribute set - 0 + 0x0 @@ -2728,12 +2740,12 @@ POSSIBILITY OF SUCH DAMAGE. Locked GPIOPORT[n].PERM register can't be changed until next reset - 1 + 0x1 Unlocked GPIOPORT[n].PERM register content can be changed - 0 + 0x0 @@ -2769,12 +2781,12 @@ POSSIBILITY OF SUCH DAMAGE. Unlocked This register can be updated - 0 + 0x0 Locked The content of this register can't be changed until the next reset - 1 + 0x1 @@ -2796,47 +2808,47 @@ POSSIBILITY OF SUCH DAMAGE. Disabled The region n is not defined as a non-secure callable region. Normal security attributes (secure or non-secure) are enforced. - 0 + 0x0 32 The region n is defined as non-secure callable with a 32-byte size - 1 + 0x1 64 The region n is defined as non-secure callable with a 64-byte size - 2 + 0x2 128 The region n is defined as non-secure callable with a 128-byte size - 3 + 0x3 256 The region n is defined as non-secure callable with a 256-byte size - 4 + 0x4 512 The region n is defined as non-secure callable with a 512-byte size - 5 + 0x5 1024 The region n is defined as non-secure callable with a 1024-byte size - 6 + 0x6 2048 The region n is defined as non-secure callable with a 2048-byte size - 7 + 0x7 4096 The region n is defined as non-secure callable with a 4096-byte size - 8 + 0x8 @@ -2848,12 +2860,12 @@ POSSIBILITY OF SUCH DAMAGE. Unlocked This register can be updated - 0 + 0x0 Locked The content of this register can't be changed until the next reset - 1 + 0x1 @@ -2889,12 +2901,12 @@ POSSIBILITY OF SUCH DAMAGE. Unlocked This register can be updated - 0 + 0x0 Locked The content of this register can't be changed until the next reset - 1 + 0x1 @@ -2916,47 +2928,47 @@ POSSIBILITY OF SUCH DAMAGE. Disabled The region n is not defined as a non-secure callable region. Normal security attributes (secure or non-secure) are enforced. - 0 + 0x0 32 The region n is defined as non-secure callable with a 32-byte size - 1 + 0x1 64 The region n is defined as non-secure callable with a 64-byte size - 2 + 0x2 128 The region n is defined as non-secure callable with a 128-byte size - 3 + 0x3 256 The region n is defined as non-secure callable with a 256-byte size - 4 + 0x4 512 The region n is defined as non-secure callable with a 512-byte size - 5 + 0x5 1024 The region n is defined as non-secure callable with a 1024-byte size - 6 + 0x6 2048 The region n is defined as non-secure callable with a 2048-byte size - 7 + 0x7 4096 The region n is defined as non-secure callable with a 4096-byte size - 8 + 0x8 @@ -2968,12 +2980,12 @@ POSSIBILITY OF SUCH DAMAGE. Unlocked This register can be updated - 0 + 0x0 Locked The content of this register can't be changed until the next reset - 1 + 0x1 @@ -3004,12 +3016,12 @@ POSSIBILITY OF SUCH DAMAGE. Enable Allow instruction fetches from flash region n - 1 + 0x1 Disable Block instruction fetches from flash region n - 0 + 0x0 @@ -3022,12 +3034,12 @@ POSSIBILITY OF SUCH DAMAGE. Enable Allow write operation to region n - 1 + 0x1 Disable Block write operation to region n - 0 + 0x0 @@ -3040,12 +3052,12 @@ POSSIBILITY OF SUCH DAMAGE. Enable Allow read operation from flash region n - 1 + 0x1 Disable Block read operation from flash region n - 0 + 0x0 @@ -3058,12 +3070,12 @@ POSSIBILITY OF SUCH DAMAGE. Non_Secure Flash region n security attribute is non-secure - 0 + 0x0 Secure Flash region n security attribute is secure - 1 + 0x1 @@ -3075,12 +3087,12 @@ POSSIBILITY OF SUCH DAMAGE. Unlocked This register can be updated - 0 + 0x0 Locked The content of this register can't be changed until the next reset - 1 + 0x1 @@ -3111,12 +3123,12 @@ POSSIBILITY OF SUCH DAMAGE. Enable Allow instruction fetches from RAM region n - 1 + 0x1 Disable Block instruction fetches from RAM region n - 0 + 0x0 @@ -3129,12 +3141,12 @@ POSSIBILITY OF SUCH DAMAGE. Enable Allow write operation to RAM region n - 1 + 0x1 Disable Block write operation to RAM region n - 0 + 0x0 @@ -3147,12 +3159,12 @@ POSSIBILITY OF SUCH DAMAGE. Enable Allow read operation from RAM region n - 1 + 0x1 Disable Block read operation from RAM region n - 0 + 0x0 @@ -3165,12 +3177,12 @@ POSSIBILITY OF SUCH DAMAGE. Non_Secure RAM region n security attribute is non-secure - 0 + 0x0 Secure RAM region n security attribute is secure - 1 + 0x1 @@ -3182,12 +3194,12 @@ POSSIBILITY OF SUCH DAMAGE. Unlocked This register can be updated - 0 + 0x0 Locked The content of this register can't be changed until the next reset - 1 + 0x1 @@ -3219,22 +3231,22 @@ POSSIBILITY OF SUCH DAMAGE. NonSecure This peripheral is always accessible as a non-secure peripheral - 0 + 0x0 Secure This peripheral is always accessible as a secure peripheral - 1 + 0x1 UserSelectable Non-secure or secure attribute for this peripheral is defined by the PERIPHID[n].PERM register - 2 + 0x2 Split This peripheral implements the split security mechanism. Non-secure or secure attribute for this peripheral is defined by the PERIPHID[n].PERM register. - 3 + 0x3 @@ -3248,17 +3260,17 @@ POSSIBILITY OF SUCH DAMAGE. NoDMA Peripheral has no DMA capability - 0 + 0x0 NoSeparateAttribute Peripheral has DMA and DMA transfers always have the same security attribute as assigned to the peripheral - 1 + 0x1 SeparateAttribute Peripheral has DMA and DMA transfers can have a different security attribute than the one assigned to the peripheral - 2 + 0x2 @@ -3271,12 +3283,12 @@ POSSIBILITY OF SUCH DAMAGE. Secure Peripheral is mapped in secure peripheral address space - 1 + 0x1 NonSecure If SECUREMAPPING == UserSelectable: Peripheral is mapped in non-secure peripheral address space. If SECUREMAPPING == Split: Peripheral is mapped in non-secure and secure peripheral address space. - 0 + 0x0 @@ -3289,12 +3301,12 @@ POSSIBILITY OF SUCH DAMAGE. Secure DMA transfers initiated by this peripheral have the secure attribute set - 1 + 0x1 NonSecure DMA transfers initiated by this peripheral have the non-secure attribute set - 0 + 0x0 @@ -3306,12 +3318,12 @@ POSSIBILITY OF SUCH DAMAGE. Unlocked This register can be updated - 0 + 0x0 Locked The content of this register can't be changed until the next reset - 1 + 0x1 @@ -3325,12 +3337,12 @@ POSSIBILITY OF SUCH DAMAGE. NotPresent Peripheral is not present - 0 + 0x0 IsPresent Peripheral is present - 1 + 0x1 @@ -3359,6 +3371,7 @@ POSSIBILITY OF SUCH DAMAGE. System OFF register 0x500 write-only + 0x00000000 SYSTEMOFF @@ -3369,7 +3382,7 @@ POSSIBILITY OF SUCH DAMAGE. Enable Enable System OFF mode - 1 + 0x1 @@ -3380,6 +3393,7 @@ POSSIBILITY OF SUCH DAMAGE. External power failure warning configuration 0x514 read-write + 0x00000000 POF @@ -3390,12 +3404,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Disable - 0 + 0x0 Enabled Enable - 1 + 0x1 @@ -3406,6 +3420,7 @@ POSSIBILITY OF SUCH DAMAGE. Enable DC/DC mode of the main voltage regulator. 0x578 read-write + 0x00000000 DCDCEN @@ -3416,12 +3431,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled DC/DC mode is disabled - 0 + 0x0 Enabled DC/DC mode is enabled - 1 + 0x1 @@ -3460,6 +3475,7 @@ POSSIBILITY OF SUCH DAMAGE. Start HFCLK source 0x000 write-only + 0x00000000 TASKS_HFCLKSTART @@ -3470,7 +3486,7 @@ POSSIBILITY OF SUCH DAMAGE. Trigger Trigger task - 1 + 0x1 @@ -3481,6 +3497,7 @@ POSSIBILITY OF SUCH DAMAGE. Stop HFCLK source 0x004 write-only + 0x00000000 TASKS_HFCLKSTOP @@ -3491,7 +3508,7 @@ POSSIBILITY OF SUCH DAMAGE. Trigger Trigger task - 1 + 0x1 @@ -3502,6 +3519,7 @@ POSSIBILITY OF SUCH DAMAGE. Start LFCLK source 0x008 write-only + 0x00000000 TASKS_LFCLKSTART @@ -3512,7 +3530,7 @@ POSSIBILITY OF SUCH DAMAGE. Trigger Trigger task - 1 + 0x1 @@ -3523,6 +3541,7 @@ POSSIBILITY OF SUCH DAMAGE. Stop LFCLK source 0x00C write-only + 0x00000000 TASKS_LFCLKSTOP @@ -3533,7 +3552,7 @@ POSSIBILITY OF SUCH DAMAGE. Trigger Trigger task - 1 + 0x1 @@ -3544,6 +3563,7 @@ POSSIBILITY OF SUCH DAMAGE. Subscribe configuration for task HFCLKSTART 0x080 read-write + 0x00000000 CHIDX @@ -3559,12 +3579,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Disable subscription - 0 + 0x0 Enabled Enable subscription - 1 + 0x1 @@ -3575,6 +3595,7 @@ POSSIBILITY OF SUCH DAMAGE. Subscribe configuration for task HFCLKSTOP 0x084 read-write + 0x00000000 CHIDX @@ -3590,12 +3611,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Disable subscription - 0 + 0x0 Enabled Enable subscription - 1 + 0x1 @@ -3606,6 +3627,7 @@ POSSIBILITY OF SUCH DAMAGE. Subscribe configuration for task LFCLKSTART 0x088 read-write + 0x00000000 CHIDX @@ -3621,12 +3643,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Disable subscription - 0 + 0x0 Enabled Enable subscription - 1 + 0x1 @@ -3637,6 +3659,7 @@ POSSIBILITY OF SUCH DAMAGE. Subscribe configuration for task LFCLKSTOP 0x08C read-write + 0x00000000 CHIDX @@ -3652,12 +3675,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Disable subscription - 0 + 0x0 Enabled Enable subscription - 1 + 0x1 @@ -3668,6 +3691,7 @@ POSSIBILITY OF SUCH DAMAGE. HFCLK oscillator started 0x100 read-write + 0x00000000 EVENTS_HFCLKSTARTED @@ -3678,12 +3702,12 @@ POSSIBILITY OF SUCH DAMAGE. NotGenerated Event not generated - 0 + 0x0 Generated Event generated - 1 + 0x1 @@ -3694,6 +3718,7 @@ POSSIBILITY OF SUCH DAMAGE. LFCLK started 0x104 read-write + 0x00000000 EVENTS_LFCLKSTARTED @@ -3704,12 +3729,12 @@ POSSIBILITY OF SUCH DAMAGE. NotGenerated Event not generated - 0 + 0x0 Generated Event generated - 1 + 0x1 @@ -3720,6 +3745,7 @@ POSSIBILITY OF SUCH DAMAGE. Publish configuration for event HFCLKSTARTED 0x180 read-write + 0x00000000 CHIDX @@ -3735,12 +3761,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Disable publishing - 0 + 0x0 Enabled Enable publishing - 1 + 0x1 @@ -3751,6 +3777,7 @@ POSSIBILITY OF SUCH DAMAGE. Publish configuration for event LFCLKSTARTED 0x184 read-write + 0x00000000 CHIDX @@ -3766,12 +3793,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Disable publishing - 0 + 0x0 Enabled Enable publishing - 1 + 0x1 @@ -3782,6 +3809,7 @@ POSSIBILITY OF SUCH DAMAGE. Enable or disable interrupt 0x300 read-write + 0x00000000 HFCLKSTARTED @@ -3792,12 +3820,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Disable - 0 + 0x0 Enabled Enable - 1 + 0x1 @@ -3810,12 +3838,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Disable - 0 + 0x0 Enabled Enable - 1 + 0x1 @@ -3826,6 +3854,7 @@ POSSIBILITY OF SUCH DAMAGE. Enable interrupt 0x304 read-write + 0x00000000 HFCLKSTARTED @@ -3837,12 +3866,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -3850,7 +3879,7 @@ POSSIBILITY OF SUCH DAMAGE. Set Enable - 1 + 0x1 @@ -3864,12 +3893,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -3877,7 +3906,7 @@ POSSIBILITY OF SUCH DAMAGE. Set Enable - 1 + 0x1 @@ -3888,6 +3917,7 @@ POSSIBILITY OF SUCH DAMAGE. Disable interrupt 0x308 read-write + 0x00000000 HFCLKSTARTED @@ -3899,12 +3929,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -3912,7 +3942,7 @@ POSSIBILITY OF SUCH DAMAGE. Clear Disable - 1 + 0x1 @@ -3926,12 +3956,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -3939,7 +3969,7 @@ POSSIBILITY OF SUCH DAMAGE. Clear Disable - 1 + 0x1 @@ -3950,6 +3980,7 @@ POSSIBILITY OF SUCH DAMAGE. Pending interrupts 0x30C read-only + 0x00000000 HFCLKSTARTED @@ -3961,12 +3992,12 @@ POSSIBILITY OF SUCH DAMAGE. NotPending Read: Not pending - 0 + 0x0 Pending Read: Pending - 1 + 0x1 @@ -3980,12 +4011,12 @@ POSSIBILITY OF SUCH DAMAGE. NotPending Read: Not pending - 0 + 0x0 Pending Read: Pending - 1 + 0x1 @@ -3996,6 +4027,7 @@ POSSIBILITY OF SUCH DAMAGE. Status indicating that HFCLKSTART task has been triggered 0x408 read-only + 0x00000000 STATUS @@ -4006,12 +4038,12 @@ POSSIBILITY OF SUCH DAMAGE. NotTriggered Task not triggered - 0 + 0x0 Triggered Task triggered - 1 + 0x1 @@ -4022,6 +4054,7 @@ POSSIBILITY OF SUCH DAMAGE. The register shows if HFXO has been requested by triggering HFCLKSTART task and if it has been started (STATE) 0x40C read-only + 0x00000000 SRC @@ -4032,12 +4065,12 @@ POSSIBILITY OF SUCH DAMAGE. HFINT HFINT - 64 MHz on-chip oscillator - 0 + 0x0 HFXO HFXO - 64 MHz clock derived from external 32 MHz crystal oscillator - 1 + 0x1 @@ -4050,12 +4083,12 @@ POSSIBILITY OF SUCH DAMAGE. NotRunning HFXO has not been started or HFCLKSTOP task has been triggered - 0 + 0x0 Running HFXO has been started (HFCLKSTARTED event has been generated) - 1 + 0x1 @@ -4066,6 +4099,7 @@ POSSIBILITY OF SUCH DAMAGE. Status indicating that LFCLKSTART task has been triggered 0x414 read-only + 0x00000000 STATUS @@ -4076,12 +4110,12 @@ POSSIBILITY OF SUCH DAMAGE. NotTriggered Task not triggered - 0 + 0x0 Triggered Task triggered - 1 + 0x1 @@ -4092,6 +4126,7 @@ POSSIBILITY OF SUCH DAMAGE. The register shows which LFCLK source has been requested (SRC) when triggering LFCLKSTART task and if the source has been started (STATE) 0x418 read-only + 0x00000000 SRC @@ -4102,17 +4137,17 @@ POSSIBILITY OF SUCH DAMAGE. RFU Reserved for future use - 0 + 0x0 LFRC 32.768 kHz RC oscillator - 1 + 0x1 LFXO 32.768 kHz crystal oscillator - 2 + 0x2 @@ -4125,12 +4160,12 @@ POSSIBILITY OF SUCH DAMAGE. NotRunning Requested LFCLK source has not been started or LFCLKSTOP task has been triggered - 0 + 0x0 Running Requested LFCLK source has been started (LFCLKSTARTED event has been generated) - 1 + 0x1 @@ -4152,17 +4187,17 @@ POSSIBILITY OF SUCH DAMAGE. RFU Reserved for future use - 0 + 0x0 LFRC 32.768 kHz RC oscillator - 1 + 0x1 LFXO 32.768 kHz crystal oscillator - 2 + 0x2 @@ -4184,17 +4219,17 @@ POSSIBILITY OF SUCH DAMAGE. RFU Reserved for future use (equals selecting LFRC) - 0 + 0x0 LFRC 32.768 kHz RC oscillator - 1 + 0x1 LFXO 32.768 kHz crystal oscillator - 2 + 0x2 @@ -4227,6 +4262,7 @@ POSSIBILITY OF SUCH DAMAGE. Request forcing PWM mode in external DC/DC voltage regulator. (Drives FPWM_DCDC pin high or low depending on a setting in UICR). 0x70 write-only + 0x00000000 TASKS_PWMREQSTART @@ -4237,7 +4273,7 @@ POSSIBILITY OF SUCH DAMAGE. Trigger Trigger task - 1 + 0x1 @@ -4248,6 +4284,7 @@ POSSIBILITY OF SUCH DAMAGE. Stop requesting forcing PWM mode in external DC/DC voltage regulator 0x74 write-only + 0x00000000 TASKS_PWMREQSTOP @@ -4258,7 +4295,7 @@ POSSIBILITY OF SUCH DAMAGE. Trigger Trigger task - 1 + 0x1 @@ -4269,6 +4306,7 @@ POSSIBILITY OF SUCH DAMAGE. Enable constant latency mode. 0x78 write-only + 0x00000000 TASKS_CONSTLAT @@ -4279,7 +4317,7 @@ POSSIBILITY OF SUCH DAMAGE. Trigger Trigger task - 1 + 0x1 @@ -4290,6 +4328,7 @@ POSSIBILITY OF SUCH DAMAGE. Enable low power mode (variable latency) 0x7C write-only + 0x00000000 TASKS_LOWPWR @@ -4300,7 +4339,7 @@ POSSIBILITY OF SUCH DAMAGE. Trigger Trigger task - 1 + 0x1 @@ -4311,6 +4350,7 @@ POSSIBILITY OF SUCH DAMAGE. Subscribe configuration for task PWMREQSTART 0xF0 read-write + 0x00000000 CHIDX @@ -4326,12 +4366,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Disable subscription - 0 + 0x0 Enabled Enable subscription - 1 + 0x1 @@ -4342,6 +4382,7 @@ POSSIBILITY OF SUCH DAMAGE. Subscribe configuration for task PWMREQSTOP 0xF4 read-write + 0x00000000 CHIDX @@ -4357,12 +4398,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Disable subscription - 0 + 0x0 Enabled Enable subscription - 1 + 0x1 @@ -4373,6 +4414,7 @@ POSSIBILITY OF SUCH DAMAGE. Subscribe configuration for task CONSTLAT 0xF8 read-write + 0x00000000 CHIDX @@ -4388,12 +4430,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Disable subscription - 0 + 0x0 Enabled Enable subscription - 1 + 0x1 @@ -4404,6 +4446,7 @@ POSSIBILITY OF SUCH DAMAGE. Subscribe configuration for task LOWPWR 0xFC read-write + 0x00000000 CHIDX @@ -4419,12 +4462,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Disable subscription - 0 + 0x0 Enabled Enable subscription - 1 + 0x1 @@ -4435,6 +4478,7 @@ POSSIBILITY OF SUCH DAMAGE. Power failure warning 0x108 read-write + 0x00000000 EVENTS_POFWARN @@ -4445,12 +4489,12 @@ POSSIBILITY OF SUCH DAMAGE. NotGenerated Event not generated - 0 + 0x0 Generated Event generated - 1 + 0x1 @@ -4461,6 +4505,7 @@ POSSIBILITY OF SUCH DAMAGE. CPU entered WFI/WFE sleep 0x114 read-write + 0x00000000 EVENTS_SLEEPENTER @@ -4471,12 +4516,12 @@ POSSIBILITY OF SUCH DAMAGE. NotGenerated Event not generated - 0 + 0x0 Generated Event generated - 1 + 0x1 @@ -4487,6 +4532,7 @@ POSSIBILITY OF SUCH DAMAGE. CPU exited WFI/WFE sleep 0x118 read-write + 0x00000000 EVENTS_SLEEPEXIT @@ -4497,12 +4543,12 @@ POSSIBILITY OF SUCH DAMAGE. NotGenerated Event not generated - 0 + 0x0 Generated Event generated - 1 + 0x1 @@ -4513,6 +4559,7 @@ POSSIBILITY OF SUCH DAMAGE. Publish configuration for event POFWARN 0x188 read-write + 0x00000000 CHIDX @@ -4528,12 +4575,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Disable publishing - 0 + 0x0 Enabled Enable publishing - 1 + 0x1 @@ -4544,6 +4591,7 @@ POSSIBILITY OF SUCH DAMAGE. Publish configuration for event SLEEPENTER 0x194 read-write + 0x00000000 CHIDX @@ -4559,12 +4607,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Disable publishing - 0 + 0x0 Enabled Enable publishing - 1 + 0x1 @@ -4575,6 +4623,7 @@ POSSIBILITY OF SUCH DAMAGE. Publish configuration for event SLEEPEXIT 0x198 read-write + 0x00000000 CHIDX @@ -4590,12 +4639,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Disable publishing - 0 + 0x0 Enabled Enable publishing - 1 + 0x1 @@ -4606,6 +4655,7 @@ POSSIBILITY OF SUCH DAMAGE. Enable or disable interrupt 0x300 read-write + 0x00000000 POFWARN @@ -4616,12 +4666,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Disable - 0 + 0x0 Enabled Enable - 1 + 0x1 @@ -4634,12 +4684,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Disable - 0 + 0x0 Enabled Enable - 1 + 0x1 @@ -4652,12 +4702,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Disable - 0 + 0x0 Enabled Enable - 1 + 0x1 @@ -4668,6 +4718,7 @@ POSSIBILITY OF SUCH DAMAGE. Enable interrupt 0x304 read-write + 0x00000000 POFWARN @@ -4679,12 +4730,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -4692,7 +4743,7 @@ POSSIBILITY OF SUCH DAMAGE. Set Enable - 1 + 0x1 @@ -4706,12 +4757,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -4719,7 +4770,7 @@ POSSIBILITY OF SUCH DAMAGE. Set Enable - 1 + 0x1 @@ -4733,12 +4784,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -4746,7 +4797,7 @@ POSSIBILITY OF SUCH DAMAGE. Set Enable - 1 + 0x1 @@ -4757,6 +4808,7 @@ POSSIBILITY OF SUCH DAMAGE. Disable interrupt 0x308 read-write + 0x00000000 POFWARN @@ -4768,12 +4820,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -4781,7 +4833,7 @@ POSSIBILITY OF SUCH DAMAGE. Clear Disable - 1 + 0x1 @@ -4795,12 +4847,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -4808,7 +4860,7 @@ POSSIBILITY OF SUCH DAMAGE. Clear Disable - 1 + 0x1 @@ -4822,12 +4874,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -4835,7 +4887,7 @@ POSSIBILITY OF SUCH DAMAGE. Clear Disable - 1 + 0x1 @@ -4846,6 +4898,7 @@ POSSIBILITY OF SUCH DAMAGE. Reset reason 0x400 read-write + 0x00000000 RESETPIN @@ -4856,12 +4909,12 @@ POSSIBILITY OF SUCH DAMAGE. NotDetected Not detected - 0 + 0x0 Detected Detected - 1 + 0x1 @@ -4874,12 +4927,12 @@ POSSIBILITY OF SUCH DAMAGE. NotDetected Not detected - 0 + 0x0 Detected Detected - 1 + 0x1 @@ -4892,12 +4945,12 @@ POSSIBILITY OF SUCH DAMAGE. NotDetected Not detected - 0 + 0x0 Detected Detected - 1 + 0x1 @@ -4910,12 +4963,12 @@ POSSIBILITY OF SUCH DAMAGE. NotDetected Not detected - 0 + 0x0 Detected Detected - 1 + 0x1 @@ -4928,12 +4981,12 @@ POSSIBILITY OF SUCH DAMAGE. NotDetected Not detected - 0 + 0x0 Detected Detected - 1 + 0x1 @@ -4946,12 +4999,12 @@ POSSIBILITY OF SUCH DAMAGE. NotDetected Not detected - 0 + 0x0 Detected Detected - 1 + 0x1 @@ -4964,12 +5017,12 @@ POSSIBILITY OF SUCH DAMAGE. NotDetected Not detected - 0 + 0x0 Detected Detected - 1 + 0x1 @@ -4980,6 +5033,7 @@ POSSIBILITY OF SUCH DAMAGE. Modem domain power status 0x440 read-only + 0x00000000 LTEMODEM @@ -4990,12 +5044,12 @@ POSSIBILITY OF SUCH DAMAGE. OFF LTE modem domain is powered off - 0 + 0x0 ON LTE modem domain is powered on - 1 + 0x1 @@ -5008,6 +5062,7 @@ POSSIBILITY OF SUCH DAMAGE. Description collection: General purpose retention register 0x51C read-write + 0x00000000 GPREGRET @@ -5039,12 +5094,12 @@ POSSIBILITY OF SUCH DAMAGE. Start Start LTE modem - 0 + 0x0 Hold Hold LTE modem disabled - 1 + 0x1 @@ -5066,12 +5121,12 @@ POSSIBILITY OF SUCH DAMAGE. Release Release force off - 0 + 0x0 Hold Hold force off active - 1 + 0x1 @@ -5155,12 +5210,12 @@ POSSIBILITY OF SUCH DAMAGE. NoDataPending No data pending in register RXDATA - 0 + 0x0 DataPending Data pending in register RXDATA - 1 + 0x1 @@ -5197,12 +5252,12 @@ POSSIBILITY OF SUCH DAMAGE. NoDataPending No data pending in register TXDATA - 0 + 0x0 DataPending Data pending in register TXDATA - 1 + 0x1 @@ -5231,12 +5286,12 @@ POSSIBILITY OF SUCH DAMAGE. Unlocked Register ERASEPROTECT.DISABLE is writeable - 0 + 0x0 Locked Register ERASEPROTECT.DISABLE is read-only - 1 + 0x1 @@ -5246,7 +5301,7 @@ POSSIBILITY OF SUCH DAMAGE. DISABLE This register disables the ERASEPROTECT register and performs an ERASEALL operation. 0x004 - read-write + read-writeonce 0x00000000 @@ -5284,6 +5339,7 @@ POSSIBILITY OF SUCH DAMAGE. Start SPI transaction 0x010 write-only + 0x00000000 TASKS_START @@ -5294,7 +5350,7 @@ POSSIBILITY OF SUCH DAMAGE. Trigger Trigger task - 1 + 0x1 @@ -5305,6 +5361,7 @@ POSSIBILITY OF SUCH DAMAGE. Stop SPI transaction 0x014 write-only + 0x00000000 TASKS_STOP @@ -5315,7 +5372,7 @@ POSSIBILITY OF SUCH DAMAGE. Trigger Trigger task - 1 + 0x1 @@ -5326,6 +5383,7 @@ POSSIBILITY OF SUCH DAMAGE. Suspend SPI transaction 0x01C write-only + 0x00000000 TASKS_SUSPEND @@ -5336,7 +5394,7 @@ POSSIBILITY OF SUCH DAMAGE. Trigger Trigger task - 1 + 0x1 @@ -5347,6 +5405,7 @@ POSSIBILITY OF SUCH DAMAGE. Resume SPI transaction 0x020 write-only + 0x00000000 TASKS_RESUME @@ -5357,7 +5416,7 @@ POSSIBILITY OF SUCH DAMAGE. Trigger Trigger task - 1 + 0x1 @@ -5368,6 +5427,7 @@ POSSIBILITY OF SUCH DAMAGE. Subscribe configuration for task START 0x090 read-write + 0x00000000 CHIDX @@ -5383,12 +5443,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Disable subscription - 0 + 0x0 Enabled Enable subscription - 1 + 0x1 @@ -5399,6 +5459,7 @@ POSSIBILITY OF SUCH DAMAGE. Subscribe configuration for task STOP 0x094 read-write + 0x00000000 CHIDX @@ -5414,12 +5475,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Disable subscription - 0 + 0x0 Enabled Enable subscription - 1 + 0x1 @@ -5430,6 +5491,7 @@ POSSIBILITY OF SUCH DAMAGE. Subscribe configuration for task SUSPEND 0x09C read-write + 0x00000000 CHIDX @@ -5445,12 +5507,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Disable subscription - 0 + 0x0 Enabled Enable subscription - 1 + 0x1 @@ -5461,6 +5523,7 @@ POSSIBILITY OF SUCH DAMAGE. Subscribe configuration for task RESUME 0x0A0 read-write + 0x00000000 CHIDX @@ -5476,12 +5539,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Disable subscription - 0 + 0x0 Enabled Enable subscription - 1 + 0x1 @@ -5492,6 +5555,7 @@ POSSIBILITY OF SUCH DAMAGE. SPI transaction has stopped 0x104 read-write + 0x00000000 EVENTS_STOPPED @@ -5502,12 +5566,12 @@ POSSIBILITY OF SUCH DAMAGE. NotGenerated Event not generated - 0 + 0x0 Generated Event generated - 1 + 0x1 @@ -5518,6 +5582,7 @@ POSSIBILITY OF SUCH DAMAGE. End of RXD buffer reached 0x110 read-write + 0x00000000 EVENTS_ENDRX @@ -5528,12 +5593,12 @@ POSSIBILITY OF SUCH DAMAGE. NotGenerated Event not generated - 0 + 0x0 Generated Event generated - 1 + 0x1 @@ -5544,6 +5609,7 @@ POSSIBILITY OF SUCH DAMAGE. End of RXD buffer and TXD buffer reached 0x118 read-write + 0x00000000 EVENTS_END @@ -5554,12 +5620,12 @@ POSSIBILITY OF SUCH DAMAGE. NotGenerated Event not generated - 0 + 0x0 Generated Event generated - 1 + 0x1 @@ -5570,6 +5636,7 @@ POSSIBILITY OF SUCH DAMAGE. End of TXD buffer reached 0x120 read-write + 0x00000000 EVENTS_ENDTX @@ -5580,12 +5647,12 @@ POSSIBILITY OF SUCH DAMAGE. NotGenerated Event not generated - 0 + 0x0 Generated Event generated - 1 + 0x1 @@ -5596,6 +5663,7 @@ POSSIBILITY OF SUCH DAMAGE. Transaction started 0x14C read-write + 0x00000000 EVENTS_STARTED @@ -5606,12 +5674,12 @@ POSSIBILITY OF SUCH DAMAGE. NotGenerated Event not generated - 0 + 0x0 Generated Event generated - 1 + 0x1 @@ -5622,6 +5690,7 @@ POSSIBILITY OF SUCH DAMAGE. Publish configuration for event STOPPED 0x184 read-write + 0x00000000 CHIDX @@ -5637,12 +5706,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Disable publishing - 0 + 0x0 Enabled Enable publishing - 1 + 0x1 @@ -5653,6 +5722,7 @@ POSSIBILITY OF SUCH DAMAGE. Publish configuration for event ENDRX 0x190 read-write + 0x00000000 CHIDX @@ -5668,12 +5738,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Disable publishing - 0 + 0x0 Enabled Enable publishing - 1 + 0x1 @@ -5684,6 +5754,7 @@ POSSIBILITY OF SUCH DAMAGE. Publish configuration for event END 0x198 read-write + 0x00000000 CHIDX @@ -5699,12 +5770,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Disable publishing - 0 + 0x0 Enabled Enable publishing - 1 + 0x1 @@ -5715,6 +5786,7 @@ POSSIBILITY OF SUCH DAMAGE. Publish configuration for event ENDTX 0x1A0 read-write + 0x00000000 CHIDX @@ -5730,12 +5802,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Disable publishing - 0 + 0x0 Enabled Enable publishing - 1 + 0x1 @@ -5746,6 +5818,7 @@ POSSIBILITY OF SUCH DAMAGE. Publish configuration for event STARTED 0x1CC read-write + 0x00000000 CHIDX @@ -5761,12 +5834,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Disable publishing - 0 + 0x0 Enabled Enable publishing - 1 + 0x1 @@ -5777,6 +5850,7 @@ POSSIBILITY OF SUCH DAMAGE. Shortcuts between local events and tasks 0x200 read-write + 0x00000000 END_START @@ -5787,12 +5861,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Disable shortcut - 0 + 0x0 Enabled Enable shortcut - 1 + 0x1 @@ -5803,6 +5877,7 @@ POSSIBILITY OF SUCH DAMAGE. Enable interrupt 0x304 read-write + 0x00000000 STOPPED @@ -5814,12 +5889,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -5827,7 +5902,7 @@ POSSIBILITY OF SUCH DAMAGE. Set Enable - 1 + 0x1 @@ -5841,12 +5916,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -5854,7 +5929,7 @@ POSSIBILITY OF SUCH DAMAGE. Set Enable - 1 + 0x1 @@ -5868,12 +5943,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -5881,7 +5956,7 @@ POSSIBILITY OF SUCH DAMAGE. Set Enable - 1 + 0x1 @@ -5895,12 +5970,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -5908,7 +5983,7 @@ POSSIBILITY OF SUCH DAMAGE. Set Enable - 1 + 0x1 @@ -5922,12 +5997,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -5935,7 +6010,7 @@ POSSIBILITY OF SUCH DAMAGE. Set Enable - 1 + 0x1 @@ -5946,6 +6021,7 @@ POSSIBILITY OF SUCH DAMAGE. Disable interrupt 0x308 read-write + 0x00000000 STOPPED @@ -5957,12 +6033,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -5970,7 +6046,7 @@ POSSIBILITY OF SUCH DAMAGE. Clear Disable - 1 + 0x1 @@ -5984,12 +6060,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -5997,7 +6073,7 @@ POSSIBILITY OF SUCH DAMAGE. Clear Disable - 1 + 0x1 @@ -6011,12 +6087,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -6024,7 +6100,7 @@ POSSIBILITY OF SUCH DAMAGE. Clear Disable - 1 + 0x1 @@ -6038,12 +6114,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -6051,7 +6127,7 @@ POSSIBILITY OF SUCH DAMAGE. Clear Disable - 1 + 0x1 @@ -6065,12 +6141,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -6078,7 +6154,7 @@ POSSIBILITY OF SUCH DAMAGE. Clear Disable - 1 + 0x1 @@ -6089,6 +6165,7 @@ POSSIBILITY OF SUCH DAMAGE. Enable SPIM 0x500 read-write + 0x00000000 ENABLE @@ -6099,12 +6176,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Disable SPIM - 0 + 0x0 Enabled Enable SPIM - 7 + 0x7 @@ -6138,12 +6215,12 @@ POSSIBILITY OF SUCH DAMAGE. Disconnected Disconnect - 1 + 0x1 Connected Connect - 0 + 0x0 @@ -6171,12 +6248,12 @@ POSSIBILITY OF SUCH DAMAGE. Disconnected Disconnect - 1 + 0x1 Connected Connect - 0 + 0x0 @@ -6204,12 +6281,12 @@ POSSIBILITY OF SUCH DAMAGE. Disconnected Disconnect - 1 + 0x1 Connected Connect - 0 + 0x0 @@ -6279,6 +6356,7 @@ POSSIBILITY OF SUCH DAMAGE. Data pointer 0x000 read-write + 0x00000000 PTR @@ -6293,6 +6371,7 @@ POSSIBILITY OF SUCH DAMAGE. Maximum number of bytes in receive buffer 0x004 read-write + 0x00000000 MAXCNT @@ -6307,6 +6386,7 @@ POSSIBILITY OF SUCH DAMAGE. Number of bytes transferred in the last transaction 0x008 read-only + 0x00000000 AMOUNT @@ -6321,6 +6401,7 @@ POSSIBILITY OF SUCH DAMAGE. EasyDMA list type 0x00C read-write + 0x00000000 LIST @@ -6331,12 +6412,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Disable EasyDMA list - 0 + 0x0 ArrayList Use array list - 1 + 0x1 @@ -6354,6 +6435,7 @@ POSSIBILITY OF SUCH DAMAGE. Data pointer 0x000 read-write + 0x00000000 PTR @@ -6368,6 +6450,7 @@ POSSIBILITY OF SUCH DAMAGE. Maximum number of bytes in transmit buffer 0x004 read-write + 0x00000000 MAXCNT @@ -6382,6 +6465,7 @@ POSSIBILITY OF SUCH DAMAGE. Number of bytes transferred in the last transaction 0x008 read-only + 0x00000000 AMOUNT @@ -6396,6 +6480,7 @@ POSSIBILITY OF SUCH DAMAGE. EasyDMA list type 0x00C read-write + 0x00000000 LIST @@ -6406,12 +6491,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Disable EasyDMA list - 0 + 0x0 ArrayList Use array list - 1 + 0x1 @@ -6423,6 +6508,7 @@ POSSIBILITY OF SUCH DAMAGE. Configuration register 0x554 read-write + 0x00000000 ORDER @@ -6433,12 +6519,12 @@ POSSIBILITY OF SUCH DAMAGE. MsbFirst Most significant bit shifted out first - 0 + 0x0 LsbFirst Least significant bit shifted out first - 1 + 0x1 @@ -6451,12 +6537,12 @@ POSSIBILITY OF SUCH DAMAGE. Leading Sample on leading edge of clock, shift serial data on trailing edge - 0 + 0x0 Trailing Sample on trailing edge of clock, shift serial data on leading edge - 1 + 0x1 @@ -6469,12 +6555,12 @@ POSSIBILITY OF SUCH DAMAGE. ActiveHigh Active high - 0 + 0x0 ActiveLow Active low - 1 + 0x1 @@ -6485,6 +6571,7 @@ POSSIBILITY OF SUCH DAMAGE. Over-read character. Character clocked out in case an over-read of the TXD buffer. 0x5C0 read-write + 0x00000000 ORC @@ -6521,6 +6608,7 @@ POSSIBILITY OF SUCH DAMAGE. Acquire SPI semaphore 0x024 write-only + 0x00000000 TASKS_ACQUIRE @@ -6531,7 +6619,7 @@ POSSIBILITY OF SUCH DAMAGE. Trigger Trigger task - 1 + 0x1 @@ -6542,6 +6630,7 @@ POSSIBILITY OF SUCH DAMAGE. Release SPI semaphore, enabling the SPI slave to acquire it 0x028 write-only + 0x00000000 TASKS_RELEASE @@ -6552,7 +6641,7 @@ POSSIBILITY OF SUCH DAMAGE. Trigger Trigger task - 1 + 0x1 @@ -6563,6 +6652,7 @@ POSSIBILITY OF SUCH DAMAGE. Subscribe configuration for task ACQUIRE 0x0A4 read-write + 0x00000000 CHIDX @@ -6578,12 +6668,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Disable subscription - 0 + 0x0 Enabled Enable subscription - 1 + 0x1 @@ -6594,6 +6684,7 @@ POSSIBILITY OF SUCH DAMAGE. Subscribe configuration for task RELEASE 0x0A8 read-write + 0x00000000 CHIDX @@ -6609,12 +6700,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Disable subscription - 0 + 0x0 Enabled Enable subscription - 1 + 0x1 @@ -6625,6 +6716,7 @@ POSSIBILITY OF SUCH DAMAGE. Granted transaction completed 0x104 read-write + 0x00000000 EVENTS_END @@ -6635,12 +6727,12 @@ POSSIBILITY OF SUCH DAMAGE. NotGenerated Event not generated - 0 + 0x0 Generated Event generated - 1 + 0x1 @@ -6651,6 +6743,7 @@ POSSIBILITY OF SUCH DAMAGE. End of RXD buffer reached 0x110 read-write + 0x00000000 EVENTS_ENDRX @@ -6661,12 +6754,12 @@ POSSIBILITY OF SUCH DAMAGE. NotGenerated Event not generated - 0 + 0x0 Generated Event generated - 1 + 0x1 @@ -6677,6 +6770,7 @@ POSSIBILITY OF SUCH DAMAGE. Semaphore acquired 0x128 read-write + 0x00000000 EVENTS_ACQUIRED @@ -6687,12 +6781,12 @@ POSSIBILITY OF SUCH DAMAGE. NotGenerated Event not generated - 0 + 0x0 Generated Event generated - 1 + 0x1 @@ -6703,6 +6797,7 @@ POSSIBILITY OF SUCH DAMAGE. Publish configuration for event END 0x184 read-write + 0x00000000 CHIDX @@ -6718,12 +6813,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Disable publishing - 0 + 0x0 Enabled Enable publishing - 1 + 0x1 @@ -6734,6 +6829,7 @@ POSSIBILITY OF SUCH DAMAGE. Publish configuration for event ENDRX 0x190 read-write + 0x00000000 CHIDX @@ -6749,12 +6845,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Disable publishing - 0 + 0x0 Enabled Enable publishing - 1 + 0x1 @@ -6765,6 +6861,7 @@ POSSIBILITY OF SUCH DAMAGE. Publish configuration for event ACQUIRED 0x1A8 read-write + 0x00000000 CHIDX @@ -6780,12 +6877,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Disable publishing - 0 + 0x0 Enabled Enable publishing - 1 + 0x1 @@ -6796,6 +6893,7 @@ POSSIBILITY OF SUCH DAMAGE. Shortcuts between local events and tasks 0x200 read-write + 0x00000000 END_ACQUIRE @@ -6806,12 +6904,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Disable shortcut - 0 + 0x0 Enabled Enable shortcut - 1 + 0x1 @@ -6822,6 +6920,7 @@ POSSIBILITY OF SUCH DAMAGE. Enable interrupt 0x304 read-write + 0x00000000 END @@ -6833,12 +6932,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -6846,7 +6945,7 @@ POSSIBILITY OF SUCH DAMAGE. Set Enable - 1 + 0x1 @@ -6860,12 +6959,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -6873,7 +6972,7 @@ POSSIBILITY OF SUCH DAMAGE. Set Enable - 1 + 0x1 @@ -6887,12 +6986,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -6900,7 +6999,7 @@ POSSIBILITY OF SUCH DAMAGE. Set Enable - 1 + 0x1 @@ -6911,6 +7010,7 @@ POSSIBILITY OF SUCH DAMAGE. Disable interrupt 0x308 read-write + 0x00000000 END @@ -6922,12 +7022,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -6935,7 +7035,7 @@ POSSIBILITY OF SUCH DAMAGE. Clear Disable - 1 + 0x1 @@ -6949,12 +7049,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -6962,7 +7062,7 @@ POSSIBILITY OF SUCH DAMAGE. Clear Disable - 1 + 0x1 @@ -6976,12 +7076,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -6989,7 +7089,7 @@ POSSIBILITY OF SUCH DAMAGE. Clear Disable - 1 + 0x1 @@ -7011,22 +7111,22 @@ POSSIBILITY OF SUCH DAMAGE. Free Semaphore is free - 0 + 0x0 CPU Semaphore is assigned to CPU - 1 + 0x1 SPIS Semaphore is assigned to SPI slave - 2 + 0x2 CPUPending Semaphore is assigned to SPI but a handover to the CPU is pending - 3 + 0x3 @@ -7037,6 +7137,7 @@ POSSIBILITY OF SUCH DAMAGE. Status from last transaction 0x440 read-write + 0x00000000 OVERREAD @@ -7048,12 +7149,12 @@ POSSIBILITY OF SUCH DAMAGE. NotPresent Read: error not present - 0 + 0x0 Present Read: error present - 1 + 0x1 @@ -7061,7 +7162,7 @@ POSSIBILITY OF SUCH DAMAGE. Clear Write: clear error on writing '1' - 1 + 0x1 @@ -7075,12 +7176,12 @@ POSSIBILITY OF SUCH DAMAGE. NotPresent Read: error not present - 0 + 0x0 Present Read: error present - 1 + 0x1 @@ -7088,7 +7189,7 @@ POSSIBILITY OF SUCH DAMAGE. Clear Write: clear error on writing '1' - 1 + 0x1 @@ -7099,6 +7200,7 @@ POSSIBILITY OF SUCH DAMAGE. Enable SPI slave 0x500 read-write + 0x00000000 ENABLE @@ -7109,12 +7211,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Disable SPI slave - 0 + 0x0 Enabled Enable SPI slave - 2 + 0x2 @@ -7148,12 +7250,12 @@ POSSIBILITY OF SUCH DAMAGE. Disconnected Disconnect - 1 + 0x1 Connected Connect - 0 + 0x0 @@ -7181,12 +7283,12 @@ POSSIBILITY OF SUCH DAMAGE. Disconnected Disconnect - 1 + 0x1 Connected Connect - 0 + 0x0 @@ -7214,12 +7316,12 @@ POSSIBILITY OF SUCH DAMAGE. Disconnected Disconnect - 1 + 0x1 Connected Connect - 0 + 0x0 @@ -7247,12 +7349,12 @@ POSSIBILITY OF SUCH DAMAGE. Disconnected Disconnect - 1 + 0x1 Connected Connect - 0 + 0x0 @@ -7270,6 +7372,7 @@ POSSIBILITY OF SUCH DAMAGE. RXD data pointer 0x000 read-write + 0x00000000 PTR @@ -7284,6 +7387,7 @@ POSSIBILITY OF SUCH DAMAGE. Maximum number of bytes in receive buffer 0x004 read-write + 0x00000000 MAXCNT @@ -7298,6 +7402,7 @@ POSSIBILITY OF SUCH DAMAGE. Number of bytes received in last granted transaction 0x008 read-only + 0x00000000 AMOUNT @@ -7312,6 +7417,7 @@ POSSIBILITY OF SUCH DAMAGE. EasyDMA list type 0x00C read-write + 0x00000000 LIST @@ -7322,12 +7428,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Disable EasyDMA list - 0 + 0x0 ArrayList Use array list - 1 + 0x1 @@ -7345,6 +7451,7 @@ POSSIBILITY OF SUCH DAMAGE. TXD data pointer 0x000 read-write + 0x00000000 PTR @@ -7359,6 +7466,7 @@ POSSIBILITY OF SUCH DAMAGE. Maximum number of bytes in transmit buffer 0x004 read-write + 0x00000000 MAXCNT @@ -7373,6 +7481,7 @@ POSSIBILITY OF SUCH DAMAGE. Number of bytes transmitted in last granted transaction 0x008 read-only + 0x00000000 AMOUNT @@ -7387,6 +7496,7 @@ POSSIBILITY OF SUCH DAMAGE. EasyDMA list type 0x00C read-write + 0x00000000 LIST @@ -7397,12 +7507,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Disable EasyDMA list - 0 + 0x0 ArrayList Use array list - 1 + 0x1 @@ -7414,6 +7524,7 @@ POSSIBILITY OF SUCH DAMAGE. Configuration register 0x554 read-write + 0x00000000 ORDER @@ -7424,12 +7535,12 @@ POSSIBILITY OF SUCH DAMAGE. MsbFirst Most significant bit shifted out first - 0 + 0x0 LsbFirst Least significant bit shifted out first - 1 + 0x1 @@ -7442,12 +7553,12 @@ POSSIBILITY OF SUCH DAMAGE. Leading Sample on leading edge of clock, shift serial data on trailing edge - 0 + 0x0 Trailing Sample on trailing edge of clock, shift serial data on leading edge - 1 + 0x1 @@ -7460,12 +7571,12 @@ POSSIBILITY OF SUCH DAMAGE. ActiveHigh Active high - 0 + 0x0 ActiveLow Active low - 1 + 0x1 @@ -7476,6 +7587,7 @@ POSSIBILITY OF SUCH DAMAGE. Default character. Character clocked out in case of an ignored transaction. 0x55C read-write + 0x00000000 DEF @@ -7490,6 +7602,7 @@ POSSIBILITY OF SUCH DAMAGE. Over-read character 0x5C0 read-write + 0x00000000 ORC @@ -7526,6 +7639,7 @@ POSSIBILITY OF SUCH DAMAGE. Start TWI receive sequence 0x000 write-only + 0x00000000 TASKS_STARTRX @@ -7536,7 +7650,7 @@ POSSIBILITY OF SUCH DAMAGE. Trigger Trigger task - 1 + 0x1 @@ -7547,6 +7661,7 @@ POSSIBILITY OF SUCH DAMAGE. Start TWI transmit sequence 0x008 write-only + 0x00000000 TASKS_STARTTX @@ -7557,7 +7672,7 @@ POSSIBILITY OF SUCH DAMAGE. Trigger Trigger task - 1 + 0x1 @@ -7568,6 +7683,7 @@ POSSIBILITY OF SUCH DAMAGE. Stop TWI transaction. Must be issued while the TWI master is not suspended. 0x014 write-only + 0x00000000 TASKS_STOP @@ -7578,7 +7694,7 @@ POSSIBILITY OF SUCH DAMAGE. Trigger Trigger task - 1 + 0x1 @@ -7589,6 +7705,7 @@ POSSIBILITY OF SUCH DAMAGE. Suspend TWI transaction 0x01C write-only + 0x00000000 TASKS_SUSPEND @@ -7599,7 +7716,7 @@ POSSIBILITY OF SUCH DAMAGE. Trigger Trigger task - 1 + 0x1 @@ -7610,6 +7727,7 @@ POSSIBILITY OF SUCH DAMAGE. Resume TWI transaction 0x020 write-only + 0x00000000 TASKS_RESUME @@ -7620,7 +7738,7 @@ POSSIBILITY OF SUCH DAMAGE. Trigger Trigger task - 1 + 0x1 @@ -7631,6 +7749,7 @@ POSSIBILITY OF SUCH DAMAGE. Subscribe configuration for task STARTRX 0x080 read-write + 0x00000000 CHIDX @@ -7646,12 +7765,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Disable subscription - 0 + 0x0 Enabled Enable subscription - 1 + 0x1 @@ -7662,6 +7781,7 @@ POSSIBILITY OF SUCH DAMAGE. Subscribe configuration for task STARTTX 0x088 read-write + 0x00000000 CHIDX @@ -7677,12 +7797,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Disable subscription - 0 + 0x0 Enabled Enable subscription - 1 + 0x1 @@ -7693,6 +7813,7 @@ POSSIBILITY OF SUCH DAMAGE. Subscribe configuration for task STOP 0x094 read-write + 0x00000000 CHIDX @@ -7708,12 +7829,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Disable subscription - 0 + 0x0 Enabled Enable subscription - 1 + 0x1 @@ -7724,6 +7845,7 @@ POSSIBILITY OF SUCH DAMAGE. Subscribe configuration for task SUSPEND 0x09C read-write + 0x00000000 CHIDX @@ -7739,12 +7861,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Disable subscription - 0 + 0x0 Enabled Enable subscription - 1 + 0x1 @@ -7755,6 +7877,7 @@ POSSIBILITY OF SUCH DAMAGE. Subscribe configuration for task RESUME 0x0A0 read-write + 0x00000000 CHIDX @@ -7770,12 +7893,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Disable subscription - 0 + 0x0 Enabled Enable subscription - 1 + 0x1 @@ -7786,6 +7909,7 @@ POSSIBILITY OF SUCH DAMAGE. TWI stopped 0x104 read-write + 0x00000000 EVENTS_STOPPED @@ -7796,12 +7920,12 @@ POSSIBILITY OF SUCH DAMAGE. NotGenerated Event not generated - 0 + 0x0 Generated Event generated - 1 + 0x1 @@ -7812,6 +7936,7 @@ POSSIBILITY OF SUCH DAMAGE. TWI error 0x124 read-write + 0x00000000 EVENTS_ERROR @@ -7822,12 +7947,12 @@ POSSIBILITY OF SUCH DAMAGE. NotGenerated Event not generated - 0 + 0x0 Generated Event generated - 1 + 0x1 @@ -7838,6 +7963,7 @@ POSSIBILITY OF SUCH DAMAGE. SUSPEND task has been issued, TWI traffic is now suspended. 0x148 read-write + 0x00000000 EVENTS_SUSPENDED @@ -7848,12 +7974,12 @@ POSSIBILITY OF SUCH DAMAGE. NotGenerated Event not generated - 0 + 0x0 Generated Event generated - 1 + 0x1 @@ -7864,6 +7990,7 @@ POSSIBILITY OF SUCH DAMAGE. Receive sequence started 0x14C read-write + 0x00000000 EVENTS_RXSTARTED @@ -7874,12 +8001,12 @@ POSSIBILITY OF SUCH DAMAGE. NotGenerated Event not generated - 0 + 0x0 Generated Event generated - 1 + 0x1 @@ -7890,6 +8017,7 @@ POSSIBILITY OF SUCH DAMAGE. Transmit sequence started 0x150 read-write + 0x00000000 EVENTS_TXSTARTED @@ -7900,12 +8028,12 @@ POSSIBILITY OF SUCH DAMAGE. NotGenerated Event not generated - 0 + 0x0 Generated Event generated - 1 + 0x1 @@ -7916,6 +8044,7 @@ POSSIBILITY OF SUCH DAMAGE. Byte boundary, starting to receive the last byte 0x15C read-write + 0x00000000 EVENTS_LASTRX @@ -7926,12 +8055,12 @@ POSSIBILITY OF SUCH DAMAGE. NotGenerated Event not generated - 0 + 0x0 Generated Event generated - 1 + 0x1 @@ -7942,6 +8071,7 @@ POSSIBILITY OF SUCH DAMAGE. Byte boundary, starting to transmit the last byte 0x160 read-write + 0x00000000 EVENTS_LASTTX @@ -7952,12 +8082,12 @@ POSSIBILITY OF SUCH DAMAGE. NotGenerated Event not generated - 0 + 0x0 Generated Event generated - 1 + 0x1 @@ -7968,6 +8098,7 @@ POSSIBILITY OF SUCH DAMAGE. Publish configuration for event STOPPED 0x184 read-write + 0x00000000 CHIDX @@ -7983,12 +8114,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Disable publishing - 0 + 0x0 Enabled Enable publishing - 1 + 0x1 @@ -7999,6 +8130,7 @@ POSSIBILITY OF SUCH DAMAGE. Publish configuration for event ERROR 0x1A4 read-write + 0x00000000 CHIDX @@ -8014,12 +8146,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Disable publishing - 0 + 0x0 Enabled Enable publishing - 1 + 0x1 @@ -8030,6 +8162,7 @@ POSSIBILITY OF SUCH DAMAGE. Publish configuration for event SUSPENDED 0x1C8 read-write + 0x00000000 CHIDX @@ -8045,12 +8178,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Disable publishing - 0 + 0x0 Enabled Enable publishing - 1 + 0x1 @@ -8061,6 +8194,7 @@ POSSIBILITY OF SUCH DAMAGE. Publish configuration for event RXSTARTED 0x1CC read-write + 0x00000000 CHIDX @@ -8076,12 +8210,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Disable publishing - 0 + 0x0 Enabled Enable publishing - 1 + 0x1 @@ -8092,6 +8226,7 @@ POSSIBILITY OF SUCH DAMAGE. Publish configuration for event TXSTARTED 0x1D0 read-write + 0x00000000 CHIDX @@ -8107,12 +8242,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Disable publishing - 0 + 0x0 Enabled Enable publishing - 1 + 0x1 @@ -8123,6 +8258,7 @@ POSSIBILITY OF SUCH DAMAGE. Publish configuration for event LASTRX 0x1DC read-write + 0x00000000 CHIDX @@ -8138,12 +8274,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Disable publishing - 0 + 0x0 Enabled Enable publishing - 1 + 0x1 @@ -8154,6 +8290,7 @@ POSSIBILITY OF SUCH DAMAGE. Publish configuration for event LASTTX 0x1E0 read-write + 0x00000000 CHIDX @@ -8169,12 +8306,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Disable publishing - 0 + 0x0 Enabled Enable publishing - 1 + 0x1 @@ -8185,6 +8322,7 @@ POSSIBILITY OF SUCH DAMAGE. Shortcuts between local events and tasks 0x200 read-write + 0x00000000 LASTTX_STARTRX @@ -8195,12 +8333,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Disable shortcut - 0 + 0x0 Enabled Enable shortcut - 1 + 0x1 @@ -8213,12 +8351,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Disable shortcut - 0 + 0x0 Enabled Enable shortcut - 1 + 0x1 @@ -8231,12 +8369,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Disable shortcut - 0 + 0x0 Enabled Enable shortcut - 1 + 0x1 @@ -8249,12 +8387,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Disable shortcut - 0 + 0x0 Enabled Enable shortcut - 1 + 0x1 @@ -8267,12 +8405,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Disable shortcut - 0 + 0x0 Enabled Enable shortcut - 1 + 0x1 @@ -8283,6 +8421,7 @@ POSSIBILITY OF SUCH DAMAGE. Enable or disable interrupt 0x300 read-write + 0x00000000 STOPPED @@ -8293,12 +8432,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Disable - 0 + 0x0 Enabled Enable - 1 + 0x1 @@ -8311,12 +8450,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Disable - 0 + 0x0 Enabled Enable - 1 + 0x1 @@ -8329,12 +8468,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Disable - 0 + 0x0 Enabled Enable - 1 + 0x1 @@ -8347,12 +8486,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Disable - 0 + 0x0 Enabled Enable - 1 + 0x1 @@ -8365,12 +8504,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Disable - 0 + 0x0 Enabled Enable - 1 + 0x1 @@ -8383,12 +8522,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Disable - 0 + 0x0 Enabled Enable - 1 + 0x1 @@ -8401,12 +8540,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Disable - 0 + 0x0 Enabled Enable - 1 + 0x1 @@ -8417,6 +8556,7 @@ POSSIBILITY OF SUCH DAMAGE. Enable interrupt 0x304 read-write + 0x00000000 STOPPED @@ -8428,12 +8568,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -8441,7 +8581,7 @@ POSSIBILITY OF SUCH DAMAGE. Set Enable - 1 + 0x1 @@ -8455,12 +8595,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -8468,7 +8608,7 @@ POSSIBILITY OF SUCH DAMAGE. Set Enable - 1 + 0x1 @@ -8482,12 +8622,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -8495,7 +8635,7 @@ POSSIBILITY OF SUCH DAMAGE. Set Enable - 1 + 0x1 @@ -8509,12 +8649,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -8522,7 +8662,7 @@ POSSIBILITY OF SUCH DAMAGE. Set Enable - 1 + 0x1 @@ -8536,12 +8676,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -8549,7 +8689,7 @@ POSSIBILITY OF SUCH DAMAGE. Set Enable - 1 + 0x1 @@ -8563,12 +8703,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -8576,7 +8716,7 @@ POSSIBILITY OF SUCH DAMAGE. Set Enable - 1 + 0x1 @@ -8590,12 +8730,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -8603,7 +8743,7 @@ POSSIBILITY OF SUCH DAMAGE. Set Enable - 1 + 0x1 @@ -8614,6 +8754,7 @@ POSSIBILITY OF SUCH DAMAGE. Disable interrupt 0x308 read-write + 0x00000000 STOPPED @@ -8625,12 +8766,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -8638,7 +8779,7 @@ POSSIBILITY OF SUCH DAMAGE. Clear Disable - 1 + 0x1 @@ -8652,12 +8793,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -8665,7 +8806,7 @@ POSSIBILITY OF SUCH DAMAGE. Clear Disable - 1 + 0x1 @@ -8679,12 +8820,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -8692,7 +8833,7 @@ POSSIBILITY OF SUCH DAMAGE. Clear Disable - 1 + 0x1 @@ -8706,12 +8847,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -8719,7 +8860,7 @@ POSSIBILITY OF SUCH DAMAGE. Clear Disable - 1 + 0x1 @@ -8733,12 +8874,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -8746,7 +8887,7 @@ POSSIBILITY OF SUCH DAMAGE. Clear Disable - 1 + 0x1 @@ -8760,12 +8901,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -8773,7 +8914,7 @@ POSSIBILITY OF SUCH DAMAGE. Clear Disable - 1 + 0x1 @@ -8787,12 +8928,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -8800,7 +8941,7 @@ POSSIBILITY OF SUCH DAMAGE. Clear Disable - 1 + 0x1 @@ -8811,6 +8952,7 @@ POSSIBILITY OF SUCH DAMAGE. Error source 0x4C4 read-write + 0x00000000 oneToClear @@ -8822,12 +8964,12 @@ POSSIBILITY OF SUCH DAMAGE. NotReceived Error did not occur - 0 + 0x0 Received Error occurred - 1 + 0x1 @@ -8840,12 +8982,12 @@ POSSIBILITY OF SUCH DAMAGE. NotReceived Error did not occur - 0 + 0x0 Received Error occurred - 1 + 0x1 @@ -8858,12 +9000,12 @@ POSSIBILITY OF SUCH DAMAGE. NotReceived Error did not occur - 0 + 0x0 Received Error occurred - 1 + 0x1 @@ -8874,6 +9016,7 @@ POSSIBILITY OF SUCH DAMAGE. Enable TWIM 0x500 read-write + 0x00000000 ENABLE @@ -8884,12 +9027,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Disable TWIM - 0 + 0x0 Enabled Enable TWIM - 6 + 0x6 @@ -8923,12 +9066,12 @@ POSSIBILITY OF SUCH DAMAGE. Disconnected Disconnect - 1 + 0x1 Connected Connect - 0 + 0x0 @@ -8956,12 +9099,12 @@ POSSIBILITY OF SUCH DAMAGE. Disconnected Disconnect - 1 + 0x1 Connected Connect - 0 + 0x0 @@ -9011,6 +9154,7 @@ POSSIBILITY OF SUCH DAMAGE. Data pointer 0x000 read-write + 0x00000000 PTR @@ -9025,6 +9169,7 @@ POSSIBILITY OF SUCH DAMAGE. Maximum number of bytes in receive buffer 0x004 read-write + 0x00000000 MAXCNT @@ -9039,6 +9184,7 @@ POSSIBILITY OF SUCH DAMAGE. Number of bytes transferred in the last transaction 0x008 read-only + 0x00000000 AMOUNT @@ -9053,6 +9199,7 @@ POSSIBILITY OF SUCH DAMAGE. EasyDMA list type 0x00C read-write + 0x00000000 LIST @@ -9063,12 +9210,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Disable EasyDMA list - 0 + 0x0 ArrayList Use array list - 1 + 0x1 @@ -9086,6 +9233,7 @@ POSSIBILITY OF SUCH DAMAGE. Data pointer 0x000 read-write + 0x00000000 PTR @@ -9100,6 +9248,7 @@ POSSIBILITY OF SUCH DAMAGE. Maximum number of bytes in transmit buffer 0x004 read-write + 0x00000000 MAXCNT @@ -9114,6 +9263,7 @@ POSSIBILITY OF SUCH DAMAGE. Number of bytes transferred in the last transaction 0x008 read-only + 0x00000000 AMOUNT @@ -9128,6 +9278,7 @@ POSSIBILITY OF SUCH DAMAGE. EasyDMA list type 0x00C read-write + 0x00000000 LIST @@ -9138,12 +9289,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Disable EasyDMA list - 0 + 0x0 ArrayList Use array list - 1 + 0x1 @@ -9155,6 +9306,7 @@ POSSIBILITY OF SUCH DAMAGE. Address used in the TWI transfer 0x588 read-write + 0x00000000 ADDRESS @@ -9191,6 +9343,7 @@ POSSIBILITY OF SUCH DAMAGE. Stop TWI transaction 0x014 write-only + 0x00000000 TASKS_STOP @@ -9201,7 +9354,7 @@ POSSIBILITY OF SUCH DAMAGE. Trigger Trigger task - 1 + 0x1 @@ -9212,6 +9365,7 @@ POSSIBILITY OF SUCH DAMAGE. Suspend TWI transaction 0x01C write-only + 0x00000000 TASKS_SUSPEND @@ -9222,7 +9376,7 @@ POSSIBILITY OF SUCH DAMAGE. Trigger Trigger task - 1 + 0x1 @@ -9233,6 +9387,7 @@ POSSIBILITY OF SUCH DAMAGE. Resume TWI transaction 0x020 write-only + 0x00000000 TASKS_RESUME @@ -9243,7 +9398,7 @@ POSSIBILITY OF SUCH DAMAGE. Trigger Trigger task - 1 + 0x1 @@ -9254,6 +9409,7 @@ POSSIBILITY OF SUCH DAMAGE. Prepare the TWI slave to respond to a write command 0x030 write-only + 0x00000000 TASKS_PREPARERX @@ -9264,7 +9420,7 @@ POSSIBILITY OF SUCH DAMAGE. Trigger Trigger task - 1 + 0x1 @@ -9275,6 +9431,7 @@ POSSIBILITY OF SUCH DAMAGE. Prepare the TWI slave to respond to a read command 0x034 write-only + 0x00000000 TASKS_PREPARETX @@ -9285,7 +9442,7 @@ POSSIBILITY OF SUCH DAMAGE. Trigger Trigger task - 1 + 0x1 @@ -9296,6 +9453,7 @@ POSSIBILITY OF SUCH DAMAGE. Subscribe configuration for task STOP 0x094 read-write + 0x00000000 CHIDX @@ -9311,12 +9469,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Disable subscription - 0 + 0x0 Enabled Enable subscription - 1 + 0x1 @@ -9327,6 +9485,7 @@ POSSIBILITY OF SUCH DAMAGE. Subscribe configuration for task SUSPEND 0x09C read-write + 0x00000000 CHIDX @@ -9342,12 +9501,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Disable subscription - 0 + 0x0 Enabled Enable subscription - 1 + 0x1 @@ -9358,6 +9517,7 @@ POSSIBILITY OF SUCH DAMAGE. Subscribe configuration for task RESUME 0x0A0 read-write + 0x00000000 CHIDX @@ -9373,12 +9533,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Disable subscription - 0 + 0x0 Enabled Enable subscription - 1 + 0x1 @@ -9389,6 +9549,7 @@ POSSIBILITY OF SUCH DAMAGE. Subscribe configuration for task PREPARERX 0x0B0 read-write + 0x00000000 CHIDX @@ -9404,12 +9565,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Disable subscription - 0 + 0x0 Enabled Enable subscription - 1 + 0x1 @@ -9420,6 +9581,7 @@ POSSIBILITY OF SUCH DAMAGE. Subscribe configuration for task PREPARETX 0x0B4 read-write + 0x00000000 CHIDX @@ -9435,12 +9597,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Disable subscription - 0 + 0x0 Enabled Enable subscription - 1 + 0x1 @@ -9451,6 +9613,7 @@ POSSIBILITY OF SUCH DAMAGE. TWI stopped 0x104 read-write + 0x00000000 EVENTS_STOPPED @@ -9461,12 +9624,12 @@ POSSIBILITY OF SUCH DAMAGE. NotGenerated Event not generated - 0 + 0x0 Generated Event generated - 1 + 0x1 @@ -9477,6 +9640,7 @@ POSSIBILITY OF SUCH DAMAGE. TWI error 0x124 read-write + 0x00000000 EVENTS_ERROR @@ -9487,12 +9651,12 @@ POSSIBILITY OF SUCH DAMAGE. NotGenerated Event not generated - 0 + 0x0 Generated Event generated - 1 + 0x1 @@ -9503,6 +9667,7 @@ POSSIBILITY OF SUCH DAMAGE. Receive sequence started 0x14C read-write + 0x00000000 EVENTS_RXSTARTED @@ -9513,12 +9678,12 @@ POSSIBILITY OF SUCH DAMAGE. NotGenerated Event not generated - 0 + 0x0 Generated Event generated - 1 + 0x1 @@ -9529,6 +9694,7 @@ POSSIBILITY OF SUCH DAMAGE. Transmit sequence started 0x150 read-write + 0x00000000 EVENTS_TXSTARTED @@ -9539,12 +9705,12 @@ POSSIBILITY OF SUCH DAMAGE. NotGenerated Event not generated - 0 + 0x0 Generated Event generated - 1 + 0x1 @@ -9555,6 +9721,7 @@ POSSIBILITY OF SUCH DAMAGE. Write command received 0x164 read-write + 0x00000000 EVENTS_WRITE @@ -9565,12 +9732,12 @@ POSSIBILITY OF SUCH DAMAGE. NotGenerated Event not generated - 0 + 0x0 Generated Event generated - 1 + 0x1 @@ -9581,6 +9748,7 @@ POSSIBILITY OF SUCH DAMAGE. Read command received 0x168 read-write + 0x00000000 EVENTS_READ @@ -9591,12 +9759,12 @@ POSSIBILITY OF SUCH DAMAGE. NotGenerated Event not generated - 0 + 0x0 Generated Event generated - 1 + 0x1 @@ -9607,6 +9775,7 @@ POSSIBILITY OF SUCH DAMAGE. Publish configuration for event STOPPED 0x184 read-write + 0x00000000 CHIDX @@ -9622,12 +9791,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Disable publishing - 0 + 0x0 Enabled Enable publishing - 1 + 0x1 @@ -9638,6 +9807,7 @@ POSSIBILITY OF SUCH DAMAGE. Publish configuration for event ERROR 0x1A4 read-write + 0x00000000 CHIDX @@ -9653,12 +9823,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Disable publishing - 0 + 0x0 Enabled Enable publishing - 1 + 0x1 @@ -9669,6 +9839,7 @@ POSSIBILITY OF SUCH DAMAGE. Publish configuration for event RXSTARTED 0x1CC read-write + 0x00000000 CHIDX @@ -9684,12 +9855,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Disable publishing - 0 + 0x0 Enabled Enable publishing - 1 + 0x1 @@ -9700,6 +9871,7 @@ POSSIBILITY OF SUCH DAMAGE. Publish configuration for event TXSTARTED 0x1D0 read-write + 0x00000000 CHIDX @@ -9715,12 +9887,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Disable publishing - 0 + 0x0 Enabled Enable publishing - 1 + 0x1 @@ -9731,6 +9903,7 @@ POSSIBILITY OF SUCH DAMAGE. Publish configuration for event WRITE 0x1E4 read-write + 0x00000000 CHIDX @@ -9746,12 +9919,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Disable publishing - 0 + 0x0 Enabled Enable publishing - 1 + 0x1 @@ -9762,6 +9935,7 @@ POSSIBILITY OF SUCH DAMAGE. Publish configuration for event READ 0x1E8 read-write + 0x00000000 CHIDX @@ -9777,12 +9951,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Disable publishing - 0 + 0x0 Enabled Enable publishing - 1 + 0x1 @@ -9793,6 +9967,7 @@ POSSIBILITY OF SUCH DAMAGE. Shortcuts between local events and tasks 0x200 read-write + 0x00000000 WRITE_SUSPEND @@ -9803,12 +9978,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Disable shortcut - 0 + 0x0 Enabled Enable shortcut - 1 + 0x1 @@ -9821,12 +9996,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Disable shortcut - 0 + 0x0 Enabled Enable shortcut - 1 + 0x1 @@ -9837,6 +10012,7 @@ POSSIBILITY OF SUCH DAMAGE. Enable or disable interrupt 0x300 read-write + 0x00000000 STOPPED @@ -9847,12 +10023,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Disable - 0 + 0x0 Enabled Enable - 1 + 0x1 @@ -9865,12 +10041,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Disable - 0 + 0x0 Enabled Enable - 1 + 0x1 @@ -9883,12 +10059,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Disable - 0 + 0x0 Enabled Enable - 1 + 0x1 @@ -9901,12 +10077,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Disable - 0 + 0x0 Enabled Enable - 1 + 0x1 @@ -9919,12 +10095,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Disable - 0 + 0x0 Enabled Enable - 1 + 0x1 @@ -9937,12 +10113,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Disable - 0 + 0x0 Enabled Enable - 1 + 0x1 @@ -9953,6 +10129,7 @@ POSSIBILITY OF SUCH DAMAGE. Enable interrupt 0x304 read-write + 0x00000000 STOPPED @@ -9964,12 +10141,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -9977,7 +10154,7 @@ POSSIBILITY OF SUCH DAMAGE. Set Enable - 1 + 0x1 @@ -9991,12 +10168,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -10004,7 +10181,7 @@ POSSIBILITY OF SUCH DAMAGE. Set Enable - 1 + 0x1 @@ -10018,12 +10195,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -10031,7 +10208,7 @@ POSSIBILITY OF SUCH DAMAGE. Set Enable - 1 + 0x1 @@ -10045,12 +10222,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -10058,7 +10235,7 @@ POSSIBILITY OF SUCH DAMAGE. Set Enable - 1 + 0x1 @@ -10072,12 +10249,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -10085,7 +10262,7 @@ POSSIBILITY OF SUCH DAMAGE. Set Enable - 1 + 0x1 @@ -10099,12 +10276,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -10112,7 +10289,7 @@ POSSIBILITY OF SUCH DAMAGE. Set Enable - 1 + 0x1 @@ -10123,6 +10300,7 @@ POSSIBILITY OF SUCH DAMAGE. Disable interrupt 0x308 read-write + 0x00000000 STOPPED @@ -10134,12 +10312,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -10147,7 +10325,7 @@ POSSIBILITY OF SUCH DAMAGE. Clear Disable - 1 + 0x1 @@ -10161,12 +10339,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -10174,7 +10352,7 @@ POSSIBILITY OF SUCH DAMAGE. Clear Disable - 1 + 0x1 @@ -10188,12 +10366,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -10201,7 +10379,7 @@ POSSIBILITY OF SUCH DAMAGE. Clear Disable - 1 + 0x1 @@ -10215,12 +10393,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -10228,7 +10406,7 @@ POSSIBILITY OF SUCH DAMAGE. Clear Disable - 1 + 0x1 @@ -10242,12 +10420,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -10255,7 +10433,7 @@ POSSIBILITY OF SUCH DAMAGE. Clear Disable - 1 + 0x1 @@ -10269,12 +10447,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -10282,7 +10460,7 @@ POSSIBILITY OF SUCH DAMAGE. Clear Disable - 1 + 0x1 @@ -10293,6 +10471,7 @@ POSSIBILITY OF SUCH DAMAGE. Error source 0x4D0 read-write + 0x00000000 oneToClear @@ -10304,12 +10483,12 @@ POSSIBILITY OF SUCH DAMAGE. NotDetected Error did not occur - 0 + 0x0 Detected Error occurred - 1 + 0x1 @@ -10322,12 +10501,12 @@ POSSIBILITY OF SUCH DAMAGE. NotReceived Error did not occur - 0 + 0x0 Received Error occurred - 1 + 0x1 @@ -10340,12 +10519,12 @@ POSSIBILITY OF SUCH DAMAGE. NotDetected Error did not occur - 0 + 0x0 Detected Error occurred - 1 + 0x1 @@ -10356,10 +10535,11 @@ POSSIBILITY OF SUCH DAMAGE. Status register indicating which address had a match 0x4D4 read-only + 0x00000000 MATCH - Indication of which address in {ADDRESS} that matched the incoming address + Indication of which address in ADDRESS that matched the incoming address 0 0 @@ -10370,6 +10550,7 @@ POSSIBILITY OF SUCH DAMAGE. Enable TWIS 0x500 read-write + 0x00000000 ENABLE @@ -10380,12 +10561,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Disable TWIS - 0 + 0x0 Enabled Enable TWIS - 9 + 0x9 @@ -10419,12 +10600,12 @@ POSSIBILITY OF SUCH DAMAGE. Disconnected Disconnect - 1 + 0x1 Connected Connect - 0 + 0x0 @@ -10452,12 +10633,12 @@ POSSIBILITY OF SUCH DAMAGE. Disconnected Disconnect - 1 + 0x1 Connected Connect - 0 + 0x0 @@ -10475,6 +10656,7 @@ POSSIBILITY OF SUCH DAMAGE. RXD Data pointer 0x000 read-write + 0x00000000 PTR @@ -10489,6 +10671,7 @@ POSSIBILITY OF SUCH DAMAGE. Maximum number of bytes in RXD buffer 0x004 read-write + 0x00000000 MAXCNT @@ -10503,6 +10686,7 @@ POSSIBILITY OF SUCH DAMAGE. Number of bytes transferred in the last RXD transaction 0x008 read-only + 0x00000000 AMOUNT @@ -10517,6 +10701,7 @@ POSSIBILITY OF SUCH DAMAGE. EasyDMA list type 0x00C read-write + 0x00000000 LIST @@ -10527,12 +10712,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Disable EasyDMA list - 0 + 0x0 ArrayList Use array list - 1 + 0x1 @@ -10550,6 +10735,7 @@ POSSIBILITY OF SUCH DAMAGE. TXD Data pointer 0x000 read-write + 0x00000000 PTR @@ -10564,6 +10750,7 @@ POSSIBILITY OF SUCH DAMAGE. Maximum number of bytes in TXD buffer 0x004 read-write + 0x00000000 MAXCNT @@ -10578,6 +10765,7 @@ POSSIBILITY OF SUCH DAMAGE. Number of bytes transferred in the last TXD transaction 0x008 read-only + 0x00000000 AMOUNT @@ -10592,6 +10780,7 @@ POSSIBILITY OF SUCH DAMAGE. EasyDMA list type 0x00C read-write + 0x00000000 LIST @@ -10602,12 +10791,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Disable EasyDMA list - 0 + 0x0 ArrayList Use array list - 1 + 0x1 @@ -10621,6 +10810,7 @@ POSSIBILITY OF SUCH DAMAGE. Description collection: TWI slave address n 0x588 read-write + 0x00000000 ADDRESS @@ -10646,12 +10836,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Disabled - 0 + 0x0 Enabled Enabled - 1 + 0x1 @@ -10664,12 +10854,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Disabled - 0 + 0x0 Enabled Enabled - 1 + 0x1 @@ -10680,6 +10870,7 @@ POSSIBILITY OF SUCH DAMAGE. Over-read character. Character sent out in case of an over-read of the transmit buffer. 0x5C0 read-write + 0x00000000 ORC @@ -10716,6 +10907,7 @@ POSSIBILITY OF SUCH DAMAGE. Start UART receiver 0x000 write-only + 0x00000000 TASKS_STARTRX @@ -10726,7 +10918,7 @@ POSSIBILITY OF SUCH DAMAGE. Trigger Trigger task - 1 + 0x1 @@ -10737,6 +10929,7 @@ POSSIBILITY OF SUCH DAMAGE. Stop UART receiver 0x004 write-only + 0x00000000 TASKS_STOPRX @@ -10747,7 +10940,7 @@ POSSIBILITY OF SUCH DAMAGE. Trigger Trigger task - 1 + 0x1 @@ -10758,6 +10951,7 @@ POSSIBILITY OF SUCH DAMAGE. Start UART transmitter 0x008 write-only + 0x00000000 TASKS_STARTTX @@ -10768,7 +10962,7 @@ POSSIBILITY OF SUCH DAMAGE. Trigger Trigger task - 1 + 0x1 @@ -10779,6 +10973,7 @@ POSSIBILITY OF SUCH DAMAGE. Stop UART transmitter 0x00C write-only + 0x00000000 TASKS_STOPTX @@ -10789,7 +10984,7 @@ POSSIBILITY OF SUCH DAMAGE. Trigger Trigger task - 1 + 0x1 @@ -10800,6 +10995,7 @@ POSSIBILITY OF SUCH DAMAGE. Flush RX FIFO into RX buffer 0x02C write-only + 0x00000000 TASKS_FLUSHRX @@ -10810,7 +11006,7 @@ POSSIBILITY OF SUCH DAMAGE. Trigger Trigger task - 1 + 0x1 @@ -10821,6 +11017,7 @@ POSSIBILITY OF SUCH DAMAGE. Subscribe configuration for task STARTRX 0x080 read-write + 0x00000000 CHIDX @@ -10836,12 +11033,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Disable subscription - 0 + 0x0 Enabled Enable subscription - 1 + 0x1 @@ -10852,6 +11049,7 @@ POSSIBILITY OF SUCH DAMAGE. Subscribe configuration for task STOPRX 0x084 read-write + 0x00000000 CHIDX @@ -10867,12 +11065,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Disable subscription - 0 + 0x0 Enabled Enable subscription - 1 + 0x1 @@ -10883,6 +11081,7 @@ POSSIBILITY OF SUCH DAMAGE. Subscribe configuration for task STARTTX 0x088 read-write + 0x00000000 CHIDX @@ -10898,12 +11097,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Disable subscription - 0 + 0x0 Enabled Enable subscription - 1 + 0x1 @@ -10914,6 +11113,7 @@ POSSIBILITY OF SUCH DAMAGE. Subscribe configuration for task STOPTX 0x08C read-write + 0x00000000 CHIDX @@ -10929,12 +11129,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Disable subscription - 0 + 0x0 Enabled Enable subscription - 1 + 0x1 @@ -10945,6 +11145,7 @@ POSSIBILITY OF SUCH DAMAGE. Subscribe configuration for task FLUSHRX 0x0AC read-write + 0x00000000 CHIDX @@ -10960,12 +11161,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Disable subscription - 0 + 0x0 Enabled Enable subscription - 1 + 0x1 @@ -10976,6 +11177,7 @@ POSSIBILITY OF SUCH DAMAGE. CTS is activated (set low). Clear To Send. 0x100 read-write + 0x00000000 EVENTS_CTS @@ -10986,12 +11188,12 @@ POSSIBILITY OF SUCH DAMAGE. NotGenerated Event not generated - 0 + 0x0 Generated Event generated - 1 + 0x1 @@ -11002,6 +11204,7 @@ POSSIBILITY OF SUCH DAMAGE. CTS is deactivated (set high). Not Clear To Send. 0x104 read-write + 0x00000000 EVENTS_NCTS @@ -11012,12 +11215,12 @@ POSSIBILITY OF SUCH DAMAGE. NotGenerated Event not generated - 0 + 0x0 Generated Event generated - 1 + 0x1 @@ -11028,6 +11231,7 @@ POSSIBILITY OF SUCH DAMAGE. Data received in RXD (but potentially not yet transferred to Data RAM) 0x108 read-write + 0x00000000 EVENTS_RXDRDY @@ -11038,12 +11242,12 @@ POSSIBILITY OF SUCH DAMAGE. NotGenerated Event not generated - 0 + 0x0 Generated Event generated - 1 + 0x1 @@ -11054,6 +11258,7 @@ POSSIBILITY OF SUCH DAMAGE. Receive buffer is filled up 0x110 read-write + 0x00000000 EVENTS_ENDRX @@ -11064,12 +11269,12 @@ POSSIBILITY OF SUCH DAMAGE. NotGenerated Event not generated - 0 + 0x0 Generated Event generated - 1 + 0x1 @@ -11080,6 +11285,7 @@ POSSIBILITY OF SUCH DAMAGE. Data sent from TXD 0x11C read-write + 0x00000000 EVENTS_TXDRDY @@ -11090,12 +11296,12 @@ POSSIBILITY OF SUCH DAMAGE. NotGenerated Event not generated - 0 + 0x0 Generated Event generated - 1 + 0x1 @@ -11106,6 +11312,7 @@ POSSIBILITY OF SUCH DAMAGE. Last TX byte transmitted 0x120 read-write + 0x00000000 EVENTS_ENDTX @@ -11116,12 +11323,12 @@ POSSIBILITY OF SUCH DAMAGE. NotGenerated Event not generated - 0 + 0x0 Generated Event generated - 1 + 0x1 @@ -11132,6 +11339,7 @@ POSSIBILITY OF SUCH DAMAGE. Error detected 0x124 read-write + 0x00000000 EVENTS_ERROR @@ -11142,12 +11350,12 @@ POSSIBILITY OF SUCH DAMAGE. NotGenerated Event not generated - 0 + 0x0 Generated Event generated - 1 + 0x1 @@ -11158,6 +11366,7 @@ POSSIBILITY OF SUCH DAMAGE. Receiver timeout 0x144 read-write + 0x00000000 EVENTS_RXTO @@ -11168,12 +11377,12 @@ POSSIBILITY OF SUCH DAMAGE. NotGenerated Event not generated - 0 + 0x0 Generated Event generated - 1 + 0x1 @@ -11184,6 +11393,7 @@ POSSIBILITY OF SUCH DAMAGE. UART receiver has started 0x14C read-write + 0x00000000 EVENTS_RXSTARTED @@ -11194,12 +11404,12 @@ POSSIBILITY OF SUCH DAMAGE. NotGenerated Event not generated - 0 + 0x0 Generated Event generated - 1 + 0x1 @@ -11210,6 +11420,7 @@ POSSIBILITY OF SUCH DAMAGE. UART transmitter has started 0x150 read-write + 0x00000000 EVENTS_TXSTARTED @@ -11220,12 +11431,12 @@ POSSIBILITY OF SUCH DAMAGE. NotGenerated Event not generated - 0 + 0x0 Generated Event generated - 1 + 0x1 @@ -11236,6 +11447,7 @@ POSSIBILITY OF SUCH DAMAGE. Transmitter stopped 0x158 read-write + 0x00000000 EVENTS_TXSTOPPED @@ -11246,12 +11458,12 @@ POSSIBILITY OF SUCH DAMAGE. NotGenerated Event not generated - 0 + 0x0 Generated Event generated - 1 + 0x1 @@ -11262,6 +11474,7 @@ POSSIBILITY OF SUCH DAMAGE. Publish configuration for event CTS 0x180 read-write + 0x00000000 CHIDX @@ -11277,12 +11490,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Disable publishing - 0 + 0x0 Enabled Enable publishing - 1 + 0x1 @@ -11293,6 +11506,7 @@ POSSIBILITY OF SUCH DAMAGE. Publish configuration for event NCTS 0x184 read-write + 0x00000000 CHIDX @@ -11308,12 +11522,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Disable publishing - 0 + 0x0 Enabled Enable publishing - 1 + 0x1 @@ -11324,6 +11538,7 @@ POSSIBILITY OF SUCH DAMAGE. Publish configuration for event RXDRDY 0x188 read-write + 0x00000000 CHIDX @@ -11339,12 +11554,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Disable publishing - 0 + 0x0 Enabled Enable publishing - 1 + 0x1 @@ -11355,6 +11570,7 @@ POSSIBILITY OF SUCH DAMAGE. Publish configuration for event ENDRX 0x190 read-write + 0x00000000 CHIDX @@ -11370,12 +11586,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Disable publishing - 0 + 0x0 Enabled Enable publishing - 1 + 0x1 @@ -11386,6 +11602,7 @@ POSSIBILITY OF SUCH DAMAGE. Publish configuration for event TXDRDY 0x19C read-write + 0x00000000 CHIDX @@ -11401,12 +11618,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Disable publishing - 0 + 0x0 Enabled Enable publishing - 1 + 0x1 @@ -11417,6 +11634,7 @@ POSSIBILITY OF SUCH DAMAGE. Publish configuration for event ENDTX 0x1A0 read-write + 0x00000000 CHIDX @@ -11432,12 +11650,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Disable publishing - 0 + 0x0 Enabled Enable publishing - 1 + 0x1 @@ -11448,6 +11666,7 @@ POSSIBILITY OF SUCH DAMAGE. Publish configuration for event ERROR 0x1A4 read-write + 0x00000000 CHIDX @@ -11463,12 +11682,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Disable publishing - 0 + 0x0 Enabled Enable publishing - 1 + 0x1 @@ -11479,6 +11698,7 @@ POSSIBILITY OF SUCH DAMAGE. Publish configuration for event RXTO 0x1C4 read-write + 0x00000000 CHIDX @@ -11494,12 +11714,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Disable publishing - 0 + 0x0 Enabled Enable publishing - 1 + 0x1 @@ -11510,6 +11730,7 @@ POSSIBILITY OF SUCH DAMAGE. Publish configuration for event RXSTARTED 0x1CC read-write + 0x00000000 CHIDX @@ -11525,12 +11746,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Disable publishing - 0 + 0x0 Enabled Enable publishing - 1 + 0x1 @@ -11541,6 +11762,7 @@ POSSIBILITY OF SUCH DAMAGE. Publish configuration for event TXSTARTED 0x1D0 read-write + 0x00000000 CHIDX @@ -11556,12 +11778,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Disable publishing - 0 + 0x0 Enabled Enable publishing - 1 + 0x1 @@ -11572,6 +11794,7 @@ POSSIBILITY OF SUCH DAMAGE. Publish configuration for event TXSTOPPED 0x1D8 read-write + 0x00000000 CHIDX @@ -11587,12 +11810,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Disable publishing - 0 + 0x0 Enabled Enable publishing - 1 + 0x1 @@ -11603,6 +11826,7 @@ POSSIBILITY OF SUCH DAMAGE. Shortcuts between local events and tasks 0x200 read-write + 0x00000000 ENDRX_STARTRX @@ -11613,12 +11837,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Disable shortcut - 0 + 0x0 Enabled Enable shortcut - 1 + 0x1 @@ -11631,12 +11855,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Disable shortcut - 0 + 0x0 Enabled Enable shortcut - 1 + 0x1 @@ -11647,6 +11871,7 @@ POSSIBILITY OF SUCH DAMAGE. Enable or disable interrupt 0x300 read-write + 0x00000000 CTS @@ -11657,12 +11882,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Disable - 0 + 0x0 Enabled Enable - 1 + 0x1 @@ -11675,12 +11900,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Disable - 0 + 0x0 Enabled Enable - 1 + 0x1 @@ -11693,12 +11918,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Disable - 0 + 0x0 Enabled Enable - 1 + 0x1 @@ -11711,12 +11936,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Disable - 0 + 0x0 Enabled Enable - 1 + 0x1 @@ -11729,12 +11954,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Disable - 0 + 0x0 Enabled Enable - 1 + 0x1 @@ -11747,12 +11972,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Disable - 0 + 0x0 Enabled Enable - 1 + 0x1 @@ -11765,12 +11990,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Disable - 0 + 0x0 Enabled Enable - 1 + 0x1 @@ -11783,12 +12008,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Disable - 0 + 0x0 Enabled Enable - 1 + 0x1 @@ -11801,12 +12026,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Disable - 0 + 0x0 Enabled Enable - 1 + 0x1 @@ -11819,12 +12044,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Disable - 0 + 0x0 Enabled Enable - 1 + 0x1 @@ -11837,12 +12062,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Disable - 0 + 0x0 Enabled Enable - 1 + 0x1 @@ -11853,6 +12078,7 @@ POSSIBILITY OF SUCH DAMAGE. Enable interrupt 0x304 read-write + 0x00000000 CTS @@ -11864,12 +12090,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -11877,7 +12103,7 @@ POSSIBILITY OF SUCH DAMAGE. Set Enable - 1 + 0x1 @@ -11891,12 +12117,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -11904,7 +12130,7 @@ POSSIBILITY OF SUCH DAMAGE. Set Enable - 1 + 0x1 @@ -11918,12 +12144,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -11931,7 +12157,7 @@ POSSIBILITY OF SUCH DAMAGE. Set Enable - 1 + 0x1 @@ -11945,12 +12171,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -11958,7 +12184,7 @@ POSSIBILITY OF SUCH DAMAGE. Set Enable - 1 + 0x1 @@ -11972,12 +12198,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -11985,7 +12211,7 @@ POSSIBILITY OF SUCH DAMAGE. Set Enable - 1 + 0x1 @@ -11999,12 +12225,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -12012,7 +12238,7 @@ POSSIBILITY OF SUCH DAMAGE. Set Enable - 1 + 0x1 @@ -12026,12 +12252,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -12039,7 +12265,7 @@ POSSIBILITY OF SUCH DAMAGE. Set Enable - 1 + 0x1 @@ -12053,12 +12279,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -12066,7 +12292,7 @@ POSSIBILITY OF SUCH DAMAGE. Set Enable - 1 + 0x1 @@ -12080,12 +12306,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -12093,7 +12319,7 @@ POSSIBILITY OF SUCH DAMAGE. Set Enable - 1 + 0x1 @@ -12107,12 +12333,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -12120,7 +12346,7 @@ POSSIBILITY OF SUCH DAMAGE. Set Enable - 1 + 0x1 @@ -12134,12 +12360,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -12147,7 +12373,7 @@ POSSIBILITY OF SUCH DAMAGE. Set Enable - 1 + 0x1 @@ -12158,6 +12384,7 @@ POSSIBILITY OF SUCH DAMAGE. Disable interrupt 0x308 read-write + 0x00000000 CTS @@ -12169,12 +12396,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -12182,7 +12409,7 @@ POSSIBILITY OF SUCH DAMAGE. Clear Disable - 1 + 0x1 @@ -12196,12 +12423,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -12209,7 +12436,7 @@ POSSIBILITY OF SUCH DAMAGE. Clear Disable - 1 + 0x1 @@ -12223,12 +12450,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -12236,7 +12463,7 @@ POSSIBILITY OF SUCH DAMAGE. Clear Disable - 1 + 0x1 @@ -12250,12 +12477,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -12263,7 +12490,7 @@ POSSIBILITY OF SUCH DAMAGE. Clear Disable - 1 + 0x1 @@ -12277,12 +12504,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -12290,7 +12517,7 @@ POSSIBILITY OF SUCH DAMAGE. Clear Disable - 1 + 0x1 @@ -12304,12 +12531,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -12317,7 +12544,7 @@ POSSIBILITY OF SUCH DAMAGE. Clear Disable - 1 + 0x1 @@ -12331,12 +12558,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -12344,7 +12571,7 @@ POSSIBILITY OF SUCH DAMAGE. Clear Disable - 1 + 0x1 @@ -12358,12 +12585,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -12371,7 +12598,7 @@ POSSIBILITY OF SUCH DAMAGE. Clear Disable - 1 + 0x1 @@ -12385,12 +12612,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -12398,7 +12625,7 @@ POSSIBILITY OF SUCH DAMAGE. Clear Disable - 1 + 0x1 @@ -12412,12 +12639,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -12425,7 +12652,7 @@ POSSIBILITY OF SUCH DAMAGE. Clear Disable - 1 + 0x1 @@ -12439,12 +12666,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -12452,7 +12679,7 @@ POSSIBILITY OF SUCH DAMAGE. Clear Disable - 1 + 0x1 @@ -12463,6 +12690,7 @@ POSSIBILITY OF SUCH DAMAGE. Error source This register is read/write one to clear. 0x480 read-write + 0x00000000 oneToClear @@ -12475,12 +12703,12 @@ POSSIBILITY OF SUCH DAMAGE. NotPresent Read: error not present - 0 + 0x0 Present Read: error present - 1 + 0x1 @@ -12494,12 +12722,12 @@ POSSIBILITY OF SUCH DAMAGE. NotPresent Read: error not present - 0 + 0x0 Present Read: error present - 1 + 0x1 @@ -12513,12 +12741,12 @@ POSSIBILITY OF SUCH DAMAGE. NotPresent Read: error not present - 0 + 0x0 Present Read: error present - 1 + 0x1 @@ -12532,12 +12760,12 @@ POSSIBILITY OF SUCH DAMAGE. NotPresent Read: error not present - 0 + 0x0 Present Read: error present - 1 + 0x1 @@ -12548,6 +12776,7 @@ POSSIBILITY OF SUCH DAMAGE. Enable UART 0x500 read-write + 0x00000000 ENABLE @@ -12558,12 +12787,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Disable UARTE - 0 + 0x0 Enabled Enable UARTE - 8 + 0x8 @@ -12597,12 +12826,12 @@ POSSIBILITY OF SUCH DAMAGE. Disconnected Disconnect - 1 + 0x1 Connected Connect - 0 + 0x0 @@ -12630,12 +12859,12 @@ POSSIBILITY OF SUCH DAMAGE. Disconnected Disconnect - 1 + 0x1 Connected Connect - 0 + 0x0 @@ -12663,12 +12892,12 @@ POSSIBILITY OF SUCH DAMAGE. Disconnected Disconnect - 1 + 0x1 Connected Connect - 0 + 0x0 @@ -12696,12 +12925,12 @@ POSSIBILITY OF SUCH DAMAGE. Disconnected Disconnect - 1 + 0x1 Connected Connect - 0 + 0x0 @@ -12826,6 +13055,7 @@ POSSIBILITY OF SUCH DAMAGE. Data pointer 0x000 read-write + 0x00000000 PTR @@ -12840,6 +13070,7 @@ POSSIBILITY OF SUCH DAMAGE. Maximum number of bytes in receive buffer 0x004 read-write + 0x00000000 MAXCNT @@ -12854,6 +13085,7 @@ POSSIBILITY OF SUCH DAMAGE. Number of bytes transferred in the last transaction 0x008 read-only + 0x00000000 AMOUNT @@ -12875,6 +13107,7 @@ POSSIBILITY OF SUCH DAMAGE. Data pointer 0x000 read-write + 0x00000000 PTR @@ -12889,6 +13122,7 @@ POSSIBILITY OF SUCH DAMAGE. Maximum number of bytes in transmit buffer 0x004 read-write + 0x00000000 MAXCNT @@ -12903,6 +13137,7 @@ POSSIBILITY OF SUCH DAMAGE. Number of bytes transferred in the last transaction 0x008 read-only + 0x00000000 AMOUNT @@ -12918,6 +13153,7 @@ POSSIBILITY OF SUCH DAMAGE. Configuration of parity and hardware flow control 0x56C read-write + 0x00000000 HWFC @@ -12928,12 +13164,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Disabled - 0 + 0x0 Enabled Enabled - 1 + 0x1 @@ -12964,12 +13200,12 @@ POSSIBILITY OF SUCH DAMAGE. One One stop bit - 0 + 0x0 Two Two stop bits - 1 + 0x1 @@ -13416,6 +13652,7 @@ POSSIBILITY OF SUCH DAMAGE. Description collection: Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is configured in CONFIG[n].POLARITY. 0x000 write-only + 0x00000000 TASKS_OUT @@ -13426,7 +13663,7 @@ POSSIBILITY OF SUCH DAMAGE. Trigger Trigger task - 1 + 0x1 @@ -13439,6 +13676,7 @@ POSSIBILITY OF SUCH DAMAGE. Description collection: Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it high. 0x030 write-only + 0x00000000 TASKS_SET @@ -13449,7 +13687,7 @@ POSSIBILITY OF SUCH DAMAGE. Trigger Trigger task - 1 + 0x1 @@ -13462,6 +13700,7 @@ POSSIBILITY OF SUCH DAMAGE. Description collection: Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it low. 0x060 write-only + 0x00000000 TASKS_CLR @@ -13472,7 +13711,7 @@ POSSIBILITY OF SUCH DAMAGE. Trigger Trigger task - 1 + 0x1 @@ -13485,6 +13724,7 @@ POSSIBILITY OF SUCH DAMAGE. Description collection: Subscribe configuration for task OUT[n] 0x080 read-write + 0x00000000 CHIDX @@ -13500,12 +13740,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Disable subscription - 0 + 0x0 Enabled Enable subscription - 1 + 0x1 @@ -13518,6 +13758,7 @@ POSSIBILITY OF SUCH DAMAGE. Description collection: Subscribe configuration for task SET[n] 0x0B0 read-write + 0x00000000 CHIDX @@ -13533,12 +13774,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Disable subscription - 0 + 0x0 Enabled Enable subscription - 1 + 0x1 @@ -13551,6 +13792,7 @@ POSSIBILITY OF SUCH DAMAGE. Description collection: Subscribe configuration for task CLR[n] 0x0E0 read-write + 0x00000000 CHIDX @@ -13566,12 +13808,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Disable subscription - 0 + 0x0 Enabled Enable subscription - 1 + 0x1 @@ -13584,6 +13826,7 @@ POSSIBILITY OF SUCH DAMAGE. Description collection: Event generated from pin specified in CONFIG[n].PSEL 0x100 read-write + 0x00000000 EVENTS_IN @@ -13594,12 +13837,12 @@ POSSIBILITY OF SUCH DAMAGE. NotGenerated Event not generated - 0 + 0x0 Generated Event generated - 1 + 0x1 @@ -13610,6 +13853,7 @@ POSSIBILITY OF SUCH DAMAGE. Event generated from multiple input GPIO pins with SENSE mechanism enabled 0x17C read-write + 0x00000000 EVENTS_PORT @@ -13620,12 +13864,12 @@ POSSIBILITY OF SUCH DAMAGE. NotGenerated Event not generated - 0 + 0x0 Generated Event generated - 1 + 0x1 @@ -13638,6 +13882,7 @@ POSSIBILITY OF SUCH DAMAGE. Description collection: Publish configuration for event IN[n] 0x180 read-write + 0x00000000 CHIDX @@ -13653,12 +13898,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Disable publishing - 0 + 0x0 Enabled Enable publishing - 1 + 0x1 @@ -13669,6 +13914,7 @@ POSSIBILITY OF SUCH DAMAGE. Publish configuration for event PORT 0x1FC read-write + 0x00000000 CHIDX @@ -13684,12 +13930,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Disable publishing - 0 + 0x0 Enabled Enable publishing - 1 + 0x1 @@ -13700,6 +13946,7 @@ POSSIBILITY OF SUCH DAMAGE. Enable interrupt 0x304 read-write + 0x00000000 IN0 @@ -13711,12 +13958,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -13724,7 +13971,7 @@ POSSIBILITY OF SUCH DAMAGE. Set Enable - 1 + 0x1 @@ -13738,12 +13985,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -13751,7 +13998,7 @@ POSSIBILITY OF SUCH DAMAGE. Set Enable - 1 + 0x1 @@ -13765,12 +14012,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -13778,7 +14025,7 @@ POSSIBILITY OF SUCH DAMAGE. Set Enable - 1 + 0x1 @@ -13792,12 +14039,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -13805,7 +14052,7 @@ POSSIBILITY OF SUCH DAMAGE. Set Enable - 1 + 0x1 @@ -13819,12 +14066,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -13832,7 +14079,7 @@ POSSIBILITY OF SUCH DAMAGE. Set Enable - 1 + 0x1 @@ -13846,12 +14093,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -13859,7 +14106,7 @@ POSSIBILITY OF SUCH DAMAGE. Set Enable - 1 + 0x1 @@ -13873,12 +14120,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -13886,7 +14133,7 @@ POSSIBILITY OF SUCH DAMAGE. Set Enable - 1 + 0x1 @@ -13900,12 +14147,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -13913,7 +14160,7 @@ POSSIBILITY OF SUCH DAMAGE. Set Enable - 1 + 0x1 @@ -13927,12 +14174,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -13940,7 +14187,7 @@ POSSIBILITY OF SUCH DAMAGE. Set Enable - 1 + 0x1 @@ -13951,6 +14198,7 @@ POSSIBILITY OF SUCH DAMAGE. Disable interrupt 0x308 read-write + 0x00000000 IN0 @@ -13962,12 +14210,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -13975,7 +14223,7 @@ POSSIBILITY OF SUCH DAMAGE. Clear Disable - 1 + 0x1 @@ -13989,12 +14237,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -14002,7 +14250,7 @@ POSSIBILITY OF SUCH DAMAGE. Clear Disable - 1 + 0x1 @@ -14016,12 +14264,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -14029,7 +14277,7 @@ POSSIBILITY OF SUCH DAMAGE. Clear Disable - 1 + 0x1 @@ -14043,12 +14291,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -14056,7 +14304,7 @@ POSSIBILITY OF SUCH DAMAGE. Clear Disable - 1 + 0x1 @@ -14070,12 +14318,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -14083,7 +14331,7 @@ POSSIBILITY OF SUCH DAMAGE. Clear Disable - 1 + 0x1 @@ -14097,12 +14345,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -14110,7 +14358,7 @@ POSSIBILITY OF SUCH DAMAGE. Clear Disable - 1 + 0x1 @@ -14124,12 +14372,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -14137,7 +14385,7 @@ POSSIBILITY OF SUCH DAMAGE. Clear Disable - 1 + 0x1 @@ -14151,12 +14399,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -14164,7 +14412,7 @@ POSSIBILITY OF SUCH DAMAGE. Clear Disable - 1 + 0x1 @@ -14178,12 +14426,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -14191,7 +14439,7 @@ POSSIBILITY OF SUCH DAMAGE. Clear Disable - 1 + 0x1 @@ -14204,6 +14452,7 @@ POSSIBILITY OF SUCH DAMAGE. Description collection: Configuration for OUT[n], SET[n], and CLR[n] tasks and IN[n] event 0x510 read-write + 0x00000000 MODE @@ -14214,17 +14463,17 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Disabled. Pin specified by PSEL will not be acquired by the GPIOTE module. - 0 + 0x0 Event Event mode - 1 + 0x1 Task Task mode - 3 + 0x3 @@ -14243,22 +14492,22 @@ POSSIBILITY OF SUCH DAMAGE. None Task mode: No effect on pin from OUT[n] task. Event mode: no IN[n] event generated on pin activity. - 0 + 0x0 LoToHi Task mode: Set pin from OUT[n] task. Event mode: Generate IN[n] event when rising edge on pin. - 1 + 0x1 HiToLo Task mode: Clear pin from OUT[n] task. Event mode: Generate IN[n] event when falling edge on pin. - 2 + 0x2 Toggle Task mode: Toggle pin from OUT[n]. Event mode: Generate IN[n] when any change on pin. - 3 + 0x3 @@ -14271,12 +14520,12 @@ POSSIBILITY OF SUCH DAMAGE. Low Task mode: Initial value of pin before task triggering is low - 0 + 0x0 High Task mode: Initial value of pin before task triggering is high - 1 + 0x1 @@ -14308,6 +14557,7 @@ POSSIBILITY OF SUCH DAMAGE. Start the ADC and prepare the result buffer in RAM 0x000 write-only + 0x00000000 TASKS_START @@ -14318,7 +14568,7 @@ POSSIBILITY OF SUCH DAMAGE. Trigger Trigger task - 1 + 0x1 @@ -14329,6 +14579,7 @@ POSSIBILITY OF SUCH DAMAGE. Take one ADC sample, if scan is enabled all channels are sampled 0x004 write-only + 0x00000000 TASKS_SAMPLE @@ -14339,7 +14590,7 @@ POSSIBILITY OF SUCH DAMAGE. Trigger Trigger task - 1 + 0x1 @@ -14350,6 +14601,7 @@ POSSIBILITY OF SUCH DAMAGE. Stop the ADC and terminate any on-going conversion 0x008 write-only + 0x00000000 TASKS_STOP @@ -14360,7 +14612,7 @@ POSSIBILITY OF SUCH DAMAGE. Trigger Trigger task - 1 + 0x1 @@ -14371,6 +14623,7 @@ POSSIBILITY OF SUCH DAMAGE. Starts offset auto-calibration 0x00C write-only + 0x00000000 TASKS_CALIBRATEOFFSET @@ -14381,7 +14634,7 @@ POSSIBILITY OF SUCH DAMAGE. Trigger Trigger task - 1 + 0x1 @@ -14392,6 +14645,7 @@ POSSIBILITY OF SUCH DAMAGE. Subscribe configuration for task START 0x080 read-write + 0x00000000 CHIDX @@ -14407,12 +14661,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Disable subscription - 0 + 0x0 Enabled Enable subscription - 1 + 0x1 @@ -14423,6 +14677,7 @@ POSSIBILITY OF SUCH DAMAGE. Subscribe configuration for task SAMPLE 0x084 read-write + 0x00000000 CHIDX @@ -14438,12 +14693,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Disable subscription - 0 + 0x0 Enabled Enable subscription - 1 + 0x1 @@ -14454,6 +14709,7 @@ POSSIBILITY OF SUCH DAMAGE. Subscribe configuration for task STOP 0x088 read-write + 0x00000000 CHIDX @@ -14469,12 +14725,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Disable subscription - 0 + 0x0 Enabled Enable subscription - 1 + 0x1 @@ -14485,6 +14741,7 @@ POSSIBILITY OF SUCH DAMAGE. Subscribe configuration for task CALIBRATEOFFSET 0x08C read-write + 0x00000000 CHIDX @@ -14500,12 +14757,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Disable subscription - 0 + 0x0 Enabled Enable subscription - 1 + 0x1 @@ -14516,6 +14773,7 @@ POSSIBILITY OF SUCH DAMAGE. The ADC has started 0x100 read-write + 0x00000000 EVENTS_STARTED @@ -14526,12 +14784,12 @@ POSSIBILITY OF SUCH DAMAGE. NotGenerated Event not generated - 0 + 0x0 Generated Event generated - 1 + 0x1 @@ -14542,6 +14800,7 @@ POSSIBILITY OF SUCH DAMAGE. The ADC has filled up the Result buffer 0x104 read-write + 0x00000000 EVENTS_END @@ -14552,12 +14811,12 @@ POSSIBILITY OF SUCH DAMAGE. NotGenerated Event not generated - 0 + 0x0 Generated Event generated - 1 + 0x1 @@ -14568,6 +14827,7 @@ POSSIBILITY OF SUCH DAMAGE. A conversion task has been completed. Depending on the mode, multiple conversions might be needed for a result to be transferred to RAM. 0x108 read-write + 0x00000000 EVENTS_DONE @@ -14578,12 +14838,12 @@ POSSIBILITY OF SUCH DAMAGE. NotGenerated Event not generated - 0 + 0x0 Generated Event generated - 1 + 0x1 @@ -14594,6 +14854,7 @@ POSSIBILITY OF SUCH DAMAGE. A result is ready to get transferred to RAM. 0x10C read-write + 0x00000000 EVENTS_RESULTDONE @@ -14604,12 +14865,12 @@ POSSIBILITY OF SUCH DAMAGE. NotGenerated Event not generated - 0 + 0x0 Generated Event generated - 1 + 0x1 @@ -14620,6 +14881,7 @@ POSSIBILITY OF SUCH DAMAGE. Calibration is complete 0x110 read-write + 0x00000000 EVENTS_CALIBRATEDONE @@ -14630,12 +14892,12 @@ POSSIBILITY OF SUCH DAMAGE. NotGenerated Event not generated - 0 + 0x0 Generated Event generated - 1 + 0x1 @@ -14646,6 +14908,7 @@ POSSIBILITY OF SUCH DAMAGE. The ADC has stopped 0x114 read-write + 0x00000000 EVENTS_STOPPED @@ -14656,12 +14919,12 @@ POSSIBILITY OF SUCH DAMAGE. NotGenerated Event not generated - 0 + 0x0 Generated Event generated - 1 + 0x1 @@ -14680,6 +14943,7 @@ POSSIBILITY OF SUCH DAMAGE. Description cluster: Last results is equal or above CH[n].LIMIT.HIGH 0x000 read-write + 0x00000000 LIMITH @@ -14690,12 +14954,12 @@ POSSIBILITY OF SUCH DAMAGE. NotGenerated Event not generated - 0 + 0x0 Generated Event generated - 1 + 0x1 @@ -14706,6 +14970,7 @@ POSSIBILITY OF SUCH DAMAGE. Description cluster: Last results is equal or below CH[n].LIMIT.LOW 0x004 read-write + 0x00000000 LIMITL @@ -14716,12 +14981,12 @@ POSSIBILITY OF SUCH DAMAGE. NotGenerated Event not generated - 0 + 0x0 Generated Event generated - 1 + 0x1 @@ -14733,6 +14998,7 @@ POSSIBILITY OF SUCH DAMAGE. Publish configuration for event STARTED 0x180 read-write + 0x00000000 CHIDX @@ -14748,12 +15014,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Disable publishing - 0 + 0x0 Enabled Enable publishing - 1 + 0x1 @@ -14764,6 +15030,7 @@ POSSIBILITY OF SUCH DAMAGE. Publish configuration for event END 0x184 read-write + 0x00000000 CHIDX @@ -14779,12 +15046,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Disable publishing - 0 + 0x0 Enabled Enable publishing - 1 + 0x1 @@ -14795,6 +15062,7 @@ POSSIBILITY OF SUCH DAMAGE. Publish configuration for event DONE 0x188 read-write + 0x00000000 CHIDX @@ -14810,12 +15078,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Disable publishing - 0 + 0x0 Enabled Enable publishing - 1 + 0x1 @@ -14826,6 +15094,7 @@ POSSIBILITY OF SUCH DAMAGE. Publish configuration for event RESULTDONE 0x18C read-write + 0x00000000 CHIDX @@ -14841,12 +15110,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Disable publishing - 0 + 0x0 Enabled Enable publishing - 1 + 0x1 @@ -14857,6 +15126,7 @@ POSSIBILITY OF SUCH DAMAGE. Publish configuration for event CALIBRATEDONE 0x190 read-write + 0x00000000 CHIDX @@ -14872,12 +15142,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Disable publishing - 0 + 0x0 Enabled Enable publishing - 1 + 0x1 @@ -14888,6 +15158,7 @@ POSSIBILITY OF SUCH DAMAGE. Publish configuration for event STOPPED 0x194 read-write + 0x00000000 CHIDX @@ -14903,12 +15174,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Disable publishing - 0 + 0x0 Enabled Enable publishing - 1 + 0x1 @@ -14927,6 +15198,7 @@ POSSIBILITY OF SUCH DAMAGE. Description cluster: Publish configuration for event CH[n].LIMITH 0x000 read-write + 0x00000000 CHIDX @@ -14942,12 +15214,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Disable publishing - 0 + 0x0 Enabled Enable publishing - 1 + 0x1 @@ -14958,6 +15230,7 @@ POSSIBILITY OF SUCH DAMAGE. Description cluster: Publish configuration for event CH[n].LIMITL 0x004 read-write + 0x00000000 CHIDX @@ -14973,12 +15246,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Disable publishing - 0 + 0x0 Enabled Enable publishing - 1 + 0x1 @@ -14990,6 +15263,7 @@ POSSIBILITY OF SUCH DAMAGE. Enable or disable interrupt 0x300 read-write + 0x00000000 STARTED @@ -15000,12 +15274,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Disable - 0 + 0x0 Enabled Enable - 1 + 0x1 @@ -15018,12 +15292,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Disable - 0 + 0x0 Enabled Enable - 1 + 0x1 @@ -15036,12 +15310,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Disable - 0 + 0x0 Enabled Enable - 1 + 0x1 @@ -15054,12 +15328,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Disable - 0 + 0x0 Enabled Enable - 1 + 0x1 @@ -15072,12 +15346,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Disable - 0 + 0x0 Enabled Enable - 1 + 0x1 @@ -15090,12 +15364,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Disable - 0 + 0x0 Enabled Enable - 1 + 0x1 @@ -15108,12 +15382,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Disable - 0 + 0x0 Enabled Enable - 1 + 0x1 @@ -15126,12 +15400,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Disable - 0 + 0x0 Enabled Enable - 1 + 0x1 @@ -15144,12 +15418,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Disable - 0 + 0x0 Enabled Enable - 1 + 0x1 @@ -15162,12 +15436,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Disable - 0 + 0x0 Enabled Enable - 1 + 0x1 @@ -15180,12 +15454,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Disable - 0 + 0x0 Enabled Enable - 1 + 0x1 @@ -15198,12 +15472,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Disable - 0 + 0x0 Enabled Enable - 1 + 0x1 @@ -15216,12 +15490,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Disable - 0 + 0x0 Enabled Enable - 1 + 0x1 @@ -15234,12 +15508,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Disable - 0 + 0x0 Enabled Enable - 1 + 0x1 @@ -15252,12 +15526,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Disable - 0 + 0x0 Enabled Enable - 1 + 0x1 @@ -15270,12 +15544,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Disable - 0 + 0x0 Enabled Enable - 1 + 0x1 @@ -15288,12 +15562,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Disable - 0 + 0x0 Enabled Enable - 1 + 0x1 @@ -15306,12 +15580,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Disable - 0 + 0x0 Enabled Enable - 1 + 0x1 @@ -15324,12 +15598,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Disable - 0 + 0x0 Enabled Enable - 1 + 0x1 @@ -15342,12 +15616,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Disable - 0 + 0x0 Enabled Enable - 1 + 0x1 @@ -15360,12 +15634,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Disable - 0 + 0x0 Enabled Enable - 1 + 0x1 @@ -15378,12 +15652,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Disable - 0 + 0x0 Enabled Enable - 1 + 0x1 @@ -15394,6 +15668,7 @@ POSSIBILITY OF SUCH DAMAGE. Enable interrupt 0x304 read-write + 0x00000000 STARTED @@ -15405,12 +15680,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -15418,7 +15693,7 @@ POSSIBILITY OF SUCH DAMAGE. Set Enable - 1 + 0x1 @@ -15432,12 +15707,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -15445,7 +15720,7 @@ POSSIBILITY OF SUCH DAMAGE. Set Enable - 1 + 0x1 @@ -15459,12 +15734,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -15472,7 +15747,7 @@ POSSIBILITY OF SUCH DAMAGE. Set Enable - 1 + 0x1 @@ -15486,12 +15761,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -15499,7 +15774,7 @@ POSSIBILITY OF SUCH DAMAGE. Set Enable - 1 + 0x1 @@ -15513,12 +15788,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -15526,7 +15801,7 @@ POSSIBILITY OF SUCH DAMAGE. Set Enable - 1 + 0x1 @@ -15540,12 +15815,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -15553,7 +15828,7 @@ POSSIBILITY OF SUCH DAMAGE. Set Enable - 1 + 0x1 @@ -15567,12 +15842,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -15580,7 +15855,7 @@ POSSIBILITY OF SUCH DAMAGE. Set Enable - 1 + 0x1 @@ -15594,12 +15869,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -15607,7 +15882,7 @@ POSSIBILITY OF SUCH DAMAGE. Set Enable - 1 + 0x1 @@ -15621,12 +15896,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -15634,7 +15909,7 @@ POSSIBILITY OF SUCH DAMAGE. Set Enable - 1 + 0x1 @@ -15648,12 +15923,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -15661,7 +15936,7 @@ POSSIBILITY OF SUCH DAMAGE. Set Enable - 1 + 0x1 @@ -15675,12 +15950,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -15688,7 +15963,7 @@ POSSIBILITY OF SUCH DAMAGE. Set Enable - 1 + 0x1 @@ -15702,12 +15977,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -15715,7 +15990,7 @@ POSSIBILITY OF SUCH DAMAGE. Set Enable - 1 + 0x1 @@ -15729,12 +16004,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -15742,7 +16017,7 @@ POSSIBILITY OF SUCH DAMAGE. Set Enable - 1 + 0x1 @@ -15756,12 +16031,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -15769,7 +16044,7 @@ POSSIBILITY OF SUCH DAMAGE. Set Enable - 1 + 0x1 @@ -15783,12 +16058,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -15796,7 +16071,7 @@ POSSIBILITY OF SUCH DAMAGE. Set Enable - 1 + 0x1 @@ -15810,12 +16085,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -15823,7 +16098,7 @@ POSSIBILITY OF SUCH DAMAGE. Set Enable - 1 + 0x1 @@ -15837,12 +16112,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -15850,7 +16125,7 @@ POSSIBILITY OF SUCH DAMAGE. Set Enable - 1 + 0x1 @@ -15864,12 +16139,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -15877,7 +16152,7 @@ POSSIBILITY OF SUCH DAMAGE. Set Enable - 1 + 0x1 @@ -15891,12 +16166,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -15904,7 +16179,7 @@ POSSIBILITY OF SUCH DAMAGE. Set Enable - 1 + 0x1 @@ -15918,12 +16193,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -15931,7 +16206,7 @@ POSSIBILITY OF SUCH DAMAGE. Set Enable - 1 + 0x1 @@ -15945,12 +16220,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -15958,7 +16233,7 @@ POSSIBILITY OF SUCH DAMAGE. Set Enable - 1 + 0x1 @@ -15972,12 +16247,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -15985,7 +16260,7 @@ POSSIBILITY OF SUCH DAMAGE. Set Enable - 1 + 0x1 @@ -15996,6 +16271,7 @@ POSSIBILITY OF SUCH DAMAGE. Disable interrupt 0x308 read-write + 0x00000000 STARTED @@ -16007,12 +16283,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -16020,7 +16296,7 @@ POSSIBILITY OF SUCH DAMAGE. Clear Disable - 1 + 0x1 @@ -16034,12 +16310,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -16047,7 +16323,7 @@ POSSIBILITY OF SUCH DAMAGE. Clear Disable - 1 + 0x1 @@ -16061,12 +16337,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -16074,7 +16350,7 @@ POSSIBILITY OF SUCH DAMAGE. Clear Disable - 1 + 0x1 @@ -16088,12 +16364,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -16101,7 +16377,7 @@ POSSIBILITY OF SUCH DAMAGE. Clear Disable - 1 + 0x1 @@ -16115,12 +16391,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -16128,7 +16404,7 @@ POSSIBILITY OF SUCH DAMAGE. Clear Disable - 1 + 0x1 @@ -16142,12 +16418,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -16155,7 +16431,7 @@ POSSIBILITY OF SUCH DAMAGE. Clear Disable - 1 + 0x1 @@ -16169,12 +16445,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -16182,7 +16458,7 @@ POSSIBILITY OF SUCH DAMAGE. Clear Disable - 1 + 0x1 @@ -16196,12 +16472,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -16209,7 +16485,7 @@ POSSIBILITY OF SUCH DAMAGE. Clear Disable - 1 + 0x1 @@ -16223,12 +16499,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -16236,7 +16512,7 @@ POSSIBILITY OF SUCH DAMAGE. Clear Disable - 1 + 0x1 @@ -16250,12 +16526,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -16263,7 +16539,7 @@ POSSIBILITY OF SUCH DAMAGE. Clear Disable - 1 + 0x1 @@ -16277,12 +16553,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -16290,7 +16566,7 @@ POSSIBILITY OF SUCH DAMAGE. Clear Disable - 1 + 0x1 @@ -16304,12 +16580,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -16317,7 +16593,7 @@ POSSIBILITY OF SUCH DAMAGE. Clear Disable - 1 + 0x1 @@ -16331,12 +16607,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -16344,7 +16620,7 @@ POSSIBILITY OF SUCH DAMAGE. Clear Disable - 1 + 0x1 @@ -16358,12 +16634,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -16371,7 +16647,7 @@ POSSIBILITY OF SUCH DAMAGE. Clear Disable - 1 + 0x1 @@ -16385,12 +16661,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -16398,7 +16674,7 @@ POSSIBILITY OF SUCH DAMAGE. Clear Disable - 1 + 0x1 @@ -16412,12 +16688,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -16425,7 +16701,7 @@ POSSIBILITY OF SUCH DAMAGE. Clear Disable - 1 + 0x1 @@ -16439,12 +16715,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -16452,7 +16728,7 @@ POSSIBILITY OF SUCH DAMAGE. Clear Disable - 1 + 0x1 @@ -16466,12 +16742,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -16479,7 +16755,7 @@ POSSIBILITY OF SUCH DAMAGE. Clear Disable - 1 + 0x1 @@ -16493,12 +16769,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -16506,7 +16782,7 @@ POSSIBILITY OF SUCH DAMAGE. Clear Disable - 1 + 0x1 @@ -16520,12 +16796,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -16533,7 +16809,7 @@ POSSIBILITY OF SUCH DAMAGE. Clear Disable - 1 + 0x1 @@ -16547,12 +16823,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -16560,7 +16836,7 @@ POSSIBILITY OF SUCH DAMAGE. Clear Disable - 1 + 0x1 @@ -16574,12 +16850,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -16587,7 +16863,7 @@ POSSIBILITY OF SUCH DAMAGE. Clear Disable - 1 + 0x1 @@ -16598,6 +16874,7 @@ POSSIBILITY OF SUCH DAMAGE. Status 0x400 read-only + 0x00000000 STATUS @@ -16608,12 +16885,12 @@ POSSIBILITY OF SUCH DAMAGE. Ready ADC is ready. No on-going conversion. - 0 + 0x0 Busy ADC is busy. Single conversion in progress. - 1 + 0x1 @@ -16624,6 +16901,7 @@ POSSIBILITY OF SUCH DAMAGE. Enable or disable ADC 0x500 read-write + 0x00000000 ENABLE @@ -16634,12 +16912,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Disable ADC - 0 + 0x0 Enabled Enable ADC - 1 + 0x1 @@ -16669,52 +16947,52 @@ POSSIBILITY OF SUCH DAMAGE. NC Not connected - 0 + 0x00 AnalogInput0 AIN0 - 1 + 0x01 AnalogInput1 AIN1 - 2 + 0x02 AnalogInput2 AIN2 - 3 + 0x03 AnalogInput3 AIN3 - 4 + 0x04 AnalogInput4 AIN4 - 5 + 0x05 AnalogInput5 AIN5 - 6 + 0x06 AnalogInput6 AIN6 - 7 + 0x07 AnalogInput7 AIN7 - 8 + 0x08 VDDGPIO VDD_GPIO - 9 + 0x09 @@ -16736,52 +17014,52 @@ POSSIBILITY OF SUCH DAMAGE. NC Not connected - 0 + 0x00 AnalogInput0 AIN0 - 1 + 0x01 AnalogInput1 AIN1 - 2 + 0x02 AnalogInput2 AIN2 - 3 + 0x03 AnalogInput3 AIN3 - 4 + 0x04 AnalogInput4 AIN4 - 5 + 0x05 AnalogInput5 AIN5 - 6 + 0x06 AnalogInput6 AIN6 - 7 + 0x07 AnalogInput7 AIN7 - 8 + 0x08 VDD_GPIO VDD_GPIO - 9 + 0x09 @@ -16803,22 +17081,22 @@ POSSIBILITY OF SUCH DAMAGE. Bypass Bypass resistor ladder - 0 + 0x0 Pulldown Pull-down to GND - 1 + 0x1 Pullup Pull-up to VDD_GPIO - 2 + 0x2 VDD1_2 Set input at VDD_GPIO/2 - 3 + 0x3 @@ -16831,22 +17109,22 @@ POSSIBILITY OF SUCH DAMAGE. Bypass Bypass resistor ladder - 0 + 0x0 Pulldown Pull-down to GND - 1 + 0x1 Pullup Pull-up to VDD_GPIO - 2 + 0x2 VDD1_2 Set input at VDD_GPIO/2 - 3 + 0x3 @@ -16859,42 +17137,42 @@ POSSIBILITY OF SUCH DAMAGE. Gain1_6 1/6 - 0 + 0x0 Gain1_5 1/5 - 1 + 0x1 Gain1_4 1/4 - 2 + 0x2 Gain1_3 1/3 - 3 + 0x3 Gain1_2 1/2 - 4 + 0x4 Gain1 1 - 5 + 0x5 Gain2 2 - 6 + 0x6 Gain4 4 - 7 + 0x7 @@ -16907,12 +17185,12 @@ POSSIBILITY OF SUCH DAMAGE. Internal Internal reference (0.6 V) - 0 + 0x0 VDD1_4 VDD_GPIO/4 as reference - 1 + 0x1 @@ -16925,32 +17203,32 @@ POSSIBILITY OF SUCH DAMAGE. 3us 3 us - 0 + 0x0 5us 5 us - 1 + 0x1 10us 10 us - 2 + 0x2 15us 15 us - 3 + 0x3 20us 20 us - 4 + 0x4 40us 40 us - 5 + 0x5 @@ -16963,12 +17241,12 @@ POSSIBILITY OF SUCH DAMAGE. SE Single ended, PSELN will be ignored, negative input to ADC shorted to GND - 0 + 0x0 Diff Differential - 1 + 0x1 @@ -16981,12 +17259,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Burst mode is disabled (normal operation) - 0 + 0x0 Enabled Burst mode is enabled. SAADC takes 2^OVERSAMPLE number of samples as fast as it can, and sends the average to Data RAM. - 1 + 0x1 @@ -17030,22 +17308,22 @@ POSSIBILITY OF SUCH DAMAGE. 8bit 8 bit - 0 + 0x0 10bit 10 bit - 1 + 0x1 12bit 12 bit - 2 + 0x2 14bit 14 bit - 3 + 0x3 @@ -17056,6 +17334,7 @@ POSSIBILITY OF SUCH DAMAGE. Oversampling configuration. OVERSAMPLE should not be combined with SCAN. The RESOLUTION is applied before averaging, thus for high OVERSAMPLE a higher RESOLUTION should be used. 0x5F4 read-write + 0x00000000 OVERSAMPLE @@ -17066,47 +17345,47 @@ POSSIBILITY OF SUCH DAMAGE. Bypass Bypass oversampling - 0 + 0x0 Over2x Oversample 2x - 1 + 0x1 Over4x Oversample 4x - 2 + 0x2 Over8x Oversample 8x - 3 + 0x3 Over16x Oversample 16x - 4 + 0x4 Over32x Oversample 32x - 5 + 0x5 Over64x Oversample 64x - 6 + 0x6 Over128x Oversample 128x - 7 + 0x7 Over256x Oversample 256x - 8 + 0x8 @@ -17117,6 +17396,7 @@ POSSIBILITY OF SUCH DAMAGE. Controls normal or continuous sample rate 0x5F8 read-write + 0x00000000 CC @@ -17133,12 +17413,12 @@ POSSIBILITY OF SUCH DAMAGE. Task Rate is controlled from SAMPLE task - 0 + 0x0 Timers Rate is controlled from local timer (use CC to control the rate) - 1 + 0x1 @@ -17155,6 +17435,7 @@ POSSIBILITY OF SUCH DAMAGE. Data pointer 0x000 read-write + 0x00000000 PTR @@ -17169,6 +17450,7 @@ POSSIBILITY OF SUCH DAMAGE. Maximum number of buffer words to transfer 0x004 read-write + 0x00000000 MAXCNT @@ -17183,6 +17465,7 @@ POSSIBILITY OF SUCH DAMAGE. Number of buffer words transferred since last START 0x008 read-only + 0x00000000 AMOUNT @@ -17230,6 +17513,7 @@ POSSIBILITY OF SUCH DAMAGE. Start Timer 0x000 write-only + 0x00000000 TASKS_START @@ -17240,7 +17524,7 @@ POSSIBILITY OF SUCH DAMAGE. Trigger Trigger task - 1 + 0x1 @@ -17251,6 +17535,7 @@ POSSIBILITY OF SUCH DAMAGE. Stop Timer 0x004 write-only + 0x00000000 TASKS_STOP @@ -17261,7 +17546,7 @@ POSSIBILITY OF SUCH DAMAGE. Trigger Trigger task - 1 + 0x1 @@ -17272,6 +17557,7 @@ POSSIBILITY OF SUCH DAMAGE. Increment Timer (Counter mode only) 0x008 write-only + 0x00000000 TASKS_COUNT @@ -17282,7 +17568,7 @@ POSSIBILITY OF SUCH DAMAGE. Trigger Trigger task - 1 + 0x1 @@ -17293,6 +17579,7 @@ POSSIBILITY OF SUCH DAMAGE. Clear time 0x00C write-only + 0x00000000 TASKS_CLEAR @@ -17303,7 +17590,7 @@ POSSIBILITY OF SUCH DAMAGE. Trigger Trigger task - 1 + 0x1 @@ -17314,6 +17601,7 @@ POSSIBILITY OF SUCH DAMAGE. Deprecated register - Shut down timer 0x010 write-only + 0x00000000 TASKS_SHUTDOWN @@ -17324,7 +17612,7 @@ POSSIBILITY OF SUCH DAMAGE. Trigger Trigger task - 1 + 0x1 @@ -17337,6 +17625,7 @@ POSSIBILITY OF SUCH DAMAGE. Description collection: Capture Timer value to CC[n] register 0x040 write-only + 0x00000000 TASKS_CAPTURE @@ -17347,7 +17636,7 @@ POSSIBILITY OF SUCH DAMAGE. Trigger Trigger task - 1 + 0x1 @@ -17358,6 +17647,7 @@ POSSIBILITY OF SUCH DAMAGE. Subscribe configuration for task START 0x080 read-write + 0x00000000 CHIDX @@ -17373,12 +17663,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Disable subscription - 0 + 0x0 Enabled Enable subscription - 1 + 0x1 @@ -17389,6 +17679,7 @@ POSSIBILITY OF SUCH DAMAGE. Subscribe configuration for task STOP 0x084 read-write + 0x00000000 CHIDX @@ -17404,12 +17695,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Disable subscription - 0 + 0x0 Enabled Enable subscription - 1 + 0x1 @@ -17420,6 +17711,7 @@ POSSIBILITY OF SUCH DAMAGE. Subscribe configuration for task COUNT 0x088 read-write + 0x00000000 CHIDX @@ -17435,12 +17727,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Disable subscription - 0 + 0x0 Enabled Enable subscription - 1 + 0x1 @@ -17451,6 +17743,7 @@ POSSIBILITY OF SUCH DAMAGE. Subscribe configuration for task CLEAR 0x08C read-write + 0x00000000 CHIDX @@ -17466,12 +17759,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Disable subscription - 0 + 0x0 Enabled Enable subscription - 1 + 0x1 @@ -17482,6 +17775,7 @@ POSSIBILITY OF SUCH DAMAGE. Deprecated register - Subscribe configuration for task SHUTDOWN 0x090 read-write + 0x00000000 CHIDX @@ -17497,12 +17791,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Disable subscription - 0 + 0x0 Enabled Enable subscription - 1 + 0x1 @@ -17515,6 +17809,7 @@ POSSIBILITY OF SUCH DAMAGE. Description collection: Subscribe configuration for task CAPTURE[n] 0x0C0 read-write + 0x00000000 CHIDX @@ -17530,12 +17825,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Disable subscription - 0 + 0x0 Enabled Enable subscription - 1 + 0x1 @@ -17548,6 +17843,7 @@ POSSIBILITY OF SUCH DAMAGE. Description collection: Compare event on CC[n] match 0x140 read-write + 0x00000000 EVENTS_COMPARE @@ -17558,12 +17854,12 @@ POSSIBILITY OF SUCH DAMAGE. NotGenerated Event not generated - 0 + 0x0 Generated Event generated - 1 + 0x1 @@ -17576,6 +17872,7 @@ POSSIBILITY OF SUCH DAMAGE. Description collection: Publish configuration for event COMPARE[n] 0x1C0 read-write + 0x00000000 CHIDX @@ -17591,12 +17888,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Disable publishing - 0 + 0x0 Enabled Enable publishing - 1 + 0x1 @@ -17607,6 +17904,7 @@ POSSIBILITY OF SUCH DAMAGE. Shortcuts between local events and tasks 0x200 read-write + 0x00000000 COMPARE0_CLEAR @@ -17617,12 +17915,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Disable shortcut - 0 + 0x0 Enabled Enable shortcut - 1 + 0x1 @@ -17635,12 +17933,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Disable shortcut - 0 + 0x0 Enabled Enable shortcut - 1 + 0x1 @@ -17653,12 +17951,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Disable shortcut - 0 + 0x0 Enabled Enable shortcut - 1 + 0x1 @@ -17671,12 +17969,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Disable shortcut - 0 + 0x0 Enabled Enable shortcut - 1 + 0x1 @@ -17689,12 +17987,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Disable shortcut - 0 + 0x0 Enabled Enable shortcut - 1 + 0x1 @@ -17707,12 +18005,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Disable shortcut - 0 + 0x0 Enabled Enable shortcut - 1 + 0x1 @@ -17725,12 +18023,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Disable shortcut - 0 + 0x0 Enabled Enable shortcut - 1 + 0x1 @@ -17743,12 +18041,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Disable shortcut - 0 + 0x0 Enabled Enable shortcut - 1 + 0x1 @@ -17761,12 +18059,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Disable shortcut - 0 + 0x0 Enabled Enable shortcut - 1 + 0x1 @@ -17779,12 +18077,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Disable shortcut - 0 + 0x0 Enabled Enable shortcut - 1 + 0x1 @@ -17797,12 +18095,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Disable shortcut - 0 + 0x0 Enabled Enable shortcut - 1 + 0x1 @@ -17815,12 +18113,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Disable shortcut - 0 + 0x0 Enabled Enable shortcut - 1 + 0x1 @@ -17831,6 +18129,7 @@ POSSIBILITY OF SUCH DAMAGE. Enable interrupt 0x304 read-write + 0x00000000 COMPARE0 @@ -17842,12 +18141,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -17855,7 +18154,7 @@ POSSIBILITY OF SUCH DAMAGE. Set Enable - 1 + 0x1 @@ -17869,12 +18168,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -17882,7 +18181,7 @@ POSSIBILITY OF SUCH DAMAGE. Set Enable - 1 + 0x1 @@ -17896,12 +18195,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -17909,7 +18208,7 @@ POSSIBILITY OF SUCH DAMAGE. Set Enable - 1 + 0x1 @@ -17923,12 +18222,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -17936,7 +18235,7 @@ POSSIBILITY OF SUCH DAMAGE. Set Enable - 1 + 0x1 @@ -17950,12 +18249,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -17963,7 +18262,7 @@ POSSIBILITY OF SUCH DAMAGE. Set Enable - 1 + 0x1 @@ -17977,12 +18276,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -17990,7 +18289,7 @@ POSSIBILITY OF SUCH DAMAGE. Set Enable - 1 + 0x1 @@ -18001,6 +18300,7 @@ POSSIBILITY OF SUCH DAMAGE. Disable interrupt 0x308 read-write + 0x00000000 COMPARE0 @@ -18012,12 +18312,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -18025,7 +18325,7 @@ POSSIBILITY OF SUCH DAMAGE. Clear Disable - 1 + 0x1 @@ -18039,12 +18339,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -18052,7 +18352,7 @@ POSSIBILITY OF SUCH DAMAGE. Clear Disable - 1 + 0x1 @@ -18066,12 +18366,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -18079,7 +18379,7 @@ POSSIBILITY OF SUCH DAMAGE. Clear Disable - 1 + 0x1 @@ -18093,12 +18393,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -18106,7 +18406,7 @@ POSSIBILITY OF SUCH DAMAGE. Clear Disable - 1 + 0x1 @@ -18120,12 +18420,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -18133,7 +18433,7 @@ POSSIBILITY OF SUCH DAMAGE. Clear Disable - 1 + 0x1 @@ -18147,12 +18447,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -18160,7 +18460,7 @@ POSSIBILITY OF SUCH DAMAGE. Clear Disable - 1 + 0x1 @@ -18171,6 +18471,7 @@ POSSIBILITY OF SUCH DAMAGE. Timer mode selection 0x504 read-write + 0x00000000 MODE @@ -18181,17 +18482,17 @@ POSSIBILITY OF SUCH DAMAGE. Timer Select Timer mode - 0 + 0x0 Counter Deprecated enumerator - Select Counter mode - 1 + 0x1 LowPowerCounter Select Low Power Counter mode - 2 + 0x2 @@ -18202,6 +18503,7 @@ POSSIBILITY OF SUCH DAMAGE. Configure the number of bits used by the TIMER 0x508 read-write + 0x00000000 BITMODE @@ -18212,22 +18514,22 @@ POSSIBILITY OF SUCH DAMAGE. 16Bit 16 bit timer bit width - 0 + 0x0 08Bit 8 bit timer bit width - 1 + 0x1 24Bit 24 bit timer bit width - 2 + 0x2 32Bit 32 bit timer bit width - 3 + 0x3 @@ -18255,6 +18557,7 @@ POSSIBILITY OF SUCH DAMAGE. Description collection: Enable one-shot operation for Capture/Compare channel n 0x514 read-write + 0x00000000 ONESHOTEN @@ -18265,12 +18568,12 @@ POSSIBILITY OF SUCH DAMAGE. Disable Disable one-shot operation - 0 + 0x0 Enable Enable one-shot operation - 1 + 0x1 @@ -18283,6 +18586,7 @@ POSSIBILITY OF SUCH DAMAGE. Description collection: Capture/Compare register n 0x540 read-write + 0x00000000 CC @@ -18373,6 +18677,7 @@ POSSIBILITY OF SUCH DAMAGE. Start RTC counter 0x000 write-only + 0x00000000 TASKS_START @@ -18383,7 +18688,7 @@ POSSIBILITY OF SUCH DAMAGE. Trigger Trigger task - 1 + 0x1 @@ -18394,6 +18699,7 @@ POSSIBILITY OF SUCH DAMAGE. Stop RTC counter 0x004 write-only + 0x00000000 TASKS_STOP @@ -18404,7 +18710,7 @@ POSSIBILITY OF SUCH DAMAGE. Trigger Trigger task - 1 + 0x1 @@ -18415,6 +18721,7 @@ POSSIBILITY OF SUCH DAMAGE. Clear RTC counter 0x008 write-only + 0x00000000 TASKS_CLEAR @@ -18425,7 +18732,7 @@ POSSIBILITY OF SUCH DAMAGE. Trigger Trigger task - 1 + 0x1 @@ -18436,6 +18743,7 @@ POSSIBILITY OF SUCH DAMAGE. Set counter to 0xFFFFF0 0x00C write-only + 0x00000000 TASKS_TRIGOVRFLW @@ -18446,7 +18754,7 @@ POSSIBILITY OF SUCH DAMAGE. Trigger Trigger task - 1 + 0x1 @@ -18457,6 +18765,7 @@ POSSIBILITY OF SUCH DAMAGE. Subscribe configuration for task START 0x080 read-write + 0x00000000 CHIDX @@ -18472,12 +18781,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Disable subscription - 0 + 0x0 Enabled Enable subscription - 1 + 0x1 @@ -18488,6 +18797,7 @@ POSSIBILITY OF SUCH DAMAGE. Subscribe configuration for task STOP 0x084 read-write + 0x00000000 CHIDX @@ -18503,12 +18813,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Disable subscription - 0 + 0x0 Enabled Enable subscription - 1 + 0x1 @@ -18519,6 +18829,7 @@ POSSIBILITY OF SUCH DAMAGE. Subscribe configuration for task CLEAR 0x088 read-write + 0x00000000 CHIDX @@ -18534,12 +18845,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Disable subscription - 0 + 0x0 Enabled Enable subscription - 1 + 0x1 @@ -18550,6 +18861,7 @@ POSSIBILITY OF SUCH DAMAGE. Subscribe configuration for task TRIGOVRFLW 0x08C read-write + 0x00000000 CHIDX @@ -18565,12 +18877,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Disable subscription - 0 + 0x0 Enabled Enable subscription - 1 + 0x1 @@ -18581,6 +18893,7 @@ POSSIBILITY OF SUCH DAMAGE. Event on counter increment 0x100 read-write + 0x00000000 EVENTS_TICK @@ -18591,12 +18904,12 @@ POSSIBILITY OF SUCH DAMAGE. NotGenerated Event not generated - 0 + 0x0 Generated Event generated - 1 + 0x1 @@ -18607,6 +18920,7 @@ POSSIBILITY OF SUCH DAMAGE. Event on counter overflow 0x104 read-write + 0x00000000 EVENTS_OVRFLW @@ -18617,12 +18931,12 @@ POSSIBILITY OF SUCH DAMAGE. NotGenerated Event not generated - 0 + 0x0 Generated Event generated - 1 + 0x1 @@ -18635,6 +18949,7 @@ POSSIBILITY OF SUCH DAMAGE. Description collection: Compare event on CC[n] match 0x140 read-write + 0x00000000 EVENTS_COMPARE @@ -18645,12 +18960,12 @@ POSSIBILITY OF SUCH DAMAGE. NotGenerated Event not generated - 0 + 0x0 Generated Event generated - 1 + 0x1 @@ -18661,6 +18976,7 @@ POSSIBILITY OF SUCH DAMAGE. Publish configuration for event TICK 0x180 read-write + 0x00000000 CHIDX @@ -18676,12 +18992,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Disable publishing - 0 + 0x0 Enabled Enable publishing - 1 + 0x1 @@ -18692,6 +19008,7 @@ POSSIBILITY OF SUCH DAMAGE. Publish configuration for event OVRFLW 0x184 read-write + 0x00000000 CHIDX @@ -18707,12 +19024,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Disable publishing - 0 + 0x0 Enabled Enable publishing - 1 + 0x1 @@ -18725,6 +19042,7 @@ POSSIBILITY OF SUCH DAMAGE. Description collection: Publish configuration for event COMPARE[n] 0x1C0 read-write + 0x00000000 CHIDX @@ -18740,12 +19058,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Disable publishing - 0 + 0x0 Enabled Enable publishing - 1 + 0x1 @@ -18756,6 +19074,7 @@ POSSIBILITY OF SUCH DAMAGE. Enable interrupt 0x304 read-write + 0x00000000 TICK @@ -18767,12 +19086,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -18780,7 +19099,7 @@ POSSIBILITY OF SUCH DAMAGE. Set Enable - 1 + 0x1 @@ -18794,12 +19113,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -18807,7 +19126,7 @@ POSSIBILITY OF SUCH DAMAGE. Set Enable - 1 + 0x1 @@ -18821,12 +19140,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -18834,7 +19153,7 @@ POSSIBILITY OF SUCH DAMAGE. Set Enable - 1 + 0x1 @@ -18848,12 +19167,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -18861,7 +19180,7 @@ POSSIBILITY OF SUCH DAMAGE. Set Enable - 1 + 0x1 @@ -18875,12 +19194,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -18888,7 +19207,7 @@ POSSIBILITY OF SUCH DAMAGE. Set Enable - 1 + 0x1 @@ -18902,12 +19221,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -18915,7 +19234,7 @@ POSSIBILITY OF SUCH DAMAGE. Set Enable - 1 + 0x1 @@ -18926,6 +19245,7 @@ POSSIBILITY OF SUCH DAMAGE. Disable interrupt 0x308 read-write + 0x00000000 TICK @@ -18937,12 +19257,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -18950,7 +19270,7 @@ POSSIBILITY OF SUCH DAMAGE. Clear Disable - 1 + 0x1 @@ -18964,12 +19284,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -18977,7 +19297,7 @@ POSSIBILITY OF SUCH DAMAGE. Clear Disable - 1 + 0x1 @@ -18991,12 +19311,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -19004,7 +19324,7 @@ POSSIBILITY OF SUCH DAMAGE. Clear Disable - 1 + 0x1 @@ -19018,12 +19338,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -19031,7 +19351,7 @@ POSSIBILITY OF SUCH DAMAGE. Clear Disable - 1 + 0x1 @@ -19045,12 +19365,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -19058,7 +19378,7 @@ POSSIBILITY OF SUCH DAMAGE. Clear Disable - 1 + 0x1 @@ -19072,12 +19392,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -19085,7 +19405,7 @@ POSSIBILITY OF SUCH DAMAGE. Clear Disable - 1 + 0x1 @@ -19096,6 +19416,7 @@ POSSIBILITY OF SUCH DAMAGE. Enable or disable event routing 0x340 read-write + 0x00000000 TICK @@ -19106,12 +19427,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Disable - 0 + 0x0 Enabled Enable - 1 + 0x1 @@ -19124,12 +19445,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Disable - 0 + 0x0 Enabled Enable - 1 + 0x1 @@ -19142,12 +19463,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Disable - 0 + 0x0 Enabled Enable - 1 + 0x1 @@ -19160,12 +19481,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Disable - 0 + 0x0 Enabled Enable - 1 + 0x1 @@ -19178,12 +19499,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Disable - 0 + 0x0 Enabled Enable - 1 + 0x1 @@ -19196,12 +19517,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Disable - 0 + 0x0 Enabled Enable - 1 + 0x1 @@ -19212,6 +19533,7 @@ POSSIBILITY OF SUCH DAMAGE. Enable event routing 0x344 read-write + 0x00000000 TICK @@ -19223,12 +19545,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -19236,7 +19558,7 @@ POSSIBILITY OF SUCH DAMAGE. Set Enable - 1 + 0x1 @@ -19250,12 +19572,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -19263,7 +19585,7 @@ POSSIBILITY OF SUCH DAMAGE. Set Enable - 1 + 0x1 @@ -19277,12 +19599,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -19290,7 +19612,7 @@ POSSIBILITY OF SUCH DAMAGE. Set Enable - 1 + 0x1 @@ -19304,12 +19626,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -19317,7 +19639,7 @@ POSSIBILITY OF SUCH DAMAGE. Set Enable - 1 + 0x1 @@ -19331,12 +19653,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -19344,7 +19666,7 @@ POSSIBILITY OF SUCH DAMAGE. Set Enable - 1 + 0x1 @@ -19358,12 +19680,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -19371,7 +19693,7 @@ POSSIBILITY OF SUCH DAMAGE. Set Enable - 1 + 0x1 @@ -19382,6 +19704,7 @@ POSSIBILITY OF SUCH DAMAGE. Disable event routing 0x348 read-write + 0x00000000 TICK @@ -19393,12 +19716,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -19406,7 +19729,7 @@ POSSIBILITY OF SUCH DAMAGE. Clear Disable - 1 + 0x1 @@ -19420,12 +19743,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -19433,7 +19756,7 @@ POSSIBILITY OF SUCH DAMAGE. Clear Disable - 1 + 0x1 @@ -19447,12 +19770,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -19460,7 +19783,7 @@ POSSIBILITY OF SUCH DAMAGE. Clear Disable - 1 + 0x1 @@ -19474,12 +19797,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -19487,7 +19810,7 @@ POSSIBILITY OF SUCH DAMAGE. Clear Disable - 1 + 0x1 @@ -19501,12 +19824,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -19514,7 +19837,7 @@ POSSIBILITY OF SUCH DAMAGE. Clear Disable - 1 + 0x1 @@ -19528,12 +19851,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -19541,7 +19864,7 @@ POSSIBILITY OF SUCH DAMAGE. Clear Disable - 1 + 0x1 @@ -19552,6 +19875,7 @@ POSSIBILITY OF SUCH DAMAGE. Current counter value 0x504 read-only + 0x00000000 COUNTER @@ -19566,6 +19890,7 @@ POSSIBILITY OF SUCH DAMAGE. 12-bit prescaler for counter frequency (32768/(PRESCALER+1)). Must be written when RTC is stopped. 0x508 read-write + 0x00000000 PRESCALER @@ -19582,6 +19907,7 @@ POSSIBILITY OF SUCH DAMAGE. Description collection: Compare register n 0x540 read-write + 0x00000000 COMPARE @@ -19632,7 +19958,8 @@ POSSIBILITY OF SUCH DAMAGE. 0x40017000 DPPIC - + + 0 0x1000 @@ -19654,6 +19981,7 @@ POSSIBILITY OF SUCH DAMAGE. Description cluster: Enable channel group n 0x000 write-only + 0x00000000 EN @@ -19664,7 +19992,7 @@ POSSIBILITY OF SUCH DAMAGE. Trigger Trigger task - 1 + 0x1 @@ -19675,6 +20003,7 @@ POSSIBILITY OF SUCH DAMAGE. Description cluster: Disable channel group n 0x004 write-only + 0x00000000 DIS @@ -19685,7 +20014,7 @@ POSSIBILITY OF SUCH DAMAGE. Trigger Trigger task - 1 + 0x1 @@ -19705,6 +20034,7 @@ POSSIBILITY OF SUCH DAMAGE. Description cluster: Subscribe configuration for task CHG[n].EN 0x000 read-write + 0x00000000 CHIDX @@ -19720,12 +20050,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Disable subscription - 0 + 0x0 Enabled Enable subscription - 1 + 0x1 @@ -19736,6 +20066,7 @@ POSSIBILITY OF SUCH DAMAGE. Description cluster: Subscribe configuration for task CHG[n].DIS 0x004 read-write + 0x00000000 CHIDX @@ -19751,12 +20082,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Disable subscription - 0 + 0x0 Enabled Enable subscription - 1 + 0x1 @@ -19768,6 +20099,7 @@ POSSIBILITY OF SUCH DAMAGE. Channel enable register 0x500 read-write + 0x00000000 CH0 @@ -19778,12 +20110,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Disable channel - 0 + 0x0 Enabled Enable channel - 1 + 0x1 @@ -19796,12 +20128,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Disable channel - 0 + 0x0 Enabled Enable channel - 1 + 0x1 @@ -19814,12 +20146,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Disable channel - 0 + 0x0 Enabled Enable channel - 1 + 0x1 @@ -19832,12 +20164,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Disable channel - 0 + 0x0 Enabled Enable channel - 1 + 0x1 @@ -19850,12 +20182,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Disable channel - 0 + 0x0 Enabled Enable channel - 1 + 0x1 @@ -19868,12 +20200,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Disable channel - 0 + 0x0 Enabled Enable channel - 1 + 0x1 @@ -19886,12 +20218,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Disable channel - 0 + 0x0 Enabled Enable channel - 1 + 0x1 @@ -19904,12 +20236,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Disable channel - 0 + 0x0 Enabled Enable channel - 1 + 0x1 @@ -19922,12 +20254,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Disable channel - 0 + 0x0 Enabled Enable channel - 1 + 0x1 @@ -19940,12 +20272,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Disable channel - 0 + 0x0 Enabled Enable channel - 1 + 0x1 @@ -19958,12 +20290,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Disable channel - 0 + 0x0 Enabled Enable channel - 1 + 0x1 @@ -19976,12 +20308,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Disable channel - 0 + 0x0 Enabled Enable channel - 1 + 0x1 @@ -19994,12 +20326,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Disable channel - 0 + 0x0 Enabled Enable channel - 1 + 0x1 @@ -20012,12 +20344,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Disable channel - 0 + 0x0 Enabled Enable channel - 1 + 0x1 @@ -20030,12 +20362,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Disable channel - 0 + 0x0 Enabled Enable channel - 1 + 0x1 @@ -20048,12 +20380,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Disable channel - 0 + 0x0 Enabled Enable channel - 1 + 0x1 @@ -20064,6 +20396,7 @@ POSSIBILITY OF SUCH DAMAGE. Channel enable set register 0x504 read-write + 0x00000000 oneToSet @@ -20076,12 +20409,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Read: Channel disabled - 0 + 0x0 Enabled Read: Channel enabled - 1 + 0x1 @@ -20089,7 +20422,7 @@ POSSIBILITY OF SUCH DAMAGE. Set Write: Enable channel - 1 + 0x1 @@ -20103,12 +20436,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Read: Channel disabled - 0 + 0x0 Enabled Read: Channel enabled - 1 + 0x1 @@ -20116,7 +20449,7 @@ POSSIBILITY OF SUCH DAMAGE. Set Write: Enable channel - 1 + 0x1 @@ -20130,12 +20463,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Read: Channel disabled - 0 + 0x0 Enabled Read: Channel enabled - 1 + 0x1 @@ -20143,7 +20476,7 @@ POSSIBILITY OF SUCH DAMAGE. Set Write: Enable channel - 1 + 0x1 @@ -20157,12 +20490,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Read: Channel disabled - 0 + 0x0 Enabled Read: Channel enabled - 1 + 0x1 @@ -20170,7 +20503,7 @@ POSSIBILITY OF SUCH DAMAGE. Set Write: Enable channel - 1 + 0x1 @@ -20184,12 +20517,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Read: Channel disabled - 0 + 0x0 Enabled Read: Channel enabled - 1 + 0x1 @@ -20197,7 +20530,7 @@ POSSIBILITY OF SUCH DAMAGE. Set Write: Enable channel - 1 + 0x1 @@ -20211,12 +20544,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Read: Channel disabled - 0 + 0x0 Enabled Read: Channel enabled - 1 + 0x1 @@ -20224,7 +20557,7 @@ POSSIBILITY OF SUCH DAMAGE. Set Write: Enable channel - 1 + 0x1 @@ -20238,12 +20571,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Read: Channel disabled - 0 + 0x0 Enabled Read: Channel enabled - 1 + 0x1 @@ -20251,7 +20584,7 @@ POSSIBILITY OF SUCH DAMAGE. Set Write: Enable channel - 1 + 0x1 @@ -20265,12 +20598,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Read: Channel disabled - 0 + 0x0 Enabled Read: Channel enabled - 1 + 0x1 @@ -20278,7 +20611,7 @@ POSSIBILITY OF SUCH DAMAGE. Set Write: Enable channel - 1 + 0x1 @@ -20292,12 +20625,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Read: Channel disabled - 0 + 0x0 Enabled Read: Channel enabled - 1 + 0x1 @@ -20305,7 +20638,7 @@ POSSIBILITY OF SUCH DAMAGE. Set Write: Enable channel - 1 + 0x1 @@ -20319,12 +20652,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Read: Channel disabled - 0 + 0x0 Enabled Read: Channel enabled - 1 + 0x1 @@ -20332,7 +20665,7 @@ POSSIBILITY OF SUCH DAMAGE. Set Write: Enable channel - 1 + 0x1 @@ -20346,12 +20679,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Read: Channel disabled - 0 + 0x0 Enabled Read: Channel enabled - 1 + 0x1 @@ -20359,7 +20692,7 @@ POSSIBILITY OF SUCH DAMAGE. Set Write: Enable channel - 1 + 0x1 @@ -20373,12 +20706,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Read: Channel disabled - 0 + 0x0 Enabled Read: Channel enabled - 1 + 0x1 @@ -20386,7 +20719,7 @@ POSSIBILITY OF SUCH DAMAGE. Set Write: Enable channel - 1 + 0x1 @@ -20400,12 +20733,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Read: Channel disabled - 0 + 0x0 Enabled Read: Channel enabled - 1 + 0x1 @@ -20413,7 +20746,7 @@ POSSIBILITY OF SUCH DAMAGE. Set Write: Enable channel - 1 + 0x1 @@ -20427,12 +20760,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Read: Channel disabled - 0 + 0x0 Enabled Read: Channel enabled - 1 + 0x1 @@ -20440,7 +20773,7 @@ POSSIBILITY OF SUCH DAMAGE. Set Write: Enable channel - 1 + 0x1 @@ -20454,12 +20787,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Read: Channel disabled - 0 + 0x0 Enabled Read: Channel enabled - 1 + 0x1 @@ -20467,7 +20800,7 @@ POSSIBILITY OF SUCH DAMAGE. Set Write: Enable channel - 1 + 0x1 @@ -20481,12 +20814,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Read: Channel disabled - 0 + 0x0 Enabled Read: Channel enabled - 1 + 0x1 @@ -20494,7 +20827,7 @@ POSSIBILITY OF SUCH DAMAGE. Set Write: Enable channel - 1 + 0x1 @@ -20505,6 +20838,7 @@ POSSIBILITY OF SUCH DAMAGE. Channel enable clear register 0x508 read-write + 0x00000000 oneToClear @@ -20517,12 +20851,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Read: Channel disabled - 0 + 0x0 Enabled Read: Channel enabled - 1 + 0x1 @@ -20530,7 +20864,7 @@ POSSIBILITY OF SUCH DAMAGE. Clear Write: Disable channel - 1 + 0x1 @@ -20544,12 +20878,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Read: Channel disabled - 0 + 0x0 Enabled Read: Channel enabled - 1 + 0x1 @@ -20557,7 +20891,7 @@ POSSIBILITY OF SUCH DAMAGE. Clear Write: Disable channel - 1 + 0x1 @@ -20571,12 +20905,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Read: Channel disabled - 0 + 0x0 Enabled Read: Channel enabled - 1 + 0x1 @@ -20584,7 +20918,7 @@ POSSIBILITY OF SUCH DAMAGE. Clear Write: Disable channel - 1 + 0x1 @@ -20598,12 +20932,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Read: Channel disabled - 0 + 0x0 Enabled Read: Channel enabled - 1 + 0x1 @@ -20611,7 +20945,7 @@ POSSIBILITY OF SUCH DAMAGE. Clear Write: Disable channel - 1 + 0x1 @@ -20625,12 +20959,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Read: Channel disabled - 0 + 0x0 Enabled Read: Channel enabled - 1 + 0x1 @@ -20638,7 +20972,7 @@ POSSIBILITY OF SUCH DAMAGE. Clear Write: Disable channel - 1 + 0x1 @@ -20652,12 +20986,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Read: Channel disabled - 0 + 0x0 Enabled Read: Channel enabled - 1 + 0x1 @@ -20665,7 +20999,7 @@ POSSIBILITY OF SUCH DAMAGE. Clear Write: Disable channel - 1 + 0x1 @@ -20679,12 +21013,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Read: Channel disabled - 0 + 0x0 Enabled Read: Channel enabled - 1 + 0x1 @@ -20692,7 +21026,7 @@ POSSIBILITY OF SUCH DAMAGE. Clear Write: Disable channel - 1 + 0x1 @@ -20706,12 +21040,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Read: Channel disabled - 0 + 0x0 Enabled Read: Channel enabled - 1 + 0x1 @@ -20719,7 +21053,7 @@ POSSIBILITY OF SUCH DAMAGE. Clear Write: Disable channel - 1 + 0x1 @@ -20733,12 +21067,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Read: Channel disabled - 0 + 0x0 Enabled Read: Channel enabled - 1 + 0x1 @@ -20746,7 +21080,7 @@ POSSIBILITY OF SUCH DAMAGE. Clear Write: Disable channel - 1 + 0x1 @@ -20760,12 +21094,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Read: Channel disabled - 0 + 0x0 Enabled Read: Channel enabled - 1 + 0x1 @@ -20773,7 +21107,7 @@ POSSIBILITY OF SUCH DAMAGE. Clear Write: Disable channel - 1 + 0x1 @@ -20787,12 +21121,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Read: Channel disabled - 0 + 0x0 Enabled Read: Channel enabled - 1 + 0x1 @@ -20800,7 +21134,7 @@ POSSIBILITY OF SUCH DAMAGE. Clear Write: Disable channel - 1 + 0x1 @@ -20814,12 +21148,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Read: Channel disabled - 0 + 0x0 Enabled Read: Channel enabled - 1 + 0x1 @@ -20827,7 +21161,7 @@ POSSIBILITY OF SUCH DAMAGE. Clear Write: Disable channel - 1 + 0x1 @@ -20841,12 +21175,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Read: Channel disabled - 0 + 0x0 Enabled Read: Channel enabled - 1 + 0x1 @@ -20854,7 +21188,7 @@ POSSIBILITY OF SUCH DAMAGE. Clear Write: Disable channel - 1 + 0x1 @@ -20868,12 +21202,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Read: Channel disabled - 0 + 0x0 Enabled Read: Channel enabled - 1 + 0x1 @@ -20881,7 +21215,7 @@ POSSIBILITY OF SUCH DAMAGE. Clear Write: Disable channel - 1 + 0x1 @@ -20895,12 +21229,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Read: Channel disabled - 0 + 0x0 Enabled Read: Channel enabled - 1 + 0x1 @@ -20908,7 +21242,7 @@ POSSIBILITY OF SUCH DAMAGE. Clear Write: Disable channel - 1 + 0x1 @@ -20922,12 +21256,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Read: Channel disabled - 0 + 0x0 Enabled Read: Channel enabled - 1 + 0x1 @@ -20935,7 +21269,7 @@ POSSIBILITY OF SUCH DAMAGE. Clear Write: Disable channel - 1 + 0x1 @@ -20948,6 +21282,7 @@ POSSIBILITY OF SUCH DAMAGE. Description collection: Channel group n Note: Writes to this register are ignored if either SUBSCRIBE_CHG[n].EN or SUBSCRIBE_CHG[n].DIS is enabled 0x800 read-write + 0x00000000 CH0 @@ -20958,12 +21293,12 @@ POSSIBILITY OF SUCH DAMAGE. Excluded Exclude - 0 + 0x0 Included Include - 1 + 0x1 @@ -20976,12 +21311,12 @@ POSSIBILITY OF SUCH DAMAGE. Excluded Exclude - 0 + 0x0 Included Include - 1 + 0x1 @@ -20994,12 +21329,12 @@ POSSIBILITY OF SUCH DAMAGE. Excluded Exclude - 0 + 0x0 Included Include - 1 + 0x1 @@ -21012,12 +21347,12 @@ POSSIBILITY OF SUCH DAMAGE. Excluded Exclude - 0 + 0x0 Included Include - 1 + 0x1 @@ -21030,12 +21365,12 @@ POSSIBILITY OF SUCH DAMAGE. Excluded Exclude - 0 + 0x0 Included Include - 1 + 0x1 @@ -21048,12 +21383,12 @@ POSSIBILITY OF SUCH DAMAGE. Excluded Exclude - 0 + 0x0 Included Include - 1 + 0x1 @@ -21066,12 +21401,12 @@ POSSIBILITY OF SUCH DAMAGE. Excluded Exclude - 0 + 0x0 Included Include - 1 + 0x1 @@ -21084,12 +21419,12 @@ POSSIBILITY OF SUCH DAMAGE. Excluded Exclude - 0 + 0x0 Included Include - 1 + 0x1 @@ -21102,12 +21437,12 @@ POSSIBILITY OF SUCH DAMAGE. Excluded Exclude - 0 + 0x0 Included Include - 1 + 0x1 @@ -21120,12 +21455,12 @@ POSSIBILITY OF SUCH DAMAGE. Excluded Exclude - 0 + 0x0 Included Include - 1 + 0x1 @@ -21138,12 +21473,12 @@ POSSIBILITY OF SUCH DAMAGE. Excluded Exclude - 0 + 0x0 Included Include - 1 + 0x1 @@ -21156,12 +21491,12 @@ POSSIBILITY OF SUCH DAMAGE. Excluded Exclude - 0 + 0x0 Included Include - 1 + 0x1 @@ -21174,12 +21509,12 @@ POSSIBILITY OF SUCH DAMAGE. Excluded Exclude - 0 + 0x0 Included Include - 1 + 0x1 @@ -21192,12 +21527,12 @@ POSSIBILITY OF SUCH DAMAGE. Excluded Exclude - 0 + 0x0 Included Include - 1 + 0x1 @@ -21210,12 +21545,12 @@ POSSIBILITY OF SUCH DAMAGE. Excluded Exclude - 0 + 0x0 Included Include - 1 + 0x1 @@ -21228,12 +21563,12 @@ POSSIBILITY OF SUCH DAMAGE. Excluded Exclude - 0 + 0x0 Included Include - 1 + 0x1 @@ -21246,7 +21581,8 @@ POSSIBILITY OF SUCH DAMAGE. Distributed programmable peripheral interconnect controller 1 0x50017000 - + + WDT_NS @@ -21272,6 +21608,7 @@ POSSIBILITY OF SUCH DAMAGE. Start the watchdog 0x000 write-only + 0x00000000 TASKS_START @@ -21282,7 +21619,7 @@ POSSIBILITY OF SUCH DAMAGE. Trigger Trigger task - 1 + 0x1 @@ -21293,6 +21630,7 @@ POSSIBILITY OF SUCH DAMAGE. Subscribe configuration for task START 0x080 read-write + 0x00000000 CHIDX @@ -21308,12 +21646,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Disable subscription - 0 + 0x0 Enabled Enable subscription - 1 + 0x1 @@ -21324,6 +21662,7 @@ POSSIBILITY OF SUCH DAMAGE. Watchdog timeout 0x100 read-write + 0x00000000 EVENTS_TIMEOUT @@ -21334,12 +21673,12 @@ POSSIBILITY OF SUCH DAMAGE. NotGenerated Event not generated - 0 + 0x0 Generated Event generated - 1 + 0x1 @@ -21350,6 +21689,7 @@ POSSIBILITY OF SUCH DAMAGE. Publish configuration for event TIMEOUT 0x180 read-write + 0x00000000 CHIDX @@ -21365,12 +21705,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Disable publishing - 0 + 0x0 Enabled Enable publishing - 1 + 0x1 @@ -21381,6 +21721,7 @@ POSSIBILITY OF SUCH DAMAGE. Enable interrupt 0x304 read-write + 0x00000000 TIMEOUT @@ -21392,12 +21733,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -21405,7 +21746,7 @@ POSSIBILITY OF SUCH DAMAGE. Set Enable - 1 + 0x1 @@ -21416,6 +21757,7 @@ POSSIBILITY OF SUCH DAMAGE. Disable interrupt 0x308 read-write + 0x00000000 TIMEOUT @@ -21427,12 +21769,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -21440,7 +21782,7 @@ POSSIBILITY OF SUCH DAMAGE. Clear Disable - 1 + 0x1 @@ -21451,6 +21793,7 @@ POSSIBILITY OF SUCH DAMAGE. Run status 0x400 read-only + 0x00000000 RUNSTATUSWDT @@ -21461,12 +21804,12 @@ POSSIBILITY OF SUCH DAMAGE. NotRunning Watchdog not running - 0 + 0x0 Running Watchdog is running - 1 + 0x1 @@ -21488,12 +21831,12 @@ POSSIBILITY OF SUCH DAMAGE. DisabledOrRequested RR[0] register is not enabled, or are already requesting reload - 0 + 0x0 EnabledAndUnrequested RR[0] register is enabled, and are not yet requesting reload - 1 + 0x1 @@ -21506,12 +21849,12 @@ POSSIBILITY OF SUCH DAMAGE. DisabledOrRequested RR[1] register is not enabled, or are already requesting reload - 0 + 0x0 EnabledAndUnrequested RR[1] register is enabled, and are not yet requesting reload - 1 + 0x1 @@ -21524,12 +21867,12 @@ POSSIBILITY OF SUCH DAMAGE. DisabledOrRequested RR[2] register is not enabled, or are already requesting reload - 0 + 0x0 EnabledAndUnrequested RR[2] register is enabled, and are not yet requesting reload - 1 + 0x1 @@ -21542,12 +21885,12 @@ POSSIBILITY OF SUCH DAMAGE. DisabledOrRequested RR[3] register is not enabled, or are already requesting reload - 0 + 0x0 EnabledAndUnrequested RR[3] register is enabled, and are not yet requesting reload - 1 + 0x1 @@ -21560,12 +21903,12 @@ POSSIBILITY OF SUCH DAMAGE. DisabledOrRequested RR[4] register is not enabled, or are already requesting reload - 0 + 0x0 EnabledAndUnrequested RR[4] register is enabled, and are not yet requesting reload - 1 + 0x1 @@ -21578,12 +21921,12 @@ POSSIBILITY OF SUCH DAMAGE. DisabledOrRequested RR[5] register is not enabled, or are already requesting reload - 0 + 0x0 EnabledAndUnrequested RR[5] register is enabled, and are not yet requesting reload - 1 + 0x1 @@ -21596,12 +21939,12 @@ POSSIBILITY OF SUCH DAMAGE. DisabledOrRequested RR[6] register is not enabled, or are already requesting reload - 0 + 0x0 EnabledAndUnrequested RR[6] register is enabled, and are not yet requesting reload - 1 + 0x1 @@ -21614,12 +21957,12 @@ POSSIBILITY OF SUCH DAMAGE. DisabledOrRequested RR[7] register is not enabled, or are already requesting reload - 0 + 0x0 EnabledAndUnrequested RR[7] register is enabled, and are not yet requesting reload - 1 + 0x1 @@ -21656,12 +21999,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Disable RR[0] register - 0 + 0x0 Enabled Enable RR[0] register - 1 + 0x1 @@ -21674,12 +22017,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Disable RR[1] register - 0 + 0x0 Enabled Enable RR[1] register - 1 + 0x1 @@ -21692,12 +22035,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Disable RR[2] register - 0 + 0x0 Enabled Enable RR[2] register - 1 + 0x1 @@ -21710,12 +22053,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Disable RR[3] register - 0 + 0x0 Enabled Enable RR[3] register - 1 + 0x1 @@ -21728,12 +22071,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Disable RR[4] register - 0 + 0x0 Enabled Enable RR[4] register - 1 + 0x1 @@ -21746,12 +22089,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Disable RR[5] register - 0 + 0x0 Enabled Enable RR[5] register - 1 + 0x1 @@ -21764,12 +22107,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Disable RR[6] register - 0 + 0x0 Enabled Enable RR[6] register - 1 + 0x1 @@ -21782,12 +22125,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Disable RR[7] register - 0 + 0x0 Enabled Enable RR[7] register - 1 + 0x1 @@ -21809,12 +22152,12 @@ POSSIBILITY OF SUCH DAMAGE. Pause Pause watchdog while the CPU is sleeping - 0 + 0x0 Run Keep the watchdog running while the CPU is sleeping - 1 + 0x1 @@ -21827,12 +22170,12 @@ POSSIBILITY OF SUCH DAMAGE. Pause Pause watchdog while the CPU is halted by the debugger - 0 + 0x0 Run Keep the watchdog running while the CPU is halted by the debugger - 1 + 0x1 @@ -21845,6 +22188,7 @@ POSSIBILITY OF SUCH DAMAGE. Description collection: Reload request n 0x600 write-only + 0x00000000 RR @@ -21900,6 +22244,7 @@ POSSIBILITY OF SUCH DAMAGE. Description collection: Trigger n for triggering the corresponding TRIGGERED[n] event 0x000 write-only + 0x00000000 TASKS_TRIGGER @@ -21910,7 +22255,7 @@ POSSIBILITY OF SUCH DAMAGE. Trigger Trigger task - 1 + 0x1 @@ -21923,6 +22268,7 @@ POSSIBILITY OF SUCH DAMAGE. Description collection: Subscribe configuration for task TRIGGER[n] 0x080 read-write + 0x00000000 CHIDX @@ -21938,12 +22284,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Disable subscription - 0 + 0x0 Enabled Enable subscription - 1 + 0x1 @@ -21956,6 +22302,7 @@ POSSIBILITY OF SUCH DAMAGE. Description collection: Event number n generated by triggering the corresponding TRIGGER[n] task 0x100 read-write + 0x00000000 EVENTS_TRIGGERED @@ -21966,12 +22313,12 @@ POSSIBILITY OF SUCH DAMAGE. NotGenerated Event not generated - 0 + 0x0 Generated Event generated - 1 + 0x1 @@ -21984,6 +22331,7 @@ POSSIBILITY OF SUCH DAMAGE. Description collection: Publish configuration for event TRIGGERED[n] 0x180 read-write + 0x00000000 CHIDX @@ -21999,12 +22347,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Disable publishing - 0 + 0x0 Enabled Enable publishing - 1 + 0x1 @@ -22015,6 +22363,7 @@ POSSIBILITY OF SUCH DAMAGE. Enable or disable interrupt 0x300 read-write + 0x00000000 TRIGGERED0 @@ -22025,12 +22374,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Disable - 0 + 0x0 Enabled Enable - 1 + 0x1 @@ -22043,12 +22392,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Disable - 0 + 0x0 Enabled Enable - 1 + 0x1 @@ -22061,12 +22410,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Disable - 0 + 0x0 Enabled Enable - 1 + 0x1 @@ -22079,12 +22428,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Disable - 0 + 0x0 Enabled Enable - 1 + 0x1 @@ -22097,12 +22446,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Disable - 0 + 0x0 Enabled Enable - 1 + 0x1 @@ -22115,12 +22464,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Disable - 0 + 0x0 Enabled Enable - 1 + 0x1 @@ -22133,12 +22482,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Disable - 0 + 0x0 Enabled Enable - 1 + 0x1 @@ -22151,12 +22500,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Disable - 0 + 0x0 Enabled Enable - 1 + 0x1 @@ -22169,12 +22518,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Disable - 0 + 0x0 Enabled Enable - 1 + 0x1 @@ -22187,12 +22536,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Disable - 0 + 0x0 Enabled Enable - 1 + 0x1 @@ -22205,12 +22554,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Disable - 0 + 0x0 Enabled Enable - 1 + 0x1 @@ -22223,12 +22572,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Disable - 0 + 0x0 Enabled Enable - 1 + 0x1 @@ -22241,12 +22590,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Disable - 0 + 0x0 Enabled Enable - 1 + 0x1 @@ -22259,12 +22608,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Disable - 0 + 0x0 Enabled Enable - 1 + 0x1 @@ -22277,12 +22626,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Disable - 0 + 0x0 Enabled Enable - 1 + 0x1 @@ -22295,12 +22644,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Disable - 0 + 0x0 Enabled Enable - 1 + 0x1 @@ -22311,6 +22660,7 @@ POSSIBILITY OF SUCH DAMAGE. Enable interrupt 0x304 read-write + 0x00000000 TRIGGERED0 @@ -22322,12 +22672,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -22335,7 +22685,7 @@ POSSIBILITY OF SUCH DAMAGE. Set Enable - 1 + 0x1 @@ -22349,12 +22699,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -22362,7 +22712,7 @@ POSSIBILITY OF SUCH DAMAGE. Set Enable - 1 + 0x1 @@ -22376,12 +22726,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -22389,7 +22739,7 @@ POSSIBILITY OF SUCH DAMAGE. Set Enable - 1 + 0x1 @@ -22403,12 +22753,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -22416,7 +22766,7 @@ POSSIBILITY OF SUCH DAMAGE. Set Enable - 1 + 0x1 @@ -22430,12 +22780,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -22443,7 +22793,7 @@ POSSIBILITY OF SUCH DAMAGE. Set Enable - 1 + 0x1 @@ -22457,12 +22807,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -22470,7 +22820,7 @@ POSSIBILITY OF SUCH DAMAGE. Set Enable - 1 + 0x1 @@ -22484,12 +22834,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -22497,7 +22847,7 @@ POSSIBILITY OF SUCH DAMAGE. Set Enable - 1 + 0x1 @@ -22511,12 +22861,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -22524,7 +22874,7 @@ POSSIBILITY OF SUCH DAMAGE. Set Enable - 1 + 0x1 @@ -22538,12 +22888,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -22551,7 +22901,7 @@ POSSIBILITY OF SUCH DAMAGE. Set Enable - 1 + 0x1 @@ -22565,12 +22915,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -22578,7 +22928,7 @@ POSSIBILITY OF SUCH DAMAGE. Set Enable - 1 + 0x1 @@ -22592,12 +22942,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -22605,7 +22955,7 @@ POSSIBILITY OF SUCH DAMAGE. Set Enable - 1 + 0x1 @@ -22619,12 +22969,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -22632,7 +22982,7 @@ POSSIBILITY OF SUCH DAMAGE. Set Enable - 1 + 0x1 @@ -22646,12 +22996,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -22659,7 +23009,7 @@ POSSIBILITY OF SUCH DAMAGE. Set Enable - 1 + 0x1 @@ -22673,12 +23023,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -22686,7 +23036,7 @@ POSSIBILITY OF SUCH DAMAGE. Set Enable - 1 + 0x1 @@ -22700,12 +23050,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -22713,7 +23063,7 @@ POSSIBILITY OF SUCH DAMAGE. Set Enable - 1 + 0x1 @@ -22727,12 +23077,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -22740,7 +23090,7 @@ POSSIBILITY OF SUCH DAMAGE. Set Enable - 1 + 0x1 @@ -22751,6 +23101,7 @@ POSSIBILITY OF SUCH DAMAGE. Disable interrupt 0x308 read-write + 0x00000000 TRIGGERED0 @@ -22762,12 +23113,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -22775,7 +23126,7 @@ POSSIBILITY OF SUCH DAMAGE. Clear Disable - 1 + 0x1 @@ -22789,12 +23140,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -22802,7 +23153,7 @@ POSSIBILITY OF SUCH DAMAGE. Clear Disable - 1 + 0x1 @@ -22816,12 +23167,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -22829,7 +23180,7 @@ POSSIBILITY OF SUCH DAMAGE. Clear Disable - 1 + 0x1 @@ -22843,12 +23194,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -22856,7 +23207,7 @@ POSSIBILITY OF SUCH DAMAGE. Clear Disable - 1 + 0x1 @@ -22870,12 +23221,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -22883,7 +23234,7 @@ POSSIBILITY OF SUCH DAMAGE. Clear Disable - 1 + 0x1 @@ -22897,12 +23248,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -22910,7 +23261,7 @@ POSSIBILITY OF SUCH DAMAGE. Clear Disable - 1 + 0x1 @@ -22924,12 +23275,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -22937,7 +23288,7 @@ POSSIBILITY OF SUCH DAMAGE. Clear Disable - 1 + 0x1 @@ -22951,12 +23302,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -22964,7 +23315,7 @@ POSSIBILITY OF SUCH DAMAGE. Clear Disable - 1 + 0x1 @@ -22978,12 +23329,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -22991,7 +23342,7 @@ POSSIBILITY OF SUCH DAMAGE. Clear Disable - 1 + 0x1 @@ -23005,12 +23356,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -23018,7 +23369,7 @@ POSSIBILITY OF SUCH DAMAGE. Clear Disable - 1 + 0x1 @@ -23032,12 +23383,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -23045,7 +23396,7 @@ POSSIBILITY OF SUCH DAMAGE. Clear Disable - 1 + 0x1 @@ -23059,12 +23410,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -23072,7 +23423,7 @@ POSSIBILITY OF SUCH DAMAGE. Clear Disable - 1 + 0x1 @@ -23086,12 +23437,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -23099,7 +23450,7 @@ POSSIBILITY OF SUCH DAMAGE. Clear Disable - 1 + 0x1 @@ -23113,12 +23464,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -23126,7 +23477,7 @@ POSSIBILITY OF SUCH DAMAGE. Clear Disable - 1 + 0x1 @@ -23140,12 +23491,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -23153,7 +23504,7 @@ POSSIBILITY OF SUCH DAMAGE. Clear Disable - 1 + 0x1 @@ -23167,12 +23518,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -23180,7 +23531,7 @@ POSSIBILITY OF SUCH DAMAGE. Clear Disable - 1 + 0x1 @@ -23333,6 +23684,7 @@ POSSIBILITY OF SUCH DAMAGE. Stops PWM pulse generation on all channels at the end of current PWM period, and stops sequence playback 0x004 write-only + 0x00000000 TASKS_STOP @@ -23343,7 +23695,7 @@ POSSIBILITY OF SUCH DAMAGE. Trigger Trigger task - 1 + 0x1 @@ -23356,6 +23708,7 @@ POSSIBILITY OF SUCH DAMAGE. Description collection: Loads the first PWM value on all enabled channels from sequence n, and starts playing that sequence at the rate defined in SEQ[n]REFRESH and/or DECODER.MODE. Causes PWM generation to start if not running. 0x008 write-only + 0x00000000 TASKS_SEQSTART @@ -23366,7 +23719,7 @@ POSSIBILITY OF SUCH DAMAGE. Trigger Trigger task - 1 + 0x1 @@ -23377,6 +23730,7 @@ POSSIBILITY OF SUCH DAMAGE. Steps by one value in the current sequence on all enabled channels if DECODER.MODE=NextStep. Does not cause PWM generation to start if not running. 0x010 write-only + 0x00000000 TASKS_NEXTSTEP @@ -23387,7 +23741,7 @@ POSSIBILITY OF SUCH DAMAGE. Trigger Trigger task - 1 + 0x1 @@ -23398,6 +23752,7 @@ POSSIBILITY OF SUCH DAMAGE. Subscribe configuration for task STOP 0x084 read-write + 0x00000000 CHIDX @@ -23413,12 +23768,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Disable subscription - 0 + 0x0 Enabled Enable subscription - 1 + 0x1 @@ -23431,6 +23786,7 @@ POSSIBILITY OF SUCH DAMAGE. Description collection: Subscribe configuration for task SEQSTART[n] 0x088 read-write + 0x00000000 CHIDX @@ -23446,12 +23802,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Disable subscription - 0 + 0x0 Enabled Enable subscription - 1 + 0x1 @@ -23462,6 +23818,7 @@ POSSIBILITY OF SUCH DAMAGE. Subscribe configuration for task NEXTSTEP 0x090 read-write + 0x00000000 CHIDX @@ -23477,12 +23834,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Disable subscription - 0 + 0x0 Enabled Enable subscription - 1 + 0x1 @@ -23493,6 +23850,7 @@ POSSIBILITY OF SUCH DAMAGE. Response to STOP task, emitted when PWM pulses are no longer generated 0x104 read-write + 0x00000000 EVENTS_STOPPED @@ -23503,12 +23861,12 @@ POSSIBILITY OF SUCH DAMAGE. NotGenerated Event not generated - 0 + 0x0 Generated Event generated - 1 + 0x1 @@ -23521,6 +23879,7 @@ POSSIBILITY OF SUCH DAMAGE. Description collection: First PWM period started on sequence n 0x108 read-write + 0x00000000 EVENTS_SEQSTARTED @@ -23531,12 +23890,12 @@ POSSIBILITY OF SUCH DAMAGE. NotGenerated Event not generated - 0 + 0x0 Generated Event generated - 1 + 0x1 @@ -23549,6 +23908,7 @@ POSSIBILITY OF SUCH DAMAGE. Description collection: Emitted at end of every sequence n, when last value from RAM has been applied to wave counter 0x110 read-write + 0x00000000 EVENTS_SEQEND @@ -23559,12 +23919,12 @@ POSSIBILITY OF SUCH DAMAGE. NotGenerated Event not generated - 0 + 0x0 Generated Event generated - 1 + 0x1 @@ -23575,6 +23935,7 @@ POSSIBILITY OF SUCH DAMAGE. Emitted at the end of each PWM period 0x118 read-write + 0x00000000 EVENTS_PWMPERIODEND @@ -23585,12 +23946,12 @@ POSSIBILITY OF SUCH DAMAGE. NotGenerated Event not generated - 0 + 0x0 Generated Event generated - 1 + 0x1 @@ -23601,6 +23962,7 @@ POSSIBILITY OF SUCH DAMAGE. Concatenated sequences have been played the amount of times defined in LOOP.CNT 0x11C read-write + 0x00000000 EVENTS_LOOPSDONE @@ -23611,12 +23973,12 @@ POSSIBILITY OF SUCH DAMAGE. NotGenerated Event not generated - 0 + 0x0 Generated Event generated - 1 + 0x1 @@ -23627,6 +23989,7 @@ POSSIBILITY OF SUCH DAMAGE. Publish configuration for event STOPPED 0x184 read-write + 0x00000000 CHIDX @@ -23642,12 +24005,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Disable publishing - 0 + 0x0 Enabled Enable publishing - 1 + 0x1 @@ -23660,6 +24023,7 @@ POSSIBILITY OF SUCH DAMAGE. Description collection: Publish configuration for event SEQSTARTED[n] 0x188 read-write + 0x00000000 CHIDX @@ -23675,12 +24039,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Disable publishing - 0 + 0x0 Enabled Enable publishing - 1 + 0x1 @@ -23693,6 +24057,7 @@ POSSIBILITY OF SUCH DAMAGE. Description collection: Publish configuration for event SEQEND[n] 0x190 read-write + 0x00000000 CHIDX @@ -23708,12 +24073,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Disable publishing - 0 + 0x0 Enabled Enable publishing - 1 + 0x1 @@ -23724,6 +24089,7 @@ POSSIBILITY OF SUCH DAMAGE. Publish configuration for event PWMPERIODEND 0x198 read-write + 0x00000000 CHIDX @@ -23739,12 +24105,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Disable publishing - 0 + 0x0 Enabled Enable publishing - 1 + 0x1 @@ -23755,6 +24121,7 @@ POSSIBILITY OF SUCH DAMAGE. Publish configuration for event LOOPSDONE 0x19C read-write + 0x00000000 CHIDX @@ -23770,12 +24137,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Disable publishing - 0 + 0x0 Enabled Enable publishing - 1 + 0x1 @@ -23786,6 +24153,7 @@ POSSIBILITY OF SUCH DAMAGE. Shortcuts between local events and tasks 0x200 read-write + 0x00000000 SEQEND0_STOP @@ -23796,12 +24164,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Disable shortcut - 0 + 0x0 Enabled Enable shortcut - 1 + 0x1 @@ -23814,12 +24182,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Disable shortcut - 0 + 0x0 Enabled Enable shortcut - 1 + 0x1 @@ -23832,12 +24200,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Disable shortcut - 0 + 0x0 Enabled Enable shortcut - 1 + 0x1 @@ -23850,12 +24218,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Disable shortcut - 0 + 0x0 Enabled Enable shortcut - 1 + 0x1 @@ -23868,12 +24236,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Disable shortcut - 0 + 0x0 Enabled Enable shortcut - 1 + 0x1 @@ -23884,6 +24252,7 @@ POSSIBILITY OF SUCH DAMAGE. Enable or disable interrupt 0x300 read-write + 0x00000000 STOPPED @@ -23894,12 +24263,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Disable - 0 + 0x0 Enabled Enable - 1 + 0x1 @@ -23912,12 +24281,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Disable - 0 + 0x0 Enabled Enable - 1 + 0x1 @@ -23930,12 +24299,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Disable - 0 + 0x0 Enabled Enable - 1 + 0x1 @@ -23948,12 +24317,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Disable - 0 + 0x0 Enabled Enable - 1 + 0x1 @@ -23966,12 +24335,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Disable - 0 + 0x0 Enabled Enable - 1 + 0x1 @@ -23984,12 +24353,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Disable - 0 + 0x0 Enabled Enable - 1 + 0x1 @@ -24002,12 +24371,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Disable - 0 + 0x0 Enabled Enable - 1 + 0x1 @@ -24018,6 +24387,7 @@ POSSIBILITY OF SUCH DAMAGE. Enable interrupt 0x304 read-write + 0x00000000 STOPPED @@ -24029,12 +24399,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -24042,7 +24412,7 @@ POSSIBILITY OF SUCH DAMAGE. Set Enable - 1 + 0x1 @@ -24056,12 +24426,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -24069,7 +24439,7 @@ POSSIBILITY OF SUCH DAMAGE. Set Enable - 1 + 0x1 @@ -24083,12 +24453,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -24096,7 +24466,7 @@ POSSIBILITY OF SUCH DAMAGE. Set Enable - 1 + 0x1 @@ -24110,12 +24480,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -24123,7 +24493,7 @@ POSSIBILITY OF SUCH DAMAGE. Set Enable - 1 + 0x1 @@ -24137,12 +24507,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -24150,7 +24520,7 @@ POSSIBILITY OF SUCH DAMAGE. Set Enable - 1 + 0x1 @@ -24164,12 +24534,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -24177,7 +24547,7 @@ POSSIBILITY OF SUCH DAMAGE. Set Enable - 1 + 0x1 @@ -24191,12 +24561,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -24204,7 +24574,7 @@ POSSIBILITY OF SUCH DAMAGE. Set Enable - 1 + 0x1 @@ -24215,6 +24585,7 @@ POSSIBILITY OF SUCH DAMAGE. Disable interrupt 0x308 read-write + 0x00000000 STOPPED @@ -24226,12 +24597,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -24239,7 +24610,7 @@ POSSIBILITY OF SUCH DAMAGE. Clear Disable - 1 + 0x1 @@ -24253,12 +24624,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -24266,7 +24637,7 @@ POSSIBILITY OF SUCH DAMAGE. Clear Disable - 1 + 0x1 @@ -24280,12 +24651,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -24293,7 +24664,7 @@ POSSIBILITY OF SUCH DAMAGE. Clear Disable - 1 + 0x1 @@ -24307,12 +24678,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -24320,7 +24691,7 @@ POSSIBILITY OF SUCH DAMAGE. Clear Disable - 1 + 0x1 @@ -24334,12 +24705,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -24347,7 +24718,7 @@ POSSIBILITY OF SUCH DAMAGE. Clear Disable - 1 + 0x1 @@ -24361,12 +24732,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -24374,7 +24745,7 @@ POSSIBILITY OF SUCH DAMAGE. Clear Disable - 1 + 0x1 @@ -24388,12 +24759,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -24401,7 +24772,7 @@ POSSIBILITY OF SUCH DAMAGE. Clear Disable - 1 + 0x1 @@ -24423,12 +24794,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Disabled - 0 + 0x0 Enabled Enable - 1 + 0x1 @@ -24450,12 +24821,12 @@ POSSIBILITY OF SUCH DAMAGE. Up Up counter, edge-aligned PWM duty cycle - 0 + 0x0 UpAndDown Up and down counter, center-aligned PWM duty cycle - 1 + 0x1 @@ -24492,42 +24863,42 @@ POSSIBILITY OF SUCH DAMAGE. DIV_1 Divide by 1 (16 MHz) - 0 + 0x0 DIV_2 Divide by 2 (8 MHz) - 1 + 0x1 DIV_4 Divide by 4 (4 MHz) - 2 + 0x2 DIV_8 Divide by 8 (2 MHz) - 3 + 0x3 DIV_16 Divide by 16 (1 MHz) - 4 + 0x4 DIV_32 Divide by 32 (500 kHz) - 5 + 0x5 DIV_64 Divide by 64 (250 kHz) - 6 + 0x6 DIV_128 Divide by 128 (125 kHz) - 7 + 0x7 @@ -24549,22 +24920,22 @@ POSSIBILITY OF SUCH DAMAGE. Common 1st half word (16-bit) used in all PWM channels 0..3 - 0 + 0x0 Grouped 1st half word (16-bit) used in channel 0..1; 2nd word in channel 2..3 - 1 + 0x1 Individual 1st half word (16-bit) in ch.0; 2nd in ch.1; ...; 4th in ch.3 - 2 + 0x2 WaveForm 1st half word (16-bit) in ch.0; 2nd in ch.1; ...; 4th in COUNTERTOP - 3 + 0x3 @@ -24577,12 +24948,12 @@ POSSIBILITY OF SUCH DAMAGE. RefreshCount SEQ[n].REFRESH is used to determine loading internal compare registers - 0 + 0x0 NextStep NEXTSTEP task causes a new value to be loaded to internal compare registers - 1 + 0x1 @@ -24604,7 +24975,7 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Looping disabled (stop at the end of the sequence) - 0 + 0x0000 @@ -24649,7 +25020,7 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Sequence is disabled, and shall not be started as it is empty - 0 + 0x0000 @@ -24671,7 +25042,7 @@ POSSIBILITY OF SUCH DAMAGE. Continuous Update every PWM period - 0 + 0x000000 @@ -24723,12 +25094,12 @@ POSSIBILITY OF SUCH DAMAGE. Disconnected Disconnect - 1 + 0x1 Connected Connect - 0 + 0x0 @@ -24838,6 +25209,7 @@ POSSIBILITY OF SUCH DAMAGE. Starts continuous PDM transfer 0x000 write-only + 0x00000000 TASKS_START @@ -24848,7 +25220,7 @@ POSSIBILITY OF SUCH DAMAGE. Trigger Trigger task - 1 + 0x1 @@ -24859,6 +25231,7 @@ POSSIBILITY OF SUCH DAMAGE. Stops PDM transfer 0x004 write-only + 0x00000000 TASKS_STOP @@ -24869,7 +25242,7 @@ POSSIBILITY OF SUCH DAMAGE. Trigger Trigger task - 1 + 0x1 @@ -24880,6 +25253,7 @@ POSSIBILITY OF SUCH DAMAGE. Subscribe configuration for task START 0x080 read-write + 0x00000000 CHIDX @@ -24895,12 +25269,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Disable subscription - 0 + 0x0 Enabled Enable subscription - 1 + 0x1 @@ -24911,6 +25285,7 @@ POSSIBILITY OF SUCH DAMAGE. Subscribe configuration for task STOP 0x084 read-write + 0x00000000 CHIDX @@ -24926,12 +25301,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Disable subscription - 0 + 0x0 Enabled Enable subscription - 1 + 0x1 @@ -24942,6 +25317,7 @@ POSSIBILITY OF SUCH DAMAGE. PDM transfer has started 0x100 read-write + 0x00000000 EVENTS_STARTED @@ -24952,12 +25328,12 @@ POSSIBILITY OF SUCH DAMAGE. NotGenerated Event not generated - 0 + 0x0 Generated Event generated - 1 + 0x1 @@ -24968,6 +25344,7 @@ POSSIBILITY OF SUCH DAMAGE. PDM transfer has finished 0x104 read-write + 0x00000000 EVENTS_STOPPED @@ -24978,12 +25355,12 @@ POSSIBILITY OF SUCH DAMAGE. NotGenerated Event not generated - 0 + 0x0 Generated Event generated - 1 + 0x1 @@ -24994,6 +25371,7 @@ POSSIBILITY OF SUCH DAMAGE. The PDM has written the last sample specified by SAMPLE.MAXCNT (or the last sample after a STOP task has been received) to Data RAM 0x108 read-write + 0x00000000 EVENTS_END @@ -25004,12 +25382,12 @@ POSSIBILITY OF SUCH DAMAGE. NotGenerated Event not generated - 0 + 0x0 Generated Event generated - 1 + 0x1 @@ -25020,6 +25398,7 @@ POSSIBILITY OF SUCH DAMAGE. Publish configuration for event STARTED 0x180 read-write + 0x00000000 CHIDX @@ -25035,12 +25414,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Disable publishing - 0 + 0x0 Enabled Enable publishing - 1 + 0x1 @@ -25051,6 +25430,7 @@ POSSIBILITY OF SUCH DAMAGE. Publish configuration for event STOPPED 0x184 read-write + 0x00000000 CHIDX @@ -25066,12 +25446,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Disable publishing - 0 + 0x0 Enabled Enable publishing - 1 + 0x1 @@ -25082,6 +25462,7 @@ POSSIBILITY OF SUCH DAMAGE. Publish configuration for event END 0x188 read-write + 0x00000000 CHIDX @@ -25097,12 +25478,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Disable publishing - 0 + 0x0 Enabled Enable publishing - 1 + 0x1 @@ -25113,6 +25494,7 @@ POSSIBILITY OF SUCH DAMAGE. Enable or disable interrupt 0x300 read-write + 0x00000000 STARTED @@ -25123,12 +25505,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Disable - 0 + 0x0 Enabled Enable - 1 + 0x1 @@ -25141,12 +25523,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Disable - 0 + 0x0 Enabled Enable - 1 + 0x1 @@ -25159,12 +25541,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Disable - 0 + 0x0 Enabled Enable - 1 + 0x1 @@ -25175,6 +25557,7 @@ POSSIBILITY OF SUCH DAMAGE. Enable interrupt 0x304 read-write + 0x00000000 STARTED @@ -25186,12 +25569,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -25199,7 +25582,7 @@ POSSIBILITY OF SUCH DAMAGE. Set Enable - 1 + 0x1 @@ -25213,12 +25596,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -25226,7 +25609,7 @@ POSSIBILITY OF SUCH DAMAGE. Set Enable - 1 + 0x1 @@ -25240,12 +25623,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -25253,7 +25636,7 @@ POSSIBILITY OF SUCH DAMAGE. Set Enable - 1 + 0x1 @@ -25264,6 +25647,7 @@ POSSIBILITY OF SUCH DAMAGE. Disable interrupt 0x308 read-write + 0x00000000 STARTED @@ -25275,12 +25659,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -25288,7 +25672,7 @@ POSSIBILITY OF SUCH DAMAGE. Clear Disable - 1 + 0x1 @@ -25302,12 +25686,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -25315,7 +25699,7 @@ POSSIBILITY OF SUCH DAMAGE. Clear Disable - 1 + 0x1 @@ -25329,12 +25713,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -25342,7 +25726,7 @@ POSSIBILITY OF SUCH DAMAGE. Clear Disable - 1 + 0x1 @@ -25364,12 +25748,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Disable - 0 + 0x0 Enabled Enable - 1 + 0x1 @@ -25438,12 +25822,12 @@ POSSIBILITY OF SUCH DAMAGE. Stereo Sample and store one pair (left + right) of 16-bit samples per RAM word R=[31:16]; L=[15:0] - 0 + 0x0 Mono Sample and store two successive left samples (16 bits each) per RAM word L1=[31:16]; L0=[15:0] - 1 + 0x1 @@ -25456,12 +25840,12 @@ POSSIBILITY OF SUCH DAMAGE. LeftFalling Left (or mono) is sampled on falling edge of PDM_CLK - 0 + 0x0 LeftRising Left (or mono) is sampled on rising edge of PDM_CLK - 1 + 0x1 @@ -25547,12 +25931,12 @@ POSSIBILITY OF SUCH DAMAGE. Ratio64 Ratio of 64 - 0 + 0x0 Ratio80 Ratio of 80 - 1 + 0x1 @@ -25586,12 +25970,12 @@ POSSIBILITY OF SUCH DAMAGE. Disconnected Disconnect - 1 + 0x1 Connected Connect - 0 + 0x0 @@ -25619,12 +26003,12 @@ POSSIBILITY OF SUCH DAMAGE. Disconnected Disconnect - 1 + 0x1 Connected Connect - 0 + 0x0 @@ -25642,6 +26026,7 @@ POSSIBILITY OF SUCH DAMAGE. RAM address pointer to write samples to with EasyDMA 0x000 read-write + 0x00000000 SAMPLEPTR @@ -25656,6 +26041,7 @@ POSSIBILITY OF SUCH DAMAGE. Number of samples to allocate memory for in EasyDMA mode 0x004 read-write + 0x00000000 BUFFSIZE @@ -25703,6 +26089,7 @@ POSSIBILITY OF SUCH DAMAGE. Starts continuous I2S transfer. Also starts MCK generator when this is enabled. 0x000 write-only + 0x00000000 TASKS_START @@ -25713,7 +26100,7 @@ POSSIBILITY OF SUCH DAMAGE. Trigger Trigger task - 1 + 0x1 @@ -25724,6 +26111,7 @@ POSSIBILITY OF SUCH DAMAGE. Stops I2S transfer. Also stops MCK generator. Triggering this task will cause the STOPPED event to be generated. 0x004 write-only + 0x00000000 TASKS_STOP @@ -25734,7 +26122,7 @@ POSSIBILITY OF SUCH DAMAGE. Trigger Trigger task - 1 + 0x1 @@ -25745,6 +26133,7 @@ POSSIBILITY OF SUCH DAMAGE. Subscribe configuration for task START 0x080 read-write + 0x00000000 CHIDX @@ -25760,12 +26149,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Disable subscription - 0 + 0x0 Enabled Enable subscription - 1 + 0x1 @@ -25776,6 +26165,7 @@ POSSIBILITY OF SUCH DAMAGE. Subscribe configuration for task STOP 0x084 read-write + 0x00000000 CHIDX @@ -25791,12 +26181,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Disable subscription - 0 + 0x0 Enabled Enable subscription - 1 + 0x1 @@ -25808,6 +26198,7 @@ POSSIBILITY OF SUCH DAMAGE. When the I2S module is started and RX is enabled, this event will be generated for every RXTXD.MAXCNT words that are received on the SDIN pin. 0x104 read-write + 0x00000000 EVENTS_RXPTRUPD @@ -25819,12 +26210,12 @@ POSSIBILITY OF SUCH DAMAGE. NotGenerated Event not generated - 0 + 0x0 Generated Event generated - 1 + 0x1 @@ -25835,6 +26226,7 @@ POSSIBILITY OF SUCH DAMAGE. I2S transfer stopped. 0x108 read-write + 0x00000000 EVENTS_STOPPED @@ -25845,12 +26237,12 @@ POSSIBILITY OF SUCH DAMAGE. NotGenerated Event not generated - 0 + 0x0 Generated Event generated - 1 + 0x1 @@ -25862,6 +26254,7 @@ POSSIBILITY OF SUCH DAMAGE. When the I2S module is started and TX is enabled, this event will be generated for every RXTXD.MAXCNT words that are sent on the SDOUT pin. 0x114 read-write + 0x00000000 EVENTS_TXPTRUPD @@ -25873,12 +26266,12 @@ POSSIBILITY OF SUCH DAMAGE. NotGenerated Event not generated - 0 + 0x0 Generated Event generated - 1 + 0x1 @@ -25889,6 +26282,7 @@ POSSIBILITY OF SUCH DAMAGE. Publish configuration for event RXPTRUPD 0x184 read-write + 0x00000000 CHIDX @@ -25904,12 +26298,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Disable publishing - 0 + 0x0 Enabled Enable publishing - 1 + 0x1 @@ -25920,6 +26314,7 @@ POSSIBILITY OF SUCH DAMAGE. Publish configuration for event STOPPED 0x188 read-write + 0x00000000 CHIDX @@ -25935,12 +26330,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Disable publishing - 0 + 0x0 Enabled Enable publishing - 1 + 0x1 @@ -25951,6 +26346,7 @@ POSSIBILITY OF SUCH DAMAGE. Publish configuration for event TXPTRUPD 0x194 read-write + 0x00000000 CHIDX @@ -25966,12 +26362,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Disable publishing - 0 + 0x0 Enabled Enable publishing - 1 + 0x1 @@ -25982,6 +26378,7 @@ POSSIBILITY OF SUCH DAMAGE. Enable or disable interrupt 0x300 read-write + 0x00000000 RXPTRUPD @@ -25992,12 +26389,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Disable - 0 + 0x0 Enabled Enable - 1 + 0x1 @@ -26010,12 +26407,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Disable - 0 + 0x0 Enabled Enable - 1 + 0x1 @@ -26028,12 +26425,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Disable - 0 + 0x0 Enabled Enable - 1 + 0x1 @@ -26044,6 +26441,7 @@ POSSIBILITY OF SUCH DAMAGE. Enable interrupt 0x304 read-write + 0x00000000 RXPTRUPD @@ -26055,12 +26453,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -26068,7 +26466,7 @@ POSSIBILITY OF SUCH DAMAGE. Set Enable - 1 + 0x1 @@ -26082,12 +26480,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -26095,7 +26493,7 @@ POSSIBILITY OF SUCH DAMAGE. Set Enable - 1 + 0x1 @@ -26109,12 +26507,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -26122,7 +26520,7 @@ POSSIBILITY OF SUCH DAMAGE. Set Enable - 1 + 0x1 @@ -26133,6 +26531,7 @@ POSSIBILITY OF SUCH DAMAGE. Disable interrupt 0x308 read-write + 0x00000000 RXPTRUPD @@ -26144,12 +26543,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -26157,7 +26556,7 @@ POSSIBILITY OF SUCH DAMAGE. Clear Disable - 1 + 0x1 @@ -26171,12 +26570,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -26184,7 +26583,7 @@ POSSIBILITY OF SUCH DAMAGE. Clear Disable - 1 + 0x1 @@ -26198,12 +26597,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -26211,7 +26610,7 @@ POSSIBILITY OF SUCH DAMAGE. Clear Disable - 1 + 0x1 @@ -26233,12 +26632,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Disable - 0 + 0x0 Enabled Enable - 1 + 0x1 @@ -26266,12 +26665,12 @@ POSSIBILITY OF SUCH DAMAGE. Master Master mode. SCK and LRCK generated from internal master clcok (MCK) and output on pins defined by PSEL.xxx. - 0 + 0x0 Slave Slave mode. SCK and LRCK generated by external master and received on pins defined by PSEL.xxx - 1 + 0x1 @@ -26293,12 +26692,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Reception disabled and now data will be written to the RXD.PTR address. - 0 + 0x0 Enabled Reception enabled. - 1 + 0x1 @@ -26320,12 +26719,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Transmission disabled and now data will be read from the RXD.TXD address. - 0 + 0x0 Enabled Transmission enabled. - 1 + 0x1 @@ -26347,12 +26746,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Master clock generator disabled and PSEL.MCK not connected(available as GPIO). - 0 + 0x0 Enabled Master clock generator running and MCK output on PSEL.MCK. - 1 + 0x1 @@ -26456,47 +26855,47 @@ POSSIBILITY OF SUCH DAMAGE. 32X LRCK = MCK / 32 - 0 + 0x0 48X LRCK = MCK / 48 - 1 + 0x1 64X LRCK = MCK / 64 - 2 + 0x2 96X LRCK = MCK / 96 - 3 + 0x3 128X LRCK = MCK / 128 - 4 + 0x4 192X LRCK = MCK / 192 - 5 + 0x5 256X LRCK = MCK / 256 - 6 + 0x6 384X LRCK = MCK / 384 - 7 + 0x7 512X LRCK = MCK / 512 - 8 + 0x8 @@ -26518,17 +26917,17 @@ POSSIBILITY OF SUCH DAMAGE. 8Bit 8 bit. - 0 + 0x0 16Bit 16 bit. - 1 + 0x1 24Bit 24 bit. - 2 + 0x2 @@ -26550,12 +26949,12 @@ POSSIBILITY OF SUCH DAMAGE. Left Left-aligned. - 0 + 0x0 Right Right-aligned. - 1 + 0x1 @@ -26577,12 +26976,12 @@ POSSIBILITY OF SUCH DAMAGE. I2S Original I2S format. - 0 + 0x0 Aligned Alternate (left- or right-aligned) format. - 1 + 0x1 @@ -26604,17 +27003,17 @@ POSSIBILITY OF SUCH DAMAGE. Stereo Stereo. - 0 + 0x0 Left Left only. - 1 + 0x1 Right Right only. - 2 + 0x2 @@ -26715,12 +27114,12 @@ POSSIBILITY OF SUCH DAMAGE. Disconnected Disconnect - 1 + 0x1 Connected Connect - 0 + 0x0 @@ -26748,12 +27147,12 @@ POSSIBILITY OF SUCH DAMAGE. Disconnected Disconnect - 1 + 0x1 Connected Connect - 0 + 0x0 @@ -26781,12 +27180,12 @@ POSSIBILITY OF SUCH DAMAGE. Disconnected Disconnect - 1 + 0x1 Connected Connect - 0 + 0x0 @@ -26814,12 +27213,12 @@ POSSIBILITY OF SUCH DAMAGE. Disconnected Disconnect - 1 + 0x1 Connected Connect - 0 + 0x0 @@ -26847,12 +27246,12 @@ POSSIBILITY OF SUCH DAMAGE. Disconnected Disconnect - 1 + 0x1 Connected Connect - 0 + 0x0 @@ -26898,6 +27297,7 @@ POSSIBILITY OF SUCH DAMAGE. Description collection: Trigger events on IPC channel enabled in SEND_CNF[n] 0x000 write-only + 0x00000000 TASKS_SEND @@ -26908,7 +27308,7 @@ POSSIBILITY OF SUCH DAMAGE. Trigger Trigger task - 1 + 0x1 @@ -26921,6 +27321,7 @@ POSSIBILITY OF SUCH DAMAGE. Description collection: Subscribe configuration for task SEND[n] 0x080 read-write + 0x00000000 CHIDX @@ -26936,12 +27337,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Disable subscription - 0 + 0x0 Enabled Enable subscription - 1 + 0x1 @@ -26954,6 +27355,7 @@ POSSIBILITY OF SUCH DAMAGE. Description collection: Event received on one or more of the enabled IPC channels in RECEIVE_CNF[n] 0x100 read-write + 0x00000000 EVENTS_RECEIVE @@ -26964,12 +27366,12 @@ POSSIBILITY OF SUCH DAMAGE. NotGenerated Event not generated - 0 + 0x0 Generated Event generated - 1 + 0x1 @@ -26982,6 +27384,7 @@ POSSIBILITY OF SUCH DAMAGE. Description collection: Publish configuration for event RECEIVE[n] 0x180 read-write + 0x00000000 CHIDX @@ -26997,12 +27400,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Disable publishing - 0 + 0x0 Enabled Enable publishing - 1 + 0x1 @@ -27013,6 +27416,7 @@ POSSIBILITY OF SUCH DAMAGE. Enable or disable interrupt 0x300 read-write + 0x00000000 RECEIVE0 @@ -27023,12 +27427,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Disable - 0 + 0x0 Enabled Enable - 1 + 0x1 @@ -27041,12 +27445,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Disable - 0 + 0x0 Enabled Enable - 1 + 0x1 @@ -27059,12 +27463,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Disable - 0 + 0x0 Enabled Enable - 1 + 0x1 @@ -27077,12 +27481,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Disable - 0 + 0x0 Enabled Enable - 1 + 0x1 @@ -27095,12 +27499,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Disable - 0 + 0x0 Enabled Enable - 1 + 0x1 @@ -27113,12 +27517,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Disable - 0 + 0x0 Enabled Enable - 1 + 0x1 @@ -27131,12 +27535,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Disable - 0 + 0x0 Enabled Enable - 1 + 0x1 @@ -27149,12 +27553,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Disable - 0 + 0x0 Enabled Enable - 1 + 0x1 @@ -27165,6 +27569,7 @@ POSSIBILITY OF SUCH DAMAGE. Enable interrupt 0x304 read-write + 0x00000000 RECEIVE0 @@ -27176,12 +27581,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -27189,7 +27594,7 @@ POSSIBILITY OF SUCH DAMAGE. Set Enable - 1 + 0x1 @@ -27203,12 +27608,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -27216,7 +27621,7 @@ POSSIBILITY OF SUCH DAMAGE. Set Enable - 1 + 0x1 @@ -27230,12 +27635,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -27243,7 +27648,7 @@ POSSIBILITY OF SUCH DAMAGE. Set Enable - 1 + 0x1 @@ -27257,12 +27662,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -27270,7 +27675,7 @@ POSSIBILITY OF SUCH DAMAGE. Set Enable - 1 + 0x1 @@ -27284,12 +27689,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -27297,7 +27702,7 @@ POSSIBILITY OF SUCH DAMAGE. Set Enable - 1 + 0x1 @@ -27311,12 +27716,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -27324,7 +27729,7 @@ POSSIBILITY OF SUCH DAMAGE. Set Enable - 1 + 0x1 @@ -27338,12 +27743,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -27351,7 +27756,7 @@ POSSIBILITY OF SUCH DAMAGE. Set Enable - 1 + 0x1 @@ -27365,12 +27770,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -27378,7 +27783,7 @@ POSSIBILITY OF SUCH DAMAGE. Set Enable - 1 + 0x1 @@ -27389,6 +27794,7 @@ POSSIBILITY OF SUCH DAMAGE. Disable interrupt 0x308 read-write + 0x00000000 RECEIVE0 @@ -27400,12 +27806,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -27413,7 +27819,7 @@ POSSIBILITY OF SUCH DAMAGE. Clear Disable - 1 + 0x1 @@ -27427,12 +27833,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -27440,7 +27846,7 @@ POSSIBILITY OF SUCH DAMAGE. Clear Disable - 1 + 0x1 @@ -27454,12 +27860,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -27467,7 +27873,7 @@ POSSIBILITY OF SUCH DAMAGE. Clear Disable - 1 + 0x1 @@ -27481,12 +27887,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -27494,7 +27900,7 @@ POSSIBILITY OF SUCH DAMAGE. Clear Disable - 1 + 0x1 @@ -27508,12 +27914,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -27521,7 +27927,7 @@ POSSIBILITY OF SUCH DAMAGE. Clear Disable - 1 + 0x1 @@ -27535,12 +27941,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -27548,7 +27954,7 @@ POSSIBILITY OF SUCH DAMAGE. Clear Disable - 1 + 0x1 @@ -27562,12 +27968,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -27575,7 +27981,7 @@ POSSIBILITY OF SUCH DAMAGE. Clear Disable - 1 + 0x1 @@ -27589,12 +27995,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -27602,7 +28008,7 @@ POSSIBILITY OF SUCH DAMAGE. Clear Disable - 1 + 0x1 @@ -27613,6 +28019,7 @@ POSSIBILITY OF SUCH DAMAGE. Pending interrupts 0x30C read-only + 0x00000000 RECEIVE0 @@ -27624,12 +28031,12 @@ POSSIBILITY OF SUCH DAMAGE. NotPending Read: Not pending - 0 + 0x0 Pending Read: Pending - 1 + 0x1 @@ -27643,12 +28050,12 @@ POSSIBILITY OF SUCH DAMAGE. NotPending Read: Not pending - 0 + 0x0 Pending Read: Pending - 1 + 0x1 @@ -27662,12 +28069,12 @@ POSSIBILITY OF SUCH DAMAGE. NotPending Read: Not pending - 0 + 0x0 Pending Read: Pending - 1 + 0x1 @@ -27681,12 +28088,12 @@ POSSIBILITY OF SUCH DAMAGE. NotPending Read: Not pending - 0 + 0x0 Pending Read: Pending - 1 + 0x1 @@ -27700,12 +28107,12 @@ POSSIBILITY OF SUCH DAMAGE. NotPending Read: Not pending - 0 + 0x0 Pending Read: Pending - 1 + 0x1 @@ -27719,12 +28126,12 @@ POSSIBILITY OF SUCH DAMAGE. NotPending Read: Not pending - 0 + 0x0 Pending Read: Pending - 1 + 0x1 @@ -27738,12 +28145,12 @@ POSSIBILITY OF SUCH DAMAGE. NotPending Read: Not pending - 0 + 0x0 Pending Read: Pending - 1 + 0x1 @@ -27757,12 +28164,12 @@ POSSIBILITY OF SUCH DAMAGE. NotPending Read: Not pending - 0 + 0x0 Pending Read: Pending - 1 + 0x1 @@ -27786,12 +28193,12 @@ POSSIBILITY OF SUCH DAMAGE. Disable Disable broadcast - 0 + 0x0 Enable Enable broadcast - 1 + 0x1 @@ -27804,12 +28211,12 @@ POSSIBILITY OF SUCH DAMAGE. Disable Disable broadcast - 0 + 0x0 Enable Enable broadcast - 1 + 0x1 @@ -27822,12 +28229,12 @@ POSSIBILITY OF SUCH DAMAGE. Disable Disable broadcast - 0 + 0x0 Enable Enable broadcast - 1 + 0x1 @@ -27840,12 +28247,12 @@ POSSIBILITY OF SUCH DAMAGE. Disable Disable broadcast - 0 + 0x0 Enable Enable broadcast - 1 + 0x1 @@ -27858,12 +28265,12 @@ POSSIBILITY OF SUCH DAMAGE. Disable Disable broadcast - 0 + 0x0 Enable Enable broadcast - 1 + 0x1 @@ -27876,12 +28283,12 @@ POSSIBILITY OF SUCH DAMAGE. Disable Disable broadcast - 0 + 0x0 Enable Enable broadcast - 1 + 0x1 @@ -27894,12 +28301,12 @@ POSSIBILITY OF SUCH DAMAGE. Disable Disable broadcast - 0 + 0x0 Enable Enable broadcast - 1 + 0x1 @@ -27912,12 +28319,12 @@ POSSIBILITY OF SUCH DAMAGE. Disable Disable broadcast - 0 + 0x0 Enable Enable broadcast - 1 + 0x1 @@ -27941,12 +28348,12 @@ POSSIBILITY OF SUCH DAMAGE. Disable Disable events - 0 + 0x0 Enable Enable events - 1 + 0x1 @@ -27959,12 +28366,12 @@ POSSIBILITY OF SUCH DAMAGE. Disable Disable events - 0 + 0x0 Enable Enable events - 1 + 0x1 @@ -27977,12 +28384,12 @@ POSSIBILITY OF SUCH DAMAGE. Disable Disable events - 0 + 0x0 Enable Enable events - 1 + 0x1 @@ -27995,12 +28402,12 @@ POSSIBILITY OF SUCH DAMAGE. Disable Disable events - 0 + 0x0 Enable Enable events - 1 + 0x1 @@ -28013,12 +28420,12 @@ POSSIBILITY OF SUCH DAMAGE. Disable Disable events - 0 + 0x0 Enable Enable events - 1 + 0x1 @@ -28031,12 +28438,12 @@ POSSIBILITY OF SUCH DAMAGE. Disable Disable events - 0 + 0x0 Enable Enable events - 1 + 0x1 @@ -28049,12 +28456,12 @@ POSSIBILITY OF SUCH DAMAGE. Disable Disable events - 0 + 0x0 Enable Enable events - 1 + 0x1 @@ -28067,12 +28474,12 @@ POSSIBILITY OF SUCH DAMAGE. Disable Disable events - 0 + 0x0 Enable Enable events - 1 + 0x1 @@ -28110,11 +28517,11 @@ POSSIBILITY OF SUCH DAMAGE. FPU_NS - FPU 0 + FPU 0x4002C000 FPU - + 0 0x1000 @@ -28136,17 +28543,6 @@ POSSIBILITY OF SUCH DAMAGE. - - FPU_S - FPU 1 - 0x5002C000 - - - - FPU - 44 - - GPIOTE1_NS GPIO Tasks and Events 1 @@ -28164,7 +28560,8 @@ POSSIBILITY OF SUCH DAMAGE. 0x40039000 APPROTECT - + + 0 0x1000 @@ -28205,14 +28602,15 @@ POSSIBILITY OF SUCH DAMAGE. FORCEPROTECT Software force SECUREAPPROTECT mechanism - 0x004 + 0x000 read-write 0x00000001 + DISABLE FORCEPROTECT - Write 0x1 to force enable SECUREAPPROTECT mechanism, which will remain set until the next reset + Write 0x1 to force enable SECUREAPPROTECT mechanism 9 9 oneToSet @@ -28240,6 +28638,7 @@ POSSIBILITY OF SUCH DAMAGE. 0x000 read-write 0x00000001 + DISABLE @@ -28259,13 +28658,15 @@ POSSIBILITY OF SUCH DAMAGE. FORCEPROTECT Software force APPROTECT mechanism - 0x004 + 0x000 read-write 0x00000001 + DISABLE + FORCEPROTECT - Write 0x1 to force enable APPROTECT mechanism, which will remain set until the next reset + Write 0x1 to force enable APPROTECT mechanism 9 9 oneToSet @@ -28290,7 +28691,8 @@ POSSIBILITY OF SUCH DAMAGE. APPROTECT_NS KMU - + + 0 0x1000 @@ -28308,6 +28710,7 @@ POSSIBILITY OF SUCH DAMAGE. Push a key slot over secure APB 0x0000 write-only + 0x00000000 TASKS_PUSH_KEYSLOT @@ -28318,7 +28721,7 @@ POSSIBILITY OF SUCH DAMAGE. Trigger Trigger task - 1 + 0x1 @@ -28329,6 +28732,7 @@ POSSIBILITY OF SUCH DAMAGE. Key slot successfully pushed over secure APB 0x100 read-write + 0x00000000 EVENTS_KEYSLOT_PUSHED @@ -28339,12 +28743,12 @@ POSSIBILITY OF SUCH DAMAGE. NotGenerated Event not generated - 0 + 0x0 Generated Event generated - 1 + 0x1 @@ -28355,6 +28759,7 @@ POSSIBILITY OF SUCH DAMAGE. Key slot has been revoked and cannot be tasked for selection 0x104 read-write + 0x00000000 EVENTS_KEYSLOT_REVOKED @@ -28365,12 +28770,12 @@ POSSIBILITY OF SUCH DAMAGE. NotGenerated Event not generated - 0 + 0x0 Generated Event generated - 1 + 0x1 @@ -28381,6 +28786,7 @@ POSSIBILITY OF SUCH DAMAGE. No key slot selected, no destination address defined, or error during push operation 0x108 read-write + 0x00000000 EVENTS_KEYSLOT_ERROR @@ -28391,12 +28797,12 @@ POSSIBILITY OF SUCH DAMAGE. NotGenerated Event not generated - 0 + 0x0 Generated Event generated - 1 + 0x1 @@ -28407,6 +28813,7 @@ POSSIBILITY OF SUCH DAMAGE. Enable or disable interrupt 0x300 read-write + 0x00000000 KEYSLOT_PUSHED @@ -28417,12 +28824,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Disable - 0 + 0x0 Enabled Enable - 1 + 0x1 @@ -28435,12 +28842,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Disable - 0 + 0x0 Enabled Enable - 1 + 0x1 @@ -28453,12 +28860,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Disable - 0 + 0x0 Enabled Enable - 1 + 0x1 @@ -28469,6 +28876,7 @@ POSSIBILITY OF SUCH DAMAGE. Enable interrupt 0x304 read-write + 0x00000000 KEYSLOT_PUSHED @@ -28480,12 +28888,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -28493,7 +28901,7 @@ POSSIBILITY OF SUCH DAMAGE. Set Enable - 1 + 0x1 @@ -28507,12 +28915,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -28520,7 +28928,7 @@ POSSIBILITY OF SUCH DAMAGE. Set Enable - 1 + 0x1 @@ -28534,12 +28942,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -28547,7 +28955,7 @@ POSSIBILITY OF SUCH DAMAGE. Set Enable - 1 + 0x1 @@ -28558,6 +28966,7 @@ POSSIBILITY OF SUCH DAMAGE. Disable interrupt 0x308 read-write + 0x00000000 KEYSLOT_PUSHED @@ -28569,12 +28978,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -28582,7 +28991,7 @@ POSSIBILITY OF SUCH DAMAGE. Clear Disable - 1 + 0x1 @@ -28596,12 +29005,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -28609,7 +29018,7 @@ POSSIBILITY OF SUCH DAMAGE. Clear Disable - 1 + 0x1 @@ -28623,12 +29032,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Read: Disabled - 0 + 0x0 Enabled Read: Enabled - 1 + 0x1 @@ -28636,7 +29045,7 @@ POSSIBILITY OF SUCH DAMAGE. Clear Disable - 1 + 0x1 @@ -28647,6 +29056,7 @@ POSSIBILITY OF SUCH DAMAGE. Pending interrupts 0x30C read-only + 0x00000000 KEYSLOT_PUSHED @@ -28658,12 +29068,12 @@ POSSIBILITY OF SUCH DAMAGE. NotPending Read: Not pending - 0 + 0x0 Pending Read: Pending - 1 + 0x1 @@ -28677,12 +29087,12 @@ POSSIBILITY OF SUCH DAMAGE. NotPending Read: Not pending - 0 + 0x0 Pending Read: Pending - 1 + 0x1 @@ -28696,12 +29106,12 @@ POSSIBILITY OF SUCH DAMAGE. NotPending Read: Not pending - 0 + 0x0 Pending Read: Pending - 1 + 0x1 @@ -28723,12 +29133,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled No key slot ID selected by KMU - 0 + 0x0 Enabled Key slot ID successfully selected by KMU - 1 + 0x1 @@ -28741,12 +29151,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled No access violation detected - 0 + 0x0 Enabled Access violation detected and blocked - 1 + 0x1 @@ -28776,7 +29186,8 @@ POSSIBILITY OF SUCH DAMAGE. APPROTECT_NS NVMC - + + 0 0x1000 @@ -28791,6 +29202,7 @@ POSSIBILITY OF SUCH DAMAGE. 0x400 read-only 0x00000001 + READY @@ -28801,12 +29213,12 @@ POSSIBILITY OF SUCH DAMAGE. Busy NVMC is busy (on-going write or erase operation) - 0 + 0x0 Ready NVMC is ready - 1 + 0x1 @@ -28818,6 +29230,7 @@ POSSIBILITY OF SUCH DAMAGE. 0x408 read-only 0x00000001 + READYNEXT @@ -28828,12 +29241,12 @@ POSSIBILITY OF SUCH DAMAGE. Busy NVMC cannot accept any write operation - 0 + 0x0 Ready NVMC is ready - 1 + 0x1 @@ -28844,6 +29257,7 @@ POSSIBILITY OF SUCH DAMAGE. Configuration register 0x504 read-write + 0x00000000 @@ -28855,22 +29269,22 @@ POSSIBILITY OF SUCH DAMAGE. Ren Read only access - 0 + 0x0 Wen Write enabled - 1 + 0x1 Een Erase enabled - 2 + 0x2 PEen Partial erase enabled - 4 + 0x4 @@ -28881,6 +29295,7 @@ POSSIBILITY OF SUCH DAMAGE. Register for erasing all non-volatile user memory 0x50C write-only + 0x00000000 @@ -28892,12 +29307,12 @@ POSSIBILITY OF SUCH DAMAGE. NoOperation No operation - 0 + 0x0 Erase Start chip erase - 1 + 0x1 @@ -28936,12 +29351,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Disable cache. Invalidates all cache entries. - 0 + 0x0 Enabled Enable cache - 1 + 0x1 @@ -28954,12 +29369,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Disable cache profiling - 0 + 0x0 Enabled Enable cache profiling - 1 + 0x1 @@ -28970,6 +29385,7 @@ POSSIBILITY OF SUCH DAMAGE. I-code cache hit counter 0x548 read-write + 0x00000000 @@ -28985,6 +29401,7 @@ POSSIBILITY OF SUCH DAMAGE. I-code cache miss counter 0x54C read-write + 0x00000000 @@ -29000,6 +29417,8 @@ POSSIBILITY OF SUCH DAMAGE. Unspecified 0x584 read-write + 0x00000000 + WEN @@ -29010,17 +29429,17 @@ POSSIBILITY OF SUCH DAMAGE. Ren Read only access - 0 + 0x0 Wen Write enabled - 1 + 0x1 Een Erase enabled - 2 + 0x2 @@ -29031,6 +29450,8 @@ POSSIBILITY OF SUCH DAMAGE. Non-secure APPROTECT enable register 0x588 write-only + 0x00000000 + SET @@ -29041,7 +29462,7 @@ POSSIBILITY OF SUCH DAMAGE. Set Set value - 1 + 0x1 @@ -29067,7 +29488,8 @@ POSSIBILITY OF SUCH DAMAGE. Access Port Protection 1 0x50039000 - + + KMU_S @@ -29075,7 +29497,8 @@ POSSIBILITY OF SUCH DAMAGE. 0x50039000 APPROTECT_S - + + KMU 57 @@ -29087,7 +29510,8 @@ POSSIBILITY OF SUCH DAMAGE. 0x50039000 APPROTECT_S - + + VMC_NS @@ -29128,12 +29552,12 @@ POSSIBILITY OF SUCH DAMAGE. Off Off - 0 + 0x0 On On - 1 + 0x1 @@ -29146,12 +29570,12 @@ POSSIBILITY OF SUCH DAMAGE. Off Off - 0 + 0x0 On On - 1 + 0x1 @@ -29164,12 +29588,12 @@ POSSIBILITY OF SUCH DAMAGE. Off Off - 0 + 0x0 On On - 1 + 0x1 @@ -29182,12 +29606,12 @@ POSSIBILITY OF SUCH DAMAGE. Off Off - 0 + 0x0 On On - 1 + 0x1 @@ -29200,12 +29624,12 @@ POSSIBILITY OF SUCH DAMAGE. Off Off - 0 + 0x0 On On - 1 + 0x1 @@ -29218,12 +29642,12 @@ POSSIBILITY OF SUCH DAMAGE. Off Off - 0 + 0x0 On On - 1 + 0x1 @@ -29236,12 +29660,12 @@ POSSIBILITY OF SUCH DAMAGE. Off Off - 0 + 0x0 On On - 1 + 0x1 @@ -29254,12 +29678,12 @@ POSSIBILITY OF SUCH DAMAGE. Off Off - 0 + 0x0 On On - 1 + 0x1 @@ -29281,7 +29705,7 @@ POSSIBILITY OF SUCH DAMAGE. On On - 1 + 0x1 @@ -29294,7 +29718,7 @@ POSSIBILITY OF SUCH DAMAGE. On On - 1 + 0x1 @@ -29307,7 +29731,7 @@ POSSIBILITY OF SUCH DAMAGE. On On - 1 + 0x1 @@ -29320,7 +29744,7 @@ POSSIBILITY OF SUCH DAMAGE. On On - 1 + 0x1 @@ -29333,7 +29757,7 @@ POSSIBILITY OF SUCH DAMAGE. On On - 1 + 0x1 @@ -29346,7 +29770,7 @@ POSSIBILITY OF SUCH DAMAGE. On On - 1 + 0x1 @@ -29359,7 +29783,7 @@ POSSIBILITY OF SUCH DAMAGE. On On - 1 + 0x1 @@ -29372,7 +29796,7 @@ POSSIBILITY OF SUCH DAMAGE. On On - 1 + 0x1 @@ -29394,7 +29818,7 @@ POSSIBILITY OF SUCH DAMAGE. Off Off - 1 + 0x1 @@ -29407,7 +29831,7 @@ POSSIBILITY OF SUCH DAMAGE. Off Off - 1 + 0x1 @@ -29420,7 +29844,7 @@ POSSIBILITY OF SUCH DAMAGE. Off Off - 1 + 0x1 @@ -29433,7 +29857,7 @@ POSSIBILITY OF SUCH DAMAGE. Off Off - 1 + 0x1 @@ -29446,7 +29870,7 @@ POSSIBILITY OF SUCH DAMAGE. Off Off - 1 + 0x1 @@ -29459,7 +29883,7 @@ POSSIBILITY OF SUCH DAMAGE. Off Off - 1 + 0x1 @@ -29472,7 +29896,7 @@ POSSIBILITY OF SUCH DAMAGE. Off Off - 1 + 0x1 @@ -29485,7 +29909,7 @@ POSSIBILITY OF SUCH DAMAGE. Off Off - 1 + 0x1 @@ -29532,17 +29956,17 @@ POSSIBILITY OF SUCH DAMAGE. K_DR Use device root key K_DR from CRYPTOCELL AO power domain - 0 + 0x0 K_PRTL Use hard-coded RTL key K_PRTL - 1 + 0x1 Session Use provided session key - 2 + 0x2 @@ -29564,12 +29988,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled K_PRTL can be selected for use from register HOST_CRYPTOKEY_SEL - 0 + 0x0 Enabled K_PRTL has been locked until next power-on reset (POR). If K_PRTL is selected anyway, a zeroed key will be used instead. - 1 + 0x1 @@ -29651,12 +30075,12 @@ POSSIBILITY OF SUCH DAMAGE. Debug CC310 operates in debug mode - 0 + 0x0 Secure CC310 operates in secure mode - 2 + 0x2 @@ -29669,12 +30093,12 @@ POSSIBILITY OF SUCH DAMAGE. Invalid Valid LCS not yet retained in the CRYPTOCELL AO power domain - 0 + 0x0 Valid Valid LCS successfully retained in the CRYPTOCELL AO power domain - 1 + 0x1 @@ -29718,12 +30142,12 @@ POSSIBILITY OF SUCH DAMAGE. Disabled CRYPTOCELL subsystem disabled - 0 + 0x0 Enabled CRYPTOCELL subsystem enabled. - 1 + 0x1 @@ -29737,7 +30161,8 @@ POSSIBILITY OF SUCH DAMAGE. 0x40842500 GPIO - + + 0 0x300 @@ -29751,6 +30176,7 @@ POSSIBILITY OF SUCH DAMAGE. Write GPIO port 0x004 read-write + 0x00000000 PIN0 @@ -29761,12 +30187,12 @@ POSSIBILITY OF SUCH DAMAGE. Low Pin driver is low - 0 + 0x0 High Pin driver is high - 1 + 0x1 @@ -29779,12 +30205,12 @@ POSSIBILITY OF SUCH DAMAGE. Low Pin driver is low - 0 + 0x0 High Pin driver is high - 1 + 0x1 @@ -29797,12 +30223,12 @@ POSSIBILITY OF SUCH DAMAGE. Low Pin driver is low - 0 + 0x0 High Pin driver is high - 1 + 0x1 @@ -29815,12 +30241,12 @@ POSSIBILITY OF SUCH DAMAGE. Low Pin driver is low - 0 + 0x0 High Pin driver is high - 1 + 0x1 @@ -29833,12 +30259,12 @@ POSSIBILITY OF SUCH DAMAGE. Low Pin driver is low - 0 + 0x0 High Pin driver is high - 1 + 0x1 @@ -29851,12 +30277,12 @@ POSSIBILITY OF SUCH DAMAGE. Low Pin driver is low - 0 + 0x0 High Pin driver is high - 1 + 0x1 @@ -29869,12 +30295,12 @@ POSSIBILITY OF SUCH DAMAGE. Low Pin driver is low - 0 + 0x0 High Pin driver is high - 1 + 0x1 @@ -29887,12 +30313,12 @@ POSSIBILITY OF SUCH DAMAGE. Low Pin driver is low - 0 + 0x0 High Pin driver is high - 1 + 0x1 @@ -29905,12 +30331,12 @@ POSSIBILITY OF SUCH DAMAGE. Low Pin driver is low - 0 + 0x0 High Pin driver is high - 1 + 0x1 @@ -29923,12 +30349,12 @@ POSSIBILITY OF SUCH DAMAGE. Low Pin driver is low - 0 + 0x0 High Pin driver is high - 1 + 0x1 @@ -29941,12 +30367,12 @@ POSSIBILITY OF SUCH DAMAGE. Low Pin driver is low - 0 + 0x0 High Pin driver is high - 1 + 0x1 @@ -29959,12 +30385,12 @@ POSSIBILITY OF SUCH DAMAGE. Low Pin driver is low - 0 + 0x0 High Pin driver is high - 1 + 0x1 @@ -29977,12 +30403,12 @@ POSSIBILITY OF SUCH DAMAGE. Low Pin driver is low - 0 + 0x0 High Pin driver is high - 1 + 0x1 @@ -29995,12 +30421,12 @@ POSSIBILITY OF SUCH DAMAGE. Low Pin driver is low - 0 + 0x0 High Pin driver is high - 1 + 0x1 @@ -30013,12 +30439,12 @@ POSSIBILITY OF SUCH DAMAGE. Low Pin driver is low - 0 + 0x0 High Pin driver is high - 1 + 0x1 @@ -30031,12 +30457,12 @@ POSSIBILITY OF SUCH DAMAGE. Low Pin driver is low - 0 + 0x0 High Pin driver is high - 1 + 0x1 @@ -30049,12 +30475,12 @@ POSSIBILITY OF SUCH DAMAGE. Low Pin driver is low - 0 + 0x0 High Pin driver is high - 1 + 0x1 @@ -30067,12 +30493,12 @@ POSSIBILITY OF SUCH DAMAGE. Low Pin driver is low - 0 + 0x0 High Pin driver is high - 1 + 0x1 @@ -30085,12 +30511,12 @@ POSSIBILITY OF SUCH DAMAGE. Low Pin driver is low - 0 + 0x0 High Pin driver is high - 1 + 0x1 @@ -30103,12 +30529,12 @@ POSSIBILITY OF SUCH DAMAGE. Low Pin driver is low - 0 + 0x0 High Pin driver is high - 1 + 0x1 @@ -30121,12 +30547,12 @@ POSSIBILITY OF SUCH DAMAGE. Low Pin driver is low - 0 + 0x0 High Pin driver is high - 1 + 0x1 @@ -30139,12 +30565,12 @@ POSSIBILITY OF SUCH DAMAGE. Low Pin driver is low - 0 + 0x0 High Pin driver is high - 1 + 0x1 @@ -30157,12 +30583,12 @@ POSSIBILITY OF SUCH DAMAGE. Low Pin driver is low - 0 + 0x0 High Pin driver is high - 1 + 0x1 @@ -30175,12 +30601,12 @@ POSSIBILITY OF SUCH DAMAGE. Low Pin driver is low - 0 + 0x0 High Pin driver is high - 1 + 0x1 @@ -30193,12 +30619,12 @@ POSSIBILITY OF SUCH DAMAGE. Low Pin driver is low - 0 + 0x0 High Pin driver is high - 1 + 0x1 @@ -30211,12 +30637,12 @@ POSSIBILITY OF SUCH DAMAGE. Low Pin driver is low - 0 + 0x0 High Pin driver is high - 1 + 0x1 @@ -30229,12 +30655,12 @@ POSSIBILITY OF SUCH DAMAGE. Low Pin driver is low - 0 + 0x0 High Pin driver is high - 1 + 0x1 @@ -30247,12 +30673,12 @@ POSSIBILITY OF SUCH DAMAGE. Low Pin driver is low - 0 + 0x0 High Pin driver is high - 1 + 0x1 @@ -30265,12 +30691,12 @@ POSSIBILITY OF SUCH DAMAGE. Low Pin driver is low - 0 + 0x0 High Pin driver is high - 1 + 0x1 @@ -30283,12 +30709,12 @@ POSSIBILITY OF SUCH DAMAGE. Low Pin driver is low - 0 + 0x0 High Pin driver is high - 1 + 0x1 @@ -30301,12 +30727,12 @@ POSSIBILITY OF SUCH DAMAGE. Low Pin driver is low - 0 + 0x0 High Pin driver is high - 1 + 0x1 @@ -30319,12 +30745,12 @@ POSSIBILITY OF SUCH DAMAGE. Low Pin driver is low - 0 + 0x0 High Pin driver is high - 1 + 0x1 @@ -30335,6 +30761,7 @@ POSSIBILITY OF SUCH DAMAGE. Set individual bits in GPIO port 0x008 read-write + 0x00000000 oneToSet @@ -30347,12 +30774,12 @@ POSSIBILITY OF SUCH DAMAGE. Low Read: pin driver is low - 0 + 0x0 High Read: pin driver is high - 1 + 0x1 @@ -30360,7 +30787,7 @@ POSSIBILITY OF SUCH DAMAGE. Set Write: writing a '1' sets the pin high; writing a '0' has no effect - 1 + 0x1 @@ -30374,12 +30801,12 @@ POSSIBILITY OF SUCH DAMAGE. Low Read: pin driver is low - 0 + 0x0 High Read: pin driver is high - 1 + 0x1 @@ -30387,7 +30814,7 @@ POSSIBILITY OF SUCH DAMAGE. Set Write: writing a '1' sets the pin high; writing a '0' has no effect - 1 + 0x1 @@ -30401,12 +30828,12 @@ POSSIBILITY OF SUCH DAMAGE. Low Read: pin driver is low - 0 + 0x0 High Read: pin driver is high - 1 + 0x1 @@ -30414,7 +30841,7 @@ POSSIBILITY OF SUCH DAMAGE. Set Write: writing a '1' sets the pin high; writing a '0' has no effect - 1 + 0x1 @@ -30428,12 +30855,12 @@ POSSIBILITY OF SUCH DAMAGE. Low Read: pin driver is low - 0 + 0x0 High Read: pin driver is high - 1 + 0x1 @@ -30441,7 +30868,7 @@ POSSIBILITY OF SUCH DAMAGE. Set Write: writing a '1' sets the pin high; writing a '0' has no effect - 1 + 0x1 @@ -30455,12 +30882,12 @@ POSSIBILITY OF SUCH DAMAGE. Low Read: pin driver is low - 0 + 0x0 High Read: pin driver is high - 1 + 0x1 @@ -30468,7 +30895,7 @@ POSSIBILITY OF SUCH DAMAGE. Set Write: writing a '1' sets the pin high; writing a '0' has no effect - 1 + 0x1 @@ -30482,12 +30909,12 @@ POSSIBILITY OF SUCH DAMAGE. Low Read: pin driver is low - 0 + 0x0 High Read: pin driver is high - 1 + 0x1 @@ -30495,7 +30922,7 @@ POSSIBILITY OF SUCH DAMAGE. Set Write: writing a '1' sets the pin high; writing a '0' has no effect - 1 + 0x1 @@ -30509,12 +30936,12 @@ POSSIBILITY OF SUCH DAMAGE. Low Read: pin driver is low - 0 + 0x0 High Read: pin driver is high - 1 + 0x1 @@ -30522,7 +30949,7 @@ POSSIBILITY OF SUCH DAMAGE. Set Write: writing a '1' sets the pin high; writing a '0' has no effect - 1 + 0x1 @@ -30536,12 +30963,12 @@ POSSIBILITY OF SUCH DAMAGE. Low Read: pin driver is low - 0 + 0x0 High Read: pin driver is high - 1 + 0x1 @@ -30549,7 +30976,7 @@ POSSIBILITY OF SUCH DAMAGE. Set Write: writing a '1' sets the pin high; writing a '0' has no effect - 1 + 0x1 @@ -30563,12 +30990,12 @@ POSSIBILITY OF SUCH DAMAGE. Low Read: pin driver is low - 0 + 0x0 High Read: pin driver is high - 1 + 0x1 @@ -30576,7 +31003,7 @@ POSSIBILITY OF SUCH DAMAGE. Set Write: writing a '1' sets the pin high; writing a '0' has no effect - 1 + 0x1 @@ -30590,12 +31017,12 @@ POSSIBILITY OF SUCH DAMAGE. Low Read: pin driver is low - 0 + 0x0 High Read: pin driver is high - 1 + 0x1 @@ -30603,7 +31030,7 @@ POSSIBILITY OF SUCH DAMAGE. Set Write: writing a '1' sets the pin high; writing a '0' has no effect - 1 + 0x1 @@ -30617,12 +31044,12 @@ POSSIBILITY OF SUCH DAMAGE. Low Read: pin driver is low - 0 + 0x0 High Read: pin driver is high - 1 + 0x1 @@ -30630,7 +31057,7 @@ POSSIBILITY OF SUCH DAMAGE. Set Write: writing a '1' sets the pin high; writing a '0' has no effect - 1 + 0x1 @@ -30644,12 +31071,12 @@ POSSIBILITY OF SUCH DAMAGE. Low Read: pin driver is low - 0 + 0x0 High Read: pin driver is high - 1 + 0x1 @@ -30657,7 +31084,7 @@ POSSIBILITY OF SUCH DAMAGE. Set Write: writing a '1' sets the pin high; writing a '0' has no effect - 1 + 0x1 @@ -30671,12 +31098,12 @@ POSSIBILITY OF SUCH DAMAGE. Low Read: pin driver is low - 0 + 0x0 High Read: pin driver is high - 1 + 0x1 @@ -30684,7 +31111,7 @@ POSSIBILITY OF SUCH DAMAGE. Set Write: writing a '1' sets the pin high; writing a '0' has no effect - 1 + 0x1 @@ -30698,12 +31125,12 @@ POSSIBILITY OF SUCH DAMAGE. Low Read: pin driver is low - 0 + 0x0 High Read: pin driver is high - 1 + 0x1 @@ -30711,7 +31138,7 @@ POSSIBILITY OF SUCH DAMAGE. Set Write: writing a '1' sets the pin high; writing a '0' has no effect - 1 + 0x1 @@ -30725,12 +31152,12 @@ POSSIBILITY OF SUCH DAMAGE. Low Read: pin driver is low - 0 + 0x0 High Read: pin driver is high - 1 + 0x1 @@ -30738,7 +31165,7 @@ POSSIBILITY OF SUCH DAMAGE. Set Write: writing a '1' sets the pin high; writing a '0' has no effect - 1 + 0x1 @@ -30752,12 +31179,12 @@ POSSIBILITY OF SUCH DAMAGE. Low Read: pin driver is low - 0 + 0x0 High Read: pin driver is high - 1 + 0x1 @@ -30765,7 +31192,7 @@ POSSIBILITY OF SUCH DAMAGE. Set Write: writing a '1' sets the pin high; writing a '0' has no effect - 1 + 0x1 @@ -30779,12 +31206,12 @@ POSSIBILITY OF SUCH DAMAGE. Low Read: pin driver is low - 0 + 0x0 High Read: pin driver is high - 1 + 0x1 @@ -30792,7 +31219,7 @@ POSSIBILITY OF SUCH DAMAGE. Set Write: writing a '1' sets the pin high; writing a '0' has no effect - 1 + 0x1 @@ -30806,12 +31233,12 @@ POSSIBILITY OF SUCH DAMAGE. Low Read: pin driver is low - 0 + 0x0 High Read: pin driver is high - 1 + 0x1 @@ -30819,7 +31246,7 @@ POSSIBILITY OF SUCH DAMAGE. Set Write: writing a '1' sets the pin high; writing a '0' has no effect - 1 + 0x1 @@ -30833,12 +31260,12 @@ POSSIBILITY OF SUCH DAMAGE. Low Read: pin driver is low - 0 + 0x0 High Read: pin driver is high - 1 + 0x1 @@ -30846,7 +31273,7 @@ POSSIBILITY OF SUCH DAMAGE. Set Write: writing a '1' sets the pin high; writing a '0' has no effect - 1 + 0x1 @@ -30860,12 +31287,12 @@ POSSIBILITY OF SUCH DAMAGE. Low Read: pin driver is low - 0 + 0x0 High Read: pin driver is high - 1 + 0x1 @@ -30873,7 +31300,7 @@ POSSIBILITY OF SUCH DAMAGE. Set Write: writing a '1' sets the pin high; writing a '0' has no effect - 1 + 0x1 @@ -30887,12 +31314,12 @@ POSSIBILITY OF SUCH DAMAGE. Low Read: pin driver is low - 0 + 0x0 High Read: pin driver is high - 1 + 0x1 @@ -30900,7 +31327,7 @@ POSSIBILITY OF SUCH DAMAGE. Set Write: writing a '1' sets the pin high; writing a '0' has no effect - 1 + 0x1 @@ -30914,12 +31341,12 @@ POSSIBILITY OF SUCH DAMAGE. Low Read: pin driver is low - 0 + 0x0 High Read: pin driver is high - 1 + 0x1 @@ -30927,7 +31354,7 @@ POSSIBILITY OF SUCH DAMAGE. Set Write: writing a '1' sets the pin high; writing a '0' has no effect - 1 + 0x1 @@ -30941,12 +31368,12 @@ POSSIBILITY OF SUCH DAMAGE. Low Read: pin driver is low - 0 + 0x0 High Read: pin driver is high - 1 + 0x1 @@ -30954,7 +31381,7 @@ POSSIBILITY OF SUCH DAMAGE. Set Write: writing a '1' sets the pin high; writing a '0' has no effect - 1 + 0x1 @@ -30968,12 +31395,12 @@ POSSIBILITY OF SUCH DAMAGE. Low Read: pin driver is low - 0 + 0x0 High Read: pin driver is high - 1 + 0x1 @@ -30981,7 +31408,7 @@ POSSIBILITY OF SUCH DAMAGE. Set Write: writing a '1' sets the pin high; writing a '0' has no effect - 1 + 0x1 @@ -30995,12 +31422,12 @@ POSSIBILITY OF SUCH DAMAGE. Low Read: pin driver is low - 0 + 0x0 High Read: pin driver is high - 1 + 0x1 @@ -31008,7 +31435,7 @@ POSSIBILITY OF SUCH DAMAGE. Set Write: writing a '1' sets the pin high; writing a '0' has no effect - 1 + 0x1 @@ -31022,12 +31449,12 @@ POSSIBILITY OF SUCH DAMAGE. Low Read: pin driver is low - 0 + 0x0 High Read: pin driver is high - 1 + 0x1 @@ -31035,7 +31462,7 @@ POSSIBILITY OF SUCH DAMAGE. Set Write: writing a '1' sets the pin high; writing a '0' has no effect - 1 + 0x1 @@ -31049,12 +31476,12 @@ POSSIBILITY OF SUCH DAMAGE. Low Read: pin driver is low - 0 + 0x0 High Read: pin driver is high - 1 + 0x1 @@ -31062,7 +31489,7 @@ POSSIBILITY OF SUCH DAMAGE. Set Write: writing a '1' sets the pin high; writing a '0' has no effect - 1 + 0x1 @@ -31076,12 +31503,12 @@ POSSIBILITY OF SUCH DAMAGE. Low Read: pin driver is low - 0 + 0x0 High Read: pin driver is high - 1 + 0x1 @@ -31089,7 +31516,7 @@ POSSIBILITY OF SUCH DAMAGE. Set Write: writing a '1' sets the pin high; writing a '0' has no effect - 1 + 0x1 @@ -31103,12 +31530,12 @@ POSSIBILITY OF SUCH DAMAGE. Low Read: pin driver is low - 0 + 0x0 High Read: pin driver is high - 1 + 0x1 @@ -31116,7 +31543,7 @@ POSSIBILITY OF SUCH DAMAGE. Set Write: writing a '1' sets the pin high; writing a '0' has no effect - 1 + 0x1 @@ -31130,12 +31557,12 @@ POSSIBILITY OF SUCH DAMAGE. Low Read: pin driver is low - 0 + 0x0 High Read: pin driver is high - 1 + 0x1 @@ -31143,7 +31570,7 @@ POSSIBILITY OF SUCH DAMAGE. Set Write: writing a '1' sets the pin high; writing a '0' has no effect - 1 + 0x1 @@ -31157,12 +31584,12 @@ POSSIBILITY OF SUCH DAMAGE. Low Read: pin driver is low - 0 + 0x0 High Read: pin driver is high - 1 + 0x1 @@ -31170,7 +31597,7 @@ POSSIBILITY OF SUCH DAMAGE. Set Write: writing a '1' sets the pin high; writing a '0' has no effect - 1 + 0x1 @@ -31184,12 +31611,12 @@ POSSIBILITY OF SUCH DAMAGE. Low Read: pin driver is low - 0 + 0x0 High Read: pin driver is high - 1 + 0x1 @@ -31197,7 +31624,7 @@ POSSIBILITY OF SUCH DAMAGE. Set Write: writing a '1' sets the pin high; writing a '0' has no effect - 1 + 0x1 @@ -31208,6 +31635,7 @@ POSSIBILITY OF SUCH DAMAGE. Clear individual bits in GPIO port 0x00C read-write + 0x00000000 oneToClear @@ -31220,12 +31648,12 @@ POSSIBILITY OF SUCH DAMAGE. Low Read: pin driver is low - 0 + 0x0 High Read: pin driver is high - 1 + 0x1 @@ -31233,7 +31661,7 @@ POSSIBILITY OF SUCH DAMAGE. Clear Write: writing a '1' sets the pin low; writing a '0' has no effect - 1 + 0x1 @@ -31247,12 +31675,12 @@ POSSIBILITY OF SUCH DAMAGE. Low Read: pin driver is low - 0 + 0x0 High Read: pin driver is high - 1 + 0x1 @@ -31260,7 +31688,7 @@ POSSIBILITY OF SUCH DAMAGE. Clear Write: writing a '1' sets the pin low; writing a '0' has no effect - 1 + 0x1 @@ -31274,12 +31702,12 @@ POSSIBILITY OF SUCH DAMAGE. Low Read: pin driver is low - 0 + 0x0 High Read: pin driver is high - 1 + 0x1 @@ -31287,7 +31715,7 @@ POSSIBILITY OF SUCH DAMAGE. Clear Write: writing a '1' sets the pin low; writing a '0' has no effect - 1 + 0x1 @@ -31301,12 +31729,12 @@ POSSIBILITY OF SUCH DAMAGE. Low Read: pin driver is low - 0 + 0x0 High Read: pin driver is high - 1 + 0x1 @@ -31314,7 +31742,7 @@ POSSIBILITY OF SUCH DAMAGE. Clear Write: writing a '1' sets the pin low; writing a '0' has no effect - 1 + 0x1 @@ -31328,12 +31756,12 @@ POSSIBILITY OF SUCH DAMAGE. Low Read: pin driver is low - 0 + 0x0 High Read: pin driver is high - 1 + 0x1 @@ -31341,7 +31769,7 @@ POSSIBILITY OF SUCH DAMAGE. Clear Write: writing a '1' sets the pin low; writing a '0' has no effect - 1 + 0x1 @@ -31355,12 +31783,12 @@ POSSIBILITY OF SUCH DAMAGE. Low Read: pin driver is low - 0 + 0x0 High Read: pin driver is high - 1 + 0x1 @@ -31368,7 +31796,7 @@ POSSIBILITY OF SUCH DAMAGE. Clear Write: writing a '1' sets the pin low; writing a '0' has no effect - 1 + 0x1 @@ -31382,12 +31810,12 @@ POSSIBILITY OF SUCH DAMAGE. Low Read: pin driver is low - 0 + 0x0 High Read: pin driver is high - 1 + 0x1 @@ -31395,7 +31823,7 @@ POSSIBILITY OF SUCH DAMAGE. Clear Write: writing a '1' sets the pin low; writing a '0' has no effect - 1 + 0x1 @@ -31409,12 +31837,12 @@ POSSIBILITY OF SUCH DAMAGE. Low Read: pin driver is low - 0 + 0x0 High Read: pin driver is high - 1 + 0x1 @@ -31422,7 +31850,7 @@ POSSIBILITY OF SUCH DAMAGE. Clear Write: writing a '1' sets the pin low; writing a '0' has no effect - 1 + 0x1 @@ -31436,12 +31864,12 @@ POSSIBILITY OF SUCH DAMAGE. Low Read: pin driver is low - 0 + 0x0 High Read: pin driver is high - 1 + 0x1 @@ -31449,7 +31877,7 @@ POSSIBILITY OF SUCH DAMAGE. Clear Write: writing a '1' sets the pin low; writing a '0' has no effect - 1 + 0x1 @@ -31463,12 +31891,12 @@ POSSIBILITY OF SUCH DAMAGE. Low Read: pin driver is low - 0 + 0x0 High Read: pin driver is high - 1 + 0x1 @@ -31476,7 +31904,7 @@ POSSIBILITY OF SUCH DAMAGE. Clear Write: writing a '1' sets the pin low; writing a '0' has no effect - 1 + 0x1 @@ -31490,12 +31918,12 @@ POSSIBILITY OF SUCH DAMAGE. Low Read: pin driver is low - 0 + 0x0 High Read: pin driver is high - 1 + 0x1 @@ -31503,7 +31931,7 @@ POSSIBILITY OF SUCH DAMAGE. Clear Write: writing a '1' sets the pin low; writing a '0' has no effect - 1 + 0x1 @@ -31517,12 +31945,12 @@ POSSIBILITY OF SUCH DAMAGE. Low Read: pin driver is low - 0 + 0x0 High Read: pin driver is high - 1 + 0x1 @@ -31530,7 +31958,7 @@ POSSIBILITY OF SUCH DAMAGE. Clear Write: writing a '1' sets the pin low; writing a '0' has no effect - 1 + 0x1 @@ -31544,12 +31972,12 @@ POSSIBILITY OF SUCH DAMAGE. Low Read: pin driver is low - 0 + 0x0 High Read: pin driver is high - 1 + 0x1 @@ -31557,7 +31985,7 @@ POSSIBILITY OF SUCH DAMAGE. Clear Write: writing a '1' sets the pin low; writing a '0' has no effect - 1 + 0x1 @@ -31571,12 +31999,12 @@ POSSIBILITY OF SUCH DAMAGE. Low Read: pin driver is low - 0 + 0x0 High Read: pin driver is high - 1 + 0x1 @@ -31584,7 +32012,7 @@ POSSIBILITY OF SUCH DAMAGE. Clear Write: writing a '1' sets the pin low; writing a '0' has no effect - 1 + 0x1 @@ -31598,12 +32026,12 @@ POSSIBILITY OF SUCH DAMAGE. Low Read: pin driver is low - 0 + 0x0 High Read: pin driver is high - 1 + 0x1 @@ -31611,7 +32039,7 @@ POSSIBILITY OF SUCH DAMAGE. Clear Write: writing a '1' sets the pin low; writing a '0' has no effect - 1 + 0x1 @@ -31625,12 +32053,12 @@ POSSIBILITY OF SUCH DAMAGE. Low Read: pin driver is low - 0 + 0x0 High Read: pin driver is high - 1 + 0x1 @@ -31638,7 +32066,7 @@ POSSIBILITY OF SUCH DAMAGE. Clear Write: writing a '1' sets the pin low; writing a '0' has no effect - 1 + 0x1 @@ -31652,12 +32080,12 @@ POSSIBILITY OF SUCH DAMAGE. Low Read: pin driver is low - 0 + 0x0 High Read: pin driver is high - 1 + 0x1 @@ -31665,7 +32093,7 @@ POSSIBILITY OF SUCH DAMAGE. Clear Write: writing a '1' sets the pin low; writing a '0' has no effect - 1 + 0x1 @@ -31679,12 +32107,12 @@ POSSIBILITY OF SUCH DAMAGE. Low Read: pin driver is low - 0 + 0x0 High Read: pin driver is high - 1 + 0x1 @@ -31692,7 +32120,7 @@ POSSIBILITY OF SUCH DAMAGE. Clear Write: writing a '1' sets the pin low; writing a '0' has no effect - 1 + 0x1 @@ -31706,12 +32134,12 @@ POSSIBILITY OF SUCH DAMAGE. Low Read: pin driver is low - 0 + 0x0 High Read: pin driver is high - 1 + 0x1 @@ -31719,7 +32147,7 @@ POSSIBILITY OF SUCH DAMAGE. Clear Write: writing a '1' sets the pin low; writing a '0' has no effect - 1 + 0x1 @@ -31733,12 +32161,12 @@ POSSIBILITY OF SUCH DAMAGE. Low Read: pin driver is low - 0 + 0x0 High Read: pin driver is high - 1 + 0x1 @@ -31746,7 +32174,7 @@ POSSIBILITY OF SUCH DAMAGE. Clear Write: writing a '1' sets the pin low; writing a '0' has no effect - 1 + 0x1 @@ -31760,12 +32188,12 @@ POSSIBILITY OF SUCH DAMAGE. Low Read: pin driver is low - 0 + 0x0 High Read: pin driver is high - 1 + 0x1 @@ -31773,7 +32201,7 @@ POSSIBILITY OF SUCH DAMAGE. Clear Write: writing a '1' sets the pin low; writing a '0' has no effect - 1 + 0x1 @@ -31787,12 +32215,12 @@ POSSIBILITY OF SUCH DAMAGE. Low Read: pin driver is low - 0 + 0x0 High Read: pin driver is high - 1 + 0x1 @@ -31800,7 +32228,7 @@ POSSIBILITY OF SUCH DAMAGE. Clear Write: writing a '1' sets the pin low; writing a '0' has no effect - 1 + 0x1 @@ -31814,12 +32242,12 @@ POSSIBILITY OF SUCH DAMAGE. Low Read: pin driver is low - 0 + 0x0 High Read: pin driver is high - 1 + 0x1 @@ -31827,7 +32255,7 @@ POSSIBILITY OF SUCH DAMAGE. Clear Write: writing a '1' sets the pin low; writing a '0' has no effect - 1 + 0x1 @@ -31841,12 +32269,12 @@ POSSIBILITY OF SUCH DAMAGE. Low Read: pin driver is low - 0 + 0x0 High Read: pin driver is high - 1 + 0x1 @@ -31854,7 +32282,7 @@ POSSIBILITY OF SUCH DAMAGE. Clear Write: writing a '1' sets the pin low; writing a '0' has no effect - 1 + 0x1 @@ -31868,12 +32296,12 @@ POSSIBILITY OF SUCH DAMAGE. Low Read: pin driver is low - 0 + 0x0 High Read: pin driver is high - 1 + 0x1 @@ -31881,7 +32309,7 @@ POSSIBILITY OF SUCH DAMAGE. Clear Write: writing a '1' sets the pin low; writing a '0' has no effect - 1 + 0x1 @@ -31895,12 +32323,12 @@ POSSIBILITY OF SUCH DAMAGE. Low Read: pin driver is low - 0 + 0x0 High Read: pin driver is high - 1 + 0x1 @@ -31908,7 +32336,7 @@ POSSIBILITY OF SUCH DAMAGE. Clear Write: writing a '1' sets the pin low; writing a '0' has no effect - 1 + 0x1 @@ -31922,12 +32350,12 @@ POSSIBILITY OF SUCH DAMAGE. Low Read: pin driver is low - 0 + 0x0 High Read: pin driver is high - 1 + 0x1 @@ -31935,7 +32363,7 @@ POSSIBILITY OF SUCH DAMAGE. Clear Write: writing a '1' sets the pin low; writing a '0' has no effect - 1 + 0x1 @@ -31949,12 +32377,12 @@ POSSIBILITY OF SUCH DAMAGE. Low Read: pin driver is low - 0 + 0x0 High Read: pin driver is high - 1 + 0x1 @@ -31962,7 +32390,7 @@ POSSIBILITY OF SUCH DAMAGE. Clear Write: writing a '1' sets the pin low; writing a '0' has no effect - 1 + 0x1 @@ -31976,12 +32404,12 @@ POSSIBILITY OF SUCH DAMAGE. Low Read: pin driver is low - 0 + 0x0 High Read: pin driver is high - 1 + 0x1 @@ -31989,7 +32417,7 @@ POSSIBILITY OF SUCH DAMAGE. Clear Write: writing a '1' sets the pin low; writing a '0' has no effect - 1 + 0x1 @@ -32003,12 +32431,12 @@ POSSIBILITY OF SUCH DAMAGE. Low Read: pin driver is low - 0 + 0x0 High Read: pin driver is high - 1 + 0x1 @@ -32016,7 +32444,7 @@ POSSIBILITY OF SUCH DAMAGE. Clear Write: writing a '1' sets the pin low; writing a '0' has no effect - 1 + 0x1 @@ -32030,12 +32458,12 @@ POSSIBILITY OF SUCH DAMAGE. Low Read: pin driver is low - 0 + 0x0 High Read: pin driver is high - 1 + 0x1 @@ -32043,7 +32471,7 @@ POSSIBILITY OF SUCH DAMAGE. Clear Write: writing a '1' sets the pin low; writing a '0' has no effect - 1 + 0x1 @@ -32057,12 +32485,12 @@ POSSIBILITY OF SUCH DAMAGE. Low Read: pin driver is low - 0 + 0x0 High Read: pin driver is high - 1 + 0x1 @@ -32070,7 +32498,7 @@ POSSIBILITY OF SUCH DAMAGE. Clear Write: writing a '1' sets the pin low; writing a '0' has no effect - 1 + 0x1 @@ -32081,6 +32509,7 @@ POSSIBILITY OF SUCH DAMAGE. Read GPIO port 0x010 read-only + 0x00000000 PIN0 @@ -32091,12 +32520,12 @@ POSSIBILITY OF SUCH DAMAGE. Low Pin input is low - 0 + 0x0 High Pin input is high - 1 + 0x1 @@ -32109,12 +32538,12 @@ POSSIBILITY OF SUCH DAMAGE. Low Pin input is low - 0 + 0x0 High Pin input is high - 1 + 0x1 @@ -32127,12 +32556,12 @@ POSSIBILITY OF SUCH DAMAGE. Low Pin input is low - 0 + 0x0 High Pin input is high - 1 + 0x1 @@ -32145,12 +32574,12 @@ POSSIBILITY OF SUCH DAMAGE. Low Pin input is low - 0 + 0x0 High Pin input is high - 1 + 0x1 @@ -32163,12 +32592,12 @@ POSSIBILITY OF SUCH DAMAGE. Low Pin input is low - 0 + 0x0 High Pin input is high - 1 + 0x1 @@ -32181,12 +32610,12 @@ POSSIBILITY OF SUCH DAMAGE. Low Pin input is low - 0 + 0x0 High Pin input is high - 1 + 0x1 @@ -32199,12 +32628,12 @@ POSSIBILITY OF SUCH DAMAGE. Low Pin input is low - 0 + 0x0 High Pin input is high - 1 + 0x1 @@ -32217,12 +32646,12 @@ POSSIBILITY OF SUCH DAMAGE. Low Pin input is low - 0 + 0x0 High Pin input is high - 1 + 0x1 @@ -32235,12 +32664,12 @@ POSSIBILITY OF SUCH DAMAGE. Low Pin input is low - 0 + 0x0 High Pin input is high - 1 + 0x1 @@ -32253,12 +32682,12 @@ POSSIBILITY OF SUCH DAMAGE. Low Pin input is low - 0 + 0x0 High Pin input is high - 1 + 0x1 @@ -32271,12 +32700,12 @@ POSSIBILITY OF SUCH DAMAGE. Low Pin input is low - 0 + 0x0 High Pin input is high - 1 + 0x1 @@ -32289,12 +32718,12 @@ POSSIBILITY OF SUCH DAMAGE. Low Pin input is low - 0 + 0x0 High Pin input is high - 1 + 0x1 @@ -32307,12 +32736,12 @@ POSSIBILITY OF SUCH DAMAGE. Low Pin input is low - 0 + 0x0 High Pin input is high - 1 + 0x1 @@ -32325,12 +32754,12 @@ POSSIBILITY OF SUCH DAMAGE. Low Pin input is low - 0 + 0x0 High Pin input is high - 1 + 0x1 @@ -32343,12 +32772,12 @@ POSSIBILITY OF SUCH DAMAGE. Low Pin input is low - 0 + 0x0 High Pin input is high - 1 + 0x1 @@ -32361,12 +32790,12 @@ POSSIBILITY OF SUCH DAMAGE. Low Pin input is low - 0 + 0x0 High Pin input is high - 1 + 0x1 @@ -32379,12 +32808,12 @@ POSSIBILITY OF SUCH DAMAGE. Low Pin input is low - 0 + 0x0 High Pin input is high - 1 + 0x1 @@ -32397,12 +32826,12 @@ POSSIBILITY OF SUCH DAMAGE. Low Pin input is low - 0 + 0x0 High Pin input is high - 1 + 0x1 @@ -32415,12 +32844,12 @@ POSSIBILITY OF SUCH DAMAGE. Low Pin input is low - 0 + 0x0 High Pin input is high - 1 + 0x1 @@ -32433,12 +32862,12 @@ POSSIBILITY OF SUCH DAMAGE. Low Pin input is low - 0 + 0x0 High Pin input is high - 1 + 0x1 @@ -32451,12 +32880,12 @@ POSSIBILITY OF SUCH DAMAGE. Low Pin input is low - 0 + 0x0 High Pin input is high - 1 + 0x1 @@ -32469,12 +32898,12 @@ POSSIBILITY OF SUCH DAMAGE. Low Pin input is low - 0 + 0x0 High Pin input is high - 1 + 0x1 @@ -32487,12 +32916,12 @@ POSSIBILITY OF SUCH DAMAGE. Low Pin input is low - 0 + 0x0 High Pin input is high - 1 + 0x1 @@ -32505,12 +32934,12 @@ POSSIBILITY OF SUCH DAMAGE. Low Pin input is low - 0 + 0x0 High Pin input is high - 1 + 0x1 @@ -32523,12 +32952,12 @@ POSSIBILITY OF SUCH DAMAGE. Low Pin input is low - 0 + 0x0 High Pin input is high - 1 + 0x1 @@ -32541,12 +32970,12 @@ POSSIBILITY OF SUCH DAMAGE. Low Pin input is low - 0 + 0x0 High Pin input is high - 1 + 0x1 @@ -32559,12 +32988,12 @@ POSSIBILITY OF SUCH DAMAGE. Low Pin input is low - 0 + 0x0 High Pin input is high - 1 + 0x1 @@ -32577,12 +33006,12 @@ POSSIBILITY OF SUCH DAMAGE. Low Pin input is low - 0 + 0x0 High Pin input is high - 1 + 0x1 @@ -32595,12 +33024,12 @@ POSSIBILITY OF SUCH DAMAGE. Low Pin input is low - 0 + 0x0 High Pin input is high - 1 + 0x1 @@ -32613,12 +33042,12 @@ POSSIBILITY OF SUCH DAMAGE. Low Pin input is low - 0 + 0x0 High Pin input is high - 1 + 0x1 @@ -32631,12 +33060,12 @@ POSSIBILITY OF SUCH DAMAGE. Low Pin input is low - 0 + 0x0 High Pin input is high - 1 + 0x1 @@ -32649,12 +33078,12 @@ POSSIBILITY OF SUCH DAMAGE. Low Pin input is low - 0 + 0x0 High Pin input is high - 1 + 0x1 @@ -32665,6 +33094,7 @@ POSSIBILITY OF SUCH DAMAGE. Direction of GPIO pins 0x014 read-write + 0x00000000 PIN0 @@ -32675,12 +33105,12 @@ POSSIBILITY OF SUCH DAMAGE. Input Pin set as input - 0 + 0x0 Output Pin set as output - 1 + 0x1 @@ -32693,12 +33123,12 @@ POSSIBILITY OF SUCH DAMAGE. Input Pin set as input - 0 + 0x0 Output Pin set as output - 1 + 0x1 @@ -32711,12 +33141,12 @@ POSSIBILITY OF SUCH DAMAGE. Input Pin set as input - 0 + 0x0 Output Pin set as output - 1 + 0x1 @@ -32729,12 +33159,12 @@ POSSIBILITY OF SUCH DAMAGE. Input Pin set as input - 0 + 0x0 Output Pin set as output - 1 + 0x1 @@ -32747,12 +33177,12 @@ POSSIBILITY OF SUCH DAMAGE. Input Pin set as input - 0 + 0x0 Output Pin set as output - 1 + 0x1 @@ -32765,12 +33195,12 @@ POSSIBILITY OF SUCH DAMAGE. Input Pin set as input - 0 + 0x0 Output Pin set as output - 1 + 0x1 @@ -32783,12 +33213,12 @@ POSSIBILITY OF SUCH DAMAGE. Input Pin set as input - 0 + 0x0 Output Pin set as output - 1 + 0x1 @@ -32801,12 +33231,12 @@ POSSIBILITY OF SUCH DAMAGE. Input Pin set as input - 0 + 0x0 Output Pin set as output - 1 + 0x1 @@ -32819,12 +33249,12 @@ POSSIBILITY OF SUCH DAMAGE. Input Pin set as input - 0 + 0x0 Output Pin set as output - 1 + 0x1 @@ -32837,12 +33267,12 @@ POSSIBILITY OF SUCH DAMAGE. Input Pin set as input - 0 + 0x0 Output Pin set as output - 1 + 0x1 @@ -32855,12 +33285,12 @@ POSSIBILITY OF SUCH DAMAGE. Input Pin set as input - 0 + 0x0 Output Pin set as output - 1 + 0x1 @@ -32873,12 +33303,12 @@ POSSIBILITY OF SUCH DAMAGE. Input Pin set as input - 0 + 0x0 Output Pin set as output - 1 + 0x1 @@ -32891,12 +33321,12 @@ POSSIBILITY OF SUCH DAMAGE. Input Pin set as input - 0 + 0x0 Output Pin set as output - 1 + 0x1 @@ -32909,12 +33339,12 @@ POSSIBILITY OF SUCH DAMAGE. Input Pin set as input - 0 + 0x0 Output Pin set as output - 1 + 0x1 @@ -32927,12 +33357,12 @@ POSSIBILITY OF SUCH DAMAGE. Input Pin set as input - 0 + 0x0 Output Pin set as output - 1 + 0x1 @@ -32945,12 +33375,12 @@ POSSIBILITY OF SUCH DAMAGE. Input Pin set as input - 0 + 0x0 Output Pin set as output - 1 + 0x1 @@ -32963,12 +33393,12 @@ POSSIBILITY OF SUCH DAMAGE. Input Pin set as input - 0 + 0x0 Output Pin set as output - 1 + 0x1 @@ -32981,12 +33411,12 @@ POSSIBILITY OF SUCH DAMAGE. Input Pin set as input - 0 + 0x0 Output Pin set as output - 1 + 0x1 @@ -32999,12 +33429,12 @@ POSSIBILITY OF SUCH DAMAGE. Input Pin set as input - 0 + 0x0 Output Pin set as output - 1 + 0x1 @@ -33017,12 +33447,12 @@ POSSIBILITY OF SUCH DAMAGE. Input Pin set as input - 0 + 0x0 Output Pin set as output - 1 + 0x1 @@ -33035,12 +33465,12 @@ POSSIBILITY OF SUCH DAMAGE. Input Pin set as input - 0 + 0x0 Output Pin set as output - 1 + 0x1 @@ -33053,12 +33483,12 @@ POSSIBILITY OF SUCH DAMAGE. Input Pin set as input - 0 + 0x0 Output Pin set as output - 1 + 0x1 @@ -33071,12 +33501,12 @@ POSSIBILITY OF SUCH DAMAGE. Input Pin set as input - 0 + 0x0 Output Pin set as output - 1 + 0x1 @@ -33089,12 +33519,12 @@ POSSIBILITY OF SUCH DAMAGE. Input Pin set as input - 0 + 0x0 Output Pin set as output - 1 + 0x1 @@ -33107,12 +33537,12 @@ POSSIBILITY OF SUCH DAMAGE. Input Pin set as input - 0 + 0x0 Output Pin set as output - 1 + 0x1 @@ -33125,12 +33555,12 @@ POSSIBILITY OF SUCH DAMAGE. Input Pin set as input - 0 + 0x0 Output Pin set as output - 1 + 0x1 @@ -33143,12 +33573,12 @@ POSSIBILITY OF SUCH DAMAGE. Input Pin set as input - 0 + 0x0 Output Pin set as output - 1 + 0x1 @@ -33161,12 +33591,12 @@ POSSIBILITY OF SUCH DAMAGE. Input Pin set as input - 0 + 0x0 Output Pin set as output - 1 + 0x1 @@ -33179,12 +33609,12 @@ POSSIBILITY OF SUCH DAMAGE. Input Pin set as input - 0 + 0x0 Output Pin set as output - 1 + 0x1 @@ -33197,12 +33627,12 @@ POSSIBILITY OF SUCH DAMAGE. Input Pin set as input - 0 + 0x0 Output Pin set as output - 1 + 0x1 @@ -33215,12 +33645,12 @@ POSSIBILITY OF SUCH DAMAGE. Input Pin set as input - 0 + 0x0 Output Pin set as output - 1 + 0x1 @@ -33233,12 +33663,12 @@ POSSIBILITY OF SUCH DAMAGE. Input Pin set as input - 0 + 0x0 Output Pin set as output - 1 + 0x1 @@ -33249,6 +33679,7 @@ POSSIBILITY OF SUCH DAMAGE. DIR set register 0x018 read-write + 0x00000000 oneToSet @@ -33261,12 +33692,12 @@ POSSIBILITY OF SUCH DAMAGE. Input Read: pin set as input - 0 + 0x0 Output Read: pin set as output - 1 + 0x1 @@ -33274,7 +33705,7 @@ POSSIBILITY OF SUCH DAMAGE. Set Write: writing a '1' sets pin to output; writing a '0' has no effect - 1 + 0x1 @@ -33288,12 +33719,12 @@ POSSIBILITY OF SUCH DAMAGE. Input Read: pin set as input - 0 + 0x0 Output Read: pin set as output - 1 + 0x1 @@ -33301,7 +33732,7 @@ POSSIBILITY OF SUCH DAMAGE. Set Write: writing a '1' sets pin to output; writing a '0' has no effect - 1 + 0x1 @@ -33315,12 +33746,12 @@ POSSIBILITY OF SUCH DAMAGE. Input Read: pin set as input - 0 + 0x0 Output Read: pin set as output - 1 + 0x1 @@ -33328,7 +33759,7 @@ POSSIBILITY OF SUCH DAMAGE. Set Write: writing a '1' sets pin to output; writing a '0' has no effect - 1 + 0x1 @@ -33342,12 +33773,12 @@ POSSIBILITY OF SUCH DAMAGE. Input Read: pin set as input - 0 + 0x0 Output Read: pin set as output - 1 + 0x1 @@ -33355,7 +33786,7 @@ POSSIBILITY OF SUCH DAMAGE. Set Write: writing a '1' sets pin to output; writing a '0' has no effect - 1 + 0x1 @@ -33369,12 +33800,12 @@ POSSIBILITY OF SUCH DAMAGE. Input Read: pin set as input - 0 + 0x0 Output Read: pin set as output - 1 + 0x1 @@ -33382,7 +33813,7 @@ POSSIBILITY OF SUCH DAMAGE. Set Write: writing a '1' sets pin to output; writing a '0' has no effect - 1 + 0x1 @@ -33396,12 +33827,12 @@ POSSIBILITY OF SUCH DAMAGE. Input Read: pin set as input - 0 + 0x0 Output Read: pin set as output - 1 + 0x1 @@ -33409,7 +33840,7 @@ POSSIBILITY OF SUCH DAMAGE. Set Write: writing a '1' sets pin to output; writing a '0' has no effect - 1 + 0x1 @@ -33423,12 +33854,12 @@ POSSIBILITY OF SUCH DAMAGE. Input Read: pin set as input - 0 + 0x0 Output Read: pin set as output - 1 + 0x1 @@ -33436,7 +33867,7 @@ POSSIBILITY OF SUCH DAMAGE. Set Write: writing a '1' sets pin to output; writing a '0' has no effect - 1 + 0x1 @@ -33450,12 +33881,12 @@ POSSIBILITY OF SUCH DAMAGE. Input Read: pin set as input - 0 + 0x0 Output Read: pin set as output - 1 + 0x1 @@ -33463,7 +33894,7 @@ POSSIBILITY OF SUCH DAMAGE. Set Write: writing a '1' sets pin to output; writing a '0' has no effect - 1 + 0x1 @@ -33477,12 +33908,12 @@ POSSIBILITY OF SUCH DAMAGE. Input Read: pin set as input - 0 + 0x0 Output Read: pin set as output - 1 + 0x1 @@ -33490,7 +33921,7 @@ POSSIBILITY OF SUCH DAMAGE. Set Write: writing a '1' sets pin to output; writing a '0' has no effect - 1 + 0x1 @@ -33504,12 +33935,12 @@ POSSIBILITY OF SUCH DAMAGE. Input Read: pin set as input - 0 + 0x0 Output Read: pin set as output - 1 + 0x1 @@ -33517,7 +33948,7 @@ POSSIBILITY OF SUCH DAMAGE. Set Write: writing a '1' sets pin to output; writing a '0' has no effect - 1 + 0x1 @@ -33531,12 +33962,12 @@ POSSIBILITY OF SUCH DAMAGE. Input Read: pin set as input - 0 + 0x0 Output Read: pin set as output - 1 + 0x1 @@ -33544,7 +33975,7 @@ POSSIBILITY OF SUCH DAMAGE. Set Write: writing a '1' sets pin to output; writing a '0' has no effect - 1 + 0x1 @@ -33558,12 +33989,12 @@ POSSIBILITY OF SUCH DAMAGE. Input Read: pin set as input - 0 + 0x0 Output Read: pin set as output - 1 + 0x1 @@ -33571,7 +34002,7 @@ POSSIBILITY OF SUCH DAMAGE. Set Write: writing a '1' sets pin to output; writing a '0' has no effect - 1 + 0x1 @@ -33585,12 +34016,12 @@ POSSIBILITY OF SUCH DAMAGE. Input Read: pin set as input - 0 + 0x0 Output Read: pin set as output - 1 + 0x1 @@ -33598,7 +34029,7 @@ POSSIBILITY OF SUCH DAMAGE. Set Write: writing a '1' sets pin to output; writing a '0' has no effect - 1 + 0x1 @@ -33612,12 +34043,12 @@ POSSIBILITY OF SUCH DAMAGE. Input Read: pin set as input - 0 + 0x0 Output Read: pin set as output - 1 + 0x1 @@ -33625,7 +34056,7 @@ POSSIBILITY OF SUCH DAMAGE. Set Write: writing a '1' sets pin to output; writing a '0' has no effect - 1 + 0x1 @@ -33639,12 +34070,12 @@ POSSIBILITY OF SUCH DAMAGE. Input Read: pin set as input - 0 + 0x0 Output Read: pin set as output - 1 + 0x1 @@ -33652,7 +34083,7 @@ POSSIBILITY OF SUCH DAMAGE. Set Write: writing a '1' sets pin to output; writing a '0' has no effect - 1 + 0x1 @@ -33666,12 +34097,12 @@ POSSIBILITY OF SUCH DAMAGE. Input Read: pin set as input - 0 + 0x0 Output Read: pin set as output - 1 + 0x1 @@ -33679,7 +34110,7 @@ POSSIBILITY OF SUCH DAMAGE. Set Write: writing a '1' sets pin to output; writing a '0' has no effect - 1 + 0x1 @@ -33693,12 +34124,12 @@ POSSIBILITY OF SUCH DAMAGE. Input Read: pin set as input - 0 + 0x0 Output Read: pin set as output - 1 + 0x1 @@ -33706,7 +34137,7 @@ POSSIBILITY OF SUCH DAMAGE. Set Write: writing a '1' sets pin to output; writing a '0' has no effect - 1 + 0x1 @@ -33720,12 +34151,12 @@ POSSIBILITY OF SUCH DAMAGE. Input Read: pin set as input - 0 + 0x0 Output Read: pin set as output - 1 + 0x1 @@ -33733,7 +34164,7 @@ POSSIBILITY OF SUCH DAMAGE. Set Write: writing a '1' sets pin to output; writing a '0' has no effect - 1 + 0x1 @@ -33747,12 +34178,12 @@ POSSIBILITY OF SUCH DAMAGE. Input Read: pin set as input - 0 + 0x0 Output Read: pin set as output - 1 + 0x1 @@ -33760,7 +34191,7 @@ POSSIBILITY OF SUCH DAMAGE. Set Write: writing a '1' sets pin to output; writing a '0' has no effect - 1 + 0x1 @@ -33774,12 +34205,12 @@ POSSIBILITY OF SUCH DAMAGE. Input Read: pin set as input - 0 + 0x0 Output Read: pin set as output - 1 + 0x1 @@ -33787,7 +34218,7 @@ POSSIBILITY OF SUCH DAMAGE. Set Write: writing a '1' sets pin to output; writing a '0' has no effect - 1 + 0x1 @@ -33801,12 +34232,12 @@ POSSIBILITY OF SUCH DAMAGE. Input Read: pin set as input - 0 + 0x0 Output Read: pin set as output - 1 + 0x1 @@ -33814,7 +34245,7 @@ POSSIBILITY OF SUCH DAMAGE. Set Write: writing a '1' sets pin to output; writing a '0' has no effect - 1 + 0x1 @@ -33828,12 +34259,12 @@ POSSIBILITY OF SUCH DAMAGE. Input Read: pin set as input - 0 + 0x0 Output Read: pin set as output - 1 + 0x1 @@ -33841,7 +34272,7 @@ POSSIBILITY OF SUCH DAMAGE. Set Write: writing a '1' sets pin to output; writing a '0' has no effect - 1 + 0x1 @@ -33855,12 +34286,12 @@ POSSIBILITY OF SUCH DAMAGE. Input Read: pin set as input - 0 + 0x0 Output Read: pin set as output - 1 + 0x1 @@ -33868,7 +34299,7 @@ POSSIBILITY OF SUCH DAMAGE. Set Write: writing a '1' sets pin to output; writing a '0' has no effect - 1 + 0x1 @@ -33882,12 +34313,12 @@ POSSIBILITY OF SUCH DAMAGE. Input Read: pin set as input - 0 + 0x0 Output Read: pin set as output - 1 + 0x1 @@ -33895,7 +34326,7 @@ POSSIBILITY OF SUCH DAMAGE. Set Write: writing a '1' sets pin to output; writing a '0' has no effect - 1 + 0x1 @@ -33909,12 +34340,12 @@ POSSIBILITY OF SUCH DAMAGE. Input Read: pin set as input - 0 + 0x0 Output Read: pin set as output - 1 + 0x1 @@ -33922,7 +34353,7 @@ POSSIBILITY OF SUCH DAMAGE. Set Write: writing a '1' sets pin to output; writing a '0' has no effect - 1 + 0x1 @@ -33936,12 +34367,12 @@ POSSIBILITY OF SUCH DAMAGE. Input Read: pin set as input - 0 + 0x0 Output Read: pin set as output - 1 + 0x1 @@ -33949,7 +34380,7 @@ POSSIBILITY OF SUCH DAMAGE. Set Write: writing a '1' sets pin to output; writing a '0' has no effect - 1 + 0x1 @@ -33963,12 +34394,12 @@ POSSIBILITY OF SUCH DAMAGE. Input Read: pin set as input - 0 + 0x0 Output Read: pin set as output - 1 + 0x1 @@ -33976,7 +34407,7 @@ POSSIBILITY OF SUCH DAMAGE. Set Write: writing a '1' sets pin to output; writing a '0' has no effect - 1 + 0x1 @@ -33990,12 +34421,12 @@ POSSIBILITY OF SUCH DAMAGE. Input Read: pin set as input - 0 + 0x0 Output Read: pin set as output - 1 + 0x1 @@ -34003,7 +34434,7 @@ POSSIBILITY OF SUCH DAMAGE. Set Write: writing a '1' sets pin to output; writing a '0' has no effect - 1 + 0x1 @@ -34017,12 +34448,12 @@ POSSIBILITY OF SUCH DAMAGE. Input Read: pin set as input - 0 + 0x0 Output Read: pin set as output - 1 + 0x1 @@ -34030,7 +34461,7 @@ POSSIBILITY OF SUCH DAMAGE. Set Write: writing a '1' sets pin to output; writing a '0' has no effect - 1 + 0x1 @@ -34044,12 +34475,12 @@ POSSIBILITY OF SUCH DAMAGE. Input Read: pin set as input - 0 + 0x0 Output Read: pin set as output - 1 + 0x1 @@ -34057,7 +34488,7 @@ POSSIBILITY OF SUCH DAMAGE. Set Write: writing a '1' sets pin to output; writing a '0' has no effect - 1 + 0x1 @@ -34071,12 +34502,12 @@ POSSIBILITY OF SUCH DAMAGE. Input Read: pin set as input - 0 + 0x0 Output Read: pin set as output - 1 + 0x1 @@ -34084,7 +34515,7 @@ POSSIBILITY OF SUCH DAMAGE. Set Write: writing a '1' sets pin to output; writing a '0' has no effect - 1 + 0x1 @@ -34098,12 +34529,12 @@ POSSIBILITY OF SUCH DAMAGE. Input Read: pin set as input - 0 + 0x0 Output Read: pin set as output - 1 + 0x1 @@ -34111,7 +34542,7 @@ POSSIBILITY OF SUCH DAMAGE. Set Write: writing a '1' sets pin to output; writing a '0' has no effect - 1 + 0x1 @@ -34122,6 +34553,7 @@ POSSIBILITY OF SUCH DAMAGE. DIR clear register 0x01C read-write + 0x00000000 oneToClear @@ -34134,12 +34566,12 @@ POSSIBILITY OF SUCH DAMAGE. Input Read: pin set as input - 0 + 0x0 Output Read: pin set as output - 1 + 0x1 @@ -34147,7 +34579,7 @@ POSSIBILITY OF SUCH DAMAGE. Clear Write: writing a '1' sets pin to input; writing a '0' has no effect - 1 + 0x1 @@ -34161,12 +34593,12 @@ POSSIBILITY OF SUCH DAMAGE. Input Read: pin set as input - 0 + 0x0 Output Read: pin set as output - 1 + 0x1 @@ -34174,7 +34606,7 @@ POSSIBILITY OF SUCH DAMAGE. Clear Write: writing a '1' sets pin to input; writing a '0' has no effect - 1 + 0x1 @@ -34188,12 +34620,12 @@ POSSIBILITY OF SUCH DAMAGE. Input Read: pin set as input - 0 + 0x0 Output Read: pin set as output - 1 + 0x1 @@ -34201,7 +34633,7 @@ POSSIBILITY OF SUCH DAMAGE. Clear Write: writing a '1' sets pin to input; writing a '0' has no effect - 1 + 0x1 @@ -34215,12 +34647,12 @@ POSSIBILITY OF SUCH DAMAGE. Input Read: pin set as input - 0 + 0x0 Output Read: pin set as output - 1 + 0x1 @@ -34228,7 +34660,7 @@ POSSIBILITY OF SUCH DAMAGE. Clear Write: writing a '1' sets pin to input; writing a '0' has no effect - 1 + 0x1 @@ -34242,12 +34674,12 @@ POSSIBILITY OF SUCH DAMAGE. Input Read: pin set as input - 0 + 0x0 Output Read: pin set as output - 1 + 0x1 @@ -34255,7 +34687,7 @@ POSSIBILITY OF SUCH DAMAGE. Clear Write: writing a '1' sets pin to input; writing a '0' has no effect - 1 + 0x1 @@ -34269,12 +34701,12 @@ POSSIBILITY OF SUCH DAMAGE. Input Read: pin set as input - 0 + 0x0 Output Read: pin set as output - 1 + 0x1 @@ -34282,7 +34714,7 @@ POSSIBILITY OF SUCH DAMAGE. Clear Write: writing a '1' sets pin to input; writing a '0' has no effect - 1 + 0x1 @@ -34296,12 +34728,12 @@ POSSIBILITY OF SUCH DAMAGE. Input Read: pin set as input - 0 + 0x0 Output Read: pin set as output - 1 + 0x1 @@ -34309,7 +34741,7 @@ POSSIBILITY OF SUCH DAMAGE. Clear Write: writing a '1' sets pin to input; writing a '0' has no effect - 1 + 0x1 @@ -34323,12 +34755,12 @@ POSSIBILITY OF SUCH DAMAGE. Input Read: pin set as input - 0 + 0x0 Output Read: pin set as output - 1 + 0x1 @@ -34336,7 +34768,7 @@ POSSIBILITY OF SUCH DAMAGE. Clear Write: writing a '1' sets pin to input; writing a '0' has no effect - 1 + 0x1 @@ -34350,12 +34782,12 @@ POSSIBILITY OF SUCH DAMAGE. Input Read: pin set as input - 0 + 0x0 Output Read: pin set as output - 1 + 0x1 @@ -34363,7 +34795,7 @@ POSSIBILITY OF SUCH DAMAGE. Clear Write: writing a '1' sets pin to input; writing a '0' has no effect - 1 + 0x1 @@ -34377,12 +34809,12 @@ POSSIBILITY OF SUCH DAMAGE. Input Read: pin set as input - 0 + 0x0 Output Read: pin set as output - 1 + 0x1 @@ -34390,7 +34822,7 @@ POSSIBILITY OF SUCH DAMAGE. Clear Write: writing a '1' sets pin to input; writing a '0' has no effect - 1 + 0x1 @@ -34404,12 +34836,12 @@ POSSIBILITY OF SUCH DAMAGE. Input Read: pin set as input - 0 + 0x0 Output Read: pin set as output - 1 + 0x1 @@ -34417,7 +34849,7 @@ POSSIBILITY OF SUCH DAMAGE. Clear Write: writing a '1' sets pin to input; writing a '0' has no effect - 1 + 0x1 @@ -34431,12 +34863,12 @@ POSSIBILITY OF SUCH DAMAGE. Input Read: pin set as input - 0 + 0x0 Output Read: pin set as output - 1 + 0x1 @@ -34444,7 +34876,7 @@ POSSIBILITY OF SUCH DAMAGE. Clear Write: writing a '1' sets pin to input; writing a '0' has no effect - 1 + 0x1 @@ -34458,12 +34890,12 @@ POSSIBILITY OF SUCH DAMAGE. Input Read: pin set as input - 0 + 0x0 Output Read: pin set as output - 1 + 0x1 @@ -34471,7 +34903,7 @@ POSSIBILITY OF SUCH DAMAGE. Clear Write: writing a '1' sets pin to input; writing a '0' has no effect - 1 + 0x1 @@ -34485,12 +34917,12 @@ POSSIBILITY OF SUCH DAMAGE. Input Read: pin set as input - 0 + 0x0 Output Read: pin set as output - 1 + 0x1 @@ -34498,7 +34930,7 @@ POSSIBILITY OF SUCH DAMAGE. Clear Write: writing a '1' sets pin to input; writing a '0' has no effect - 1 + 0x1 @@ -34512,12 +34944,12 @@ POSSIBILITY OF SUCH DAMAGE. Input Read: pin set as input - 0 + 0x0 Output Read: pin set as output - 1 + 0x1 @@ -34525,7 +34957,7 @@ POSSIBILITY OF SUCH DAMAGE. Clear Write: writing a '1' sets pin to input; writing a '0' has no effect - 1 + 0x1 @@ -34539,12 +34971,12 @@ POSSIBILITY OF SUCH DAMAGE. Input Read: pin set as input - 0 + 0x0 Output Read: pin set as output - 1 + 0x1 @@ -34552,7 +34984,7 @@ POSSIBILITY OF SUCH DAMAGE. Clear Write: writing a '1' sets pin to input; writing a '0' has no effect - 1 + 0x1 @@ -34566,12 +34998,12 @@ POSSIBILITY OF SUCH DAMAGE. Input Read: pin set as input - 0 + 0x0 Output Read: pin set as output - 1 + 0x1 @@ -34579,7 +35011,7 @@ POSSIBILITY OF SUCH DAMAGE. Clear Write: writing a '1' sets pin to input; writing a '0' has no effect - 1 + 0x1 @@ -34593,12 +35025,12 @@ POSSIBILITY OF SUCH DAMAGE. Input Read: pin set as input - 0 + 0x0 Output Read: pin set as output - 1 + 0x1 @@ -34606,7 +35038,7 @@ POSSIBILITY OF SUCH DAMAGE. Clear Write: writing a '1' sets pin to input; writing a '0' has no effect - 1 + 0x1 @@ -34620,12 +35052,12 @@ POSSIBILITY OF SUCH DAMAGE. Input Read: pin set as input - 0 + 0x0 Output Read: pin set as output - 1 + 0x1 @@ -34633,7 +35065,7 @@ POSSIBILITY OF SUCH DAMAGE. Clear Write: writing a '1' sets pin to input; writing a '0' has no effect - 1 + 0x1 @@ -34647,12 +35079,12 @@ POSSIBILITY OF SUCH DAMAGE. Input Read: pin set as input - 0 + 0x0 Output Read: pin set as output - 1 + 0x1 @@ -34660,7 +35092,7 @@ POSSIBILITY OF SUCH DAMAGE. Clear Write: writing a '1' sets pin to input; writing a '0' has no effect - 1 + 0x1 @@ -34674,12 +35106,12 @@ POSSIBILITY OF SUCH DAMAGE. Input Read: pin set as input - 0 + 0x0 Output Read: pin set as output - 1 + 0x1 @@ -34687,7 +35119,7 @@ POSSIBILITY OF SUCH DAMAGE. Clear Write: writing a '1' sets pin to input; writing a '0' has no effect - 1 + 0x1 @@ -34701,12 +35133,12 @@ POSSIBILITY OF SUCH DAMAGE. Input Read: pin set as input - 0 + 0x0 Output Read: pin set as output - 1 + 0x1 @@ -34714,7 +35146,7 @@ POSSIBILITY OF SUCH DAMAGE. Clear Write: writing a '1' sets pin to input; writing a '0' has no effect - 1 + 0x1 @@ -34728,12 +35160,12 @@ POSSIBILITY OF SUCH DAMAGE. Input Read: pin set as input - 0 + 0x0 Output Read: pin set as output - 1 + 0x1 @@ -34741,7 +35173,7 @@ POSSIBILITY OF SUCH DAMAGE. Clear Write: writing a '1' sets pin to input; writing a '0' has no effect - 1 + 0x1 @@ -34755,12 +35187,12 @@ POSSIBILITY OF SUCH DAMAGE. Input Read: pin set as input - 0 + 0x0 Output Read: pin set as output - 1 + 0x1 @@ -34768,7 +35200,7 @@ POSSIBILITY OF SUCH DAMAGE. Clear Write: writing a '1' sets pin to input; writing a '0' has no effect - 1 + 0x1 @@ -34782,12 +35214,12 @@ POSSIBILITY OF SUCH DAMAGE. Input Read: pin set as input - 0 + 0x0 Output Read: pin set as output - 1 + 0x1 @@ -34795,7 +35227,7 @@ POSSIBILITY OF SUCH DAMAGE. Clear Write: writing a '1' sets pin to input; writing a '0' has no effect - 1 + 0x1 @@ -34809,12 +35241,12 @@ POSSIBILITY OF SUCH DAMAGE. Input Read: pin set as input - 0 + 0x0 Output Read: pin set as output - 1 + 0x1 @@ -34822,7 +35254,7 @@ POSSIBILITY OF SUCH DAMAGE. Clear Write: writing a '1' sets pin to input; writing a '0' has no effect - 1 + 0x1 @@ -34836,12 +35268,12 @@ POSSIBILITY OF SUCH DAMAGE. Input Read: pin set as input - 0 + 0x0 Output Read: pin set as output - 1 + 0x1 @@ -34849,7 +35281,7 @@ POSSIBILITY OF SUCH DAMAGE. Clear Write: writing a '1' sets pin to input; writing a '0' has no effect - 1 + 0x1 @@ -34863,12 +35295,12 @@ POSSIBILITY OF SUCH DAMAGE. Input Read: pin set as input - 0 + 0x0 Output Read: pin set as output - 1 + 0x1 @@ -34876,7 +35308,7 @@ POSSIBILITY OF SUCH DAMAGE. Clear Write: writing a '1' sets pin to input; writing a '0' has no effect - 1 + 0x1 @@ -34890,12 +35322,12 @@ POSSIBILITY OF SUCH DAMAGE. Input Read: pin set as input - 0 + 0x0 Output Read: pin set as output - 1 + 0x1 @@ -34903,7 +35335,7 @@ POSSIBILITY OF SUCH DAMAGE. Clear Write: writing a '1' sets pin to input; writing a '0' has no effect - 1 + 0x1 @@ -34917,12 +35349,12 @@ POSSIBILITY OF SUCH DAMAGE. Input Read: pin set as input - 0 + 0x0 Output Read: pin set as output - 1 + 0x1 @@ -34930,7 +35362,7 @@ POSSIBILITY OF SUCH DAMAGE. Clear Write: writing a '1' sets pin to input; writing a '0' has no effect - 1 + 0x1 @@ -34944,12 +35376,12 @@ POSSIBILITY OF SUCH DAMAGE. Input Read: pin set as input - 0 + 0x0 Output Read: pin set as output - 1 + 0x1 @@ -34957,7 +35389,7 @@ POSSIBILITY OF SUCH DAMAGE. Clear Write: writing a '1' sets pin to input; writing a '0' has no effect - 1 + 0x1 @@ -34971,12 +35403,12 @@ POSSIBILITY OF SUCH DAMAGE. Input Read: pin set as input - 0 + 0x0 Output Read: pin set as output - 1 + 0x1 @@ -34984,7 +35416,7 @@ POSSIBILITY OF SUCH DAMAGE. Clear Write: writing a '1' sets pin to input; writing a '0' has no effect - 1 + 0x1 @@ -34995,6 +35427,7 @@ POSSIBILITY OF SUCH DAMAGE. Latch register indicating what GPIO pins that have met the criteria set in the PIN_CNF[n].SENSE registers 0x020 read-write + 0x00000000 PIN0 @@ -35005,12 +35438,12 @@ POSSIBILITY OF SUCH DAMAGE. NotLatched Criteria has not been met - 0 + 0x0 Latched Criteria has been met - 1 + 0x1 @@ -35023,12 +35456,12 @@ POSSIBILITY OF SUCH DAMAGE. NotLatched Criteria has not been met - 0 + 0x0 Latched Criteria has been met - 1 + 0x1 @@ -35041,12 +35474,12 @@ POSSIBILITY OF SUCH DAMAGE. NotLatched Criteria has not been met - 0 + 0x0 Latched Criteria has been met - 1 + 0x1 @@ -35059,12 +35492,12 @@ POSSIBILITY OF SUCH DAMAGE. NotLatched Criteria has not been met - 0 + 0x0 Latched Criteria has been met - 1 + 0x1 @@ -35077,12 +35510,12 @@ POSSIBILITY OF SUCH DAMAGE. NotLatched Criteria has not been met - 0 + 0x0 Latched Criteria has been met - 1 + 0x1 @@ -35095,12 +35528,12 @@ POSSIBILITY OF SUCH DAMAGE. NotLatched Criteria has not been met - 0 + 0x0 Latched Criteria has been met - 1 + 0x1 @@ -35113,12 +35546,12 @@ POSSIBILITY OF SUCH DAMAGE. NotLatched Criteria has not been met - 0 + 0x0 Latched Criteria has been met - 1 + 0x1 @@ -35131,12 +35564,12 @@ POSSIBILITY OF SUCH DAMAGE. NotLatched Criteria has not been met - 0 + 0x0 Latched Criteria has been met - 1 + 0x1 @@ -35149,12 +35582,12 @@ POSSIBILITY OF SUCH DAMAGE. NotLatched Criteria has not been met - 0 + 0x0 Latched Criteria has been met - 1 + 0x1 @@ -35167,12 +35600,12 @@ POSSIBILITY OF SUCH DAMAGE. NotLatched Criteria has not been met - 0 + 0x0 Latched Criteria has been met - 1 + 0x1 @@ -35185,12 +35618,12 @@ POSSIBILITY OF SUCH DAMAGE. NotLatched Criteria has not been met - 0 + 0x0 Latched Criteria has been met - 1 + 0x1 @@ -35203,12 +35636,12 @@ POSSIBILITY OF SUCH DAMAGE. NotLatched Criteria has not been met - 0 + 0x0 Latched Criteria has been met - 1 + 0x1 @@ -35221,12 +35654,12 @@ POSSIBILITY OF SUCH DAMAGE. NotLatched Criteria has not been met - 0 + 0x0 Latched Criteria has been met - 1 + 0x1 @@ -35239,12 +35672,12 @@ POSSIBILITY OF SUCH DAMAGE. NotLatched Criteria has not been met - 0 + 0x0 Latched Criteria has been met - 1 + 0x1 @@ -35257,12 +35690,12 @@ POSSIBILITY OF SUCH DAMAGE. NotLatched Criteria has not been met - 0 + 0x0 Latched Criteria has been met - 1 + 0x1 @@ -35275,12 +35708,12 @@ POSSIBILITY OF SUCH DAMAGE. NotLatched Criteria has not been met - 0 + 0x0 Latched Criteria has been met - 1 + 0x1 @@ -35293,12 +35726,12 @@ POSSIBILITY OF SUCH DAMAGE. NotLatched Criteria has not been met - 0 + 0x0 Latched Criteria has been met - 1 + 0x1 @@ -35311,12 +35744,12 @@ POSSIBILITY OF SUCH DAMAGE. NotLatched Criteria has not been met - 0 + 0x0 Latched Criteria has been met - 1 + 0x1 @@ -35329,12 +35762,12 @@ POSSIBILITY OF SUCH DAMAGE. NotLatched Criteria has not been met - 0 + 0x0 Latched Criteria has been met - 1 + 0x1 @@ -35347,12 +35780,12 @@ POSSIBILITY OF SUCH DAMAGE. NotLatched Criteria has not been met - 0 + 0x0 Latched Criteria has been met - 1 + 0x1 @@ -35365,12 +35798,12 @@ POSSIBILITY OF SUCH DAMAGE. NotLatched Criteria has not been met - 0 + 0x0 Latched Criteria has been met - 1 + 0x1 @@ -35383,12 +35816,12 @@ POSSIBILITY OF SUCH DAMAGE. NotLatched Criteria has not been met - 0 + 0x0 Latched Criteria has been met - 1 + 0x1 @@ -35401,12 +35834,12 @@ POSSIBILITY OF SUCH DAMAGE. NotLatched Criteria has not been met - 0 + 0x0 Latched Criteria has been met - 1 + 0x1 @@ -35419,12 +35852,12 @@ POSSIBILITY OF SUCH DAMAGE. NotLatched Criteria has not been met - 0 + 0x0 Latched Criteria has been met - 1 + 0x1 @@ -35437,12 +35870,12 @@ POSSIBILITY OF SUCH DAMAGE. NotLatched Criteria has not been met - 0 + 0x0 Latched Criteria has been met - 1 + 0x1 @@ -35455,12 +35888,12 @@ POSSIBILITY OF SUCH DAMAGE. NotLatched Criteria has not been met - 0 + 0x0 Latched Criteria has been met - 1 + 0x1 @@ -35473,12 +35906,12 @@ POSSIBILITY OF SUCH DAMAGE. NotLatched Criteria has not been met - 0 + 0x0 Latched Criteria has been met - 1 + 0x1 @@ -35491,12 +35924,12 @@ POSSIBILITY OF SUCH DAMAGE. NotLatched Criteria has not been met - 0 + 0x0 Latched Criteria has been met - 1 + 0x1 @@ -35509,12 +35942,12 @@ POSSIBILITY OF SUCH DAMAGE. NotLatched Criteria has not been met - 0 + 0x0 Latched Criteria has been met - 1 + 0x1 @@ -35527,12 +35960,12 @@ POSSIBILITY OF SUCH DAMAGE. NotLatched Criteria has not been met - 0 + 0x0 Latched Criteria has been met - 1 + 0x1 @@ -35545,12 +35978,12 @@ POSSIBILITY OF SUCH DAMAGE. NotLatched Criteria has not been met - 0 + 0x0 Latched Criteria has been met - 1 + 0x1 @@ -35563,12 +35996,12 @@ POSSIBILITY OF SUCH DAMAGE. NotLatched Criteria has not been met - 0 + 0x0 Latched Criteria has been met - 1 + 0x1 @@ -35579,6 +36012,7 @@ POSSIBILITY OF SUCH DAMAGE. Select between default DETECT signal behavior and LDETECT mode (For non-secure pin only) 0x024 read-write + 0x00000000 DETECTMODE @@ -35589,12 +36023,12 @@ POSSIBILITY OF SUCH DAMAGE. Default DETECT directly connected to PIN DETECT signals - 0 + 0x0 LDETECT Use the latched LDETECT behavior - 1 + 0x1 @@ -35605,6 +36039,7 @@ POSSIBILITY OF SUCH DAMAGE. Select between default DETECT signal behavior and LDETECT mode (For secure pin only) 0x028 read-write + 0x00000000 DETECTMODE @@ -35615,12 +36050,12 @@ POSSIBILITY OF SUCH DAMAGE. Default DETECT directly connected to PIN DETECT signals - 0 + 0x0 LDETECT Use the latched LDETECT behavior - 1 + 0x1 @@ -35644,12 +36079,12 @@ POSSIBILITY OF SUCH DAMAGE. Input Configure pin as an input pin - 0 + 0x0 Output Configure pin as an output pin - 1 + 0x1 @@ -35662,12 +36097,12 @@ POSSIBILITY OF SUCH DAMAGE. Connect Connect input buffer - 0 + 0x0 Disconnect Disconnect input buffer - 1 + 0x1 @@ -35680,17 +36115,17 @@ POSSIBILITY OF SUCH DAMAGE. Disabled No pull - 0 + 0x0 Pulldown Pull down on pin - 1 + 0x1 Pullup Pull up on pin - 3 + 0x3 @@ -35703,42 +36138,42 @@ POSSIBILITY OF SUCH DAMAGE. S0S1 Standard '0', standard '1' - 0 + 0x0 H0S1 High drive '0', standard '1' - 1 + 0x1 S0H1 Standard '0', high drive '1' - 2 + 0x2 H0H1 High drive '0', high 'drive '1'' - 3 + 0x3 D0S1 Disconnect '0', standard '1' (normally used for wired-or connections) - 4 + 0x4 D0H1 Disconnect '0', high drive '1' (normally used for wired-or connections) - 5 + 0x5 S0D1 Standard '0', disconnect '1' (normally used for wired-and connections) - 6 + 0x6 H0D1 High drive '0', disconnect '1' (normally used for wired-and connections) - 7 + 0x7 @@ -35751,17 +36186,17 @@ POSSIBILITY OF SUCH DAMAGE. Disabled Disabled - 0 + 0x0 High Sense for high level - 2 + 0x2 Low Sense for low level - 3 + 0x3 @@ -35774,7 +36209,8 @@ POSSIBILITY OF SUCH DAMAGE. GPIO Port 1 0x50842500 - + + \ No newline at end of file diff --git a/mdk/nrf9120_bitfields.h b/mdk/nrf9120_bitfields.h index 2a1b529f4..7781ec724 100644 --- a/mdk/nrf9120_bitfields.h +++ b/mdk/nrf9120_bitfields.h @@ -51,7 +51,7 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: APPROTECT_SECUREAPPROTECT_FORCEPROTECT */ /* Description: Software force SECUREAPPROTECT mechanism */ -/* Bit 9 : Write 0x1 to force enable SECUREAPPROTECT mechanism, which will remain set until the next reset */ +/* Bit 9 : Write 0x1 to force enable SECUREAPPROTECT mechanism */ #define APPROTECT_SECUREAPPROTECT_FORCEPROTECT_FORCEPROTECT_Pos (9UL) /*!< Position of FORCEPROTECT field. */ #define APPROTECT_SECUREAPPROTECT_FORCEPROTECT_FORCEPROTECT_Msk (0x1UL << APPROTECT_SECUREAPPROTECT_FORCEPROTECT_FORCEPROTECT_Pos) /*!< Bit mask of FORCEPROTECT field. */ #define APPROTECT_SECUREAPPROTECT_FORCEPROTECT_FORCEPROTECT_Force (0x1UL) /*!< Software force enable SECUREAPPROTECT mechanism */ @@ -67,7 +67,7 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: APPROTECT_APPROTECT_FORCEPROTECT */ /* Description: Software force APPROTECT mechanism */ -/* Bit 9 : Write 0x1 to force enable APPROTECT mechanism, which will remain set until the next reset */ +/* Bit 9 : Write 0x1 to force enable APPROTECT mechanism */ #define APPROTECT_APPROTECT_FORCEPROTECT_FORCEPROTECT_Pos (9UL) /*!< Position of FORCEPROTECT field. */ #define APPROTECT_APPROTECT_FORCEPROTECT_FORCEPROTECT_Msk (0x1UL << APPROTECT_APPROTECT_FORCEPROTECT_FORCEPROTECT_Pos) /*!< Bit mask of FORCEPROTECT field. */ #define APPROTECT_APPROTECT_FORCEPROTECT_FORCEPROTECT_Force (0x1UL) /*!< Software force enable APPROTECT mechanism */ @@ -82,9 +82,9 @@ POSSIBILITY OF SUCH DAMAGE. /* Bits 1..0 : Select the source of the HW key that is used by the AES engine */ #define CC_HOST_RGF_HOST_CRYPTOKEY_SEL_HOST_CRYPTOKEY_SEL_Pos (0UL) /*!< Position of HOST_CRYPTOKEY_SEL field. */ #define CC_HOST_RGF_HOST_CRYPTOKEY_SEL_HOST_CRYPTOKEY_SEL_Msk (0x3UL << CC_HOST_RGF_HOST_CRYPTOKEY_SEL_HOST_CRYPTOKEY_SEL_Pos) /*!< Bit mask of HOST_CRYPTOKEY_SEL field. */ -#define CC_HOST_RGF_HOST_CRYPTOKEY_SEL_HOST_CRYPTOKEY_SEL_K_DR (0UL) /*!< Use device root key K_DR from CRYPTOCELL AO power domain */ -#define CC_HOST_RGF_HOST_CRYPTOKEY_SEL_HOST_CRYPTOKEY_SEL_K_PRTL (1UL) /*!< Use hard-coded RTL key K_PRTL */ -#define CC_HOST_RGF_HOST_CRYPTOKEY_SEL_HOST_CRYPTOKEY_SEL_Session (2UL) /*!< Use provided session key */ +#define CC_HOST_RGF_HOST_CRYPTOKEY_SEL_HOST_CRYPTOKEY_SEL_K_DR (0x0UL) /*!< Use device root key K_DR from CRYPTOCELL AO power domain */ +#define CC_HOST_RGF_HOST_CRYPTOKEY_SEL_HOST_CRYPTOKEY_SEL_K_PRTL (0x1UL) /*!< Use hard-coded RTL key K_PRTL */ +#define CC_HOST_RGF_HOST_CRYPTOKEY_SEL_HOST_CRYPTOKEY_SEL_Session (0x2UL) /*!< Use provided session key */ /* Register: CC_HOST_RGF_HOST_IOT_KPRTL_LOCK */ /* Description: This write-once register is the K_PRTL lock register. When this register is set, K_PRTL cannot be used and a zeroed key will be used instead. The value of this register is saved in the CRYPTOCELL AO power domain. */ @@ -92,8 +92,8 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 0 : This register is the K_PRTL lock register. When this register is set, K_PRTL cannot be used and a zeroed key will be used instead. The value of this register is saved in the CRYPTOCELL AO power domain. */ #define CC_HOST_RGF_HOST_IOT_KPRTL_LOCK_HOST_IOT_KPRTL_LOCK_Pos (0UL) /*!< Position of HOST_IOT_KPRTL_LOCK field. */ #define CC_HOST_RGF_HOST_IOT_KPRTL_LOCK_HOST_IOT_KPRTL_LOCK_Msk (0x1UL << CC_HOST_RGF_HOST_IOT_KPRTL_LOCK_HOST_IOT_KPRTL_LOCK_Pos) /*!< Bit mask of HOST_IOT_KPRTL_LOCK field. */ -#define CC_HOST_RGF_HOST_IOT_KPRTL_LOCK_HOST_IOT_KPRTL_LOCK_Disabled (0UL) /*!< K_PRTL can be selected for use from register HOST_CRYPTOKEY_SEL */ -#define CC_HOST_RGF_HOST_IOT_KPRTL_LOCK_HOST_IOT_KPRTL_LOCK_Enabled (1UL) /*!< K_PRTL has been locked until next power-on reset (POR). If K_PRTL is selected anyway, a zeroed key will be used instead. */ +#define CC_HOST_RGF_HOST_IOT_KPRTL_LOCK_HOST_IOT_KPRTL_LOCK_Disabled (0x0UL) /*!< K_PRTL can be selected for use from register HOST_CRYPTOKEY_SEL */ +#define CC_HOST_RGF_HOST_IOT_KPRTL_LOCK_HOST_IOT_KPRTL_LOCK_Enabled (0x1UL) /*!< K_PRTL has been locked until next power-on reset (POR). If K_PRTL is selected anyway, a zeroed key will be used instead. */ /* Register: CC_HOST_RGF_HOST_IOT_KDR0 */ /* Description: This register holds bits 31:0 of K_DR. The value of this register is saved in the CRYPTOCELL AO power domain. Reading from this address returns the K_DR valid status indicating if K_DR is successfully retained. */ @@ -129,14 +129,14 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 8 : Read-only field. Indicates if CRYPTOCELL LCS has been successfully configured since last reset. */ #define CC_HOST_RGF_HOST_IOT_LCS_LCS_IS_VALID_Pos (8UL) /*!< Position of LCS_IS_VALID field. */ #define CC_HOST_RGF_HOST_IOT_LCS_LCS_IS_VALID_Msk (0x1UL << CC_HOST_RGF_HOST_IOT_LCS_LCS_IS_VALID_Pos) /*!< Bit mask of LCS_IS_VALID field. */ -#define CC_HOST_RGF_HOST_IOT_LCS_LCS_IS_VALID_Invalid (0UL) /*!< Valid LCS not yet retained in the CRYPTOCELL AO power domain */ -#define CC_HOST_RGF_HOST_IOT_LCS_LCS_IS_VALID_Valid (1UL) /*!< Valid LCS successfully retained in the CRYPTOCELL AO power domain */ +#define CC_HOST_RGF_HOST_IOT_LCS_LCS_IS_VALID_Invalid (0x0UL) /*!< Valid LCS not yet retained in the CRYPTOCELL AO power domain */ +#define CC_HOST_RGF_HOST_IOT_LCS_LCS_IS_VALID_Valid (0x1UL) /*!< Valid LCS successfully retained in the CRYPTOCELL AO power domain */ /* Bits 2..0 : Lifecycle state value. This field is write-once per reset. */ #define CC_HOST_RGF_HOST_IOT_LCS_LCS_Pos (0UL) /*!< Position of LCS field. */ #define CC_HOST_RGF_HOST_IOT_LCS_LCS_Msk (0x7UL << CC_HOST_RGF_HOST_IOT_LCS_LCS_Pos) /*!< Bit mask of LCS field. */ -#define CC_HOST_RGF_HOST_IOT_LCS_LCS_Debug (0UL) /*!< CC310 operates in debug mode */ -#define CC_HOST_RGF_HOST_IOT_LCS_LCS_Secure (2UL) /*!< CC310 operates in secure mode */ +#define CC_HOST_RGF_HOST_IOT_LCS_LCS_Debug (0x0UL) /*!< CC310 operates in debug mode */ +#define CC_HOST_RGF_HOST_IOT_LCS_LCS_Secure (0x2UL) /*!< CC310 operates in secure mode */ /* Peripheral: CLOCK */ @@ -148,7 +148,7 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 0 : Start HFCLK source */ #define CLOCK_TASKS_HFCLKSTART_TASKS_HFCLKSTART_Pos (0UL) /*!< Position of TASKS_HFCLKSTART field. */ #define CLOCK_TASKS_HFCLKSTART_TASKS_HFCLKSTART_Msk (0x1UL << CLOCK_TASKS_HFCLKSTART_TASKS_HFCLKSTART_Pos) /*!< Bit mask of TASKS_HFCLKSTART field. */ -#define CLOCK_TASKS_HFCLKSTART_TASKS_HFCLKSTART_Trigger (1UL) /*!< Trigger task */ +#define CLOCK_TASKS_HFCLKSTART_TASKS_HFCLKSTART_Trigger (0x1UL) /*!< Trigger task */ /* Register: CLOCK_TASKS_HFCLKSTOP */ /* Description: Stop HFCLK source */ @@ -156,7 +156,7 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 0 : Stop HFCLK source */ #define CLOCK_TASKS_HFCLKSTOP_TASKS_HFCLKSTOP_Pos (0UL) /*!< Position of TASKS_HFCLKSTOP field. */ #define CLOCK_TASKS_HFCLKSTOP_TASKS_HFCLKSTOP_Msk (0x1UL << CLOCK_TASKS_HFCLKSTOP_TASKS_HFCLKSTOP_Pos) /*!< Bit mask of TASKS_HFCLKSTOP field. */ -#define CLOCK_TASKS_HFCLKSTOP_TASKS_HFCLKSTOP_Trigger (1UL) /*!< Trigger task */ +#define CLOCK_TASKS_HFCLKSTOP_TASKS_HFCLKSTOP_Trigger (0x1UL) /*!< Trigger task */ /* Register: CLOCK_TASKS_LFCLKSTART */ /* Description: Start LFCLK source */ @@ -164,7 +164,7 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 0 : Start LFCLK source */ #define CLOCK_TASKS_LFCLKSTART_TASKS_LFCLKSTART_Pos (0UL) /*!< Position of TASKS_LFCLKSTART field. */ #define CLOCK_TASKS_LFCLKSTART_TASKS_LFCLKSTART_Msk (0x1UL << CLOCK_TASKS_LFCLKSTART_TASKS_LFCLKSTART_Pos) /*!< Bit mask of TASKS_LFCLKSTART field. */ -#define CLOCK_TASKS_LFCLKSTART_TASKS_LFCLKSTART_Trigger (1UL) /*!< Trigger task */ +#define CLOCK_TASKS_LFCLKSTART_TASKS_LFCLKSTART_Trigger (0x1UL) /*!< Trigger task */ /* Register: CLOCK_TASKS_LFCLKSTOP */ /* Description: Stop LFCLK source */ @@ -172,7 +172,7 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 0 : Stop LFCLK source */ #define CLOCK_TASKS_LFCLKSTOP_TASKS_LFCLKSTOP_Pos (0UL) /*!< Position of TASKS_LFCLKSTOP field. */ #define CLOCK_TASKS_LFCLKSTOP_TASKS_LFCLKSTOP_Msk (0x1UL << CLOCK_TASKS_LFCLKSTOP_TASKS_LFCLKSTOP_Pos) /*!< Bit mask of TASKS_LFCLKSTOP field. */ -#define CLOCK_TASKS_LFCLKSTOP_TASKS_LFCLKSTOP_Trigger (1UL) /*!< Trigger task */ +#define CLOCK_TASKS_LFCLKSTOP_TASKS_LFCLKSTOP_Trigger (0x1UL) /*!< Trigger task */ /* Register: CLOCK_SUBSCRIBE_HFCLKSTART */ /* Description: Subscribe configuration for task HFCLKSTART */ @@ -180,8 +180,8 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 31 : */ #define CLOCK_SUBSCRIBE_HFCLKSTART_EN_Pos (31UL) /*!< Position of EN field. */ #define CLOCK_SUBSCRIBE_HFCLKSTART_EN_Msk (0x1UL << CLOCK_SUBSCRIBE_HFCLKSTART_EN_Pos) /*!< Bit mask of EN field. */ -#define CLOCK_SUBSCRIBE_HFCLKSTART_EN_Disabled (0UL) /*!< Disable subscription */ -#define CLOCK_SUBSCRIBE_HFCLKSTART_EN_Enabled (1UL) /*!< Enable subscription */ +#define CLOCK_SUBSCRIBE_HFCLKSTART_EN_Disabled (0x0UL) /*!< Disable subscription */ +#define CLOCK_SUBSCRIBE_HFCLKSTART_EN_Enabled (0x1UL) /*!< Enable subscription */ /* Bits 7..0 : DPPI channel that task HFCLKSTART will subscribe to */ #define CLOCK_SUBSCRIBE_HFCLKSTART_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ @@ -193,8 +193,8 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 31 : */ #define CLOCK_SUBSCRIBE_HFCLKSTOP_EN_Pos (31UL) /*!< Position of EN field. */ #define CLOCK_SUBSCRIBE_HFCLKSTOP_EN_Msk (0x1UL << CLOCK_SUBSCRIBE_HFCLKSTOP_EN_Pos) /*!< Bit mask of EN field. */ -#define CLOCK_SUBSCRIBE_HFCLKSTOP_EN_Disabled (0UL) /*!< Disable subscription */ -#define CLOCK_SUBSCRIBE_HFCLKSTOP_EN_Enabled (1UL) /*!< Enable subscription */ +#define CLOCK_SUBSCRIBE_HFCLKSTOP_EN_Disabled (0x0UL) /*!< Disable subscription */ +#define CLOCK_SUBSCRIBE_HFCLKSTOP_EN_Enabled (0x1UL) /*!< Enable subscription */ /* Bits 7..0 : DPPI channel that task HFCLKSTOP will subscribe to */ #define CLOCK_SUBSCRIBE_HFCLKSTOP_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ @@ -206,8 +206,8 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 31 : */ #define CLOCK_SUBSCRIBE_LFCLKSTART_EN_Pos (31UL) /*!< Position of EN field. */ #define CLOCK_SUBSCRIBE_LFCLKSTART_EN_Msk (0x1UL << CLOCK_SUBSCRIBE_LFCLKSTART_EN_Pos) /*!< Bit mask of EN field. */ -#define CLOCK_SUBSCRIBE_LFCLKSTART_EN_Disabled (0UL) /*!< Disable subscription */ -#define CLOCK_SUBSCRIBE_LFCLKSTART_EN_Enabled (1UL) /*!< Enable subscription */ +#define CLOCK_SUBSCRIBE_LFCLKSTART_EN_Disabled (0x0UL) /*!< Disable subscription */ +#define CLOCK_SUBSCRIBE_LFCLKSTART_EN_Enabled (0x1UL) /*!< Enable subscription */ /* Bits 7..0 : DPPI channel that task LFCLKSTART will subscribe to */ #define CLOCK_SUBSCRIBE_LFCLKSTART_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ @@ -219,8 +219,8 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 31 : */ #define CLOCK_SUBSCRIBE_LFCLKSTOP_EN_Pos (31UL) /*!< Position of EN field. */ #define CLOCK_SUBSCRIBE_LFCLKSTOP_EN_Msk (0x1UL << CLOCK_SUBSCRIBE_LFCLKSTOP_EN_Pos) /*!< Bit mask of EN field. */ -#define CLOCK_SUBSCRIBE_LFCLKSTOP_EN_Disabled (0UL) /*!< Disable subscription */ -#define CLOCK_SUBSCRIBE_LFCLKSTOP_EN_Enabled (1UL) /*!< Enable subscription */ +#define CLOCK_SUBSCRIBE_LFCLKSTOP_EN_Disabled (0x0UL) /*!< Disable subscription */ +#define CLOCK_SUBSCRIBE_LFCLKSTOP_EN_Enabled (0x1UL) /*!< Enable subscription */ /* Bits 7..0 : DPPI channel that task LFCLKSTOP will subscribe to */ #define CLOCK_SUBSCRIBE_LFCLKSTOP_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ @@ -232,8 +232,8 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 0 : HFCLK oscillator started */ #define CLOCK_EVENTS_HFCLKSTARTED_EVENTS_HFCLKSTARTED_Pos (0UL) /*!< Position of EVENTS_HFCLKSTARTED field. */ #define CLOCK_EVENTS_HFCLKSTARTED_EVENTS_HFCLKSTARTED_Msk (0x1UL << CLOCK_EVENTS_HFCLKSTARTED_EVENTS_HFCLKSTARTED_Pos) /*!< Bit mask of EVENTS_HFCLKSTARTED field. */ -#define CLOCK_EVENTS_HFCLKSTARTED_EVENTS_HFCLKSTARTED_NotGenerated (0UL) /*!< Event not generated */ -#define CLOCK_EVENTS_HFCLKSTARTED_EVENTS_HFCLKSTARTED_Generated (1UL) /*!< Event generated */ +#define CLOCK_EVENTS_HFCLKSTARTED_EVENTS_HFCLKSTARTED_NotGenerated (0x0UL) /*!< Event not generated */ +#define CLOCK_EVENTS_HFCLKSTARTED_EVENTS_HFCLKSTARTED_Generated (0x1UL) /*!< Event generated */ /* Register: CLOCK_EVENTS_LFCLKSTARTED */ /* Description: LFCLK started */ @@ -241,8 +241,8 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 0 : LFCLK started */ #define CLOCK_EVENTS_LFCLKSTARTED_EVENTS_LFCLKSTARTED_Pos (0UL) /*!< Position of EVENTS_LFCLKSTARTED field. */ #define CLOCK_EVENTS_LFCLKSTARTED_EVENTS_LFCLKSTARTED_Msk (0x1UL << CLOCK_EVENTS_LFCLKSTARTED_EVENTS_LFCLKSTARTED_Pos) /*!< Bit mask of EVENTS_LFCLKSTARTED field. */ -#define CLOCK_EVENTS_LFCLKSTARTED_EVENTS_LFCLKSTARTED_NotGenerated (0UL) /*!< Event not generated */ -#define CLOCK_EVENTS_LFCLKSTARTED_EVENTS_LFCLKSTARTED_Generated (1UL) /*!< Event generated */ +#define CLOCK_EVENTS_LFCLKSTARTED_EVENTS_LFCLKSTARTED_NotGenerated (0x0UL) /*!< Event not generated */ +#define CLOCK_EVENTS_LFCLKSTARTED_EVENTS_LFCLKSTARTED_Generated (0x1UL) /*!< Event generated */ /* Register: CLOCK_PUBLISH_HFCLKSTARTED */ /* Description: Publish configuration for event HFCLKSTARTED */ @@ -250,8 +250,8 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 31 : */ #define CLOCK_PUBLISH_HFCLKSTARTED_EN_Pos (31UL) /*!< Position of EN field. */ #define CLOCK_PUBLISH_HFCLKSTARTED_EN_Msk (0x1UL << CLOCK_PUBLISH_HFCLKSTARTED_EN_Pos) /*!< Bit mask of EN field. */ -#define CLOCK_PUBLISH_HFCLKSTARTED_EN_Disabled (0UL) /*!< Disable publishing */ -#define CLOCK_PUBLISH_HFCLKSTARTED_EN_Enabled (1UL) /*!< Enable publishing */ +#define CLOCK_PUBLISH_HFCLKSTARTED_EN_Disabled (0x0UL) /*!< Disable publishing */ +#define CLOCK_PUBLISH_HFCLKSTARTED_EN_Enabled (0x1UL) /*!< Enable publishing */ /* Bits 7..0 : DPPI channel that event HFCLKSTARTED will publish to */ #define CLOCK_PUBLISH_HFCLKSTARTED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ @@ -263,8 +263,8 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 31 : */ #define CLOCK_PUBLISH_LFCLKSTARTED_EN_Pos (31UL) /*!< Position of EN field. */ #define CLOCK_PUBLISH_LFCLKSTARTED_EN_Msk (0x1UL << CLOCK_PUBLISH_LFCLKSTARTED_EN_Pos) /*!< Bit mask of EN field. */ -#define CLOCK_PUBLISH_LFCLKSTARTED_EN_Disabled (0UL) /*!< Disable publishing */ -#define CLOCK_PUBLISH_LFCLKSTARTED_EN_Enabled (1UL) /*!< Enable publishing */ +#define CLOCK_PUBLISH_LFCLKSTARTED_EN_Disabled (0x0UL) /*!< Disable publishing */ +#define CLOCK_PUBLISH_LFCLKSTARTED_EN_Enabled (0x1UL) /*!< Enable publishing */ /* Bits 7..0 : DPPI channel that event LFCLKSTARTED will publish to */ #define CLOCK_PUBLISH_LFCLKSTARTED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ @@ -276,14 +276,14 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 1 : Enable or disable interrupt for event LFCLKSTARTED */ #define CLOCK_INTEN_LFCLKSTARTED_Pos (1UL) /*!< Position of LFCLKSTARTED field. */ #define CLOCK_INTEN_LFCLKSTARTED_Msk (0x1UL << CLOCK_INTEN_LFCLKSTARTED_Pos) /*!< Bit mask of LFCLKSTARTED field. */ -#define CLOCK_INTEN_LFCLKSTARTED_Disabled (0UL) /*!< Disable */ -#define CLOCK_INTEN_LFCLKSTARTED_Enabled (1UL) /*!< Enable */ +#define CLOCK_INTEN_LFCLKSTARTED_Disabled (0x0UL) /*!< Disable */ +#define CLOCK_INTEN_LFCLKSTARTED_Enabled (0x1UL) /*!< Enable */ /* Bit 0 : Enable or disable interrupt for event HFCLKSTARTED */ #define CLOCK_INTEN_HFCLKSTARTED_Pos (0UL) /*!< Position of HFCLKSTARTED field. */ #define CLOCK_INTEN_HFCLKSTARTED_Msk (0x1UL << CLOCK_INTEN_HFCLKSTARTED_Pos) /*!< Bit mask of HFCLKSTARTED field. */ -#define CLOCK_INTEN_HFCLKSTARTED_Disabled (0UL) /*!< Disable */ -#define CLOCK_INTEN_HFCLKSTARTED_Enabled (1UL) /*!< Enable */ +#define CLOCK_INTEN_HFCLKSTARTED_Disabled (0x0UL) /*!< Disable */ +#define CLOCK_INTEN_HFCLKSTARTED_Enabled (0x1UL) /*!< Enable */ /* Register: CLOCK_INTENSET */ /* Description: Enable interrupt */ @@ -291,16 +291,16 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 1 : Write '1' to enable interrupt for event LFCLKSTARTED */ #define CLOCK_INTENSET_LFCLKSTARTED_Pos (1UL) /*!< Position of LFCLKSTARTED field. */ #define CLOCK_INTENSET_LFCLKSTARTED_Msk (0x1UL << CLOCK_INTENSET_LFCLKSTARTED_Pos) /*!< Bit mask of LFCLKSTARTED field. */ -#define CLOCK_INTENSET_LFCLKSTARTED_Disabled (0UL) /*!< Read: Disabled */ -#define CLOCK_INTENSET_LFCLKSTARTED_Enabled (1UL) /*!< Read: Enabled */ -#define CLOCK_INTENSET_LFCLKSTARTED_Set (1UL) /*!< Enable */ +#define CLOCK_INTENSET_LFCLKSTARTED_Disabled (0x0UL) /*!< Read: Disabled */ +#define CLOCK_INTENSET_LFCLKSTARTED_Enabled (0x1UL) /*!< Read: Enabled */ +#define CLOCK_INTENSET_LFCLKSTARTED_Set (0x1UL) /*!< Enable */ /* Bit 0 : Write '1' to enable interrupt for event HFCLKSTARTED */ #define CLOCK_INTENSET_HFCLKSTARTED_Pos (0UL) /*!< Position of HFCLKSTARTED field. */ #define CLOCK_INTENSET_HFCLKSTARTED_Msk (0x1UL << CLOCK_INTENSET_HFCLKSTARTED_Pos) /*!< Bit mask of HFCLKSTARTED field. */ -#define CLOCK_INTENSET_HFCLKSTARTED_Disabled (0UL) /*!< Read: Disabled */ -#define CLOCK_INTENSET_HFCLKSTARTED_Enabled (1UL) /*!< Read: Enabled */ -#define CLOCK_INTENSET_HFCLKSTARTED_Set (1UL) /*!< Enable */ +#define CLOCK_INTENSET_HFCLKSTARTED_Disabled (0x0UL) /*!< Read: Disabled */ +#define CLOCK_INTENSET_HFCLKSTARTED_Enabled (0x1UL) /*!< Read: Enabled */ +#define CLOCK_INTENSET_HFCLKSTARTED_Set (0x1UL) /*!< Enable */ /* Register: CLOCK_INTENCLR */ /* Description: Disable interrupt */ @@ -308,16 +308,16 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 1 : Write '1' to disable interrupt for event LFCLKSTARTED */ #define CLOCK_INTENCLR_LFCLKSTARTED_Pos (1UL) /*!< Position of LFCLKSTARTED field. */ #define CLOCK_INTENCLR_LFCLKSTARTED_Msk (0x1UL << CLOCK_INTENCLR_LFCLKSTARTED_Pos) /*!< Bit mask of LFCLKSTARTED field. */ -#define CLOCK_INTENCLR_LFCLKSTARTED_Disabled (0UL) /*!< Read: Disabled */ -#define CLOCK_INTENCLR_LFCLKSTARTED_Enabled (1UL) /*!< Read: Enabled */ -#define CLOCK_INTENCLR_LFCLKSTARTED_Clear (1UL) /*!< Disable */ +#define CLOCK_INTENCLR_LFCLKSTARTED_Disabled (0x0UL) /*!< Read: Disabled */ +#define CLOCK_INTENCLR_LFCLKSTARTED_Enabled (0x1UL) /*!< Read: Enabled */ +#define CLOCK_INTENCLR_LFCLKSTARTED_Clear (0x1UL) /*!< Disable */ /* Bit 0 : Write '1' to disable interrupt for event HFCLKSTARTED */ #define CLOCK_INTENCLR_HFCLKSTARTED_Pos (0UL) /*!< Position of HFCLKSTARTED field. */ #define CLOCK_INTENCLR_HFCLKSTARTED_Msk (0x1UL << CLOCK_INTENCLR_HFCLKSTARTED_Pos) /*!< Bit mask of HFCLKSTARTED field. */ -#define CLOCK_INTENCLR_HFCLKSTARTED_Disabled (0UL) /*!< Read: Disabled */ -#define CLOCK_INTENCLR_HFCLKSTARTED_Enabled (1UL) /*!< Read: Enabled */ -#define CLOCK_INTENCLR_HFCLKSTARTED_Clear (1UL) /*!< Disable */ +#define CLOCK_INTENCLR_HFCLKSTARTED_Disabled (0x0UL) /*!< Read: Disabled */ +#define CLOCK_INTENCLR_HFCLKSTARTED_Enabled (0x1UL) /*!< Read: Enabled */ +#define CLOCK_INTENCLR_HFCLKSTARTED_Clear (0x1UL) /*!< Disable */ /* Register: CLOCK_INTPEND */ /* Description: Pending interrupts */ @@ -325,14 +325,14 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 1 : Read pending status of interrupt for event LFCLKSTARTED */ #define CLOCK_INTPEND_LFCLKSTARTED_Pos (1UL) /*!< Position of LFCLKSTARTED field. */ #define CLOCK_INTPEND_LFCLKSTARTED_Msk (0x1UL << CLOCK_INTPEND_LFCLKSTARTED_Pos) /*!< Bit mask of LFCLKSTARTED field. */ -#define CLOCK_INTPEND_LFCLKSTARTED_NotPending (0UL) /*!< Read: Not pending */ -#define CLOCK_INTPEND_LFCLKSTARTED_Pending (1UL) /*!< Read: Pending */ +#define CLOCK_INTPEND_LFCLKSTARTED_NotPending (0x0UL) /*!< Read: Not pending */ +#define CLOCK_INTPEND_LFCLKSTARTED_Pending (0x1UL) /*!< Read: Pending */ /* Bit 0 : Read pending status of interrupt for event HFCLKSTARTED */ #define CLOCK_INTPEND_HFCLKSTARTED_Pos (0UL) /*!< Position of HFCLKSTARTED field. */ #define CLOCK_INTPEND_HFCLKSTARTED_Msk (0x1UL << CLOCK_INTPEND_HFCLKSTARTED_Pos) /*!< Bit mask of HFCLKSTARTED field. */ -#define CLOCK_INTPEND_HFCLKSTARTED_NotPending (0UL) /*!< Read: Not pending */ -#define CLOCK_INTPEND_HFCLKSTARTED_Pending (1UL) /*!< Read: Pending */ +#define CLOCK_INTPEND_HFCLKSTARTED_NotPending (0x0UL) /*!< Read: Not pending */ +#define CLOCK_INTPEND_HFCLKSTARTED_Pending (0x1UL) /*!< Read: Pending */ /* Register: CLOCK_HFCLKRUN */ /* Description: Status indicating that HFCLKSTART task has been triggered */ @@ -340,8 +340,8 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 0 : HFCLKSTART task triggered or not */ #define CLOCK_HFCLKRUN_STATUS_Pos (0UL) /*!< Position of STATUS field. */ #define CLOCK_HFCLKRUN_STATUS_Msk (0x1UL << CLOCK_HFCLKRUN_STATUS_Pos) /*!< Bit mask of STATUS field. */ -#define CLOCK_HFCLKRUN_STATUS_NotTriggered (0UL) /*!< Task not triggered */ -#define CLOCK_HFCLKRUN_STATUS_Triggered (1UL) /*!< Task triggered */ +#define CLOCK_HFCLKRUN_STATUS_NotTriggered (0x0UL) /*!< Task not triggered */ +#define CLOCK_HFCLKRUN_STATUS_Triggered (0x1UL) /*!< Task triggered */ /* Register: CLOCK_HFCLKSTAT */ /* Description: The register shows if HFXO has been requested by triggering HFCLKSTART task and if it has been started (STATE) */ @@ -349,14 +349,14 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 16 : HFCLK state */ #define CLOCK_HFCLKSTAT_STATE_Pos (16UL) /*!< Position of STATE field. */ #define CLOCK_HFCLKSTAT_STATE_Msk (0x1UL << CLOCK_HFCLKSTAT_STATE_Pos) /*!< Bit mask of STATE field. */ -#define CLOCK_HFCLKSTAT_STATE_NotRunning (0UL) /*!< HFXO has not been started or HFCLKSTOP task has been triggered */ -#define CLOCK_HFCLKSTAT_STATE_Running (1UL) /*!< HFXO has been started (HFCLKSTARTED event has been generated) */ +#define CLOCK_HFCLKSTAT_STATE_NotRunning (0x0UL) /*!< HFXO has not been started or HFCLKSTOP task has been triggered */ +#define CLOCK_HFCLKSTAT_STATE_Running (0x1UL) /*!< HFXO has been started (HFCLKSTARTED event has been generated) */ /* Bit 0 : Active clock source */ #define CLOCK_HFCLKSTAT_SRC_Pos (0UL) /*!< Position of SRC field. */ #define CLOCK_HFCLKSTAT_SRC_Msk (0x1UL << CLOCK_HFCLKSTAT_SRC_Pos) /*!< Bit mask of SRC field. */ -#define CLOCK_HFCLKSTAT_SRC_HFINT (0UL) /*!< HFINT - 64 MHz on-chip oscillator */ -#define CLOCK_HFCLKSTAT_SRC_HFXO (1UL) /*!< HFXO - 64 MHz clock derived from external 32 MHz crystal oscillator */ +#define CLOCK_HFCLKSTAT_SRC_HFINT (0x0UL) /*!< HFINT - 64 MHz on-chip oscillator */ +#define CLOCK_HFCLKSTAT_SRC_HFXO (0x1UL) /*!< HFXO - 64 MHz clock derived from external 32 MHz crystal oscillator */ /* Register: CLOCK_LFCLKRUN */ /* Description: Status indicating that LFCLKSTART task has been triggered */ @@ -364,8 +364,8 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 0 : LFCLKSTART task triggered or not */ #define CLOCK_LFCLKRUN_STATUS_Pos (0UL) /*!< Position of STATUS field. */ #define CLOCK_LFCLKRUN_STATUS_Msk (0x1UL << CLOCK_LFCLKRUN_STATUS_Pos) /*!< Bit mask of STATUS field. */ -#define CLOCK_LFCLKRUN_STATUS_NotTriggered (0UL) /*!< Task not triggered */ -#define CLOCK_LFCLKRUN_STATUS_Triggered (1UL) /*!< Task triggered */ +#define CLOCK_LFCLKRUN_STATUS_NotTriggered (0x0UL) /*!< Task not triggered */ +#define CLOCK_LFCLKRUN_STATUS_Triggered (0x1UL) /*!< Task triggered */ /* Register: CLOCK_LFCLKSTAT */ /* Description: The register shows which LFCLK source has been requested (SRC) when triggering LFCLKSTART task and if the source has been started (STATE) */ @@ -373,15 +373,15 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 16 : LFCLK state */ #define CLOCK_LFCLKSTAT_STATE_Pos (16UL) /*!< Position of STATE field. */ #define CLOCK_LFCLKSTAT_STATE_Msk (0x1UL << CLOCK_LFCLKSTAT_STATE_Pos) /*!< Bit mask of STATE field. */ -#define CLOCK_LFCLKSTAT_STATE_NotRunning (0UL) /*!< Requested LFCLK source has not been started or LFCLKSTOP task has been triggered */ -#define CLOCK_LFCLKSTAT_STATE_Running (1UL) /*!< Requested LFCLK source has been started (LFCLKSTARTED event has been generated) */ +#define CLOCK_LFCLKSTAT_STATE_NotRunning (0x0UL) /*!< Requested LFCLK source has not been started or LFCLKSTOP task has been triggered */ +#define CLOCK_LFCLKSTAT_STATE_Running (0x1UL) /*!< Requested LFCLK source has been started (LFCLKSTARTED event has been generated) */ /* Bits 1..0 : Active clock source */ #define CLOCK_LFCLKSTAT_SRC_Pos (0UL) /*!< Position of SRC field. */ #define CLOCK_LFCLKSTAT_SRC_Msk (0x3UL << CLOCK_LFCLKSTAT_SRC_Pos) /*!< Bit mask of SRC field. */ -#define CLOCK_LFCLKSTAT_SRC_RFU (0UL) /*!< Reserved for future use */ -#define CLOCK_LFCLKSTAT_SRC_LFRC (1UL) /*!< 32.768 kHz RC oscillator */ -#define CLOCK_LFCLKSTAT_SRC_LFXO (2UL) /*!< 32.768 kHz crystal oscillator */ +#define CLOCK_LFCLKSTAT_SRC_RFU (0x0UL) /*!< Reserved for future use */ +#define CLOCK_LFCLKSTAT_SRC_LFRC (0x1UL) /*!< 32.768 kHz RC oscillator */ +#define CLOCK_LFCLKSTAT_SRC_LFXO (0x2UL) /*!< 32.768 kHz crystal oscillator */ /* Register: CLOCK_LFCLKSRCCOPY */ /* Description: Copy of LFCLKSRC register, set after LFCLKSTART task has been triggered */ @@ -389,9 +389,9 @@ POSSIBILITY OF SUCH DAMAGE. /* Bits 1..0 : Clock source */ #define CLOCK_LFCLKSRCCOPY_SRC_Pos (0UL) /*!< Position of SRC field. */ #define CLOCK_LFCLKSRCCOPY_SRC_Msk (0x3UL << CLOCK_LFCLKSRCCOPY_SRC_Pos) /*!< Bit mask of SRC field. */ -#define CLOCK_LFCLKSRCCOPY_SRC_RFU (0UL) /*!< Reserved for future use */ -#define CLOCK_LFCLKSRCCOPY_SRC_LFRC (1UL) /*!< 32.768 kHz RC oscillator */ -#define CLOCK_LFCLKSRCCOPY_SRC_LFXO (2UL) /*!< 32.768 kHz crystal oscillator */ +#define CLOCK_LFCLKSRCCOPY_SRC_RFU (0x0UL) /*!< Reserved for future use */ +#define CLOCK_LFCLKSRCCOPY_SRC_LFRC (0x1UL) /*!< 32.768 kHz RC oscillator */ +#define CLOCK_LFCLKSRCCOPY_SRC_LFXO (0x2UL) /*!< 32.768 kHz crystal oscillator */ /* Register: CLOCK_LFCLKSRC */ /* Description: Clock source for the LFCLK. LFCLKSTART task starts starts a clock source selected with this register. */ @@ -399,9 +399,9 @@ POSSIBILITY OF SUCH DAMAGE. /* Bits 1..0 : Clock source */ #define CLOCK_LFCLKSRC_SRC_Pos (0UL) /*!< Position of SRC field. */ #define CLOCK_LFCLKSRC_SRC_Msk (0x3UL << CLOCK_LFCLKSRC_SRC_Pos) /*!< Bit mask of SRC field. */ -#define CLOCK_LFCLKSRC_SRC_RFU (0UL) /*!< Reserved for future use (equals selecting LFRC) */ -#define CLOCK_LFCLKSRC_SRC_LFRC (1UL) /*!< 32.768 kHz RC oscillator */ -#define CLOCK_LFCLKSRC_SRC_LFXO (2UL) /*!< 32.768 kHz crystal oscillator */ +#define CLOCK_LFCLKSRC_SRC_RFU (0x0UL) /*!< Reserved for future use (equals selecting LFRC) */ +#define CLOCK_LFCLKSRC_SRC_LFRC (0x1UL) /*!< 32.768 kHz RC oscillator */ +#define CLOCK_LFCLKSRC_SRC_LFXO (0x2UL) /*!< 32.768 kHz crystal oscillator */ /* Peripheral: CRYPTOCELL */ @@ -413,8 +413,8 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 0 : Enable or disable the CRYPTOCELL subsystem */ #define CRYPTOCELL_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ #define CRYPTOCELL_ENABLE_ENABLE_Msk (0x1UL << CRYPTOCELL_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ -#define CRYPTOCELL_ENABLE_ENABLE_Disabled (0UL) /*!< CRYPTOCELL subsystem disabled */ -#define CRYPTOCELL_ENABLE_ENABLE_Enabled (1UL) /*!< CRYPTOCELL subsystem enabled. */ +#define CRYPTOCELL_ENABLE_ENABLE_Disabled (0x0UL) /*!< CRYPTOCELL subsystem disabled */ +#define CRYPTOCELL_ENABLE_ENABLE_Enabled (0x1UL) /*!< CRYPTOCELL subsystem enabled. */ /* Peripheral: CTRLAPPERI */ @@ -433,8 +433,8 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 0 : Status of data in register RXDATA */ #define CTRLAPPERI_MAILBOX_RXSTATUS_RXSTATUS_Pos (0UL) /*!< Position of RXSTATUS field. */ #define CTRLAPPERI_MAILBOX_RXSTATUS_RXSTATUS_Msk (0x1UL << CTRLAPPERI_MAILBOX_RXSTATUS_RXSTATUS_Pos) /*!< Bit mask of RXSTATUS field. */ -#define CTRLAPPERI_MAILBOX_RXSTATUS_RXSTATUS_NoDataPending (0UL) /*!< No data pending in register RXDATA */ -#define CTRLAPPERI_MAILBOX_RXSTATUS_RXSTATUS_DataPending (1UL) /*!< Data pending in register RXDATA */ +#define CTRLAPPERI_MAILBOX_RXSTATUS_RXSTATUS_NoDataPending (0x0UL) /*!< No data pending in register RXDATA */ +#define CTRLAPPERI_MAILBOX_RXSTATUS_RXSTATUS_DataPending (0x1UL) /*!< Data pending in register RXDATA */ /* Register: CTRLAPPERI_MAILBOX_TXDATA */ /* Description: Data sent from the CPU to the debugger. */ @@ -449,8 +449,8 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 0 : Status of data in register TXDATA */ #define CTRLAPPERI_MAILBOX_TXSTATUS_TXSTATUS_Pos (0UL) /*!< Position of TXSTATUS field. */ #define CTRLAPPERI_MAILBOX_TXSTATUS_TXSTATUS_Msk (0x1UL << CTRLAPPERI_MAILBOX_TXSTATUS_TXSTATUS_Pos) /*!< Bit mask of TXSTATUS field. */ -#define CTRLAPPERI_MAILBOX_TXSTATUS_TXSTATUS_NoDataPending (0UL) /*!< No data pending in register TXDATA */ -#define CTRLAPPERI_MAILBOX_TXSTATUS_TXSTATUS_DataPending (1UL) /*!< Data pending in register TXDATA */ +#define CTRLAPPERI_MAILBOX_TXSTATUS_TXSTATUS_NoDataPending (0x0UL) /*!< No data pending in register TXDATA */ +#define CTRLAPPERI_MAILBOX_TXSTATUS_TXSTATUS_DataPending (0x1UL) /*!< Data pending in register TXDATA */ /* Register: CTRLAPPERI_ERASEPROTECT_LOCK */ /* Description: This register locks the ERASEPROTECT.DISABLE register from being written until next reset. */ @@ -458,8 +458,8 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 0 : Lock ERASEPROTECT.DISABLE register from being written until next reset */ #define CTRLAPPERI_ERASEPROTECT_LOCK_LOCK_Pos (0UL) /*!< Position of LOCK field. */ #define CTRLAPPERI_ERASEPROTECT_LOCK_LOCK_Msk (0x1UL << CTRLAPPERI_ERASEPROTECT_LOCK_LOCK_Pos) /*!< Bit mask of LOCK field. */ -#define CTRLAPPERI_ERASEPROTECT_LOCK_LOCK_Unlocked (0UL) /*!< Register ERASEPROTECT.DISABLE is writeable */ -#define CTRLAPPERI_ERASEPROTECT_LOCK_LOCK_Locked (1UL) /*!< Register ERASEPROTECT.DISABLE is read-only */ +#define CTRLAPPERI_ERASEPROTECT_LOCK_LOCK_Unlocked (0x0UL) /*!< Register ERASEPROTECT.DISABLE is writeable */ +#define CTRLAPPERI_ERASEPROTECT_LOCK_LOCK_Locked (0x1UL) /*!< Register ERASEPROTECT.DISABLE is read-only */ /* Register: CTRLAPPERI_ERASEPROTECT_DISABLE */ /* Description: This register disables the ERASEPROTECT register and performs an ERASEALL operation. */ @@ -478,7 +478,7 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 0 : Enable channel group n */ #define DPPIC_TASKS_CHG_EN_EN_Pos (0UL) /*!< Position of EN field. */ #define DPPIC_TASKS_CHG_EN_EN_Msk (0x1UL << DPPIC_TASKS_CHG_EN_EN_Pos) /*!< Bit mask of EN field. */ -#define DPPIC_TASKS_CHG_EN_EN_Trigger (1UL) /*!< Trigger task */ +#define DPPIC_TASKS_CHG_EN_EN_Trigger (0x1UL) /*!< Trigger task */ /* Register: DPPIC_TASKS_CHG_DIS */ /* Description: Description cluster: Disable channel group n */ @@ -486,7 +486,7 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 0 : Disable channel group n */ #define DPPIC_TASKS_CHG_DIS_DIS_Pos (0UL) /*!< Position of DIS field. */ #define DPPIC_TASKS_CHG_DIS_DIS_Msk (0x1UL << DPPIC_TASKS_CHG_DIS_DIS_Pos) /*!< Bit mask of DIS field. */ -#define DPPIC_TASKS_CHG_DIS_DIS_Trigger (1UL) /*!< Trigger task */ +#define DPPIC_TASKS_CHG_DIS_DIS_Trigger (0x1UL) /*!< Trigger task */ /* Register: DPPIC_SUBSCRIBE_CHG_EN */ /* Description: Description cluster: Subscribe configuration for task CHG[n].EN */ @@ -494,8 +494,8 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 31 : */ #define DPPIC_SUBSCRIBE_CHG_EN_EN_Pos (31UL) /*!< Position of EN field. */ #define DPPIC_SUBSCRIBE_CHG_EN_EN_Msk (0x1UL << DPPIC_SUBSCRIBE_CHG_EN_EN_Pos) /*!< Bit mask of EN field. */ -#define DPPIC_SUBSCRIBE_CHG_EN_EN_Disabled (0UL) /*!< Disable subscription */ -#define DPPIC_SUBSCRIBE_CHG_EN_EN_Enabled (1UL) /*!< Enable subscription */ +#define DPPIC_SUBSCRIBE_CHG_EN_EN_Disabled (0x0UL) /*!< Disable subscription */ +#define DPPIC_SUBSCRIBE_CHG_EN_EN_Enabled (0x1UL) /*!< Enable subscription */ /* Bits 7..0 : DPPI channel that task CHG[n].EN will subscribe to */ #define DPPIC_SUBSCRIBE_CHG_EN_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ @@ -507,8 +507,8 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 31 : */ #define DPPIC_SUBSCRIBE_CHG_DIS_EN_Pos (31UL) /*!< Position of EN field. */ #define DPPIC_SUBSCRIBE_CHG_DIS_EN_Msk (0x1UL << DPPIC_SUBSCRIBE_CHG_DIS_EN_Pos) /*!< Bit mask of EN field. */ -#define DPPIC_SUBSCRIBE_CHG_DIS_EN_Disabled (0UL) /*!< Disable subscription */ -#define DPPIC_SUBSCRIBE_CHG_DIS_EN_Enabled (1UL) /*!< Enable subscription */ +#define DPPIC_SUBSCRIBE_CHG_DIS_EN_Disabled (0x0UL) /*!< Disable subscription */ +#define DPPIC_SUBSCRIBE_CHG_DIS_EN_Enabled (0x1UL) /*!< Enable subscription */ /* Bits 7..0 : DPPI channel that task CHG[n].DIS will subscribe to */ #define DPPIC_SUBSCRIBE_CHG_DIS_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ @@ -520,98 +520,98 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 15 : Enable or disable channel 15 */ #define DPPIC_CHEN_CH15_Pos (15UL) /*!< Position of CH15 field. */ #define DPPIC_CHEN_CH15_Msk (0x1UL << DPPIC_CHEN_CH15_Pos) /*!< Bit mask of CH15 field. */ -#define DPPIC_CHEN_CH15_Disabled (0UL) /*!< Disable channel */ -#define DPPIC_CHEN_CH15_Enabled (1UL) /*!< Enable channel */ +#define DPPIC_CHEN_CH15_Disabled (0x0UL) /*!< Disable channel */ +#define DPPIC_CHEN_CH15_Enabled (0x1UL) /*!< Enable channel */ /* Bit 14 : Enable or disable channel 14 */ #define DPPIC_CHEN_CH14_Pos (14UL) /*!< Position of CH14 field. */ #define DPPIC_CHEN_CH14_Msk (0x1UL << DPPIC_CHEN_CH14_Pos) /*!< Bit mask of CH14 field. */ -#define DPPIC_CHEN_CH14_Disabled (0UL) /*!< Disable channel */ -#define DPPIC_CHEN_CH14_Enabled (1UL) /*!< Enable channel */ +#define DPPIC_CHEN_CH14_Disabled (0x0UL) /*!< Disable channel */ +#define DPPIC_CHEN_CH14_Enabled (0x1UL) /*!< Enable channel */ /* Bit 13 : Enable or disable channel 13 */ #define DPPIC_CHEN_CH13_Pos (13UL) /*!< Position of CH13 field. */ #define DPPIC_CHEN_CH13_Msk (0x1UL << DPPIC_CHEN_CH13_Pos) /*!< Bit mask of CH13 field. */ -#define DPPIC_CHEN_CH13_Disabled (0UL) /*!< Disable channel */ -#define DPPIC_CHEN_CH13_Enabled (1UL) /*!< Enable channel */ +#define DPPIC_CHEN_CH13_Disabled (0x0UL) /*!< Disable channel */ +#define DPPIC_CHEN_CH13_Enabled (0x1UL) /*!< Enable channel */ /* Bit 12 : Enable or disable channel 12 */ #define DPPIC_CHEN_CH12_Pos (12UL) /*!< Position of CH12 field. */ #define DPPIC_CHEN_CH12_Msk (0x1UL << DPPIC_CHEN_CH12_Pos) /*!< Bit mask of CH12 field. */ -#define DPPIC_CHEN_CH12_Disabled (0UL) /*!< Disable channel */ -#define DPPIC_CHEN_CH12_Enabled (1UL) /*!< Enable channel */ +#define DPPIC_CHEN_CH12_Disabled (0x0UL) /*!< Disable channel */ +#define DPPIC_CHEN_CH12_Enabled (0x1UL) /*!< Enable channel */ /* Bit 11 : Enable or disable channel 11 */ #define DPPIC_CHEN_CH11_Pos (11UL) /*!< Position of CH11 field. */ #define DPPIC_CHEN_CH11_Msk (0x1UL << DPPIC_CHEN_CH11_Pos) /*!< Bit mask of CH11 field. */ -#define DPPIC_CHEN_CH11_Disabled (0UL) /*!< Disable channel */ -#define DPPIC_CHEN_CH11_Enabled (1UL) /*!< Enable channel */ +#define DPPIC_CHEN_CH11_Disabled (0x0UL) /*!< Disable channel */ +#define DPPIC_CHEN_CH11_Enabled (0x1UL) /*!< Enable channel */ /* Bit 10 : Enable or disable channel 10 */ #define DPPIC_CHEN_CH10_Pos (10UL) /*!< Position of CH10 field. */ #define DPPIC_CHEN_CH10_Msk (0x1UL << DPPIC_CHEN_CH10_Pos) /*!< Bit mask of CH10 field. */ -#define DPPIC_CHEN_CH10_Disabled (0UL) /*!< Disable channel */ -#define DPPIC_CHEN_CH10_Enabled (1UL) /*!< Enable channel */ +#define DPPIC_CHEN_CH10_Disabled (0x0UL) /*!< Disable channel */ +#define DPPIC_CHEN_CH10_Enabled (0x1UL) /*!< Enable channel */ /* Bit 9 : Enable or disable channel 9 */ #define DPPIC_CHEN_CH9_Pos (9UL) /*!< Position of CH9 field. */ #define DPPIC_CHEN_CH9_Msk (0x1UL << DPPIC_CHEN_CH9_Pos) /*!< Bit mask of CH9 field. */ -#define DPPIC_CHEN_CH9_Disabled (0UL) /*!< Disable channel */ -#define DPPIC_CHEN_CH9_Enabled (1UL) /*!< Enable channel */ +#define DPPIC_CHEN_CH9_Disabled (0x0UL) /*!< Disable channel */ +#define DPPIC_CHEN_CH9_Enabled (0x1UL) /*!< Enable channel */ /* Bit 8 : Enable or disable channel 8 */ #define DPPIC_CHEN_CH8_Pos (8UL) /*!< Position of CH8 field. */ #define DPPIC_CHEN_CH8_Msk (0x1UL << DPPIC_CHEN_CH8_Pos) /*!< Bit mask of CH8 field. */ -#define DPPIC_CHEN_CH8_Disabled (0UL) /*!< Disable channel */ -#define DPPIC_CHEN_CH8_Enabled (1UL) /*!< Enable channel */ +#define DPPIC_CHEN_CH8_Disabled (0x0UL) /*!< Disable channel */ +#define DPPIC_CHEN_CH8_Enabled (0x1UL) /*!< Enable channel */ /* Bit 7 : Enable or disable channel 7 */ #define DPPIC_CHEN_CH7_Pos (7UL) /*!< Position of CH7 field. */ #define DPPIC_CHEN_CH7_Msk (0x1UL << DPPIC_CHEN_CH7_Pos) /*!< Bit mask of CH7 field. */ -#define DPPIC_CHEN_CH7_Disabled (0UL) /*!< Disable channel */ -#define DPPIC_CHEN_CH7_Enabled (1UL) /*!< Enable channel */ +#define DPPIC_CHEN_CH7_Disabled (0x0UL) /*!< Disable channel */ +#define DPPIC_CHEN_CH7_Enabled (0x1UL) /*!< Enable channel */ /* Bit 6 : Enable or disable channel 6 */ #define DPPIC_CHEN_CH6_Pos (6UL) /*!< Position of CH6 field. */ #define DPPIC_CHEN_CH6_Msk (0x1UL << DPPIC_CHEN_CH6_Pos) /*!< Bit mask of CH6 field. */ -#define DPPIC_CHEN_CH6_Disabled (0UL) /*!< Disable channel */ -#define DPPIC_CHEN_CH6_Enabled (1UL) /*!< Enable channel */ +#define DPPIC_CHEN_CH6_Disabled (0x0UL) /*!< Disable channel */ +#define DPPIC_CHEN_CH6_Enabled (0x1UL) /*!< Enable channel */ /* Bit 5 : Enable or disable channel 5 */ #define DPPIC_CHEN_CH5_Pos (5UL) /*!< Position of CH5 field. */ #define DPPIC_CHEN_CH5_Msk (0x1UL << DPPIC_CHEN_CH5_Pos) /*!< Bit mask of CH5 field. */ -#define DPPIC_CHEN_CH5_Disabled (0UL) /*!< Disable channel */ -#define DPPIC_CHEN_CH5_Enabled (1UL) /*!< Enable channel */ +#define DPPIC_CHEN_CH5_Disabled (0x0UL) /*!< Disable channel */ +#define DPPIC_CHEN_CH5_Enabled (0x1UL) /*!< Enable channel */ /* Bit 4 : Enable or disable channel 4 */ #define DPPIC_CHEN_CH4_Pos (4UL) /*!< Position of CH4 field. */ #define DPPIC_CHEN_CH4_Msk (0x1UL << DPPIC_CHEN_CH4_Pos) /*!< Bit mask of CH4 field. */ -#define DPPIC_CHEN_CH4_Disabled (0UL) /*!< Disable channel */ -#define DPPIC_CHEN_CH4_Enabled (1UL) /*!< Enable channel */ +#define DPPIC_CHEN_CH4_Disabled (0x0UL) /*!< Disable channel */ +#define DPPIC_CHEN_CH4_Enabled (0x1UL) /*!< Enable channel */ /* Bit 3 : Enable or disable channel 3 */ #define DPPIC_CHEN_CH3_Pos (3UL) /*!< Position of CH3 field. */ #define DPPIC_CHEN_CH3_Msk (0x1UL << DPPIC_CHEN_CH3_Pos) /*!< Bit mask of CH3 field. */ -#define DPPIC_CHEN_CH3_Disabled (0UL) /*!< Disable channel */ -#define DPPIC_CHEN_CH3_Enabled (1UL) /*!< Enable channel */ +#define DPPIC_CHEN_CH3_Disabled (0x0UL) /*!< Disable channel */ +#define DPPIC_CHEN_CH3_Enabled (0x1UL) /*!< Enable channel */ /* Bit 2 : Enable or disable channel 2 */ #define DPPIC_CHEN_CH2_Pos (2UL) /*!< Position of CH2 field. */ #define DPPIC_CHEN_CH2_Msk (0x1UL << DPPIC_CHEN_CH2_Pos) /*!< Bit mask of CH2 field. */ -#define DPPIC_CHEN_CH2_Disabled (0UL) /*!< Disable channel */ -#define DPPIC_CHEN_CH2_Enabled (1UL) /*!< Enable channel */ +#define DPPIC_CHEN_CH2_Disabled (0x0UL) /*!< Disable channel */ +#define DPPIC_CHEN_CH2_Enabled (0x1UL) /*!< Enable channel */ /* Bit 1 : Enable or disable channel 1 */ #define DPPIC_CHEN_CH1_Pos (1UL) /*!< Position of CH1 field. */ #define DPPIC_CHEN_CH1_Msk (0x1UL << DPPIC_CHEN_CH1_Pos) /*!< Bit mask of CH1 field. */ -#define DPPIC_CHEN_CH1_Disabled (0UL) /*!< Disable channel */ -#define DPPIC_CHEN_CH1_Enabled (1UL) /*!< Enable channel */ +#define DPPIC_CHEN_CH1_Disabled (0x0UL) /*!< Disable channel */ +#define DPPIC_CHEN_CH1_Enabled (0x1UL) /*!< Enable channel */ /* Bit 0 : Enable or disable channel 0 */ #define DPPIC_CHEN_CH0_Pos (0UL) /*!< Position of CH0 field. */ #define DPPIC_CHEN_CH0_Msk (0x1UL << DPPIC_CHEN_CH0_Pos) /*!< Bit mask of CH0 field. */ -#define DPPIC_CHEN_CH0_Disabled (0UL) /*!< Disable channel */ -#define DPPIC_CHEN_CH0_Enabled (1UL) /*!< Enable channel */ +#define DPPIC_CHEN_CH0_Disabled (0x0UL) /*!< Disable channel */ +#define DPPIC_CHEN_CH0_Enabled (0x1UL) /*!< Enable channel */ /* Register: DPPIC_CHENSET */ /* Description: Channel enable set register */ @@ -619,114 +619,114 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 15 : Channel 15 enable set register. Writing 0 has no effect. */ #define DPPIC_CHENSET_CH15_Pos (15UL) /*!< Position of CH15 field. */ #define DPPIC_CHENSET_CH15_Msk (0x1UL << DPPIC_CHENSET_CH15_Pos) /*!< Bit mask of CH15 field. */ -#define DPPIC_CHENSET_CH15_Disabled (0UL) /*!< Read: Channel disabled */ -#define DPPIC_CHENSET_CH15_Enabled (1UL) /*!< Read: Channel enabled */ -#define DPPIC_CHENSET_CH15_Set (1UL) /*!< Write: Enable channel */ +#define DPPIC_CHENSET_CH15_Disabled (0x0UL) /*!< Read: Channel disabled */ +#define DPPIC_CHENSET_CH15_Enabled (0x1UL) /*!< Read: Channel enabled */ +#define DPPIC_CHENSET_CH15_Set (0x1UL) /*!< Write: Enable channel */ /* Bit 14 : Channel 14 enable set register. Writing 0 has no effect. */ #define DPPIC_CHENSET_CH14_Pos (14UL) /*!< Position of CH14 field. */ #define DPPIC_CHENSET_CH14_Msk (0x1UL << DPPIC_CHENSET_CH14_Pos) /*!< Bit mask of CH14 field. */ -#define DPPIC_CHENSET_CH14_Disabled (0UL) /*!< Read: Channel disabled */ -#define DPPIC_CHENSET_CH14_Enabled (1UL) /*!< Read: Channel enabled */ -#define DPPIC_CHENSET_CH14_Set (1UL) /*!< Write: Enable channel */ +#define DPPIC_CHENSET_CH14_Disabled (0x0UL) /*!< Read: Channel disabled */ +#define DPPIC_CHENSET_CH14_Enabled (0x1UL) /*!< Read: Channel enabled */ +#define DPPIC_CHENSET_CH14_Set (0x1UL) /*!< Write: Enable channel */ /* Bit 13 : Channel 13 enable set register. Writing 0 has no effect. */ #define DPPIC_CHENSET_CH13_Pos (13UL) /*!< Position of CH13 field. */ #define DPPIC_CHENSET_CH13_Msk (0x1UL << DPPIC_CHENSET_CH13_Pos) /*!< Bit mask of CH13 field. */ -#define DPPIC_CHENSET_CH13_Disabled (0UL) /*!< Read: Channel disabled */ -#define DPPIC_CHENSET_CH13_Enabled (1UL) /*!< Read: Channel enabled */ -#define DPPIC_CHENSET_CH13_Set (1UL) /*!< Write: Enable channel */ +#define DPPIC_CHENSET_CH13_Disabled (0x0UL) /*!< Read: Channel disabled */ +#define DPPIC_CHENSET_CH13_Enabled (0x1UL) /*!< Read: Channel enabled */ +#define DPPIC_CHENSET_CH13_Set (0x1UL) /*!< Write: Enable channel */ /* Bit 12 : Channel 12 enable set register. Writing 0 has no effect. */ #define DPPIC_CHENSET_CH12_Pos (12UL) /*!< Position of CH12 field. */ #define DPPIC_CHENSET_CH12_Msk (0x1UL << DPPIC_CHENSET_CH12_Pos) /*!< Bit mask of CH12 field. */ -#define DPPIC_CHENSET_CH12_Disabled (0UL) /*!< Read: Channel disabled */ -#define DPPIC_CHENSET_CH12_Enabled (1UL) /*!< Read: Channel enabled */ -#define DPPIC_CHENSET_CH12_Set (1UL) /*!< Write: Enable channel */ +#define DPPIC_CHENSET_CH12_Disabled (0x0UL) /*!< Read: Channel disabled */ +#define DPPIC_CHENSET_CH12_Enabled (0x1UL) /*!< Read: Channel enabled */ +#define DPPIC_CHENSET_CH12_Set (0x1UL) /*!< Write: Enable channel */ /* Bit 11 : Channel 11 enable set register. Writing 0 has no effect. */ #define DPPIC_CHENSET_CH11_Pos (11UL) /*!< Position of CH11 field. */ #define DPPIC_CHENSET_CH11_Msk (0x1UL << DPPIC_CHENSET_CH11_Pos) /*!< Bit mask of CH11 field. */ -#define DPPIC_CHENSET_CH11_Disabled (0UL) /*!< Read: Channel disabled */ -#define DPPIC_CHENSET_CH11_Enabled (1UL) /*!< Read: Channel enabled */ -#define DPPIC_CHENSET_CH11_Set (1UL) /*!< Write: Enable channel */ +#define DPPIC_CHENSET_CH11_Disabled (0x0UL) /*!< Read: Channel disabled */ +#define DPPIC_CHENSET_CH11_Enabled (0x1UL) /*!< Read: Channel enabled */ +#define DPPIC_CHENSET_CH11_Set (0x1UL) /*!< Write: Enable channel */ /* Bit 10 : Channel 10 enable set register. Writing 0 has no effect. */ #define DPPIC_CHENSET_CH10_Pos (10UL) /*!< Position of CH10 field. */ #define DPPIC_CHENSET_CH10_Msk (0x1UL << DPPIC_CHENSET_CH10_Pos) /*!< Bit mask of CH10 field. */ -#define DPPIC_CHENSET_CH10_Disabled (0UL) /*!< Read: Channel disabled */ -#define DPPIC_CHENSET_CH10_Enabled (1UL) /*!< Read: Channel enabled */ -#define DPPIC_CHENSET_CH10_Set (1UL) /*!< Write: Enable channel */ +#define DPPIC_CHENSET_CH10_Disabled (0x0UL) /*!< Read: Channel disabled */ +#define DPPIC_CHENSET_CH10_Enabled (0x1UL) /*!< Read: Channel enabled */ +#define DPPIC_CHENSET_CH10_Set (0x1UL) /*!< Write: Enable channel */ /* Bit 9 : Channel 9 enable set register. Writing 0 has no effect. */ #define DPPIC_CHENSET_CH9_Pos (9UL) /*!< Position of CH9 field. */ #define DPPIC_CHENSET_CH9_Msk (0x1UL << DPPIC_CHENSET_CH9_Pos) /*!< Bit mask of CH9 field. */ -#define DPPIC_CHENSET_CH9_Disabled (0UL) /*!< Read: Channel disabled */ -#define DPPIC_CHENSET_CH9_Enabled (1UL) /*!< Read: Channel enabled */ -#define DPPIC_CHENSET_CH9_Set (1UL) /*!< Write: Enable channel */ +#define DPPIC_CHENSET_CH9_Disabled (0x0UL) /*!< Read: Channel disabled */ +#define DPPIC_CHENSET_CH9_Enabled (0x1UL) /*!< Read: Channel enabled */ +#define DPPIC_CHENSET_CH9_Set (0x1UL) /*!< Write: Enable channel */ /* Bit 8 : Channel 8 enable set register. Writing 0 has no effect. */ #define DPPIC_CHENSET_CH8_Pos (8UL) /*!< Position of CH8 field. */ #define DPPIC_CHENSET_CH8_Msk (0x1UL << DPPIC_CHENSET_CH8_Pos) /*!< Bit mask of CH8 field. */ -#define DPPIC_CHENSET_CH8_Disabled (0UL) /*!< Read: Channel disabled */ -#define DPPIC_CHENSET_CH8_Enabled (1UL) /*!< Read: Channel enabled */ -#define DPPIC_CHENSET_CH8_Set (1UL) /*!< Write: Enable channel */ +#define DPPIC_CHENSET_CH8_Disabled (0x0UL) /*!< Read: Channel disabled */ +#define DPPIC_CHENSET_CH8_Enabled (0x1UL) /*!< Read: Channel enabled */ +#define DPPIC_CHENSET_CH8_Set (0x1UL) /*!< Write: Enable channel */ /* Bit 7 : Channel 7 enable set register. Writing 0 has no effect. */ #define DPPIC_CHENSET_CH7_Pos (7UL) /*!< Position of CH7 field. */ #define DPPIC_CHENSET_CH7_Msk (0x1UL << DPPIC_CHENSET_CH7_Pos) /*!< Bit mask of CH7 field. */ -#define DPPIC_CHENSET_CH7_Disabled (0UL) /*!< Read: Channel disabled */ -#define DPPIC_CHENSET_CH7_Enabled (1UL) /*!< Read: Channel enabled */ -#define DPPIC_CHENSET_CH7_Set (1UL) /*!< Write: Enable channel */ +#define DPPIC_CHENSET_CH7_Disabled (0x0UL) /*!< Read: Channel disabled */ +#define DPPIC_CHENSET_CH7_Enabled (0x1UL) /*!< Read: Channel enabled */ +#define DPPIC_CHENSET_CH7_Set (0x1UL) /*!< Write: Enable channel */ /* Bit 6 : Channel 6 enable set register. Writing 0 has no effect. */ #define DPPIC_CHENSET_CH6_Pos (6UL) /*!< Position of CH6 field. */ #define DPPIC_CHENSET_CH6_Msk (0x1UL << DPPIC_CHENSET_CH6_Pos) /*!< Bit mask of CH6 field. */ -#define DPPIC_CHENSET_CH6_Disabled (0UL) /*!< Read: Channel disabled */ -#define DPPIC_CHENSET_CH6_Enabled (1UL) /*!< Read: Channel enabled */ -#define DPPIC_CHENSET_CH6_Set (1UL) /*!< Write: Enable channel */ +#define DPPIC_CHENSET_CH6_Disabled (0x0UL) /*!< Read: Channel disabled */ +#define DPPIC_CHENSET_CH6_Enabled (0x1UL) /*!< Read: Channel enabled */ +#define DPPIC_CHENSET_CH6_Set (0x1UL) /*!< Write: Enable channel */ /* Bit 5 : Channel 5 enable set register. Writing 0 has no effect. */ #define DPPIC_CHENSET_CH5_Pos (5UL) /*!< Position of CH5 field. */ #define DPPIC_CHENSET_CH5_Msk (0x1UL << DPPIC_CHENSET_CH5_Pos) /*!< Bit mask of CH5 field. */ -#define DPPIC_CHENSET_CH5_Disabled (0UL) /*!< Read: Channel disabled */ -#define DPPIC_CHENSET_CH5_Enabled (1UL) /*!< Read: Channel enabled */ -#define DPPIC_CHENSET_CH5_Set (1UL) /*!< Write: Enable channel */ +#define DPPIC_CHENSET_CH5_Disabled (0x0UL) /*!< Read: Channel disabled */ +#define DPPIC_CHENSET_CH5_Enabled (0x1UL) /*!< Read: Channel enabled */ +#define DPPIC_CHENSET_CH5_Set (0x1UL) /*!< Write: Enable channel */ /* Bit 4 : Channel 4 enable set register. Writing 0 has no effect. */ #define DPPIC_CHENSET_CH4_Pos (4UL) /*!< Position of CH4 field. */ #define DPPIC_CHENSET_CH4_Msk (0x1UL << DPPIC_CHENSET_CH4_Pos) /*!< Bit mask of CH4 field. */ -#define DPPIC_CHENSET_CH4_Disabled (0UL) /*!< Read: Channel disabled */ -#define DPPIC_CHENSET_CH4_Enabled (1UL) /*!< Read: Channel enabled */ -#define DPPIC_CHENSET_CH4_Set (1UL) /*!< Write: Enable channel */ +#define DPPIC_CHENSET_CH4_Disabled (0x0UL) /*!< Read: Channel disabled */ +#define DPPIC_CHENSET_CH4_Enabled (0x1UL) /*!< Read: Channel enabled */ +#define DPPIC_CHENSET_CH4_Set (0x1UL) /*!< Write: Enable channel */ /* Bit 3 : Channel 3 enable set register. Writing 0 has no effect. */ #define DPPIC_CHENSET_CH3_Pos (3UL) /*!< Position of CH3 field. */ #define DPPIC_CHENSET_CH3_Msk (0x1UL << DPPIC_CHENSET_CH3_Pos) /*!< Bit mask of CH3 field. */ -#define DPPIC_CHENSET_CH3_Disabled (0UL) /*!< Read: Channel disabled */ -#define DPPIC_CHENSET_CH3_Enabled (1UL) /*!< Read: Channel enabled */ -#define DPPIC_CHENSET_CH3_Set (1UL) /*!< Write: Enable channel */ +#define DPPIC_CHENSET_CH3_Disabled (0x0UL) /*!< Read: Channel disabled */ +#define DPPIC_CHENSET_CH3_Enabled (0x1UL) /*!< Read: Channel enabled */ +#define DPPIC_CHENSET_CH3_Set (0x1UL) /*!< Write: Enable channel */ /* Bit 2 : Channel 2 enable set register. Writing 0 has no effect. */ #define DPPIC_CHENSET_CH2_Pos (2UL) /*!< Position of CH2 field. */ #define DPPIC_CHENSET_CH2_Msk (0x1UL << DPPIC_CHENSET_CH2_Pos) /*!< Bit mask of CH2 field. */ -#define DPPIC_CHENSET_CH2_Disabled (0UL) /*!< Read: Channel disabled */ -#define DPPIC_CHENSET_CH2_Enabled (1UL) /*!< Read: Channel enabled */ -#define DPPIC_CHENSET_CH2_Set (1UL) /*!< Write: Enable channel */ +#define DPPIC_CHENSET_CH2_Disabled (0x0UL) /*!< Read: Channel disabled */ +#define DPPIC_CHENSET_CH2_Enabled (0x1UL) /*!< Read: Channel enabled */ +#define DPPIC_CHENSET_CH2_Set (0x1UL) /*!< Write: Enable channel */ /* Bit 1 : Channel 1 enable set register. Writing 0 has no effect. */ #define DPPIC_CHENSET_CH1_Pos (1UL) /*!< Position of CH1 field. */ #define DPPIC_CHENSET_CH1_Msk (0x1UL << DPPIC_CHENSET_CH1_Pos) /*!< Bit mask of CH1 field. */ -#define DPPIC_CHENSET_CH1_Disabled (0UL) /*!< Read: Channel disabled */ -#define DPPIC_CHENSET_CH1_Enabled (1UL) /*!< Read: Channel enabled */ -#define DPPIC_CHENSET_CH1_Set (1UL) /*!< Write: Enable channel */ +#define DPPIC_CHENSET_CH1_Disabled (0x0UL) /*!< Read: Channel disabled */ +#define DPPIC_CHENSET_CH1_Enabled (0x1UL) /*!< Read: Channel enabled */ +#define DPPIC_CHENSET_CH1_Set (0x1UL) /*!< Write: Enable channel */ /* Bit 0 : Channel 0 enable set register. Writing 0 has no effect. */ #define DPPIC_CHENSET_CH0_Pos (0UL) /*!< Position of CH0 field. */ #define DPPIC_CHENSET_CH0_Msk (0x1UL << DPPIC_CHENSET_CH0_Pos) /*!< Bit mask of CH0 field. */ -#define DPPIC_CHENSET_CH0_Disabled (0UL) /*!< Read: Channel disabled */ -#define DPPIC_CHENSET_CH0_Enabled (1UL) /*!< Read: Channel enabled */ -#define DPPIC_CHENSET_CH0_Set (1UL) /*!< Write: Enable channel */ +#define DPPIC_CHENSET_CH0_Disabled (0x0UL) /*!< Read: Channel disabled */ +#define DPPIC_CHENSET_CH0_Enabled (0x1UL) /*!< Read: Channel enabled */ +#define DPPIC_CHENSET_CH0_Set (0x1UL) /*!< Write: Enable channel */ /* Register: DPPIC_CHENCLR */ /* Description: Channel enable clear register */ @@ -734,114 +734,114 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 15 : Channel 15 enable clear register. Writing 0 has no effect. */ #define DPPIC_CHENCLR_CH15_Pos (15UL) /*!< Position of CH15 field. */ #define DPPIC_CHENCLR_CH15_Msk (0x1UL << DPPIC_CHENCLR_CH15_Pos) /*!< Bit mask of CH15 field. */ -#define DPPIC_CHENCLR_CH15_Disabled (0UL) /*!< Read: Channel disabled */ -#define DPPIC_CHENCLR_CH15_Enabled (1UL) /*!< Read: Channel enabled */ -#define DPPIC_CHENCLR_CH15_Clear (1UL) /*!< Write: Disable channel */ +#define DPPIC_CHENCLR_CH15_Disabled (0x0UL) /*!< Read: Channel disabled */ +#define DPPIC_CHENCLR_CH15_Enabled (0x1UL) /*!< Read: Channel enabled */ +#define DPPIC_CHENCLR_CH15_Clear (0x1UL) /*!< Write: Disable channel */ /* Bit 14 : Channel 14 enable clear register. Writing 0 has no effect. */ #define DPPIC_CHENCLR_CH14_Pos (14UL) /*!< Position of CH14 field. */ #define DPPIC_CHENCLR_CH14_Msk (0x1UL << DPPIC_CHENCLR_CH14_Pos) /*!< Bit mask of CH14 field. */ -#define DPPIC_CHENCLR_CH14_Disabled (0UL) /*!< Read: Channel disabled */ -#define DPPIC_CHENCLR_CH14_Enabled (1UL) /*!< Read: Channel enabled */ -#define DPPIC_CHENCLR_CH14_Clear (1UL) /*!< Write: Disable channel */ +#define DPPIC_CHENCLR_CH14_Disabled (0x0UL) /*!< Read: Channel disabled */ +#define DPPIC_CHENCLR_CH14_Enabled (0x1UL) /*!< Read: Channel enabled */ +#define DPPIC_CHENCLR_CH14_Clear (0x1UL) /*!< Write: Disable channel */ /* Bit 13 : Channel 13 enable clear register. Writing 0 has no effect. */ #define DPPIC_CHENCLR_CH13_Pos (13UL) /*!< Position of CH13 field. */ #define DPPIC_CHENCLR_CH13_Msk (0x1UL << DPPIC_CHENCLR_CH13_Pos) /*!< Bit mask of CH13 field. */ -#define DPPIC_CHENCLR_CH13_Disabled (0UL) /*!< Read: Channel disabled */ -#define DPPIC_CHENCLR_CH13_Enabled (1UL) /*!< Read: Channel enabled */ -#define DPPIC_CHENCLR_CH13_Clear (1UL) /*!< Write: Disable channel */ +#define DPPIC_CHENCLR_CH13_Disabled (0x0UL) /*!< Read: Channel disabled */ +#define DPPIC_CHENCLR_CH13_Enabled (0x1UL) /*!< Read: Channel enabled */ +#define DPPIC_CHENCLR_CH13_Clear (0x1UL) /*!< Write: Disable channel */ /* Bit 12 : Channel 12 enable clear register. Writing 0 has no effect. */ #define DPPIC_CHENCLR_CH12_Pos (12UL) /*!< Position of CH12 field. */ #define DPPIC_CHENCLR_CH12_Msk (0x1UL << DPPIC_CHENCLR_CH12_Pos) /*!< Bit mask of CH12 field. */ -#define DPPIC_CHENCLR_CH12_Disabled (0UL) /*!< Read: Channel disabled */ -#define DPPIC_CHENCLR_CH12_Enabled (1UL) /*!< Read: Channel enabled */ -#define DPPIC_CHENCLR_CH12_Clear (1UL) /*!< Write: Disable channel */ +#define DPPIC_CHENCLR_CH12_Disabled (0x0UL) /*!< Read: Channel disabled */ +#define DPPIC_CHENCLR_CH12_Enabled (0x1UL) /*!< Read: Channel enabled */ +#define DPPIC_CHENCLR_CH12_Clear (0x1UL) /*!< Write: Disable channel */ /* Bit 11 : Channel 11 enable clear register. Writing 0 has no effect. */ #define DPPIC_CHENCLR_CH11_Pos (11UL) /*!< Position of CH11 field. */ #define DPPIC_CHENCLR_CH11_Msk (0x1UL << DPPIC_CHENCLR_CH11_Pos) /*!< Bit mask of CH11 field. */ -#define DPPIC_CHENCLR_CH11_Disabled (0UL) /*!< Read: Channel disabled */ -#define DPPIC_CHENCLR_CH11_Enabled (1UL) /*!< Read: Channel enabled */ -#define DPPIC_CHENCLR_CH11_Clear (1UL) /*!< Write: Disable channel */ +#define DPPIC_CHENCLR_CH11_Disabled (0x0UL) /*!< Read: Channel disabled */ +#define DPPIC_CHENCLR_CH11_Enabled (0x1UL) /*!< Read: Channel enabled */ +#define DPPIC_CHENCLR_CH11_Clear (0x1UL) /*!< Write: Disable channel */ /* Bit 10 : Channel 10 enable clear register. Writing 0 has no effect. */ #define DPPIC_CHENCLR_CH10_Pos (10UL) /*!< Position of CH10 field. */ #define DPPIC_CHENCLR_CH10_Msk (0x1UL << DPPIC_CHENCLR_CH10_Pos) /*!< Bit mask of CH10 field. */ -#define DPPIC_CHENCLR_CH10_Disabled (0UL) /*!< Read: Channel disabled */ -#define DPPIC_CHENCLR_CH10_Enabled (1UL) /*!< Read: Channel enabled */ -#define DPPIC_CHENCLR_CH10_Clear (1UL) /*!< Write: Disable channel */ +#define DPPIC_CHENCLR_CH10_Disabled (0x0UL) /*!< Read: Channel disabled */ +#define DPPIC_CHENCLR_CH10_Enabled (0x1UL) /*!< Read: Channel enabled */ +#define DPPIC_CHENCLR_CH10_Clear (0x1UL) /*!< Write: Disable channel */ /* Bit 9 : Channel 9 enable clear register. Writing 0 has no effect. */ #define DPPIC_CHENCLR_CH9_Pos (9UL) /*!< Position of CH9 field. */ #define DPPIC_CHENCLR_CH9_Msk (0x1UL << DPPIC_CHENCLR_CH9_Pos) /*!< Bit mask of CH9 field. */ -#define DPPIC_CHENCLR_CH9_Disabled (0UL) /*!< Read: Channel disabled */ -#define DPPIC_CHENCLR_CH9_Enabled (1UL) /*!< Read: Channel enabled */ -#define DPPIC_CHENCLR_CH9_Clear (1UL) /*!< Write: Disable channel */ +#define DPPIC_CHENCLR_CH9_Disabled (0x0UL) /*!< Read: Channel disabled */ +#define DPPIC_CHENCLR_CH9_Enabled (0x1UL) /*!< Read: Channel enabled */ +#define DPPIC_CHENCLR_CH9_Clear (0x1UL) /*!< Write: Disable channel */ /* Bit 8 : Channel 8 enable clear register. Writing 0 has no effect. */ #define DPPIC_CHENCLR_CH8_Pos (8UL) /*!< Position of CH8 field. */ #define DPPIC_CHENCLR_CH8_Msk (0x1UL << DPPIC_CHENCLR_CH8_Pos) /*!< Bit mask of CH8 field. */ -#define DPPIC_CHENCLR_CH8_Disabled (0UL) /*!< Read: Channel disabled */ -#define DPPIC_CHENCLR_CH8_Enabled (1UL) /*!< Read: Channel enabled */ -#define DPPIC_CHENCLR_CH8_Clear (1UL) /*!< Write: Disable channel */ +#define DPPIC_CHENCLR_CH8_Disabled (0x0UL) /*!< Read: Channel disabled */ +#define DPPIC_CHENCLR_CH8_Enabled (0x1UL) /*!< Read: Channel enabled */ +#define DPPIC_CHENCLR_CH8_Clear (0x1UL) /*!< Write: Disable channel */ /* Bit 7 : Channel 7 enable clear register. Writing 0 has no effect. */ #define DPPIC_CHENCLR_CH7_Pos (7UL) /*!< Position of CH7 field. */ #define DPPIC_CHENCLR_CH7_Msk (0x1UL << DPPIC_CHENCLR_CH7_Pos) /*!< Bit mask of CH7 field. */ -#define DPPIC_CHENCLR_CH7_Disabled (0UL) /*!< Read: Channel disabled */ -#define DPPIC_CHENCLR_CH7_Enabled (1UL) /*!< Read: Channel enabled */ -#define DPPIC_CHENCLR_CH7_Clear (1UL) /*!< Write: Disable channel */ +#define DPPIC_CHENCLR_CH7_Disabled (0x0UL) /*!< Read: Channel disabled */ +#define DPPIC_CHENCLR_CH7_Enabled (0x1UL) /*!< Read: Channel enabled */ +#define DPPIC_CHENCLR_CH7_Clear (0x1UL) /*!< Write: Disable channel */ /* Bit 6 : Channel 6 enable clear register. Writing 0 has no effect. */ #define DPPIC_CHENCLR_CH6_Pos (6UL) /*!< Position of CH6 field. */ #define DPPIC_CHENCLR_CH6_Msk (0x1UL << DPPIC_CHENCLR_CH6_Pos) /*!< Bit mask of CH6 field. */ -#define DPPIC_CHENCLR_CH6_Disabled (0UL) /*!< Read: Channel disabled */ -#define DPPIC_CHENCLR_CH6_Enabled (1UL) /*!< Read: Channel enabled */ -#define DPPIC_CHENCLR_CH6_Clear (1UL) /*!< Write: Disable channel */ +#define DPPIC_CHENCLR_CH6_Disabled (0x0UL) /*!< Read: Channel disabled */ +#define DPPIC_CHENCLR_CH6_Enabled (0x1UL) /*!< Read: Channel enabled */ +#define DPPIC_CHENCLR_CH6_Clear (0x1UL) /*!< Write: Disable channel */ /* Bit 5 : Channel 5 enable clear register. Writing 0 has no effect. */ #define DPPIC_CHENCLR_CH5_Pos (5UL) /*!< Position of CH5 field. */ #define DPPIC_CHENCLR_CH5_Msk (0x1UL << DPPIC_CHENCLR_CH5_Pos) /*!< Bit mask of CH5 field. */ -#define DPPIC_CHENCLR_CH5_Disabled (0UL) /*!< Read: Channel disabled */ -#define DPPIC_CHENCLR_CH5_Enabled (1UL) /*!< Read: Channel enabled */ -#define DPPIC_CHENCLR_CH5_Clear (1UL) /*!< Write: Disable channel */ +#define DPPIC_CHENCLR_CH5_Disabled (0x0UL) /*!< Read: Channel disabled */ +#define DPPIC_CHENCLR_CH5_Enabled (0x1UL) /*!< Read: Channel enabled */ +#define DPPIC_CHENCLR_CH5_Clear (0x1UL) /*!< Write: Disable channel */ /* Bit 4 : Channel 4 enable clear register. Writing 0 has no effect. */ #define DPPIC_CHENCLR_CH4_Pos (4UL) /*!< Position of CH4 field. */ #define DPPIC_CHENCLR_CH4_Msk (0x1UL << DPPIC_CHENCLR_CH4_Pos) /*!< Bit mask of CH4 field. */ -#define DPPIC_CHENCLR_CH4_Disabled (0UL) /*!< Read: Channel disabled */ -#define DPPIC_CHENCLR_CH4_Enabled (1UL) /*!< Read: Channel enabled */ -#define DPPIC_CHENCLR_CH4_Clear (1UL) /*!< Write: Disable channel */ +#define DPPIC_CHENCLR_CH4_Disabled (0x0UL) /*!< Read: Channel disabled */ +#define DPPIC_CHENCLR_CH4_Enabled (0x1UL) /*!< Read: Channel enabled */ +#define DPPIC_CHENCLR_CH4_Clear (0x1UL) /*!< Write: Disable channel */ /* Bit 3 : Channel 3 enable clear register. Writing 0 has no effect. */ #define DPPIC_CHENCLR_CH3_Pos (3UL) /*!< Position of CH3 field. */ #define DPPIC_CHENCLR_CH3_Msk (0x1UL << DPPIC_CHENCLR_CH3_Pos) /*!< Bit mask of CH3 field. */ -#define DPPIC_CHENCLR_CH3_Disabled (0UL) /*!< Read: Channel disabled */ -#define DPPIC_CHENCLR_CH3_Enabled (1UL) /*!< Read: Channel enabled */ -#define DPPIC_CHENCLR_CH3_Clear (1UL) /*!< Write: Disable channel */ +#define DPPIC_CHENCLR_CH3_Disabled (0x0UL) /*!< Read: Channel disabled */ +#define DPPIC_CHENCLR_CH3_Enabled (0x1UL) /*!< Read: Channel enabled */ +#define DPPIC_CHENCLR_CH3_Clear (0x1UL) /*!< Write: Disable channel */ /* Bit 2 : Channel 2 enable clear register. Writing 0 has no effect. */ #define DPPIC_CHENCLR_CH2_Pos (2UL) /*!< Position of CH2 field. */ #define DPPIC_CHENCLR_CH2_Msk (0x1UL << DPPIC_CHENCLR_CH2_Pos) /*!< Bit mask of CH2 field. */ -#define DPPIC_CHENCLR_CH2_Disabled (0UL) /*!< Read: Channel disabled */ -#define DPPIC_CHENCLR_CH2_Enabled (1UL) /*!< Read: Channel enabled */ -#define DPPIC_CHENCLR_CH2_Clear (1UL) /*!< Write: Disable channel */ +#define DPPIC_CHENCLR_CH2_Disabled (0x0UL) /*!< Read: Channel disabled */ +#define DPPIC_CHENCLR_CH2_Enabled (0x1UL) /*!< Read: Channel enabled */ +#define DPPIC_CHENCLR_CH2_Clear (0x1UL) /*!< Write: Disable channel */ /* Bit 1 : Channel 1 enable clear register. Writing 0 has no effect. */ #define DPPIC_CHENCLR_CH1_Pos (1UL) /*!< Position of CH1 field. */ #define DPPIC_CHENCLR_CH1_Msk (0x1UL << DPPIC_CHENCLR_CH1_Pos) /*!< Bit mask of CH1 field. */ -#define DPPIC_CHENCLR_CH1_Disabled (0UL) /*!< Read: Channel disabled */ -#define DPPIC_CHENCLR_CH1_Enabled (1UL) /*!< Read: Channel enabled */ -#define DPPIC_CHENCLR_CH1_Clear (1UL) /*!< Write: Disable channel */ +#define DPPIC_CHENCLR_CH1_Disabled (0x0UL) /*!< Read: Channel disabled */ +#define DPPIC_CHENCLR_CH1_Enabled (0x1UL) /*!< Read: Channel enabled */ +#define DPPIC_CHENCLR_CH1_Clear (0x1UL) /*!< Write: Disable channel */ /* Bit 0 : Channel 0 enable clear register. Writing 0 has no effect. */ #define DPPIC_CHENCLR_CH0_Pos (0UL) /*!< Position of CH0 field. */ #define DPPIC_CHENCLR_CH0_Msk (0x1UL << DPPIC_CHENCLR_CH0_Pos) /*!< Bit mask of CH0 field. */ -#define DPPIC_CHENCLR_CH0_Disabled (0UL) /*!< Read: Channel disabled */ -#define DPPIC_CHENCLR_CH0_Enabled (1UL) /*!< Read: Channel enabled */ -#define DPPIC_CHENCLR_CH0_Clear (1UL) /*!< Write: Disable channel */ +#define DPPIC_CHENCLR_CH0_Disabled (0x0UL) /*!< Read: Channel disabled */ +#define DPPIC_CHENCLR_CH0_Enabled (0x1UL) /*!< Read: Channel enabled */ +#define DPPIC_CHENCLR_CH0_Clear (0x1UL) /*!< Write: Disable channel */ /* Register: DPPIC_CHG */ /* Description: Description collection: Channel group n Note: Writes to this register are ignored if either SUBSCRIBE_CHG[n].EN or SUBSCRIBE_CHG[n].DIS is enabled */ @@ -849,98 +849,98 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 15 : Include or exclude channel 15 */ #define DPPIC_CHG_CH15_Pos (15UL) /*!< Position of CH15 field. */ #define DPPIC_CHG_CH15_Msk (0x1UL << DPPIC_CHG_CH15_Pos) /*!< Bit mask of CH15 field. */ -#define DPPIC_CHG_CH15_Excluded (0UL) /*!< Exclude */ -#define DPPIC_CHG_CH15_Included (1UL) /*!< Include */ +#define DPPIC_CHG_CH15_Excluded (0x0UL) /*!< Exclude */ +#define DPPIC_CHG_CH15_Included (0x1UL) /*!< Include */ /* Bit 14 : Include or exclude channel 14 */ #define DPPIC_CHG_CH14_Pos (14UL) /*!< Position of CH14 field. */ #define DPPIC_CHG_CH14_Msk (0x1UL << DPPIC_CHG_CH14_Pos) /*!< Bit mask of CH14 field. */ -#define DPPIC_CHG_CH14_Excluded (0UL) /*!< Exclude */ -#define DPPIC_CHG_CH14_Included (1UL) /*!< Include */ +#define DPPIC_CHG_CH14_Excluded (0x0UL) /*!< Exclude */ +#define DPPIC_CHG_CH14_Included (0x1UL) /*!< Include */ /* Bit 13 : Include or exclude channel 13 */ #define DPPIC_CHG_CH13_Pos (13UL) /*!< Position of CH13 field. */ #define DPPIC_CHG_CH13_Msk (0x1UL << DPPIC_CHG_CH13_Pos) /*!< Bit mask of CH13 field. */ -#define DPPIC_CHG_CH13_Excluded (0UL) /*!< Exclude */ -#define DPPIC_CHG_CH13_Included (1UL) /*!< Include */ +#define DPPIC_CHG_CH13_Excluded (0x0UL) /*!< Exclude */ +#define DPPIC_CHG_CH13_Included (0x1UL) /*!< Include */ /* Bit 12 : Include or exclude channel 12 */ #define DPPIC_CHG_CH12_Pos (12UL) /*!< Position of CH12 field. */ #define DPPIC_CHG_CH12_Msk (0x1UL << DPPIC_CHG_CH12_Pos) /*!< Bit mask of CH12 field. */ -#define DPPIC_CHG_CH12_Excluded (0UL) /*!< Exclude */ -#define DPPIC_CHG_CH12_Included (1UL) /*!< Include */ +#define DPPIC_CHG_CH12_Excluded (0x0UL) /*!< Exclude */ +#define DPPIC_CHG_CH12_Included (0x1UL) /*!< Include */ /* Bit 11 : Include or exclude channel 11 */ #define DPPIC_CHG_CH11_Pos (11UL) /*!< Position of CH11 field. */ #define DPPIC_CHG_CH11_Msk (0x1UL << DPPIC_CHG_CH11_Pos) /*!< Bit mask of CH11 field. */ -#define DPPIC_CHG_CH11_Excluded (0UL) /*!< Exclude */ -#define DPPIC_CHG_CH11_Included (1UL) /*!< Include */ +#define DPPIC_CHG_CH11_Excluded (0x0UL) /*!< Exclude */ +#define DPPIC_CHG_CH11_Included (0x1UL) /*!< Include */ /* Bit 10 : Include or exclude channel 10 */ #define DPPIC_CHG_CH10_Pos (10UL) /*!< Position of CH10 field. */ #define DPPIC_CHG_CH10_Msk (0x1UL << DPPIC_CHG_CH10_Pos) /*!< Bit mask of CH10 field. */ -#define DPPIC_CHG_CH10_Excluded (0UL) /*!< Exclude */ -#define DPPIC_CHG_CH10_Included (1UL) /*!< Include */ +#define DPPIC_CHG_CH10_Excluded (0x0UL) /*!< Exclude */ +#define DPPIC_CHG_CH10_Included (0x1UL) /*!< Include */ /* Bit 9 : Include or exclude channel 9 */ #define DPPIC_CHG_CH9_Pos (9UL) /*!< Position of CH9 field. */ #define DPPIC_CHG_CH9_Msk (0x1UL << DPPIC_CHG_CH9_Pos) /*!< Bit mask of CH9 field. */ -#define DPPIC_CHG_CH9_Excluded (0UL) /*!< Exclude */ -#define DPPIC_CHG_CH9_Included (1UL) /*!< Include */ +#define DPPIC_CHG_CH9_Excluded (0x0UL) /*!< Exclude */ +#define DPPIC_CHG_CH9_Included (0x1UL) /*!< Include */ /* Bit 8 : Include or exclude channel 8 */ #define DPPIC_CHG_CH8_Pos (8UL) /*!< Position of CH8 field. */ #define DPPIC_CHG_CH8_Msk (0x1UL << DPPIC_CHG_CH8_Pos) /*!< Bit mask of CH8 field. */ -#define DPPIC_CHG_CH8_Excluded (0UL) /*!< Exclude */ -#define DPPIC_CHG_CH8_Included (1UL) /*!< Include */ +#define DPPIC_CHG_CH8_Excluded (0x0UL) /*!< Exclude */ +#define DPPIC_CHG_CH8_Included (0x1UL) /*!< Include */ /* Bit 7 : Include or exclude channel 7 */ #define DPPIC_CHG_CH7_Pos (7UL) /*!< Position of CH7 field. */ #define DPPIC_CHG_CH7_Msk (0x1UL << DPPIC_CHG_CH7_Pos) /*!< Bit mask of CH7 field. */ -#define DPPIC_CHG_CH7_Excluded (0UL) /*!< Exclude */ -#define DPPIC_CHG_CH7_Included (1UL) /*!< Include */ +#define DPPIC_CHG_CH7_Excluded (0x0UL) /*!< Exclude */ +#define DPPIC_CHG_CH7_Included (0x1UL) /*!< Include */ /* Bit 6 : Include or exclude channel 6 */ #define DPPIC_CHG_CH6_Pos (6UL) /*!< Position of CH6 field. */ #define DPPIC_CHG_CH6_Msk (0x1UL << DPPIC_CHG_CH6_Pos) /*!< Bit mask of CH6 field. */ -#define DPPIC_CHG_CH6_Excluded (0UL) /*!< Exclude */ -#define DPPIC_CHG_CH6_Included (1UL) /*!< Include */ +#define DPPIC_CHG_CH6_Excluded (0x0UL) /*!< Exclude */ +#define DPPIC_CHG_CH6_Included (0x1UL) /*!< Include */ /* Bit 5 : Include or exclude channel 5 */ #define DPPIC_CHG_CH5_Pos (5UL) /*!< Position of CH5 field. */ #define DPPIC_CHG_CH5_Msk (0x1UL << DPPIC_CHG_CH5_Pos) /*!< Bit mask of CH5 field. */ -#define DPPIC_CHG_CH5_Excluded (0UL) /*!< Exclude */ -#define DPPIC_CHG_CH5_Included (1UL) /*!< Include */ +#define DPPIC_CHG_CH5_Excluded (0x0UL) /*!< Exclude */ +#define DPPIC_CHG_CH5_Included (0x1UL) /*!< Include */ /* Bit 4 : Include or exclude channel 4 */ #define DPPIC_CHG_CH4_Pos (4UL) /*!< Position of CH4 field. */ #define DPPIC_CHG_CH4_Msk (0x1UL << DPPIC_CHG_CH4_Pos) /*!< Bit mask of CH4 field. */ -#define DPPIC_CHG_CH4_Excluded (0UL) /*!< Exclude */ -#define DPPIC_CHG_CH4_Included (1UL) /*!< Include */ +#define DPPIC_CHG_CH4_Excluded (0x0UL) /*!< Exclude */ +#define DPPIC_CHG_CH4_Included (0x1UL) /*!< Include */ /* Bit 3 : Include or exclude channel 3 */ #define DPPIC_CHG_CH3_Pos (3UL) /*!< Position of CH3 field. */ #define DPPIC_CHG_CH3_Msk (0x1UL << DPPIC_CHG_CH3_Pos) /*!< Bit mask of CH3 field. */ -#define DPPIC_CHG_CH3_Excluded (0UL) /*!< Exclude */ -#define DPPIC_CHG_CH3_Included (1UL) /*!< Include */ +#define DPPIC_CHG_CH3_Excluded (0x0UL) /*!< Exclude */ +#define DPPIC_CHG_CH3_Included (0x1UL) /*!< Include */ /* Bit 2 : Include or exclude channel 2 */ #define DPPIC_CHG_CH2_Pos (2UL) /*!< Position of CH2 field. */ #define DPPIC_CHG_CH2_Msk (0x1UL << DPPIC_CHG_CH2_Pos) /*!< Bit mask of CH2 field. */ -#define DPPIC_CHG_CH2_Excluded (0UL) /*!< Exclude */ -#define DPPIC_CHG_CH2_Included (1UL) /*!< Include */ +#define DPPIC_CHG_CH2_Excluded (0x0UL) /*!< Exclude */ +#define DPPIC_CHG_CH2_Included (0x1UL) /*!< Include */ /* Bit 1 : Include or exclude channel 1 */ #define DPPIC_CHG_CH1_Pos (1UL) /*!< Position of CH1 field. */ #define DPPIC_CHG_CH1_Msk (0x1UL << DPPIC_CHG_CH1_Pos) /*!< Bit mask of CH1 field. */ -#define DPPIC_CHG_CH1_Excluded (0UL) /*!< Exclude */ -#define DPPIC_CHG_CH1_Included (1UL) /*!< Include */ +#define DPPIC_CHG_CH1_Excluded (0x0UL) /*!< Exclude */ +#define DPPIC_CHG_CH1_Included (0x1UL) /*!< Include */ /* Bit 0 : Include or exclude channel 0 */ #define DPPIC_CHG_CH0_Pos (0UL) /*!< Position of CH0 field. */ #define DPPIC_CHG_CH0_Msk (0x1UL << DPPIC_CHG_CH0_Pos) /*!< Bit mask of CH0 field. */ -#define DPPIC_CHG_CH0_Excluded (0UL) /*!< Exclude */ -#define DPPIC_CHG_CH0_Included (1UL) /*!< Include */ +#define DPPIC_CHG_CH0_Excluded (0x0UL) /*!< Exclude */ +#define DPPIC_CHG_CH0_Included (0x1UL) /*!< Include */ /* Peripheral: EGU */ @@ -952,7 +952,7 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 0 : Trigger n for triggering the corresponding TRIGGERED[n] event */ #define EGU_TASKS_TRIGGER_TASKS_TRIGGER_Pos (0UL) /*!< Position of TASKS_TRIGGER field. */ #define EGU_TASKS_TRIGGER_TASKS_TRIGGER_Msk (0x1UL << EGU_TASKS_TRIGGER_TASKS_TRIGGER_Pos) /*!< Bit mask of TASKS_TRIGGER field. */ -#define EGU_TASKS_TRIGGER_TASKS_TRIGGER_Trigger (1UL) /*!< Trigger task */ +#define EGU_TASKS_TRIGGER_TASKS_TRIGGER_Trigger (0x1UL) /*!< Trigger task */ /* Register: EGU_SUBSCRIBE_TRIGGER */ /* Description: Description collection: Subscribe configuration for task TRIGGER[n] */ @@ -960,8 +960,8 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 31 : */ #define EGU_SUBSCRIBE_TRIGGER_EN_Pos (31UL) /*!< Position of EN field. */ #define EGU_SUBSCRIBE_TRIGGER_EN_Msk (0x1UL << EGU_SUBSCRIBE_TRIGGER_EN_Pos) /*!< Bit mask of EN field. */ -#define EGU_SUBSCRIBE_TRIGGER_EN_Disabled (0UL) /*!< Disable subscription */ -#define EGU_SUBSCRIBE_TRIGGER_EN_Enabled (1UL) /*!< Enable subscription */ +#define EGU_SUBSCRIBE_TRIGGER_EN_Disabled (0x0UL) /*!< Disable subscription */ +#define EGU_SUBSCRIBE_TRIGGER_EN_Enabled (0x1UL) /*!< Enable subscription */ /* Bits 7..0 : DPPI channel that task TRIGGER[n] will subscribe to */ #define EGU_SUBSCRIBE_TRIGGER_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ @@ -973,8 +973,8 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 0 : Event number n generated by triggering the corresponding TRIGGER[n] task */ #define EGU_EVENTS_TRIGGERED_EVENTS_TRIGGERED_Pos (0UL) /*!< Position of EVENTS_TRIGGERED field. */ #define EGU_EVENTS_TRIGGERED_EVENTS_TRIGGERED_Msk (0x1UL << EGU_EVENTS_TRIGGERED_EVENTS_TRIGGERED_Pos) /*!< Bit mask of EVENTS_TRIGGERED field. */ -#define EGU_EVENTS_TRIGGERED_EVENTS_TRIGGERED_NotGenerated (0UL) /*!< Event not generated */ -#define EGU_EVENTS_TRIGGERED_EVENTS_TRIGGERED_Generated (1UL) /*!< Event generated */ +#define EGU_EVENTS_TRIGGERED_EVENTS_TRIGGERED_NotGenerated (0x0UL) /*!< Event not generated */ +#define EGU_EVENTS_TRIGGERED_EVENTS_TRIGGERED_Generated (0x1UL) /*!< Event generated */ /* Register: EGU_PUBLISH_TRIGGERED */ /* Description: Description collection: Publish configuration for event TRIGGERED[n] */ @@ -982,8 +982,8 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 31 : */ #define EGU_PUBLISH_TRIGGERED_EN_Pos (31UL) /*!< Position of EN field. */ #define EGU_PUBLISH_TRIGGERED_EN_Msk (0x1UL << EGU_PUBLISH_TRIGGERED_EN_Pos) /*!< Bit mask of EN field. */ -#define EGU_PUBLISH_TRIGGERED_EN_Disabled (0UL) /*!< Disable publishing */ -#define EGU_PUBLISH_TRIGGERED_EN_Enabled (1UL) /*!< Enable publishing */ +#define EGU_PUBLISH_TRIGGERED_EN_Disabled (0x0UL) /*!< Disable publishing */ +#define EGU_PUBLISH_TRIGGERED_EN_Enabled (0x1UL) /*!< Enable publishing */ /* Bits 7..0 : DPPI channel that event TRIGGERED[n] will publish to */ #define EGU_PUBLISH_TRIGGERED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ @@ -995,98 +995,98 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 15 : Enable or disable interrupt for event TRIGGERED[15] */ #define EGU_INTEN_TRIGGERED15_Pos (15UL) /*!< Position of TRIGGERED15 field. */ #define EGU_INTEN_TRIGGERED15_Msk (0x1UL << EGU_INTEN_TRIGGERED15_Pos) /*!< Bit mask of TRIGGERED15 field. */ -#define EGU_INTEN_TRIGGERED15_Disabled (0UL) /*!< Disable */ -#define EGU_INTEN_TRIGGERED15_Enabled (1UL) /*!< Enable */ +#define EGU_INTEN_TRIGGERED15_Disabled (0x0UL) /*!< Disable */ +#define EGU_INTEN_TRIGGERED15_Enabled (0x1UL) /*!< Enable */ /* Bit 14 : Enable or disable interrupt for event TRIGGERED[14] */ #define EGU_INTEN_TRIGGERED14_Pos (14UL) /*!< Position of TRIGGERED14 field. */ #define EGU_INTEN_TRIGGERED14_Msk (0x1UL << EGU_INTEN_TRIGGERED14_Pos) /*!< Bit mask of TRIGGERED14 field. */ -#define EGU_INTEN_TRIGGERED14_Disabled (0UL) /*!< Disable */ -#define EGU_INTEN_TRIGGERED14_Enabled (1UL) /*!< Enable */ +#define EGU_INTEN_TRIGGERED14_Disabled (0x0UL) /*!< Disable */ +#define EGU_INTEN_TRIGGERED14_Enabled (0x1UL) /*!< Enable */ /* Bit 13 : Enable or disable interrupt for event TRIGGERED[13] */ #define EGU_INTEN_TRIGGERED13_Pos (13UL) /*!< Position of TRIGGERED13 field. */ #define EGU_INTEN_TRIGGERED13_Msk (0x1UL << EGU_INTEN_TRIGGERED13_Pos) /*!< Bit mask of TRIGGERED13 field. */ -#define EGU_INTEN_TRIGGERED13_Disabled (0UL) /*!< Disable */ -#define EGU_INTEN_TRIGGERED13_Enabled (1UL) /*!< Enable */ +#define EGU_INTEN_TRIGGERED13_Disabled (0x0UL) /*!< Disable */ +#define EGU_INTEN_TRIGGERED13_Enabled (0x1UL) /*!< Enable */ /* Bit 12 : Enable or disable interrupt for event TRIGGERED[12] */ #define EGU_INTEN_TRIGGERED12_Pos (12UL) /*!< Position of TRIGGERED12 field. */ #define EGU_INTEN_TRIGGERED12_Msk (0x1UL << EGU_INTEN_TRIGGERED12_Pos) /*!< Bit mask of TRIGGERED12 field. */ -#define EGU_INTEN_TRIGGERED12_Disabled (0UL) /*!< Disable */ -#define EGU_INTEN_TRIGGERED12_Enabled (1UL) /*!< Enable */ +#define EGU_INTEN_TRIGGERED12_Disabled (0x0UL) /*!< Disable */ +#define EGU_INTEN_TRIGGERED12_Enabled (0x1UL) /*!< Enable */ /* Bit 11 : Enable or disable interrupt for event TRIGGERED[11] */ #define EGU_INTEN_TRIGGERED11_Pos (11UL) /*!< Position of TRIGGERED11 field. */ #define EGU_INTEN_TRIGGERED11_Msk (0x1UL << EGU_INTEN_TRIGGERED11_Pos) /*!< Bit mask of TRIGGERED11 field. */ -#define EGU_INTEN_TRIGGERED11_Disabled (0UL) /*!< Disable */ -#define EGU_INTEN_TRIGGERED11_Enabled (1UL) /*!< Enable */ +#define EGU_INTEN_TRIGGERED11_Disabled (0x0UL) /*!< Disable */ +#define EGU_INTEN_TRIGGERED11_Enabled (0x1UL) /*!< Enable */ /* Bit 10 : Enable or disable interrupt for event TRIGGERED[10] */ #define EGU_INTEN_TRIGGERED10_Pos (10UL) /*!< Position of TRIGGERED10 field. */ #define EGU_INTEN_TRIGGERED10_Msk (0x1UL << EGU_INTEN_TRIGGERED10_Pos) /*!< Bit mask of TRIGGERED10 field. */ -#define EGU_INTEN_TRIGGERED10_Disabled (0UL) /*!< Disable */ -#define EGU_INTEN_TRIGGERED10_Enabled (1UL) /*!< Enable */ +#define EGU_INTEN_TRIGGERED10_Disabled (0x0UL) /*!< Disable */ +#define EGU_INTEN_TRIGGERED10_Enabled (0x1UL) /*!< Enable */ /* Bit 9 : Enable or disable interrupt for event TRIGGERED[9] */ #define EGU_INTEN_TRIGGERED9_Pos (9UL) /*!< Position of TRIGGERED9 field. */ #define EGU_INTEN_TRIGGERED9_Msk (0x1UL << EGU_INTEN_TRIGGERED9_Pos) /*!< Bit mask of TRIGGERED9 field. */ -#define EGU_INTEN_TRIGGERED9_Disabled (0UL) /*!< Disable */ -#define EGU_INTEN_TRIGGERED9_Enabled (1UL) /*!< Enable */ +#define EGU_INTEN_TRIGGERED9_Disabled (0x0UL) /*!< Disable */ +#define EGU_INTEN_TRIGGERED9_Enabled (0x1UL) /*!< Enable */ /* Bit 8 : Enable or disable interrupt for event TRIGGERED[8] */ #define EGU_INTEN_TRIGGERED8_Pos (8UL) /*!< Position of TRIGGERED8 field. */ #define EGU_INTEN_TRIGGERED8_Msk (0x1UL << EGU_INTEN_TRIGGERED8_Pos) /*!< Bit mask of TRIGGERED8 field. */ -#define EGU_INTEN_TRIGGERED8_Disabled (0UL) /*!< Disable */ -#define EGU_INTEN_TRIGGERED8_Enabled (1UL) /*!< Enable */ +#define EGU_INTEN_TRIGGERED8_Disabled (0x0UL) /*!< Disable */ +#define EGU_INTEN_TRIGGERED8_Enabled (0x1UL) /*!< Enable */ /* Bit 7 : Enable or disable interrupt for event TRIGGERED[7] */ #define EGU_INTEN_TRIGGERED7_Pos (7UL) /*!< Position of TRIGGERED7 field. */ #define EGU_INTEN_TRIGGERED7_Msk (0x1UL << EGU_INTEN_TRIGGERED7_Pos) /*!< Bit mask of TRIGGERED7 field. */ -#define EGU_INTEN_TRIGGERED7_Disabled (0UL) /*!< Disable */ -#define EGU_INTEN_TRIGGERED7_Enabled (1UL) /*!< Enable */ +#define EGU_INTEN_TRIGGERED7_Disabled (0x0UL) /*!< Disable */ +#define EGU_INTEN_TRIGGERED7_Enabled (0x1UL) /*!< Enable */ /* Bit 6 : Enable or disable interrupt for event TRIGGERED[6] */ #define EGU_INTEN_TRIGGERED6_Pos (6UL) /*!< Position of TRIGGERED6 field. */ #define EGU_INTEN_TRIGGERED6_Msk (0x1UL << EGU_INTEN_TRIGGERED6_Pos) /*!< Bit mask of TRIGGERED6 field. */ -#define EGU_INTEN_TRIGGERED6_Disabled (0UL) /*!< Disable */ -#define EGU_INTEN_TRIGGERED6_Enabled (1UL) /*!< Enable */ +#define EGU_INTEN_TRIGGERED6_Disabled (0x0UL) /*!< Disable */ +#define EGU_INTEN_TRIGGERED6_Enabled (0x1UL) /*!< Enable */ /* Bit 5 : Enable or disable interrupt for event TRIGGERED[5] */ #define EGU_INTEN_TRIGGERED5_Pos (5UL) /*!< Position of TRIGGERED5 field. */ #define EGU_INTEN_TRIGGERED5_Msk (0x1UL << EGU_INTEN_TRIGGERED5_Pos) /*!< Bit mask of TRIGGERED5 field. */ -#define EGU_INTEN_TRIGGERED5_Disabled (0UL) /*!< Disable */ -#define EGU_INTEN_TRIGGERED5_Enabled (1UL) /*!< Enable */ +#define EGU_INTEN_TRIGGERED5_Disabled (0x0UL) /*!< Disable */ +#define EGU_INTEN_TRIGGERED5_Enabled (0x1UL) /*!< Enable */ /* Bit 4 : Enable or disable interrupt for event TRIGGERED[4] */ #define EGU_INTEN_TRIGGERED4_Pos (4UL) /*!< Position of TRIGGERED4 field. */ #define EGU_INTEN_TRIGGERED4_Msk (0x1UL << EGU_INTEN_TRIGGERED4_Pos) /*!< Bit mask of TRIGGERED4 field. */ -#define EGU_INTEN_TRIGGERED4_Disabled (0UL) /*!< Disable */ -#define EGU_INTEN_TRIGGERED4_Enabled (1UL) /*!< Enable */ +#define EGU_INTEN_TRIGGERED4_Disabled (0x0UL) /*!< Disable */ +#define EGU_INTEN_TRIGGERED4_Enabled (0x1UL) /*!< Enable */ /* Bit 3 : Enable or disable interrupt for event TRIGGERED[3] */ #define EGU_INTEN_TRIGGERED3_Pos (3UL) /*!< Position of TRIGGERED3 field. */ #define EGU_INTEN_TRIGGERED3_Msk (0x1UL << EGU_INTEN_TRIGGERED3_Pos) /*!< Bit mask of TRIGGERED3 field. */ -#define EGU_INTEN_TRIGGERED3_Disabled (0UL) /*!< Disable */ -#define EGU_INTEN_TRIGGERED3_Enabled (1UL) /*!< Enable */ +#define EGU_INTEN_TRIGGERED3_Disabled (0x0UL) /*!< Disable */ +#define EGU_INTEN_TRIGGERED3_Enabled (0x1UL) /*!< Enable */ /* Bit 2 : Enable or disable interrupt for event TRIGGERED[2] */ #define EGU_INTEN_TRIGGERED2_Pos (2UL) /*!< Position of TRIGGERED2 field. */ #define EGU_INTEN_TRIGGERED2_Msk (0x1UL << EGU_INTEN_TRIGGERED2_Pos) /*!< Bit mask of TRIGGERED2 field. */ -#define EGU_INTEN_TRIGGERED2_Disabled (0UL) /*!< Disable */ -#define EGU_INTEN_TRIGGERED2_Enabled (1UL) /*!< Enable */ +#define EGU_INTEN_TRIGGERED2_Disabled (0x0UL) /*!< Disable */ +#define EGU_INTEN_TRIGGERED2_Enabled (0x1UL) /*!< Enable */ /* Bit 1 : Enable or disable interrupt for event TRIGGERED[1] */ #define EGU_INTEN_TRIGGERED1_Pos (1UL) /*!< Position of TRIGGERED1 field. */ #define EGU_INTEN_TRIGGERED1_Msk (0x1UL << EGU_INTEN_TRIGGERED1_Pos) /*!< Bit mask of TRIGGERED1 field. */ -#define EGU_INTEN_TRIGGERED1_Disabled (0UL) /*!< Disable */ -#define EGU_INTEN_TRIGGERED1_Enabled (1UL) /*!< Enable */ +#define EGU_INTEN_TRIGGERED1_Disabled (0x0UL) /*!< Disable */ +#define EGU_INTEN_TRIGGERED1_Enabled (0x1UL) /*!< Enable */ /* Bit 0 : Enable or disable interrupt for event TRIGGERED[0] */ #define EGU_INTEN_TRIGGERED0_Pos (0UL) /*!< Position of TRIGGERED0 field. */ #define EGU_INTEN_TRIGGERED0_Msk (0x1UL << EGU_INTEN_TRIGGERED0_Pos) /*!< Bit mask of TRIGGERED0 field. */ -#define EGU_INTEN_TRIGGERED0_Disabled (0UL) /*!< Disable */ -#define EGU_INTEN_TRIGGERED0_Enabled (1UL) /*!< Enable */ +#define EGU_INTEN_TRIGGERED0_Disabled (0x0UL) /*!< Disable */ +#define EGU_INTEN_TRIGGERED0_Enabled (0x1UL) /*!< Enable */ /* Register: EGU_INTENSET */ /* Description: Enable interrupt */ @@ -1094,114 +1094,114 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 15 : Write '1' to enable interrupt for event TRIGGERED[15] */ #define EGU_INTENSET_TRIGGERED15_Pos (15UL) /*!< Position of TRIGGERED15 field. */ #define EGU_INTENSET_TRIGGERED15_Msk (0x1UL << EGU_INTENSET_TRIGGERED15_Pos) /*!< Bit mask of TRIGGERED15 field. */ -#define EGU_INTENSET_TRIGGERED15_Disabled (0UL) /*!< Read: Disabled */ -#define EGU_INTENSET_TRIGGERED15_Enabled (1UL) /*!< Read: Enabled */ -#define EGU_INTENSET_TRIGGERED15_Set (1UL) /*!< Enable */ +#define EGU_INTENSET_TRIGGERED15_Disabled (0x0UL) /*!< Read: Disabled */ +#define EGU_INTENSET_TRIGGERED15_Enabled (0x1UL) /*!< Read: Enabled */ +#define EGU_INTENSET_TRIGGERED15_Set (0x1UL) /*!< Enable */ /* Bit 14 : Write '1' to enable interrupt for event TRIGGERED[14] */ #define EGU_INTENSET_TRIGGERED14_Pos (14UL) /*!< Position of TRIGGERED14 field. */ #define EGU_INTENSET_TRIGGERED14_Msk (0x1UL << EGU_INTENSET_TRIGGERED14_Pos) /*!< Bit mask of TRIGGERED14 field. */ -#define EGU_INTENSET_TRIGGERED14_Disabled (0UL) /*!< Read: Disabled */ -#define EGU_INTENSET_TRIGGERED14_Enabled (1UL) /*!< Read: Enabled */ -#define EGU_INTENSET_TRIGGERED14_Set (1UL) /*!< Enable */ +#define EGU_INTENSET_TRIGGERED14_Disabled (0x0UL) /*!< Read: Disabled */ +#define EGU_INTENSET_TRIGGERED14_Enabled (0x1UL) /*!< Read: Enabled */ +#define EGU_INTENSET_TRIGGERED14_Set (0x1UL) /*!< Enable */ /* Bit 13 : Write '1' to enable interrupt for event TRIGGERED[13] */ #define EGU_INTENSET_TRIGGERED13_Pos (13UL) /*!< Position of TRIGGERED13 field. */ #define EGU_INTENSET_TRIGGERED13_Msk (0x1UL << EGU_INTENSET_TRIGGERED13_Pos) /*!< Bit mask of TRIGGERED13 field. */ -#define EGU_INTENSET_TRIGGERED13_Disabled (0UL) /*!< Read: Disabled */ -#define EGU_INTENSET_TRIGGERED13_Enabled (1UL) /*!< Read: Enabled */ -#define EGU_INTENSET_TRIGGERED13_Set (1UL) /*!< Enable */ +#define EGU_INTENSET_TRIGGERED13_Disabled (0x0UL) /*!< Read: Disabled */ +#define EGU_INTENSET_TRIGGERED13_Enabled (0x1UL) /*!< Read: Enabled */ +#define EGU_INTENSET_TRIGGERED13_Set (0x1UL) /*!< Enable */ /* Bit 12 : Write '1' to enable interrupt for event TRIGGERED[12] */ #define EGU_INTENSET_TRIGGERED12_Pos (12UL) /*!< Position of TRIGGERED12 field. */ #define EGU_INTENSET_TRIGGERED12_Msk (0x1UL << EGU_INTENSET_TRIGGERED12_Pos) /*!< Bit mask of TRIGGERED12 field. */ -#define EGU_INTENSET_TRIGGERED12_Disabled (0UL) /*!< Read: Disabled */ -#define EGU_INTENSET_TRIGGERED12_Enabled (1UL) /*!< Read: Enabled */ -#define EGU_INTENSET_TRIGGERED12_Set (1UL) /*!< Enable */ +#define EGU_INTENSET_TRIGGERED12_Disabled (0x0UL) /*!< Read: Disabled */ +#define EGU_INTENSET_TRIGGERED12_Enabled (0x1UL) /*!< Read: Enabled */ +#define EGU_INTENSET_TRIGGERED12_Set (0x1UL) /*!< Enable */ /* Bit 11 : Write '1' to enable interrupt for event TRIGGERED[11] */ #define EGU_INTENSET_TRIGGERED11_Pos (11UL) /*!< Position of TRIGGERED11 field. */ #define EGU_INTENSET_TRIGGERED11_Msk (0x1UL << EGU_INTENSET_TRIGGERED11_Pos) /*!< Bit mask of TRIGGERED11 field. */ -#define EGU_INTENSET_TRIGGERED11_Disabled (0UL) /*!< Read: Disabled */ -#define EGU_INTENSET_TRIGGERED11_Enabled (1UL) /*!< Read: Enabled */ -#define EGU_INTENSET_TRIGGERED11_Set (1UL) /*!< Enable */ +#define EGU_INTENSET_TRIGGERED11_Disabled (0x0UL) /*!< Read: Disabled */ +#define EGU_INTENSET_TRIGGERED11_Enabled (0x1UL) /*!< Read: Enabled */ +#define EGU_INTENSET_TRIGGERED11_Set (0x1UL) /*!< Enable */ /* Bit 10 : Write '1' to enable interrupt for event TRIGGERED[10] */ #define EGU_INTENSET_TRIGGERED10_Pos (10UL) /*!< Position of TRIGGERED10 field. */ #define EGU_INTENSET_TRIGGERED10_Msk (0x1UL << EGU_INTENSET_TRIGGERED10_Pos) /*!< Bit mask of TRIGGERED10 field. */ -#define EGU_INTENSET_TRIGGERED10_Disabled (0UL) /*!< Read: Disabled */ -#define EGU_INTENSET_TRIGGERED10_Enabled (1UL) /*!< Read: Enabled */ -#define EGU_INTENSET_TRIGGERED10_Set (1UL) /*!< Enable */ +#define EGU_INTENSET_TRIGGERED10_Disabled (0x0UL) /*!< Read: Disabled */ +#define EGU_INTENSET_TRIGGERED10_Enabled (0x1UL) /*!< Read: Enabled */ +#define EGU_INTENSET_TRIGGERED10_Set (0x1UL) /*!< Enable */ /* Bit 9 : Write '1' to enable interrupt for event TRIGGERED[9] */ #define EGU_INTENSET_TRIGGERED9_Pos (9UL) /*!< Position of TRIGGERED9 field. */ #define EGU_INTENSET_TRIGGERED9_Msk (0x1UL << EGU_INTENSET_TRIGGERED9_Pos) /*!< Bit mask of TRIGGERED9 field. */ -#define EGU_INTENSET_TRIGGERED9_Disabled (0UL) /*!< Read: Disabled */ -#define EGU_INTENSET_TRIGGERED9_Enabled (1UL) /*!< Read: Enabled */ -#define EGU_INTENSET_TRIGGERED9_Set (1UL) /*!< Enable */ +#define EGU_INTENSET_TRIGGERED9_Disabled (0x0UL) /*!< Read: Disabled */ +#define EGU_INTENSET_TRIGGERED9_Enabled (0x1UL) /*!< Read: Enabled */ +#define EGU_INTENSET_TRIGGERED9_Set (0x1UL) /*!< Enable */ /* Bit 8 : Write '1' to enable interrupt for event TRIGGERED[8] */ #define EGU_INTENSET_TRIGGERED8_Pos (8UL) /*!< Position of TRIGGERED8 field. */ #define EGU_INTENSET_TRIGGERED8_Msk (0x1UL << EGU_INTENSET_TRIGGERED8_Pos) /*!< Bit mask of TRIGGERED8 field. */ -#define EGU_INTENSET_TRIGGERED8_Disabled (0UL) /*!< Read: Disabled */ -#define EGU_INTENSET_TRIGGERED8_Enabled (1UL) /*!< Read: Enabled */ -#define EGU_INTENSET_TRIGGERED8_Set (1UL) /*!< Enable */ +#define EGU_INTENSET_TRIGGERED8_Disabled (0x0UL) /*!< Read: Disabled */ +#define EGU_INTENSET_TRIGGERED8_Enabled (0x1UL) /*!< Read: Enabled */ +#define EGU_INTENSET_TRIGGERED8_Set (0x1UL) /*!< Enable */ /* Bit 7 : Write '1' to enable interrupt for event TRIGGERED[7] */ #define EGU_INTENSET_TRIGGERED7_Pos (7UL) /*!< Position of TRIGGERED7 field. */ #define EGU_INTENSET_TRIGGERED7_Msk (0x1UL << EGU_INTENSET_TRIGGERED7_Pos) /*!< Bit mask of TRIGGERED7 field. */ -#define EGU_INTENSET_TRIGGERED7_Disabled (0UL) /*!< Read: Disabled */ -#define EGU_INTENSET_TRIGGERED7_Enabled (1UL) /*!< Read: Enabled */ -#define EGU_INTENSET_TRIGGERED7_Set (1UL) /*!< Enable */ +#define EGU_INTENSET_TRIGGERED7_Disabled (0x0UL) /*!< Read: Disabled */ +#define EGU_INTENSET_TRIGGERED7_Enabled (0x1UL) /*!< Read: Enabled */ +#define EGU_INTENSET_TRIGGERED7_Set (0x1UL) /*!< Enable */ /* Bit 6 : Write '1' to enable interrupt for event TRIGGERED[6] */ #define EGU_INTENSET_TRIGGERED6_Pos (6UL) /*!< Position of TRIGGERED6 field. */ #define EGU_INTENSET_TRIGGERED6_Msk (0x1UL << EGU_INTENSET_TRIGGERED6_Pos) /*!< Bit mask of TRIGGERED6 field. */ -#define EGU_INTENSET_TRIGGERED6_Disabled (0UL) /*!< Read: Disabled */ -#define EGU_INTENSET_TRIGGERED6_Enabled (1UL) /*!< Read: Enabled */ -#define EGU_INTENSET_TRIGGERED6_Set (1UL) /*!< Enable */ +#define EGU_INTENSET_TRIGGERED6_Disabled (0x0UL) /*!< Read: Disabled */ +#define EGU_INTENSET_TRIGGERED6_Enabled (0x1UL) /*!< Read: Enabled */ +#define EGU_INTENSET_TRIGGERED6_Set (0x1UL) /*!< Enable */ /* Bit 5 : Write '1' to enable interrupt for event TRIGGERED[5] */ #define EGU_INTENSET_TRIGGERED5_Pos (5UL) /*!< Position of TRIGGERED5 field. */ #define EGU_INTENSET_TRIGGERED5_Msk (0x1UL << EGU_INTENSET_TRIGGERED5_Pos) /*!< Bit mask of TRIGGERED5 field. */ -#define EGU_INTENSET_TRIGGERED5_Disabled (0UL) /*!< Read: Disabled */ -#define EGU_INTENSET_TRIGGERED5_Enabled (1UL) /*!< Read: Enabled */ -#define EGU_INTENSET_TRIGGERED5_Set (1UL) /*!< Enable */ +#define EGU_INTENSET_TRIGGERED5_Disabled (0x0UL) /*!< Read: Disabled */ +#define EGU_INTENSET_TRIGGERED5_Enabled (0x1UL) /*!< Read: Enabled */ +#define EGU_INTENSET_TRIGGERED5_Set (0x1UL) /*!< Enable */ /* Bit 4 : Write '1' to enable interrupt for event TRIGGERED[4] */ #define EGU_INTENSET_TRIGGERED4_Pos (4UL) /*!< Position of TRIGGERED4 field. */ #define EGU_INTENSET_TRIGGERED4_Msk (0x1UL << EGU_INTENSET_TRIGGERED4_Pos) /*!< Bit mask of TRIGGERED4 field. */ -#define EGU_INTENSET_TRIGGERED4_Disabled (0UL) /*!< Read: Disabled */ -#define EGU_INTENSET_TRIGGERED4_Enabled (1UL) /*!< Read: Enabled */ -#define EGU_INTENSET_TRIGGERED4_Set (1UL) /*!< Enable */ +#define EGU_INTENSET_TRIGGERED4_Disabled (0x0UL) /*!< Read: Disabled */ +#define EGU_INTENSET_TRIGGERED4_Enabled (0x1UL) /*!< Read: Enabled */ +#define EGU_INTENSET_TRIGGERED4_Set (0x1UL) /*!< Enable */ /* Bit 3 : Write '1' to enable interrupt for event TRIGGERED[3] */ #define EGU_INTENSET_TRIGGERED3_Pos (3UL) /*!< Position of TRIGGERED3 field. */ #define EGU_INTENSET_TRIGGERED3_Msk (0x1UL << EGU_INTENSET_TRIGGERED3_Pos) /*!< Bit mask of TRIGGERED3 field. */ -#define EGU_INTENSET_TRIGGERED3_Disabled (0UL) /*!< Read: Disabled */ -#define EGU_INTENSET_TRIGGERED3_Enabled (1UL) /*!< Read: Enabled */ -#define EGU_INTENSET_TRIGGERED3_Set (1UL) /*!< Enable */ +#define EGU_INTENSET_TRIGGERED3_Disabled (0x0UL) /*!< Read: Disabled */ +#define EGU_INTENSET_TRIGGERED3_Enabled (0x1UL) /*!< Read: Enabled */ +#define EGU_INTENSET_TRIGGERED3_Set (0x1UL) /*!< Enable */ /* Bit 2 : Write '1' to enable interrupt for event TRIGGERED[2] */ #define EGU_INTENSET_TRIGGERED2_Pos (2UL) /*!< Position of TRIGGERED2 field. */ #define EGU_INTENSET_TRIGGERED2_Msk (0x1UL << EGU_INTENSET_TRIGGERED2_Pos) /*!< Bit mask of TRIGGERED2 field. */ -#define EGU_INTENSET_TRIGGERED2_Disabled (0UL) /*!< Read: Disabled */ -#define EGU_INTENSET_TRIGGERED2_Enabled (1UL) /*!< Read: Enabled */ -#define EGU_INTENSET_TRIGGERED2_Set (1UL) /*!< Enable */ +#define EGU_INTENSET_TRIGGERED2_Disabled (0x0UL) /*!< Read: Disabled */ +#define EGU_INTENSET_TRIGGERED2_Enabled (0x1UL) /*!< Read: Enabled */ +#define EGU_INTENSET_TRIGGERED2_Set (0x1UL) /*!< Enable */ /* Bit 1 : Write '1' to enable interrupt for event TRIGGERED[1] */ #define EGU_INTENSET_TRIGGERED1_Pos (1UL) /*!< Position of TRIGGERED1 field. */ #define EGU_INTENSET_TRIGGERED1_Msk (0x1UL << EGU_INTENSET_TRIGGERED1_Pos) /*!< Bit mask of TRIGGERED1 field. */ -#define EGU_INTENSET_TRIGGERED1_Disabled (0UL) /*!< Read: Disabled */ -#define EGU_INTENSET_TRIGGERED1_Enabled (1UL) /*!< Read: Enabled */ -#define EGU_INTENSET_TRIGGERED1_Set (1UL) /*!< Enable */ +#define EGU_INTENSET_TRIGGERED1_Disabled (0x0UL) /*!< Read: Disabled */ +#define EGU_INTENSET_TRIGGERED1_Enabled (0x1UL) /*!< Read: Enabled */ +#define EGU_INTENSET_TRIGGERED1_Set (0x1UL) /*!< Enable */ /* Bit 0 : Write '1' to enable interrupt for event TRIGGERED[0] */ #define EGU_INTENSET_TRIGGERED0_Pos (0UL) /*!< Position of TRIGGERED0 field. */ #define EGU_INTENSET_TRIGGERED0_Msk (0x1UL << EGU_INTENSET_TRIGGERED0_Pos) /*!< Bit mask of TRIGGERED0 field. */ -#define EGU_INTENSET_TRIGGERED0_Disabled (0UL) /*!< Read: Disabled */ -#define EGU_INTENSET_TRIGGERED0_Enabled (1UL) /*!< Read: Enabled */ -#define EGU_INTENSET_TRIGGERED0_Set (1UL) /*!< Enable */ +#define EGU_INTENSET_TRIGGERED0_Disabled (0x0UL) /*!< Read: Disabled */ +#define EGU_INTENSET_TRIGGERED0_Enabled (0x1UL) /*!< Read: Enabled */ +#define EGU_INTENSET_TRIGGERED0_Set (0x1UL) /*!< Enable */ /* Register: EGU_INTENCLR */ /* Description: Disable interrupt */ @@ -1209,114 +1209,114 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 15 : Write '1' to disable interrupt for event TRIGGERED[15] */ #define EGU_INTENCLR_TRIGGERED15_Pos (15UL) /*!< Position of TRIGGERED15 field. */ #define EGU_INTENCLR_TRIGGERED15_Msk (0x1UL << EGU_INTENCLR_TRIGGERED15_Pos) /*!< Bit mask of TRIGGERED15 field. */ -#define EGU_INTENCLR_TRIGGERED15_Disabled (0UL) /*!< Read: Disabled */ -#define EGU_INTENCLR_TRIGGERED15_Enabled (1UL) /*!< Read: Enabled */ -#define EGU_INTENCLR_TRIGGERED15_Clear (1UL) /*!< Disable */ +#define EGU_INTENCLR_TRIGGERED15_Disabled (0x0UL) /*!< Read: Disabled */ +#define EGU_INTENCLR_TRIGGERED15_Enabled (0x1UL) /*!< Read: Enabled */ +#define EGU_INTENCLR_TRIGGERED15_Clear (0x1UL) /*!< Disable */ /* Bit 14 : Write '1' to disable interrupt for event TRIGGERED[14] */ #define EGU_INTENCLR_TRIGGERED14_Pos (14UL) /*!< Position of TRIGGERED14 field. */ #define EGU_INTENCLR_TRIGGERED14_Msk (0x1UL << EGU_INTENCLR_TRIGGERED14_Pos) /*!< Bit mask of TRIGGERED14 field. */ -#define EGU_INTENCLR_TRIGGERED14_Disabled (0UL) /*!< Read: Disabled */ -#define EGU_INTENCLR_TRIGGERED14_Enabled (1UL) /*!< Read: Enabled */ -#define EGU_INTENCLR_TRIGGERED14_Clear (1UL) /*!< Disable */ +#define EGU_INTENCLR_TRIGGERED14_Disabled (0x0UL) /*!< Read: Disabled */ +#define EGU_INTENCLR_TRIGGERED14_Enabled (0x1UL) /*!< Read: Enabled */ +#define EGU_INTENCLR_TRIGGERED14_Clear (0x1UL) /*!< Disable */ /* Bit 13 : Write '1' to disable interrupt for event TRIGGERED[13] */ #define EGU_INTENCLR_TRIGGERED13_Pos (13UL) /*!< Position of TRIGGERED13 field. */ #define EGU_INTENCLR_TRIGGERED13_Msk (0x1UL << EGU_INTENCLR_TRIGGERED13_Pos) /*!< Bit mask of TRIGGERED13 field. */ -#define EGU_INTENCLR_TRIGGERED13_Disabled (0UL) /*!< Read: Disabled */ -#define EGU_INTENCLR_TRIGGERED13_Enabled (1UL) /*!< Read: Enabled */ -#define EGU_INTENCLR_TRIGGERED13_Clear (1UL) /*!< Disable */ +#define EGU_INTENCLR_TRIGGERED13_Disabled (0x0UL) /*!< Read: Disabled */ +#define EGU_INTENCLR_TRIGGERED13_Enabled (0x1UL) /*!< Read: Enabled */ +#define EGU_INTENCLR_TRIGGERED13_Clear (0x1UL) /*!< Disable */ /* Bit 12 : Write '1' to disable interrupt for event TRIGGERED[12] */ #define EGU_INTENCLR_TRIGGERED12_Pos (12UL) /*!< Position of TRIGGERED12 field. */ #define EGU_INTENCLR_TRIGGERED12_Msk (0x1UL << EGU_INTENCLR_TRIGGERED12_Pos) /*!< Bit mask of TRIGGERED12 field. */ -#define EGU_INTENCLR_TRIGGERED12_Disabled (0UL) /*!< Read: Disabled */ -#define EGU_INTENCLR_TRIGGERED12_Enabled (1UL) /*!< Read: Enabled */ -#define EGU_INTENCLR_TRIGGERED12_Clear (1UL) /*!< Disable */ +#define EGU_INTENCLR_TRIGGERED12_Disabled (0x0UL) /*!< Read: Disabled */ +#define EGU_INTENCLR_TRIGGERED12_Enabled (0x1UL) /*!< Read: Enabled */ +#define EGU_INTENCLR_TRIGGERED12_Clear (0x1UL) /*!< Disable */ /* Bit 11 : Write '1' to disable interrupt for event TRIGGERED[11] */ #define EGU_INTENCLR_TRIGGERED11_Pos (11UL) /*!< Position of TRIGGERED11 field. */ #define EGU_INTENCLR_TRIGGERED11_Msk (0x1UL << EGU_INTENCLR_TRIGGERED11_Pos) /*!< Bit mask of TRIGGERED11 field. */ -#define EGU_INTENCLR_TRIGGERED11_Disabled (0UL) /*!< Read: Disabled */ -#define EGU_INTENCLR_TRIGGERED11_Enabled (1UL) /*!< Read: Enabled */ -#define EGU_INTENCLR_TRIGGERED11_Clear (1UL) /*!< Disable */ +#define EGU_INTENCLR_TRIGGERED11_Disabled (0x0UL) /*!< Read: Disabled */ +#define EGU_INTENCLR_TRIGGERED11_Enabled (0x1UL) /*!< Read: Enabled */ +#define EGU_INTENCLR_TRIGGERED11_Clear (0x1UL) /*!< Disable */ /* Bit 10 : Write '1' to disable interrupt for event TRIGGERED[10] */ #define EGU_INTENCLR_TRIGGERED10_Pos (10UL) /*!< Position of TRIGGERED10 field. */ #define EGU_INTENCLR_TRIGGERED10_Msk (0x1UL << EGU_INTENCLR_TRIGGERED10_Pos) /*!< Bit mask of TRIGGERED10 field. */ -#define EGU_INTENCLR_TRIGGERED10_Disabled (0UL) /*!< Read: Disabled */ -#define EGU_INTENCLR_TRIGGERED10_Enabled (1UL) /*!< Read: Enabled */ -#define EGU_INTENCLR_TRIGGERED10_Clear (1UL) /*!< Disable */ +#define EGU_INTENCLR_TRIGGERED10_Disabled (0x0UL) /*!< Read: Disabled */ +#define EGU_INTENCLR_TRIGGERED10_Enabled (0x1UL) /*!< Read: Enabled */ +#define EGU_INTENCLR_TRIGGERED10_Clear (0x1UL) /*!< Disable */ /* Bit 9 : Write '1' to disable interrupt for event TRIGGERED[9] */ #define EGU_INTENCLR_TRIGGERED9_Pos (9UL) /*!< Position of TRIGGERED9 field. */ #define EGU_INTENCLR_TRIGGERED9_Msk (0x1UL << EGU_INTENCLR_TRIGGERED9_Pos) /*!< Bit mask of TRIGGERED9 field. */ -#define EGU_INTENCLR_TRIGGERED9_Disabled (0UL) /*!< Read: Disabled */ -#define EGU_INTENCLR_TRIGGERED9_Enabled (1UL) /*!< Read: Enabled */ -#define EGU_INTENCLR_TRIGGERED9_Clear (1UL) /*!< Disable */ +#define EGU_INTENCLR_TRIGGERED9_Disabled (0x0UL) /*!< Read: Disabled */ +#define EGU_INTENCLR_TRIGGERED9_Enabled (0x1UL) /*!< Read: Enabled */ +#define EGU_INTENCLR_TRIGGERED9_Clear (0x1UL) /*!< Disable */ /* Bit 8 : Write '1' to disable interrupt for event TRIGGERED[8] */ #define EGU_INTENCLR_TRIGGERED8_Pos (8UL) /*!< Position of TRIGGERED8 field. */ #define EGU_INTENCLR_TRIGGERED8_Msk (0x1UL << EGU_INTENCLR_TRIGGERED8_Pos) /*!< Bit mask of TRIGGERED8 field. */ -#define EGU_INTENCLR_TRIGGERED8_Disabled (0UL) /*!< Read: Disabled */ -#define EGU_INTENCLR_TRIGGERED8_Enabled (1UL) /*!< Read: Enabled */ -#define EGU_INTENCLR_TRIGGERED8_Clear (1UL) /*!< Disable */ +#define EGU_INTENCLR_TRIGGERED8_Disabled (0x0UL) /*!< Read: Disabled */ +#define EGU_INTENCLR_TRIGGERED8_Enabled (0x1UL) /*!< Read: Enabled */ +#define EGU_INTENCLR_TRIGGERED8_Clear (0x1UL) /*!< Disable */ /* Bit 7 : Write '1' to disable interrupt for event TRIGGERED[7] */ #define EGU_INTENCLR_TRIGGERED7_Pos (7UL) /*!< Position of TRIGGERED7 field. */ #define EGU_INTENCLR_TRIGGERED7_Msk (0x1UL << EGU_INTENCLR_TRIGGERED7_Pos) /*!< Bit mask of TRIGGERED7 field. */ -#define EGU_INTENCLR_TRIGGERED7_Disabled (0UL) /*!< Read: Disabled */ -#define EGU_INTENCLR_TRIGGERED7_Enabled (1UL) /*!< Read: Enabled */ -#define EGU_INTENCLR_TRIGGERED7_Clear (1UL) /*!< Disable */ +#define EGU_INTENCLR_TRIGGERED7_Disabled (0x0UL) /*!< Read: Disabled */ +#define EGU_INTENCLR_TRIGGERED7_Enabled (0x1UL) /*!< Read: Enabled */ +#define EGU_INTENCLR_TRIGGERED7_Clear (0x1UL) /*!< Disable */ /* Bit 6 : Write '1' to disable interrupt for event TRIGGERED[6] */ #define EGU_INTENCLR_TRIGGERED6_Pos (6UL) /*!< Position of TRIGGERED6 field. */ #define EGU_INTENCLR_TRIGGERED6_Msk (0x1UL << EGU_INTENCLR_TRIGGERED6_Pos) /*!< Bit mask of TRIGGERED6 field. */ -#define EGU_INTENCLR_TRIGGERED6_Disabled (0UL) /*!< Read: Disabled */ -#define EGU_INTENCLR_TRIGGERED6_Enabled (1UL) /*!< Read: Enabled */ -#define EGU_INTENCLR_TRIGGERED6_Clear (1UL) /*!< Disable */ +#define EGU_INTENCLR_TRIGGERED6_Disabled (0x0UL) /*!< Read: Disabled */ +#define EGU_INTENCLR_TRIGGERED6_Enabled (0x1UL) /*!< Read: Enabled */ +#define EGU_INTENCLR_TRIGGERED6_Clear (0x1UL) /*!< Disable */ /* Bit 5 : Write '1' to disable interrupt for event TRIGGERED[5] */ #define EGU_INTENCLR_TRIGGERED5_Pos (5UL) /*!< Position of TRIGGERED5 field. */ #define EGU_INTENCLR_TRIGGERED5_Msk (0x1UL << EGU_INTENCLR_TRIGGERED5_Pos) /*!< Bit mask of TRIGGERED5 field. */ -#define EGU_INTENCLR_TRIGGERED5_Disabled (0UL) /*!< Read: Disabled */ -#define EGU_INTENCLR_TRIGGERED5_Enabled (1UL) /*!< Read: Enabled */ -#define EGU_INTENCLR_TRIGGERED5_Clear (1UL) /*!< Disable */ +#define EGU_INTENCLR_TRIGGERED5_Disabled (0x0UL) /*!< Read: Disabled */ +#define EGU_INTENCLR_TRIGGERED5_Enabled (0x1UL) /*!< Read: Enabled */ +#define EGU_INTENCLR_TRIGGERED5_Clear (0x1UL) /*!< Disable */ /* Bit 4 : Write '1' to disable interrupt for event TRIGGERED[4] */ #define EGU_INTENCLR_TRIGGERED4_Pos (4UL) /*!< Position of TRIGGERED4 field. */ #define EGU_INTENCLR_TRIGGERED4_Msk (0x1UL << EGU_INTENCLR_TRIGGERED4_Pos) /*!< Bit mask of TRIGGERED4 field. */ -#define EGU_INTENCLR_TRIGGERED4_Disabled (0UL) /*!< Read: Disabled */ -#define EGU_INTENCLR_TRIGGERED4_Enabled (1UL) /*!< Read: Enabled */ -#define EGU_INTENCLR_TRIGGERED4_Clear (1UL) /*!< Disable */ +#define EGU_INTENCLR_TRIGGERED4_Disabled (0x0UL) /*!< Read: Disabled */ +#define EGU_INTENCLR_TRIGGERED4_Enabled (0x1UL) /*!< Read: Enabled */ +#define EGU_INTENCLR_TRIGGERED4_Clear (0x1UL) /*!< Disable */ /* Bit 3 : Write '1' to disable interrupt for event TRIGGERED[3] */ #define EGU_INTENCLR_TRIGGERED3_Pos (3UL) /*!< Position of TRIGGERED3 field. */ #define EGU_INTENCLR_TRIGGERED3_Msk (0x1UL << EGU_INTENCLR_TRIGGERED3_Pos) /*!< Bit mask of TRIGGERED3 field. */ -#define EGU_INTENCLR_TRIGGERED3_Disabled (0UL) /*!< Read: Disabled */ -#define EGU_INTENCLR_TRIGGERED3_Enabled (1UL) /*!< Read: Enabled */ -#define EGU_INTENCLR_TRIGGERED3_Clear (1UL) /*!< Disable */ +#define EGU_INTENCLR_TRIGGERED3_Disabled (0x0UL) /*!< Read: Disabled */ +#define EGU_INTENCLR_TRIGGERED3_Enabled (0x1UL) /*!< Read: Enabled */ +#define EGU_INTENCLR_TRIGGERED3_Clear (0x1UL) /*!< Disable */ /* Bit 2 : Write '1' to disable interrupt for event TRIGGERED[2] */ #define EGU_INTENCLR_TRIGGERED2_Pos (2UL) /*!< Position of TRIGGERED2 field. */ #define EGU_INTENCLR_TRIGGERED2_Msk (0x1UL << EGU_INTENCLR_TRIGGERED2_Pos) /*!< Bit mask of TRIGGERED2 field. */ -#define EGU_INTENCLR_TRIGGERED2_Disabled (0UL) /*!< Read: Disabled */ -#define EGU_INTENCLR_TRIGGERED2_Enabled (1UL) /*!< Read: Enabled */ -#define EGU_INTENCLR_TRIGGERED2_Clear (1UL) /*!< Disable */ +#define EGU_INTENCLR_TRIGGERED2_Disabled (0x0UL) /*!< Read: Disabled */ +#define EGU_INTENCLR_TRIGGERED2_Enabled (0x1UL) /*!< Read: Enabled */ +#define EGU_INTENCLR_TRIGGERED2_Clear (0x1UL) /*!< Disable */ /* Bit 1 : Write '1' to disable interrupt for event TRIGGERED[1] */ #define EGU_INTENCLR_TRIGGERED1_Pos (1UL) /*!< Position of TRIGGERED1 field. */ #define EGU_INTENCLR_TRIGGERED1_Msk (0x1UL << EGU_INTENCLR_TRIGGERED1_Pos) /*!< Bit mask of TRIGGERED1 field. */ -#define EGU_INTENCLR_TRIGGERED1_Disabled (0UL) /*!< Read: Disabled */ -#define EGU_INTENCLR_TRIGGERED1_Enabled (1UL) /*!< Read: Enabled */ -#define EGU_INTENCLR_TRIGGERED1_Clear (1UL) /*!< Disable */ +#define EGU_INTENCLR_TRIGGERED1_Disabled (0x0UL) /*!< Read: Disabled */ +#define EGU_INTENCLR_TRIGGERED1_Enabled (0x1UL) /*!< Read: Enabled */ +#define EGU_INTENCLR_TRIGGERED1_Clear (0x1UL) /*!< Disable */ /* Bit 0 : Write '1' to disable interrupt for event TRIGGERED[0] */ #define EGU_INTENCLR_TRIGGERED0_Pos (0UL) /*!< Position of TRIGGERED0 field. */ #define EGU_INTENCLR_TRIGGERED0_Msk (0x1UL << EGU_INTENCLR_TRIGGERED0_Pos) /*!< Bit mask of TRIGGERED0 field. */ -#define EGU_INTENCLR_TRIGGERED0_Disabled (0UL) /*!< Read: Disabled */ -#define EGU_INTENCLR_TRIGGERED0_Enabled (1UL) /*!< Read: Enabled */ -#define EGU_INTENCLR_TRIGGERED0_Clear (1UL) /*!< Disable */ +#define EGU_INTENCLR_TRIGGERED0_Disabled (0x0UL) /*!< Read: Disabled */ +#define EGU_INTENCLR_TRIGGERED0_Enabled (0x1UL) /*!< Read: Enabled */ +#define EGU_INTENCLR_TRIGGERED0_Clear (0x1UL) /*!< Disable */ /* Peripheral: FICR */ @@ -1357,8 +1357,8 @@ POSSIBILITY OF SUCH DAMAGE. /* Bits 31..0 : Part code */ #define FICR_INFO_PART_PART_Pos (0UL) /*!< Position of PART field. */ #define FICR_INFO_PART_PART_Msk (0xFFFFFFFFUL << FICR_INFO_PART_PART_Pos) /*!< Bit mask of PART field. */ -#define FICR_INFO_PART_PART_N9120 (0x9120UL) /*!< nRF9120 */ -#define FICR_INFO_PART_PART_N9160 (0x9160UL) /*!< nRF9160 */ +#define FICR_INFO_PART_PART_N9120 (0x00009120UL) /*!< nRF9120 */ +#define FICR_INFO_PART_PART_N9160 (0x00009160UL) /*!< nRF9160 */ /* Register: FICR_INFO_VARIANT */ /* Description: Part Variant, Hardware version and Production configuration */ @@ -1377,7 +1377,7 @@ POSSIBILITY OF SUCH DAMAGE. /* Bits 31..0 : Package option */ #define FICR_INFO_PACKAGE_PACKAGE_Pos (0UL) /*!< Position of PACKAGE field. */ #define FICR_INFO_PACKAGE_PACKAGE_Msk (0xFFFFFFFFUL << FICR_INFO_PACKAGE_PACKAGE_Pos) /*!< Bit mask of PACKAGE field. */ -#define FICR_INFO_PACKAGE_PACKAGE_CF (0x2002UL) /*!< CFxx - 236 ball wlCSP */ +#define FICR_INFO_PACKAGE_PACKAGE_CF (0x00002002UL) /*!< CFxx - 236 ball wlCSP */ /* Register: FICR_INFO_RAM */ /* Description: RAM variant */ @@ -1385,7 +1385,7 @@ POSSIBILITY OF SUCH DAMAGE. /* Bits 31..0 : RAM variant */ #define FICR_INFO_RAM_RAM_Pos (0UL) /*!< Position of RAM field. */ #define FICR_INFO_RAM_RAM_Msk (0xFFFFFFFFUL << FICR_INFO_RAM_RAM_Pos) /*!< Bit mask of RAM field. */ -#define FICR_INFO_RAM_RAM_K256 (0x100UL) /*!< 256 kByte RAM */ +#define FICR_INFO_RAM_RAM_K256 (0x00000100UL) /*!< 256 kByte RAM */ #define FICR_INFO_RAM_RAM_Unspecified (0xFFFFFFFFUL) /*!< Unspecified */ /* Register: FICR_INFO_FLASH */ @@ -1394,7 +1394,7 @@ POSSIBILITY OF SUCH DAMAGE. /* Bits 31..0 : Flash variant */ #define FICR_INFO_FLASH_FLASH_Pos (0UL) /*!< Position of FLASH field. */ #define FICR_INFO_FLASH_FLASH_Msk (0xFFFFFFFFUL << FICR_INFO_FLASH_FLASH_Pos) /*!< Bit mask of FLASH field. */ -#define FICR_INFO_FLASH_FLASH_K1024 (0x400UL) /*!< 1 MByte FLASH */ +#define FICR_INFO_FLASH_FLASH_K1024 (0x00000400UL) /*!< 1 MByte FLASH */ /* Register: FICR_INFO_CODEPAGESIZE */ /* Description: Code memory page size */ @@ -1402,7 +1402,7 @@ POSSIBILITY OF SUCH DAMAGE. /* Bits 31..0 : Code memory page size */ #define FICR_INFO_CODEPAGESIZE_CODEPAGESIZE_Pos (0UL) /*!< Position of CODEPAGESIZE field. */ #define FICR_INFO_CODEPAGESIZE_CODEPAGESIZE_Msk (0xFFFFFFFFUL << FICR_INFO_CODEPAGESIZE_CODEPAGESIZE_Pos) /*!< Bit mask of CODEPAGESIZE field. */ -#define FICR_INFO_CODEPAGESIZE_CODEPAGESIZE_K4096 (0x1000UL) /*!< 4 kByte */ +#define FICR_INFO_CODEPAGESIZE_CODEPAGESIZE_K4096 (0x00001000UL) /*!< 4 kByte */ /* Register: FICR_INFO_CODESIZE */ /* Description: Code memory size */ @@ -1410,7 +1410,7 @@ POSSIBILITY OF SUCH DAMAGE. /* Bits 31..0 : Code memory size in number of pages Total code space is: CODEPAGESIZE * CODESIZE */ #define FICR_INFO_CODESIZE_CODESIZE_Pos (0UL) /*!< Position of CODESIZE field. */ #define FICR_INFO_CODESIZE_CODESIZE_Msk (0xFFFFFFFFUL << FICR_INFO_CODESIZE_CODESIZE_Pos) /*!< Bit mask of CODESIZE field. */ -#define FICR_INFO_CODESIZE_CODESIZE_P256 (256UL) /*!< 256 pages */ +#define FICR_INFO_CODESIZE_CODESIZE_P256 (0x00000100UL) /*!< 256 pages */ /* Register: FICR_INFO_DEVICETYPE */ /* Description: Device type */ @@ -1418,7 +1418,7 @@ POSSIBILITY OF SUCH DAMAGE. /* Bits 31..0 : Device type */ #define FICR_INFO_DEVICETYPE_DEVICETYPE_Pos (0UL) /*!< Position of DEVICETYPE field. */ #define FICR_INFO_DEVICETYPE_DEVICETYPE_Msk (0xFFFFFFFFUL << FICR_INFO_DEVICETYPE_DEVICETYPE_Pos) /*!< Bit mask of DEVICETYPE field. */ -#define FICR_INFO_DEVICETYPE_DEVICETYPE_Die (0x0000000UL) /*!< Device is an physical DIE */ +#define FICR_INFO_DEVICETYPE_DEVICETYPE_Die (0x00000000UL) /*!< Device is an physical DIE */ #define FICR_INFO_DEVICETYPE_DEVICETYPE_FPGA (0xFFFFFFFFUL) /*!< Device is an FPGA */ /* Register: FICR_TRIMCNF_ADDR */ @@ -1501,7 +1501,7 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 0 : Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is configured in CONFIG[n].POLARITY. */ #define GPIOTE_TASKS_OUT_TASKS_OUT_Pos (0UL) /*!< Position of TASKS_OUT field. */ #define GPIOTE_TASKS_OUT_TASKS_OUT_Msk (0x1UL << GPIOTE_TASKS_OUT_TASKS_OUT_Pos) /*!< Bit mask of TASKS_OUT field. */ -#define GPIOTE_TASKS_OUT_TASKS_OUT_Trigger (1UL) /*!< Trigger task */ +#define GPIOTE_TASKS_OUT_TASKS_OUT_Trigger (0x1UL) /*!< Trigger task */ /* Register: GPIOTE_TASKS_SET */ /* Description: Description collection: Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it high. */ @@ -1509,7 +1509,7 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 0 : Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it high. */ #define GPIOTE_TASKS_SET_TASKS_SET_Pos (0UL) /*!< Position of TASKS_SET field. */ #define GPIOTE_TASKS_SET_TASKS_SET_Msk (0x1UL << GPIOTE_TASKS_SET_TASKS_SET_Pos) /*!< Bit mask of TASKS_SET field. */ -#define GPIOTE_TASKS_SET_TASKS_SET_Trigger (1UL) /*!< Trigger task */ +#define GPIOTE_TASKS_SET_TASKS_SET_Trigger (0x1UL) /*!< Trigger task */ /* Register: GPIOTE_TASKS_CLR */ /* Description: Description collection: Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it low. */ @@ -1517,7 +1517,7 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 0 : Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it low. */ #define GPIOTE_TASKS_CLR_TASKS_CLR_Pos (0UL) /*!< Position of TASKS_CLR field. */ #define GPIOTE_TASKS_CLR_TASKS_CLR_Msk (0x1UL << GPIOTE_TASKS_CLR_TASKS_CLR_Pos) /*!< Bit mask of TASKS_CLR field. */ -#define GPIOTE_TASKS_CLR_TASKS_CLR_Trigger (1UL) /*!< Trigger task */ +#define GPIOTE_TASKS_CLR_TASKS_CLR_Trigger (0x1UL) /*!< Trigger task */ /* Register: GPIOTE_SUBSCRIBE_OUT */ /* Description: Description collection: Subscribe configuration for task OUT[n] */ @@ -1525,8 +1525,8 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 31 : */ #define GPIOTE_SUBSCRIBE_OUT_EN_Pos (31UL) /*!< Position of EN field. */ #define GPIOTE_SUBSCRIBE_OUT_EN_Msk (0x1UL << GPIOTE_SUBSCRIBE_OUT_EN_Pos) /*!< Bit mask of EN field. */ -#define GPIOTE_SUBSCRIBE_OUT_EN_Disabled (0UL) /*!< Disable subscription */ -#define GPIOTE_SUBSCRIBE_OUT_EN_Enabled (1UL) /*!< Enable subscription */ +#define GPIOTE_SUBSCRIBE_OUT_EN_Disabled (0x0UL) /*!< Disable subscription */ +#define GPIOTE_SUBSCRIBE_OUT_EN_Enabled (0x1UL) /*!< Enable subscription */ /* Bits 7..0 : DPPI channel that task OUT[n] will subscribe to */ #define GPIOTE_SUBSCRIBE_OUT_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ @@ -1538,8 +1538,8 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 31 : */ #define GPIOTE_SUBSCRIBE_SET_EN_Pos (31UL) /*!< Position of EN field. */ #define GPIOTE_SUBSCRIBE_SET_EN_Msk (0x1UL << GPIOTE_SUBSCRIBE_SET_EN_Pos) /*!< Bit mask of EN field. */ -#define GPIOTE_SUBSCRIBE_SET_EN_Disabled (0UL) /*!< Disable subscription */ -#define GPIOTE_SUBSCRIBE_SET_EN_Enabled (1UL) /*!< Enable subscription */ +#define GPIOTE_SUBSCRIBE_SET_EN_Disabled (0x0UL) /*!< Disable subscription */ +#define GPIOTE_SUBSCRIBE_SET_EN_Enabled (0x1UL) /*!< Enable subscription */ /* Bits 7..0 : DPPI channel that task SET[n] will subscribe to */ #define GPIOTE_SUBSCRIBE_SET_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ @@ -1551,8 +1551,8 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 31 : */ #define GPIOTE_SUBSCRIBE_CLR_EN_Pos (31UL) /*!< Position of EN field. */ #define GPIOTE_SUBSCRIBE_CLR_EN_Msk (0x1UL << GPIOTE_SUBSCRIBE_CLR_EN_Pos) /*!< Bit mask of EN field. */ -#define GPIOTE_SUBSCRIBE_CLR_EN_Disabled (0UL) /*!< Disable subscription */ -#define GPIOTE_SUBSCRIBE_CLR_EN_Enabled (1UL) /*!< Enable subscription */ +#define GPIOTE_SUBSCRIBE_CLR_EN_Disabled (0x0UL) /*!< Disable subscription */ +#define GPIOTE_SUBSCRIBE_CLR_EN_Enabled (0x1UL) /*!< Enable subscription */ /* Bits 7..0 : DPPI channel that task CLR[n] will subscribe to */ #define GPIOTE_SUBSCRIBE_CLR_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ @@ -1564,8 +1564,8 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 0 : Event generated from pin specified in CONFIG[n].PSEL */ #define GPIOTE_EVENTS_IN_EVENTS_IN_Pos (0UL) /*!< Position of EVENTS_IN field. */ #define GPIOTE_EVENTS_IN_EVENTS_IN_Msk (0x1UL << GPIOTE_EVENTS_IN_EVENTS_IN_Pos) /*!< Bit mask of EVENTS_IN field. */ -#define GPIOTE_EVENTS_IN_EVENTS_IN_NotGenerated (0UL) /*!< Event not generated */ -#define GPIOTE_EVENTS_IN_EVENTS_IN_Generated (1UL) /*!< Event generated */ +#define GPIOTE_EVENTS_IN_EVENTS_IN_NotGenerated (0x0UL) /*!< Event not generated */ +#define GPIOTE_EVENTS_IN_EVENTS_IN_Generated (0x1UL) /*!< Event generated */ /* Register: GPIOTE_EVENTS_PORT */ /* Description: Event generated from multiple input GPIO pins with SENSE mechanism enabled */ @@ -1573,8 +1573,8 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 0 : Event generated from multiple input GPIO pins with SENSE mechanism enabled */ #define GPIOTE_EVENTS_PORT_EVENTS_PORT_Pos (0UL) /*!< Position of EVENTS_PORT field. */ #define GPIOTE_EVENTS_PORT_EVENTS_PORT_Msk (0x1UL << GPIOTE_EVENTS_PORT_EVENTS_PORT_Pos) /*!< Bit mask of EVENTS_PORT field. */ -#define GPIOTE_EVENTS_PORT_EVENTS_PORT_NotGenerated (0UL) /*!< Event not generated */ -#define GPIOTE_EVENTS_PORT_EVENTS_PORT_Generated (1UL) /*!< Event generated */ +#define GPIOTE_EVENTS_PORT_EVENTS_PORT_NotGenerated (0x0UL) /*!< Event not generated */ +#define GPIOTE_EVENTS_PORT_EVENTS_PORT_Generated (0x1UL) /*!< Event generated */ /* Register: GPIOTE_PUBLISH_IN */ /* Description: Description collection: Publish configuration for event IN[n] */ @@ -1582,8 +1582,8 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 31 : */ #define GPIOTE_PUBLISH_IN_EN_Pos (31UL) /*!< Position of EN field. */ #define GPIOTE_PUBLISH_IN_EN_Msk (0x1UL << GPIOTE_PUBLISH_IN_EN_Pos) /*!< Bit mask of EN field. */ -#define GPIOTE_PUBLISH_IN_EN_Disabled (0UL) /*!< Disable publishing */ -#define GPIOTE_PUBLISH_IN_EN_Enabled (1UL) /*!< Enable publishing */ +#define GPIOTE_PUBLISH_IN_EN_Disabled (0x0UL) /*!< Disable publishing */ +#define GPIOTE_PUBLISH_IN_EN_Enabled (0x1UL) /*!< Enable publishing */ /* Bits 7..0 : DPPI channel that event IN[n] will publish to */ #define GPIOTE_PUBLISH_IN_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ @@ -1595,8 +1595,8 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 31 : */ #define GPIOTE_PUBLISH_PORT_EN_Pos (31UL) /*!< Position of EN field. */ #define GPIOTE_PUBLISH_PORT_EN_Msk (0x1UL << GPIOTE_PUBLISH_PORT_EN_Pos) /*!< Bit mask of EN field. */ -#define GPIOTE_PUBLISH_PORT_EN_Disabled (0UL) /*!< Disable publishing */ -#define GPIOTE_PUBLISH_PORT_EN_Enabled (1UL) /*!< Enable publishing */ +#define GPIOTE_PUBLISH_PORT_EN_Disabled (0x0UL) /*!< Disable publishing */ +#define GPIOTE_PUBLISH_PORT_EN_Enabled (0x1UL) /*!< Enable publishing */ /* Bits 7..0 : DPPI channel that event PORT will publish to */ #define GPIOTE_PUBLISH_PORT_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ @@ -1608,65 +1608,65 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 31 : Write '1' to enable interrupt for event PORT */ #define GPIOTE_INTENSET_PORT_Pos (31UL) /*!< Position of PORT field. */ #define GPIOTE_INTENSET_PORT_Msk (0x1UL << GPIOTE_INTENSET_PORT_Pos) /*!< Bit mask of PORT field. */ -#define GPIOTE_INTENSET_PORT_Disabled (0UL) /*!< Read: Disabled */ -#define GPIOTE_INTENSET_PORT_Enabled (1UL) /*!< Read: Enabled */ -#define GPIOTE_INTENSET_PORT_Set (1UL) /*!< Enable */ +#define GPIOTE_INTENSET_PORT_Disabled (0x0UL) /*!< Read: Disabled */ +#define GPIOTE_INTENSET_PORT_Enabled (0x1UL) /*!< Read: Enabled */ +#define GPIOTE_INTENSET_PORT_Set (0x1UL) /*!< Enable */ /* Bit 7 : Write '1' to enable interrupt for event IN[7] */ #define GPIOTE_INTENSET_IN7_Pos (7UL) /*!< Position of IN7 field. */ #define GPIOTE_INTENSET_IN7_Msk (0x1UL << GPIOTE_INTENSET_IN7_Pos) /*!< Bit mask of IN7 field. */ -#define GPIOTE_INTENSET_IN7_Disabled (0UL) /*!< Read: Disabled */ -#define GPIOTE_INTENSET_IN7_Enabled (1UL) /*!< Read: Enabled */ -#define GPIOTE_INTENSET_IN7_Set (1UL) /*!< Enable */ +#define GPIOTE_INTENSET_IN7_Disabled (0x0UL) /*!< Read: Disabled */ +#define GPIOTE_INTENSET_IN7_Enabled (0x1UL) /*!< Read: Enabled */ +#define GPIOTE_INTENSET_IN7_Set (0x1UL) /*!< Enable */ /* Bit 6 : Write '1' to enable interrupt for event IN[6] */ #define GPIOTE_INTENSET_IN6_Pos (6UL) /*!< Position of IN6 field. */ #define GPIOTE_INTENSET_IN6_Msk (0x1UL << GPIOTE_INTENSET_IN6_Pos) /*!< Bit mask of IN6 field. */ -#define GPIOTE_INTENSET_IN6_Disabled (0UL) /*!< Read: Disabled */ -#define GPIOTE_INTENSET_IN6_Enabled (1UL) /*!< Read: Enabled */ -#define GPIOTE_INTENSET_IN6_Set (1UL) /*!< Enable */ +#define GPIOTE_INTENSET_IN6_Disabled (0x0UL) /*!< Read: Disabled */ +#define GPIOTE_INTENSET_IN6_Enabled (0x1UL) /*!< Read: Enabled */ +#define GPIOTE_INTENSET_IN6_Set (0x1UL) /*!< Enable */ /* Bit 5 : Write '1' to enable interrupt for event IN[5] */ #define GPIOTE_INTENSET_IN5_Pos (5UL) /*!< Position of IN5 field. */ #define GPIOTE_INTENSET_IN5_Msk (0x1UL << GPIOTE_INTENSET_IN5_Pos) /*!< Bit mask of IN5 field. */ -#define GPIOTE_INTENSET_IN5_Disabled (0UL) /*!< Read: Disabled */ -#define GPIOTE_INTENSET_IN5_Enabled (1UL) /*!< Read: Enabled */ -#define GPIOTE_INTENSET_IN5_Set (1UL) /*!< Enable */ +#define GPIOTE_INTENSET_IN5_Disabled (0x0UL) /*!< Read: Disabled */ +#define GPIOTE_INTENSET_IN5_Enabled (0x1UL) /*!< Read: Enabled */ +#define GPIOTE_INTENSET_IN5_Set (0x1UL) /*!< Enable */ /* Bit 4 : Write '1' to enable interrupt for event IN[4] */ #define GPIOTE_INTENSET_IN4_Pos (4UL) /*!< Position of IN4 field. */ #define GPIOTE_INTENSET_IN4_Msk (0x1UL << GPIOTE_INTENSET_IN4_Pos) /*!< Bit mask of IN4 field. */ -#define GPIOTE_INTENSET_IN4_Disabled (0UL) /*!< Read: Disabled */ -#define GPIOTE_INTENSET_IN4_Enabled (1UL) /*!< Read: Enabled */ -#define GPIOTE_INTENSET_IN4_Set (1UL) /*!< Enable */ +#define GPIOTE_INTENSET_IN4_Disabled (0x0UL) /*!< Read: Disabled */ +#define GPIOTE_INTENSET_IN4_Enabled (0x1UL) /*!< Read: Enabled */ +#define GPIOTE_INTENSET_IN4_Set (0x1UL) /*!< Enable */ /* Bit 3 : Write '1' to enable interrupt for event IN[3] */ #define GPIOTE_INTENSET_IN3_Pos (3UL) /*!< Position of IN3 field. */ #define GPIOTE_INTENSET_IN3_Msk (0x1UL << GPIOTE_INTENSET_IN3_Pos) /*!< Bit mask of IN3 field. */ -#define GPIOTE_INTENSET_IN3_Disabled (0UL) /*!< Read: Disabled */ -#define GPIOTE_INTENSET_IN3_Enabled (1UL) /*!< Read: Enabled */ -#define GPIOTE_INTENSET_IN3_Set (1UL) /*!< Enable */ +#define GPIOTE_INTENSET_IN3_Disabled (0x0UL) /*!< Read: Disabled */ +#define GPIOTE_INTENSET_IN3_Enabled (0x1UL) /*!< Read: Enabled */ +#define GPIOTE_INTENSET_IN3_Set (0x1UL) /*!< Enable */ /* Bit 2 : Write '1' to enable interrupt for event IN[2] */ #define GPIOTE_INTENSET_IN2_Pos (2UL) /*!< Position of IN2 field. */ #define GPIOTE_INTENSET_IN2_Msk (0x1UL << GPIOTE_INTENSET_IN2_Pos) /*!< Bit mask of IN2 field. */ -#define GPIOTE_INTENSET_IN2_Disabled (0UL) /*!< Read: Disabled */ -#define GPIOTE_INTENSET_IN2_Enabled (1UL) /*!< Read: Enabled */ -#define GPIOTE_INTENSET_IN2_Set (1UL) /*!< Enable */ +#define GPIOTE_INTENSET_IN2_Disabled (0x0UL) /*!< Read: Disabled */ +#define GPIOTE_INTENSET_IN2_Enabled (0x1UL) /*!< Read: Enabled */ +#define GPIOTE_INTENSET_IN2_Set (0x1UL) /*!< Enable */ /* Bit 1 : Write '1' to enable interrupt for event IN[1] */ #define GPIOTE_INTENSET_IN1_Pos (1UL) /*!< Position of IN1 field. */ #define GPIOTE_INTENSET_IN1_Msk (0x1UL << GPIOTE_INTENSET_IN1_Pos) /*!< Bit mask of IN1 field. */ -#define GPIOTE_INTENSET_IN1_Disabled (0UL) /*!< Read: Disabled */ -#define GPIOTE_INTENSET_IN1_Enabled (1UL) /*!< Read: Enabled */ -#define GPIOTE_INTENSET_IN1_Set (1UL) /*!< Enable */ +#define GPIOTE_INTENSET_IN1_Disabled (0x0UL) /*!< Read: Disabled */ +#define GPIOTE_INTENSET_IN1_Enabled (0x1UL) /*!< Read: Enabled */ +#define GPIOTE_INTENSET_IN1_Set (0x1UL) /*!< Enable */ /* Bit 0 : Write '1' to enable interrupt for event IN[0] */ #define GPIOTE_INTENSET_IN0_Pos (0UL) /*!< Position of IN0 field. */ #define GPIOTE_INTENSET_IN0_Msk (0x1UL << GPIOTE_INTENSET_IN0_Pos) /*!< Bit mask of IN0 field. */ -#define GPIOTE_INTENSET_IN0_Disabled (0UL) /*!< Read: Disabled */ -#define GPIOTE_INTENSET_IN0_Enabled (1UL) /*!< Read: Enabled */ -#define GPIOTE_INTENSET_IN0_Set (1UL) /*!< Enable */ +#define GPIOTE_INTENSET_IN0_Disabled (0x0UL) /*!< Read: Disabled */ +#define GPIOTE_INTENSET_IN0_Enabled (0x1UL) /*!< Read: Enabled */ +#define GPIOTE_INTENSET_IN0_Set (0x1UL) /*!< Enable */ /* Register: GPIOTE_INTENCLR */ /* Description: Disable interrupt */ @@ -1674,65 +1674,65 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 31 : Write '1' to disable interrupt for event PORT */ #define GPIOTE_INTENCLR_PORT_Pos (31UL) /*!< Position of PORT field. */ #define GPIOTE_INTENCLR_PORT_Msk (0x1UL << GPIOTE_INTENCLR_PORT_Pos) /*!< Bit mask of PORT field. */ -#define GPIOTE_INTENCLR_PORT_Disabled (0UL) /*!< Read: Disabled */ -#define GPIOTE_INTENCLR_PORT_Enabled (1UL) /*!< Read: Enabled */ -#define GPIOTE_INTENCLR_PORT_Clear (1UL) /*!< Disable */ +#define GPIOTE_INTENCLR_PORT_Disabled (0x0UL) /*!< Read: Disabled */ +#define GPIOTE_INTENCLR_PORT_Enabled (0x1UL) /*!< Read: Enabled */ +#define GPIOTE_INTENCLR_PORT_Clear (0x1UL) /*!< Disable */ /* Bit 7 : Write '1' to disable interrupt for event IN[7] */ #define GPIOTE_INTENCLR_IN7_Pos (7UL) /*!< Position of IN7 field. */ #define GPIOTE_INTENCLR_IN7_Msk (0x1UL << GPIOTE_INTENCLR_IN7_Pos) /*!< Bit mask of IN7 field. */ -#define GPIOTE_INTENCLR_IN7_Disabled (0UL) /*!< Read: Disabled */ -#define GPIOTE_INTENCLR_IN7_Enabled (1UL) /*!< Read: Enabled */ -#define GPIOTE_INTENCLR_IN7_Clear (1UL) /*!< Disable */ +#define GPIOTE_INTENCLR_IN7_Disabled (0x0UL) /*!< Read: Disabled */ +#define GPIOTE_INTENCLR_IN7_Enabled (0x1UL) /*!< Read: Enabled */ +#define GPIOTE_INTENCLR_IN7_Clear (0x1UL) /*!< Disable */ /* Bit 6 : Write '1' to disable interrupt for event IN[6] */ #define GPIOTE_INTENCLR_IN6_Pos (6UL) /*!< Position of IN6 field. */ #define GPIOTE_INTENCLR_IN6_Msk (0x1UL << GPIOTE_INTENCLR_IN6_Pos) /*!< Bit mask of IN6 field. */ -#define GPIOTE_INTENCLR_IN6_Disabled (0UL) /*!< Read: Disabled */ -#define GPIOTE_INTENCLR_IN6_Enabled (1UL) /*!< Read: Enabled */ -#define GPIOTE_INTENCLR_IN6_Clear (1UL) /*!< Disable */ +#define GPIOTE_INTENCLR_IN6_Disabled (0x0UL) /*!< Read: Disabled */ +#define GPIOTE_INTENCLR_IN6_Enabled (0x1UL) /*!< Read: Enabled */ +#define GPIOTE_INTENCLR_IN6_Clear (0x1UL) /*!< Disable */ /* Bit 5 : Write '1' to disable interrupt for event IN[5] */ #define GPIOTE_INTENCLR_IN5_Pos (5UL) /*!< Position of IN5 field. */ #define GPIOTE_INTENCLR_IN5_Msk (0x1UL << GPIOTE_INTENCLR_IN5_Pos) /*!< Bit mask of IN5 field. */ -#define GPIOTE_INTENCLR_IN5_Disabled (0UL) /*!< Read: Disabled */ -#define GPIOTE_INTENCLR_IN5_Enabled (1UL) /*!< Read: Enabled */ -#define GPIOTE_INTENCLR_IN5_Clear (1UL) /*!< Disable */ +#define GPIOTE_INTENCLR_IN5_Disabled (0x0UL) /*!< Read: Disabled */ +#define GPIOTE_INTENCLR_IN5_Enabled (0x1UL) /*!< Read: Enabled */ +#define GPIOTE_INTENCLR_IN5_Clear (0x1UL) /*!< Disable */ /* Bit 4 : Write '1' to disable interrupt for event IN[4] */ #define GPIOTE_INTENCLR_IN4_Pos (4UL) /*!< Position of IN4 field. */ #define GPIOTE_INTENCLR_IN4_Msk (0x1UL << GPIOTE_INTENCLR_IN4_Pos) /*!< Bit mask of IN4 field. */ -#define GPIOTE_INTENCLR_IN4_Disabled (0UL) /*!< Read: Disabled */ -#define GPIOTE_INTENCLR_IN4_Enabled (1UL) /*!< Read: Enabled */ -#define GPIOTE_INTENCLR_IN4_Clear (1UL) /*!< Disable */ +#define GPIOTE_INTENCLR_IN4_Disabled (0x0UL) /*!< Read: Disabled */ +#define GPIOTE_INTENCLR_IN4_Enabled (0x1UL) /*!< Read: Enabled */ +#define GPIOTE_INTENCLR_IN4_Clear (0x1UL) /*!< Disable */ /* Bit 3 : Write '1' to disable interrupt for event IN[3] */ #define GPIOTE_INTENCLR_IN3_Pos (3UL) /*!< Position of IN3 field. */ #define GPIOTE_INTENCLR_IN3_Msk (0x1UL << GPIOTE_INTENCLR_IN3_Pos) /*!< Bit mask of IN3 field. */ -#define GPIOTE_INTENCLR_IN3_Disabled (0UL) /*!< Read: Disabled */ -#define GPIOTE_INTENCLR_IN3_Enabled (1UL) /*!< Read: Enabled */ -#define GPIOTE_INTENCLR_IN3_Clear (1UL) /*!< Disable */ +#define GPIOTE_INTENCLR_IN3_Disabled (0x0UL) /*!< Read: Disabled */ +#define GPIOTE_INTENCLR_IN3_Enabled (0x1UL) /*!< Read: Enabled */ +#define GPIOTE_INTENCLR_IN3_Clear (0x1UL) /*!< Disable */ /* Bit 2 : Write '1' to disable interrupt for event IN[2] */ #define GPIOTE_INTENCLR_IN2_Pos (2UL) /*!< Position of IN2 field. */ #define GPIOTE_INTENCLR_IN2_Msk (0x1UL << GPIOTE_INTENCLR_IN2_Pos) /*!< Bit mask of IN2 field. */ -#define GPIOTE_INTENCLR_IN2_Disabled (0UL) /*!< Read: Disabled */ -#define GPIOTE_INTENCLR_IN2_Enabled (1UL) /*!< Read: Enabled */ -#define GPIOTE_INTENCLR_IN2_Clear (1UL) /*!< Disable */ +#define GPIOTE_INTENCLR_IN2_Disabled (0x0UL) /*!< Read: Disabled */ +#define GPIOTE_INTENCLR_IN2_Enabled (0x1UL) /*!< Read: Enabled */ +#define GPIOTE_INTENCLR_IN2_Clear (0x1UL) /*!< Disable */ /* Bit 1 : Write '1' to disable interrupt for event IN[1] */ #define GPIOTE_INTENCLR_IN1_Pos (1UL) /*!< Position of IN1 field. */ #define GPIOTE_INTENCLR_IN1_Msk (0x1UL << GPIOTE_INTENCLR_IN1_Pos) /*!< Bit mask of IN1 field. */ -#define GPIOTE_INTENCLR_IN1_Disabled (0UL) /*!< Read: Disabled */ -#define GPIOTE_INTENCLR_IN1_Enabled (1UL) /*!< Read: Enabled */ -#define GPIOTE_INTENCLR_IN1_Clear (1UL) /*!< Disable */ +#define GPIOTE_INTENCLR_IN1_Disabled (0x0UL) /*!< Read: Disabled */ +#define GPIOTE_INTENCLR_IN1_Enabled (0x1UL) /*!< Read: Enabled */ +#define GPIOTE_INTENCLR_IN1_Clear (0x1UL) /*!< Disable */ /* Bit 0 : Write '1' to disable interrupt for event IN[0] */ #define GPIOTE_INTENCLR_IN0_Pos (0UL) /*!< Position of IN0 field. */ #define GPIOTE_INTENCLR_IN0_Msk (0x1UL << GPIOTE_INTENCLR_IN0_Pos) /*!< Bit mask of IN0 field. */ -#define GPIOTE_INTENCLR_IN0_Disabled (0UL) /*!< Read: Disabled */ -#define GPIOTE_INTENCLR_IN0_Enabled (1UL) /*!< Read: Enabled */ -#define GPIOTE_INTENCLR_IN0_Clear (1UL) /*!< Disable */ +#define GPIOTE_INTENCLR_IN0_Disabled (0x0UL) /*!< Read: Disabled */ +#define GPIOTE_INTENCLR_IN0_Enabled (0x1UL) /*!< Read: Enabled */ +#define GPIOTE_INTENCLR_IN0_Clear (0x1UL) /*!< Disable */ /* Register: GPIOTE_CONFIG */ /* Description: Description collection: Configuration for OUT[n], SET[n], and CLR[n] tasks and IN[n] event */ @@ -1740,16 +1740,16 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 20 : When in task mode: Initial value of the output when the GPIOTE channel is configured. When in event mode: No effect. */ #define GPIOTE_CONFIG_OUTINIT_Pos (20UL) /*!< Position of OUTINIT field. */ #define GPIOTE_CONFIG_OUTINIT_Msk (0x1UL << GPIOTE_CONFIG_OUTINIT_Pos) /*!< Bit mask of OUTINIT field. */ -#define GPIOTE_CONFIG_OUTINIT_Low (0UL) /*!< Task mode: Initial value of pin before task triggering is low */ -#define GPIOTE_CONFIG_OUTINIT_High (1UL) /*!< Task mode: Initial value of pin before task triggering is high */ +#define GPIOTE_CONFIG_OUTINIT_Low (0x0UL) /*!< Task mode: Initial value of pin before task triggering is low */ +#define GPIOTE_CONFIG_OUTINIT_High (0x1UL) /*!< Task mode: Initial value of pin before task triggering is high */ /* Bits 17..16 : When In task mode: Operation to be performed on output when OUT[n] task is triggered. When In event mode: Operation on input that shall trigger IN[n] event. */ #define GPIOTE_CONFIG_POLARITY_Pos (16UL) /*!< Position of POLARITY field. */ #define GPIOTE_CONFIG_POLARITY_Msk (0x3UL << GPIOTE_CONFIG_POLARITY_Pos) /*!< Bit mask of POLARITY field. */ -#define GPIOTE_CONFIG_POLARITY_None (0UL) /*!< Task mode: No effect on pin from OUT[n] task. Event mode: no IN[n] event generated on pin activity. */ -#define GPIOTE_CONFIG_POLARITY_LoToHi (1UL) /*!< Task mode: Set pin from OUT[n] task. Event mode: Generate IN[n] event when rising edge on pin. */ -#define GPIOTE_CONFIG_POLARITY_HiToLo (2UL) /*!< Task mode: Clear pin from OUT[n] task. Event mode: Generate IN[n] event when falling edge on pin. */ -#define GPIOTE_CONFIG_POLARITY_Toggle (3UL) /*!< Task mode: Toggle pin from OUT[n]. Event mode: Generate IN[n] when any change on pin. */ +#define GPIOTE_CONFIG_POLARITY_None (0x0UL) /*!< Task mode: No effect on pin from OUT[n] task. Event mode: no IN[n] event generated on pin activity. */ +#define GPIOTE_CONFIG_POLARITY_LoToHi (0x1UL) /*!< Task mode: Set pin from OUT[n] task. Event mode: Generate IN[n] event when rising edge on pin. */ +#define GPIOTE_CONFIG_POLARITY_HiToLo (0x2UL) /*!< Task mode: Clear pin from OUT[n] task. Event mode: Generate IN[n] event when falling edge on pin. */ +#define GPIOTE_CONFIG_POLARITY_Toggle (0x3UL) /*!< Task mode: Toggle pin from OUT[n]. Event mode: Generate IN[n] when any change on pin. */ /* Bits 12..8 : GPIO number associated with SET[n], CLR[n], and OUT[n] tasks and IN[n] event */ #define GPIOTE_CONFIG_PSEL_Pos (8UL) /*!< Position of PSEL field. */ @@ -1758,9 +1758,9 @@ POSSIBILITY OF SUCH DAMAGE. /* Bits 1..0 : Mode */ #define GPIOTE_CONFIG_MODE_Pos (0UL) /*!< Position of MODE field. */ #define GPIOTE_CONFIG_MODE_Msk (0x3UL << GPIOTE_CONFIG_MODE_Pos) /*!< Bit mask of MODE field. */ -#define GPIOTE_CONFIG_MODE_Disabled (0UL) /*!< Disabled. Pin specified by PSEL will not be acquired by the GPIOTE module. */ -#define GPIOTE_CONFIG_MODE_Event (1UL) /*!< Event mode */ -#define GPIOTE_CONFIG_MODE_Task (3UL) /*!< Task mode */ +#define GPIOTE_CONFIG_MODE_Disabled (0x0UL) /*!< Disabled. Pin specified by PSEL will not be acquired by the GPIOTE module. */ +#define GPIOTE_CONFIG_MODE_Event (0x1UL) /*!< Event mode */ +#define GPIOTE_CONFIG_MODE_Task (0x3UL) /*!< Task mode */ /* Peripheral: I2S */ @@ -1772,7 +1772,7 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 0 : Starts continuous I2S transfer. Also starts MCK generator when this is enabled. */ #define I2S_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */ #define I2S_TASKS_START_TASKS_START_Msk (0x1UL << I2S_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */ -#define I2S_TASKS_START_TASKS_START_Trigger (1UL) /*!< Trigger task */ +#define I2S_TASKS_START_TASKS_START_Trigger (0x1UL) /*!< Trigger task */ /* Register: I2S_TASKS_STOP */ /* Description: Stops I2S transfer. Also stops MCK generator. Triggering this task will cause the STOPPED event to be generated. */ @@ -1780,7 +1780,7 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 0 : Stops I2S transfer. Also stops MCK generator. Triggering this task will cause the STOPPED event to be generated. */ #define I2S_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */ #define I2S_TASKS_STOP_TASKS_STOP_Msk (0x1UL << I2S_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */ -#define I2S_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */ +#define I2S_TASKS_STOP_TASKS_STOP_Trigger (0x1UL) /*!< Trigger task */ /* Register: I2S_SUBSCRIBE_START */ /* Description: Subscribe configuration for task START */ @@ -1788,8 +1788,8 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 31 : */ #define I2S_SUBSCRIBE_START_EN_Pos (31UL) /*!< Position of EN field. */ #define I2S_SUBSCRIBE_START_EN_Msk (0x1UL << I2S_SUBSCRIBE_START_EN_Pos) /*!< Bit mask of EN field. */ -#define I2S_SUBSCRIBE_START_EN_Disabled (0UL) /*!< Disable subscription */ -#define I2S_SUBSCRIBE_START_EN_Enabled (1UL) /*!< Enable subscription */ +#define I2S_SUBSCRIBE_START_EN_Disabled (0x0UL) /*!< Disable subscription */ +#define I2S_SUBSCRIBE_START_EN_Enabled (0x1UL) /*!< Enable subscription */ /* Bits 7..0 : DPPI channel that task START will subscribe to */ #define I2S_SUBSCRIBE_START_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ @@ -1801,8 +1801,8 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 31 : */ #define I2S_SUBSCRIBE_STOP_EN_Pos (31UL) /*!< Position of EN field. */ #define I2S_SUBSCRIBE_STOP_EN_Msk (0x1UL << I2S_SUBSCRIBE_STOP_EN_Pos) /*!< Bit mask of EN field. */ -#define I2S_SUBSCRIBE_STOP_EN_Disabled (0UL) /*!< Disable subscription */ -#define I2S_SUBSCRIBE_STOP_EN_Enabled (1UL) /*!< Enable subscription */ +#define I2S_SUBSCRIBE_STOP_EN_Disabled (0x0UL) /*!< Disable subscription */ +#define I2S_SUBSCRIBE_STOP_EN_Enabled (0x1UL) /*!< Enable subscription */ /* Bits 7..0 : DPPI channel that task STOP will subscribe to */ #define I2S_SUBSCRIBE_STOP_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ @@ -1816,8 +1816,8 @@ POSSIBILITY OF SUCH DAMAGE. When the I2S module is started and RX is enabled, this event will be generated for every RXTXD.MAXCNT words that are received on the SDIN pin. */ #define I2S_EVENTS_RXPTRUPD_EVENTS_RXPTRUPD_Pos (0UL) /*!< Position of EVENTS_RXPTRUPD field. */ #define I2S_EVENTS_RXPTRUPD_EVENTS_RXPTRUPD_Msk (0x1UL << I2S_EVENTS_RXPTRUPD_EVENTS_RXPTRUPD_Pos) /*!< Bit mask of EVENTS_RXPTRUPD field. */ -#define I2S_EVENTS_RXPTRUPD_EVENTS_RXPTRUPD_NotGenerated (0UL) /*!< Event not generated */ -#define I2S_EVENTS_RXPTRUPD_EVENTS_RXPTRUPD_Generated (1UL) /*!< Event generated */ +#define I2S_EVENTS_RXPTRUPD_EVENTS_RXPTRUPD_NotGenerated (0x0UL) /*!< Event not generated */ +#define I2S_EVENTS_RXPTRUPD_EVENTS_RXPTRUPD_Generated (0x1UL) /*!< Event generated */ /* Register: I2S_EVENTS_STOPPED */ /* Description: I2S transfer stopped. */ @@ -1825,8 +1825,8 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 0 : I2S transfer stopped. */ #define I2S_EVENTS_STOPPED_EVENTS_STOPPED_Pos (0UL) /*!< Position of EVENTS_STOPPED field. */ #define I2S_EVENTS_STOPPED_EVENTS_STOPPED_Msk (0x1UL << I2S_EVENTS_STOPPED_EVENTS_STOPPED_Pos) /*!< Bit mask of EVENTS_STOPPED field. */ -#define I2S_EVENTS_STOPPED_EVENTS_STOPPED_NotGenerated (0UL) /*!< Event not generated */ -#define I2S_EVENTS_STOPPED_EVENTS_STOPPED_Generated (1UL) /*!< Event generated */ +#define I2S_EVENTS_STOPPED_EVENTS_STOPPED_NotGenerated (0x0UL) /*!< Event not generated */ +#define I2S_EVENTS_STOPPED_EVENTS_STOPPED_Generated (0x1UL) /*!< Event generated */ /* Register: I2S_EVENTS_TXPTRUPD */ /* Description: The TDX.PTR register has been copied to internal double-buffers. @@ -1836,8 +1836,8 @@ POSSIBILITY OF SUCH DAMAGE. When the I2S module is started and TX is enabled, this event will be generated for every RXTXD.MAXCNT words that are sent on the SDOUT pin. */ #define I2S_EVENTS_TXPTRUPD_EVENTS_TXPTRUPD_Pos (0UL) /*!< Position of EVENTS_TXPTRUPD field. */ #define I2S_EVENTS_TXPTRUPD_EVENTS_TXPTRUPD_Msk (0x1UL << I2S_EVENTS_TXPTRUPD_EVENTS_TXPTRUPD_Pos) /*!< Bit mask of EVENTS_TXPTRUPD field. */ -#define I2S_EVENTS_TXPTRUPD_EVENTS_TXPTRUPD_NotGenerated (0UL) /*!< Event not generated */ -#define I2S_EVENTS_TXPTRUPD_EVENTS_TXPTRUPD_Generated (1UL) /*!< Event generated */ +#define I2S_EVENTS_TXPTRUPD_EVENTS_TXPTRUPD_NotGenerated (0x0UL) /*!< Event not generated */ +#define I2S_EVENTS_TXPTRUPD_EVENTS_TXPTRUPD_Generated (0x1UL) /*!< Event generated */ /* Register: I2S_PUBLISH_RXPTRUPD */ /* Description: Publish configuration for event RXPTRUPD */ @@ -1845,8 +1845,8 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 31 : */ #define I2S_PUBLISH_RXPTRUPD_EN_Pos (31UL) /*!< Position of EN field. */ #define I2S_PUBLISH_RXPTRUPD_EN_Msk (0x1UL << I2S_PUBLISH_RXPTRUPD_EN_Pos) /*!< Bit mask of EN field. */ -#define I2S_PUBLISH_RXPTRUPD_EN_Disabled (0UL) /*!< Disable publishing */ -#define I2S_PUBLISH_RXPTRUPD_EN_Enabled (1UL) /*!< Enable publishing */ +#define I2S_PUBLISH_RXPTRUPD_EN_Disabled (0x0UL) /*!< Disable publishing */ +#define I2S_PUBLISH_RXPTRUPD_EN_Enabled (0x1UL) /*!< Enable publishing */ /* Bits 7..0 : DPPI channel that event RXPTRUPD will publish to */ #define I2S_PUBLISH_RXPTRUPD_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ @@ -1858,8 +1858,8 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 31 : */ #define I2S_PUBLISH_STOPPED_EN_Pos (31UL) /*!< Position of EN field. */ #define I2S_PUBLISH_STOPPED_EN_Msk (0x1UL << I2S_PUBLISH_STOPPED_EN_Pos) /*!< Bit mask of EN field. */ -#define I2S_PUBLISH_STOPPED_EN_Disabled (0UL) /*!< Disable publishing */ -#define I2S_PUBLISH_STOPPED_EN_Enabled (1UL) /*!< Enable publishing */ +#define I2S_PUBLISH_STOPPED_EN_Disabled (0x0UL) /*!< Disable publishing */ +#define I2S_PUBLISH_STOPPED_EN_Enabled (0x1UL) /*!< Enable publishing */ /* Bits 7..0 : DPPI channel that event STOPPED will publish to */ #define I2S_PUBLISH_STOPPED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ @@ -1871,8 +1871,8 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 31 : */ #define I2S_PUBLISH_TXPTRUPD_EN_Pos (31UL) /*!< Position of EN field. */ #define I2S_PUBLISH_TXPTRUPD_EN_Msk (0x1UL << I2S_PUBLISH_TXPTRUPD_EN_Pos) /*!< Bit mask of EN field. */ -#define I2S_PUBLISH_TXPTRUPD_EN_Disabled (0UL) /*!< Disable publishing */ -#define I2S_PUBLISH_TXPTRUPD_EN_Enabled (1UL) /*!< Enable publishing */ +#define I2S_PUBLISH_TXPTRUPD_EN_Disabled (0x0UL) /*!< Disable publishing */ +#define I2S_PUBLISH_TXPTRUPD_EN_Enabled (0x1UL) /*!< Enable publishing */ /* Bits 7..0 : DPPI channel that event TXPTRUPD will publish to */ #define I2S_PUBLISH_TXPTRUPD_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ @@ -1884,20 +1884,20 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 5 : Enable or disable interrupt for event TXPTRUPD */ #define I2S_INTEN_TXPTRUPD_Pos (5UL) /*!< Position of TXPTRUPD field. */ #define I2S_INTEN_TXPTRUPD_Msk (0x1UL << I2S_INTEN_TXPTRUPD_Pos) /*!< Bit mask of TXPTRUPD field. */ -#define I2S_INTEN_TXPTRUPD_Disabled (0UL) /*!< Disable */ -#define I2S_INTEN_TXPTRUPD_Enabled (1UL) /*!< Enable */ +#define I2S_INTEN_TXPTRUPD_Disabled (0x0UL) /*!< Disable */ +#define I2S_INTEN_TXPTRUPD_Enabled (0x1UL) /*!< Enable */ /* Bit 2 : Enable or disable interrupt for event STOPPED */ #define I2S_INTEN_STOPPED_Pos (2UL) /*!< Position of STOPPED field. */ #define I2S_INTEN_STOPPED_Msk (0x1UL << I2S_INTEN_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ -#define I2S_INTEN_STOPPED_Disabled (0UL) /*!< Disable */ -#define I2S_INTEN_STOPPED_Enabled (1UL) /*!< Enable */ +#define I2S_INTEN_STOPPED_Disabled (0x0UL) /*!< Disable */ +#define I2S_INTEN_STOPPED_Enabled (0x1UL) /*!< Enable */ /* Bit 1 : Enable or disable interrupt for event RXPTRUPD */ #define I2S_INTEN_RXPTRUPD_Pos (1UL) /*!< Position of RXPTRUPD field. */ #define I2S_INTEN_RXPTRUPD_Msk (0x1UL << I2S_INTEN_RXPTRUPD_Pos) /*!< Bit mask of RXPTRUPD field. */ -#define I2S_INTEN_RXPTRUPD_Disabled (0UL) /*!< Disable */ -#define I2S_INTEN_RXPTRUPD_Enabled (1UL) /*!< Enable */ +#define I2S_INTEN_RXPTRUPD_Disabled (0x0UL) /*!< Disable */ +#define I2S_INTEN_RXPTRUPD_Enabled (0x1UL) /*!< Enable */ /* Register: I2S_INTENSET */ /* Description: Enable interrupt */ @@ -1905,23 +1905,23 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 5 : Write '1' to enable interrupt for event TXPTRUPD */ #define I2S_INTENSET_TXPTRUPD_Pos (5UL) /*!< Position of TXPTRUPD field. */ #define I2S_INTENSET_TXPTRUPD_Msk (0x1UL << I2S_INTENSET_TXPTRUPD_Pos) /*!< Bit mask of TXPTRUPD field. */ -#define I2S_INTENSET_TXPTRUPD_Disabled (0UL) /*!< Read: Disabled */ -#define I2S_INTENSET_TXPTRUPD_Enabled (1UL) /*!< Read: Enabled */ -#define I2S_INTENSET_TXPTRUPD_Set (1UL) /*!< Enable */ +#define I2S_INTENSET_TXPTRUPD_Disabled (0x0UL) /*!< Read: Disabled */ +#define I2S_INTENSET_TXPTRUPD_Enabled (0x1UL) /*!< Read: Enabled */ +#define I2S_INTENSET_TXPTRUPD_Set (0x1UL) /*!< Enable */ /* Bit 2 : Write '1' to enable interrupt for event STOPPED */ #define I2S_INTENSET_STOPPED_Pos (2UL) /*!< Position of STOPPED field. */ #define I2S_INTENSET_STOPPED_Msk (0x1UL << I2S_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ -#define I2S_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */ -#define I2S_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */ -#define I2S_INTENSET_STOPPED_Set (1UL) /*!< Enable */ +#define I2S_INTENSET_STOPPED_Disabled (0x0UL) /*!< Read: Disabled */ +#define I2S_INTENSET_STOPPED_Enabled (0x1UL) /*!< Read: Enabled */ +#define I2S_INTENSET_STOPPED_Set (0x1UL) /*!< Enable */ /* Bit 1 : Write '1' to enable interrupt for event RXPTRUPD */ #define I2S_INTENSET_RXPTRUPD_Pos (1UL) /*!< Position of RXPTRUPD field. */ #define I2S_INTENSET_RXPTRUPD_Msk (0x1UL << I2S_INTENSET_RXPTRUPD_Pos) /*!< Bit mask of RXPTRUPD field. */ -#define I2S_INTENSET_RXPTRUPD_Disabled (0UL) /*!< Read: Disabled */ -#define I2S_INTENSET_RXPTRUPD_Enabled (1UL) /*!< Read: Enabled */ -#define I2S_INTENSET_RXPTRUPD_Set (1UL) /*!< Enable */ +#define I2S_INTENSET_RXPTRUPD_Disabled (0x0UL) /*!< Read: Disabled */ +#define I2S_INTENSET_RXPTRUPD_Enabled (0x1UL) /*!< Read: Enabled */ +#define I2S_INTENSET_RXPTRUPD_Set (0x1UL) /*!< Enable */ /* Register: I2S_INTENCLR */ /* Description: Disable interrupt */ @@ -1929,23 +1929,23 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 5 : Write '1' to disable interrupt for event TXPTRUPD */ #define I2S_INTENCLR_TXPTRUPD_Pos (5UL) /*!< Position of TXPTRUPD field. */ #define I2S_INTENCLR_TXPTRUPD_Msk (0x1UL << I2S_INTENCLR_TXPTRUPD_Pos) /*!< Bit mask of TXPTRUPD field. */ -#define I2S_INTENCLR_TXPTRUPD_Disabled (0UL) /*!< Read: Disabled */ -#define I2S_INTENCLR_TXPTRUPD_Enabled (1UL) /*!< Read: Enabled */ -#define I2S_INTENCLR_TXPTRUPD_Clear (1UL) /*!< Disable */ +#define I2S_INTENCLR_TXPTRUPD_Disabled (0x0UL) /*!< Read: Disabled */ +#define I2S_INTENCLR_TXPTRUPD_Enabled (0x1UL) /*!< Read: Enabled */ +#define I2S_INTENCLR_TXPTRUPD_Clear (0x1UL) /*!< Disable */ /* Bit 2 : Write '1' to disable interrupt for event STOPPED */ #define I2S_INTENCLR_STOPPED_Pos (2UL) /*!< Position of STOPPED field. */ #define I2S_INTENCLR_STOPPED_Msk (0x1UL << I2S_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ -#define I2S_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */ -#define I2S_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */ -#define I2S_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */ +#define I2S_INTENCLR_STOPPED_Disabled (0x0UL) /*!< Read: Disabled */ +#define I2S_INTENCLR_STOPPED_Enabled (0x1UL) /*!< Read: Enabled */ +#define I2S_INTENCLR_STOPPED_Clear (0x1UL) /*!< Disable */ /* Bit 1 : Write '1' to disable interrupt for event RXPTRUPD */ #define I2S_INTENCLR_RXPTRUPD_Pos (1UL) /*!< Position of RXPTRUPD field. */ #define I2S_INTENCLR_RXPTRUPD_Msk (0x1UL << I2S_INTENCLR_RXPTRUPD_Pos) /*!< Bit mask of RXPTRUPD field. */ -#define I2S_INTENCLR_RXPTRUPD_Disabled (0UL) /*!< Read: Disabled */ -#define I2S_INTENCLR_RXPTRUPD_Enabled (1UL) /*!< Read: Enabled */ -#define I2S_INTENCLR_RXPTRUPD_Clear (1UL) /*!< Disable */ +#define I2S_INTENCLR_RXPTRUPD_Disabled (0x0UL) /*!< Read: Disabled */ +#define I2S_INTENCLR_RXPTRUPD_Enabled (0x1UL) /*!< Read: Enabled */ +#define I2S_INTENCLR_RXPTRUPD_Clear (0x1UL) /*!< Disable */ /* Register: I2S_ENABLE */ /* Description: Enable I2S module. */ @@ -1953,8 +1953,8 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 0 : Enable I2S module. */ #define I2S_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ #define I2S_ENABLE_ENABLE_Msk (0x1UL << I2S_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ -#define I2S_ENABLE_ENABLE_Disabled (0UL) /*!< Disable */ -#define I2S_ENABLE_ENABLE_Enabled (1UL) /*!< Enable */ +#define I2S_ENABLE_ENABLE_Disabled (0x0UL) /*!< Disable */ +#define I2S_ENABLE_ENABLE_Enabled (0x1UL) /*!< Enable */ /* Register: I2S_CONFIG_MODE */ /* Description: I2S mode. */ @@ -1962,8 +1962,8 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 0 : I2S mode. */ #define I2S_CONFIG_MODE_MODE_Pos (0UL) /*!< Position of MODE field. */ #define I2S_CONFIG_MODE_MODE_Msk (0x1UL << I2S_CONFIG_MODE_MODE_Pos) /*!< Bit mask of MODE field. */ -#define I2S_CONFIG_MODE_MODE_Master (0UL) /*!< Master mode. SCK and LRCK generated from internal master clcok (MCK) and output on pins defined by PSEL.xxx. */ -#define I2S_CONFIG_MODE_MODE_Slave (1UL) /*!< Slave mode. SCK and LRCK generated by external master and received on pins defined by PSEL.xxx */ +#define I2S_CONFIG_MODE_MODE_Master (0x0UL) /*!< Master mode. SCK and LRCK generated from internal master clcok (MCK) and output on pins defined by PSEL.xxx. */ +#define I2S_CONFIG_MODE_MODE_Slave (0x1UL) /*!< Slave mode. SCK and LRCK generated by external master and received on pins defined by PSEL.xxx */ /* Register: I2S_CONFIG_RXEN */ /* Description: Reception (RX) enable. */ @@ -1971,8 +1971,8 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 0 : Reception (RX) enable. */ #define I2S_CONFIG_RXEN_RXEN_Pos (0UL) /*!< Position of RXEN field. */ #define I2S_CONFIG_RXEN_RXEN_Msk (0x1UL << I2S_CONFIG_RXEN_RXEN_Pos) /*!< Bit mask of RXEN field. */ -#define I2S_CONFIG_RXEN_RXEN_Disabled (0UL) /*!< Reception disabled and now data will be written to the RXD.PTR address. */ -#define I2S_CONFIG_RXEN_RXEN_Enabled (1UL) /*!< Reception enabled. */ +#define I2S_CONFIG_RXEN_RXEN_Disabled (0x0UL) /*!< Reception disabled and now data will be written to the RXD.PTR address. */ +#define I2S_CONFIG_RXEN_RXEN_Enabled (0x1UL) /*!< Reception enabled. */ /* Register: I2S_CONFIG_TXEN */ /* Description: Transmission (TX) enable. */ @@ -1980,8 +1980,8 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 0 : Transmission (TX) enable. */ #define I2S_CONFIG_TXEN_TXEN_Pos (0UL) /*!< Position of TXEN field. */ #define I2S_CONFIG_TXEN_TXEN_Msk (0x1UL << I2S_CONFIG_TXEN_TXEN_Pos) /*!< Bit mask of TXEN field. */ -#define I2S_CONFIG_TXEN_TXEN_Disabled (0UL) /*!< Transmission disabled and now data will be read from the RXD.TXD address. */ -#define I2S_CONFIG_TXEN_TXEN_Enabled (1UL) /*!< Transmission enabled. */ +#define I2S_CONFIG_TXEN_TXEN_Disabled (0x0UL) /*!< Transmission disabled and now data will be read from the RXD.TXD address. */ +#define I2S_CONFIG_TXEN_TXEN_Enabled (0x1UL) /*!< Transmission enabled. */ /* Register: I2S_CONFIG_MCKEN */ /* Description: Master clock generator enable. */ @@ -1989,8 +1989,8 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 0 : Master clock generator enable. */ #define I2S_CONFIG_MCKEN_MCKEN_Pos (0UL) /*!< Position of MCKEN field. */ #define I2S_CONFIG_MCKEN_MCKEN_Msk (0x1UL << I2S_CONFIG_MCKEN_MCKEN_Pos) /*!< Bit mask of MCKEN field. */ -#define I2S_CONFIG_MCKEN_MCKEN_Disabled (0UL) /*!< Master clock generator disabled and PSEL.MCK not connected(available as GPIO). */ -#define I2S_CONFIG_MCKEN_MCKEN_Enabled (1UL) /*!< Master clock generator running and MCK output on PSEL.MCK. */ +#define I2S_CONFIG_MCKEN_MCKEN_Disabled (0x0UL) /*!< Master clock generator disabled and PSEL.MCK not connected(available as GPIO). */ +#define I2S_CONFIG_MCKEN_MCKEN_Enabled (0x1UL) /*!< Master clock generator running and MCK output on PSEL.MCK. */ /* Register: I2S_CONFIG_MCKFREQ */ /* Description: Master clock generator frequency. */ @@ -2018,15 +2018,15 @@ POSSIBILITY OF SUCH DAMAGE. /* Bits 3..0 : MCK / LRCK ratio. */ #define I2S_CONFIG_RATIO_RATIO_Pos (0UL) /*!< Position of RATIO field. */ #define I2S_CONFIG_RATIO_RATIO_Msk (0xFUL << I2S_CONFIG_RATIO_RATIO_Pos) /*!< Bit mask of RATIO field. */ -#define I2S_CONFIG_RATIO_RATIO_32X (0UL) /*!< LRCK = MCK / 32 */ -#define I2S_CONFIG_RATIO_RATIO_48X (1UL) /*!< LRCK = MCK / 48 */ -#define I2S_CONFIG_RATIO_RATIO_64X (2UL) /*!< LRCK = MCK / 64 */ -#define I2S_CONFIG_RATIO_RATIO_96X (3UL) /*!< LRCK = MCK / 96 */ -#define I2S_CONFIG_RATIO_RATIO_128X (4UL) /*!< LRCK = MCK / 128 */ -#define I2S_CONFIG_RATIO_RATIO_192X (5UL) /*!< LRCK = MCK / 192 */ -#define I2S_CONFIG_RATIO_RATIO_256X (6UL) /*!< LRCK = MCK / 256 */ -#define I2S_CONFIG_RATIO_RATIO_384X (7UL) /*!< LRCK = MCK / 384 */ -#define I2S_CONFIG_RATIO_RATIO_512X (8UL) /*!< LRCK = MCK / 512 */ +#define I2S_CONFIG_RATIO_RATIO_32X (0x0UL) /*!< LRCK = MCK / 32 */ +#define I2S_CONFIG_RATIO_RATIO_48X (0x1UL) /*!< LRCK = MCK / 48 */ +#define I2S_CONFIG_RATIO_RATIO_64X (0x2UL) /*!< LRCK = MCK / 64 */ +#define I2S_CONFIG_RATIO_RATIO_96X (0x3UL) /*!< LRCK = MCK / 96 */ +#define I2S_CONFIG_RATIO_RATIO_128X (0x4UL) /*!< LRCK = MCK / 128 */ +#define I2S_CONFIG_RATIO_RATIO_192X (0x5UL) /*!< LRCK = MCK / 192 */ +#define I2S_CONFIG_RATIO_RATIO_256X (0x6UL) /*!< LRCK = MCK / 256 */ +#define I2S_CONFIG_RATIO_RATIO_384X (0x7UL) /*!< LRCK = MCK / 384 */ +#define I2S_CONFIG_RATIO_RATIO_512X (0x8UL) /*!< LRCK = MCK / 512 */ /* Register: I2S_CONFIG_SWIDTH */ /* Description: Sample width. */ @@ -2034,9 +2034,9 @@ POSSIBILITY OF SUCH DAMAGE. /* Bits 1..0 : Sample width. */ #define I2S_CONFIG_SWIDTH_SWIDTH_Pos (0UL) /*!< Position of SWIDTH field. */ #define I2S_CONFIG_SWIDTH_SWIDTH_Msk (0x3UL << I2S_CONFIG_SWIDTH_SWIDTH_Pos) /*!< Bit mask of SWIDTH field. */ -#define I2S_CONFIG_SWIDTH_SWIDTH_8Bit (0UL) /*!< 8 bit. */ -#define I2S_CONFIG_SWIDTH_SWIDTH_16Bit (1UL) /*!< 16 bit. */ -#define I2S_CONFIG_SWIDTH_SWIDTH_24Bit (2UL) /*!< 24 bit. */ +#define I2S_CONFIG_SWIDTH_SWIDTH_8Bit (0x0UL) /*!< 8 bit. */ +#define I2S_CONFIG_SWIDTH_SWIDTH_16Bit (0x1UL) /*!< 16 bit. */ +#define I2S_CONFIG_SWIDTH_SWIDTH_24Bit (0x2UL) /*!< 24 bit. */ /* Register: I2S_CONFIG_ALIGN */ /* Description: Alignment of sample within a frame. */ @@ -2044,8 +2044,8 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 0 : Alignment of sample within a frame. */ #define I2S_CONFIG_ALIGN_ALIGN_Pos (0UL) /*!< Position of ALIGN field. */ #define I2S_CONFIG_ALIGN_ALIGN_Msk (0x1UL << I2S_CONFIG_ALIGN_ALIGN_Pos) /*!< Bit mask of ALIGN field. */ -#define I2S_CONFIG_ALIGN_ALIGN_Left (0UL) /*!< Left-aligned. */ -#define I2S_CONFIG_ALIGN_ALIGN_Right (1UL) /*!< Right-aligned. */ +#define I2S_CONFIG_ALIGN_ALIGN_Left (0x0UL) /*!< Left-aligned. */ +#define I2S_CONFIG_ALIGN_ALIGN_Right (0x1UL) /*!< Right-aligned. */ /* Register: I2S_CONFIG_FORMAT */ /* Description: Frame format. */ @@ -2053,8 +2053,8 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 0 : Frame format. */ #define I2S_CONFIG_FORMAT_FORMAT_Pos (0UL) /*!< Position of FORMAT field. */ #define I2S_CONFIG_FORMAT_FORMAT_Msk (0x1UL << I2S_CONFIG_FORMAT_FORMAT_Pos) /*!< Bit mask of FORMAT field. */ -#define I2S_CONFIG_FORMAT_FORMAT_I2S (0UL) /*!< Original I2S format. */ -#define I2S_CONFIG_FORMAT_FORMAT_Aligned (1UL) /*!< Alternate (left- or right-aligned) format. */ +#define I2S_CONFIG_FORMAT_FORMAT_I2S (0x0UL) /*!< Original I2S format. */ +#define I2S_CONFIG_FORMAT_FORMAT_Aligned (0x1UL) /*!< Alternate (left- or right-aligned) format. */ /* Register: I2S_CONFIG_CHANNELS */ /* Description: Enable channels. */ @@ -2062,9 +2062,9 @@ POSSIBILITY OF SUCH DAMAGE. /* Bits 1..0 : Enable channels. */ #define I2S_CONFIG_CHANNELS_CHANNELS_Pos (0UL) /*!< Position of CHANNELS field. */ #define I2S_CONFIG_CHANNELS_CHANNELS_Msk (0x3UL << I2S_CONFIG_CHANNELS_CHANNELS_Pos) /*!< Bit mask of CHANNELS field. */ -#define I2S_CONFIG_CHANNELS_CHANNELS_Stereo (0UL) /*!< Stereo. */ -#define I2S_CONFIG_CHANNELS_CHANNELS_Left (1UL) /*!< Left only. */ -#define I2S_CONFIG_CHANNELS_CHANNELS_Right (2UL) /*!< Right only. */ +#define I2S_CONFIG_CHANNELS_CHANNELS_Stereo (0x0UL) /*!< Stereo. */ +#define I2S_CONFIG_CHANNELS_CHANNELS_Left (0x1UL) /*!< Left only. */ +#define I2S_CONFIG_CHANNELS_CHANNELS_Right (0x2UL) /*!< Right only. */ /* Register: I2S_RXD_PTR */ /* Description: Receive buffer RAM start address. */ @@ -2093,8 +2093,8 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 31 : Connection */ #define I2S_PSEL_MCK_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ #define I2S_PSEL_MCK_CONNECT_Msk (0x1UL << I2S_PSEL_MCK_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ -#define I2S_PSEL_MCK_CONNECT_Connected (0UL) /*!< Connect */ -#define I2S_PSEL_MCK_CONNECT_Disconnected (1UL) /*!< Disconnect */ +#define I2S_PSEL_MCK_CONNECT_Connected (0x0UL) /*!< Connect */ +#define I2S_PSEL_MCK_CONNECT_Disconnected (0x1UL) /*!< Disconnect */ /* Bits 4..0 : Pin number */ #define I2S_PSEL_MCK_PIN_Pos (0UL) /*!< Position of PIN field. */ @@ -2106,8 +2106,8 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 31 : Connection */ #define I2S_PSEL_SCK_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ #define I2S_PSEL_SCK_CONNECT_Msk (0x1UL << I2S_PSEL_SCK_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ -#define I2S_PSEL_SCK_CONNECT_Connected (0UL) /*!< Connect */ -#define I2S_PSEL_SCK_CONNECT_Disconnected (1UL) /*!< Disconnect */ +#define I2S_PSEL_SCK_CONNECT_Connected (0x0UL) /*!< Connect */ +#define I2S_PSEL_SCK_CONNECT_Disconnected (0x1UL) /*!< Disconnect */ /* Bits 4..0 : Pin number */ #define I2S_PSEL_SCK_PIN_Pos (0UL) /*!< Position of PIN field. */ @@ -2119,8 +2119,8 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 31 : Connection */ #define I2S_PSEL_LRCK_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ #define I2S_PSEL_LRCK_CONNECT_Msk (0x1UL << I2S_PSEL_LRCK_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ -#define I2S_PSEL_LRCK_CONNECT_Connected (0UL) /*!< Connect */ -#define I2S_PSEL_LRCK_CONNECT_Disconnected (1UL) /*!< Disconnect */ +#define I2S_PSEL_LRCK_CONNECT_Connected (0x0UL) /*!< Connect */ +#define I2S_PSEL_LRCK_CONNECT_Disconnected (0x1UL) /*!< Disconnect */ /* Bits 4..0 : Pin number */ #define I2S_PSEL_LRCK_PIN_Pos (0UL) /*!< Position of PIN field. */ @@ -2132,8 +2132,8 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 31 : Connection */ #define I2S_PSEL_SDIN_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ #define I2S_PSEL_SDIN_CONNECT_Msk (0x1UL << I2S_PSEL_SDIN_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ -#define I2S_PSEL_SDIN_CONNECT_Connected (0UL) /*!< Connect */ -#define I2S_PSEL_SDIN_CONNECT_Disconnected (1UL) /*!< Disconnect */ +#define I2S_PSEL_SDIN_CONNECT_Connected (0x0UL) /*!< Connect */ +#define I2S_PSEL_SDIN_CONNECT_Disconnected (0x1UL) /*!< Disconnect */ /* Bits 4..0 : Pin number */ #define I2S_PSEL_SDIN_PIN_Pos (0UL) /*!< Position of PIN field. */ @@ -2145,8 +2145,8 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 31 : Connection */ #define I2S_PSEL_SDOUT_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ #define I2S_PSEL_SDOUT_CONNECT_Msk (0x1UL << I2S_PSEL_SDOUT_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ -#define I2S_PSEL_SDOUT_CONNECT_Connected (0UL) /*!< Connect */ -#define I2S_PSEL_SDOUT_CONNECT_Disconnected (1UL) /*!< Disconnect */ +#define I2S_PSEL_SDOUT_CONNECT_Connected (0x0UL) /*!< Connect */ +#define I2S_PSEL_SDOUT_CONNECT_Disconnected (0x1UL) /*!< Disconnect */ /* Bits 4..0 : Pin number */ #define I2S_PSEL_SDOUT_PIN_Pos (0UL) /*!< Position of PIN field. */ @@ -2162,7 +2162,7 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 0 : Trigger events on IPC channel enabled in SEND_CNF[n] */ #define IPC_TASKS_SEND_TASKS_SEND_Pos (0UL) /*!< Position of TASKS_SEND field. */ #define IPC_TASKS_SEND_TASKS_SEND_Msk (0x1UL << IPC_TASKS_SEND_TASKS_SEND_Pos) /*!< Bit mask of TASKS_SEND field. */ -#define IPC_TASKS_SEND_TASKS_SEND_Trigger (1UL) /*!< Trigger task */ +#define IPC_TASKS_SEND_TASKS_SEND_Trigger (0x1UL) /*!< Trigger task */ /* Register: IPC_SUBSCRIBE_SEND */ /* Description: Description collection: Subscribe configuration for task SEND[n] */ @@ -2170,8 +2170,8 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 31 : */ #define IPC_SUBSCRIBE_SEND_EN_Pos (31UL) /*!< Position of EN field. */ #define IPC_SUBSCRIBE_SEND_EN_Msk (0x1UL << IPC_SUBSCRIBE_SEND_EN_Pos) /*!< Bit mask of EN field. */ -#define IPC_SUBSCRIBE_SEND_EN_Disabled (0UL) /*!< Disable subscription */ -#define IPC_SUBSCRIBE_SEND_EN_Enabled (1UL) /*!< Enable subscription */ +#define IPC_SUBSCRIBE_SEND_EN_Disabled (0x0UL) /*!< Disable subscription */ +#define IPC_SUBSCRIBE_SEND_EN_Enabled (0x1UL) /*!< Enable subscription */ /* Bits 7..0 : DPPI channel that task SEND[n] will subscribe to */ #define IPC_SUBSCRIBE_SEND_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ @@ -2183,8 +2183,8 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 0 : Event received on one or more of the enabled IPC channels in RECEIVE_CNF[n] */ #define IPC_EVENTS_RECEIVE_EVENTS_RECEIVE_Pos (0UL) /*!< Position of EVENTS_RECEIVE field. */ #define IPC_EVENTS_RECEIVE_EVENTS_RECEIVE_Msk (0x1UL << IPC_EVENTS_RECEIVE_EVENTS_RECEIVE_Pos) /*!< Bit mask of EVENTS_RECEIVE field. */ -#define IPC_EVENTS_RECEIVE_EVENTS_RECEIVE_NotGenerated (0UL) /*!< Event not generated */ -#define IPC_EVENTS_RECEIVE_EVENTS_RECEIVE_Generated (1UL) /*!< Event generated */ +#define IPC_EVENTS_RECEIVE_EVENTS_RECEIVE_NotGenerated (0x0UL) /*!< Event not generated */ +#define IPC_EVENTS_RECEIVE_EVENTS_RECEIVE_Generated (0x1UL) /*!< Event generated */ /* Register: IPC_PUBLISH_RECEIVE */ /* Description: Description collection: Publish configuration for event RECEIVE[n] */ @@ -2192,8 +2192,8 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 31 : */ #define IPC_PUBLISH_RECEIVE_EN_Pos (31UL) /*!< Position of EN field. */ #define IPC_PUBLISH_RECEIVE_EN_Msk (0x1UL << IPC_PUBLISH_RECEIVE_EN_Pos) /*!< Bit mask of EN field. */ -#define IPC_PUBLISH_RECEIVE_EN_Disabled (0UL) /*!< Disable publishing */ -#define IPC_PUBLISH_RECEIVE_EN_Enabled (1UL) /*!< Enable publishing */ +#define IPC_PUBLISH_RECEIVE_EN_Disabled (0x0UL) /*!< Disable publishing */ +#define IPC_PUBLISH_RECEIVE_EN_Enabled (0x1UL) /*!< Enable publishing */ /* Bits 7..0 : DPPI channel that event RECEIVE[n] will publish to */ #define IPC_PUBLISH_RECEIVE_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ @@ -2205,50 +2205,50 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 7 : Enable or disable interrupt for event RECEIVE[7] */ #define IPC_INTEN_RECEIVE7_Pos (7UL) /*!< Position of RECEIVE7 field. */ #define IPC_INTEN_RECEIVE7_Msk (0x1UL << IPC_INTEN_RECEIVE7_Pos) /*!< Bit mask of RECEIVE7 field. */ -#define IPC_INTEN_RECEIVE7_Disabled (0UL) /*!< Disable */ -#define IPC_INTEN_RECEIVE7_Enabled (1UL) /*!< Enable */ +#define IPC_INTEN_RECEIVE7_Disabled (0x0UL) /*!< Disable */ +#define IPC_INTEN_RECEIVE7_Enabled (0x1UL) /*!< Enable */ /* Bit 6 : Enable or disable interrupt for event RECEIVE[6] */ #define IPC_INTEN_RECEIVE6_Pos (6UL) /*!< Position of RECEIVE6 field. */ #define IPC_INTEN_RECEIVE6_Msk (0x1UL << IPC_INTEN_RECEIVE6_Pos) /*!< Bit mask of RECEIVE6 field. */ -#define IPC_INTEN_RECEIVE6_Disabled (0UL) /*!< Disable */ -#define IPC_INTEN_RECEIVE6_Enabled (1UL) /*!< Enable */ +#define IPC_INTEN_RECEIVE6_Disabled (0x0UL) /*!< Disable */ +#define IPC_INTEN_RECEIVE6_Enabled (0x1UL) /*!< Enable */ /* Bit 5 : Enable or disable interrupt for event RECEIVE[5] */ #define IPC_INTEN_RECEIVE5_Pos (5UL) /*!< Position of RECEIVE5 field. */ #define IPC_INTEN_RECEIVE5_Msk (0x1UL << IPC_INTEN_RECEIVE5_Pos) /*!< Bit mask of RECEIVE5 field. */ -#define IPC_INTEN_RECEIVE5_Disabled (0UL) /*!< Disable */ -#define IPC_INTEN_RECEIVE5_Enabled (1UL) /*!< Enable */ +#define IPC_INTEN_RECEIVE5_Disabled (0x0UL) /*!< Disable */ +#define IPC_INTEN_RECEIVE5_Enabled (0x1UL) /*!< Enable */ /* Bit 4 : Enable or disable interrupt for event RECEIVE[4] */ #define IPC_INTEN_RECEIVE4_Pos (4UL) /*!< Position of RECEIVE4 field. */ #define IPC_INTEN_RECEIVE4_Msk (0x1UL << IPC_INTEN_RECEIVE4_Pos) /*!< Bit mask of RECEIVE4 field. */ -#define IPC_INTEN_RECEIVE4_Disabled (0UL) /*!< Disable */ -#define IPC_INTEN_RECEIVE4_Enabled (1UL) /*!< Enable */ +#define IPC_INTEN_RECEIVE4_Disabled (0x0UL) /*!< Disable */ +#define IPC_INTEN_RECEIVE4_Enabled (0x1UL) /*!< Enable */ /* Bit 3 : Enable or disable interrupt for event RECEIVE[3] */ #define IPC_INTEN_RECEIVE3_Pos (3UL) /*!< Position of RECEIVE3 field. */ #define IPC_INTEN_RECEIVE3_Msk (0x1UL << IPC_INTEN_RECEIVE3_Pos) /*!< Bit mask of RECEIVE3 field. */ -#define IPC_INTEN_RECEIVE3_Disabled (0UL) /*!< Disable */ -#define IPC_INTEN_RECEIVE3_Enabled (1UL) /*!< Enable */ +#define IPC_INTEN_RECEIVE3_Disabled (0x0UL) /*!< Disable */ +#define IPC_INTEN_RECEIVE3_Enabled (0x1UL) /*!< Enable */ /* Bit 2 : Enable or disable interrupt for event RECEIVE[2] */ #define IPC_INTEN_RECEIVE2_Pos (2UL) /*!< Position of RECEIVE2 field. */ #define IPC_INTEN_RECEIVE2_Msk (0x1UL << IPC_INTEN_RECEIVE2_Pos) /*!< Bit mask of RECEIVE2 field. */ -#define IPC_INTEN_RECEIVE2_Disabled (0UL) /*!< Disable */ -#define IPC_INTEN_RECEIVE2_Enabled (1UL) /*!< Enable */ +#define IPC_INTEN_RECEIVE2_Disabled (0x0UL) /*!< Disable */ +#define IPC_INTEN_RECEIVE2_Enabled (0x1UL) /*!< Enable */ /* Bit 1 : Enable or disable interrupt for event RECEIVE[1] */ #define IPC_INTEN_RECEIVE1_Pos (1UL) /*!< Position of RECEIVE1 field. */ #define IPC_INTEN_RECEIVE1_Msk (0x1UL << IPC_INTEN_RECEIVE1_Pos) /*!< Bit mask of RECEIVE1 field. */ -#define IPC_INTEN_RECEIVE1_Disabled (0UL) /*!< Disable */ -#define IPC_INTEN_RECEIVE1_Enabled (1UL) /*!< Enable */ +#define IPC_INTEN_RECEIVE1_Disabled (0x0UL) /*!< Disable */ +#define IPC_INTEN_RECEIVE1_Enabled (0x1UL) /*!< Enable */ /* Bit 0 : Enable or disable interrupt for event RECEIVE[0] */ #define IPC_INTEN_RECEIVE0_Pos (0UL) /*!< Position of RECEIVE0 field. */ #define IPC_INTEN_RECEIVE0_Msk (0x1UL << IPC_INTEN_RECEIVE0_Pos) /*!< Bit mask of RECEIVE0 field. */ -#define IPC_INTEN_RECEIVE0_Disabled (0UL) /*!< Disable */ -#define IPC_INTEN_RECEIVE0_Enabled (1UL) /*!< Enable */ +#define IPC_INTEN_RECEIVE0_Disabled (0x0UL) /*!< Disable */ +#define IPC_INTEN_RECEIVE0_Enabled (0x1UL) /*!< Enable */ /* Register: IPC_INTENSET */ /* Description: Enable interrupt */ @@ -2256,58 +2256,58 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 7 : Write '1' to enable interrupt for event RECEIVE[7] */ #define IPC_INTENSET_RECEIVE7_Pos (7UL) /*!< Position of RECEIVE7 field. */ #define IPC_INTENSET_RECEIVE7_Msk (0x1UL << IPC_INTENSET_RECEIVE7_Pos) /*!< Bit mask of RECEIVE7 field. */ -#define IPC_INTENSET_RECEIVE7_Disabled (0UL) /*!< Read: Disabled */ -#define IPC_INTENSET_RECEIVE7_Enabled (1UL) /*!< Read: Enabled */ -#define IPC_INTENSET_RECEIVE7_Set (1UL) /*!< Enable */ +#define IPC_INTENSET_RECEIVE7_Disabled (0x0UL) /*!< Read: Disabled */ +#define IPC_INTENSET_RECEIVE7_Enabled (0x1UL) /*!< Read: Enabled */ +#define IPC_INTENSET_RECEIVE7_Set (0x1UL) /*!< Enable */ /* Bit 6 : Write '1' to enable interrupt for event RECEIVE[6] */ #define IPC_INTENSET_RECEIVE6_Pos (6UL) /*!< Position of RECEIVE6 field. */ #define IPC_INTENSET_RECEIVE6_Msk (0x1UL << IPC_INTENSET_RECEIVE6_Pos) /*!< Bit mask of RECEIVE6 field. */ -#define IPC_INTENSET_RECEIVE6_Disabled (0UL) /*!< Read: Disabled */ -#define IPC_INTENSET_RECEIVE6_Enabled (1UL) /*!< Read: Enabled */ -#define IPC_INTENSET_RECEIVE6_Set (1UL) /*!< Enable */ +#define IPC_INTENSET_RECEIVE6_Disabled (0x0UL) /*!< Read: Disabled */ +#define IPC_INTENSET_RECEIVE6_Enabled (0x1UL) /*!< Read: Enabled */ +#define IPC_INTENSET_RECEIVE6_Set (0x1UL) /*!< Enable */ /* Bit 5 : Write '1' to enable interrupt for event RECEIVE[5] */ #define IPC_INTENSET_RECEIVE5_Pos (5UL) /*!< Position of RECEIVE5 field. */ #define IPC_INTENSET_RECEIVE5_Msk (0x1UL << IPC_INTENSET_RECEIVE5_Pos) /*!< Bit mask of RECEIVE5 field. */ -#define IPC_INTENSET_RECEIVE5_Disabled (0UL) /*!< Read: Disabled */ -#define IPC_INTENSET_RECEIVE5_Enabled (1UL) /*!< Read: Enabled */ -#define IPC_INTENSET_RECEIVE5_Set (1UL) /*!< Enable */ +#define IPC_INTENSET_RECEIVE5_Disabled (0x0UL) /*!< Read: Disabled */ +#define IPC_INTENSET_RECEIVE5_Enabled (0x1UL) /*!< Read: Enabled */ +#define IPC_INTENSET_RECEIVE5_Set (0x1UL) /*!< Enable */ /* Bit 4 : Write '1' to enable interrupt for event RECEIVE[4] */ #define IPC_INTENSET_RECEIVE4_Pos (4UL) /*!< Position of RECEIVE4 field. */ #define IPC_INTENSET_RECEIVE4_Msk (0x1UL << IPC_INTENSET_RECEIVE4_Pos) /*!< Bit mask of RECEIVE4 field. */ -#define IPC_INTENSET_RECEIVE4_Disabled (0UL) /*!< Read: Disabled */ -#define IPC_INTENSET_RECEIVE4_Enabled (1UL) /*!< Read: Enabled */ -#define IPC_INTENSET_RECEIVE4_Set (1UL) /*!< Enable */ +#define IPC_INTENSET_RECEIVE4_Disabled (0x0UL) /*!< Read: Disabled */ +#define IPC_INTENSET_RECEIVE4_Enabled (0x1UL) /*!< Read: Enabled */ +#define IPC_INTENSET_RECEIVE4_Set (0x1UL) /*!< Enable */ /* Bit 3 : Write '1' to enable interrupt for event RECEIVE[3] */ #define IPC_INTENSET_RECEIVE3_Pos (3UL) /*!< Position of RECEIVE3 field. */ #define IPC_INTENSET_RECEIVE3_Msk (0x1UL << IPC_INTENSET_RECEIVE3_Pos) /*!< Bit mask of RECEIVE3 field. */ -#define IPC_INTENSET_RECEIVE3_Disabled (0UL) /*!< Read: Disabled */ -#define IPC_INTENSET_RECEIVE3_Enabled (1UL) /*!< Read: Enabled */ -#define IPC_INTENSET_RECEIVE3_Set (1UL) /*!< Enable */ +#define IPC_INTENSET_RECEIVE3_Disabled (0x0UL) /*!< Read: Disabled */ +#define IPC_INTENSET_RECEIVE3_Enabled (0x1UL) /*!< Read: Enabled */ +#define IPC_INTENSET_RECEIVE3_Set (0x1UL) /*!< Enable */ /* Bit 2 : Write '1' to enable interrupt for event RECEIVE[2] */ #define IPC_INTENSET_RECEIVE2_Pos (2UL) /*!< Position of RECEIVE2 field. */ #define IPC_INTENSET_RECEIVE2_Msk (0x1UL << IPC_INTENSET_RECEIVE2_Pos) /*!< Bit mask of RECEIVE2 field. */ -#define IPC_INTENSET_RECEIVE2_Disabled (0UL) /*!< Read: Disabled */ -#define IPC_INTENSET_RECEIVE2_Enabled (1UL) /*!< Read: Enabled */ -#define IPC_INTENSET_RECEIVE2_Set (1UL) /*!< Enable */ +#define IPC_INTENSET_RECEIVE2_Disabled (0x0UL) /*!< Read: Disabled */ +#define IPC_INTENSET_RECEIVE2_Enabled (0x1UL) /*!< Read: Enabled */ +#define IPC_INTENSET_RECEIVE2_Set (0x1UL) /*!< Enable */ /* Bit 1 : Write '1' to enable interrupt for event RECEIVE[1] */ #define IPC_INTENSET_RECEIVE1_Pos (1UL) /*!< Position of RECEIVE1 field. */ #define IPC_INTENSET_RECEIVE1_Msk (0x1UL << IPC_INTENSET_RECEIVE1_Pos) /*!< Bit mask of RECEIVE1 field. */ -#define IPC_INTENSET_RECEIVE1_Disabled (0UL) /*!< Read: Disabled */ -#define IPC_INTENSET_RECEIVE1_Enabled (1UL) /*!< Read: Enabled */ -#define IPC_INTENSET_RECEIVE1_Set (1UL) /*!< Enable */ +#define IPC_INTENSET_RECEIVE1_Disabled (0x0UL) /*!< Read: Disabled */ +#define IPC_INTENSET_RECEIVE1_Enabled (0x1UL) /*!< Read: Enabled */ +#define IPC_INTENSET_RECEIVE1_Set (0x1UL) /*!< Enable */ /* Bit 0 : Write '1' to enable interrupt for event RECEIVE[0] */ #define IPC_INTENSET_RECEIVE0_Pos (0UL) /*!< Position of RECEIVE0 field. */ #define IPC_INTENSET_RECEIVE0_Msk (0x1UL << IPC_INTENSET_RECEIVE0_Pos) /*!< Bit mask of RECEIVE0 field. */ -#define IPC_INTENSET_RECEIVE0_Disabled (0UL) /*!< Read: Disabled */ -#define IPC_INTENSET_RECEIVE0_Enabled (1UL) /*!< Read: Enabled */ -#define IPC_INTENSET_RECEIVE0_Set (1UL) /*!< Enable */ +#define IPC_INTENSET_RECEIVE0_Disabled (0x0UL) /*!< Read: Disabled */ +#define IPC_INTENSET_RECEIVE0_Enabled (0x1UL) /*!< Read: Enabled */ +#define IPC_INTENSET_RECEIVE0_Set (0x1UL) /*!< Enable */ /* Register: IPC_INTENCLR */ /* Description: Disable interrupt */ @@ -2315,58 +2315,58 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 7 : Write '1' to disable interrupt for event RECEIVE[7] */ #define IPC_INTENCLR_RECEIVE7_Pos (7UL) /*!< Position of RECEIVE7 field. */ #define IPC_INTENCLR_RECEIVE7_Msk (0x1UL << IPC_INTENCLR_RECEIVE7_Pos) /*!< Bit mask of RECEIVE7 field. */ -#define IPC_INTENCLR_RECEIVE7_Disabled (0UL) /*!< Read: Disabled */ -#define IPC_INTENCLR_RECEIVE7_Enabled (1UL) /*!< Read: Enabled */ -#define IPC_INTENCLR_RECEIVE7_Clear (1UL) /*!< Disable */ +#define IPC_INTENCLR_RECEIVE7_Disabled (0x0UL) /*!< Read: Disabled */ +#define IPC_INTENCLR_RECEIVE7_Enabled (0x1UL) /*!< Read: Enabled */ +#define IPC_INTENCLR_RECEIVE7_Clear (0x1UL) /*!< Disable */ /* Bit 6 : Write '1' to disable interrupt for event RECEIVE[6] */ #define IPC_INTENCLR_RECEIVE6_Pos (6UL) /*!< Position of RECEIVE6 field. */ #define IPC_INTENCLR_RECEIVE6_Msk (0x1UL << IPC_INTENCLR_RECEIVE6_Pos) /*!< Bit mask of RECEIVE6 field. */ -#define IPC_INTENCLR_RECEIVE6_Disabled (0UL) /*!< Read: Disabled */ -#define IPC_INTENCLR_RECEIVE6_Enabled (1UL) /*!< Read: Enabled */ -#define IPC_INTENCLR_RECEIVE6_Clear (1UL) /*!< Disable */ +#define IPC_INTENCLR_RECEIVE6_Disabled (0x0UL) /*!< Read: Disabled */ +#define IPC_INTENCLR_RECEIVE6_Enabled (0x1UL) /*!< Read: Enabled */ +#define IPC_INTENCLR_RECEIVE6_Clear (0x1UL) /*!< Disable */ /* Bit 5 : Write '1' to disable interrupt for event RECEIVE[5] */ #define IPC_INTENCLR_RECEIVE5_Pos (5UL) /*!< Position of RECEIVE5 field. */ #define IPC_INTENCLR_RECEIVE5_Msk (0x1UL << IPC_INTENCLR_RECEIVE5_Pos) /*!< Bit mask of RECEIVE5 field. */ -#define IPC_INTENCLR_RECEIVE5_Disabled (0UL) /*!< Read: Disabled */ -#define IPC_INTENCLR_RECEIVE5_Enabled (1UL) /*!< Read: Enabled */ -#define IPC_INTENCLR_RECEIVE5_Clear (1UL) /*!< Disable */ +#define IPC_INTENCLR_RECEIVE5_Disabled (0x0UL) /*!< Read: Disabled */ +#define IPC_INTENCLR_RECEIVE5_Enabled (0x1UL) /*!< Read: Enabled */ +#define IPC_INTENCLR_RECEIVE5_Clear (0x1UL) /*!< Disable */ /* Bit 4 : Write '1' to disable interrupt for event RECEIVE[4] */ #define IPC_INTENCLR_RECEIVE4_Pos (4UL) /*!< Position of RECEIVE4 field. */ #define IPC_INTENCLR_RECEIVE4_Msk (0x1UL << IPC_INTENCLR_RECEIVE4_Pos) /*!< Bit mask of RECEIVE4 field. */ -#define IPC_INTENCLR_RECEIVE4_Disabled (0UL) /*!< Read: Disabled */ -#define IPC_INTENCLR_RECEIVE4_Enabled (1UL) /*!< Read: Enabled */ -#define IPC_INTENCLR_RECEIVE4_Clear (1UL) /*!< Disable */ +#define IPC_INTENCLR_RECEIVE4_Disabled (0x0UL) /*!< Read: Disabled */ +#define IPC_INTENCLR_RECEIVE4_Enabled (0x1UL) /*!< Read: Enabled */ +#define IPC_INTENCLR_RECEIVE4_Clear (0x1UL) /*!< Disable */ /* Bit 3 : Write '1' to disable interrupt for event RECEIVE[3] */ #define IPC_INTENCLR_RECEIVE3_Pos (3UL) /*!< Position of RECEIVE3 field. */ #define IPC_INTENCLR_RECEIVE3_Msk (0x1UL << IPC_INTENCLR_RECEIVE3_Pos) /*!< Bit mask of RECEIVE3 field. */ -#define IPC_INTENCLR_RECEIVE3_Disabled (0UL) /*!< Read: Disabled */ -#define IPC_INTENCLR_RECEIVE3_Enabled (1UL) /*!< Read: Enabled */ -#define IPC_INTENCLR_RECEIVE3_Clear (1UL) /*!< Disable */ +#define IPC_INTENCLR_RECEIVE3_Disabled (0x0UL) /*!< Read: Disabled */ +#define IPC_INTENCLR_RECEIVE3_Enabled (0x1UL) /*!< Read: Enabled */ +#define IPC_INTENCLR_RECEIVE3_Clear (0x1UL) /*!< Disable */ /* Bit 2 : Write '1' to disable interrupt for event RECEIVE[2] */ #define IPC_INTENCLR_RECEIVE2_Pos (2UL) /*!< Position of RECEIVE2 field. */ #define IPC_INTENCLR_RECEIVE2_Msk (0x1UL << IPC_INTENCLR_RECEIVE2_Pos) /*!< Bit mask of RECEIVE2 field. */ -#define IPC_INTENCLR_RECEIVE2_Disabled (0UL) /*!< Read: Disabled */ -#define IPC_INTENCLR_RECEIVE2_Enabled (1UL) /*!< Read: Enabled */ -#define IPC_INTENCLR_RECEIVE2_Clear (1UL) /*!< Disable */ +#define IPC_INTENCLR_RECEIVE2_Disabled (0x0UL) /*!< Read: Disabled */ +#define IPC_INTENCLR_RECEIVE2_Enabled (0x1UL) /*!< Read: Enabled */ +#define IPC_INTENCLR_RECEIVE2_Clear (0x1UL) /*!< Disable */ /* Bit 1 : Write '1' to disable interrupt for event RECEIVE[1] */ #define IPC_INTENCLR_RECEIVE1_Pos (1UL) /*!< Position of RECEIVE1 field. */ #define IPC_INTENCLR_RECEIVE1_Msk (0x1UL << IPC_INTENCLR_RECEIVE1_Pos) /*!< Bit mask of RECEIVE1 field. */ -#define IPC_INTENCLR_RECEIVE1_Disabled (0UL) /*!< Read: Disabled */ -#define IPC_INTENCLR_RECEIVE1_Enabled (1UL) /*!< Read: Enabled */ -#define IPC_INTENCLR_RECEIVE1_Clear (1UL) /*!< Disable */ +#define IPC_INTENCLR_RECEIVE1_Disabled (0x0UL) /*!< Read: Disabled */ +#define IPC_INTENCLR_RECEIVE1_Enabled (0x1UL) /*!< Read: Enabled */ +#define IPC_INTENCLR_RECEIVE1_Clear (0x1UL) /*!< Disable */ /* Bit 0 : Write '1' to disable interrupt for event RECEIVE[0] */ #define IPC_INTENCLR_RECEIVE0_Pos (0UL) /*!< Position of RECEIVE0 field. */ #define IPC_INTENCLR_RECEIVE0_Msk (0x1UL << IPC_INTENCLR_RECEIVE0_Pos) /*!< Bit mask of RECEIVE0 field. */ -#define IPC_INTENCLR_RECEIVE0_Disabled (0UL) /*!< Read: Disabled */ -#define IPC_INTENCLR_RECEIVE0_Enabled (1UL) /*!< Read: Enabled */ -#define IPC_INTENCLR_RECEIVE0_Clear (1UL) /*!< Disable */ +#define IPC_INTENCLR_RECEIVE0_Disabled (0x0UL) /*!< Read: Disabled */ +#define IPC_INTENCLR_RECEIVE0_Enabled (0x1UL) /*!< Read: Enabled */ +#define IPC_INTENCLR_RECEIVE0_Clear (0x1UL) /*!< Disable */ /* Register: IPC_INTPEND */ /* Description: Pending interrupts */ @@ -2374,50 +2374,50 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 7 : Read pending status of interrupt for event RECEIVE[7] */ #define IPC_INTPEND_RECEIVE7_Pos (7UL) /*!< Position of RECEIVE7 field. */ #define IPC_INTPEND_RECEIVE7_Msk (0x1UL << IPC_INTPEND_RECEIVE7_Pos) /*!< Bit mask of RECEIVE7 field. */ -#define IPC_INTPEND_RECEIVE7_NotPending (0UL) /*!< Read: Not pending */ -#define IPC_INTPEND_RECEIVE7_Pending (1UL) /*!< Read: Pending */ +#define IPC_INTPEND_RECEIVE7_NotPending (0x0UL) /*!< Read: Not pending */ +#define IPC_INTPEND_RECEIVE7_Pending (0x1UL) /*!< Read: Pending */ /* Bit 6 : Read pending status of interrupt for event RECEIVE[6] */ #define IPC_INTPEND_RECEIVE6_Pos (6UL) /*!< Position of RECEIVE6 field. */ #define IPC_INTPEND_RECEIVE6_Msk (0x1UL << IPC_INTPEND_RECEIVE6_Pos) /*!< Bit mask of RECEIVE6 field. */ -#define IPC_INTPEND_RECEIVE6_NotPending (0UL) /*!< Read: Not pending */ -#define IPC_INTPEND_RECEIVE6_Pending (1UL) /*!< Read: Pending */ +#define IPC_INTPEND_RECEIVE6_NotPending (0x0UL) /*!< Read: Not pending */ +#define IPC_INTPEND_RECEIVE6_Pending (0x1UL) /*!< Read: Pending */ /* Bit 5 : Read pending status of interrupt for event RECEIVE[5] */ #define IPC_INTPEND_RECEIVE5_Pos (5UL) /*!< Position of RECEIVE5 field. */ #define IPC_INTPEND_RECEIVE5_Msk (0x1UL << IPC_INTPEND_RECEIVE5_Pos) /*!< Bit mask of RECEIVE5 field. */ -#define IPC_INTPEND_RECEIVE5_NotPending (0UL) /*!< Read: Not pending */ -#define IPC_INTPEND_RECEIVE5_Pending (1UL) /*!< Read: Pending */ +#define IPC_INTPEND_RECEIVE5_NotPending (0x0UL) /*!< Read: Not pending */ +#define IPC_INTPEND_RECEIVE5_Pending (0x1UL) /*!< Read: Pending */ /* Bit 4 : Read pending status of interrupt for event RECEIVE[4] */ #define IPC_INTPEND_RECEIVE4_Pos (4UL) /*!< Position of RECEIVE4 field. */ #define IPC_INTPEND_RECEIVE4_Msk (0x1UL << IPC_INTPEND_RECEIVE4_Pos) /*!< Bit mask of RECEIVE4 field. */ -#define IPC_INTPEND_RECEIVE4_NotPending (0UL) /*!< Read: Not pending */ -#define IPC_INTPEND_RECEIVE4_Pending (1UL) /*!< Read: Pending */ +#define IPC_INTPEND_RECEIVE4_NotPending (0x0UL) /*!< Read: Not pending */ +#define IPC_INTPEND_RECEIVE4_Pending (0x1UL) /*!< Read: Pending */ /* Bit 3 : Read pending status of interrupt for event RECEIVE[3] */ #define IPC_INTPEND_RECEIVE3_Pos (3UL) /*!< Position of RECEIVE3 field. */ #define IPC_INTPEND_RECEIVE3_Msk (0x1UL << IPC_INTPEND_RECEIVE3_Pos) /*!< Bit mask of RECEIVE3 field. */ -#define IPC_INTPEND_RECEIVE3_NotPending (0UL) /*!< Read: Not pending */ -#define IPC_INTPEND_RECEIVE3_Pending (1UL) /*!< Read: Pending */ +#define IPC_INTPEND_RECEIVE3_NotPending (0x0UL) /*!< Read: Not pending */ +#define IPC_INTPEND_RECEIVE3_Pending (0x1UL) /*!< Read: Pending */ /* Bit 2 : Read pending status of interrupt for event RECEIVE[2] */ #define IPC_INTPEND_RECEIVE2_Pos (2UL) /*!< Position of RECEIVE2 field. */ #define IPC_INTPEND_RECEIVE2_Msk (0x1UL << IPC_INTPEND_RECEIVE2_Pos) /*!< Bit mask of RECEIVE2 field. */ -#define IPC_INTPEND_RECEIVE2_NotPending (0UL) /*!< Read: Not pending */ -#define IPC_INTPEND_RECEIVE2_Pending (1UL) /*!< Read: Pending */ +#define IPC_INTPEND_RECEIVE2_NotPending (0x0UL) /*!< Read: Not pending */ +#define IPC_INTPEND_RECEIVE2_Pending (0x1UL) /*!< Read: Pending */ /* Bit 1 : Read pending status of interrupt for event RECEIVE[1] */ #define IPC_INTPEND_RECEIVE1_Pos (1UL) /*!< Position of RECEIVE1 field. */ #define IPC_INTPEND_RECEIVE1_Msk (0x1UL << IPC_INTPEND_RECEIVE1_Pos) /*!< Bit mask of RECEIVE1 field. */ -#define IPC_INTPEND_RECEIVE1_NotPending (0UL) /*!< Read: Not pending */ -#define IPC_INTPEND_RECEIVE1_Pending (1UL) /*!< Read: Pending */ +#define IPC_INTPEND_RECEIVE1_NotPending (0x0UL) /*!< Read: Not pending */ +#define IPC_INTPEND_RECEIVE1_Pending (0x1UL) /*!< Read: Pending */ /* Bit 0 : Read pending status of interrupt for event RECEIVE[0] */ #define IPC_INTPEND_RECEIVE0_Pos (0UL) /*!< Position of RECEIVE0 field. */ #define IPC_INTPEND_RECEIVE0_Msk (0x1UL << IPC_INTPEND_RECEIVE0_Pos) /*!< Bit mask of RECEIVE0 field. */ -#define IPC_INTPEND_RECEIVE0_NotPending (0UL) /*!< Read: Not pending */ -#define IPC_INTPEND_RECEIVE0_Pending (1UL) /*!< Read: Pending */ +#define IPC_INTPEND_RECEIVE0_NotPending (0x0UL) /*!< Read: Not pending */ +#define IPC_INTPEND_RECEIVE0_Pending (0x1UL) /*!< Read: Pending */ /* Register: IPC_SEND_CNF */ /* Description: Description collection: Send event configuration for TASKS_SEND[n] */ @@ -2425,50 +2425,50 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 7 : Enable broadcasting on IPC channel 7 */ #define IPC_SEND_CNF_CHEN7_Pos (7UL) /*!< Position of CHEN7 field. */ #define IPC_SEND_CNF_CHEN7_Msk (0x1UL << IPC_SEND_CNF_CHEN7_Pos) /*!< Bit mask of CHEN7 field. */ -#define IPC_SEND_CNF_CHEN7_Disable (0UL) /*!< Disable broadcast */ -#define IPC_SEND_CNF_CHEN7_Enable (1UL) /*!< Enable broadcast */ +#define IPC_SEND_CNF_CHEN7_Disable (0x0UL) /*!< Disable broadcast */ +#define IPC_SEND_CNF_CHEN7_Enable (0x1UL) /*!< Enable broadcast */ /* Bit 6 : Enable broadcasting on IPC channel 6 */ #define IPC_SEND_CNF_CHEN6_Pos (6UL) /*!< Position of CHEN6 field. */ #define IPC_SEND_CNF_CHEN6_Msk (0x1UL << IPC_SEND_CNF_CHEN6_Pos) /*!< Bit mask of CHEN6 field. */ -#define IPC_SEND_CNF_CHEN6_Disable (0UL) /*!< Disable broadcast */ -#define IPC_SEND_CNF_CHEN6_Enable (1UL) /*!< Enable broadcast */ +#define IPC_SEND_CNF_CHEN6_Disable (0x0UL) /*!< Disable broadcast */ +#define IPC_SEND_CNF_CHEN6_Enable (0x1UL) /*!< Enable broadcast */ /* Bit 5 : Enable broadcasting on IPC channel 5 */ #define IPC_SEND_CNF_CHEN5_Pos (5UL) /*!< Position of CHEN5 field. */ #define IPC_SEND_CNF_CHEN5_Msk (0x1UL << IPC_SEND_CNF_CHEN5_Pos) /*!< Bit mask of CHEN5 field. */ -#define IPC_SEND_CNF_CHEN5_Disable (0UL) /*!< Disable broadcast */ -#define IPC_SEND_CNF_CHEN5_Enable (1UL) /*!< Enable broadcast */ +#define IPC_SEND_CNF_CHEN5_Disable (0x0UL) /*!< Disable broadcast */ +#define IPC_SEND_CNF_CHEN5_Enable (0x1UL) /*!< Enable broadcast */ /* Bit 4 : Enable broadcasting on IPC channel 4 */ #define IPC_SEND_CNF_CHEN4_Pos (4UL) /*!< Position of CHEN4 field. */ #define IPC_SEND_CNF_CHEN4_Msk (0x1UL << IPC_SEND_CNF_CHEN4_Pos) /*!< Bit mask of CHEN4 field. */ -#define IPC_SEND_CNF_CHEN4_Disable (0UL) /*!< Disable broadcast */ -#define IPC_SEND_CNF_CHEN4_Enable (1UL) /*!< Enable broadcast */ +#define IPC_SEND_CNF_CHEN4_Disable (0x0UL) /*!< Disable broadcast */ +#define IPC_SEND_CNF_CHEN4_Enable (0x1UL) /*!< Enable broadcast */ /* Bit 3 : Enable broadcasting on IPC channel 3 */ #define IPC_SEND_CNF_CHEN3_Pos (3UL) /*!< Position of CHEN3 field. */ #define IPC_SEND_CNF_CHEN3_Msk (0x1UL << IPC_SEND_CNF_CHEN3_Pos) /*!< Bit mask of CHEN3 field. */ -#define IPC_SEND_CNF_CHEN3_Disable (0UL) /*!< Disable broadcast */ -#define IPC_SEND_CNF_CHEN3_Enable (1UL) /*!< Enable broadcast */ +#define IPC_SEND_CNF_CHEN3_Disable (0x0UL) /*!< Disable broadcast */ +#define IPC_SEND_CNF_CHEN3_Enable (0x1UL) /*!< Enable broadcast */ /* Bit 2 : Enable broadcasting on IPC channel 2 */ #define IPC_SEND_CNF_CHEN2_Pos (2UL) /*!< Position of CHEN2 field. */ #define IPC_SEND_CNF_CHEN2_Msk (0x1UL << IPC_SEND_CNF_CHEN2_Pos) /*!< Bit mask of CHEN2 field. */ -#define IPC_SEND_CNF_CHEN2_Disable (0UL) /*!< Disable broadcast */ -#define IPC_SEND_CNF_CHEN2_Enable (1UL) /*!< Enable broadcast */ +#define IPC_SEND_CNF_CHEN2_Disable (0x0UL) /*!< Disable broadcast */ +#define IPC_SEND_CNF_CHEN2_Enable (0x1UL) /*!< Enable broadcast */ /* Bit 1 : Enable broadcasting on IPC channel 1 */ #define IPC_SEND_CNF_CHEN1_Pos (1UL) /*!< Position of CHEN1 field. */ #define IPC_SEND_CNF_CHEN1_Msk (0x1UL << IPC_SEND_CNF_CHEN1_Pos) /*!< Bit mask of CHEN1 field. */ -#define IPC_SEND_CNF_CHEN1_Disable (0UL) /*!< Disable broadcast */ -#define IPC_SEND_CNF_CHEN1_Enable (1UL) /*!< Enable broadcast */ +#define IPC_SEND_CNF_CHEN1_Disable (0x0UL) /*!< Disable broadcast */ +#define IPC_SEND_CNF_CHEN1_Enable (0x1UL) /*!< Enable broadcast */ /* Bit 0 : Enable broadcasting on IPC channel 0 */ #define IPC_SEND_CNF_CHEN0_Pos (0UL) /*!< Position of CHEN0 field. */ #define IPC_SEND_CNF_CHEN0_Msk (0x1UL << IPC_SEND_CNF_CHEN0_Pos) /*!< Bit mask of CHEN0 field. */ -#define IPC_SEND_CNF_CHEN0_Disable (0UL) /*!< Disable broadcast */ -#define IPC_SEND_CNF_CHEN0_Enable (1UL) /*!< Enable broadcast */ +#define IPC_SEND_CNF_CHEN0_Disable (0x0UL) /*!< Disable broadcast */ +#define IPC_SEND_CNF_CHEN0_Enable (0x1UL) /*!< Enable broadcast */ /* Register: IPC_RECEIVE_CNF */ /* Description: Description collection: Receive event configuration for EVENTS_RECEIVE[n] */ @@ -2476,50 +2476,50 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 7 : Enable subscription to IPC channel 7 */ #define IPC_RECEIVE_CNF_CHEN7_Pos (7UL) /*!< Position of CHEN7 field. */ #define IPC_RECEIVE_CNF_CHEN7_Msk (0x1UL << IPC_RECEIVE_CNF_CHEN7_Pos) /*!< Bit mask of CHEN7 field. */ -#define IPC_RECEIVE_CNF_CHEN7_Disable (0UL) /*!< Disable events */ -#define IPC_RECEIVE_CNF_CHEN7_Enable (1UL) /*!< Enable events */ +#define IPC_RECEIVE_CNF_CHEN7_Disable (0x0UL) /*!< Disable events */ +#define IPC_RECEIVE_CNF_CHEN7_Enable (0x1UL) /*!< Enable events */ /* Bit 6 : Enable subscription to IPC channel 6 */ #define IPC_RECEIVE_CNF_CHEN6_Pos (6UL) /*!< Position of CHEN6 field. */ #define IPC_RECEIVE_CNF_CHEN6_Msk (0x1UL << IPC_RECEIVE_CNF_CHEN6_Pos) /*!< Bit mask of CHEN6 field. */ -#define IPC_RECEIVE_CNF_CHEN6_Disable (0UL) /*!< Disable events */ -#define IPC_RECEIVE_CNF_CHEN6_Enable (1UL) /*!< Enable events */ +#define IPC_RECEIVE_CNF_CHEN6_Disable (0x0UL) /*!< Disable events */ +#define IPC_RECEIVE_CNF_CHEN6_Enable (0x1UL) /*!< Enable events */ /* Bit 5 : Enable subscription to IPC channel 5 */ #define IPC_RECEIVE_CNF_CHEN5_Pos (5UL) /*!< Position of CHEN5 field. */ #define IPC_RECEIVE_CNF_CHEN5_Msk (0x1UL << IPC_RECEIVE_CNF_CHEN5_Pos) /*!< Bit mask of CHEN5 field. */ -#define IPC_RECEIVE_CNF_CHEN5_Disable (0UL) /*!< Disable events */ -#define IPC_RECEIVE_CNF_CHEN5_Enable (1UL) /*!< Enable events */ +#define IPC_RECEIVE_CNF_CHEN5_Disable (0x0UL) /*!< Disable events */ +#define IPC_RECEIVE_CNF_CHEN5_Enable (0x1UL) /*!< Enable events */ /* Bit 4 : Enable subscription to IPC channel 4 */ #define IPC_RECEIVE_CNF_CHEN4_Pos (4UL) /*!< Position of CHEN4 field. */ #define IPC_RECEIVE_CNF_CHEN4_Msk (0x1UL << IPC_RECEIVE_CNF_CHEN4_Pos) /*!< Bit mask of CHEN4 field. */ -#define IPC_RECEIVE_CNF_CHEN4_Disable (0UL) /*!< Disable events */ -#define IPC_RECEIVE_CNF_CHEN4_Enable (1UL) /*!< Enable events */ +#define IPC_RECEIVE_CNF_CHEN4_Disable (0x0UL) /*!< Disable events */ +#define IPC_RECEIVE_CNF_CHEN4_Enable (0x1UL) /*!< Enable events */ /* Bit 3 : Enable subscription to IPC channel 3 */ #define IPC_RECEIVE_CNF_CHEN3_Pos (3UL) /*!< Position of CHEN3 field. */ #define IPC_RECEIVE_CNF_CHEN3_Msk (0x1UL << IPC_RECEIVE_CNF_CHEN3_Pos) /*!< Bit mask of CHEN3 field. */ -#define IPC_RECEIVE_CNF_CHEN3_Disable (0UL) /*!< Disable events */ -#define IPC_RECEIVE_CNF_CHEN3_Enable (1UL) /*!< Enable events */ +#define IPC_RECEIVE_CNF_CHEN3_Disable (0x0UL) /*!< Disable events */ +#define IPC_RECEIVE_CNF_CHEN3_Enable (0x1UL) /*!< Enable events */ /* Bit 2 : Enable subscription to IPC channel 2 */ #define IPC_RECEIVE_CNF_CHEN2_Pos (2UL) /*!< Position of CHEN2 field. */ #define IPC_RECEIVE_CNF_CHEN2_Msk (0x1UL << IPC_RECEIVE_CNF_CHEN2_Pos) /*!< Bit mask of CHEN2 field. */ -#define IPC_RECEIVE_CNF_CHEN2_Disable (0UL) /*!< Disable events */ -#define IPC_RECEIVE_CNF_CHEN2_Enable (1UL) /*!< Enable events */ +#define IPC_RECEIVE_CNF_CHEN2_Disable (0x0UL) /*!< Disable events */ +#define IPC_RECEIVE_CNF_CHEN2_Enable (0x1UL) /*!< Enable events */ /* Bit 1 : Enable subscription to IPC channel 1 */ #define IPC_RECEIVE_CNF_CHEN1_Pos (1UL) /*!< Position of CHEN1 field. */ #define IPC_RECEIVE_CNF_CHEN1_Msk (0x1UL << IPC_RECEIVE_CNF_CHEN1_Pos) /*!< Bit mask of CHEN1 field. */ -#define IPC_RECEIVE_CNF_CHEN1_Disable (0UL) /*!< Disable events */ -#define IPC_RECEIVE_CNF_CHEN1_Enable (1UL) /*!< Enable events */ +#define IPC_RECEIVE_CNF_CHEN1_Disable (0x0UL) /*!< Disable events */ +#define IPC_RECEIVE_CNF_CHEN1_Enable (0x1UL) /*!< Enable events */ /* Bit 0 : Enable subscription to IPC channel 0 */ #define IPC_RECEIVE_CNF_CHEN0_Pos (0UL) /*!< Position of CHEN0 field. */ #define IPC_RECEIVE_CNF_CHEN0_Msk (0x1UL << IPC_RECEIVE_CNF_CHEN0_Pos) /*!< Bit mask of CHEN0 field. */ -#define IPC_RECEIVE_CNF_CHEN0_Disable (0UL) /*!< Disable events */ -#define IPC_RECEIVE_CNF_CHEN0_Enable (1UL) /*!< Enable events */ +#define IPC_RECEIVE_CNF_CHEN0_Disable (0x0UL) /*!< Disable events */ +#define IPC_RECEIVE_CNF_CHEN0_Enable (0x1UL) /*!< Enable events */ /* Register: IPC_GPMEM */ /* Description: Description collection: General purpose memory */ @@ -2538,7 +2538,7 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 0 : Push a key slot over secure APB */ #define KMU_TASKS_PUSH_KEYSLOT_TASKS_PUSH_KEYSLOT_Pos (0UL) /*!< Position of TASKS_PUSH_KEYSLOT field. */ #define KMU_TASKS_PUSH_KEYSLOT_TASKS_PUSH_KEYSLOT_Msk (0x1UL << KMU_TASKS_PUSH_KEYSLOT_TASKS_PUSH_KEYSLOT_Pos) /*!< Bit mask of TASKS_PUSH_KEYSLOT field. */ -#define KMU_TASKS_PUSH_KEYSLOT_TASKS_PUSH_KEYSLOT_Trigger (1UL) /*!< Trigger task */ +#define KMU_TASKS_PUSH_KEYSLOT_TASKS_PUSH_KEYSLOT_Trigger (0x1UL) /*!< Trigger task */ /* Register: KMU_EVENTS_KEYSLOT_PUSHED */ /* Description: Key slot successfully pushed over secure APB */ @@ -2546,8 +2546,8 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 0 : Key slot successfully pushed over secure APB */ #define KMU_EVENTS_KEYSLOT_PUSHED_EVENTS_KEYSLOT_PUSHED_Pos (0UL) /*!< Position of EVENTS_KEYSLOT_PUSHED field. */ #define KMU_EVENTS_KEYSLOT_PUSHED_EVENTS_KEYSLOT_PUSHED_Msk (0x1UL << KMU_EVENTS_KEYSLOT_PUSHED_EVENTS_KEYSLOT_PUSHED_Pos) /*!< Bit mask of EVENTS_KEYSLOT_PUSHED field. */ -#define KMU_EVENTS_KEYSLOT_PUSHED_EVENTS_KEYSLOT_PUSHED_NotGenerated (0UL) /*!< Event not generated */ -#define KMU_EVENTS_KEYSLOT_PUSHED_EVENTS_KEYSLOT_PUSHED_Generated (1UL) /*!< Event generated */ +#define KMU_EVENTS_KEYSLOT_PUSHED_EVENTS_KEYSLOT_PUSHED_NotGenerated (0x0UL) /*!< Event not generated */ +#define KMU_EVENTS_KEYSLOT_PUSHED_EVENTS_KEYSLOT_PUSHED_Generated (0x1UL) /*!< Event generated */ /* Register: KMU_EVENTS_KEYSLOT_REVOKED */ /* Description: Key slot has been revoked and cannot be tasked for selection */ @@ -2555,8 +2555,8 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 0 : Key slot has been revoked and cannot be tasked for selection */ #define KMU_EVENTS_KEYSLOT_REVOKED_EVENTS_KEYSLOT_REVOKED_Pos (0UL) /*!< Position of EVENTS_KEYSLOT_REVOKED field. */ #define KMU_EVENTS_KEYSLOT_REVOKED_EVENTS_KEYSLOT_REVOKED_Msk (0x1UL << KMU_EVENTS_KEYSLOT_REVOKED_EVENTS_KEYSLOT_REVOKED_Pos) /*!< Bit mask of EVENTS_KEYSLOT_REVOKED field. */ -#define KMU_EVENTS_KEYSLOT_REVOKED_EVENTS_KEYSLOT_REVOKED_NotGenerated (0UL) /*!< Event not generated */ -#define KMU_EVENTS_KEYSLOT_REVOKED_EVENTS_KEYSLOT_REVOKED_Generated (1UL) /*!< Event generated */ +#define KMU_EVENTS_KEYSLOT_REVOKED_EVENTS_KEYSLOT_REVOKED_NotGenerated (0x0UL) /*!< Event not generated */ +#define KMU_EVENTS_KEYSLOT_REVOKED_EVENTS_KEYSLOT_REVOKED_Generated (0x1UL) /*!< Event generated */ /* Register: KMU_EVENTS_KEYSLOT_ERROR */ /* Description: No key slot selected, no destination address defined, or error during push operation */ @@ -2564,8 +2564,8 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 0 : No key slot selected, no destination address defined, or error during push operation */ #define KMU_EVENTS_KEYSLOT_ERROR_EVENTS_KEYSLOT_ERROR_Pos (0UL) /*!< Position of EVENTS_KEYSLOT_ERROR field. */ #define KMU_EVENTS_KEYSLOT_ERROR_EVENTS_KEYSLOT_ERROR_Msk (0x1UL << KMU_EVENTS_KEYSLOT_ERROR_EVENTS_KEYSLOT_ERROR_Pos) /*!< Bit mask of EVENTS_KEYSLOT_ERROR field. */ -#define KMU_EVENTS_KEYSLOT_ERROR_EVENTS_KEYSLOT_ERROR_NotGenerated (0UL) /*!< Event not generated */ -#define KMU_EVENTS_KEYSLOT_ERROR_EVENTS_KEYSLOT_ERROR_Generated (1UL) /*!< Event generated */ +#define KMU_EVENTS_KEYSLOT_ERROR_EVENTS_KEYSLOT_ERROR_NotGenerated (0x0UL) /*!< Event not generated */ +#define KMU_EVENTS_KEYSLOT_ERROR_EVENTS_KEYSLOT_ERROR_Generated (0x1UL) /*!< Event generated */ /* Register: KMU_INTEN */ /* Description: Enable or disable interrupt */ @@ -2573,20 +2573,20 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 2 : Enable or disable interrupt for event KEYSLOT_ERROR */ #define KMU_INTEN_KEYSLOT_ERROR_Pos (2UL) /*!< Position of KEYSLOT_ERROR field. */ #define KMU_INTEN_KEYSLOT_ERROR_Msk (0x1UL << KMU_INTEN_KEYSLOT_ERROR_Pos) /*!< Bit mask of KEYSLOT_ERROR field. */ -#define KMU_INTEN_KEYSLOT_ERROR_Disabled (0UL) /*!< Disable */ -#define KMU_INTEN_KEYSLOT_ERROR_Enabled (1UL) /*!< Enable */ +#define KMU_INTEN_KEYSLOT_ERROR_Disabled (0x0UL) /*!< Disable */ +#define KMU_INTEN_KEYSLOT_ERROR_Enabled (0x1UL) /*!< Enable */ /* Bit 1 : Enable or disable interrupt for event KEYSLOT_REVOKED */ #define KMU_INTEN_KEYSLOT_REVOKED_Pos (1UL) /*!< Position of KEYSLOT_REVOKED field. */ #define KMU_INTEN_KEYSLOT_REVOKED_Msk (0x1UL << KMU_INTEN_KEYSLOT_REVOKED_Pos) /*!< Bit mask of KEYSLOT_REVOKED field. */ -#define KMU_INTEN_KEYSLOT_REVOKED_Disabled (0UL) /*!< Disable */ -#define KMU_INTEN_KEYSLOT_REVOKED_Enabled (1UL) /*!< Enable */ +#define KMU_INTEN_KEYSLOT_REVOKED_Disabled (0x0UL) /*!< Disable */ +#define KMU_INTEN_KEYSLOT_REVOKED_Enabled (0x1UL) /*!< Enable */ /* Bit 0 : Enable or disable interrupt for event KEYSLOT_PUSHED */ #define KMU_INTEN_KEYSLOT_PUSHED_Pos (0UL) /*!< Position of KEYSLOT_PUSHED field. */ #define KMU_INTEN_KEYSLOT_PUSHED_Msk (0x1UL << KMU_INTEN_KEYSLOT_PUSHED_Pos) /*!< Bit mask of KEYSLOT_PUSHED field. */ -#define KMU_INTEN_KEYSLOT_PUSHED_Disabled (0UL) /*!< Disable */ -#define KMU_INTEN_KEYSLOT_PUSHED_Enabled (1UL) /*!< Enable */ +#define KMU_INTEN_KEYSLOT_PUSHED_Disabled (0x0UL) /*!< Disable */ +#define KMU_INTEN_KEYSLOT_PUSHED_Enabled (0x1UL) /*!< Enable */ /* Register: KMU_INTENSET */ /* Description: Enable interrupt */ @@ -2594,23 +2594,23 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 2 : Write '1' to enable interrupt for event KEYSLOT_ERROR */ #define KMU_INTENSET_KEYSLOT_ERROR_Pos (2UL) /*!< Position of KEYSLOT_ERROR field. */ #define KMU_INTENSET_KEYSLOT_ERROR_Msk (0x1UL << KMU_INTENSET_KEYSLOT_ERROR_Pos) /*!< Bit mask of KEYSLOT_ERROR field. */ -#define KMU_INTENSET_KEYSLOT_ERROR_Disabled (0UL) /*!< Read: Disabled */ -#define KMU_INTENSET_KEYSLOT_ERROR_Enabled (1UL) /*!< Read: Enabled */ -#define KMU_INTENSET_KEYSLOT_ERROR_Set (1UL) /*!< Enable */ +#define KMU_INTENSET_KEYSLOT_ERROR_Disabled (0x0UL) /*!< Read: Disabled */ +#define KMU_INTENSET_KEYSLOT_ERROR_Enabled (0x1UL) /*!< Read: Enabled */ +#define KMU_INTENSET_KEYSLOT_ERROR_Set (0x1UL) /*!< Enable */ /* Bit 1 : Write '1' to enable interrupt for event KEYSLOT_REVOKED */ #define KMU_INTENSET_KEYSLOT_REVOKED_Pos (1UL) /*!< Position of KEYSLOT_REVOKED field. */ #define KMU_INTENSET_KEYSLOT_REVOKED_Msk (0x1UL << KMU_INTENSET_KEYSLOT_REVOKED_Pos) /*!< Bit mask of KEYSLOT_REVOKED field. */ -#define KMU_INTENSET_KEYSLOT_REVOKED_Disabled (0UL) /*!< Read: Disabled */ -#define KMU_INTENSET_KEYSLOT_REVOKED_Enabled (1UL) /*!< Read: Enabled */ -#define KMU_INTENSET_KEYSLOT_REVOKED_Set (1UL) /*!< Enable */ +#define KMU_INTENSET_KEYSLOT_REVOKED_Disabled (0x0UL) /*!< Read: Disabled */ +#define KMU_INTENSET_KEYSLOT_REVOKED_Enabled (0x1UL) /*!< Read: Enabled */ +#define KMU_INTENSET_KEYSLOT_REVOKED_Set (0x1UL) /*!< Enable */ /* Bit 0 : Write '1' to enable interrupt for event KEYSLOT_PUSHED */ #define KMU_INTENSET_KEYSLOT_PUSHED_Pos (0UL) /*!< Position of KEYSLOT_PUSHED field. */ #define KMU_INTENSET_KEYSLOT_PUSHED_Msk (0x1UL << KMU_INTENSET_KEYSLOT_PUSHED_Pos) /*!< Bit mask of KEYSLOT_PUSHED field. */ -#define KMU_INTENSET_KEYSLOT_PUSHED_Disabled (0UL) /*!< Read: Disabled */ -#define KMU_INTENSET_KEYSLOT_PUSHED_Enabled (1UL) /*!< Read: Enabled */ -#define KMU_INTENSET_KEYSLOT_PUSHED_Set (1UL) /*!< Enable */ +#define KMU_INTENSET_KEYSLOT_PUSHED_Disabled (0x0UL) /*!< Read: Disabled */ +#define KMU_INTENSET_KEYSLOT_PUSHED_Enabled (0x1UL) /*!< Read: Enabled */ +#define KMU_INTENSET_KEYSLOT_PUSHED_Set (0x1UL) /*!< Enable */ /* Register: KMU_INTENCLR */ /* Description: Disable interrupt */ @@ -2618,23 +2618,23 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 2 : Write '1' to disable interrupt for event KEYSLOT_ERROR */ #define KMU_INTENCLR_KEYSLOT_ERROR_Pos (2UL) /*!< Position of KEYSLOT_ERROR field. */ #define KMU_INTENCLR_KEYSLOT_ERROR_Msk (0x1UL << KMU_INTENCLR_KEYSLOT_ERROR_Pos) /*!< Bit mask of KEYSLOT_ERROR field. */ -#define KMU_INTENCLR_KEYSLOT_ERROR_Disabled (0UL) /*!< Read: Disabled */ -#define KMU_INTENCLR_KEYSLOT_ERROR_Enabled (1UL) /*!< Read: Enabled */ -#define KMU_INTENCLR_KEYSLOT_ERROR_Clear (1UL) /*!< Disable */ +#define KMU_INTENCLR_KEYSLOT_ERROR_Disabled (0x0UL) /*!< Read: Disabled */ +#define KMU_INTENCLR_KEYSLOT_ERROR_Enabled (0x1UL) /*!< Read: Enabled */ +#define KMU_INTENCLR_KEYSLOT_ERROR_Clear (0x1UL) /*!< Disable */ /* Bit 1 : Write '1' to disable interrupt for event KEYSLOT_REVOKED */ #define KMU_INTENCLR_KEYSLOT_REVOKED_Pos (1UL) /*!< Position of KEYSLOT_REVOKED field. */ #define KMU_INTENCLR_KEYSLOT_REVOKED_Msk (0x1UL << KMU_INTENCLR_KEYSLOT_REVOKED_Pos) /*!< Bit mask of KEYSLOT_REVOKED field. */ -#define KMU_INTENCLR_KEYSLOT_REVOKED_Disabled (0UL) /*!< Read: Disabled */ -#define KMU_INTENCLR_KEYSLOT_REVOKED_Enabled (1UL) /*!< Read: Enabled */ -#define KMU_INTENCLR_KEYSLOT_REVOKED_Clear (1UL) /*!< Disable */ +#define KMU_INTENCLR_KEYSLOT_REVOKED_Disabled (0x0UL) /*!< Read: Disabled */ +#define KMU_INTENCLR_KEYSLOT_REVOKED_Enabled (0x1UL) /*!< Read: Enabled */ +#define KMU_INTENCLR_KEYSLOT_REVOKED_Clear (0x1UL) /*!< Disable */ /* Bit 0 : Write '1' to disable interrupt for event KEYSLOT_PUSHED */ #define KMU_INTENCLR_KEYSLOT_PUSHED_Pos (0UL) /*!< Position of KEYSLOT_PUSHED field. */ #define KMU_INTENCLR_KEYSLOT_PUSHED_Msk (0x1UL << KMU_INTENCLR_KEYSLOT_PUSHED_Pos) /*!< Bit mask of KEYSLOT_PUSHED field. */ -#define KMU_INTENCLR_KEYSLOT_PUSHED_Disabled (0UL) /*!< Read: Disabled */ -#define KMU_INTENCLR_KEYSLOT_PUSHED_Enabled (1UL) /*!< Read: Enabled */ -#define KMU_INTENCLR_KEYSLOT_PUSHED_Clear (1UL) /*!< Disable */ +#define KMU_INTENCLR_KEYSLOT_PUSHED_Disabled (0x0UL) /*!< Read: Disabled */ +#define KMU_INTENCLR_KEYSLOT_PUSHED_Enabled (0x1UL) /*!< Read: Enabled */ +#define KMU_INTENCLR_KEYSLOT_PUSHED_Clear (0x1UL) /*!< Disable */ /* Register: KMU_INTPEND */ /* Description: Pending interrupts */ @@ -2642,20 +2642,20 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 2 : Read pending status of interrupt for event KEYSLOT_ERROR */ #define KMU_INTPEND_KEYSLOT_ERROR_Pos (2UL) /*!< Position of KEYSLOT_ERROR field. */ #define KMU_INTPEND_KEYSLOT_ERROR_Msk (0x1UL << KMU_INTPEND_KEYSLOT_ERROR_Pos) /*!< Bit mask of KEYSLOT_ERROR field. */ -#define KMU_INTPEND_KEYSLOT_ERROR_NotPending (0UL) /*!< Read: Not pending */ -#define KMU_INTPEND_KEYSLOT_ERROR_Pending (1UL) /*!< Read: Pending */ +#define KMU_INTPEND_KEYSLOT_ERROR_NotPending (0x0UL) /*!< Read: Not pending */ +#define KMU_INTPEND_KEYSLOT_ERROR_Pending (0x1UL) /*!< Read: Pending */ /* Bit 1 : Read pending status of interrupt for event KEYSLOT_REVOKED */ #define KMU_INTPEND_KEYSLOT_REVOKED_Pos (1UL) /*!< Position of KEYSLOT_REVOKED field. */ #define KMU_INTPEND_KEYSLOT_REVOKED_Msk (0x1UL << KMU_INTPEND_KEYSLOT_REVOKED_Pos) /*!< Bit mask of KEYSLOT_REVOKED field. */ -#define KMU_INTPEND_KEYSLOT_REVOKED_NotPending (0UL) /*!< Read: Not pending */ -#define KMU_INTPEND_KEYSLOT_REVOKED_Pending (1UL) /*!< Read: Pending */ +#define KMU_INTPEND_KEYSLOT_REVOKED_NotPending (0x0UL) /*!< Read: Not pending */ +#define KMU_INTPEND_KEYSLOT_REVOKED_Pending (0x1UL) /*!< Read: Pending */ /* Bit 0 : Read pending status of interrupt for event KEYSLOT_PUSHED */ #define KMU_INTPEND_KEYSLOT_PUSHED_Pos (0UL) /*!< Position of KEYSLOT_PUSHED field. */ #define KMU_INTPEND_KEYSLOT_PUSHED_Msk (0x1UL << KMU_INTPEND_KEYSLOT_PUSHED_Pos) /*!< Bit mask of KEYSLOT_PUSHED field. */ -#define KMU_INTPEND_KEYSLOT_PUSHED_NotPending (0UL) /*!< Read: Not pending */ -#define KMU_INTPEND_KEYSLOT_PUSHED_Pending (1UL) /*!< Read: Pending */ +#define KMU_INTPEND_KEYSLOT_PUSHED_NotPending (0x0UL) /*!< Read: Not pending */ +#define KMU_INTPEND_KEYSLOT_PUSHED_Pending (0x1UL) /*!< Read: Pending */ /* Register: KMU_STATUS */ /* Description: Status bits for KMU operation */ @@ -2663,14 +2663,14 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 1 : Violation status */ #define KMU_STATUS_BLOCKED_Pos (1UL) /*!< Position of BLOCKED field. */ #define KMU_STATUS_BLOCKED_Msk (0x1UL << KMU_STATUS_BLOCKED_Pos) /*!< Bit mask of BLOCKED field. */ -#define KMU_STATUS_BLOCKED_Disabled (0UL) /*!< No access violation detected */ -#define KMU_STATUS_BLOCKED_Enabled (1UL) /*!< Access violation detected and blocked */ +#define KMU_STATUS_BLOCKED_Disabled (0x0UL) /*!< No access violation detected */ +#define KMU_STATUS_BLOCKED_Enabled (0x1UL) /*!< Access violation detected and blocked */ /* Bit 0 : Key slot ID successfully selected by the KMU */ #define KMU_STATUS_SELECTED_Pos (0UL) /*!< Position of SELECTED field. */ #define KMU_STATUS_SELECTED_Msk (0x1UL << KMU_STATUS_SELECTED_Pos) /*!< Bit mask of SELECTED field. */ -#define KMU_STATUS_SELECTED_Disabled (0UL) /*!< No key slot ID selected by KMU */ -#define KMU_STATUS_SELECTED_Enabled (1UL) /*!< Key slot ID successfully selected by KMU */ +#define KMU_STATUS_SELECTED_Disabled (0x0UL) /*!< No key slot ID selected by KMU */ +#define KMU_STATUS_SELECTED_Enabled (0x1UL) /*!< Key slot ID successfully selected by KMU */ /* Register: KMU_SELECTKEYSLOT */ /* Description: Select key slot to be read over AHB or pushed over secure APB when TASKS_PUSH_KEYSLOT is started */ @@ -2689,8 +2689,8 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 0 : NVMC is ready or busy */ #define NVMC_READY_READY_Pos (0UL) /*!< Position of READY field. */ #define NVMC_READY_READY_Msk (0x1UL << NVMC_READY_READY_Pos) /*!< Bit mask of READY field. */ -#define NVMC_READY_READY_Busy (0UL) /*!< NVMC is busy (on-going write or erase operation) */ -#define NVMC_READY_READY_Ready (1UL) /*!< NVMC is ready */ +#define NVMC_READY_READY_Busy (0x0UL) /*!< NVMC is busy (on-going write or erase operation) */ +#define NVMC_READY_READY_Ready (0x1UL) /*!< NVMC is ready */ /* Register: NVMC_READYNEXT */ /* Description: Ready flag */ @@ -2698,8 +2698,8 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 0 : NVMC can accept a new write operation */ #define NVMC_READYNEXT_READYNEXT_Pos (0UL) /*!< Position of READYNEXT field. */ #define NVMC_READYNEXT_READYNEXT_Msk (0x1UL << NVMC_READYNEXT_READYNEXT_Pos) /*!< Bit mask of READYNEXT field. */ -#define NVMC_READYNEXT_READYNEXT_Busy (0UL) /*!< NVMC cannot accept any write operation */ -#define NVMC_READYNEXT_READYNEXT_Ready (1UL) /*!< NVMC is ready */ +#define NVMC_READYNEXT_READYNEXT_Busy (0x0UL) /*!< NVMC cannot accept any write operation */ +#define NVMC_READYNEXT_READYNEXT_Ready (0x1UL) /*!< NVMC is ready */ /* Register: NVMC_CONFIG */ /* Description: Configuration register */ @@ -2707,10 +2707,10 @@ POSSIBILITY OF SUCH DAMAGE. /* Bits 2..0 : Program memory access mode. It is strongly recommended to only activate erase and write modes when they are actively used. Enabling write or erase will invalidate the cache and keep it invalidated. */ #define NVMC_CONFIG_WEN_Pos (0UL) /*!< Position of WEN field. */ #define NVMC_CONFIG_WEN_Msk (0x7UL << NVMC_CONFIG_WEN_Pos) /*!< Bit mask of WEN field. */ -#define NVMC_CONFIG_WEN_Ren (0UL) /*!< Read only access */ -#define NVMC_CONFIG_WEN_Wen (1UL) /*!< Write enabled */ -#define NVMC_CONFIG_WEN_Een (2UL) /*!< Erase enabled */ -#define NVMC_CONFIG_WEN_PEen (4UL) /*!< Partial erase enabled */ +#define NVMC_CONFIG_WEN_Ren (0x0UL) /*!< Read only access */ +#define NVMC_CONFIG_WEN_Wen (0x1UL) /*!< Write enabled */ +#define NVMC_CONFIG_WEN_Een (0x2UL) /*!< Erase enabled */ +#define NVMC_CONFIG_WEN_PEen (0x4UL) /*!< Partial erase enabled */ /* Register: NVMC_ERASEALL */ /* Description: Register for erasing all non-volatile user memory */ @@ -2718,8 +2718,8 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 0 : Erase all non-volatile memory including UICR registers. Note that erasing must be enabled by setting CONFIG.WEN = Een before the non-volatile memory can be erased. */ #define NVMC_ERASEALL_ERASEALL_Pos (0UL) /*!< Position of ERASEALL field. */ #define NVMC_ERASEALL_ERASEALL_Msk (0x1UL << NVMC_ERASEALL_ERASEALL_Pos) /*!< Bit mask of ERASEALL field. */ -#define NVMC_ERASEALL_ERASEALL_NoOperation (0UL) /*!< No operation */ -#define NVMC_ERASEALL_ERASEALL_Erase (1UL) /*!< Start chip erase */ +#define NVMC_ERASEALL_ERASEALL_NoOperation (0x0UL) /*!< No operation */ +#define NVMC_ERASEALL_ERASEALL_Erase (0x1UL) /*!< Start chip erase */ /* Register: NVMC_ERASEPAGEPARTIALCFG */ /* Description: Register for partial erase configuration */ @@ -2734,14 +2734,14 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 8 : Cache profiling enable */ #define NVMC_ICACHECNF_CACHEPROFEN_Pos (8UL) /*!< Position of CACHEPROFEN field. */ #define NVMC_ICACHECNF_CACHEPROFEN_Msk (0x1UL << NVMC_ICACHECNF_CACHEPROFEN_Pos) /*!< Bit mask of CACHEPROFEN field. */ -#define NVMC_ICACHECNF_CACHEPROFEN_Disabled (0UL) /*!< Disable cache profiling */ -#define NVMC_ICACHECNF_CACHEPROFEN_Enabled (1UL) /*!< Enable cache profiling */ +#define NVMC_ICACHECNF_CACHEPROFEN_Disabled (0x0UL) /*!< Disable cache profiling */ +#define NVMC_ICACHECNF_CACHEPROFEN_Enabled (0x1UL) /*!< Enable cache profiling */ /* Bit 0 : Cache enable */ #define NVMC_ICACHECNF_CACHEEN_Pos (0UL) /*!< Position of CACHEEN field. */ #define NVMC_ICACHECNF_CACHEEN_Msk (0x1UL << NVMC_ICACHECNF_CACHEEN_Pos) /*!< Bit mask of CACHEEN field. */ -#define NVMC_ICACHECNF_CACHEEN_Disabled (0UL) /*!< Disable cache. Invalidates all cache entries. */ -#define NVMC_ICACHECNF_CACHEEN_Enabled (1UL) /*!< Enable cache */ +#define NVMC_ICACHECNF_CACHEEN_Disabled (0x0UL) /*!< Disable cache. Invalidates all cache entries. */ +#define NVMC_ICACHECNF_CACHEEN_Enabled (0x1UL) /*!< Enable cache */ /* Register: NVMC_IHIT */ /* Description: I-code cache hit counter */ @@ -2763,9 +2763,9 @@ POSSIBILITY OF SUCH DAMAGE. /* Bits 1..0 : Program memory access mode. It is strongly recommended to only activate erase and write modes when they are actively used. Enabling write or erase will invalidate the cache and keep it invalidated. */ #define NVMC_CONFIGNS_WEN_Pos (0UL) /*!< Position of WEN field. */ #define NVMC_CONFIGNS_WEN_Msk (0x3UL << NVMC_CONFIGNS_WEN_Pos) /*!< Bit mask of WEN field. */ -#define NVMC_CONFIGNS_WEN_Ren (0UL) /*!< Read only access */ -#define NVMC_CONFIGNS_WEN_Wen (1UL) /*!< Write enabled */ -#define NVMC_CONFIGNS_WEN_Een (2UL) /*!< Erase enabled */ +#define NVMC_CONFIGNS_WEN_Ren (0x0UL) /*!< Read only access */ +#define NVMC_CONFIGNS_WEN_Wen (0x1UL) /*!< Write enabled */ +#define NVMC_CONFIGNS_WEN_Een (0x2UL) /*!< Erase enabled */ /* Register: NVMC_WRITEUICRNS */ /* Description: Non-secure APPROTECT enable register */ @@ -2778,7 +2778,7 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 0 : Allow non-secure code to set APPROTECT */ #define NVMC_WRITEUICRNS_SET_Pos (0UL) /*!< Position of SET field. */ #define NVMC_WRITEUICRNS_SET_Msk (0x1UL << NVMC_WRITEUICRNS_SET_Pos) /*!< Bit mask of SET field. */ -#define NVMC_WRITEUICRNS_SET_Set (1UL) /*!< Set value */ +#define NVMC_WRITEUICRNS_SET_Set (0x1UL) /*!< Set value */ /* Peripheral: GPIO */ @@ -2790,194 +2790,194 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 31 : Pin 31 */ #define GPIO_OUT_PIN31_Pos (31UL) /*!< Position of PIN31 field. */ #define GPIO_OUT_PIN31_Msk (0x1UL << GPIO_OUT_PIN31_Pos) /*!< Bit mask of PIN31 field. */ -#define GPIO_OUT_PIN31_Low (0UL) /*!< Pin driver is low */ -#define GPIO_OUT_PIN31_High (1UL) /*!< Pin driver is high */ +#define GPIO_OUT_PIN31_Low (0x0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN31_High (0x1UL) /*!< Pin driver is high */ /* Bit 30 : Pin 30 */ #define GPIO_OUT_PIN30_Pos (30UL) /*!< Position of PIN30 field. */ #define GPIO_OUT_PIN30_Msk (0x1UL << GPIO_OUT_PIN30_Pos) /*!< Bit mask of PIN30 field. */ -#define GPIO_OUT_PIN30_Low (0UL) /*!< Pin driver is low */ -#define GPIO_OUT_PIN30_High (1UL) /*!< Pin driver is high */ +#define GPIO_OUT_PIN30_Low (0x0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN30_High (0x1UL) /*!< Pin driver is high */ /* Bit 29 : Pin 29 */ #define GPIO_OUT_PIN29_Pos (29UL) /*!< Position of PIN29 field. */ #define GPIO_OUT_PIN29_Msk (0x1UL << GPIO_OUT_PIN29_Pos) /*!< Bit mask of PIN29 field. */ -#define GPIO_OUT_PIN29_Low (0UL) /*!< Pin driver is low */ -#define GPIO_OUT_PIN29_High (1UL) /*!< Pin driver is high */ +#define GPIO_OUT_PIN29_Low (0x0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN29_High (0x1UL) /*!< Pin driver is high */ /* Bit 28 : Pin 28 */ #define GPIO_OUT_PIN28_Pos (28UL) /*!< Position of PIN28 field. */ #define GPIO_OUT_PIN28_Msk (0x1UL << GPIO_OUT_PIN28_Pos) /*!< Bit mask of PIN28 field. */ -#define GPIO_OUT_PIN28_Low (0UL) /*!< Pin driver is low */ -#define GPIO_OUT_PIN28_High (1UL) /*!< Pin driver is high */ +#define GPIO_OUT_PIN28_Low (0x0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN28_High (0x1UL) /*!< Pin driver is high */ /* Bit 27 : Pin 27 */ #define GPIO_OUT_PIN27_Pos (27UL) /*!< Position of PIN27 field. */ #define GPIO_OUT_PIN27_Msk (0x1UL << GPIO_OUT_PIN27_Pos) /*!< Bit mask of PIN27 field. */ -#define GPIO_OUT_PIN27_Low (0UL) /*!< Pin driver is low */ -#define GPIO_OUT_PIN27_High (1UL) /*!< Pin driver is high */ +#define GPIO_OUT_PIN27_Low (0x0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN27_High (0x1UL) /*!< Pin driver is high */ /* Bit 26 : Pin 26 */ #define GPIO_OUT_PIN26_Pos (26UL) /*!< Position of PIN26 field. */ #define GPIO_OUT_PIN26_Msk (0x1UL << GPIO_OUT_PIN26_Pos) /*!< Bit mask of PIN26 field. */ -#define GPIO_OUT_PIN26_Low (0UL) /*!< Pin driver is low */ -#define GPIO_OUT_PIN26_High (1UL) /*!< Pin driver is high */ +#define GPIO_OUT_PIN26_Low (0x0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN26_High (0x1UL) /*!< Pin driver is high */ /* Bit 25 : Pin 25 */ #define GPIO_OUT_PIN25_Pos (25UL) /*!< Position of PIN25 field. */ #define GPIO_OUT_PIN25_Msk (0x1UL << GPIO_OUT_PIN25_Pos) /*!< Bit mask of PIN25 field. */ -#define GPIO_OUT_PIN25_Low (0UL) /*!< Pin driver is low */ -#define GPIO_OUT_PIN25_High (1UL) /*!< Pin driver is high */ +#define GPIO_OUT_PIN25_Low (0x0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN25_High (0x1UL) /*!< Pin driver is high */ /* Bit 24 : Pin 24 */ #define GPIO_OUT_PIN24_Pos (24UL) /*!< Position of PIN24 field. */ #define GPIO_OUT_PIN24_Msk (0x1UL << GPIO_OUT_PIN24_Pos) /*!< Bit mask of PIN24 field. */ -#define GPIO_OUT_PIN24_Low (0UL) /*!< Pin driver is low */ -#define GPIO_OUT_PIN24_High (1UL) /*!< Pin driver is high */ +#define GPIO_OUT_PIN24_Low (0x0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN24_High (0x1UL) /*!< Pin driver is high */ /* Bit 23 : Pin 23 */ #define GPIO_OUT_PIN23_Pos (23UL) /*!< Position of PIN23 field. */ #define GPIO_OUT_PIN23_Msk (0x1UL << GPIO_OUT_PIN23_Pos) /*!< Bit mask of PIN23 field. */ -#define GPIO_OUT_PIN23_Low (0UL) /*!< Pin driver is low */ -#define GPIO_OUT_PIN23_High (1UL) /*!< Pin driver is high */ +#define GPIO_OUT_PIN23_Low (0x0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN23_High (0x1UL) /*!< Pin driver is high */ /* Bit 22 : Pin 22 */ #define GPIO_OUT_PIN22_Pos (22UL) /*!< Position of PIN22 field. */ #define GPIO_OUT_PIN22_Msk (0x1UL << GPIO_OUT_PIN22_Pos) /*!< Bit mask of PIN22 field. */ -#define GPIO_OUT_PIN22_Low (0UL) /*!< Pin driver is low */ -#define GPIO_OUT_PIN22_High (1UL) /*!< Pin driver is high */ +#define GPIO_OUT_PIN22_Low (0x0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN22_High (0x1UL) /*!< Pin driver is high */ /* Bit 21 : Pin 21 */ #define GPIO_OUT_PIN21_Pos (21UL) /*!< Position of PIN21 field. */ #define GPIO_OUT_PIN21_Msk (0x1UL << GPIO_OUT_PIN21_Pos) /*!< Bit mask of PIN21 field. */ -#define GPIO_OUT_PIN21_Low (0UL) /*!< Pin driver is low */ -#define GPIO_OUT_PIN21_High (1UL) /*!< Pin driver is high */ +#define GPIO_OUT_PIN21_Low (0x0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN21_High (0x1UL) /*!< Pin driver is high */ /* Bit 20 : Pin 20 */ #define GPIO_OUT_PIN20_Pos (20UL) /*!< Position of PIN20 field. */ #define GPIO_OUT_PIN20_Msk (0x1UL << GPIO_OUT_PIN20_Pos) /*!< Bit mask of PIN20 field. */ -#define GPIO_OUT_PIN20_Low (0UL) /*!< Pin driver is low */ -#define GPIO_OUT_PIN20_High (1UL) /*!< Pin driver is high */ +#define GPIO_OUT_PIN20_Low (0x0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN20_High (0x1UL) /*!< Pin driver is high */ /* Bit 19 : Pin 19 */ #define GPIO_OUT_PIN19_Pos (19UL) /*!< Position of PIN19 field. */ #define GPIO_OUT_PIN19_Msk (0x1UL << GPIO_OUT_PIN19_Pos) /*!< Bit mask of PIN19 field. */ -#define GPIO_OUT_PIN19_Low (0UL) /*!< Pin driver is low */ -#define GPIO_OUT_PIN19_High (1UL) /*!< Pin driver is high */ +#define GPIO_OUT_PIN19_Low (0x0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN19_High (0x1UL) /*!< Pin driver is high */ /* Bit 18 : Pin 18 */ #define GPIO_OUT_PIN18_Pos (18UL) /*!< Position of PIN18 field. */ #define GPIO_OUT_PIN18_Msk (0x1UL << GPIO_OUT_PIN18_Pos) /*!< Bit mask of PIN18 field. */ -#define GPIO_OUT_PIN18_Low (0UL) /*!< Pin driver is low */ -#define GPIO_OUT_PIN18_High (1UL) /*!< Pin driver is high */ +#define GPIO_OUT_PIN18_Low (0x0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN18_High (0x1UL) /*!< Pin driver is high */ /* Bit 17 : Pin 17 */ #define GPIO_OUT_PIN17_Pos (17UL) /*!< Position of PIN17 field. */ #define GPIO_OUT_PIN17_Msk (0x1UL << GPIO_OUT_PIN17_Pos) /*!< Bit mask of PIN17 field. */ -#define GPIO_OUT_PIN17_Low (0UL) /*!< Pin driver is low */ -#define GPIO_OUT_PIN17_High (1UL) /*!< Pin driver is high */ +#define GPIO_OUT_PIN17_Low (0x0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN17_High (0x1UL) /*!< Pin driver is high */ /* Bit 16 : Pin 16 */ #define GPIO_OUT_PIN16_Pos (16UL) /*!< Position of PIN16 field. */ #define GPIO_OUT_PIN16_Msk (0x1UL << GPIO_OUT_PIN16_Pos) /*!< Bit mask of PIN16 field. */ -#define GPIO_OUT_PIN16_Low (0UL) /*!< Pin driver is low */ -#define GPIO_OUT_PIN16_High (1UL) /*!< Pin driver is high */ +#define GPIO_OUT_PIN16_Low (0x0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN16_High (0x1UL) /*!< Pin driver is high */ /* Bit 15 : Pin 15 */ #define GPIO_OUT_PIN15_Pos (15UL) /*!< Position of PIN15 field. */ #define GPIO_OUT_PIN15_Msk (0x1UL << GPIO_OUT_PIN15_Pos) /*!< Bit mask of PIN15 field. */ -#define GPIO_OUT_PIN15_Low (0UL) /*!< Pin driver is low */ -#define GPIO_OUT_PIN15_High (1UL) /*!< Pin driver is high */ +#define GPIO_OUT_PIN15_Low (0x0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN15_High (0x1UL) /*!< Pin driver is high */ /* Bit 14 : Pin 14 */ #define GPIO_OUT_PIN14_Pos (14UL) /*!< Position of PIN14 field. */ #define GPIO_OUT_PIN14_Msk (0x1UL << GPIO_OUT_PIN14_Pos) /*!< Bit mask of PIN14 field. */ -#define GPIO_OUT_PIN14_Low (0UL) /*!< Pin driver is low */ -#define GPIO_OUT_PIN14_High (1UL) /*!< Pin driver is high */ +#define GPIO_OUT_PIN14_Low (0x0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN14_High (0x1UL) /*!< Pin driver is high */ /* Bit 13 : Pin 13 */ #define GPIO_OUT_PIN13_Pos (13UL) /*!< Position of PIN13 field. */ #define GPIO_OUT_PIN13_Msk (0x1UL << GPIO_OUT_PIN13_Pos) /*!< Bit mask of PIN13 field. */ -#define GPIO_OUT_PIN13_Low (0UL) /*!< Pin driver is low */ -#define GPIO_OUT_PIN13_High (1UL) /*!< Pin driver is high */ +#define GPIO_OUT_PIN13_Low (0x0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN13_High (0x1UL) /*!< Pin driver is high */ /* Bit 12 : Pin 12 */ #define GPIO_OUT_PIN12_Pos (12UL) /*!< Position of PIN12 field. */ #define GPIO_OUT_PIN12_Msk (0x1UL << GPIO_OUT_PIN12_Pos) /*!< Bit mask of PIN12 field. */ -#define GPIO_OUT_PIN12_Low (0UL) /*!< Pin driver is low */ -#define GPIO_OUT_PIN12_High (1UL) /*!< Pin driver is high */ +#define GPIO_OUT_PIN12_Low (0x0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN12_High (0x1UL) /*!< Pin driver is high */ /* Bit 11 : Pin 11 */ #define GPIO_OUT_PIN11_Pos (11UL) /*!< Position of PIN11 field. */ #define GPIO_OUT_PIN11_Msk (0x1UL << GPIO_OUT_PIN11_Pos) /*!< Bit mask of PIN11 field. */ -#define GPIO_OUT_PIN11_Low (0UL) /*!< Pin driver is low */ -#define GPIO_OUT_PIN11_High (1UL) /*!< Pin driver is high */ +#define GPIO_OUT_PIN11_Low (0x0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN11_High (0x1UL) /*!< Pin driver is high */ /* Bit 10 : Pin 10 */ #define GPIO_OUT_PIN10_Pos (10UL) /*!< Position of PIN10 field. */ #define GPIO_OUT_PIN10_Msk (0x1UL << GPIO_OUT_PIN10_Pos) /*!< Bit mask of PIN10 field. */ -#define GPIO_OUT_PIN10_Low (0UL) /*!< Pin driver is low */ -#define GPIO_OUT_PIN10_High (1UL) /*!< Pin driver is high */ +#define GPIO_OUT_PIN10_Low (0x0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN10_High (0x1UL) /*!< Pin driver is high */ /* Bit 9 : Pin 9 */ #define GPIO_OUT_PIN9_Pos (9UL) /*!< Position of PIN9 field. */ #define GPIO_OUT_PIN9_Msk (0x1UL << GPIO_OUT_PIN9_Pos) /*!< Bit mask of PIN9 field. */ -#define GPIO_OUT_PIN9_Low (0UL) /*!< Pin driver is low */ -#define GPIO_OUT_PIN9_High (1UL) /*!< Pin driver is high */ +#define GPIO_OUT_PIN9_Low (0x0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN9_High (0x1UL) /*!< Pin driver is high */ /* Bit 8 : Pin 8 */ #define GPIO_OUT_PIN8_Pos (8UL) /*!< Position of PIN8 field. */ #define GPIO_OUT_PIN8_Msk (0x1UL << GPIO_OUT_PIN8_Pos) /*!< Bit mask of PIN8 field. */ -#define GPIO_OUT_PIN8_Low (0UL) /*!< Pin driver is low */ -#define GPIO_OUT_PIN8_High (1UL) /*!< Pin driver is high */ +#define GPIO_OUT_PIN8_Low (0x0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN8_High (0x1UL) /*!< Pin driver is high */ /* Bit 7 : Pin 7 */ #define GPIO_OUT_PIN7_Pos (7UL) /*!< Position of PIN7 field. */ #define GPIO_OUT_PIN7_Msk (0x1UL << GPIO_OUT_PIN7_Pos) /*!< Bit mask of PIN7 field. */ -#define GPIO_OUT_PIN7_Low (0UL) /*!< Pin driver is low */ -#define GPIO_OUT_PIN7_High (1UL) /*!< Pin driver is high */ +#define GPIO_OUT_PIN7_Low (0x0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN7_High (0x1UL) /*!< Pin driver is high */ /* Bit 6 : Pin 6 */ #define GPIO_OUT_PIN6_Pos (6UL) /*!< Position of PIN6 field. */ #define GPIO_OUT_PIN6_Msk (0x1UL << GPIO_OUT_PIN6_Pos) /*!< Bit mask of PIN6 field. */ -#define GPIO_OUT_PIN6_Low (0UL) /*!< Pin driver is low */ -#define GPIO_OUT_PIN6_High (1UL) /*!< Pin driver is high */ +#define GPIO_OUT_PIN6_Low (0x0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN6_High (0x1UL) /*!< Pin driver is high */ /* Bit 5 : Pin 5 */ #define GPIO_OUT_PIN5_Pos (5UL) /*!< Position of PIN5 field. */ #define GPIO_OUT_PIN5_Msk (0x1UL << GPIO_OUT_PIN5_Pos) /*!< Bit mask of PIN5 field. */ -#define GPIO_OUT_PIN5_Low (0UL) /*!< Pin driver is low */ -#define GPIO_OUT_PIN5_High (1UL) /*!< Pin driver is high */ +#define GPIO_OUT_PIN5_Low (0x0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN5_High (0x1UL) /*!< Pin driver is high */ /* Bit 4 : Pin 4 */ #define GPIO_OUT_PIN4_Pos (4UL) /*!< Position of PIN4 field. */ #define GPIO_OUT_PIN4_Msk (0x1UL << GPIO_OUT_PIN4_Pos) /*!< Bit mask of PIN4 field. */ -#define GPIO_OUT_PIN4_Low (0UL) /*!< Pin driver is low */ -#define GPIO_OUT_PIN4_High (1UL) /*!< Pin driver is high */ +#define GPIO_OUT_PIN4_Low (0x0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN4_High (0x1UL) /*!< Pin driver is high */ /* Bit 3 : Pin 3 */ #define GPIO_OUT_PIN3_Pos (3UL) /*!< Position of PIN3 field. */ #define GPIO_OUT_PIN3_Msk (0x1UL << GPIO_OUT_PIN3_Pos) /*!< Bit mask of PIN3 field. */ -#define GPIO_OUT_PIN3_Low (0UL) /*!< Pin driver is low */ -#define GPIO_OUT_PIN3_High (1UL) /*!< Pin driver is high */ +#define GPIO_OUT_PIN3_Low (0x0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN3_High (0x1UL) /*!< Pin driver is high */ /* Bit 2 : Pin 2 */ #define GPIO_OUT_PIN2_Pos (2UL) /*!< Position of PIN2 field. */ #define GPIO_OUT_PIN2_Msk (0x1UL << GPIO_OUT_PIN2_Pos) /*!< Bit mask of PIN2 field. */ -#define GPIO_OUT_PIN2_Low (0UL) /*!< Pin driver is low */ -#define GPIO_OUT_PIN2_High (1UL) /*!< Pin driver is high */ +#define GPIO_OUT_PIN2_Low (0x0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN2_High (0x1UL) /*!< Pin driver is high */ /* Bit 1 : Pin 1 */ #define GPIO_OUT_PIN1_Pos (1UL) /*!< Position of PIN1 field. */ #define GPIO_OUT_PIN1_Msk (0x1UL << GPIO_OUT_PIN1_Pos) /*!< Bit mask of PIN1 field. */ -#define GPIO_OUT_PIN1_Low (0UL) /*!< Pin driver is low */ -#define GPIO_OUT_PIN1_High (1UL) /*!< Pin driver is high */ +#define GPIO_OUT_PIN1_Low (0x0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN1_High (0x1UL) /*!< Pin driver is high */ /* Bit 0 : Pin 0 */ #define GPIO_OUT_PIN0_Pos (0UL) /*!< Position of PIN0 field. */ #define GPIO_OUT_PIN0_Msk (0x1UL << GPIO_OUT_PIN0_Pos) /*!< Bit mask of PIN0 field. */ -#define GPIO_OUT_PIN0_Low (0UL) /*!< Pin driver is low */ -#define GPIO_OUT_PIN0_High (1UL) /*!< Pin driver is high */ +#define GPIO_OUT_PIN0_Low (0x0UL) /*!< Pin driver is low */ +#define GPIO_OUT_PIN0_High (0x1UL) /*!< Pin driver is high */ /* Register: GPIO_OUTSET */ /* Description: Set individual bits in GPIO port */ @@ -2985,226 +2985,226 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 31 : Pin 31 */ #define GPIO_OUTSET_PIN31_Pos (31UL) /*!< Position of PIN31 field. */ #define GPIO_OUTSET_PIN31_Msk (0x1UL << GPIO_OUTSET_PIN31_Pos) /*!< Bit mask of PIN31 field. */ -#define GPIO_OUTSET_PIN31_Low (0UL) /*!< Read: pin driver is low */ -#define GPIO_OUTSET_PIN31_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTSET_PIN31_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ +#define GPIO_OUTSET_PIN31_Low (0x0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN31_High (0x1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN31_Set (0x1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ /* Bit 30 : Pin 30 */ #define GPIO_OUTSET_PIN30_Pos (30UL) /*!< Position of PIN30 field. */ #define GPIO_OUTSET_PIN30_Msk (0x1UL << GPIO_OUTSET_PIN30_Pos) /*!< Bit mask of PIN30 field. */ -#define GPIO_OUTSET_PIN30_Low (0UL) /*!< Read: pin driver is low */ -#define GPIO_OUTSET_PIN30_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTSET_PIN30_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ +#define GPIO_OUTSET_PIN30_Low (0x0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN30_High (0x1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN30_Set (0x1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ /* Bit 29 : Pin 29 */ #define GPIO_OUTSET_PIN29_Pos (29UL) /*!< Position of PIN29 field. */ #define GPIO_OUTSET_PIN29_Msk (0x1UL << GPIO_OUTSET_PIN29_Pos) /*!< Bit mask of PIN29 field. */ -#define GPIO_OUTSET_PIN29_Low (0UL) /*!< Read: pin driver is low */ -#define GPIO_OUTSET_PIN29_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTSET_PIN29_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ +#define GPIO_OUTSET_PIN29_Low (0x0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN29_High (0x1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN29_Set (0x1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ /* Bit 28 : Pin 28 */ #define GPIO_OUTSET_PIN28_Pos (28UL) /*!< Position of PIN28 field. */ #define GPIO_OUTSET_PIN28_Msk (0x1UL << GPIO_OUTSET_PIN28_Pos) /*!< Bit mask of PIN28 field. */ -#define GPIO_OUTSET_PIN28_Low (0UL) /*!< Read: pin driver is low */ -#define GPIO_OUTSET_PIN28_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTSET_PIN28_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ +#define GPIO_OUTSET_PIN28_Low (0x0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN28_High (0x1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN28_Set (0x1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ /* Bit 27 : Pin 27 */ #define GPIO_OUTSET_PIN27_Pos (27UL) /*!< Position of PIN27 field. */ #define GPIO_OUTSET_PIN27_Msk (0x1UL << GPIO_OUTSET_PIN27_Pos) /*!< Bit mask of PIN27 field. */ -#define GPIO_OUTSET_PIN27_Low (0UL) /*!< Read: pin driver is low */ -#define GPIO_OUTSET_PIN27_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTSET_PIN27_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ +#define GPIO_OUTSET_PIN27_Low (0x0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN27_High (0x1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN27_Set (0x1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ /* Bit 26 : Pin 26 */ #define GPIO_OUTSET_PIN26_Pos (26UL) /*!< Position of PIN26 field. */ #define GPIO_OUTSET_PIN26_Msk (0x1UL << GPIO_OUTSET_PIN26_Pos) /*!< Bit mask of PIN26 field. */ -#define GPIO_OUTSET_PIN26_Low (0UL) /*!< Read: pin driver is low */ -#define GPIO_OUTSET_PIN26_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTSET_PIN26_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ +#define GPIO_OUTSET_PIN26_Low (0x0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN26_High (0x1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN26_Set (0x1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ /* Bit 25 : Pin 25 */ #define GPIO_OUTSET_PIN25_Pos (25UL) /*!< Position of PIN25 field. */ #define GPIO_OUTSET_PIN25_Msk (0x1UL << GPIO_OUTSET_PIN25_Pos) /*!< Bit mask of PIN25 field. */ -#define GPIO_OUTSET_PIN25_Low (0UL) /*!< Read: pin driver is low */ -#define GPIO_OUTSET_PIN25_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTSET_PIN25_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ +#define GPIO_OUTSET_PIN25_Low (0x0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN25_High (0x1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN25_Set (0x1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ /* Bit 24 : Pin 24 */ #define GPIO_OUTSET_PIN24_Pos (24UL) /*!< Position of PIN24 field. */ #define GPIO_OUTSET_PIN24_Msk (0x1UL << GPIO_OUTSET_PIN24_Pos) /*!< Bit mask of PIN24 field. */ -#define GPIO_OUTSET_PIN24_Low (0UL) /*!< Read: pin driver is low */ -#define GPIO_OUTSET_PIN24_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTSET_PIN24_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ +#define GPIO_OUTSET_PIN24_Low (0x0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN24_High (0x1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN24_Set (0x1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ /* Bit 23 : Pin 23 */ #define GPIO_OUTSET_PIN23_Pos (23UL) /*!< Position of PIN23 field. */ #define GPIO_OUTSET_PIN23_Msk (0x1UL << GPIO_OUTSET_PIN23_Pos) /*!< Bit mask of PIN23 field. */ -#define GPIO_OUTSET_PIN23_Low (0UL) /*!< Read: pin driver is low */ -#define GPIO_OUTSET_PIN23_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTSET_PIN23_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ +#define GPIO_OUTSET_PIN23_Low (0x0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN23_High (0x1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN23_Set (0x1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ /* Bit 22 : Pin 22 */ #define GPIO_OUTSET_PIN22_Pos (22UL) /*!< Position of PIN22 field. */ #define GPIO_OUTSET_PIN22_Msk (0x1UL << GPIO_OUTSET_PIN22_Pos) /*!< Bit mask of PIN22 field. */ -#define GPIO_OUTSET_PIN22_Low (0UL) /*!< Read: pin driver is low */ -#define GPIO_OUTSET_PIN22_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTSET_PIN22_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ +#define GPIO_OUTSET_PIN22_Low (0x0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN22_High (0x1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN22_Set (0x1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ /* Bit 21 : Pin 21 */ #define GPIO_OUTSET_PIN21_Pos (21UL) /*!< Position of PIN21 field. */ #define GPIO_OUTSET_PIN21_Msk (0x1UL << GPIO_OUTSET_PIN21_Pos) /*!< Bit mask of PIN21 field. */ -#define GPIO_OUTSET_PIN21_Low (0UL) /*!< Read: pin driver is low */ -#define GPIO_OUTSET_PIN21_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTSET_PIN21_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ +#define GPIO_OUTSET_PIN21_Low (0x0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN21_High (0x1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN21_Set (0x1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ /* Bit 20 : Pin 20 */ #define GPIO_OUTSET_PIN20_Pos (20UL) /*!< Position of PIN20 field. */ #define GPIO_OUTSET_PIN20_Msk (0x1UL << GPIO_OUTSET_PIN20_Pos) /*!< Bit mask of PIN20 field. */ -#define GPIO_OUTSET_PIN20_Low (0UL) /*!< Read: pin driver is low */ -#define GPIO_OUTSET_PIN20_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTSET_PIN20_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ +#define GPIO_OUTSET_PIN20_Low (0x0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN20_High (0x1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN20_Set (0x1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ /* Bit 19 : Pin 19 */ #define GPIO_OUTSET_PIN19_Pos (19UL) /*!< Position of PIN19 field. */ #define GPIO_OUTSET_PIN19_Msk (0x1UL << GPIO_OUTSET_PIN19_Pos) /*!< Bit mask of PIN19 field. */ -#define GPIO_OUTSET_PIN19_Low (0UL) /*!< Read: pin driver is low */ -#define GPIO_OUTSET_PIN19_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTSET_PIN19_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ +#define GPIO_OUTSET_PIN19_Low (0x0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN19_High (0x1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN19_Set (0x1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ /* Bit 18 : Pin 18 */ #define GPIO_OUTSET_PIN18_Pos (18UL) /*!< Position of PIN18 field. */ #define GPIO_OUTSET_PIN18_Msk (0x1UL << GPIO_OUTSET_PIN18_Pos) /*!< Bit mask of PIN18 field. */ -#define GPIO_OUTSET_PIN18_Low (0UL) /*!< Read: pin driver is low */ -#define GPIO_OUTSET_PIN18_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTSET_PIN18_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ +#define GPIO_OUTSET_PIN18_Low (0x0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN18_High (0x1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN18_Set (0x1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ /* Bit 17 : Pin 17 */ #define GPIO_OUTSET_PIN17_Pos (17UL) /*!< Position of PIN17 field. */ #define GPIO_OUTSET_PIN17_Msk (0x1UL << GPIO_OUTSET_PIN17_Pos) /*!< Bit mask of PIN17 field. */ -#define GPIO_OUTSET_PIN17_Low (0UL) /*!< Read: pin driver is low */ -#define GPIO_OUTSET_PIN17_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTSET_PIN17_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ +#define GPIO_OUTSET_PIN17_Low (0x0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN17_High (0x1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN17_Set (0x1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ /* Bit 16 : Pin 16 */ #define GPIO_OUTSET_PIN16_Pos (16UL) /*!< Position of PIN16 field. */ #define GPIO_OUTSET_PIN16_Msk (0x1UL << GPIO_OUTSET_PIN16_Pos) /*!< Bit mask of PIN16 field. */ -#define GPIO_OUTSET_PIN16_Low (0UL) /*!< Read: pin driver is low */ -#define GPIO_OUTSET_PIN16_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTSET_PIN16_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ +#define GPIO_OUTSET_PIN16_Low (0x0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN16_High (0x1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN16_Set (0x1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ /* Bit 15 : Pin 15 */ #define GPIO_OUTSET_PIN15_Pos (15UL) /*!< Position of PIN15 field. */ #define GPIO_OUTSET_PIN15_Msk (0x1UL << GPIO_OUTSET_PIN15_Pos) /*!< Bit mask of PIN15 field. */ -#define GPIO_OUTSET_PIN15_Low (0UL) /*!< Read: pin driver is low */ -#define GPIO_OUTSET_PIN15_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTSET_PIN15_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ +#define GPIO_OUTSET_PIN15_Low (0x0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN15_High (0x1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN15_Set (0x1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ /* Bit 14 : Pin 14 */ #define GPIO_OUTSET_PIN14_Pos (14UL) /*!< Position of PIN14 field. */ #define GPIO_OUTSET_PIN14_Msk (0x1UL << GPIO_OUTSET_PIN14_Pos) /*!< Bit mask of PIN14 field. */ -#define GPIO_OUTSET_PIN14_Low (0UL) /*!< Read: pin driver is low */ -#define GPIO_OUTSET_PIN14_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTSET_PIN14_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ +#define GPIO_OUTSET_PIN14_Low (0x0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN14_High (0x1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN14_Set (0x1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ /* Bit 13 : Pin 13 */ #define GPIO_OUTSET_PIN13_Pos (13UL) /*!< Position of PIN13 field. */ #define GPIO_OUTSET_PIN13_Msk (0x1UL << GPIO_OUTSET_PIN13_Pos) /*!< Bit mask of PIN13 field. */ -#define GPIO_OUTSET_PIN13_Low (0UL) /*!< Read: pin driver is low */ -#define GPIO_OUTSET_PIN13_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTSET_PIN13_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ +#define GPIO_OUTSET_PIN13_Low (0x0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN13_High (0x1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN13_Set (0x1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ /* Bit 12 : Pin 12 */ #define GPIO_OUTSET_PIN12_Pos (12UL) /*!< Position of PIN12 field. */ #define GPIO_OUTSET_PIN12_Msk (0x1UL << GPIO_OUTSET_PIN12_Pos) /*!< Bit mask of PIN12 field. */ -#define GPIO_OUTSET_PIN12_Low (0UL) /*!< Read: pin driver is low */ -#define GPIO_OUTSET_PIN12_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTSET_PIN12_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ +#define GPIO_OUTSET_PIN12_Low (0x0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN12_High (0x1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN12_Set (0x1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ /* Bit 11 : Pin 11 */ #define GPIO_OUTSET_PIN11_Pos (11UL) /*!< Position of PIN11 field. */ #define GPIO_OUTSET_PIN11_Msk (0x1UL << GPIO_OUTSET_PIN11_Pos) /*!< Bit mask of PIN11 field. */ -#define GPIO_OUTSET_PIN11_Low (0UL) /*!< Read: pin driver is low */ -#define GPIO_OUTSET_PIN11_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTSET_PIN11_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ +#define GPIO_OUTSET_PIN11_Low (0x0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN11_High (0x1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN11_Set (0x1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ /* Bit 10 : Pin 10 */ #define GPIO_OUTSET_PIN10_Pos (10UL) /*!< Position of PIN10 field. */ #define GPIO_OUTSET_PIN10_Msk (0x1UL << GPIO_OUTSET_PIN10_Pos) /*!< Bit mask of PIN10 field. */ -#define GPIO_OUTSET_PIN10_Low (0UL) /*!< Read: pin driver is low */ -#define GPIO_OUTSET_PIN10_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTSET_PIN10_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ +#define GPIO_OUTSET_PIN10_Low (0x0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN10_High (0x1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN10_Set (0x1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ /* Bit 9 : Pin 9 */ #define GPIO_OUTSET_PIN9_Pos (9UL) /*!< Position of PIN9 field. */ #define GPIO_OUTSET_PIN9_Msk (0x1UL << GPIO_OUTSET_PIN9_Pos) /*!< Bit mask of PIN9 field. */ -#define GPIO_OUTSET_PIN9_Low (0UL) /*!< Read: pin driver is low */ -#define GPIO_OUTSET_PIN9_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTSET_PIN9_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ +#define GPIO_OUTSET_PIN9_Low (0x0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN9_High (0x1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN9_Set (0x1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ /* Bit 8 : Pin 8 */ #define GPIO_OUTSET_PIN8_Pos (8UL) /*!< Position of PIN8 field. */ #define GPIO_OUTSET_PIN8_Msk (0x1UL << GPIO_OUTSET_PIN8_Pos) /*!< Bit mask of PIN8 field. */ -#define GPIO_OUTSET_PIN8_Low (0UL) /*!< Read: pin driver is low */ -#define GPIO_OUTSET_PIN8_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTSET_PIN8_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ +#define GPIO_OUTSET_PIN8_Low (0x0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN8_High (0x1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN8_Set (0x1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ /* Bit 7 : Pin 7 */ #define GPIO_OUTSET_PIN7_Pos (7UL) /*!< Position of PIN7 field. */ #define GPIO_OUTSET_PIN7_Msk (0x1UL << GPIO_OUTSET_PIN7_Pos) /*!< Bit mask of PIN7 field. */ -#define GPIO_OUTSET_PIN7_Low (0UL) /*!< Read: pin driver is low */ -#define GPIO_OUTSET_PIN7_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTSET_PIN7_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ +#define GPIO_OUTSET_PIN7_Low (0x0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN7_High (0x1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN7_Set (0x1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ /* Bit 6 : Pin 6 */ #define GPIO_OUTSET_PIN6_Pos (6UL) /*!< Position of PIN6 field. */ #define GPIO_OUTSET_PIN6_Msk (0x1UL << GPIO_OUTSET_PIN6_Pos) /*!< Bit mask of PIN6 field. */ -#define GPIO_OUTSET_PIN6_Low (0UL) /*!< Read: pin driver is low */ -#define GPIO_OUTSET_PIN6_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTSET_PIN6_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ +#define GPIO_OUTSET_PIN6_Low (0x0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN6_High (0x1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN6_Set (0x1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ /* Bit 5 : Pin 5 */ #define GPIO_OUTSET_PIN5_Pos (5UL) /*!< Position of PIN5 field. */ #define GPIO_OUTSET_PIN5_Msk (0x1UL << GPIO_OUTSET_PIN5_Pos) /*!< Bit mask of PIN5 field. */ -#define GPIO_OUTSET_PIN5_Low (0UL) /*!< Read: pin driver is low */ -#define GPIO_OUTSET_PIN5_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTSET_PIN5_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ +#define GPIO_OUTSET_PIN5_Low (0x0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN5_High (0x1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN5_Set (0x1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ /* Bit 4 : Pin 4 */ #define GPIO_OUTSET_PIN4_Pos (4UL) /*!< Position of PIN4 field. */ #define GPIO_OUTSET_PIN4_Msk (0x1UL << GPIO_OUTSET_PIN4_Pos) /*!< Bit mask of PIN4 field. */ -#define GPIO_OUTSET_PIN4_Low (0UL) /*!< Read: pin driver is low */ -#define GPIO_OUTSET_PIN4_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTSET_PIN4_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ +#define GPIO_OUTSET_PIN4_Low (0x0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN4_High (0x1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN4_Set (0x1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ /* Bit 3 : Pin 3 */ #define GPIO_OUTSET_PIN3_Pos (3UL) /*!< Position of PIN3 field. */ #define GPIO_OUTSET_PIN3_Msk (0x1UL << GPIO_OUTSET_PIN3_Pos) /*!< Bit mask of PIN3 field. */ -#define GPIO_OUTSET_PIN3_Low (0UL) /*!< Read: pin driver is low */ -#define GPIO_OUTSET_PIN3_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTSET_PIN3_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ +#define GPIO_OUTSET_PIN3_Low (0x0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN3_High (0x1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN3_Set (0x1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ /* Bit 2 : Pin 2 */ #define GPIO_OUTSET_PIN2_Pos (2UL) /*!< Position of PIN2 field. */ #define GPIO_OUTSET_PIN2_Msk (0x1UL << GPIO_OUTSET_PIN2_Pos) /*!< Bit mask of PIN2 field. */ -#define GPIO_OUTSET_PIN2_Low (0UL) /*!< Read: pin driver is low */ -#define GPIO_OUTSET_PIN2_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTSET_PIN2_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ +#define GPIO_OUTSET_PIN2_Low (0x0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN2_High (0x1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN2_Set (0x1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ /* Bit 1 : Pin 1 */ #define GPIO_OUTSET_PIN1_Pos (1UL) /*!< Position of PIN1 field. */ #define GPIO_OUTSET_PIN1_Msk (0x1UL << GPIO_OUTSET_PIN1_Pos) /*!< Bit mask of PIN1 field. */ -#define GPIO_OUTSET_PIN1_Low (0UL) /*!< Read: pin driver is low */ -#define GPIO_OUTSET_PIN1_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTSET_PIN1_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ +#define GPIO_OUTSET_PIN1_Low (0x0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN1_High (0x1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN1_Set (0x1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ /* Bit 0 : Pin 0 */ #define GPIO_OUTSET_PIN0_Pos (0UL) /*!< Position of PIN0 field. */ #define GPIO_OUTSET_PIN0_Msk (0x1UL << GPIO_OUTSET_PIN0_Pos) /*!< Bit mask of PIN0 field. */ -#define GPIO_OUTSET_PIN0_Low (0UL) /*!< Read: pin driver is low */ -#define GPIO_OUTSET_PIN0_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTSET_PIN0_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ +#define GPIO_OUTSET_PIN0_Low (0x0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTSET_PIN0_High (0x1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTSET_PIN0_Set (0x1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ /* Register: GPIO_OUTCLR */ /* Description: Clear individual bits in GPIO port */ @@ -3212,226 +3212,226 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 31 : Pin 31 */ #define GPIO_OUTCLR_PIN31_Pos (31UL) /*!< Position of PIN31 field. */ #define GPIO_OUTCLR_PIN31_Msk (0x1UL << GPIO_OUTCLR_PIN31_Pos) /*!< Bit mask of PIN31 field. */ -#define GPIO_OUTCLR_PIN31_Low (0UL) /*!< Read: pin driver is low */ -#define GPIO_OUTCLR_PIN31_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTCLR_PIN31_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ +#define GPIO_OUTCLR_PIN31_Low (0x0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN31_High (0x1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN31_Clear (0x1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ /* Bit 30 : Pin 30 */ #define GPIO_OUTCLR_PIN30_Pos (30UL) /*!< Position of PIN30 field. */ #define GPIO_OUTCLR_PIN30_Msk (0x1UL << GPIO_OUTCLR_PIN30_Pos) /*!< Bit mask of PIN30 field. */ -#define GPIO_OUTCLR_PIN30_Low (0UL) /*!< Read: pin driver is low */ -#define GPIO_OUTCLR_PIN30_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTCLR_PIN30_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ +#define GPIO_OUTCLR_PIN30_Low (0x0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN30_High (0x1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN30_Clear (0x1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ /* Bit 29 : Pin 29 */ #define GPIO_OUTCLR_PIN29_Pos (29UL) /*!< Position of PIN29 field. */ #define GPIO_OUTCLR_PIN29_Msk (0x1UL << GPIO_OUTCLR_PIN29_Pos) /*!< Bit mask of PIN29 field. */ -#define GPIO_OUTCLR_PIN29_Low (0UL) /*!< Read: pin driver is low */ -#define GPIO_OUTCLR_PIN29_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTCLR_PIN29_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ +#define GPIO_OUTCLR_PIN29_Low (0x0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN29_High (0x1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN29_Clear (0x1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ /* Bit 28 : Pin 28 */ #define GPIO_OUTCLR_PIN28_Pos (28UL) /*!< Position of PIN28 field. */ #define GPIO_OUTCLR_PIN28_Msk (0x1UL << GPIO_OUTCLR_PIN28_Pos) /*!< Bit mask of PIN28 field. */ -#define GPIO_OUTCLR_PIN28_Low (0UL) /*!< Read: pin driver is low */ -#define GPIO_OUTCLR_PIN28_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTCLR_PIN28_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ +#define GPIO_OUTCLR_PIN28_Low (0x0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN28_High (0x1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN28_Clear (0x1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ /* Bit 27 : Pin 27 */ #define GPIO_OUTCLR_PIN27_Pos (27UL) /*!< Position of PIN27 field. */ #define GPIO_OUTCLR_PIN27_Msk (0x1UL << GPIO_OUTCLR_PIN27_Pos) /*!< Bit mask of PIN27 field. */ -#define GPIO_OUTCLR_PIN27_Low (0UL) /*!< Read: pin driver is low */ -#define GPIO_OUTCLR_PIN27_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTCLR_PIN27_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ +#define GPIO_OUTCLR_PIN27_Low (0x0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN27_High (0x1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN27_Clear (0x1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ /* Bit 26 : Pin 26 */ #define GPIO_OUTCLR_PIN26_Pos (26UL) /*!< Position of PIN26 field. */ #define GPIO_OUTCLR_PIN26_Msk (0x1UL << GPIO_OUTCLR_PIN26_Pos) /*!< Bit mask of PIN26 field. */ -#define GPIO_OUTCLR_PIN26_Low (0UL) /*!< Read: pin driver is low */ -#define GPIO_OUTCLR_PIN26_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTCLR_PIN26_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ +#define GPIO_OUTCLR_PIN26_Low (0x0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN26_High (0x1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN26_Clear (0x1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ /* Bit 25 : Pin 25 */ #define GPIO_OUTCLR_PIN25_Pos (25UL) /*!< Position of PIN25 field. */ #define GPIO_OUTCLR_PIN25_Msk (0x1UL << GPIO_OUTCLR_PIN25_Pos) /*!< Bit mask of PIN25 field. */ -#define GPIO_OUTCLR_PIN25_Low (0UL) /*!< Read: pin driver is low */ -#define GPIO_OUTCLR_PIN25_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTCLR_PIN25_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ +#define GPIO_OUTCLR_PIN25_Low (0x0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN25_High (0x1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN25_Clear (0x1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ /* Bit 24 : Pin 24 */ #define GPIO_OUTCLR_PIN24_Pos (24UL) /*!< Position of PIN24 field. */ #define GPIO_OUTCLR_PIN24_Msk (0x1UL << GPIO_OUTCLR_PIN24_Pos) /*!< Bit mask of PIN24 field. */ -#define GPIO_OUTCLR_PIN24_Low (0UL) /*!< Read: pin driver is low */ -#define GPIO_OUTCLR_PIN24_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTCLR_PIN24_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ +#define GPIO_OUTCLR_PIN24_Low (0x0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN24_High (0x1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN24_Clear (0x1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ /* Bit 23 : Pin 23 */ #define GPIO_OUTCLR_PIN23_Pos (23UL) /*!< Position of PIN23 field. */ #define GPIO_OUTCLR_PIN23_Msk (0x1UL << GPIO_OUTCLR_PIN23_Pos) /*!< Bit mask of PIN23 field. */ -#define GPIO_OUTCLR_PIN23_Low (0UL) /*!< Read: pin driver is low */ -#define GPIO_OUTCLR_PIN23_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTCLR_PIN23_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ +#define GPIO_OUTCLR_PIN23_Low (0x0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN23_High (0x1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN23_Clear (0x1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ /* Bit 22 : Pin 22 */ #define GPIO_OUTCLR_PIN22_Pos (22UL) /*!< Position of PIN22 field. */ #define GPIO_OUTCLR_PIN22_Msk (0x1UL << GPIO_OUTCLR_PIN22_Pos) /*!< Bit mask of PIN22 field. */ -#define GPIO_OUTCLR_PIN22_Low (0UL) /*!< Read: pin driver is low */ -#define GPIO_OUTCLR_PIN22_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTCLR_PIN22_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ +#define GPIO_OUTCLR_PIN22_Low (0x0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN22_High (0x1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN22_Clear (0x1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ /* Bit 21 : Pin 21 */ #define GPIO_OUTCLR_PIN21_Pos (21UL) /*!< Position of PIN21 field. */ #define GPIO_OUTCLR_PIN21_Msk (0x1UL << GPIO_OUTCLR_PIN21_Pos) /*!< Bit mask of PIN21 field. */ -#define GPIO_OUTCLR_PIN21_Low (0UL) /*!< Read: pin driver is low */ -#define GPIO_OUTCLR_PIN21_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTCLR_PIN21_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ +#define GPIO_OUTCLR_PIN21_Low (0x0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN21_High (0x1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN21_Clear (0x1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ /* Bit 20 : Pin 20 */ #define GPIO_OUTCLR_PIN20_Pos (20UL) /*!< Position of PIN20 field. */ #define GPIO_OUTCLR_PIN20_Msk (0x1UL << GPIO_OUTCLR_PIN20_Pos) /*!< Bit mask of PIN20 field. */ -#define GPIO_OUTCLR_PIN20_Low (0UL) /*!< Read: pin driver is low */ -#define GPIO_OUTCLR_PIN20_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTCLR_PIN20_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ +#define GPIO_OUTCLR_PIN20_Low (0x0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN20_High (0x1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN20_Clear (0x1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ /* Bit 19 : Pin 19 */ #define GPIO_OUTCLR_PIN19_Pos (19UL) /*!< Position of PIN19 field. */ #define GPIO_OUTCLR_PIN19_Msk (0x1UL << GPIO_OUTCLR_PIN19_Pos) /*!< Bit mask of PIN19 field. */ -#define GPIO_OUTCLR_PIN19_Low (0UL) /*!< Read: pin driver is low */ -#define GPIO_OUTCLR_PIN19_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTCLR_PIN19_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ +#define GPIO_OUTCLR_PIN19_Low (0x0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN19_High (0x1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN19_Clear (0x1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ /* Bit 18 : Pin 18 */ #define GPIO_OUTCLR_PIN18_Pos (18UL) /*!< Position of PIN18 field. */ #define GPIO_OUTCLR_PIN18_Msk (0x1UL << GPIO_OUTCLR_PIN18_Pos) /*!< Bit mask of PIN18 field. */ -#define GPIO_OUTCLR_PIN18_Low (0UL) /*!< Read: pin driver is low */ -#define GPIO_OUTCLR_PIN18_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTCLR_PIN18_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ +#define GPIO_OUTCLR_PIN18_Low (0x0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN18_High (0x1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN18_Clear (0x1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ /* Bit 17 : Pin 17 */ #define GPIO_OUTCLR_PIN17_Pos (17UL) /*!< Position of PIN17 field. */ #define GPIO_OUTCLR_PIN17_Msk (0x1UL << GPIO_OUTCLR_PIN17_Pos) /*!< Bit mask of PIN17 field. */ -#define GPIO_OUTCLR_PIN17_Low (0UL) /*!< Read: pin driver is low */ -#define GPIO_OUTCLR_PIN17_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTCLR_PIN17_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ +#define GPIO_OUTCLR_PIN17_Low (0x0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN17_High (0x1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN17_Clear (0x1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ /* Bit 16 : Pin 16 */ #define GPIO_OUTCLR_PIN16_Pos (16UL) /*!< Position of PIN16 field. */ #define GPIO_OUTCLR_PIN16_Msk (0x1UL << GPIO_OUTCLR_PIN16_Pos) /*!< Bit mask of PIN16 field. */ -#define GPIO_OUTCLR_PIN16_Low (0UL) /*!< Read: pin driver is low */ -#define GPIO_OUTCLR_PIN16_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTCLR_PIN16_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ +#define GPIO_OUTCLR_PIN16_Low (0x0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN16_High (0x1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN16_Clear (0x1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ /* Bit 15 : Pin 15 */ #define GPIO_OUTCLR_PIN15_Pos (15UL) /*!< Position of PIN15 field. */ #define GPIO_OUTCLR_PIN15_Msk (0x1UL << GPIO_OUTCLR_PIN15_Pos) /*!< Bit mask of PIN15 field. */ -#define GPIO_OUTCLR_PIN15_Low (0UL) /*!< Read: pin driver is low */ -#define GPIO_OUTCLR_PIN15_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTCLR_PIN15_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ +#define GPIO_OUTCLR_PIN15_Low (0x0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN15_High (0x1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN15_Clear (0x1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ /* Bit 14 : Pin 14 */ #define GPIO_OUTCLR_PIN14_Pos (14UL) /*!< Position of PIN14 field. */ #define GPIO_OUTCLR_PIN14_Msk (0x1UL << GPIO_OUTCLR_PIN14_Pos) /*!< Bit mask of PIN14 field. */ -#define GPIO_OUTCLR_PIN14_Low (0UL) /*!< Read: pin driver is low */ -#define GPIO_OUTCLR_PIN14_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTCLR_PIN14_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ +#define GPIO_OUTCLR_PIN14_Low (0x0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN14_High (0x1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN14_Clear (0x1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ /* Bit 13 : Pin 13 */ #define GPIO_OUTCLR_PIN13_Pos (13UL) /*!< Position of PIN13 field. */ #define GPIO_OUTCLR_PIN13_Msk (0x1UL << GPIO_OUTCLR_PIN13_Pos) /*!< Bit mask of PIN13 field. */ -#define GPIO_OUTCLR_PIN13_Low (0UL) /*!< Read: pin driver is low */ -#define GPIO_OUTCLR_PIN13_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTCLR_PIN13_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ +#define GPIO_OUTCLR_PIN13_Low (0x0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN13_High (0x1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN13_Clear (0x1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ /* Bit 12 : Pin 12 */ #define GPIO_OUTCLR_PIN12_Pos (12UL) /*!< Position of PIN12 field. */ #define GPIO_OUTCLR_PIN12_Msk (0x1UL << GPIO_OUTCLR_PIN12_Pos) /*!< Bit mask of PIN12 field. */ -#define GPIO_OUTCLR_PIN12_Low (0UL) /*!< Read: pin driver is low */ -#define GPIO_OUTCLR_PIN12_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTCLR_PIN12_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ +#define GPIO_OUTCLR_PIN12_Low (0x0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN12_High (0x1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN12_Clear (0x1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ /* Bit 11 : Pin 11 */ #define GPIO_OUTCLR_PIN11_Pos (11UL) /*!< Position of PIN11 field. */ #define GPIO_OUTCLR_PIN11_Msk (0x1UL << GPIO_OUTCLR_PIN11_Pos) /*!< Bit mask of PIN11 field. */ -#define GPIO_OUTCLR_PIN11_Low (0UL) /*!< Read: pin driver is low */ -#define GPIO_OUTCLR_PIN11_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTCLR_PIN11_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ +#define GPIO_OUTCLR_PIN11_Low (0x0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN11_High (0x1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN11_Clear (0x1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ /* Bit 10 : Pin 10 */ #define GPIO_OUTCLR_PIN10_Pos (10UL) /*!< Position of PIN10 field. */ #define GPIO_OUTCLR_PIN10_Msk (0x1UL << GPIO_OUTCLR_PIN10_Pos) /*!< Bit mask of PIN10 field. */ -#define GPIO_OUTCLR_PIN10_Low (0UL) /*!< Read: pin driver is low */ -#define GPIO_OUTCLR_PIN10_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTCLR_PIN10_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ +#define GPIO_OUTCLR_PIN10_Low (0x0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN10_High (0x1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN10_Clear (0x1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ /* Bit 9 : Pin 9 */ #define GPIO_OUTCLR_PIN9_Pos (9UL) /*!< Position of PIN9 field. */ #define GPIO_OUTCLR_PIN9_Msk (0x1UL << GPIO_OUTCLR_PIN9_Pos) /*!< Bit mask of PIN9 field. */ -#define GPIO_OUTCLR_PIN9_Low (0UL) /*!< Read: pin driver is low */ -#define GPIO_OUTCLR_PIN9_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTCLR_PIN9_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ +#define GPIO_OUTCLR_PIN9_Low (0x0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN9_High (0x1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN9_Clear (0x1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ /* Bit 8 : Pin 8 */ #define GPIO_OUTCLR_PIN8_Pos (8UL) /*!< Position of PIN8 field. */ #define GPIO_OUTCLR_PIN8_Msk (0x1UL << GPIO_OUTCLR_PIN8_Pos) /*!< Bit mask of PIN8 field. */ -#define GPIO_OUTCLR_PIN8_Low (0UL) /*!< Read: pin driver is low */ -#define GPIO_OUTCLR_PIN8_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTCLR_PIN8_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ +#define GPIO_OUTCLR_PIN8_Low (0x0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN8_High (0x1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN8_Clear (0x1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ /* Bit 7 : Pin 7 */ #define GPIO_OUTCLR_PIN7_Pos (7UL) /*!< Position of PIN7 field. */ #define GPIO_OUTCLR_PIN7_Msk (0x1UL << GPIO_OUTCLR_PIN7_Pos) /*!< Bit mask of PIN7 field. */ -#define GPIO_OUTCLR_PIN7_Low (0UL) /*!< Read: pin driver is low */ -#define GPIO_OUTCLR_PIN7_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTCLR_PIN7_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ +#define GPIO_OUTCLR_PIN7_Low (0x0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN7_High (0x1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN7_Clear (0x1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ /* Bit 6 : Pin 6 */ #define GPIO_OUTCLR_PIN6_Pos (6UL) /*!< Position of PIN6 field. */ #define GPIO_OUTCLR_PIN6_Msk (0x1UL << GPIO_OUTCLR_PIN6_Pos) /*!< Bit mask of PIN6 field. */ -#define GPIO_OUTCLR_PIN6_Low (0UL) /*!< Read: pin driver is low */ -#define GPIO_OUTCLR_PIN6_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTCLR_PIN6_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ +#define GPIO_OUTCLR_PIN6_Low (0x0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN6_High (0x1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN6_Clear (0x1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ /* Bit 5 : Pin 5 */ #define GPIO_OUTCLR_PIN5_Pos (5UL) /*!< Position of PIN5 field. */ #define GPIO_OUTCLR_PIN5_Msk (0x1UL << GPIO_OUTCLR_PIN5_Pos) /*!< Bit mask of PIN5 field. */ -#define GPIO_OUTCLR_PIN5_Low (0UL) /*!< Read: pin driver is low */ -#define GPIO_OUTCLR_PIN5_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTCLR_PIN5_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ +#define GPIO_OUTCLR_PIN5_Low (0x0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN5_High (0x1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN5_Clear (0x1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ /* Bit 4 : Pin 4 */ #define GPIO_OUTCLR_PIN4_Pos (4UL) /*!< Position of PIN4 field. */ #define GPIO_OUTCLR_PIN4_Msk (0x1UL << GPIO_OUTCLR_PIN4_Pos) /*!< Bit mask of PIN4 field. */ -#define GPIO_OUTCLR_PIN4_Low (0UL) /*!< Read: pin driver is low */ -#define GPIO_OUTCLR_PIN4_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTCLR_PIN4_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ +#define GPIO_OUTCLR_PIN4_Low (0x0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN4_High (0x1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN4_Clear (0x1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ /* Bit 3 : Pin 3 */ #define GPIO_OUTCLR_PIN3_Pos (3UL) /*!< Position of PIN3 field. */ #define GPIO_OUTCLR_PIN3_Msk (0x1UL << GPIO_OUTCLR_PIN3_Pos) /*!< Bit mask of PIN3 field. */ -#define GPIO_OUTCLR_PIN3_Low (0UL) /*!< Read: pin driver is low */ -#define GPIO_OUTCLR_PIN3_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTCLR_PIN3_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ +#define GPIO_OUTCLR_PIN3_Low (0x0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN3_High (0x1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN3_Clear (0x1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ /* Bit 2 : Pin 2 */ #define GPIO_OUTCLR_PIN2_Pos (2UL) /*!< Position of PIN2 field. */ #define GPIO_OUTCLR_PIN2_Msk (0x1UL << GPIO_OUTCLR_PIN2_Pos) /*!< Bit mask of PIN2 field. */ -#define GPIO_OUTCLR_PIN2_Low (0UL) /*!< Read: pin driver is low */ -#define GPIO_OUTCLR_PIN2_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTCLR_PIN2_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ +#define GPIO_OUTCLR_PIN2_Low (0x0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN2_High (0x1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN2_Clear (0x1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ /* Bit 1 : Pin 1 */ #define GPIO_OUTCLR_PIN1_Pos (1UL) /*!< Position of PIN1 field. */ #define GPIO_OUTCLR_PIN1_Msk (0x1UL << GPIO_OUTCLR_PIN1_Pos) /*!< Bit mask of PIN1 field. */ -#define GPIO_OUTCLR_PIN1_Low (0UL) /*!< Read: pin driver is low */ -#define GPIO_OUTCLR_PIN1_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTCLR_PIN1_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ +#define GPIO_OUTCLR_PIN1_Low (0x0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN1_High (0x1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN1_Clear (0x1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ /* Bit 0 : Pin 0 */ #define GPIO_OUTCLR_PIN0_Pos (0UL) /*!< Position of PIN0 field. */ #define GPIO_OUTCLR_PIN0_Msk (0x1UL << GPIO_OUTCLR_PIN0_Pos) /*!< Bit mask of PIN0 field. */ -#define GPIO_OUTCLR_PIN0_Low (0UL) /*!< Read: pin driver is low */ -#define GPIO_OUTCLR_PIN0_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTCLR_PIN0_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ +#define GPIO_OUTCLR_PIN0_Low (0x0UL) /*!< Read: pin driver is low */ +#define GPIO_OUTCLR_PIN0_High (0x1UL) /*!< Read: pin driver is high */ +#define GPIO_OUTCLR_PIN0_Clear (0x1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ /* Register: GPIO_IN */ /* Description: Read GPIO port */ @@ -3439,194 +3439,194 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 31 : Pin 31 */ #define GPIO_IN_PIN31_Pos (31UL) /*!< Position of PIN31 field. */ #define GPIO_IN_PIN31_Msk (0x1UL << GPIO_IN_PIN31_Pos) /*!< Bit mask of PIN31 field. */ -#define GPIO_IN_PIN31_Low (0UL) /*!< Pin input is low */ -#define GPIO_IN_PIN31_High (1UL) /*!< Pin input is high */ +#define GPIO_IN_PIN31_Low (0x0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN31_High (0x1UL) /*!< Pin input is high */ /* Bit 30 : Pin 30 */ #define GPIO_IN_PIN30_Pos (30UL) /*!< Position of PIN30 field. */ #define GPIO_IN_PIN30_Msk (0x1UL << GPIO_IN_PIN30_Pos) /*!< Bit mask of PIN30 field. */ -#define GPIO_IN_PIN30_Low (0UL) /*!< Pin input is low */ -#define GPIO_IN_PIN30_High (1UL) /*!< Pin input is high */ +#define GPIO_IN_PIN30_Low (0x0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN30_High (0x1UL) /*!< Pin input is high */ /* Bit 29 : Pin 29 */ #define GPIO_IN_PIN29_Pos (29UL) /*!< Position of PIN29 field. */ #define GPIO_IN_PIN29_Msk (0x1UL << GPIO_IN_PIN29_Pos) /*!< Bit mask of PIN29 field. */ -#define GPIO_IN_PIN29_Low (0UL) /*!< Pin input is low */ -#define GPIO_IN_PIN29_High (1UL) /*!< Pin input is high */ +#define GPIO_IN_PIN29_Low (0x0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN29_High (0x1UL) /*!< Pin input is high */ /* Bit 28 : Pin 28 */ #define GPIO_IN_PIN28_Pos (28UL) /*!< Position of PIN28 field. */ #define GPIO_IN_PIN28_Msk (0x1UL << GPIO_IN_PIN28_Pos) /*!< Bit mask of PIN28 field. */ -#define GPIO_IN_PIN28_Low (0UL) /*!< Pin input is low */ -#define GPIO_IN_PIN28_High (1UL) /*!< Pin input is high */ +#define GPIO_IN_PIN28_Low (0x0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN28_High (0x1UL) /*!< Pin input is high */ /* Bit 27 : Pin 27 */ #define GPIO_IN_PIN27_Pos (27UL) /*!< Position of PIN27 field. */ #define GPIO_IN_PIN27_Msk (0x1UL << GPIO_IN_PIN27_Pos) /*!< Bit mask of PIN27 field. */ -#define GPIO_IN_PIN27_Low (0UL) /*!< Pin input is low */ -#define GPIO_IN_PIN27_High (1UL) /*!< Pin input is high */ +#define GPIO_IN_PIN27_Low (0x0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN27_High (0x1UL) /*!< Pin input is high */ /* Bit 26 : Pin 26 */ #define GPIO_IN_PIN26_Pos (26UL) /*!< Position of PIN26 field. */ #define GPIO_IN_PIN26_Msk (0x1UL << GPIO_IN_PIN26_Pos) /*!< Bit mask of PIN26 field. */ -#define GPIO_IN_PIN26_Low (0UL) /*!< Pin input is low */ -#define GPIO_IN_PIN26_High (1UL) /*!< Pin input is high */ +#define GPIO_IN_PIN26_Low (0x0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN26_High (0x1UL) /*!< Pin input is high */ /* Bit 25 : Pin 25 */ #define GPIO_IN_PIN25_Pos (25UL) /*!< Position of PIN25 field. */ #define GPIO_IN_PIN25_Msk (0x1UL << GPIO_IN_PIN25_Pos) /*!< Bit mask of PIN25 field. */ -#define GPIO_IN_PIN25_Low (0UL) /*!< Pin input is low */ -#define GPIO_IN_PIN25_High (1UL) /*!< Pin input is high */ +#define GPIO_IN_PIN25_Low (0x0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN25_High (0x1UL) /*!< Pin input is high */ /* Bit 24 : Pin 24 */ #define GPIO_IN_PIN24_Pos (24UL) /*!< Position of PIN24 field. */ #define GPIO_IN_PIN24_Msk (0x1UL << GPIO_IN_PIN24_Pos) /*!< Bit mask of PIN24 field. */ -#define GPIO_IN_PIN24_Low (0UL) /*!< Pin input is low */ -#define GPIO_IN_PIN24_High (1UL) /*!< Pin input is high */ +#define GPIO_IN_PIN24_Low (0x0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN24_High (0x1UL) /*!< Pin input is high */ /* Bit 23 : Pin 23 */ #define GPIO_IN_PIN23_Pos (23UL) /*!< Position of PIN23 field. */ #define GPIO_IN_PIN23_Msk (0x1UL << GPIO_IN_PIN23_Pos) /*!< Bit mask of PIN23 field. */ -#define GPIO_IN_PIN23_Low (0UL) /*!< Pin input is low */ -#define GPIO_IN_PIN23_High (1UL) /*!< Pin input is high */ +#define GPIO_IN_PIN23_Low (0x0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN23_High (0x1UL) /*!< Pin input is high */ /* Bit 22 : Pin 22 */ #define GPIO_IN_PIN22_Pos (22UL) /*!< Position of PIN22 field. */ #define GPIO_IN_PIN22_Msk (0x1UL << GPIO_IN_PIN22_Pos) /*!< Bit mask of PIN22 field. */ -#define GPIO_IN_PIN22_Low (0UL) /*!< Pin input is low */ -#define GPIO_IN_PIN22_High (1UL) /*!< Pin input is high */ +#define GPIO_IN_PIN22_Low (0x0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN22_High (0x1UL) /*!< Pin input is high */ /* Bit 21 : Pin 21 */ #define GPIO_IN_PIN21_Pos (21UL) /*!< Position of PIN21 field. */ #define GPIO_IN_PIN21_Msk (0x1UL << GPIO_IN_PIN21_Pos) /*!< Bit mask of PIN21 field. */ -#define GPIO_IN_PIN21_Low (0UL) /*!< Pin input is low */ -#define GPIO_IN_PIN21_High (1UL) /*!< Pin input is high */ +#define GPIO_IN_PIN21_Low (0x0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN21_High (0x1UL) /*!< Pin input is high */ /* Bit 20 : Pin 20 */ #define GPIO_IN_PIN20_Pos (20UL) /*!< Position of PIN20 field. */ #define GPIO_IN_PIN20_Msk (0x1UL << GPIO_IN_PIN20_Pos) /*!< Bit mask of PIN20 field. */ -#define GPIO_IN_PIN20_Low (0UL) /*!< Pin input is low */ -#define GPIO_IN_PIN20_High (1UL) /*!< Pin input is high */ +#define GPIO_IN_PIN20_Low (0x0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN20_High (0x1UL) /*!< Pin input is high */ /* Bit 19 : Pin 19 */ #define GPIO_IN_PIN19_Pos (19UL) /*!< Position of PIN19 field. */ #define GPIO_IN_PIN19_Msk (0x1UL << GPIO_IN_PIN19_Pos) /*!< Bit mask of PIN19 field. */ -#define GPIO_IN_PIN19_Low (0UL) /*!< Pin input is low */ -#define GPIO_IN_PIN19_High (1UL) /*!< Pin input is high */ +#define GPIO_IN_PIN19_Low (0x0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN19_High (0x1UL) /*!< Pin input is high */ /* Bit 18 : Pin 18 */ #define GPIO_IN_PIN18_Pos (18UL) /*!< Position of PIN18 field. */ #define GPIO_IN_PIN18_Msk (0x1UL << GPIO_IN_PIN18_Pos) /*!< Bit mask of PIN18 field. */ -#define GPIO_IN_PIN18_Low (0UL) /*!< Pin input is low */ -#define GPIO_IN_PIN18_High (1UL) /*!< Pin input is high */ +#define GPIO_IN_PIN18_Low (0x0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN18_High (0x1UL) /*!< Pin input is high */ /* Bit 17 : Pin 17 */ #define GPIO_IN_PIN17_Pos (17UL) /*!< Position of PIN17 field. */ #define GPIO_IN_PIN17_Msk (0x1UL << GPIO_IN_PIN17_Pos) /*!< Bit mask of PIN17 field. */ -#define GPIO_IN_PIN17_Low (0UL) /*!< Pin input is low */ -#define GPIO_IN_PIN17_High (1UL) /*!< Pin input is high */ +#define GPIO_IN_PIN17_Low (0x0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN17_High (0x1UL) /*!< Pin input is high */ /* Bit 16 : Pin 16 */ #define GPIO_IN_PIN16_Pos (16UL) /*!< Position of PIN16 field. */ #define GPIO_IN_PIN16_Msk (0x1UL << GPIO_IN_PIN16_Pos) /*!< Bit mask of PIN16 field. */ -#define GPIO_IN_PIN16_Low (0UL) /*!< Pin input is low */ -#define GPIO_IN_PIN16_High (1UL) /*!< Pin input is high */ +#define GPIO_IN_PIN16_Low (0x0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN16_High (0x1UL) /*!< Pin input is high */ /* Bit 15 : Pin 15 */ #define GPIO_IN_PIN15_Pos (15UL) /*!< Position of PIN15 field. */ #define GPIO_IN_PIN15_Msk (0x1UL << GPIO_IN_PIN15_Pos) /*!< Bit mask of PIN15 field. */ -#define GPIO_IN_PIN15_Low (0UL) /*!< Pin input is low */ -#define GPIO_IN_PIN15_High (1UL) /*!< Pin input is high */ +#define GPIO_IN_PIN15_Low (0x0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN15_High (0x1UL) /*!< Pin input is high */ /* Bit 14 : Pin 14 */ #define GPIO_IN_PIN14_Pos (14UL) /*!< Position of PIN14 field. */ #define GPIO_IN_PIN14_Msk (0x1UL << GPIO_IN_PIN14_Pos) /*!< Bit mask of PIN14 field. */ -#define GPIO_IN_PIN14_Low (0UL) /*!< Pin input is low */ -#define GPIO_IN_PIN14_High (1UL) /*!< Pin input is high */ +#define GPIO_IN_PIN14_Low (0x0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN14_High (0x1UL) /*!< Pin input is high */ /* Bit 13 : Pin 13 */ #define GPIO_IN_PIN13_Pos (13UL) /*!< Position of PIN13 field. */ #define GPIO_IN_PIN13_Msk (0x1UL << GPIO_IN_PIN13_Pos) /*!< Bit mask of PIN13 field. */ -#define GPIO_IN_PIN13_Low (0UL) /*!< Pin input is low */ -#define GPIO_IN_PIN13_High (1UL) /*!< Pin input is high */ +#define GPIO_IN_PIN13_Low (0x0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN13_High (0x1UL) /*!< Pin input is high */ /* Bit 12 : Pin 12 */ #define GPIO_IN_PIN12_Pos (12UL) /*!< Position of PIN12 field. */ #define GPIO_IN_PIN12_Msk (0x1UL << GPIO_IN_PIN12_Pos) /*!< Bit mask of PIN12 field. */ -#define GPIO_IN_PIN12_Low (0UL) /*!< Pin input is low */ -#define GPIO_IN_PIN12_High (1UL) /*!< Pin input is high */ +#define GPIO_IN_PIN12_Low (0x0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN12_High (0x1UL) /*!< Pin input is high */ /* Bit 11 : Pin 11 */ #define GPIO_IN_PIN11_Pos (11UL) /*!< Position of PIN11 field. */ #define GPIO_IN_PIN11_Msk (0x1UL << GPIO_IN_PIN11_Pos) /*!< Bit mask of PIN11 field. */ -#define GPIO_IN_PIN11_Low (0UL) /*!< Pin input is low */ -#define GPIO_IN_PIN11_High (1UL) /*!< Pin input is high */ +#define GPIO_IN_PIN11_Low (0x0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN11_High (0x1UL) /*!< Pin input is high */ /* Bit 10 : Pin 10 */ #define GPIO_IN_PIN10_Pos (10UL) /*!< Position of PIN10 field. */ #define GPIO_IN_PIN10_Msk (0x1UL << GPIO_IN_PIN10_Pos) /*!< Bit mask of PIN10 field. */ -#define GPIO_IN_PIN10_Low (0UL) /*!< Pin input is low */ -#define GPIO_IN_PIN10_High (1UL) /*!< Pin input is high */ +#define GPIO_IN_PIN10_Low (0x0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN10_High (0x1UL) /*!< Pin input is high */ /* Bit 9 : Pin 9 */ #define GPIO_IN_PIN9_Pos (9UL) /*!< Position of PIN9 field. */ #define GPIO_IN_PIN9_Msk (0x1UL << GPIO_IN_PIN9_Pos) /*!< Bit mask of PIN9 field. */ -#define GPIO_IN_PIN9_Low (0UL) /*!< Pin input is low */ -#define GPIO_IN_PIN9_High (1UL) /*!< Pin input is high */ +#define GPIO_IN_PIN9_Low (0x0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN9_High (0x1UL) /*!< Pin input is high */ /* Bit 8 : Pin 8 */ #define GPIO_IN_PIN8_Pos (8UL) /*!< Position of PIN8 field. */ #define GPIO_IN_PIN8_Msk (0x1UL << GPIO_IN_PIN8_Pos) /*!< Bit mask of PIN8 field. */ -#define GPIO_IN_PIN8_Low (0UL) /*!< Pin input is low */ -#define GPIO_IN_PIN8_High (1UL) /*!< Pin input is high */ +#define GPIO_IN_PIN8_Low (0x0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN8_High (0x1UL) /*!< Pin input is high */ /* Bit 7 : Pin 7 */ #define GPIO_IN_PIN7_Pos (7UL) /*!< Position of PIN7 field. */ #define GPIO_IN_PIN7_Msk (0x1UL << GPIO_IN_PIN7_Pos) /*!< Bit mask of PIN7 field. */ -#define GPIO_IN_PIN7_Low (0UL) /*!< Pin input is low */ -#define GPIO_IN_PIN7_High (1UL) /*!< Pin input is high */ +#define GPIO_IN_PIN7_Low (0x0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN7_High (0x1UL) /*!< Pin input is high */ /* Bit 6 : Pin 6 */ #define GPIO_IN_PIN6_Pos (6UL) /*!< Position of PIN6 field. */ #define GPIO_IN_PIN6_Msk (0x1UL << GPIO_IN_PIN6_Pos) /*!< Bit mask of PIN6 field. */ -#define GPIO_IN_PIN6_Low (0UL) /*!< Pin input is low */ -#define GPIO_IN_PIN6_High (1UL) /*!< Pin input is high */ +#define GPIO_IN_PIN6_Low (0x0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN6_High (0x1UL) /*!< Pin input is high */ /* Bit 5 : Pin 5 */ #define GPIO_IN_PIN5_Pos (5UL) /*!< Position of PIN5 field. */ #define GPIO_IN_PIN5_Msk (0x1UL << GPIO_IN_PIN5_Pos) /*!< Bit mask of PIN5 field. */ -#define GPIO_IN_PIN5_Low (0UL) /*!< Pin input is low */ -#define GPIO_IN_PIN5_High (1UL) /*!< Pin input is high */ +#define GPIO_IN_PIN5_Low (0x0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN5_High (0x1UL) /*!< Pin input is high */ /* Bit 4 : Pin 4 */ #define GPIO_IN_PIN4_Pos (4UL) /*!< Position of PIN4 field. */ #define GPIO_IN_PIN4_Msk (0x1UL << GPIO_IN_PIN4_Pos) /*!< Bit mask of PIN4 field. */ -#define GPIO_IN_PIN4_Low (0UL) /*!< Pin input is low */ -#define GPIO_IN_PIN4_High (1UL) /*!< Pin input is high */ +#define GPIO_IN_PIN4_Low (0x0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN4_High (0x1UL) /*!< Pin input is high */ /* Bit 3 : Pin 3 */ #define GPIO_IN_PIN3_Pos (3UL) /*!< Position of PIN3 field. */ #define GPIO_IN_PIN3_Msk (0x1UL << GPIO_IN_PIN3_Pos) /*!< Bit mask of PIN3 field. */ -#define GPIO_IN_PIN3_Low (0UL) /*!< Pin input is low */ -#define GPIO_IN_PIN3_High (1UL) /*!< Pin input is high */ +#define GPIO_IN_PIN3_Low (0x0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN3_High (0x1UL) /*!< Pin input is high */ /* Bit 2 : Pin 2 */ #define GPIO_IN_PIN2_Pos (2UL) /*!< Position of PIN2 field. */ #define GPIO_IN_PIN2_Msk (0x1UL << GPIO_IN_PIN2_Pos) /*!< Bit mask of PIN2 field. */ -#define GPIO_IN_PIN2_Low (0UL) /*!< Pin input is low */ -#define GPIO_IN_PIN2_High (1UL) /*!< Pin input is high */ +#define GPIO_IN_PIN2_Low (0x0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN2_High (0x1UL) /*!< Pin input is high */ /* Bit 1 : Pin 1 */ #define GPIO_IN_PIN1_Pos (1UL) /*!< Position of PIN1 field. */ #define GPIO_IN_PIN1_Msk (0x1UL << GPIO_IN_PIN1_Pos) /*!< Bit mask of PIN1 field. */ -#define GPIO_IN_PIN1_Low (0UL) /*!< Pin input is low */ -#define GPIO_IN_PIN1_High (1UL) /*!< Pin input is high */ +#define GPIO_IN_PIN1_Low (0x0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN1_High (0x1UL) /*!< Pin input is high */ /* Bit 0 : Pin 0 */ #define GPIO_IN_PIN0_Pos (0UL) /*!< Position of PIN0 field. */ #define GPIO_IN_PIN0_Msk (0x1UL << GPIO_IN_PIN0_Pos) /*!< Bit mask of PIN0 field. */ -#define GPIO_IN_PIN0_Low (0UL) /*!< Pin input is low */ -#define GPIO_IN_PIN0_High (1UL) /*!< Pin input is high */ +#define GPIO_IN_PIN0_Low (0x0UL) /*!< Pin input is low */ +#define GPIO_IN_PIN0_High (0x1UL) /*!< Pin input is high */ /* Register: GPIO_DIR */ /* Description: Direction of GPIO pins */ @@ -3634,194 +3634,194 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 31 : Pin 31 */ #define GPIO_DIR_PIN31_Pos (31UL) /*!< Position of PIN31 field. */ #define GPIO_DIR_PIN31_Msk (0x1UL << GPIO_DIR_PIN31_Pos) /*!< Bit mask of PIN31 field. */ -#define GPIO_DIR_PIN31_Input (0UL) /*!< Pin set as input */ -#define GPIO_DIR_PIN31_Output (1UL) /*!< Pin set as output */ +#define GPIO_DIR_PIN31_Input (0x0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN31_Output (0x1UL) /*!< Pin set as output */ /* Bit 30 : Pin 30 */ #define GPIO_DIR_PIN30_Pos (30UL) /*!< Position of PIN30 field. */ #define GPIO_DIR_PIN30_Msk (0x1UL << GPIO_DIR_PIN30_Pos) /*!< Bit mask of PIN30 field. */ -#define GPIO_DIR_PIN30_Input (0UL) /*!< Pin set as input */ -#define GPIO_DIR_PIN30_Output (1UL) /*!< Pin set as output */ +#define GPIO_DIR_PIN30_Input (0x0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN30_Output (0x1UL) /*!< Pin set as output */ /* Bit 29 : Pin 29 */ #define GPIO_DIR_PIN29_Pos (29UL) /*!< Position of PIN29 field. */ #define GPIO_DIR_PIN29_Msk (0x1UL << GPIO_DIR_PIN29_Pos) /*!< Bit mask of PIN29 field. */ -#define GPIO_DIR_PIN29_Input (0UL) /*!< Pin set as input */ -#define GPIO_DIR_PIN29_Output (1UL) /*!< Pin set as output */ +#define GPIO_DIR_PIN29_Input (0x0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN29_Output (0x1UL) /*!< Pin set as output */ /* Bit 28 : Pin 28 */ #define GPIO_DIR_PIN28_Pos (28UL) /*!< Position of PIN28 field. */ #define GPIO_DIR_PIN28_Msk (0x1UL << GPIO_DIR_PIN28_Pos) /*!< Bit mask of PIN28 field. */ -#define GPIO_DIR_PIN28_Input (0UL) /*!< Pin set as input */ -#define GPIO_DIR_PIN28_Output (1UL) /*!< Pin set as output */ +#define GPIO_DIR_PIN28_Input (0x0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN28_Output (0x1UL) /*!< Pin set as output */ /* Bit 27 : Pin 27 */ #define GPIO_DIR_PIN27_Pos (27UL) /*!< Position of PIN27 field. */ #define GPIO_DIR_PIN27_Msk (0x1UL << GPIO_DIR_PIN27_Pos) /*!< Bit mask of PIN27 field. */ -#define GPIO_DIR_PIN27_Input (0UL) /*!< Pin set as input */ -#define GPIO_DIR_PIN27_Output (1UL) /*!< Pin set as output */ +#define GPIO_DIR_PIN27_Input (0x0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN27_Output (0x1UL) /*!< Pin set as output */ /* Bit 26 : Pin 26 */ #define GPIO_DIR_PIN26_Pos (26UL) /*!< Position of PIN26 field. */ #define GPIO_DIR_PIN26_Msk (0x1UL << GPIO_DIR_PIN26_Pos) /*!< Bit mask of PIN26 field. */ -#define GPIO_DIR_PIN26_Input (0UL) /*!< Pin set as input */ -#define GPIO_DIR_PIN26_Output (1UL) /*!< Pin set as output */ +#define GPIO_DIR_PIN26_Input (0x0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN26_Output (0x1UL) /*!< Pin set as output */ /* Bit 25 : Pin 25 */ #define GPIO_DIR_PIN25_Pos (25UL) /*!< Position of PIN25 field. */ #define GPIO_DIR_PIN25_Msk (0x1UL << GPIO_DIR_PIN25_Pos) /*!< Bit mask of PIN25 field. */ -#define GPIO_DIR_PIN25_Input (0UL) /*!< Pin set as input */ -#define GPIO_DIR_PIN25_Output (1UL) /*!< Pin set as output */ +#define GPIO_DIR_PIN25_Input (0x0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN25_Output (0x1UL) /*!< Pin set as output */ /* Bit 24 : Pin 24 */ #define GPIO_DIR_PIN24_Pos (24UL) /*!< Position of PIN24 field. */ #define GPIO_DIR_PIN24_Msk (0x1UL << GPIO_DIR_PIN24_Pos) /*!< Bit mask of PIN24 field. */ -#define GPIO_DIR_PIN24_Input (0UL) /*!< Pin set as input */ -#define GPIO_DIR_PIN24_Output (1UL) /*!< Pin set as output */ +#define GPIO_DIR_PIN24_Input (0x0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN24_Output (0x1UL) /*!< Pin set as output */ /* Bit 23 : Pin 23 */ #define GPIO_DIR_PIN23_Pos (23UL) /*!< Position of PIN23 field. */ #define GPIO_DIR_PIN23_Msk (0x1UL << GPIO_DIR_PIN23_Pos) /*!< Bit mask of PIN23 field. */ -#define GPIO_DIR_PIN23_Input (0UL) /*!< Pin set as input */ -#define GPIO_DIR_PIN23_Output (1UL) /*!< Pin set as output */ +#define GPIO_DIR_PIN23_Input (0x0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN23_Output (0x1UL) /*!< Pin set as output */ /* Bit 22 : Pin 22 */ #define GPIO_DIR_PIN22_Pos (22UL) /*!< Position of PIN22 field. */ #define GPIO_DIR_PIN22_Msk (0x1UL << GPIO_DIR_PIN22_Pos) /*!< Bit mask of PIN22 field. */ -#define GPIO_DIR_PIN22_Input (0UL) /*!< Pin set as input */ -#define GPIO_DIR_PIN22_Output (1UL) /*!< Pin set as output */ +#define GPIO_DIR_PIN22_Input (0x0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN22_Output (0x1UL) /*!< Pin set as output */ /* Bit 21 : Pin 21 */ #define GPIO_DIR_PIN21_Pos (21UL) /*!< Position of PIN21 field. */ #define GPIO_DIR_PIN21_Msk (0x1UL << GPIO_DIR_PIN21_Pos) /*!< Bit mask of PIN21 field. */ -#define GPIO_DIR_PIN21_Input (0UL) /*!< Pin set as input */ -#define GPIO_DIR_PIN21_Output (1UL) /*!< Pin set as output */ +#define GPIO_DIR_PIN21_Input (0x0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN21_Output (0x1UL) /*!< Pin set as output */ /* Bit 20 : Pin 20 */ #define GPIO_DIR_PIN20_Pos (20UL) /*!< Position of PIN20 field. */ #define GPIO_DIR_PIN20_Msk (0x1UL << GPIO_DIR_PIN20_Pos) /*!< Bit mask of PIN20 field. */ -#define GPIO_DIR_PIN20_Input (0UL) /*!< Pin set as input */ -#define GPIO_DIR_PIN20_Output (1UL) /*!< Pin set as output */ +#define GPIO_DIR_PIN20_Input (0x0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN20_Output (0x1UL) /*!< Pin set as output */ /* Bit 19 : Pin 19 */ #define GPIO_DIR_PIN19_Pos (19UL) /*!< Position of PIN19 field. */ #define GPIO_DIR_PIN19_Msk (0x1UL << GPIO_DIR_PIN19_Pos) /*!< Bit mask of PIN19 field. */ -#define GPIO_DIR_PIN19_Input (0UL) /*!< Pin set as input */ -#define GPIO_DIR_PIN19_Output (1UL) /*!< Pin set as output */ +#define GPIO_DIR_PIN19_Input (0x0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN19_Output (0x1UL) /*!< Pin set as output */ /* Bit 18 : Pin 18 */ #define GPIO_DIR_PIN18_Pos (18UL) /*!< Position of PIN18 field. */ #define GPIO_DIR_PIN18_Msk (0x1UL << GPIO_DIR_PIN18_Pos) /*!< Bit mask of PIN18 field. */ -#define GPIO_DIR_PIN18_Input (0UL) /*!< Pin set as input */ -#define GPIO_DIR_PIN18_Output (1UL) /*!< Pin set as output */ +#define GPIO_DIR_PIN18_Input (0x0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN18_Output (0x1UL) /*!< Pin set as output */ /* Bit 17 : Pin 17 */ #define GPIO_DIR_PIN17_Pos (17UL) /*!< Position of PIN17 field. */ #define GPIO_DIR_PIN17_Msk (0x1UL << GPIO_DIR_PIN17_Pos) /*!< Bit mask of PIN17 field. */ -#define GPIO_DIR_PIN17_Input (0UL) /*!< Pin set as input */ -#define GPIO_DIR_PIN17_Output (1UL) /*!< Pin set as output */ +#define GPIO_DIR_PIN17_Input (0x0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN17_Output (0x1UL) /*!< Pin set as output */ /* Bit 16 : Pin 16 */ #define GPIO_DIR_PIN16_Pos (16UL) /*!< Position of PIN16 field. */ #define GPIO_DIR_PIN16_Msk (0x1UL << GPIO_DIR_PIN16_Pos) /*!< Bit mask of PIN16 field. */ -#define GPIO_DIR_PIN16_Input (0UL) /*!< Pin set as input */ -#define GPIO_DIR_PIN16_Output (1UL) /*!< Pin set as output */ +#define GPIO_DIR_PIN16_Input (0x0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN16_Output (0x1UL) /*!< Pin set as output */ /* Bit 15 : Pin 15 */ #define GPIO_DIR_PIN15_Pos (15UL) /*!< Position of PIN15 field. */ #define GPIO_DIR_PIN15_Msk (0x1UL << GPIO_DIR_PIN15_Pos) /*!< Bit mask of PIN15 field. */ -#define GPIO_DIR_PIN15_Input (0UL) /*!< Pin set as input */ -#define GPIO_DIR_PIN15_Output (1UL) /*!< Pin set as output */ +#define GPIO_DIR_PIN15_Input (0x0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN15_Output (0x1UL) /*!< Pin set as output */ /* Bit 14 : Pin 14 */ #define GPIO_DIR_PIN14_Pos (14UL) /*!< Position of PIN14 field. */ #define GPIO_DIR_PIN14_Msk (0x1UL << GPIO_DIR_PIN14_Pos) /*!< Bit mask of PIN14 field. */ -#define GPIO_DIR_PIN14_Input (0UL) /*!< Pin set as input */ -#define GPIO_DIR_PIN14_Output (1UL) /*!< Pin set as output */ +#define GPIO_DIR_PIN14_Input (0x0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN14_Output (0x1UL) /*!< Pin set as output */ /* Bit 13 : Pin 13 */ #define GPIO_DIR_PIN13_Pos (13UL) /*!< Position of PIN13 field. */ #define GPIO_DIR_PIN13_Msk (0x1UL << GPIO_DIR_PIN13_Pos) /*!< Bit mask of PIN13 field. */ -#define GPIO_DIR_PIN13_Input (0UL) /*!< Pin set as input */ -#define GPIO_DIR_PIN13_Output (1UL) /*!< Pin set as output */ +#define GPIO_DIR_PIN13_Input (0x0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN13_Output (0x1UL) /*!< Pin set as output */ /* Bit 12 : Pin 12 */ #define GPIO_DIR_PIN12_Pos (12UL) /*!< Position of PIN12 field. */ #define GPIO_DIR_PIN12_Msk (0x1UL << GPIO_DIR_PIN12_Pos) /*!< Bit mask of PIN12 field. */ -#define GPIO_DIR_PIN12_Input (0UL) /*!< Pin set as input */ -#define GPIO_DIR_PIN12_Output (1UL) /*!< Pin set as output */ +#define GPIO_DIR_PIN12_Input (0x0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN12_Output (0x1UL) /*!< Pin set as output */ /* Bit 11 : Pin 11 */ #define GPIO_DIR_PIN11_Pos (11UL) /*!< Position of PIN11 field. */ #define GPIO_DIR_PIN11_Msk (0x1UL << GPIO_DIR_PIN11_Pos) /*!< Bit mask of PIN11 field. */ -#define GPIO_DIR_PIN11_Input (0UL) /*!< Pin set as input */ -#define GPIO_DIR_PIN11_Output (1UL) /*!< Pin set as output */ +#define GPIO_DIR_PIN11_Input (0x0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN11_Output (0x1UL) /*!< Pin set as output */ /* Bit 10 : Pin 10 */ #define GPIO_DIR_PIN10_Pos (10UL) /*!< Position of PIN10 field. */ #define GPIO_DIR_PIN10_Msk (0x1UL << GPIO_DIR_PIN10_Pos) /*!< Bit mask of PIN10 field. */ -#define GPIO_DIR_PIN10_Input (0UL) /*!< Pin set as input */ -#define GPIO_DIR_PIN10_Output (1UL) /*!< Pin set as output */ +#define GPIO_DIR_PIN10_Input (0x0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN10_Output (0x1UL) /*!< Pin set as output */ /* Bit 9 : Pin 9 */ #define GPIO_DIR_PIN9_Pos (9UL) /*!< Position of PIN9 field. */ #define GPIO_DIR_PIN9_Msk (0x1UL << GPIO_DIR_PIN9_Pos) /*!< Bit mask of PIN9 field. */ -#define GPIO_DIR_PIN9_Input (0UL) /*!< Pin set as input */ -#define GPIO_DIR_PIN9_Output (1UL) /*!< Pin set as output */ +#define GPIO_DIR_PIN9_Input (0x0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN9_Output (0x1UL) /*!< Pin set as output */ /* Bit 8 : Pin 8 */ #define GPIO_DIR_PIN8_Pos (8UL) /*!< Position of PIN8 field. */ #define GPIO_DIR_PIN8_Msk (0x1UL << GPIO_DIR_PIN8_Pos) /*!< Bit mask of PIN8 field. */ -#define GPIO_DIR_PIN8_Input (0UL) /*!< Pin set as input */ -#define GPIO_DIR_PIN8_Output (1UL) /*!< Pin set as output */ +#define GPIO_DIR_PIN8_Input (0x0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN8_Output (0x1UL) /*!< Pin set as output */ /* Bit 7 : Pin 7 */ #define GPIO_DIR_PIN7_Pos (7UL) /*!< Position of PIN7 field. */ #define GPIO_DIR_PIN7_Msk (0x1UL << GPIO_DIR_PIN7_Pos) /*!< Bit mask of PIN7 field. */ -#define GPIO_DIR_PIN7_Input (0UL) /*!< Pin set as input */ -#define GPIO_DIR_PIN7_Output (1UL) /*!< Pin set as output */ +#define GPIO_DIR_PIN7_Input (0x0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN7_Output (0x1UL) /*!< Pin set as output */ /* Bit 6 : Pin 6 */ #define GPIO_DIR_PIN6_Pos (6UL) /*!< Position of PIN6 field. */ #define GPIO_DIR_PIN6_Msk (0x1UL << GPIO_DIR_PIN6_Pos) /*!< Bit mask of PIN6 field. */ -#define GPIO_DIR_PIN6_Input (0UL) /*!< Pin set as input */ -#define GPIO_DIR_PIN6_Output (1UL) /*!< Pin set as output */ +#define GPIO_DIR_PIN6_Input (0x0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN6_Output (0x1UL) /*!< Pin set as output */ /* Bit 5 : Pin 5 */ #define GPIO_DIR_PIN5_Pos (5UL) /*!< Position of PIN5 field. */ #define GPIO_DIR_PIN5_Msk (0x1UL << GPIO_DIR_PIN5_Pos) /*!< Bit mask of PIN5 field. */ -#define GPIO_DIR_PIN5_Input (0UL) /*!< Pin set as input */ -#define GPIO_DIR_PIN5_Output (1UL) /*!< Pin set as output */ +#define GPIO_DIR_PIN5_Input (0x0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN5_Output (0x1UL) /*!< Pin set as output */ /* Bit 4 : Pin 4 */ #define GPIO_DIR_PIN4_Pos (4UL) /*!< Position of PIN4 field. */ #define GPIO_DIR_PIN4_Msk (0x1UL << GPIO_DIR_PIN4_Pos) /*!< Bit mask of PIN4 field. */ -#define GPIO_DIR_PIN4_Input (0UL) /*!< Pin set as input */ -#define GPIO_DIR_PIN4_Output (1UL) /*!< Pin set as output */ +#define GPIO_DIR_PIN4_Input (0x0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN4_Output (0x1UL) /*!< Pin set as output */ /* Bit 3 : Pin 3 */ #define GPIO_DIR_PIN3_Pos (3UL) /*!< Position of PIN3 field. */ #define GPIO_DIR_PIN3_Msk (0x1UL << GPIO_DIR_PIN3_Pos) /*!< Bit mask of PIN3 field. */ -#define GPIO_DIR_PIN3_Input (0UL) /*!< Pin set as input */ -#define GPIO_DIR_PIN3_Output (1UL) /*!< Pin set as output */ +#define GPIO_DIR_PIN3_Input (0x0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN3_Output (0x1UL) /*!< Pin set as output */ /* Bit 2 : Pin 2 */ #define GPIO_DIR_PIN2_Pos (2UL) /*!< Position of PIN2 field. */ #define GPIO_DIR_PIN2_Msk (0x1UL << GPIO_DIR_PIN2_Pos) /*!< Bit mask of PIN2 field. */ -#define GPIO_DIR_PIN2_Input (0UL) /*!< Pin set as input */ -#define GPIO_DIR_PIN2_Output (1UL) /*!< Pin set as output */ +#define GPIO_DIR_PIN2_Input (0x0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN2_Output (0x1UL) /*!< Pin set as output */ /* Bit 1 : Pin 1 */ #define GPIO_DIR_PIN1_Pos (1UL) /*!< Position of PIN1 field. */ #define GPIO_DIR_PIN1_Msk (0x1UL << GPIO_DIR_PIN1_Pos) /*!< Bit mask of PIN1 field. */ -#define GPIO_DIR_PIN1_Input (0UL) /*!< Pin set as input */ -#define GPIO_DIR_PIN1_Output (1UL) /*!< Pin set as output */ +#define GPIO_DIR_PIN1_Input (0x0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN1_Output (0x1UL) /*!< Pin set as output */ /* Bit 0 : Pin 0 */ #define GPIO_DIR_PIN0_Pos (0UL) /*!< Position of PIN0 field. */ #define GPIO_DIR_PIN0_Msk (0x1UL << GPIO_DIR_PIN0_Pos) /*!< Bit mask of PIN0 field. */ -#define GPIO_DIR_PIN0_Input (0UL) /*!< Pin set as input */ -#define GPIO_DIR_PIN0_Output (1UL) /*!< Pin set as output */ +#define GPIO_DIR_PIN0_Input (0x0UL) /*!< Pin set as input */ +#define GPIO_DIR_PIN0_Output (0x1UL) /*!< Pin set as output */ /* Register: GPIO_DIRSET */ /* Description: DIR set register */ @@ -3829,226 +3829,226 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 31 : Set as output pin 31 */ #define GPIO_DIRSET_PIN31_Pos (31UL) /*!< Position of PIN31 field. */ #define GPIO_DIRSET_PIN31_Msk (0x1UL << GPIO_DIRSET_PIN31_Pos) /*!< Bit mask of PIN31 field. */ -#define GPIO_DIRSET_PIN31_Input (0UL) /*!< Read: pin set as input */ -#define GPIO_DIRSET_PIN31_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRSET_PIN31_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ +#define GPIO_DIRSET_PIN31_Input (0x0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN31_Output (0x1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN31_Set (0x1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ /* Bit 30 : Set as output pin 30 */ #define GPIO_DIRSET_PIN30_Pos (30UL) /*!< Position of PIN30 field. */ #define GPIO_DIRSET_PIN30_Msk (0x1UL << GPIO_DIRSET_PIN30_Pos) /*!< Bit mask of PIN30 field. */ -#define GPIO_DIRSET_PIN30_Input (0UL) /*!< Read: pin set as input */ -#define GPIO_DIRSET_PIN30_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRSET_PIN30_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ +#define GPIO_DIRSET_PIN30_Input (0x0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN30_Output (0x1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN30_Set (0x1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ /* Bit 29 : Set as output pin 29 */ #define GPIO_DIRSET_PIN29_Pos (29UL) /*!< Position of PIN29 field. */ #define GPIO_DIRSET_PIN29_Msk (0x1UL << GPIO_DIRSET_PIN29_Pos) /*!< Bit mask of PIN29 field. */ -#define GPIO_DIRSET_PIN29_Input (0UL) /*!< Read: pin set as input */ -#define GPIO_DIRSET_PIN29_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRSET_PIN29_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ +#define GPIO_DIRSET_PIN29_Input (0x0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN29_Output (0x1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN29_Set (0x1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ /* Bit 28 : Set as output pin 28 */ #define GPIO_DIRSET_PIN28_Pos (28UL) /*!< Position of PIN28 field. */ #define GPIO_DIRSET_PIN28_Msk (0x1UL << GPIO_DIRSET_PIN28_Pos) /*!< Bit mask of PIN28 field. */ -#define GPIO_DIRSET_PIN28_Input (0UL) /*!< Read: pin set as input */ -#define GPIO_DIRSET_PIN28_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRSET_PIN28_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ +#define GPIO_DIRSET_PIN28_Input (0x0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN28_Output (0x1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN28_Set (0x1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ /* Bit 27 : Set as output pin 27 */ #define GPIO_DIRSET_PIN27_Pos (27UL) /*!< Position of PIN27 field. */ #define GPIO_DIRSET_PIN27_Msk (0x1UL << GPIO_DIRSET_PIN27_Pos) /*!< Bit mask of PIN27 field. */ -#define GPIO_DIRSET_PIN27_Input (0UL) /*!< Read: pin set as input */ -#define GPIO_DIRSET_PIN27_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRSET_PIN27_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ +#define GPIO_DIRSET_PIN27_Input (0x0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN27_Output (0x1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN27_Set (0x1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ /* Bit 26 : Set as output pin 26 */ #define GPIO_DIRSET_PIN26_Pos (26UL) /*!< Position of PIN26 field. */ #define GPIO_DIRSET_PIN26_Msk (0x1UL << GPIO_DIRSET_PIN26_Pos) /*!< Bit mask of PIN26 field. */ -#define GPIO_DIRSET_PIN26_Input (0UL) /*!< Read: pin set as input */ -#define GPIO_DIRSET_PIN26_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRSET_PIN26_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ +#define GPIO_DIRSET_PIN26_Input (0x0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN26_Output (0x1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN26_Set (0x1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ /* Bit 25 : Set as output pin 25 */ #define GPIO_DIRSET_PIN25_Pos (25UL) /*!< Position of PIN25 field. */ #define GPIO_DIRSET_PIN25_Msk (0x1UL << GPIO_DIRSET_PIN25_Pos) /*!< Bit mask of PIN25 field. */ -#define GPIO_DIRSET_PIN25_Input (0UL) /*!< Read: pin set as input */ -#define GPIO_DIRSET_PIN25_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRSET_PIN25_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ +#define GPIO_DIRSET_PIN25_Input (0x0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN25_Output (0x1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN25_Set (0x1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ /* Bit 24 : Set as output pin 24 */ #define GPIO_DIRSET_PIN24_Pos (24UL) /*!< Position of PIN24 field. */ #define GPIO_DIRSET_PIN24_Msk (0x1UL << GPIO_DIRSET_PIN24_Pos) /*!< Bit mask of PIN24 field. */ -#define GPIO_DIRSET_PIN24_Input (0UL) /*!< Read: pin set as input */ -#define GPIO_DIRSET_PIN24_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRSET_PIN24_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ +#define GPIO_DIRSET_PIN24_Input (0x0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN24_Output (0x1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN24_Set (0x1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ /* Bit 23 : Set as output pin 23 */ #define GPIO_DIRSET_PIN23_Pos (23UL) /*!< Position of PIN23 field. */ #define GPIO_DIRSET_PIN23_Msk (0x1UL << GPIO_DIRSET_PIN23_Pos) /*!< Bit mask of PIN23 field. */ -#define GPIO_DIRSET_PIN23_Input (0UL) /*!< Read: pin set as input */ -#define GPIO_DIRSET_PIN23_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRSET_PIN23_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ +#define GPIO_DIRSET_PIN23_Input (0x0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN23_Output (0x1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN23_Set (0x1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ /* Bit 22 : Set as output pin 22 */ #define GPIO_DIRSET_PIN22_Pos (22UL) /*!< Position of PIN22 field. */ #define GPIO_DIRSET_PIN22_Msk (0x1UL << GPIO_DIRSET_PIN22_Pos) /*!< Bit mask of PIN22 field. */ -#define GPIO_DIRSET_PIN22_Input (0UL) /*!< Read: pin set as input */ -#define GPIO_DIRSET_PIN22_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRSET_PIN22_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ +#define GPIO_DIRSET_PIN22_Input (0x0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN22_Output (0x1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN22_Set (0x1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ /* Bit 21 : Set as output pin 21 */ #define GPIO_DIRSET_PIN21_Pos (21UL) /*!< Position of PIN21 field. */ #define GPIO_DIRSET_PIN21_Msk (0x1UL << GPIO_DIRSET_PIN21_Pos) /*!< Bit mask of PIN21 field. */ -#define GPIO_DIRSET_PIN21_Input (0UL) /*!< Read: pin set as input */ -#define GPIO_DIRSET_PIN21_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRSET_PIN21_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ +#define GPIO_DIRSET_PIN21_Input (0x0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN21_Output (0x1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN21_Set (0x1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ /* Bit 20 : Set as output pin 20 */ #define GPIO_DIRSET_PIN20_Pos (20UL) /*!< Position of PIN20 field. */ #define GPIO_DIRSET_PIN20_Msk (0x1UL << GPIO_DIRSET_PIN20_Pos) /*!< Bit mask of PIN20 field. */ -#define GPIO_DIRSET_PIN20_Input (0UL) /*!< Read: pin set as input */ -#define GPIO_DIRSET_PIN20_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRSET_PIN20_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ +#define GPIO_DIRSET_PIN20_Input (0x0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN20_Output (0x1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN20_Set (0x1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ /* Bit 19 : Set as output pin 19 */ #define GPIO_DIRSET_PIN19_Pos (19UL) /*!< Position of PIN19 field. */ #define GPIO_DIRSET_PIN19_Msk (0x1UL << GPIO_DIRSET_PIN19_Pos) /*!< Bit mask of PIN19 field. */ -#define GPIO_DIRSET_PIN19_Input (0UL) /*!< Read: pin set as input */ -#define GPIO_DIRSET_PIN19_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRSET_PIN19_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ +#define GPIO_DIRSET_PIN19_Input (0x0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN19_Output (0x1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN19_Set (0x1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ /* Bit 18 : Set as output pin 18 */ #define GPIO_DIRSET_PIN18_Pos (18UL) /*!< Position of PIN18 field. */ #define GPIO_DIRSET_PIN18_Msk (0x1UL << GPIO_DIRSET_PIN18_Pos) /*!< Bit mask of PIN18 field. */ -#define GPIO_DIRSET_PIN18_Input (0UL) /*!< Read: pin set as input */ -#define GPIO_DIRSET_PIN18_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRSET_PIN18_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ +#define GPIO_DIRSET_PIN18_Input (0x0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN18_Output (0x1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN18_Set (0x1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ /* Bit 17 : Set as output pin 17 */ #define GPIO_DIRSET_PIN17_Pos (17UL) /*!< Position of PIN17 field. */ #define GPIO_DIRSET_PIN17_Msk (0x1UL << GPIO_DIRSET_PIN17_Pos) /*!< Bit mask of PIN17 field. */ -#define GPIO_DIRSET_PIN17_Input (0UL) /*!< Read: pin set as input */ -#define GPIO_DIRSET_PIN17_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRSET_PIN17_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ +#define GPIO_DIRSET_PIN17_Input (0x0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN17_Output (0x1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN17_Set (0x1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ /* Bit 16 : Set as output pin 16 */ #define GPIO_DIRSET_PIN16_Pos (16UL) /*!< Position of PIN16 field. */ #define GPIO_DIRSET_PIN16_Msk (0x1UL << GPIO_DIRSET_PIN16_Pos) /*!< Bit mask of PIN16 field. */ -#define GPIO_DIRSET_PIN16_Input (0UL) /*!< Read: pin set as input */ -#define GPIO_DIRSET_PIN16_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRSET_PIN16_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ +#define GPIO_DIRSET_PIN16_Input (0x0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN16_Output (0x1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN16_Set (0x1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ /* Bit 15 : Set as output pin 15 */ #define GPIO_DIRSET_PIN15_Pos (15UL) /*!< Position of PIN15 field. */ #define GPIO_DIRSET_PIN15_Msk (0x1UL << GPIO_DIRSET_PIN15_Pos) /*!< Bit mask of PIN15 field. */ -#define GPIO_DIRSET_PIN15_Input (0UL) /*!< Read: pin set as input */ -#define GPIO_DIRSET_PIN15_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRSET_PIN15_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ +#define GPIO_DIRSET_PIN15_Input (0x0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN15_Output (0x1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN15_Set (0x1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ /* Bit 14 : Set as output pin 14 */ #define GPIO_DIRSET_PIN14_Pos (14UL) /*!< Position of PIN14 field. */ #define GPIO_DIRSET_PIN14_Msk (0x1UL << GPIO_DIRSET_PIN14_Pos) /*!< Bit mask of PIN14 field. */ -#define GPIO_DIRSET_PIN14_Input (0UL) /*!< Read: pin set as input */ -#define GPIO_DIRSET_PIN14_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRSET_PIN14_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ +#define GPIO_DIRSET_PIN14_Input (0x0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN14_Output (0x1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN14_Set (0x1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ /* Bit 13 : Set as output pin 13 */ #define GPIO_DIRSET_PIN13_Pos (13UL) /*!< Position of PIN13 field. */ #define GPIO_DIRSET_PIN13_Msk (0x1UL << GPIO_DIRSET_PIN13_Pos) /*!< Bit mask of PIN13 field. */ -#define GPIO_DIRSET_PIN13_Input (0UL) /*!< Read: pin set as input */ -#define GPIO_DIRSET_PIN13_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRSET_PIN13_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ +#define GPIO_DIRSET_PIN13_Input (0x0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN13_Output (0x1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN13_Set (0x1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ /* Bit 12 : Set as output pin 12 */ #define GPIO_DIRSET_PIN12_Pos (12UL) /*!< Position of PIN12 field. */ #define GPIO_DIRSET_PIN12_Msk (0x1UL << GPIO_DIRSET_PIN12_Pos) /*!< Bit mask of PIN12 field. */ -#define GPIO_DIRSET_PIN12_Input (0UL) /*!< Read: pin set as input */ -#define GPIO_DIRSET_PIN12_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRSET_PIN12_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ +#define GPIO_DIRSET_PIN12_Input (0x0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN12_Output (0x1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN12_Set (0x1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ /* Bit 11 : Set as output pin 11 */ #define GPIO_DIRSET_PIN11_Pos (11UL) /*!< Position of PIN11 field. */ #define GPIO_DIRSET_PIN11_Msk (0x1UL << GPIO_DIRSET_PIN11_Pos) /*!< Bit mask of PIN11 field. */ -#define GPIO_DIRSET_PIN11_Input (0UL) /*!< Read: pin set as input */ -#define GPIO_DIRSET_PIN11_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRSET_PIN11_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ +#define GPIO_DIRSET_PIN11_Input (0x0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN11_Output (0x1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN11_Set (0x1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ /* Bit 10 : Set as output pin 10 */ #define GPIO_DIRSET_PIN10_Pos (10UL) /*!< Position of PIN10 field. */ #define GPIO_DIRSET_PIN10_Msk (0x1UL << GPIO_DIRSET_PIN10_Pos) /*!< Bit mask of PIN10 field. */ -#define GPIO_DIRSET_PIN10_Input (0UL) /*!< Read: pin set as input */ -#define GPIO_DIRSET_PIN10_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRSET_PIN10_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ +#define GPIO_DIRSET_PIN10_Input (0x0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN10_Output (0x1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN10_Set (0x1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ /* Bit 9 : Set as output pin 9 */ #define GPIO_DIRSET_PIN9_Pos (9UL) /*!< Position of PIN9 field. */ #define GPIO_DIRSET_PIN9_Msk (0x1UL << GPIO_DIRSET_PIN9_Pos) /*!< Bit mask of PIN9 field. */ -#define GPIO_DIRSET_PIN9_Input (0UL) /*!< Read: pin set as input */ -#define GPIO_DIRSET_PIN9_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRSET_PIN9_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ +#define GPIO_DIRSET_PIN9_Input (0x0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN9_Output (0x1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN9_Set (0x1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ /* Bit 8 : Set as output pin 8 */ #define GPIO_DIRSET_PIN8_Pos (8UL) /*!< Position of PIN8 field. */ #define GPIO_DIRSET_PIN8_Msk (0x1UL << GPIO_DIRSET_PIN8_Pos) /*!< Bit mask of PIN8 field. */ -#define GPIO_DIRSET_PIN8_Input (0UL) /*!< Read: pin set as input */ -#define GPIO_DIRSET_PIN8_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRSET_PIN8_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ +#define GPIO_DIRSET_PIN8_Input (0x0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN8_Output (0x1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN8_Set (0x1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ /* Bit 7 : Set as output pin 7 */ #define GPIO_DIRSET_PIN7_Pos (7UL) /*!< Position of PIN7 field. */ #define GPIO_DIRSET_PIN7_Msk (0x1UL << GPIO_DIRSET_PIN7_Pos) /*!< Bit mask of PIN7 field. */ -#define GPIO_DIRSET_PIN7_Input (0UL) /*!< Read: pin set as input */ -#define GPIO_DIRSET_PIN7_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRSET_PIN7_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ +#define GPIO_DIRSET_PIN7_Input (0x0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN7_Output (0x1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN7_Set (0x1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ /* Bit 6 : Set as output pin 6 */ #define GPIO_DIRSET_PIN6_Pos (6UL) /*!< Position of PIN6 field. */ #define GPIO_DIRSET_PIN6_Msk (0x1UL << GPIO_DIRSET_PIN6_Pos) /*!< Bit mask of PIN6 field. */ -#define GPIO_DIRSET_PIN6_Input (0UL) /*!< Read: pin set as input */ -#define GPIO_DIRSET_PIN6_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRSET_PIN6_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ +#define GPIO_DIRSET_PIN6_Input (0x0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN6_Output (0x1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN6_Set (0x1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ /* Bit 5 : Set as output pin 5 */ #define GPIO_DIRSET_PIN5_Pos (5UL) /*!< Position of PIN5 field. */ #define GPIO_DIRSET_PIN5_Msk (0x1UL << GPIO_DIRSET_PIN5_Pos) /*!< Bit mask of PIN5 field. */ -#define GPIO_DIRSET_PIN5_Input (0UL) /*!< Read: pin set as input */ -#define GPIO_DIRSET_PIN5_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRSET_PIN5_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ +#define GPIO_DIRSET_PIN5_Input (0x0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN5_Output (0x1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN5_Set (0x1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ /* Bit 4 : Set as output pin 4 */ #define GPIO_DIRSET_PIN4_Pos (4UL) /*!< Position of PIN4 field. */ #define GPIO_DIRSET_PIN4_Msk (0x1UL << GPIO_DIRSET_PIN4_Pos) /*!< Bit mask of PIN4 field. */ -#define GPIO_DIRSET_PIN4_Input (0UL) /*!< Read: pin set as input */ -#define GPIO_DIRSET_PIN4_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRSET_PIN4_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ +#define GPIO_DIRSET_PIN4_Input (0x0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN4_Output (0x1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN4_Set (0x1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ /* Bit 3 : Set as output pin 3 */ #define GPIO_DIRSET_PIN3_Pos (3UL) /*!< Position of PIN3 field. */ #define GPIO_DIRSET_PIN3_Msk (0x1UL << GPIO_DIRSET_PIN3_Pos) /*!< Bit mask of PIN3 field. */ -#define GPIO_DIRSET_PIN3_Input (0UL) /*!< Read: pin set as input */ -#define GPIO_DIRSET_PIN3_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRSET_PIN3_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ +#define GPIO_DIRSET_PIN3_Input (0x0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN3_Output (0x1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN3_Set (0x1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ /* Bit 2 : Set as output pin 2 */ #define GPIO_DIRSET_PIN2_Pos (2UL) /*!< Position of PIN2 field. */ #define GPIO_DIRSET_PIN2_Msk (0x1UL << GPIO_DIRSET_PIN2_Pos) /*!< Bit mask of PIN2 field. */ -#define GPIO_DIRSET_PIN2_Input (0UL) /*!< Read: pin set as input */ -#define GPIO_DIRSET_PIN2_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRSET_PIN2_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ +#define GPIO_DIRSET_PIN2_Input (0x0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN2_Output (0x1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN2_Set (0x1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ /* Bit 1 : Set as output pin 1 */ #define GPIO_DIRSET_PIN1_Pos (1UL) /*!< Position of PIN1 field. */ #define GPIO_DIRSET_PIN1_Msk (0x1UL << GPIO_DIRSET_PIN1_Pos) /*!< Bit mask of PIN1 field. */ -#define GPIO_DIRSET_PIN1_Input (0UL) /*!< Read: pin set as input */ -#define GPIO_DIRSET_PIN1_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRSET_PIN1_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ +#define GPIO_DIRSET_PIN1_Input (0x0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN1_Output (0x1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN1_Set (0x1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ /* Bit 0 : Set as output pin 0 */ #define GPIO_DIRSET_PIN0_Pos (0UL) /*!< Position of PIN0 field. */ #define GPIO_DIRSET_PIN0_Msk (0x1UL << GPIO_DIRSET_PIN0_Pos) /*!< Bit mask of PIN0 field. */ -#define GPIO_DIRSET_PIN0_Input (0UL) /*!< Read: pin set as input */ -#define GPIO_DIRSET_PIN0_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRSET_PIN0_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ +#define GPIO_DIRSET_PIN0_Input (0x0UL) /*!< Read: pin set as input */ +#define GPIO_DIRSET_PIN0_Output (0x1UL) /*!< Read: pin set as output */ +#define GPIO_DIRSET_PIN0_Set (0x1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ /* Register: GPIO_DIRCLR */ /* Description: DIR clear register */ @@ -4056,226 +4056,226 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 31 : Set as input pin 31 */ #define GPIO_DIRCLR_PIN31_Pos (31UL) /*!< Position of PIN31 field. */ #define GPIO_DIRCLR_PIN31_Msk (0x1UL << GPIO_DIRCLR_PIN31_Pos) /*!< Bit mask of PIN31 field. */ -#define GPIO_DIRCLR_PIN31_Input (0UL) /*!< Read: pin set as input */ -#define GPIO_DIRCLR_PIN31_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRCLR_PIN31_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ +#define GPIO_DIRCLR_PIN31_Input (0x0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN31_Output (0x1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN31_Clear (0x1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ /* Bit 30 : Set as input pin 30 */ #define GPIO_DIRCLR_PIN30_Pos (30UL) /*!< Position of PIN30 field. */ #define GPIO_DIRCLR_PIN30_Msk (0x1UL << GPIO_DIRCLR_PIN30_Pos) /*!< Bit mask of PIN30 field. */ -#define GPIO_DIRCLR_PIN30_Input (0UL) /*!< Read: pin set as input */ -#define GPIO_DIRCLR_PIN30_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRCLR_PIN30_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ +#define GPIO_DIRCLR_PIN30_Input (0x0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN30_Output (0x1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN30_Clear (0x1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ /* Bit 29 : Set as input pin 29 */ #define GPIO_DIRCLR_PIN29_Pos (29UL) /*!< Position of PIN29 field. */ #define GPIO_DIRCLR_PIN29_Msk (0x1UL << GPIO_DIRCLR_PIN29_Pos) /*!< Bit mask of PIN29 field. */ -#define GPIO_DIRCLR_PIN29_Input (0UL) /*!< Read: pin set as input */ -#define GPIO_DIRCLR_PIN29_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRCLR_PIN29_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ +#define GPIO_DIRCLR_PIN29_Input (0x0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN29_Output (0x1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN29_Clear (0x1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ /* Bit 28 : Set as input pin 28 */ #define GPIO_DIRCLR_PIN28_Pos (28UL) /*!< Position of PIN28 field. */ #define GPIO_DIRCLR_PIN28_Msk (0x1UL << GPIO_DIRCLR_PIN28_Pos) /*!< Bit mask of PIN28 field. */ -#define GPIO_DIRCLR_PIN28_Input (0UL) /*!< Read: pin set as input */ -#define GPIO_DIRCLR_PIN28_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRCLR_PIN28_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ +#define GPIO_DIRCLR_PIN28_Input (0x0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN28_Output (0x1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN28_Clear (0x1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ /* Bit 27 : Set as input pin 27 */ #define GPIO_DIRCLR_PIN27_Pos (27UL) /*!< Position of PIN27 field. */ #define GPIO_DIRCLR_PIN27_Msk (0x1UL << GPIO_DIRCLR_PIN27_Pos) /*!< Bit mask of PIN27 field. */ -#define GPIO_DIRCLR_PIN27_Input (0UL) /*!< Read: pin set as input */ -#define GPIO_DIRCLR_PIN27_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRCLR_PIN27_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ +#define GPIO_DIRCLR_PIN27_Input (0x0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN27_Output (0x1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN27_Clear (0x1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ /* Bit 26 : Set as input pin 26 */ #define GPIO_DIRCLR_PIN26_Pos (26UL) /*!< Position of PIN26 field. */ #define GPIO_DIRCLR_PIN26_Msk (0x1UL << GPIO_DIRCLR_PIN26_Pos) /*!< Bit mask of PIN26 field. */ -#define GPIO_DIRCLR_PIN26_Input (0UL) /*!< Read: pin set as input */ -#define GPIO_DIRCLR_PIN26_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRCLR_PIN26_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ +#define GPIO_DIRCLR_PIN26_Input (0x0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN26_Output (0x1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN26_Clear (0x1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ /* Bit 25 : Set as input pin 25 */ #define GPIO_DIRCLR_PIN25_Pos (25UL) /*!< Position of PIN25 field. */ #define GPIO_DIRCLR_PIN25_Msk (0x1UL << GPIO_DIRCLR_PIN25_Pos) /*!< Bit mask of PIN25 field. */ -#define GPIO_DIRCLR_PIN25_Input (0UL) /*!< Read: pin set as input */ -#define GPIO_DIRCLR_PIN25_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRCLR_PIN25_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ +#define GPIO_DIRCLR_PIN25_Input (0x0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN25_Output (0x1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN25_Clear (0x1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ /* Bit 24 : Set as input pin 24 */ #define GPIO_DIRCLR_PIN24_Pos (24UL) /*!< Position of PIN24 field. */ #define GPIO_DIRCLR_PIN24_Msk (0x1UL << GPIO_DIRCLR_PIN24_Pos) /*!< Bit mask of PIN24 field. */ -#define GPIO_DIRCLR_PIN24_Input (0UL) /*!< Read: pin set as input */ -#define GPIO_DIRCLR_PIN24_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRCLR_PIN24_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ +#define GPIO_DIRCLR_PIN24_Input (0x0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN24_Output (0x1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN24_Clear (0x1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ /* Bit 23 : Set as input pin 23 */ #define GPIO_DIRCLR_PIN23_Pos (23UL) /*!< Position of PIN23 field. */ #define GPIO_DIRCLR_PIN23_Msk (0x1UL << GPIO_DIRCLR_PIN23_Pos) /*!< Bit mask of PIN23 field. */ -#define GPIO_DIRCLR_PIN23_Input (0UL) /*!< Read: pin set as input */ -#define GPIO_DIRCLR_PIN23_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRCLR_PIN23_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ +#define GPIO_DIRCLR_PIN23_Input (0x0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN23_Output (0x1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN23_Clear (0x1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ /* Bit 22 : Set as input pin 22 */ #define GPIO_DIRCLR_PIN22_Pos (22UL) /*!< Position of PIN22 field. */ #define GPIO_DIRCLR_PIN22_Msk (0x1UL << GPIO_DIRCLR_PIN22_Pos) /*!< Bit mask of PIN22 field. */ -#define GPIO_DIRCLR_PIN22_Input (0UL) /*!< Read: pin set as input */ -#define GPIO_DIRCLR_PIN22_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRCLR_PIN22_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ +#define GPIO_DIRCLR_PIN22_Input (0x0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN22_Output (0x1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN22_Clear (0x1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ /* Bit 21 : Set as input pin 21 */ #define GPIO_DIRCLR_PIN21_Pos (21UL) /*!< Position of PIN21 field. */ #define GPIO_DIRCLR_PIN21_Msk (0x1UL << GPIO_DIRCLR_PIN21_Pos) /*!< Bit mask of PIN21 field. */ -#define GPIO_DIRCLR_PIN21_Input (0UL) /*!< Read: pin set as input */ -#define GPIO_DIRCLR_PIN21_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRCLR_PIN21_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ +#define GPIO_DIRCLR_PIN21_Input (0x0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN21_Output (0x1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN21_Clear (0x1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ /* Bit 20 : Set as input pin 20 */ #define GPIO_DIRCLR_PIN20_Pos (20UL) /*!< Position of PIN20 field. */ #define GPIO_DIRCLR_PIN20_Msk (0x1UL << GPIO_DIRCLR_PIN20_Pos) /*!< Bit mask of PIN20 field. */ -#define GPIO_DIRCLR_PIN20_Input (0UL) /*!< Read: pin set as input */ -#define GPIO_DIRCLR_PIN20_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRCLR_PIN20_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ +#define GPIO_DIRCLR_PIN20_Input (0x0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN20_Output (0x1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN20_Clear (0x1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ /* Bit 19 : Set as input pin 19 */ #define GPIO_DIRCLR_PIN19_Pos (19UL) /*!< Position of PIN19 field. */ #define GPIO_DIRCLR_PIN19_Msk (0x1UL << GPIO_DIRCLR_PIN19_Pos) /*!< Bit mask of PIN19 field. */ -#define GPIO_DIRCLR_PIN19_Input (0UL) /*!< Read: pin set as input */ -#define GPIO_DIRCLR_PIN19_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRCLR_PIN19_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ +#define GPIO_DIRCLR_PIN19_Input (0x0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN19_Output (0x1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN19_Clear (0x1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ /* Bit 18 : Set as input pin 18 */ #define GPIO_DIRCLR_PIN18_Pos (18UL) /*!< Position of PIN18 field. */ #define GPIO_DIRCLR_PIN18_Msk (0x1UL << GPIO_DIRCLR_PIN18_Pos) /*!< Bit mask of PIN18 field. */ -#define GPIO_DIRCLR_PIN18_Input (0UL) /*!< Read: pin set as input */ -#define GPIO_DIRCLR_PIN18_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRCLR_PIN18_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ +#define GPIO_DIRCLR_PIN18_Input (0x0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN18_Output (0x1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN18_Clear (0x1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ /* Bit 17 : Set as input pin 17 */ #define GPIO_DIRCLR_PIN17_Pos (17UL) /*!< Position of PIN17 field. */ #define GPIO_DIRCLR_PIN17_Msk (0x1UL << GPIO_DIRCLR_PIN17_Pos) /*!< Bit mask of PIN17 field. */ -#define GPIO_DIRCLR_PIN17_Input (0UL) /*!< Read: pin set as input */ -#define GPIO_DIRCLR_PIN17_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRCLR_PIN17_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ +#define GPIO_DIRCLR_PIN17_Input (0x0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN17_Output (0x1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN17_Clear (0x1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ /* Bit 16 : Set as input pin 16 */ #define GPIO_DIRCLR_PIN16_Pos (16UL) /*!< Position of PIN16 field. */ #define GPIO_DIRCLR_PIN16_Msk (0x1UL << GPIO_DIRCLR_PIN16_Pos) /*!< Bit mask of PIN16 field. */ -#define GPIO_DIRCLR_PIN16_Input (0UL) /*!< Read: pin set as input */ -#define GPIO_DIRCLR_PIN16_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRCLR_PIN16_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ +#define GPIO_DIRCLR_PIN16_Input (0x0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN16_Output (0x1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN16_Clear (0x1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ /* Bit 15 : Set as input pin 15 */ #define GPIO_DIRCLR_PIN15_Pos (15UL) /*!< Position of PIN15 field. */ #define GPIO_DIRCLR_PIN15_Msk (0x1UL << GPIO_DIRCLR_PIN15_Pos) /*!< Bit mask of PIN15 field. */ -#define GPIO_DIRCLR_PIN15_Input (0UL) /*!< Read: pin set as input */ -#define GPIO_DIRCLR_PIN15_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRCLR_PIN15_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ +#define GPIO_DIRCLR_PIN15_Input (0x0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN15_Output (0x1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN15_Clear (0x1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ /* Bit 14 : Set as input pin 14 */ #define GPIO_DIRCLR_PIN14_Pos (14UL) /*!< Position of PIN14 field. */ #define GPIO_DIRCLR_PIN14_Msk (0x1UL << GPIO_DIRCLR_PIN14_Pos) /*!< Bit mask of PIN14 field. */ -#define GPIO_DIRCLR_PIN14_Input (0UL) /*!< Read: pin set as input */ -#define GPIO_DIRCLR_PIN14_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRCLR_PIN14_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ +#define GPIO_DIRCLR_PIN14_Input (0x0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN14_Output (0x1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN14_Clear (0x1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ /* Bit 13 : Set as input pin 13 */ #define GPIO_DIRCLR_PIN13_Pos (13UL) /*!< Position of PIN13 field. */ #define GPIO_DIRCLR_PIN13_Msk (0x1UL << GPIO_DIRCLR_PIN13_Pos) /*!< Bit mask of PIN13 field. */ -#define GPIO_DIRCLR_PIN13_Input (0UL) /*!< Read: pin set as input */ -#define GPIO_DIRCLR_PIN13_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRCLR_PIN13_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ +#define GPIO_DIRCLR_PIN13_Input (0x0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN13_Output (0x1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN13_Clear (0x1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ /* Bit 12 : Set as input pin 12 */ #define GPIO_DIRCLR_PIN12_Pos (12UL) /*!< Position of PIN12 field. */ #define GPIO_DIRCLR_PIN12_Msk (0x1UL << GPIO_DIRCLR_PIN12_Pos) /*!< Bit mask of PIN12 field. */ -#define GPIO_DIRCLR_PIN12_Input (0UL) /*!< Read: pin set as input */ -#define GPIO_DIRCLR_PIN12_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRCLR_PIN12_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ +#define GPIO_DIRCLR_PIN12_Input (0x0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN12_Output (0x1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN12_Clear (0x1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ /* Bit 11 : Set as input pin 11 */ #define GPIO_DIRCLR_PIN11_Pos (11UL) /*!< Position of PIN11 field. */ #define GPIO_DIRCLR_PIN11_Msk (0x1UL << GPIO_DIRCLR_PIN11_Pos) /*!< Bit mask of PIN11 field. */ -#define GPIO_DIRCLR_PIN11_Input (0UL) /*!< Read: pin set as input */ -#define GPIO_DIRCLR_PIN11_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRCLR_PIN11_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ +#define GPIO_DIRCLR_PIN11_Input (0x0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN11_Output (0x1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN11_Clear (0x1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ /* Bit 10 : Set as input pin 10 */ #define GPIO_DIRCLR_PIN10_Pos (10UL) /*!< Position of PIN10 field. */ #define GPIO_DIRCLR_PIN10_Msk (0x1UL << GPIO_DIRCLR_PIN10_Pos) /*!< Bit mask of PIN10 field. */ -#define GPIO_DIRCLR_PIN10_Input (0UL) /*!< Read: pin set as input */ -#define GPIO_DIRCLR_PIN10_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRCLR_PIN10_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ +#define GPIO_DIRCLR_PIN10_Input (0x0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN10_Output (0x1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN10_Clear (0x1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ /* Bit 9 : Set as input pin 9 */ #define GPIO_DIRCLR_PIN9_Pos (9UL) /*!< Position of PIN9 field. */ #define GPIO_DIRCLR_PIN9_Msk (0x1UL << GPIO_DIRCLR_PIN9_Pos) /*!< Bit mask of PIN9 field. */ -#define GPIO_DIRCLR_PIN9_Input (0UL) /*!< Read: pin set as input */ -#define GPIO_DIRCLR_PIN9_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRCLR_PIN9_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ +#define GPIO_DIRCLR_PIN9_Input (0x0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN9_Output (0x1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN9_Clear (0x1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ /* Bit 8 : Set as input pin 8 */ #define GPIO_DIRCLR_PIN8_Pos (8UL) /*!< Position of PIN8 field. */ #define GPIO_DIRCLR_PIN8_Msk (0x1UL << GPIO_DIRCLR_PIN8_Pos) /*!< Bit mask of PIN8 field. */ -#define GPIO_DIRCLR_PIN8_Input (0UL) /*!< Read: pin set as input */ -#define GPIO_DIRCLR_PIN8_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRCLR_PIN8_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ +#define GPIO_DIRCLR_PIN8_Input (0x0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN8_Output (0x1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN8_Clear (0x1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ /* Bit 7 : Set as input pin 7 */ #define GPIO_DIRCLR_PIN7_Pos (7UL) /*!< Position of PIN7 field. */ #define GPIO_DIRCLR_PIN7_Msk (0x1UL << GPIO_DIRCLR_PIN7_Pos) /*!< Bit mask of PIN7 field. */ -#define GPIO_DIRCLR_PIN7_Input (0UL) /*!< Read: pin set as input */ -#define GPIO_DIRCLR_PIN7_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRCLR_PIN7_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ +#define GPIO_DIRCLR_PIN7_Input (0x0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN7_Output (0x1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN7_Clear (0x1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ /* Bit 6 : Set as input pin 6 */ #define GPIO_DIRCLR_PIN6_Pos (6UL) /*!< Position of PIN6 field. */ #define GPIO_DIRCLR_PIN6_Msk (0x1UL << GPIO_DIRCLR_PIN6_Pos) /*!< Bit mask of PIN6 field. */ -#define GPIO_DIRCLR_PIN6_Input (0UL) /*!< Read: pin set as input */ -#define GPIO_DIRCLR_PIN6_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRCLR_PIN6_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ +#define GPIO_DIRCLR_PIN6_Input (0x0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN6_Output (0x1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN6_Clear (0x1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ /* Bit 5 : Set as input pin 5 */ #define GPIO_DIRCLR_PIN5_Pos (5UL) /*!< Position of PIN5 field. */ #define GPIO_DIRCLR_PIN5_Msk (0x1UL << GPIO_DIRCLR_PIN5_Pos) /*!< Bit mask of PIN5 field. */ -#define GPIO_DIRCLR_PIN5_Input (0UL) /*!< Read: pin set as input */ -#define GPIO_DIRCLR_PIN5_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRCLR_PIN5_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ +#define GPIO_DIRCLR_PIN5_Input (0x0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN5_Output (0x1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN5_Clear (0x1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ /* Bit 4 : Set as input pin 4 */ #define GPIO_DIRCLR_PIN4_Pos (4UL) /*!< Position of PIN4 field. */ #define GPIO_DIRCLR_PIN4_Msk (0x1UL << GPIO_DIRCLR_PIN4_Pos) /*!< Bit mask of PIN4 field. */ -#define GPIO_DIRCLR_PIN4_Input (0UL) /*!< Read: pin set as input */ -#define GPIO_DIRCLR_PIN4_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRCLR_PIN4_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ +#define GPIO_DIRCLR_PIN4_Input (0x0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN4_Output (0x1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN4_Clear (0x1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ /* Bit 3 : Set as input pin 3 */ #define GPIO_DIRCLR_PIN3_Pos (3UL) /*!< Position of PIN3 field. */ #define GPIO_DIRCLR_PIN3_Msk (0x1UL << GPIO_DIRCLR_PIN3_Pos) /*!< Bit mask of PIN3 field. */ -#define GPIO_DIRCLR_PIN3_Input (0UL) /*!< Read: pin set as input */ -#define GPIO_DIRCLR_PIN3_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRCLR_PIN3_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ +#define GPIO_DIRCLR_PIN3_Input (0x0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN3_Output (0x1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN3_Clear (0x1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ /* Bit 2 : Set as input pin 2 */ #define GPIO_DIRCLR_PIN2_Pos (2UL) /*!< Position of PIN2 field. */ #define GPIO_DIRCLR_PIN2_Msk (0x1UL << GPIO_DIRCLR_PIN2_Pos) /*!< Bit mask of PIN2 field. */ -#define GPIO_DIRCLR_PIN2_Input (0UL) /*!< Read: pin set as input */ -#define GPIO_DIRCLR_PIN2_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRCLR_PIN2_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ +#define GPIO_DIRCLR_PIN2_Input (0x0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN2_Output (0x1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN2_Clear (0x1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ /* Bit 1 : Set as input pin 1 */ #define GPIO_DIRCLR_PIN1_Pos (1UL) /*!< Position of PIN1 field. */ #define GPIO_DIRCLR_PIN1_Msk (0x1UL << GPIO_DIRCLR_PIN1_Pos) /*!< Bit mask of PIN1 field. */ -#define GPIO_DIRCLR_PIN1_Input (0UL) /*!< Read: pin set as input */ -#define GPIO_DIRCLR_PIN1_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRCLR_PIN1_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ +#define GPIO_DIRCLR_PIN1_Input (0x0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN1_Output (0x1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN1_Clear (0x1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ /* Bit 0 : Set as input pin 0 */ #define GPIO_DIRCLR_PIN0_Pos (0UL) /*!< Position of PIN0 field. */ #define GPIO_DIRCLR_PIN0_Msk (0x1UL << GPIO_DIRCLR_PIN0_Pos) /*!< Bit mask of PIN0 field. */ -#define GPIO_DIRCLR_PIN0_Input (0UL) /*!< Read: pin set as input */ -#define GPIO_DIRCLR_PIN0_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRCLR_PIN0_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ +#define GPIO_DIRCLR_PIN0_Input (0x0UL) /*!< Read: pin set as input */ +#define GPIO_DIRCLR_PIN0_Output (0x1UL) /*!< Read: pin set as output */ +#define GPIO_DIRCLR_PIN0_Clear (0x1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ /* Register: GPIO_LATCH */ /* Description: Latch register indicating what GPIO pins that have met the criteria set in the PIN_CNF[n].SENSE registers */ @@ -4283,194 +4283,194 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 31 : Status on whether PIN[31] has met criteria set in PIN_CNF[31].SENSE register. Write '1' to clear. */ #define GPIO_LATCH_PIN31_Pos (31UL) /*!< Position of PIN31 field. */ #define GPIO_LATCH_PIN31_Msk (0x1UL << GPIO_LATCH_PIN31_Pos) /*!< Bit mask of PIN31 field. */ -#define GPIO_LATCH_PIN31_NotLatched (0UL) /*!< Criteria has not been met */ -#define GPIO_LATCH_PIN31_Latched (1UL) /*!< Criteria has been met */ +#define GPIO_LATCH_PIN31_NotLatched (0x0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN31_Latched (0x1UL) /*!< Criteria has been met */ /* Bit 30 : Status on whether PIN[30] has met criteria set in PIN_CNF[30].SENSE register. Write '1' to clear. */ #define GPIO_LATCH_PIN30_Pos (30UL) /*!< Position of PIN30 field. */ #define GPIO_LATCH_PIN30_Msk (0x1UL << GPIO_LATCH_PIN30_Pos) /*!< Bit mask of PIN30 field. */ -#define GPIO_LATCH_PIN30_NotLatched (0UL) /*!< Criteria has not been met */ -#define GPIO_LATCH_PIN30_Latched (1UL) /*!< Criteria has been met */ +#define GPIO_LATCH_PIN30_NotLatched (0x0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN30_Latched (0x1UL) /*!< Criteria has been met */ /* Bit 29 : Status on whether PIN[29] has met criteria set in PIN_CNF[29].SENSE register. Write '1' to clear. */ #define GPIO_LATCH_PIN29_Pos (29UL) /*!< Position of PIN29 field. */ #define GPIO_LATCH_PIN29_Msk (0x1UL << GPIO_LATCH_PIN29_Pos) /*!< Bit mask of PIN29 field. */ -#define GPIO_LATCH_PIN29_NotLatched (0UL) /*!< Criteria has not been met */ -#define GPIO_LATCH_PIN29_Latched (1UL) /*!< Criteria has been met */ +#define GPIO_LATCH_PIN29_NotLatched (0x0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN29_Latched (0x1UL) /*!< Criteria has been met */ /* Bit 28 : Status on whether PIN[28] has met criteria set in PIN_CNF[28].SENSE register. Write '1' to clear. */ #define GPIO_LATCH_PIN28_Pos (28UL) /*!< Position of PIN28 field. */ #define GPIO_LATCH_PIN28_Msk (0x1UL << GPIO_LATCH_PIN28_Pos) /*!< Bit mask of PIN28 field. */ -#define GPIO_LATCH_PIN28_NotLatched (0UL) /*!< Criteria has not been met */ -#define GPIO_LATCH_PIN28_Latched (1UL) /*!< Criteria has been met */ +#define GPIO_LATCH_PIN28_NotLatched (0x0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN28_Latched (0x1UL) /*!< Criteria has been met */ /* Bit 27 : Status on whether PIN[27] has met criteria set in PIN_CNF[27].SENSE register. Write '1' to clear. */ #define GPIO_LATCH_PIN27_Pos (27UL) /*!< Position of PIN27 field. */ #define GPIO_LATCH_PIN27_Msk (0x1UL << GPIO_LATCH_PIN27_Pos) /*!< Bit mask of PIN27 field. */ -#define GPIO_LATCH_PIN27_NotLatched (0UL) /*!< Criteria has not been met */ -#define GPIO_LATCH_PIN27_Latched (1UL) /*!< Criteria has been met */ +#define GPIO_LATCH_PIN27_NotLatched (0x0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN27_Latched (0x1UL) /*!< Criteria has been met */ /* Bit 26 : Status on whether PIN[26] has met criteria set in PIN_CNF[26].SENSE register. Write '1' to clear. */ #define GPIO_LATCH_PIN26_Pos (26UL) /*!< Position of PIN26 field. */ #define GPIO_LATCH_PIN26_Msk (0x1UL << GPIO_LATCH_PIN26_Pos) /*!< Bit mask of PIN26 field. */ -#define GPIO_LATCH_PIN26_NotLatched (0UL) /*!< Criteria has not been met */ -#define GPIO_LATCH_PIN26_Latched (1UL) /*!< Criteria has been met */ +#define GPIO_LATCH_PIN26_NotLatched (0x0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN26_Latched (0x1UL) /*!< Criteria has been met */ /* Bit 25 : Status on whether PIN[25] has met criteria set in PIN_CNF[25].SENSE register. Write '1' to clear. */ #define GPIO_LATCH_PIN25_Pos (25UL) /*!< Position of PIN25 field. */ #define GPIO_LATCH_PIN25_Msk (0x1UL << GPIO_LATCH_PIN25_Pos) /*!< Bit mask of PIN25 field. */ -#define GPIO_LATCH_PIN25_NotLatched (0UL) /*!< Criteria has not been met */ -#define GPIO_LATCH_PIN25_Latched (1UL) /*!< Criteria has been met */ +#define GPIO_LATCH_PIN25_NotLatched (0x0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN25_Latched (0x1UL) /*!< Criteria has been met */ /* Bit 24 : Status on whether PIN[24] has met criteria set in PIN_CNF[24].SENSE register. Write '1' to clear. */ #define GPIO_LATCH_PIN24_Pos (24UL) /*!< Position of PIN24 field. */ #define GPIO_LATCH_PIN24_Msk (0x1UL << GPIO_LATCH_PIN24_Pos) /*!< Bit mask of PIN24 field. */ -#define GPIO_LATCH_PIN24_NotLatched (0UL) /*!< Criteria has not been met */ -#define GPIO_LATCH_PIN24_Latched (1UL) /*!< Criteria has been met */ +#define GPIO_LATCH_PIN24_NotLatched (0x0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN24_Latched (0x1UL) /*!< Criteria has been met */ /* Bit 23 : Status on whether PIN[23] has met criteria set in PIN_CNF[23].SENSE register. Write '1' to clear. */ #define GPIO_LATCH_PIN23_Pos (23UL) /*!< Position of PIN23 field. */ #define GPIO_LATCH_PIN23_Msk (0x1UL << GPIO_LATCH_PIN23_Pos) /*!< Bit mask of PIN23 field. */ -#define GPIO_LATCH_PIN23_NotLatched (0UL) /*!< Criteria has not been met */ -#define GPIO_LATCH_PIN23_Latched (1UL) /*!< Criteria has been met */ +#define GPIO_LATCH_PIN23_NotLatched (0x0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN23_Latched (0x1UL) /*!< Criteria has been met */ /* Bit 22 : Status on whether PIN[22] has met criteria set in PIN_CNF[22].SENSE register. Write '1' to clear. */ #define GPIO_LATCH_PIN22_Pos (22UL) /*!< Position of PIN22 field. */ #define GPIO_LATCH_PIN22_Msk (0x1UL << GPIO_LATCH_PIN22_Pos) /*!< Bit mask of PIN22 field. */ -#define GPIO_LATCH_PIN22_NotLatched (0UL) /*!< Criteria has not been met */ -#define GPIO_LATCH_PIN22_Latched (1UL) /*!< Criteria has been met */ +#define GPIO_LATCH_PIN22_NotLatched (0x0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN22_Latched (0x1UL) /*!< Criteria has been met */ /* Bit 21 : Status on whether PIN[21] has met criteria set in PIN_CNF[21].SENSE register. Write '1' to clear. */ #define GPIO_LATCH_PIN21_Pos (21UL) /*!< Position of PIN21 field. */ #define GPIO_LATCH_PIN21_Msk (0x1UL << GPIO_LATCH_PIN21_Pos) /*!< Bit mask of PIN21 field. */ -#define GPIO_LATCH_PIN21_NotLatched (0UL) /*!< Criteria has not been met */ -#define GPIO_LATCH_PIN21_Latched (1UL) /*!< Criteria has been met */ +#define GPIO_LATCH_PIN21_NotLatched (0x0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN21_Latched (0x1UL) /*!< Criteria has been met */ /* Bit 20 : Status on whether PIN[20] has met criteria set in PIN_CNF[20].SENSE register. Write '1' to clear. */ #define GPIO_LATCH_PIN20_Pos (20UL) /*!< Position of PIN20 field. */ #define GPIO_LATCH_PIN20_Msk (0x1UL << GPIO_LATCH_PIN20_Pos) /*!< Bit mask of PIN20 field. */ -#define GPIO_LATCH_PIN20_NotLatched (0UL) /*!< Criteria has not been met */ -#define GPIO_LATCH_PIN20_Latched (1UL) /*!< Criteria has been met */ +#define GPIO_LATCH_PIN20_NotLatched (0x0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN20_Latched (0x1UL) /*!< Criteria has been met */ /* Bit 19 : Status on whether PIN[19] has met criteria set in PIN_CNF[19].SENSE register. Write '1' to clear. */ #define GPIO_LATCH_PIN19_Pos (19UL) /*!< Position of PIN19 field. */ #define GPIO_LATCH_PIN19_Msk (0x1UL << GPIO_LATCH_PIN19_Pos) /*!< Bit mask of PIN19 field. */ -#define GPIO_LATCH_PIN19_NotLatched (0UL) /*!< Criteria has not been met */ -#define GPIO_LATCH_PIN19_Latched (1UL) /*!< Criteria has been met */ +#define GPIO_LATCH_PIN19_NotLatched (0x0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN19_Latched (0x1UL) /*!< Criteria has been met */ /* Bit 18 : Status on whether PIN[18] has met criteria set in PIN_CNF[18].SENSE register. Write '1' to clear. */ #define GPIO_LATCH_PIN18_Pos (18UL) /*!< Position of PIN18 field. */ #define GPIO_LATCH_PIN18_Msk (0x1UL << GPIO_LATCH_PIN18_Pos) /*!< Bit mask of PIN18 field. */ -#define GPIO_LATCH_PIN18_NotLatched (0UL) /*!< Criteria has not been met */ -#define GPIO_LATCH_PIN18_Latched (1UL) /*!< Criteria has been met */ +#define GPIO_LATCH_PIN18_NotLatched (0x0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN18_Latched (0x1UL) /*!< Criteria has been met */ /* Bit 17 : Status on whether PIN[17] has met criteria set in PIN_CNF[17].SENSE register. Write '1' to clear. */ #define GPIO_LATCH_PIN17_Pos (17UL) /*!< Position of PIN17 field. */ #define GPIO_LATCH_PIN17_Msk (0x1UL << GPIO_LATCH_PIN17_Pos) /*!< Bit mask of PIN17 field. */ -#define GPIO_LATCH_PIN17_NotLatched (0UL) /*!< Criteria has not been met */ -#define GPIO_LATCH_PIN17_Latched (1UL) /*!< Criteria has been met */ +#define GPIO_LATCH_PIN17_NotLatched (0x0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN17_Latched (0x1UL) /*!< Criteria has been met */ /* Bit 16 : Status on whether PIN[16] has met criteria set in PIN_CNF[16].SENSE register. Write '1' to clear. */ #define GPIO_LATCH_PIN16_Pos (16UL) /*!< Position of PIN16 field. */ #define GPIO_LATCH_PIN16_Msk (0x1UL << GPIO_LATCH_PIN16_Pos) /*!< Bit mask of PIN16 field. */ -#define GPIO_LATCH_PIN16_NotLatched (0UL) /*!< Criteria has not been met */ -#define GPIO_LATCH_PIN16_Latched (1UL) /*!< Criteria has been met */ +#define GPIO_LATCH_PIN16_NotLatched (0x0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN16_Latched (0x1UL) /*!< Criteria has been met */ /* Bit 15 : Status on whether PIN[15] has met criteria set in PIN_CNF[15].SENSE register. Write '1' to clear. */ #define GPIO_LATCH_PIN15_Pos (15UL) /*!< Position of PIN15 field. */ #define GPIO_LATCH_PIN15_Msk (0x1UL << GPIO_LATCH_PIN15_Pos) /*!< Bit mask of PIN15 field. */ -#define GPIO_LATCH_PIN15_NotLatched (0UL) /*!< Criteria has not been met */ -#define GPIO_LATCH_PIN15_Latched (1UL) /*!< Criteria has been met */ +#define GPIO_LATCH_PIN15_NotLatched (0x0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN15_Latched (0x1UL) /*!< Criteria has been met */ /* Bit 14 : Status on whether PIN[14] has met criteria set in PIN_CNF[14].SENSE register. Write '1' to clear. */ #define GPIO_LATCH_PIN14_Pos (14UL) /*!< Position of PIN14 field. */ #define GPIO_LATCH_PIN14_Msk (0x1UL << GPIO_LATCH_PIN14_Pos) /*!< Bit mask of PIN14 field. */ -#define GPIO_LATCH_PIN14_NotLatched (0UL) /*!< Criteria has not been met */ -#define GPIO_LATCH_PIN14_Latched (1UL) /*!< Criteria has been met */ +#define GPIO_LATCH_PIN14_NotLatched (0x0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN14_Latched (0x1UL) /*!< Criteria has been met */ /* Bit 13 : Status on whether PIN[13] has met criteria set in PIN_CNF[13].SENSE register. Write '1' to clear. */ #define GPIO_LATCH_PIN13_Pos (13UL) /*!< Position of PIN13 field. */ #define GPIO_LATCH_PIN13_Msk (0x1UL << GPIO_LATCH_PIN13_Pos) /*!< Bit mask of PIN13 field. */ -#define GPIO_LATCH_PIN13_NotLatched (0UL) /*!< Criteria has not been met */ -#define GPIO_LATCH_PIN13_Latched (1UL) /*!< Criteria has been met */ +#define GPIO_LATCH_PIN13_NotLatched (0x0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN13_Latched (0x1UL) /*!< Criteria has been met */ /* Bit 12 : Status on whether PIN[12] has met criteria set in PIN_CNF[12].SENSE register. Write '1' to clear. */ #define GPIO_LATCH_PIN12_Pos (12UL) /*!< Position of PIN12 field. */ #define GPIO_LATCH_PIN12_Msk (0x1UL << GPIO_LATCH_PIN12_Pos) /*!< Bit mask of PIN12 field. */ -#define GPIO_LATCH_PIN12_NotLatched (0UL) /*!< Criteria has not been met */ -#define GPIO_LATCH_PIN12_Latched (1UL) /*!< Criteria has been met */ +#define GPIO_LATCH_PIN12_NotLatched (0x0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN12_Latched (0x1UL) /*!< Criteria has been met */ /* Bit 11 : Status on whether PIN[11] has met criteria set in PIN_CNF[11].SENSE register. Write '1' to clear. */ #define GPIO_LATCH_PIN11_Pos (11UL) /*!< Position of PIN11 field. */ #define GPIO_LATCH_PIN11_Msk (0x1UL << GPIO_LATCH_PIN11_Pos) /*!< Bit mask of PIN11 field. */ -#define GPIO_LATCH_PIN11_NotLatched (0UL) /*!< Criteria has not been met */ -#define GPIO_LATCH_PIN11_Latched (1UL) /*!< Criteria has been met */ +#define GPIO_LATCH_PIN11_NotLatched (0x0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN11_Latched (0x1UL) /*!< Criteria has been met */ /* Bit 10 : Status on whether PIN[10] has met criteria set in PIN_CNF[10].SENSE register. Write '1' to clear. */ #define GPIO_LATCH_PIN10_Pos (10UL) /*!< Position of PIN10 field. */ #define GPIO_LATCH_PIN10_Msk (0x1UL << GPIO_LATCH_PIN10_Pos) /*!< Bit mask of PIN10 field. */ -#define GPIO_LATCH_PIN10_NotLatched (0UL) /*!< Criteria has not been met */ -#define GPIO_LATCH_PIN10_Latched (1UL) /*!< Criteria has been met */ +#define GPIO_LATCH_PIN10_NotLatched (0x0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN10_Latched (0x1UL) /*!< Criteria has been met */ /* Bit 9 : Status on whether PIN[9] has met criteria set in PIN_CNF[9].SENSE register. Write '1' to clear. */ #define GPIO_LATCH_PIN9_Pos (9UL) /*!< Position of PIN9 field. */ #define GPIO_LATCH_PIN9_Msk (0x1UL << GPIO_LATCH_PIN9_Pos) /*!< Bit mask of PIN9 field. */ -#define GPIO_LATCH_PIN9_NotLatched (0UL) /*!< Criteria has not been met */ -#define GPIO_LATCH_PIN9_Latched (1UL) /*!< Criteria has been met */ +#define GPIO_LATCH_PIN9_NotLatched (0x0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN9_Latched (0x1UL) /*!< Criteria has been met */ /* Bit 8 : Status on whether PIN[8] has met criteria set in PIN_CNF[8].SENSE register. Write '1' to clear. */ #define GPIO_LATCH_PIN8_Pos (8UL) /*!< Position of PIN8 field. */ #define GPIO_LATCH_PIN8_Msk (0x1UL << GPIO_LATCH_PIN8_Pos) /*!< Bit mask of PIN8 field. */ -#define GPIO_LATCH_PIN8_NotLatched (0UL) /*!< Criteria has not been met */ -#define GPIO_LATCH_PIN8_Latched (1UL) /*!< Criteria has been met */ +#define GPIO_LATCH_PIN8_NotLatched (0x0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN8_Latched (0x1UL) /*!< Criteria has been met */ /* Bit 7 : Status on whether PIN[7] has met criteria set in PIN_CNF[7].SENSE register. Write '1' to clear. */ #define GPIO_LATCH_PIN7_Pos (7UL) /*!< Position of PIN7 field. */ #define GPIO_LATCH_PIN7_Msk (0x1UL << GPIO_LATCH_PIN7_Pos) /*!< Bit mask of PIN7 field. */ -#define GPIO_LATCH_PIN7_NotLatched (0UL) /*!< Criteria has not been met */ -#define GPIO_LATCH_PIN7_Latched (1UL) /*!< Criteria has been met */ +#define GPIO_LATCH_PIN7_NotLatched (0x0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN7_Latched (0x1UL) /*!< Criteria has been met */ /* Bit 6 : Status on whether PIN[6] has met criteria set in PIN_CNF[6].SENSE register. Write '1' to clear. */ #define GPIO_LATCH_PIN6_Pos (6UL) /*!< Position of PIN6 field. */ #define GPIO_LATCH_PIN6_Msk (0x1UL << GPIO_LATCH_PIN6_Pos) /*!< Bit mask of PIN6 field. */ -#define GPIO_LATCH_PIN6_NotLatched (0UL) /*!< Criteria has not been met */ -#define GPIO_LATCH_PIN6_Latched (1UL) /*!< Criteria has been met */ +#define GPIO_LATCH_PIN6_NotLatched (0x0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN6_Latched (0x1UL) /*!< Criteria has been met */ /* Bit 5 : Status on whether PIN[5] has met criteria set in PIN_CNF[5].SENSE register. Write '1' to clear. */ #define GPIO_LATCH_PIN5_Pos (5UL) /*!< Position of PIN5 field. */ #define GPIO_LATCH_PIN5_Msk (0x1UL << GPIO_LATCH_PIN5_Pos) /*!< Bit mask of PIN5 field. */ -#define GPIO_LATCH_PIN5_NotLatched (0UL) /*!< Criteria has not been met */ -#define GPIO_LATCH_PIN5_Latched (1UL) /*!< Criteria has been met */ +#define GPIO_LATCH_PIN5_NotLatched (0x0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN5_Latched (0x1UL) /*!< Criteria has been met */ /* Bit 4 : Status on whether PIN[4] has met criteria set in PIN_CNF[4].SENSE register. Write '1' to clear. */ #define GPIO_LATCH_PIN4_Pos (4UL) /*!< Position of PIN4 field. */ #define GPIO_LATCH_PIN4_Msk (0x1UL << GPIO_LATCH_PIN4_Pos) /*!< Bit mask of PIN4 field. */ -#define GPIO_LATCH_PIN4_NotLatched (0UL) /*!< Criteria has not been met */ -#define GPIO_LATCH_PIN4_Latched (1UL) /*!< Criteria has been met */ +#define GPIO_LATCH_PIN4_NotLatched (0x0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN4_Latched (0x1UL) /*!< Criteria has been met */ /* Bit 3 : Status on whether PIN[3] has met criteria set in PIN_CNF[3].SENSE register. Write '1' to clear. */ #define GPIO_LATCH_PIN3_Pos (3UL) /*!< Position of PIN3 field. */ #define GPIO_LATCH_PIN3_Msk (0x1UL << GPIO_LATCH_PIN3_Pos) /*!< Bit mask of PIN3 field. */ -#define GPIO_LATCH_PIN3_NotLatched (0UL) /*!< Criteria has not been met */ -#define GPIO_LATCH_PIN3_Latched (1UL) /*!< Criteria has been met */ +#define GPIO_LATCH_PIN3_NotLatched (0x0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN3_Latched (0x1UL) /*!< Criteria has been met */ /* Bit 2 : Status on whether PIN[2] has met criteria set in PIN_CNF[2].SENSE register. Write '1' to clear. */ #define GPIO_LATCH_PIN2_Pos (2UL) /*!< Position of PIN2 field. */ #define GPIO_LATCH_PIN2_Msk (0x1UL << GPIO_LATCH_PIN2_Pos) /*!< Bit mask of PIN2 field. */ -#define GPIO_LATCH_PIN2_NotLatched (0UL) /*!< Criteria has not been met */ -#define GPIO_LATCH_PIN2_Latched (1UL) /*!< Criteria has been met */ +#define GPIO_LATCH_PIN2_NotLatched (0x0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN2_Latched (0x1UL) /*!< Criteria has been met */ /* Bit 1 : Status on whether PIN[1] has met criteria set in PIN_CNF[1].SENSE register. Write '1' to clear. */ #define GPIO_LATCH_PIN1_Pos (1UL) /*!< Position of PIN1 field. */ #define GPIO_LATCH_PIN1_Msk (0x1UL << GPIO_LATCH_PIN1_Pos) /*!< Bit mask of PIN1 field. */ -#define GPIO_LATCH_PIN1_NotLatched (0UL) /*!< Criteria has not been met */ -#define GPIO_LATCH_PIN1_Latched (1UL) /*!< Criteria has been met */ +#define GPIO_LATCH_PIN1_NotLatched (0x0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN1_Latched (0x1UL) /*!< Criteria has been met */ /* Bit 0 : Status on whether PIN[0] has met criteria set in PIN_CNF[0].SENSE register. Write '1' to clear. */ #define GPIO_LATCH_PIN0_Pos (0UL) /*!< Position of PIN0 field. */ #define GPIO_LATCH_PIN0_Msk (0x1UL << GPIO_LATCH_PIN0_Pos) /*!< Bit mask of PIN0 field. */ -#define GPIO_LATCH_PIN0_NotLatched (0UL) /*!< Criteria has not been met */ -#define GPIO_LATCH_PIN0_Latched (1UL) /*!< Criteria has been met */ +#define GPIO_LATCH_PIN0_NotLatched (0x0UL) /*!< Criteria has not been met */ +#define GPIO_LATCH_PIN0_Latched (0x1UL) /*!< Criteria has been met */ /* Register: GPIO_DETECTMODE */ /* Description: Select between default DETECT signal behavior and LDETECT mode (For non-secure pin only) */ @@ -4478,8 +4478,8 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 0 : Select between default DETECT signal behavior and LDETECT mode */ #define GPIO_DETECTMODE_DETECTMODE_Pos (0UL) /*!< Position of DETECTMODE field. */ #define GPIO_DETECTMODE_DETECTMODE_Msk (0x1UL << GPIO_DETECTMODE_DETECTMODE_Pos) /*!< Bit mask of DETECTMODE field. */ -#define GPIO_DETECTMODE_DETECTMODE_Default (0UL) /*!< DETECT directly connected to PIN DETECT signals */ -#define GPIO_DETECTMODE_DETECTMODE_LDETECT (1UL) /*!< Use the latched LDETECT behavior */ +#define GPIO_DETECTMODE_DETECTMODE_Default (0x0UL) /*!< DETECT directly connected to PIN DETECT signals */ +#define GPIO_DETECTMODE_DETECTMODE_LDETECT (0x1UL) /*!< Use the latched LDETECT behavior */ /* Register: GPIO_DETECTMODE_SEC */ /* Description: Select between default DETECT signal behavior and LDETECT mode (For secure pin only) */ @@ -4487,8 +4487,8 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 0 : Select between default DETECT signal behavior and LDETECT mode */ #define GPIO_DETECTMODE_SEC_DETECTMODE_Pos (0UL) /*!< Position of DETECTMODE field. */ #define GPIO_DETECTMODE_SEC_DETECTMODE_Msk (0x1UL << GPIO_DETECTMODE_SEC_DETECTMODE_Pos) /*!< Bit mask of DETECTMODE field. */ -#define GPIO_DETECTMODE_SEC_DETECTMODE_Default (0UL) /*!< DETECT directly connected to PIN DETECT signals */ -#define GPIO_DETECTMODE_SEC_DETECTMODE_LDETECT (1UL) /*!< Use the latched LDETECT behavior */ +#define GPIO_DETECTMODE_SEC_DETECTMODE_Default (0x0UL) /*!< DETECT directly connected to PIN DETECT signals */ +#define GPIO_DETECTMODE_SEC_DETECTMODE_LDETECT (0x1UL) /*!< Use the latched LDETECT behavior */ /* Register: GPIO_PIN_CNF */ /* Description: Description collection: Configuration of GPIO pins */ @@ -4496,40 +4496,40 @@ POSSIBILITY OF SUCH DAMAGE. /* Bits 17..16 : Pin sensing mechanism */ #define GPIO_PIN_CNF_SENSE_Pos (16UL) /*!< Position of SENSE field. */ #define GPIO_PIN_CNF_SENSE_Msk (0x3UL << GPIO_PIN_CNF_SENSE_Pos) /*!< Bit mask of SENSE field. */ -#define GPIO_PIN_CNF_SENSE_Disabled (0UL) /*!< Disabled */ -#define GPIO_PIN_CNF_SENSE_High (2UL) /*!< Sense for high level */ -#define GPIO_PIN_CNF_SENSE_Low (3UL) /*!< Sense for low level */ +#define GPIO_PIN_CNF_SENSE_Disabled (0x0UL) /*!< Disabled */ +#define GPIO_PIN_CNF_SENSE_High (0x2UL) /*!< Sense for high level */ +#define GPIO_PIN_CNF_SENSE_Low (0x3UL) /*!< Sense for low level */ /* Bits 10..8 : Drive configuration */ #define GPIO_PIN_CNF_DRIVE_Pos (8UL) /*!< Position of DRIVE field. */ #define GPIO_PIN_CNF_DRIVE_Msk (0x7UL << GPIO_PIN_CNF_DRIVE_Pos) /*!< Bit mask of DRIVE field. */ -#define GPIO_PIN_CNF_DRIVE_S0S1 (0UL) /*!< Standard '0', standard '1' */ -#define GPIO_PIN_CNF_DRIVE_H0S1 (1UL) /*!< High drive '0', standard '1' */ -#define GPIO_PIN_CNF_DRIVE_S0H1 (2UL) /*!< Standard '0', high drive '1' */ -#define GPIO_PIN_CNF_DRIVE_H0H1 (3UL) /*!< High drive '0', high 'drive '1'' */ -#define GPIO_PIN_CNF_DRIVE_D0S1 (4UL) /*!< Disconnect '0', standard '1' (normally used for wired-or connections) */ -#define GPIO_PIN_CNF_DRIVE_D0H1 (5UL) /*!< Disconnect '0', high drive '1' (normally used for wired-or connections) */ -#define GPIO_PIN_CNF_DRIVE_S0D1 (6UL) /*!< Standard '0', disconnect '1' (normally used for wired-and connections) */ -#define GPIO_PIN_CNF_DRIVE_H0D1 (7UL) /*!< High drive '0', disconnect '1' (normally used for wired-and connections) */ +#define GPIO_PIN_CNF_DRIVE_S0S1 (0x0UL) /*!< Standard '0', standard '1' */ +#define GPIO_PIN_CNF_DRIVE_H0S1 (0x1UL) /*!< High drive '0', standard '1' */ +#define GPIO_PIN_CNF_DRIVE_S0H1 (0x2UL) /*!< Standard '0', high drive '1' */ +#define GPIO_PIN_CNF_DRIVE_H0H1 (0x3UL) /*!< High drive '0', high 'drive '1'' */ +#define GPIO_PIN_CNF_DRIVE_D0S1 (0x4UL) /*!< Disconnect '0', standard '1' (normally used for wired-or connections) */ +#define GPIO_PIN_CNF_DRIVE_D0H1 (0x5UL) /*!< Disconnect '0', high drive '1' (normally used for wired-or connections) */ +#define GPIO_PIN_CNF_DRIVE_S0D1 (0x6UL) /*!< Standard '0', disconnect '1' (normally used for wired-and connections) */ +#define GPIO_PIN_CNF_DRIVE_H0D1 (0x7UL) /*!< High drive '0', disconnect '1' (normally used for wired-and connections) */ /* Bits 3..2 : Pull configuration */ #define GPIO_PIN_CNF_PULL_Pos (2UL) /*!< Position of PULL field. */ #define GPIO_PIN_CNF_PULL_Msk (0x3UL << GPIO_PIN_CNF_PULL_Pos) /*!< Bit mask of PULL field. */ -#define GPIO_PIN_CNF_PULL_Disabled (0UL) /*!< No pull */ -#define GPIO_PIN_CNF_PULL_Pulldown (1UL) /*!< Pull down on pin */ -#define GPIO_PIN_CNF_PULL_Pullup (3UL) /*!< Pull up on pin */ +#define GPIO_PIN_CNF_PULL_Disabled (0x0UL) /*!< No pull */ +#define GPIO_PIN_CNF_PULL_Pulldown (0x1UL) /*!< Pull down on pin */ +#define GPIO_PIN_CNF_PULL_Pullup (0x3UL) /*!< Pull up on pin */ /* Bit 1 : Connect or disconnect input buffer */ #define GPIO_PIN_CNF_INPUT_Pos (1UL) /*!< Position of INPUT field. */ #define GPIO_PIN_CNF_INPUT_Msk (0x1UL << GPIO_PIN_CNF_INPUT_Pos) /*!< Bit mask of INPUT field. */ -#define GPIO_PIN_CNF_INPUT_Connect (0UL) /*!< Connect input buffer */ -#define GPIO_PIN_CNF_INPUT_Disconnect (1UL) /*!< Disconnect input buffer */ +#define GPIO_PIN_CNF_INPUT_Connect (0x0UL) /*!< Connect input buffer */ +#define GPIO_PIN_CNF_INPUT_Disconnect (0x1UL) /*!< Disconnect input buffer */ /* Bit 0 : Pin direction. Same physical register as DIR register */ #define GPIO_PIN_CNF_DIR_Pos (0UL) /*!< Position of DIR field. */ #define GPIO_PIN_CNF_DIR_Msk (0x1UL << GPIO_PIN_CNF_DIR_Pos) /*!< Bit mask of DIR field. */ -#define GPIO_PIN_CNF_DIR_Input (0UL) /*!< Configure pin as an input pin */ -#define GPIO_PIN_CNF_DIR_Output (1UL) /*!< Configure pin as an output pin */ +#define GPIO_PIN_CNF_DIR_Input (0x0UL) /*!< Configure pin as an input pin */ +#define GPIO_PIN_CNF_DIR_Output (0x1UL) /*!< Configure pin as an output pin */ /* Peripheral: PDM */ @@ -4541,7 +4541,7 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 0 : Starts continuous PDM transfer */ #define PDM_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */ #define PDM_TASKS_START_TASKS_START_Msk (0x1UL << PDM_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */ -#define PDM_TASKS_START_TASKS_START_Trigger (1UL) /*!< Trigger task */ +#define PDM_TASKS_START_TASKS_START_Trigger (0x1UL) /*!< Trigger task */ /* Register: PDM_TASKS_STOP */ /* Description: Stops PDM transfer */ @@ -4549,7 +4549,7 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 0 : Stops PDM transfer */ #define PDM_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */ #define PDM_TASKS_STOP_TASKS_STOP_Msk (0x1UL << PDM_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */ -#define PDM_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */ +#define PDM_TASKS_STOP_TASKS_STOP_Trigger (0x1UL) /*!< Trigger task */ /* Register: PDM_SUBSCRIBE_START */ /* Description: Subscribe configuration for task START */ @@ -4557,8 +4557,8 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 31 : */ #define PDM_SUBSCRIBE_START_EN_Pos (31UL) /*!< Position of EN field. */ #define PDM_SUBSCRIBE_START_EN_Msk (0x1UL << PDM_SUBSCRIBE_START_EN_Pos) /*!< Bit mask of EN field. */ -#define PDM_SUBSCRIBE_START_EN_Disabled (0UL) /*!< Disable subscription */ -#define PDM_SUBSCRIBE_START_EN_Enabled (1UL) /*!< Enable subscription */ +#define PDM_SUBSCRIBE_START_EN_Disabled (0x0UL) /*!< Disable subscription */ +#define PDM_SUBSCRIBE_START_EN_Enabled (0x1UL) /*!< Enable subscription */ /* Bits 7..0 : DPPI channel that task START will subscribe to */ #define PDM_SUBSCRIBE_START_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ @@ -4570,8 +4570,8 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 31 : */ #define PDM_SUBSCRIBE_STOP_EN_Pos (31UL) /*!< Position of EN field. */ #define PDM_SUBSCRIBE_STOP_EN_Msk (0x1UL << PDM_SUBSCRIBE_STOP_EN_Pos) /*!< Bit mask of EN field. */ -#define PDM_SUBSCRIBE_STOP_EN_Disabled (0UL) /*!< Disable subscription */ -#define PDM_SUBSCRIBE_STOP_EN_Enabled (1UL) /*!< Enable subscription */ +#define PDM_SUBSCRIBE_STOP_EN_Disabled (0x0UL) /*!< Disable subscription */ +#define PDM_SUBSCRIBE_STOP_EN_Enabled (0x1UL) /*!< Enable subscription */ /* Bits 7..0 : DPPI channel that task STOP will subscribe to */ #define PDM_SUBSCRIBE_STOP_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ @@ -4583,8 +4583,8 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 0 : PDM transfer has started */ #define PDM_EVENTS_STARTED_EVENTS_STARTED_Pos (0UL) /*!< Position of EVENTS_STARTED field. */ #define PDM_EVENTS_STARTED_EVENTS_STARTED_Msk (0x1UL << PDM_EVENTS_STARTED_EVENTS_STARTED_Pos) /*!< Bit mask of EVENTS_STARTED field. */ -#define PDM_EVENTS_STARTED_EVENTS_STARTED_NotGenerated (0UL) /*!< Event not generated */ -#define PDM_EVENTS_STARTED_EVENTS_STARTED_Generated (1UL) /*!< Event generated */ +#define PDM_EVENTS_STARTED_EVENTS_STARTED_NotGenerated (0x0UL) /*!< Event not generated */ +#define PDM_EVENTS_STARTED_EVENTS_STARTED_Generated (0x1UL) /*!< Event generated */ /* Register: PDM_EVENTS_STOPPED */ /* Description: PDM transfer has finished */ @@ -4592,8 +4592,8 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 0 : PDM transfer has finished */ #define PDM_EVENTS_STOPPED_EVENTS_STOPPED_Pos (0UL) /*!< Position of EVENTS_STOPPED field. */ #define PDM_EVENTS_STOPPED_EVENTS_STOPPED_Msk (0x1UL << PDM_EVENTS_STOPPED_EVENTS_STOPPED_Pos) /*!< Bit mask of EVENTS_STOPPED field. */ -#define PDM_EVENTS_STOPPED_EVENTS_STOPPED_NotGenerated (0UL) /*!< Event not generated */ -#define PDM_EVENTS_STOPPED_EVENTS_STOPPED_Generated (1UL) /*!< Event generated */ +#define PDM_EVENTS_STOPPED_EVENTS_STOPPED_NotGenerated (0x0UL) /*!< Event not generated */ +#define PDM_EVENTS_STOPPED_EVENTS_STOPPED_Generated (0x1UL) /*!< Event generated */ /* Register: PDM_EVENTS_END */ /* Description: The PDM has written the last sample specified by SAMPLE.MAXCNT (or the last sample after a STOP task has been received) to Data RAM */ @@ -4601,8 +4601,8 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 0 : The PDM has written the last sample specified by SAMPLE.MAXCNT (or the last sample after a STOP task has been received) to Data RAM */ #define PDM_EVENTS_END_EVENTS_END_Pos (0UL) /*!< Position of EVENTS_END field. */ #define PDM_EVENTS_END_EVENTS_END_Msk (0x1UL << PDM_EVENTS_END_EVENTS_END_Pos) /*!< Bit mask of EVENTS_END field. */ -#define PDM_EVENTS_END_EVENTS_END_NotGenerated (0UL) /*!< Event not generated */ -#define PDM_EVENTS_END_EVENTS_END_Generated (1UL) /*!< Event generated */ +#define PDM_EVENTS_END_EVENTS_END_NotGenerated (0x0UL) /*!< Event not generated */ +#define PDM_EVENTS_END_EVENTS_END_Generated (0x1UL) /*!< Event generated */ /* Register: PDM_PUBLISH_STARTED */ /* Description: Publish configuration for event STARTED */ @@ -4610,8 +4610,8 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 31 : */ #define PDM_PUBLISH_STARTED_EN_Pos (31UL) /*!< Position of EN field. */ #define PDM_PUBLISH_STARTED_EN_Msk (0x1UL << PDM_PUBLISH_STARTED_EN_Pos) /*!< Bit mask of EN field. */ -#define PDM_PUBLISH_STARTED_EN_Disabled (0UL) /*!< Disable publishing */ -#define PDM_PUBLISH_STARTED_EN_Enabled (1UL) /*!< Enable publishing */ +#define PDM_PUBLISH_STARTED_EN_Disabled (0x0UL) /*!< Disable publishing */ +#define PDM_PUBLISH_STARTED_EN_Enabled (0x1UL) /*!< Enable publishing */ /* Bits 7..0 : DPPI channel that event STARTED will publish to */ #define PDM_PUBLISH_STARTED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ @@ -4623,8 +4623,8 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 31 : */ #define PDM_PUBLISH_STOPPED_EN_Pos (31UL) /*!< Position of EN field. */ #define PDM_PUBLISH_STOPPED_EN_Msk (0x1UL << PDM_PUBLISH_STOPPED_EN_Pos) /*!< Bit mask of EN field. */ -#define PDM_PUBLISH_STOPPED_EN_Disabled (0UL) /*!< Disable publishing */ -#define PDM_PUBLISH_STOPPED_EN_Enabled (1UL) /*!< Enable publishing */ +#define PDM_PUBLISH_STOPPED_EN_Disabled (0x0UL) /*!< Disable publishing */ +#define PDM_PUBLISH_STOPPED_EN_Enabled (0x1UL) /*!< Enable publishing */ /* Bits 7..0 : DPPI channel that event STOPPED will publish to */ #define PDM_PUBLISH_STOPPED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ @@ -4636,8 +4636,8 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 31 : */ #define PDM_PUBLISH_END_EN_Pos (31UL) /*!< Position of EN field. */ #define PDM_PUBLISH_END_EN_Msk (0x1UL << PDM_PUBLISH_END_EN_Pos) /*!< Bit mask of EN field. */ -#define PDM_PUBLISH_END_EN_Disabled (0UL) /*!< Disable publishing */ -#define PDM_PUBLISH_END_EN_Enabled (1UL) /*!< Enable publishing */ +#define PDM_PUBLISH_END_EN_Disabled (0x0UL) /*!< Disable publishing */ +#define PDM_PUBLISH_END_EN_Enabled (0x1UL) /*!< Enable publishing */ /* Bits 7..0 : DPPI channel that event END will publish to */ #define PDM_PUBLISH_END_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ @@ -4649,20 +4649,20 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 2 : Enable or disable interrupt for event END */ #define PDM_INTEN_END_Pos (2UL) /*!< Position of END field. */ #define PDM_INTEN_END_Msk (0x1UL << PDM_INTEN_END_Pos) /*!< Bit mask of END field. */ -#define PDM_INTEN_END_Disabled (0UL) /*!< Disable */ -#define PDM_INTEN_END_Enabled (1UL) /*!< Enable */ +#define PDM_INTEN_END_Disabled (0x0UL) /*!< Disable */ +#define PDM_INTEN_END_Enabled (0x1UL) /*!< Enable */ /* Bit 1 : Enable or disable interrupt for event STOPPED */ #define PDM_INTEN_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ #define PDM_INTEN_STOPPED_Msk (0x1UL << PDM_INTEN_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ -#define PDM_INTEN_STOPPED_Disabled (0UL) /*!< Disable */ -#define PDM_INTEN_STOPPED_Enabled (1UL) /*!< Enable */ +#define PDM_INTEN_STOPPED_Disabled (0x0UL) /*!< Disable */ +#define PDM_INTEN_STOPPED_Enabled (0x1UL) /*!< Enable */ /* Bit 0 : Enable or disable interrupt for event STARTED */ #define PDM_INTEN_STARTED_Pos (0UL) /*!< Position of STARTED field. */ #define PDM_INTEN_STARTED_Msk (0x1UL << PDM_INTEN_STARTED_Pos) /*!< Bit mask of STARTED field. */ -#define PDM_INTEN_STARTED_Disabled (0UL) /*!< Disable */ -#define PDM_INTEN_STARTED_Enabled (1UL) /*!< Enable */ +#define PDM_INTEN_STARTED_Disabled (0x0UL) /*!< Disable */ +#define PDM_INTEN_STARTED_Enabled (0x1UL) /*!< Enable */ /* Register: PDM_INTENSET */ /* Description: Enable interrupt */ @@ -4670,23 +4670,23 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 2 : Write '1' to enable interrupt for event END */ #define PDM_INTENSET_END_Pos (2UL) /*!< Position of END field. */ #define PDM_INTENSET_END_Msk (0x1UL << PDM_INTENSET_END_Pos) /*!< Bit mask of END field. */ -#define PDM_INTENSET_END_Disabled (0UL) /*!< Read: Disabled */ -#define PDM_INTENSET_END_Enabled (1UL) /*!< Read: Enabled */ -#define PDM_INTENSET_END_Set (1UL) /*!< Enable */ +#define PDM_INTENSET_END_Disabled (0x0UL) /*!< Read: Disabled */ +#define PDM_INTENSET_END_Enabled (0x1UL) /*!< Read: Enabled */ +#define PDM_INTENSET_END_Set (0x1UL) /*!< Enable */ /* Bit 1 : Write '1' to enable interrupt for event STOPPED */ #define PDM_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ #define PDM_INTENSET_STOPPED_Msk (0x1UL << PDM_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ -#define PDM_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */ -#define PDM_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */ -#define PDM_INTENSET_STOPPED_Set (1UL) /*!< Enable */ +#define PDM_INTENSET_STOPPED_Disabled (0x0UL) /*!< Read: Disabled */ +#define PDM_INTENSET_STOPPED_Enabled (0x1UL) /*!< Read: Enabled */ +#define PDM_INTENSET_STOPPED_Set (0x1UL) /*!< Enable */ /* Bit 0 : Write '1' to enable interrupt for event STARTED */ #define PDM_INTENSET_STARTED_Pos (0UL) /*!< Position of STARTED field. */ #define PDM_INTENSET_STARTED_Msk (0x1UL << PDM_INTENSET_STARTED_Pos) /*!< Bit mask of STARTED field. */ -#define PDM_INTENSET_STARTED_Disabled (0UL) /*!< Read: Disabled */ -#define PDM_INTENSET_STARTED_Enabled (1UL) /*!< Read: Enabled */ -#define PDM_INTENSET_STARTED_Set (1UL) /*!< Enable */ +#define PDM_INTENSET_STARTED_Disabled (0x0UL) /*!< Read: Disabled */ +#define PDM_INTENSET_STARTED_Enabled (0x1UL) /*!< Read: Enabled */ +#define PDM_INTENSET_STARTED_Set (0x1UL) /*!< Enable */ /* Register: PDM_INTENCLR */ /* Description: Disable interrupt */ @@ -4694,23 +4694,23 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 2 : Write '1' to disable interrupt for event END */ #define PDM_INTENCLR_END_Pos (2UL) /*!< Position of END field. */ #define PDM_INTENCLR_END_Msk (0x1UL << PDM_INTENCLR_END_Pos) /*!< Bit mask of END field. */ -#define PDM_INTENCLR_END_Disabled (0UL) /*!< Read: Disabled */ -#define PDM_INTENCLR_END_Enabled (1UL) /*!< Read: Enabled */ -#define PDM_INTENCLR_END_Clear (1UL) /*!< Disable */ +#define PDM_INTENCLR_END_Disabled (0x0UL) /*!< Read: Disabled */ +#define PDM_INTENCLR_END_Enabled (0x1UL) /*!< Read: Enabled */ +#define PDM_INTENCLR_END_Clear (0x1UL) /*!< Disable */ /* Bit 1 : Write '1' to disable interrupt for event STOPPED */ #define PDM_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ #define PDM_INTENCLR_STOPPED_Msk (0x1UL << PDM_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ -#define PDM_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */ -#define PDM_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */ -#define PDM_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */ +#define PDM_INTENCLR_STOPPED_Disabled (0x0UL) /*!< Read: Disabled */ +#define PDM_INTENCLR_STOPPED_Enabled (0x1UL) /*!< Read: Enabled */ +#define PDM_INTENCLR_STOPPED_Clear (0x1UL) /*!< Disable */ /* Bit 0 : Write '1' to disable interrupt for event STARTED */ #define PDM_INTENCLR_STARTED_Pos (0UL) /*!< Position of STARTED field. */ #define PDM_INTENCLR_STARTED_Msk (0x1UL << PDM_INTENCLR_STARTED_Pos) /*!< Bit mask of STARTED field. */ -#define PDM_INTENCLR_STARTED_Disabled (0UL) /*!< Read: Disabled */ -#define PDM_INTENCLR_STARTED_Enabled (1UL) /*!< Read: Enabled */ -#define PDM_INTENCLR_STARTED_Clear (1UL) /*!< Disable */ +#define PDM_INTENCLR_STARTED_Disabled (0x0UL) /*!< Read: Disabled */ +#define PDM_INTENCLR_STARTED_Enabled (0x1UL) /*!< Read: Enabled */ +#define PDM_INTENCLR_STARTED_Clear (0x1UL) /*!< Disable */ /* Register: PDM_ENABLE */ /* Description: PDM module enable register */ @@ -4718,8 +4718,8 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 0 : Enable or disable PDM module */ #define PDM_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ #define PDM_ENABLE_ENABLE_Msk (0x1UL << PDM_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ -#define PDM_ENABLE_ENABLE_Disabled (0UL) /*!< Disable */ -#define PDM_ENABLE_ENABLE_Enabled (1UL) /*!< Enable */ +#define PDM_ENABLE_ENABLE_Disabled (0x0UL) /*!< Disable */ +#define PDM_ENABLE_ENABLE_Enabled (0x1UL) /*!< Enable */ /* Register: PDM_PDMCLKCTRL */ /* Description: PDM clock generator control */ @@ -4740,14 +4740,14 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 1 : Defines on which PDM_CLK edge left (or mono) is sampled */ #define PDM_MODE_EDGE_Pos (1UL) /*!< Position of EDGE field. */ #define PDM_MODE_EDGE_Msk (0x1UL << PDM_MODE_EDGE_Pos) /*!< Bit mask of EDGE field. */ -#define PDM_MODE_EDGE_LeftFalling (0UL) /*!< Left (or mono) is sampled on falling edge of PDM_CLK */ -#define PDM_MODE_EDGE_LeftRising (1UL) /*!< Left (or mono) is sampled on rising edge of PDM_CLK */ +#define PDM_MODE_EDGE_LeftFalling (0x0UL) /*!< Left (or mono) is sampled on falling edge of PDM_CLK */ +#define PDM_MODE_EDGE_LeftRising (0x1UL) /*!< Left (or mono) is sampled on rising edge of PDM_CLK */ /* Bit 0 : Mono or stereo operation */ #define PDM_MODE_OPERATION_Pos (0UL) /*!< Position of OPERATION field. */ #define PDM_MODE_OPERATION_Msk (0x1UL << PDM_MODE_OPERATION_Pos) /*!< Bit mask of OPERATION field. */ -#define PDM_MODE_OPERATION_Stereo (0UL) /*!< Sample and store one pair (left + right) of 16-bit samples per RAM word R=[31:16]; L=[15:0] */ -#define PDM_MODE_OPERATION_Mono (1UL) /*!< Sample and store two successive left samples (16 bits each) per RAM word L1=[31:16]; L0=[15:0] */ +#define PDM_MODE_OPERATION_Stereo (0x0UL) /*!< Sample and store one pair (left + right) of 16-bit samples per RAM word R=[31:16]; L=[15:0] */ +#define PDM_MODE_OPERATION_Mono (0x1UL) /*!< Sample and store two successive left samples (16 bits each) per RAM word L1=[31:16]; L0=[15:0] */ /* Register: PDM_GAINL */ /* Description: Left output gain adjustment */ @@ -4775,8 +4775,8 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 0 : Selects the ratio between PDM_CLK and output sample rate */ #define PDM_RATIO_RATIO_Pos (0UL) /*!< Position of RATIO field. */ #define PDM_RATIO_RATIO_Msk (0x1UL << PDM_RATIO_RATIO_Pos) /*!< Bit mask of RATIO field. */ -#define PDM_RATIO_RATIO_Ratio64 (0UL) /*!< Ratio of 64 */ -#define PDM_RATIO_RATIO_Ratio80 (1UL) /*!< Ratio of 80 */ +#define PDM_RATIO_RATIO_Ratio64 (0x0UL) /*!< Ratio of 64 */ +#define PDM_RATIO_RATIO_Ratio80 (0x1UL) /*!< Ratio of 80 */ /* Register: PDM_PSEL_CLK */ /* Description: Pin number configuration for PDM CLK signal */ @@ -4784,8 +4784,8 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 31 : Connection */ #define PDM_PSEL_CLK_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ #define PDM_PSEL_CLK_CONNECT_Msk (0x1UL << PDM_PSEL_CLK_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ -#define PDM_PSEL_CLK_CONNECT_Connected (0UL) /*!< Connect */ -#define PDM_PSEL_CLK_CONNECT_Disconnected (1UL) /*!< Disconnect */ +#define PDM_PSEL_CLK_CONNECT_Connected (0x0UL) /*!< Connect */ +#define PDM_PSEL_CLK_CONNECT_Disconnected (0x1UL) /*!< Disconnect */ /* Bits 4..0 : Pin number */ #define PDM_PSEL_CLK_PIN_Pos (0UL) /*!< Position of PIN field. */ @@ -4797,8 +4797,8 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 31 : Connection */ #define PDM_PSEL_DIN_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ #define PDM_PSEL_DIN_CONNECT_Msk (0x1UL << PDM_PSEL_DIN_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ -#define PDM_PSEL_DIN_CONNECT_Connected (0UL) /*!< Connect */ -#define PDM_PSEL_DIN_CONNECT_Disconnected (1UL) /*!< Disconnect */ +#define PDM_PSEL_DIN_CONNECT_Connected (0x0UL) /*!< Connect */ +#define PDM_PSEL_DIN_CONNECT_Disconnected (0x1UL) /*!< Disconnect */ /* Bits 4..0 : Pin number */ #define PDM_PSEL_DIN_PIN_Pos (0UL) /*!< Position of PIN field. */ @@ -4828,7 +4828,7 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 0 : Request forcing PWM mode in external DC/DC voltage regulator. (Drives FPWM_DCDC pin high or low depending on a setting in UICR). */ #define POWER_TASKS_PWMREQSTART_TASKS_PWMREQSTART_Pos (0UL) /*!< Position of TASKS_PWMREQSTART field. */ #define POWER_TASKS_PWMREQSTART_TASKS_PWMREQSTART_Msk (0x1UL << POWER_TASKS_PWMREQSTART_TASKS_PWMREQSTART_Pos) /*!< Bit mask of TASKS_PWMREQSTART field. */ -#define POWER_TASKS_PWMREQSTART_TASKS_PWMREQSTART_Trigger (1UL) /*!< Trigger task */ +#define POWER_TASKS_PWMREQSTART_TASKS_PWMREQSTART_Trigger (0x1UL) /*!< Trigger task */ /* Register: POWER_TASKS_PWMREQSTOP */ /* Description: Stop requesting forcing PWM mode in external DC/DC voltage regulator */ @@ -4836,7 +4836,7 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 0 : Stop requesting forcing PWM mode in external DC/DC voltage regulator */ #define POWER_TASKS_PWMREQSTOP_TASKS_PWMREQSTOP_Pos (0UL) /*!< Position of TASKS_PWMREQSTOP field. */ #define POWER_TASKS_PWMREQSTOP_TASKS_PWMREQSTOP_Msk (0x1UL << POWER_TASKS_PWMREQSTOP_TASKS_PWMREQSTOP_Pos) /*!< Bit mask of TASKS_PWMREQSTOP field. */ -#define POWER_TASKS_PWMREQSTOP_TASKS_PWMREQSTOP_Trigger (1UL) /*!< Trigger task */ +#define POWER_TASKS_PWMREQSTOP_TASKS_PWMREQSTOP_Trigger (0x1UL) /*!< Trigger task */ /* Register: POWER_TASKS_CONSTLAT */ /* Description: Enable constant latency mode. */ @@ -4844,7 +4844,7 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 0 : Enable constant latency mode. */ #define POWER_TASKS_CONSTLAT_TASKS_CONSTLAT_Pos (0UL) /*!< Position of TASKS_CONSTLAT field. */ #define POWER_TASKS_CONSTLAT_TASKS_CONSTLAT_Msk (0x1UL << POWER_TASKS_CONSTLAT_TASKS_CONSTLAT_Pos) /*!< Bit mask of TASKS_CONSTLAT field. */ -#define POWER_TASKS_CONSTLAT_TASKS_CONSTLAT_Trigger (1UL) /*!< Trigger task */ +#define POWER_TASKS_CONSTLAT_TASKS_CONSTLAT_Trigger (0x1UL) /*!< Trigger task */ /* Register: POWER_TASKS_LOWPWR */ /* Description: Enable low power mode (variable latency) */ @@ -4852,7 +4852,7 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 0 : Enable low power mode (variable latency) */ #define POWER_TASKS_LOWPWR_TASKS_LOWPWR_Pos (0UL) /*!< Position of TASKS_LOWPWR field. */ #define POWER_TASKS_LOWPWR_TASKS_LOWPWR_Msk (0x1UL << POWER_TASKS_LOWPWR_TASKS_LOWPWR_Pos) /*!< Bit mask of TASKS_LOWPWR field. */ -#define POWER_TASKS_LOWPWR_TASKS_LOWPWR_Trigger (1UL) /*!< Trigger task */ +#define POWER_TASKS_LOWPWR_TASKS_LOWPWR_Trigger (0x1UL) /*!< Trigger task */ /* Register: POWER_SUBSCRIBE_PWMREQSTART */ /* Description: Subscribe configuration for task PWMREQSTART */ @@ -4860,8 +4860,8 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 31 : */ #define POWER_SUBSCRIBE_PWMREQSTART_EN_Pos (31UL) /*!< Position of EN field. */ #define POWER_SUBSCRIBE_PWMREQSTART_EN_Msk (0x1UL << POWER_SUBSCRIBE_PWMREQSTART_EN_Pos) /*!< Bit mask of EN field. */ -#define POWER_SUBSCRIBE_PWMREQSTART_EN_Disabled (0UL) /*!< Disable subscription */ -#define POWER_SUBSCRIBE_PWMREQSTART_EN_Enabled (1UL) /*!< Enable subscription */ +#define POWER_SUBSCRIBE_PWMREQSTART_EN_Disabled (0x0UL) /*!< Disable subscription */ +#define POWER_SUBSCRIBE_PWMREQSTART_EN_Enabled (0x1UL) /*!< Enable subscription */ /* Bits 7..0 : DPPI channel that task PWMREQSTART will subscribe to */ #define POWER_SUBSCRIBE_PWMREQSTART_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ @@ -4873,8 +4873,8 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 31 : */ #define POWER_SUBSCRIBE_PWMREQSTOP_EN_Pos (31UL) /*!< Position of EN field. */ #define POWER_SUBSCRIBE_PWMREQSTOP_EN_Msk (0x1UL << POWER_SUBSCRIBE_PWMREQSTOP_EN_Pos) /*!< Bit mask of EN field. */ -#define POWER_SUBSCRIBE_PWMREQSTOP_EN_Disabled (0UL) /*!< Disable subscription */ -#define POWER_SUBSCRIBE_PWMREQSTOP_EN_Enabled (1UL) /*!< Enable subscription */ +#define POWER_SUBSCRIBE_PWMREQSTOP_EN_Disabled (0x0UL) /*!< Disable subscription */ +#define POWER_SUBSCRIBE_PWMREQSTOP_EN_Enabled (0x1UL) /*!< Enable subscription */ /* Bits 7..0 : DPPI channel that task PWMREQSTOP will subscribe to */ #define POWER_SUBSCRIBE_PWMREQSTOP_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ @@ -4886,8 +4886,8 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 31 : */ #define POWER_SUBSCRIBE_CONSTLAT_EN_Pos (31UL) /*!< Position of EN field. */ #define POWER_SUBSCRIBE_CONSTLAT_EN_Msk (0x1UL << POWER_SUBSCRIBE_CONSTLAT_EN_Pos) /*!< Bit mask of EN field. */ -#define POWER_SUBSCRIBE_CONSTLAT_EN_Disabled (0UL) /*!< Disable subscription */ -#define POWER_SUBSCRIBE_CONSTLAT_EN_Enabled (1UL) /*!< Enable subscription */ +#define POWER_SUBSCRIBE_CONSTLAT_EN_Disabled (0x0UL) /*!< Disable subscription */ +#define POWER_SUBSCRIBE_CONSTLAT_EN_Enabled (0x1UL) /*!< Enable subscription */ /* Bits 7..0 : DPPI channel that task CONSTLAT will subscribe to */ #define POWER_SUBSCRIBE_CONSTLAT_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ @@ -4899,8 +4899,8 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 31 : */ #define POWER_SUBSCRIBE_LOWPWR_EN_Pos (31UL) /*!< Position of EN field. */ #define POWER_SUBSCRIBE_LOWPWR_EN_Msk (0x1UL << POWER_SUBSCRIBE_LOWPWR_EN_Pos) /*!< Bit mask of EN field. */ -#define POWER_SUBSCRIBE_LOWPWR_EN_Disabled (0UL) /*!< Disable subscription */ -#define POWER_SUBSCRIBE_LOWPWR_EN_Enabled (1UL) /*!< Enable subscription */ +#define POWER_SUBSCRIBE_LOWPWR_EN_Disabled (0x0UL) /*!< Disable subscription */ +#define POWER_SUBSCRIBE_LOWPWR_EN_Enabled (0x1UL) /*!< Enable subscription */ /* Bits 7..0 : DPPI channel that task LOWPWR will subscribe to */ #define POWER_SUBSCRIBE_LOWPWR_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ @@ -4912,8 +4912,8 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 0 : Power failure warning */ #define POWER_EVENTS_POFWARN_EVENTS_POFWARN_Pos (0UL) /*!< Position of EVENTS_POFWARN field. */ #define POWER_EVENTS_POFWARN_EVENTS_POFWARN_Msk (0x1UL << POWER_EVENTS_POFWARN_EVENTS_POFWARN_Pos) /*!< Bit mask of EVENTS_POFWARN field. */ -#define POWER_EVENTS_POFWARN_EVENTS_POFWARN_NotGenerated (0UL) /*!< Event not generated */ -#define POWER_EVENTS_POFWARN_EVENTS_POFWARN_Generated (1UL) /*!< Event generated */ +#define POWER_EVENTS_POFWARN_EVENTS_POFWARN_NotGenerated (0x0UL) /*!< Event not generated */ +#define POWER_EVENTS_POFWARN_EVENTS_POFWARN_Generated (0x1UL) /*!< Event generated */ /* Register: POWER_EVENTS_SLEEPENTER */ /* Description: CPU entered WFI/WFE sleep */ @@ -4921,8 +4921,8 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 0 : CPU entered WFI/WFE sleep */ #define POWER_EVENTS_SLEEPENTER_EVENTS_SLEEPENTER_Pos (0UL) /*!< Position of EVENTS_SLEEPENTER field. */ #define POWER_EVENTS_SLEEPENTER_EVENTS_SLEEPENTER_Msk (0x1UL << POWER_EVENTS_SLEEPENTER_EVENTS_SLEEPENTER_Pos) /*!< Bit mask of EVENTS_SLEEPENTER field. */ -#define POWER_EVENTS_SLEEPENTER_EVENTS_SLEEPENTER_NotGenerated (0UL) /*!< Event not generated */ -#define POWER_EVENTS_SLEEPENTER_EVENTS_SLEEPENTER_Generated (1UL) /*!< Event generated */ +#define POWER_EVENTS_SLEEPENTER_EVENTS_SLEEPENTER_NotGenerated (0x0UL) /*!< Event not generated */ +#define POWER_EVENTS_SLEEPENTER_EVENTS_SLEEPENTER_Generated (0x1UL) /*!< Event generated */ /* Register: POWER_EVENTS_SLEEPEXIT */ /* Description: CPU exited WFI/WFE sleep */ @@ -4930,8 +4930,8 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 0 : CPU exited WFI/WFE sleep */ #define POWER_EVENTS_SLEEPEXIT_EVENTS_SLEEPEXIT_Pos (0UL) /*!< Position of EVENTS_SLEEPEXIT field. */ #define POWER_EVENTS_SLEEPEXIT_EVENTS_SLEEPEXIT_Msk (0x1UL << POWER_EVENTS_SLEEPEXIT_EVENTS_SLEEPEXIT_Pos) /*!< Bit mask of EVENTS_SLEEPEXIT field. */ -#define POWER_EVENTS_SLEEPEXIT_EVENTS_SLEEPEXIT_NotGenerated (0UL) /*!< Event not generated */ -#define POWER_EVENTS_SLEEPEXIT_EVENTS_SLEEPEXIT_Generated (1UL) /*!< Event generated */ +#define POWER_EVENTS_SLEEPEXIT_EVENTS_SLEEPEXIT_NotGenerated (0x0UL) /*!< Event not generated */ +#define POWER_EVENTS_SLEEPEXIT_EVENTS_SLEEPEXIT_Generated (0x1UL) /*!< Event generated */ /* Register: POWER_PUBLISH_POFWARN */ /* Description: Publish configuration for event POFWARN */ @@ -4939,8 +4939,8 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 31 : */ #define POWER_PUBLISH_POFWARN_EN_Pos (31UL) /*!< Position of EN field. */ #define POWER_PUBLISH_POFWARN_EN_Msk (0x1UL << POWER_PUBLISH_POFWARN_EN_Pos) /*!< Bit mask of EN field. */ -#define POWER_PUBLISH_POFWARN_EN_Disabled (0UL) /*!< Disable publishing */ -#define POWER_PUBLISH_POFWARN_EN_Enabled (1UL) /*!< Enable publishing */ +#define POWER_PUBLISH_POFWARN_EN_Disabled (0x0UL) /*!< Disable publishing */ +#define POWER_PUBLISH_POFWARN_EN_Enabled (0x1UL) /*!< Enable publishing */ /* Bits 7..0 : DPPI channel that event POFWARN will publish to */ #define POWER_PUBLISH_POFWARN_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ @@ -4952,8 +4952,8 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 31 : */ #define POWER_PUBLISH_SLEEPENTER_EN_Pos (31UL) /*!< Position of EN field. */ #define POWER_PUBLISH_SLEEPENTER_EN_Msk (0x1UL << POWER_PUBLISH_SLEEPENTER_EN_Pos) /*!< Bit mask of EN field. */ -#define POWER_PUBLISH_SLEEPENTER_EN_Disabled (0UL) /*!< Disable publishing */ -#define POWER_PUBLISH_SLEEPENTER_EN_Enabled (1UL) /*!< Enable publishing */ +#define POWER_PUBLISH_SLEEPENTER_EN_Disabled (0x0UL) /*!< Disable publishing */ +#define POWER_PUBLISH_SLEEPENTER_EN_Enabled (0x1UL) /*!< Enable publishing */ /* Bits 7..0 : DPPI channel that event SLEEPENTER will publish to */ #define POWER_PUBLISH_SLEEPENTER_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ @@ -4965,8 +4965,8 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 31 : */ #define POWER_PUBLISH_SLEEPEXIT_EN_Pos (31UL) /*!< Position of EN field. */ #define POWER_PUBLISH_SLEEPEXIT_EN_Msk (0x1UL << POWER_PUBLISH_SLEEPEXIT_EN_Pos) /*!< Bit mask of EN field. */ -#define POWER_PUBLISH_SLEEPEXIT_EN_Disabled (0UL) /*!< Disable publishing */ -#define POWER_PUBLISH_SLEEPEXIT_EN_Enabled (1UL) /*!< Enable publishing */ +#define POWER_PUBLISH_SLEEPEXIT_EN_Disabled (0x0UL) /*!< Disable publishing */ +#define POWER_PUBLISH_SLEEPEXIT_EN_Enabled (0x1UL) /*!< Enable publishing */ /* Bits 7..0 : DPPI channel that event SLEEPEXIT will publish to */ #define POWER_PUBLISH_SLEEPEXIT_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ @@ -4978,20 +4978,20 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 6 : Enable or disable interrupt for event SLEEPEXIT */ #define POWER_INTEN_SLEEPEXIT_Pos (6UL) /*!< Position of SLEEPEXIT field. */ #define POWER_INTEN_SLEEPEXIT_Msk (0x1UL << POWER_INTEN_SLEEPEXIT_Pos) /*!< Bit mask of SLEEPEXIT field. */ -#define POWER_INTEN_SLEEPEXIT_Disabled (0UL) /*!< Disable */ -#define POWER_INTEN_SLEEPEXIT_Enabled (1UL) /*!< Enable */ +#define POWER_INTEN_SLEEPEXIT_Disabled (0x0UL) /*!< Disable */ +#define POWER_INTEN_SLEEPEXIT_Enabled (0x1UL) /*!< Enable */ /* Bit 5 : Enable or disable interrupt for event SLEEPENTER */ #define POWER_INTEN_SLEEPENTER_Pos (5UL) /*!< Position of SLEEPENTER field. */ #define POWER_INTEN_SLEEPENTER_Msk (0x1UL << POWER_INTEN_SLEEPENTER_Pos) /*!< Bit mask of SLEEPENTER field. */ -#define POWER_INTEN_SLEEPENTER_Disabled (0UL) /*!< Disable */ -#define POWER_INTEN_SLEEPENTER_Enabled (1UL) /*!< Enable */ +#define POWER_INTEN_SLEEPENTER_Disabled (0x0UL) /*!< Disable */ +#define POWER_INTEN_SLEEPENTER_Enabled (0x1UL) /*!< Enable */ /* Bit 2 : Enable or disable interrupt for event POFWARN */ #define POWER_INTEN_POFWARN_Pos (2UL) /*!< Position of POFWARN field. */ #define POWER_INTEN_POFWARN_Msk (0x1UL << POWER_INTEN_POFWARN_Pos) /*!< Bit mask of POFWARN field. */ -#define POWER_INTEN_POFWARN_Disabled (0UL) /*!< Disable */ -#define POWER_INTEN_POFWARN_Enabled (1UL) /*!< Enable */ +#define POWER_INTEN_POFWARN_Disabled (0x0UL) /*!< Disable */ +#define POWER_INTEN_POFWARN_Enabled (0x1UL) /*!< Enable */ /* Register: POWER_INTENSET */ /* Description: Enable interrupt */ @@ -4999,23 +4999,23 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 6 : Write '1' to enable interrupt for event SLEEPEXIT */ #define POWER_INTENSET_SLEEPEXIT_Pos (6UL) /*!< Position of SLEEPEXIT field. */ #define POWER_INTENSET_SLEEPEXIT_Msk (0x1UL << POWER_INTENSET_SLEEPEXIT_Pos) /*!< Bit mask of SLEEPEXIT field. */ -#define POWER_INTENSET_SLEEPEXIT_Disabled (0UL) /*!< Read: Disabled */ -#define POWER_INTENSET_SLEEPEXIT_Enabled (1UL) /*!< Read: Enabled */ -#define POWER_INTENSET_SLEEPEXIT_Set (1UL) /*!< Enable */ +#define POWER_INTENSET_SLEEPEXIT_Disabled (0x0UL) /*!< Read: Disabled */ +#define POWER_INTENSET_SLEEPEXIT_Enabled (0x1UL) /*!< Read: Enabled */ +#define POWER_INTENSET_SLEEPEXIT_Set (0x1UL) /*!< Enable */ /* Bit 5 : Write '1' to enable interrupt for event SLEEPENTER */ #define POWER_INTENSET_SLEEPENTER_Pos (5UL) /*!< Position of SLEEPENTER field. */ #define POWER_INTENSET_SLEEPENTER_Msk (0x1UL << POWER_INTENSET_SLEEPENTER_Pos) /*!< Bit mask of SLEEPENTER field. */ -#define POWER_INTENSET_SLEEPENTER_Disabled (0UL) /*!< Read: Disabled */ -#define POWER_INTENSET_SLEEPENTER_Enabled (1UL) /*!< Read: Enabled */ -#define POWER_INTENSET_SLEEPENTER_Set (1UL) /*!< Enable */ +#define POWER_INTENSET_SLEEPENTER_Disabled (0x0UL) /*!< Read: Disabled */ +#define POWER_INTENSET_SLEEPENTER_Enabled (0x1UL) /*!< Read: Enabled */ +#define POWER_INTENSET_SLEEPENTER_Set (0x1UL) /*!< Enable */ /* Bit 2 : Write '1' to enable interrupt for event POFWARN */ #define POWER_INTENSET_POFWARN_Pos (2UL) /*!< Position of POFWARN field. */ #define POWER_INTENSET_POFWARN_Msk (0x1UL << POWER_INTENSET_POFWARN_Pos) /*!< Bit mask of POFWARN field. */ -#define POWER_INTENSET_POFWARN_Disabled (0UL) /*!< Read: Disabled */ -#define POWER_INTENSET_POFWARN_Enabled (1UL) /*!< Read: Enabled */ -#define POWER_INTENSET_POFWARN_Set (1UL) /*!< Enable */ +#define POWER_INTENSET_POFWARN_Disabled (0x0UL) /*!< Read: Disabled */ +#define POWER_INTENSET_POFWARN_Enabled (0x1UL) /*!< Read: Enabled */ +#define POWER_INTENSET_POFWARN_Set (0x1UL) /*!< Enable */ /* Register: POWER_INTENCLR */ /* Description: Disable interrupt */ @@ -5023,23 +5023,23 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 6 : Write '1' to disable interrupt for event SLEEPEXIT */ #define POWER_INTENCLR_SLEEPEXIT_Pos (6UL) /*!< Position of SLEEPEXIT field. */ #define POWER_INTENCLR_SLEEPEXIT_Msk (0x1UL << POWER_INTENCLR_SLEEPEXIT_Pos) /*!< Bit mask of SLEEPEXIT field. */ -#define POWER_INTENCLR_SLEEPEXIT_Disabled (0UL) /*!< Read: Disabled */ -#define POWER_INTENCLR_SLEEPEXIT_Enabled (1UL) /*!< Read: Enabled */ -#define POWER_INTENCLR_SLEEPEXIT_Clear (1UL) /*!< Disable */ +#define POWER_INTENCLR_SLEEPEXIT_Disabled (0x0UL) /*!< Read: Disabled */ +#define POWER_INTENCLR_SLEEPEXIT_Enabled (0x1UL) /*!< Read: Enabled */ +#define POWER_INTENCLR_SLEEPEXIT_Clear (0x1UL) /*!< Disable */ /* Bit 5 : Write '1' to disable interrupt for event SLEEPENTER */ #define POWER_INTENCLR_SLEEPENTER_Pos (5UL) /*!< Position of SLEEPENTER field. */ #define POWER_INTENCLR_SLEEPENTER_Msk (0x1UL << POWER_INTENCLR_SLEEPENTER_Pos) /*!< Bit mask of SLEEPENTER field. */ -#define POWER_INTENCLR_SLEEPENTER_Disabled (0UL) /*!< Read: Disabled */ -#define POWER_INTENCLR_SLEEPENTER_Enabled (1UL) /*!< Read: Enabled */ -#define POWER_INTENCLR_SLEEPENTER_Clear (1UL) /*!< Disable */ +#define POWER_INTENCLR_SLEEPENTER_Disabled (0x0UL) /*!< Read: Disabled */ +#define POWER_INTENCLR_SLEEPENTER_Enabled (0x1UL) /*!< Read: Enabled */ +#define POWER_INTENCLR_SLEEPENTER_Clear (0x1UL) /*!< Disable */ /* Bit 2 : Write '1' to disable interrupt for event POFWARN */ #define POWER_INTENCLR_POFWARN_Pos (2UL) /*!< Position of POFWARN field. */ #define POWER_INTENCLR_POFWARN_Msk (0x1UL << POWER_INTENCLR_POFWARN_Pos) /*!< Bit mask of POFWARN field. */ -#define POWER_INTENCLR_POFWARN_Disabled (0UL) /*!< Read: Disabled */ -#define POWER_INTENCLR_POFWARN_Enabled (1UL) /*!< Read: Enabled */ -#define POWER_INTENCLR_POFWARN_Clear (1UL) /*!< Disable */ +#define POWER_INTENCLR_POFWARN_Disabled (0x0UL) /*!< Read: Disabled */ +#define POWER_INTENCLR_POFWARN_Enabled (0x1UL) /*!< Read: Enabled */ +#define POWER_INTENCLR_POFWARN_Clear (0x1UL) /*!< Disable */ /* Register: POWER_RESETREAS */ /* Description: Reset reason */ @@ -5047,44 +5047,44 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 18 : Reset triggered through CTRL-AP */ #define POWER_RESETREAS_CTRLAP_Pos (18UL) /*!< Position of CTRLAP field. */ #define POWER_RESETREAS_CTRLAP_Msk (0x1UL << POWER_RESETREAS_CTRLAP_Pos) /*!< Bit mask of CTRLAP field. */ -#define POWER_RESETREAS_CTRLAP_NotDetected (0UL) /*!< Not detected */ -#define POWER_RESETREAS_CTRLAP_Detected (1UL) /*!< Detected */ +#define POWER_RESETREAS_CTRLAP_NotDetected (0x0UL) /*!< Not detected */ +#define POWER_RESETREAS_CTRLAP_Detected (0x1UL) /*!< Detected */ /* Bit 17 : Reset from CPU lock-up detected */ #define POWER_RESETREAS_LOCKUP_Pos (17UL) /*!< Position of LOCKUP field. */ #define POWER_RESETREAS_LOCKUP_Msk (0x1UL << POWER_RESETREAS_LOCKUP_Pos) /*!< Bit mask of LOCKUP field. */ -#define POWER_RESETREAS_LOCKUP_NotDetected (0UL) /*!< Not detected */ -#define POWER_RESETREAS_LOCKUP_Detected (1UL) /*!< Detected */ +#define POWER_RESETREAS_LOCKUP_NotDetected (0x0UL) /*!< Not detected */ +#define POWER_RESETREAS_LOCKUP_Detected (0x1UL) /*!< Detected */ /* Bit 16 : Reset from AIRCR.SYSRESETREQ detected */ #define POWER_RESETREAS_SREQ_Pos (16UL) /*!< Position of SREQ field. */ #define POWER_RESETREAS_SREQ_Msk (0x1UL << POWER_RESETREAS_SREQ_Pos) /*!< Bit mask of SREQ field. */ -#define POWER_RESETREAS_SREQ_NotDetected (0UL) /*!< Not detected */ -#define POWER_RESETREAS_SREQ_Detected (1UL) /*!< Detected */ +#define POWER_RESETREAS_SREQ_NotDetected (0x0UL) /*!< Not detected */ +#define POWER_RESETREAS_SREQ_Detected (0x1UL) /*!< Detected */ /* Bit 4 : Reset due to wakeup from System OFF mode, when wakeup is triggered by entering debug interface mode */ #define POWER_RESETREAS_DIF_Pos (4UL) /*!< Position of DIF field. */ #define POWER_RESETREAS_DIF_Msk (0x1UL << POWER_RESETREAS_DIF_Pos) /*!< Bit mask of DIF field. */ -#define POWER_RESETREAS_DIF_NotDetected (0UL) /*!< Not detected */ -#define POWER_RESETREAS_DIF_Detected (1UL) /*!< Detected */ +#define POWER_RESETREAS_DIF_NotDetected (0x0UL) /*!< Not detected */ +#define POWER_RESETREAS_DIF_Detected (0x1UL) /*!< Detected */ /* Bit 2 : Reset due to wakeup from System OFF mode, when wakeup is triggered by DETECT signal from GPIO */ #define POWER_RESETREAS_OFF_Pos (2UL) /*!< Position of OFF field. */ #define POWER_RESETREAS_OFF_Msk (0x1UL << POWER_RESETREAS_OFF_Pos) /*!< Bit mask of OFF field. */ -#define POWER_RESETREAS_OFF_NotDetected (0UL) /*!< Not detected */ -#define POWER_RESETREAS_OFF_Detected (1UL) /*!< Detected */ +#define POWER_RESETREAS_OFF_NotDetected (0x0UL) /*!< Not detected */ +#define POWER_RESETREAS_OFF_Detected (0x1UL) /*!< Detected */ /* Bit 1 : Reset from global watchdog detected */ #define POWER_RESETREAS_DOG_Pos (1UL) /*!< Position of DOG field. */ #define POWER_RESETREAS_DOG_Msk (0x1UL << POWER_RESETREAS_DOG_Pos) /*!< Bit mask of DOG field. */ -#define POWER_RESETREAS_DOG_NotDetected (0UL) /*!< Not detected */ -#define POWER_RESETREAS_DOG_Detected (1UL) /*!< Detected */ +#define POWER_RESETREAS_DOG_NotDetected (0x0UL) /*!< Not detected */ +#define POWER_RESETREAS_DOG_Detected (0x1UL) /*!< Detected */ /* Bit 0 : Reset from pin reset detected */ #define POWER_RESETREAS_RESETPIN_Pos (0UL) /*!< Position of RESETPIN field. */ #define POWER_RESETREAS_RESETPIN_Msk (0x1UL << POWER_RESETREAS_RESETPIN_Pos) /*!< Bit mask of RESETPIN field. */ -#define POWER_RESETREAS_RESETPIN_NotDetected (0UL) /*!< Not detected */ -#define POWER_RESETREAS_RESETPIN_Detected (1UL) /*!< Detected */ +#define POWER_RESETREAS_RESETPIN_NotDetected (0x0UL) /*!< Not detected */ +#define POWER_RESETREAS_RESETPIN_Detected (0x1UL) /*!< Detected */ /* Register: POWER_POWERSTATUS */ /* Description: Modem domain power status */ @@ -5092,8 +5092,8 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 0 : LTE modem domain status */ #define POWER_POWERSTATUS_LTEMODEM_Pos (0UL) /*!< Position of LTEMODEM field. */ #define POWER_POWERSTATUS_LTEMODEM_Msk (0x1UL << POWER_POWERSTATUS_LTEMODEM_Pos) /*!< Bit mask of LTEMODEM field. */ -#define POWER_POWERSTATUS_LTEMODEM_OFF (0UL) /*!< LTE modem domain is powered off */ -#define POWER_POWERSTATUS_LTEMODEM_ON (1UL) /*!< LTE modem domain is powered on */ +#define POWER_POWERSTATUS_LTEMODEM_OFF (0x0UL) /*!< LTE modem domain is powered off */ +#define POWER_POWERSTATUS_LTEMODEM_ON (0x1UL) /*!< LTE modem domain is powered on */ /* Register: POWER_GPREGRET */ /* Description: Description collection: General purpose retention register */ @@ -5108,8 +5108,8 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 0 : Start LTE modem */ #define POWER_LTEMODEM_STARTN_STARTN_Pos (0UL) /*!< Position of STARTN field. */ #define POWER_LTEMODEM_STARTN_STARTN_Msk (0x1UL << POWER_LTEMODEM_STARTN_STARTN_Pos) /*!< Bit mask of STARTN field. */ -#define POWER_LTEMODEM_STARTN_STARTN_Start (0UL) /*!< Start LTE modem */ -#define POWER_LTEMODEM_STARTN_STARTN_Hold (1UL) /*!< Hold LTE modem disabled */ +#define POWER_LTEMODEM_STARTN_STARTN_Start (0x0UL) /*!< Start LTE modem */ +#define POWER_LTEMODEM_STARTN_STARTN_Hold (0x1UL) /*!< Hold LTE modem disabled */ /* Register: POWER_LTEMODEM_FORCEOFF */ /* Description: Force off LTE modem */ @@ -5117,8 +5117,8 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 0 : Force off LTE modem */ #define POWER_LTEMODEM_FORCEOFF_FORCEOFF_Pos (0UL) /*!< Position of FORCEOFF field. */ #define POWER_LTEMODEM_FORCEOFF_FORCEOFF_Msk (0x1UL << POWER_LTEMODEM_FORCEOFF_FORCEOFF_Pos) /*!< Bit mask of FORCEOFF field. */ -#define POWER_LTEMODEM_FORCEOFF_FORCEOFF_Release (0UL) /*!< Release force off */ -#define POWER_LTEMODEM_FORCEOFF_FORCEOFF_Hold (1UL) /*!< Hold force off active */ +#define POWER_LTEMODEM_FORCEOFF_FORCEOFF_Release (0x0UL) /*!< Release force off */ +#define POWER_LTEMODEM_FORCEOFF_FORCEOFF_Hold (0x1UL) /*!< Hold force off active */ /* Peripheral: PWM */ @@ -5130,7 +5130,7 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 0 : Stops PWM pulse generation on all channels at the end of current PWM period, and stops sequence playback */ #define PWM_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */ #define PWM_TASKS_STOP_TASKS_STOP_Msk (0x1UL << PWM_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */ -#define PWM_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */ +#define PWM_TASKS_STOP_TASKS_STOP_Trigger (0x1UL) /*!< Trigger task */ /* Register: PWM_TASKS_SEQSTART */ /* Description: Description collection: Loads the first PWM value on all enabled channels from sequence n, and starts playing that sequence at the rate defined in SEQ[n]REFRESH and/or DECODER.MODE. Causes PWM generation to start if not running. */ @@ -5138,7 +5138,7 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 0 : Loads the first PWM value on all enabled channels from sequence n, and starts playing that sequence at the rate defined in SEQ[n]REFRESH and/or DECODER.MODE. Causes PWM generation to start if not running. */ #define PWM_TASKS_SEQSTART_TASKS_SEQSTART_Pos (0UL) /*!< Position of TASKS_SEQSTART field. */ #define PWM_TASKS_SEQSTART_TASKS_SEQSTART_Msk (0x1UL << PWM_TASKS_SEQSTART_TASKS_SEQSTART_Pos) /*!< Bit mask of TASKS_SEQSTART field. */ -#define PWM_TASKS_SEQSTART_TASKS_SEQSTART_Trigger (1UL) /*!< Trigger task */ +#define PWM_TASKS_SEQSTART_TASKS_SEQSTART_Trigger (0x1UL) /*!< Trigger task */ /* Register: PWM_TASKS_NEXTSTEP */ /* Description: Steps by one value in the current sequence on all enabled channels if DECODER.MODE=NextStep. Does not cause PWM generation to start if not running. */ @@ -5146,7 +5146,7 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 0 : Steps by one value in the current sequence on all enabled channels if DECODER.MODE=NextStep. Does not cause PWM generation to start if not running. */ #define PWM_TASKS_NEXTSTEP_TASKS_NEXTSTEP_Pos (0UL) /*!< Position of TASKS_NEXTSTEP field. */ #define PWM_TASKS_NEXTSTEP_TASKS_NEXTSTEP_Msk (0x1UL << PWM_TASKS_NEXTSTEP_TASKS_NEXTSTEP_Pos) /*!< Bit mask of TASKS_NEXTSTEP field. */ -#define PWM_TASKS_NEXTSTEP_TASKS_NEXTSTEP_Trigger (1UL) /*!< Trigger task */ +#define PWM_TASKS_NEXTSTEP_TASKS_NEXTSTEP_Trigger (0x1UL) /*!< Trigger task */ /* Register: PWM_SUBSCRIBE_STOP */ /* Description: Subscribe configuration for task STOP */ @@ -5154,8 +5154,8 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 31 : */ #define PWM_SUBSCRIBE_STOP_EN_Pos (31UL) /*!< Position of EN field. */ #define PWM_SUBSCRIBE_STOP_EN_Msk (0x1UL << PWM_SUBSCRIBE_STOP_EN_Pos) /*!< Bit mask of EN field. */ -#define PWM_SUBSCRIBE_STOP_EN_Disabled (0UL) /*!< Disable subscription */ -#define PWM_SUBSCRIBE_STOP_EN_Enabled (1UL) /*!< Enable subscription */ +#define PWM_SUBSCRIBE_STOP_EN_Disabled (0x0UL) /*!< Disable subscription */ +#define PWM_SUBSCRIBE_STOP_EN_Enabled (0x1UL) /*!< Enable subscription */ /* Bits 7..0 : DPPI channel that task STOP will subscribe to */ #define PWM_SUBSCRIBE_STOP_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ @@ -5167,8 +5167,8 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 31 : */ #define PWM_SUBSCRIBE_SEQSTART_EN_Pos (31UL) /*!< Position of EN field. */ #define PWM_SUBSCRIBE_SEQSTART_EN_Msk (0x1UL << PWM_SUBSCRIBE_SEQSTART_EN_Pos) /*!< Bit mask of EN field. */ -#define PWM_SUBSCRIBE_SEQSTART_EN_Disabled (0UL) /*!< Disable subscription */ -#define PWM_SUBSCRIBE_SEQSTART_EN_Enabled (1UL) /*!< Enable subscription */ +#define PWM_SUBSCRIBE_SEQSTART_EN_Disabled (0x0UL) /*!< Disable subscription */ +#define PWM_SUBSCRIBE_SEQSTART_EN_Enabled (0x1UL) /*!< Enable subscription */ /* Bits 7..0 : DPPI channel that task SEQSTART[n] will subscribe to */ #define PWM_SUBSCRIBE_SEQSTART_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ @@ -5180,8 +5180,8 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 31 : */ #define PWM_SUBSCRIBE_NEXTSTEP_EN_Pos (31UL) /*!< Position of EN field. */ #define PWM_SUBSCRIBE_NEXTSTEP_EN_Msk (0x1UL << PWM_SUBSCRIBE_NEXTSTEP_EN_Pos) /*!< Bit mask of EN field. */ -#define PWM_SUBSCRIBE_NEXTSTEP_EN_Disabled (0UL) /*!< Disable subscription */ -#define PWM_SUBSCRIBE_NEXTSTEP_EN_Enabled (1UL) /*!< Enable subscription */ +#define PWM_SUBSCRIBE_NEXTSTEP_EN_Disabled (0x0UL) /*!< Disable subscription */ +#define PWM_SUBSCRIBE_NEXTSTEP_EN_Enabled (0x1UL) /*!< Enable subscription */ /* Bits 7..0 : DPPI channel that task NEXTSTEP will subscribe to */ #define PWM_SUBSCRIBE_NEXTSTEP_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ @@ -5193,8 +5193,8 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 0 : Response to STOP task, emitted when PWM pulses are no longer generated */ #define PWM_EVENTS_STOPPED_EVENTS_STOPPED_Pos (0UL) /*!< Position of EVENTS_STOPPED field. */ #define PWM_EVENTS_STOPPED_EVENTS_STOPPED_Msk (0x1UL << PWM_EVENTS_STOPPED_EVENTS_STOPPED_Pos) /*!< Bit mask of EVENTS_STOPPED field. */ -#define PWM_EVENTS_STOPPED_EVENTS_STOPPED_NotGenerated (0UL) /*!< Event not generated */ -#define PWM_EVENTS_STOPPED_EVENTS_STOPPED_Generated (1UL) /*!< Event generated */ +#define PWM_EVENTS_STOPPED_EVENTS_STOPPED_NotGenerated (0x0UL) /*!< Event not generated */ +#define PWM_EVENTS_STOPPED_EVENTS_STOPPED_Generated (0x1UL) /*!< Event generated */ /* Register: PWM_EVENTS_SEQSTARTED */ /* Description: Description collection: First PWM period started on sequence n */ @@ -5202,8 +5202,8 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 0 : First PWM period started on sequence n */ #define PWM_EVENTS_SEQSTARTED_EVENTS_SEQSTARTED_Pos (0UL) /*!< Position of EVENTS_SEQSTARTED field. */ #define PWM_EVENTS_SEQSTARTED_EVENTS_SEQSTARTED_Msk (0x1UL << PWM_EVENTS_SEQSTARTED_EVENTS_SEQSTARTED_Pos) /*!< Bit mask of EVENTS_SEQSTARTED field. */ -#define PWM_EVENTS_SEQSTARTED_EVENTS_SEQSTARTED_NotGenerated (0UL) /*!< Event not generated */ -#define PWM_EVENTS_SEQSTARTED_EVENTS_SEQSTARTED_Generated (1UL) /*!< Event generated */ +#define PWM_EVENTS_SEQSTARTED_EVENTS_SEQSTARTED_NotGenerated (0x0UL) /*!< Event not generated */ +#define PWM_EVENTS_SEQSTARTED_EVENTS_SEQSTARTED_Generated (0x1UL) /*!< Event generated */ /* Register: PWM_EVENTS_SEQEND */ /* Description: Description collection: Emitted at end of every sequence n, when last value from RAM has been applied to wave counter */ @@ -5211,8 +5211,8 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 0 : Emitted at end of every sequence n, when last value from RAM has been applied to wave counter */ #define PWM_EVENTS_SEQEND_EVENTS_SEQEND_Pos (0UL) /*!< Position of EVENTS_SEQEND field. */ #define PWM_EVENTS_SEQEND_EVENTS_SEQEND_Msk (0x1UL << PWM_EVENTS_SEQEND_EVENTS_SEQEND_Pos) /*!< Bit mask of EVENTS_SEQEND field. */ -#define PWM_EVENTS_SEQEND_EVENTS_SEQEND_NotGenerated (0UL) /*!< Event not generated */ -#define PWM_EVENTS_SEQEND_EVENTS_SEQEND_Generated (1UL) /*!< Event generated */ +#define PWM_EVENTS_SEQEND_EVENTS_SEQEND_NotGenerated (0x0UL) /*!< Event not generated */ +#define PWM_EVENTS_SEQEND_EVENTS_SEQEND_Generated (0x1UL) /*!< Event generated */ /* Register: PWM_EVENTS_PWMPERIODEND */ /* Description: Emitted at the end of each PWM period */ @@ -5220,8 +5220,8 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 0 : Emitted at the end of each PWM period */ #define PWM_EVENTS_PWMPERIODEND_EVENTS_PWMPERIODEND_Pos (0UL) /*!< Position of EVENTS_PWMPERIODEND field. */ #define PWM_EVENTS_PWMPERIODEND_EVENTS_PWMPERIODEND_Msk (0x1UL << PWM_EVENTS_PWMPERIODEND_EVENTS_PWMPERIODEND_Pos) /*!< Bit mask of EVENTS_PWMPERIODEND field. */ -#define PWM_EVENTS_PWMPERIODEND_EVENTS_PWMPERIODEND_NotGenerated (0UL) /*!< Event not generated */ -#define PWM_EVENTS_PWMPERIODEND_EVENTS_PWMPERIODEND_Generated (1UL) /*!< Event generated */ +#define PWM_EVENTS_PWMPERIODEND_EVENTS_PWMPERIODEND_NotGenerated (0x0UL) /*!< Event not generated */ +#define PWM_EVENTS_PWMPERIODEND_EVENTS_PWMPERIODEND_Generated (0x1UL) /*!< Event generated */ /* Register: PWM_EVENTS_LOOPSDONE */ /* Description: Concatenated sequences have been played the amount of times defined in LOOP.CNT */ @@ -5229,8 +5229,8 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 0 : Concatenated sequences have been played the amount of times defined in LOOP.CNT */ #define PWM_EVENTS_LOOPSDONE_EVENTS_LOOPSDONE_Pos (0UL) /*!< Position of EVENTS_LOOPSDONE field. */ #define PWM_EVENTS_LOOPSDONE_EVENTS_LOOPSDONE_Msk (0x1UL << PWM_EVENTS_LOOPSDONE_EVENTS_LOOPSDONE_Pos) /*!< Bit mask of EVENTS_LOOPSDONE field. */ -#define PWM_EVENTS_LOOPSDONE_EVENTS_LOOPSDONE_NotGenerated (0UL) /*!< Event not generated */ -#define PWM_EVENTS_LOOPSDONE_EVENTS_LOOPSDONE_Generated (1UL) /*!< Event generated */ +#define PWM_EVENTS_LOOPSDONE_EVENTS_LOOPSDONE_NotGenerated (0x0UL) /*!< Event not generated */ +#define PWM_EVENTS_LOOPSDONE_EVENTS_LOOPSDONE_Generated (0x1UL) /*!< Event generated */ /* Register: PWM_PUBLISH_STOPPED */ /* Description: Publish configuration for event STOPPED */ @@ -5238,8 +5238,8 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 31 : */ #define PWM_PUBLISH_STOPPED_EN_Pos (31UL) /*!< Position of EN field. */ #define PWM_PUBLISH_STOPPED_EN_Msk (0x1UL << PWM_PUBLISH_STOPPED_EN_Pos) /*!< Bit mask of EN field. */ -#define PWM_PUBLISH_STOPPED_EN_Disabled (0UL) /*!< Disable publishing */ -#define PWM_PUBLISH_STOPPED_EN_Enabled (1UL) /*!< Enable publishing */ +#define PWM_PUBLISH_STOPPED_EN_Disabled (0x0UL) /*!< Disable publishing */ +#define PWM_PUBLISH_STOPPED_EN_Enabled (0x1UL) /*!< Enable publishing */ /* Bits 7..0 : DPPI channel that event STOPPED will publish to */ #define PWM_PUBLISH_STOPPED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ @@ -5251,8 +5251,8 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 31 : */ #define PWM_PUBLISH_SEQSTARTED_EN_Pos (31UL) /*!< Position of EN field. */ #define PWM_PUBLISH_SEQSTARTED_EN_Msk (0x1UL << PWM_PUBLISH_SEQSTARTED_EN_Pos) /*!< Bit mask of EN field. */ -#define PWM_PUBLISH_SEQSTARTED_EN_Disabled (0UL) /*!< Disable publishing */ -#define PWM_PUBLISH_SEQSTARTED_EN_Enabled (1UL) /*!< Enable publishing */ +#define PWM_PUBLISH_SEQSTARTED_EN_Disabled (0x0UL) /*!< Disable publishing */ +#define PWM_PUBLISH_SEQSTARTED_EN_Enabled (0x1UL) /*!< Enable publishing */ /* Bits 7..0 : DPPI channel that event SEQSTARTED[n] will publish to */ #define PWM_PUBLISH_SEQSTARTED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ @@ -5264,8 +5264,8 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 31 : */ #define PWM_PUBLISH_SEQEND_EN_Pos (31UL) /*!< Position of EN field. */ #define PWM_PUBLISH_SEQEND_EN_Msk (0x1UL << PWM_PUBLISH_SEQEND_EN_Pos) /*!< Bit mask of EN field. */ -#define PWM_PUBLISH_SEQEND_EN_Disabled (0UL) /*!< Disable publishing */ -#define PWM_PUBLISH_SEQEND_EN_Enabled (1UL) /*!< Enable publishing */ +#define PWM_PUBLISH_SEQEND_EN_Disabled (0x0UL) /*!< Disable publishing */ +#define PWM_PUBLISH_SEQEND_EN_Enabled (0x1UL) /*!< Enable publishing */ /* Bits 7..0 : DPPI channel that event SEQEND[n] will publish to */ #define PWM_PUBLISH_SEQEND_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ @@ -5277,8 +5277,8 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 31 : */ #define PWM_PUBLISH_PWMPERIODEND_EN_Pos (31UL) /*!< Position of EN field. */ #define PWM_PUBLISH_PWMPERIODEND_EN_Msk (0x1UL << PWM_PUBLISH_PWMPERIODEND_EN_Pos) /*!< Bit mask of EN field. */ -#define PWM_PUBLISH_PWMPERIODEND_EN_Disabled (0UL) /*!< Disable publishing */ -#define PWM_PUBLISH_PWMPERIODEND_EN_Enabled (1UL) /*!< Enable publishing */ +#define PWM_PUBLISH_PWMPERIODEND_EN_Disabled (0x0UL) /*!< Disable publishing */ +#define PWM_PUBLISH_PWMPERIODEND_EN_Enabled (0x1UL) /*!< Enable publishing */ /* Bits 7..0 : DPPI channel that event PWMPERIODEND will publish to */ #define PWM_PUBLISH_PWMPERIODEND_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ @@ -5290,8 +5290,8 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 31 : */ #define PWM_PUBLISH_LOOPSDONE_EN_Pos (31UL) /*!< Position of EN field. */ #define PWM_PUBLISH_LOOPSDONE_EN_Msk (0x1UL << PWM_PUBLISH_LOOPSDONE_EN_Pos) /*!< Bit mask of EN field. */ -#define PWM_PUBLISH_LOOPSDONE_EN_Disabled (0UL) /*!< Disable publishing */ -#define PWM_PUBLISH_LOOPSDONE_EN_Enabled (1UL) /*!< Enable publishing */ +#define PWM_PUBLISH_LOOPSDONE_EN_Disabled (0x0UL) /*!< Disable publishing */ +#define PWM_PUBLISH_LOOPSDONE_EN_Enabled (0x1UL) /*!< Enable publishing */ /* Bits 7..0 : DPPI channel that event LOOPSDONE will publish to */ #define PWM_PUBLISH_LOOPSDONE_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ @@ -5303,32 +5303,32 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 4 : Shortcut between event LOOPSDONE and task STOP */ #define PWM_SHORTS_LOOPSDONE_STOP_Pos (4UL) /*!< Position of LOOPSDONE_STOP field. */ #define PWM_SHORTS_LOOPSDONE_STOP_Msk (0x1UL << PWM_SHORTS_LOOPSDONE_STOP_Pos) /*!< Bit mask of LOOPSDONE_STOP field. */ -#define PWM_SHORTS_LOOPSDONE_STOP_Disabled (0UL) /*!< Disable shortcut */ -#define PWM_SHORTS_LOOPSDONE_STOP_Enabled (1UL) /*!< Enable shortcut */ +#define PWM_SHORTS_LOOPSDONE_STOP_Disabled (0x0UL) /*!< Disable shortcut */ +#define PWM_SHORTS_LOOPSDONE_STOP_Enabled (0x1UL) /*!< Enable shortcut */ /* Bit 3 : Shortcut between event LOOPSDONE and task SEQSTART[1] */ #define PWM_SHORTS_LOOPSDONE_SEQSTART1_Pos (3UL) /*!< Position of LOOPSDONE_SEQSTART1 field. */ #define PWM_SHORTS_LOOPSDONE_SEQSTART1_Msk (0x1UL << PWM_SHORTS_LOOPSDONE_SEQSTART1_Pos) /*!< Bit mask of LOOPSDONE_SEQSTART1 field. */ -#define PWM_SHORTS_LOOPSDONE_SEQSTART1_Disabled (0UL) /*!< Disable shortcut */ -#define PWM_SHORTS_LOOPSDONE_SEQSTART1_Enabled (1UL) /*!< Enable shortcut */ +#define PWM_SHORTS_LOOPSDONE_SEQSTART1_Disabled (0x0UL) /*!< Disable shortcut */ +#define PWM_SHORTS_LOOPSDONE_SEQSTART1_Enabled (0x1UL) /*!< Enable shortcut */ /* Bit 2 : Shortcut between event LOOPSDONE and task SEQSTART[0] */ #define PWM_SHORTS_LOOPSDONE_SEQSTART0_Pos (2UL) /*!< Position of LOOPSDONE_SEQSTART0 field. */ #define PWM_SHORTS_LOOPSDONE_SEQSTART0_Msk (0x1UL << PWM_SHORTS_LOOPSDONE_SEQSTART0_Pos) /*!< Bit mask of LOOPSDONE_SEQSTART0 field. */ -#define PWM_SHORTS_LOOPSDONE_SEQSTART0_Disabled (0UL) /*!< Disable shortcut */ -#define PWM_SHORTS_LOOPSDONE_SEQSTART0_Enabled (1UL) /*!< Enable shortcut */ +#define PWM_SHORTS_LOOPSDONE_SEQSTART0_Disabled (0x0UL) /*!< Disable shortcut */ +#define PWM_SHORTS_LOOPSDONE_SEQSTART0_Enabled (0x1UL) /*!< Enable shortcut */ /* Bit 1 : Shortcut between event SEQEND[1] and task STOP */ #define PWM_SHORTS_SEQEND1_STOP_Pos (1UL) /*!< Position of SEQEND1_STOP field. */ #define PWM_SHORTS_SEQEND1_STOP_Msk (0x1UL << PWM_SHORTS_SEQEND1_STOP_Pos) /*!< Bit mask of SEQEND1_STOP field. */ -#define PWM_SHORTS_SEQEND1_STOP_Disabled (0UL) /*!< Disable shortcut */ -#define PWM_SHORTS_SEQEND1_STOP_Enabled (1UL) /*!< Enable shortcut */ +#define PWM_SHORTS_SEQEND1_STOP_Disabled (0x0UL) /*!< Disable shortcut */ +#define PWM_SHORTS_SEQEND1_STOP_Enabled (0x1UL) /*!< Enable shortcut */ /* Bit 0 : Shortcut between event SEQEND[0] and task STOP */ #define PWM_SHORTS_SEQEND0_STOP_Pos (0UL) /*!< Position of SEQEND0_STOP field. */ #define PWM_SHORTS_SEQEND0_STOP_Msk (0x1UL << PWM_SHORTS_SEQEND0_STOP_Pos) /*!< Bit mask of SEQEND0_STOP field. */ -#define PWM_SHORTS_SEQEND0_STOP_Disabled (0UL) /*!< Disable shortcut */ -#define PWM_SHORTS_SEQEND0_STOP_Enabled (1UL) /*!< Enable shortcut */ +#define PWM_SHORTS_SEQEND0_STOP_Disabled (0x0UL) /*!< Disable shortcut */ +#define PWM_SHORTS_SEQEND0_STOP_Enabled (0x1UL) /*!< Enable shortcut */ /* Register: PWM_INTEN */ /* Description: Enable or disable interrupt */ @@ -5336,44 +5336,44 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 7 : Enable or disable interrupt for event LOOPSDONE */ #define PWM_INTEN_LOOPSDONE_Pos (7UL) /*!< Position of LOOPSDONE field. */ #define PWM_INTEN_LOOPSDONE_Msk (0x1UL << PWM_INTEN_LOOPSDONE_Pos) /*!< Bit mask of LOOPSDONE field. */ -#define PWM_INTEN_LOOPSDONE_Disabled (0UL) /*!< Disable */ -#define PWM_INTEN_LOOPSDONE_Enabled (1UL) /*!< Enable */ +#define PWM_INTEN_LOOPSDONE_Disabled (0x0UL) /*!< Disable */ +#define PWM_INTEN_LOOPSDONE_Enabled (0x1UL) /*!< Enable */ /* Bit 6 : Enable or disable interrupt for event PWMPERIODEND */ #define PWM_INTEN_PWMPERIODEND_Pos (6UL) /*!< Position of PWMPERIODEND field. */ #define PWM_INTEN_PWMPERIODEND_Msk (0x1UL << PWM_INTEN_PWMPERIODEND_Pos) /*!< Bit mask of PWMPERIODEND field. */ -#define PWM_INTEN_PWMPERIODEND_Disabled (0UL) /*!< Disable */ -#define PWM_INTEN_PWMPERIODEND_Enabled (1UL) /*!< Enable */ +#define PWM_INTEN_PWMPERIODEND_Disabled (0x0UL) /*!< Disable */ +#define PWM_INTEN_PWMPERIODEND_Enabled (0x1UL) /*!< Enable */ /* Bit 5 : Enable or disable interrupt for event SEQEND[1] */ #define PWM_INTEN_SEQEND1_Pos (5UL) /*!< Position of SEQEND1 field. */ #define PWM_INTEN_SEQEND1_Msk (0x1UL << PWM_INTEN_SEQEND1_Pos) /*!< Bit mask of SEQEND1 field. */ -#define PWM_INTEN_SEQEND1_Disabled (0UL) /*!< Disable */ -#define PWM_INTEN_SEQEND1_Enabled (1UL) /*!< Enable */ +#define PWM_INTEN_SEQEND1_Disabled (0x0UL) /*!< Disable */ +#define PWM_INTEN_SEQEND1_Enabled (0x1UL) /*!< Enable */ /* Bit 4 : Enable or disable interrupt for event SEQEND[0] */ #define PWM_INTEN_SEQEND0_Pos (4UL) /*!< Position of SEQEND0 field. */ #define PWM_INTEN_SEQEND0_Msk (0x1UL << PWM_INTEN_SEQEND0_Pos) /*!< Bit mask of SEQEND0 field. */ -#define PWM_INTEN_SEQEND0_Disabled (0UL) /*!< Disable */ -#define PWM_INTEN_SEQEND0_Enabled (1UL) /*!< Enable */ +#define PWM_INTEN_SEQEND0_Disabled (0x0UL) /*!< Disable */ +#define PWM_INTEN_SEQEND0_Enabled (0x1UL) /*!< Enable */ /* Bit 3 : Enable or disable interrupt for event SEQSTARTED[1] */ #define PWM_INTEN_SEQSTARTED1_Pos (3UL) /*!< Position of SEQSTARTED1 field. */ #define PWM_INTEN_SEQSTARTED1_Msk (0x1UL << PWM_INTEN_SEQSTARTED1_Pos) /*!< Bit mask of SEQSTARTED1 field. */ -#define PWM_INTEN_SEQSTARTED1_Disabled (0UL) /*!< Disable */ -#define PWM_INTEN_SEQSTARTED1_Enabled (1UL) /*!< Enable */ +#define PWM_INTEN_SEQSTARTED1_Disabled (0x0UL) /*!< Disable */ +#define PWM_INTEN_SEQSTARTED1_Enabled (0x1UL) /*!< Enable */ /* Bit 2 : Enable or disable interrupt for event SEQSTARTED[0] */ #define PWM_INTEN_SEQSTARTED0_Pos (2UL) /*!< Position of SEQSTARTED0 field. */ #define PWM_INTEN_SEQSTARTED0_Msk (0x1UL << PWM_INTEN_SEQSTARTED0_Pos) /*!< Bit mask of SEQSTARTED0 field. */ -#define PWM_INTEN_SEQSTARTED0_Disabled (0UL) /*!< Disable */ -#define PWM_INTEN_SEQSTARTED0_Enabled (1UL) /*!< Enable */ +#define PWM_INTEN_SEQSTARTED0_Disabled (0x0UL) /*!< Disable */ +#define PWM_INTEN_SEQSTARTED0_Enabled (0x1UL) /*!< Enable */ /* Bit 1 : Enable or disable interrupt for event STOPPED */ #define PWM_INTEN_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ #define PWM_INTEN_STOPPED_Msk (0x1UL << PWM_INTEN_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ -#define PWM_INTEN_STOPPED_Disabled (0UL) /*!< Disable */ -#define PWM_INTEN_STOPPED_Enabled (1UL) /*!< Enable */ +#define PWM_INTEN_STOPPED_Disabled (0x0UL) /*!< Disable */ +#define PWM_INTEN_STOPPED_Enabled (0x1UL) /*!< Enable */ /* Register: PWM_INTENSET */ /* Description: Enable interrupt */ @@ -5381,51 +5381,51 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 7 : Write '1' to enable interrupt for event LOOPSDONE */ #define PWM_INTENSET_LOOPSDONE_Pos (7UL) /*!< Position of LOOPSDONE field. */ #define PWM_INTENSET_LOOPSDONE_Msk (0x1UL << PWM_INTENSET_LOOPSDONE_Pos) /*!< Bit mask of LOOPSDONE field. */ -#define PWM_INTENSET_LOOPSDONE_Disabled (0UL) /*!< Read: Disabled */ -#define PWM_INTENSET_LOOPSDONE_Enabled (1UL) /*!< Read: Enabled */ -#define PWM_INTENSET_LOOPSDONE_Set (1UL) /*!< Enable */ +#define PWM_INTENSET_LOOPSDONE_Disabled (0x0UL) /*!< Read: Disabled */ +#define PWM_INTENSET_LOOPSDONE_Enabled (0x1UL) /*!< Read: Enabled */ +#define PWM_INTENSET_LOOPSDONE_Set (0x1UL) /*!< Enable */ /* Bit 6 : Write '1' to enable interrupt for event PWMPERIODEND */ #define PWM_INTENSET_PWMPERIODEND_Pos (6UL) /*!< Position of PWMPERIODEND field. */ #define PWM_INTENSET_PWMPERIODEND_Msk (0x1UL << PWM_INTENSET_PWMPERIODEND_Pos) /*!< Bit mask of PWMPERIODEND field. */ -#define PWM_INTENSET_PWMPERIODEND_Disabled (0UL) /*!< Read: Disabled */ -#define PWM_INTENSET_PWMPERIODEND_Enabled (1UL) /*!< Read: Enabled */ -#define PWM_INTENSET_PWMPERIODEND_Set (1UL) /*!< Enable */ +#define PWM_INTENSET_PWMPERIODEND_Disabled (0x0UL) /*!< Read: Disabled */ +#define PWM_INTENSET_PWMPERIODEND_Enabled (0x1UL) /*!< Read: Enabled */ +#define PWM_INTENSET_PWMPERIODEND_Set (0x1UL) /*!< Enable */ /* Bit 5 : Write '1' to enable interrupt for event SEQEND[1] */ #define PWM_INTENSET_SEQEND1_Pos (5UL) /*!< Position of SEQEND1 field. */ #define PWM_INTENSET_SEQEND1_Msk (0x1UL << PWM_INTENSET_SEQEND1_Pos) /*!< Bit mask of SEQEND1 field. */ -#define PWM_INTENSET_SEQEND1_Disabled (0UL) /*!< Read: Disabled */ -#define PWM_INTENSET_SEQEND1_Enabled (1UL) /*!< Read: Enabled */ -#define PWM_INTENSET_SEQEND1_Set (1UL) /*!< Enable */ +#define PWM_INTENSET_SEQEND1_Disabled (0x0UL) /*!< Read: Disabled */ +#define PWM_INTENSET_SEQEND1_Enabled (0x1UL) /*!< Read: Enabled */ +#define PWM_INTENSET_SEQEND1_Set (0x1UL) /*!< Enable */ /* Bit 4 : Write '1' to enable interrupt for event SEQEND[0] */ #define PWM_INTENSET_SEQEND0_Pos (4UL) /*!< Position of SEQEND0 field. */ #define PWM_INTENSET_SEQEND0_Msk (0x1UL << PWM_INTENSET_SEQEND0_Pos) /*!< Bit mask of SEQEND0 field. */ -#define PWM_INTENSET_SEQEND0_Disabled (0UL) /*!< Read: Disabled */ -#define PWM_INTENSET_SEQEND0_Enabled (1UL) /*!< Read: Enabled */ -#define PWM_INTENSET_SEQEND0_Set (1UL) /*!< Enable */ +#define PWM_INTENSET_SEQEND0_Disabled (0x0UL) /*!< Read: Disabled */ +#define PWM_INTENSET_SEQEND0_Enabled (0x1UL) /*!< Read: Enabled */ +#define PWM_INTENSET_SEQEND0_Set (0x1UL) /*!< Enable */ /* Bit 3 : Write '1' to enable interrupt for event SEQSTARTED[1] */ #define PWM_INTENSET_SEQSTARTED1_Pos (3UL) /*!< Position of SEQSTARTED1 field. */ #define PWM_INTENSET_SEQSTARTED1_Msk (0x1UL << PWM_INTENSET_SEQSTARTED1_Pos) /*!< Bit mask of SEQSTARTED1 field. */ -#define PWM_INTENSET_SEQSTARTED1_Disabled (0UL) /*!< Read: Disabled */ -#define PWM_INTENSET_SEQSTARTED1_Enabled (1UL) /*!< Read: Enabled */ -#define PWM_INTENSET_SEQSTARTED1_Set (1UL) /*!< Enable */ +#define PWM_INTENSET_SEQSTARTED1_Disabled (0x0UL) /*!< Read: Disabled */ +#define PWM_INTENSET_SEQSTARTED1_Enabled (0x1UL) /*!< Read: Enabled */ +#define PWM_INTENSET_SEQSTARTED1_Set (0x1UL) /*!< Enable */ /* Bit 2 : Write '1' to enable interrupt for event SEQSTARTED[0] */ #define PWM_INTENSET_SEQSTARTED0_Pos (2UL) /*!< Position of SEQSTARTED0 field. */ #define PWM_INTENSET_SEQSTARTED0_Msk (0x1UL << PWM_INTENSET_SEQSTARTED0_Pos) /*!< Bit mask of SEQSTARTED0 field. */ -#define PWM_INTENSET_SEQSTARTED0_Disabled (0UL) /*!< Read: Disabled */ -#define PWM_INTENSET_SEQSTARTED0_Enabled (1UL) /*!< Read: Enabled */ -#define PWM_INTENSET_SEQSTARTED0_Set (1UL) /*!< Enable */ +#define PWM_INTENSET_SEQSTARTED0_Disabled (0x0UL) /*!< Read: Disabled */ +#define PWM_INTENSET_SEQSTARTED0_Enabled (0x1UL) /*!< Read: Enabled */ +#define PWM_INTENSET_SEQSTARTED0_Set (0x1UL) /*!< Enable */ /* Bit 1 : Write '1' to enable interrupt for event STOPPED */ #define PWM_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ #define PWM_INTENSET_STOPPED_Msk (0x1UL << PWM_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ -#define PWM_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */ -#define PWM_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */ -#define PWM_INTENSET_STOPPED_Set (1UL) /*!< Enable */ +#define PWM_INTENSET_STOPPED_Disabled (0x0UL) /*!< Read: Disabled */ +#define PWM_INTENSET_STOPPED_Enabled (0x1UL) /*!< Read: Enabled */ +#define PWM_INTENSET_STOPPED_Set (0x1UL) /*!< Enable */ /* Register: PWM_INTENCLR */ /* Description: Disable interrupt */ @@ -5433,51 +5433,51 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 7 : Write '1' to disable interrupt for event LOOPSDONE */ #define PWM_INTENCLR_LOOPSDONE_Pos (7UL) /*!< Position of LOOPSDONE field. */ #define PWM_INTENCLR_LOOPSDONE_Msk (0x1UL << PWM_INTENCLR_LOOPSDONE_Pos) /*!< Bit mask of LOOPSDONE field. */ -#define PWM_INTENCLR_LOOPSDONE_Disabled (0UL) /*!< Read: Disabled */ -#define PWM_INTENCLR_LOOPSDONE_Enabled (1UL) /*!< Read: Enabled */ -#define PWM_INTENCLR_LOOPSDONE_Clear (1UL) /*!< Disable */ +#define PWM_INTENCLR_LOOPSDONE_Disabled (0x0UL) /*!< Read: Disabled */ +#define PWM_INTENCLR_LOOPSDONE_Enabled (0x1UL) /*!< Read: Enabled */ +#define PWM_INTENCLR_LOOPSDONE_Clear (0x1UL) /*!< Disable */ /* Bit 6 : Write '1' to disable interrupt for event PWMPERIODEND */ #define PWM_INTENCLR_PWMPERIODEND_Pos (6UL) /*!< Position of PWMPERIODEND field. */ #define PWM_INTENCLR_PWMPERIODEND_Msk (0x1UL << PWM_INTENCLR_PWMPERIODEND_Pos) /*!< Bit mask of PWMPERIODEND field. */ -#define PWM_INTENCLR_PWMPERIODEND_Disabled (0UL) /*!< Read: Disabled */ -#define PWM_INTENCLR_PWMPERIODEND_Enabled (1UL) /*!< Read: Enabled */ -#define PWM_INTENCLR_PWMPERIODEND_Clear (1UL) /*!< Disable */ +#define PWM_INTENCLR_PWMPERIODEND_Disabled (0x0UL) /*!< Read: Disabled */ +#define PWM_INTENCLR_PWMPERIODEND_Enabled (0x1UL) /*!< Read: Enabled */ +#define PWM_INTENCLR_PWMPERIODEND_Clear (0x1UL) /*!< Disable */ /* Bit 5 : Write '1' to disable interrupt for event SEQEND[1] */ #define PWM_INTENCLR_SEQEND1_Pos (5UL) /*!< Position of SEQEND1 field. */ #define PWM_INTENCLR_SEQEND1_Msk (0x1UL << PWM_INTENCLR_SEQEND1_Pos) /*!< Bit mask of SEQEND1 field. */ -#define PWM_INTENCLR_SEQEND1_Disabled (0UL) /*!< Read: Disabled */ -#define PWM_INTENCLR_SEQEND1_Enabled (1UL) /*!< Read: Enabled */ -#define PWM_INTENCLR_SEQEND1_Clear (1UL) /*!< Disable */ +#define PWM_INTENCLR_SEQEND1_Disabled (0x0UL) /*!< Read: Disabled */ +#define PWM_INTENCLR_SEQEND1_Enabled (0x1UL) /*!< Read: Enabled */ +#define PWM_INTENCLR_SEQEND1_Clear (0x1UL) /*!< Disable */ /* Bit 4 : Write '1' to disable interrupt for event SEQEND[0] */ #define PWM_INTENCLR_SEQEND0_Pos (4UL) /*!< Position of SEQEND0 field. */ #define PWM_INTENCLR_SEQEND0_Msk (0x1UL << PWM_INTENCLR_SEQEND0_Pos) /*!< Bit mask of SEQEND0 field. */ -#define PWM_INTENCLR_SEQEND0_Disabled (0UL) /*!< Read: Disabled */ -#define PWM_INTENCLR_SEQEND0_Enabled (1UL) /*!< Read: Enabled */ -#define PWM_INTENCLR_SEQEND0_Clear (1UL) /*!< Disable */ +#define PWM_INTENCLR_SEQEND0_Disabled (0x0UL) /*!< Read: Disabled */ +#define PWM_INTENCLR_SEQEND0_Enabled (0x1UL) /*!< Read: Enabled */ +#define PWM_INTENCLR_SEQEND0_Clear (0x1UL) /*!< Disable */ /* Bit 3 : Write '1' to disable interrupt for event SEQSTARTED[1] */ #define PWM_INTENCLR_SEQSTARTED1_Pos (3UL) /*!< Position of SEQSTARTED1 field. */ #define PWM_INTENCLR_SEQSTARTED1_Msk (0x1UL << PWM_INTENCLR_SEQSTARTED1_Pos) /*!< Bit mask of SEQSTARTED1 field. */ -#define PWM_INTENCLR_SEQSTARTED1_Disabled (0UL) /*!< Read: Disabled */ -#define PWM_INTENCLR_SEQSTARTED1_Enabled (1UL) /*!< Read: Enabled */ -#define PWM_INTENCLR_SEQSTARTED1_Clear (1UL) /*!< Disable */ +#define PWM_INTENCLR_SEQSTARTED1_Disabled (0x0UL) /*!< Read: Disabled */ +#define PWM_INTENCLR_SEQSTARTED1_Enabled (0x1UL) /*!< Read: Enabled */ +#define PWM_INTENCLR_SEQSTARTED1_Clear (0x1UL) /*!< Disable */ /* Bit 2 : Write '1' to disable interrupt for event SEQSTARTED[0] */ #define PWM_INTENCLR_SEQSTARTED0_Pos (2UL) /*!< Position of SEQSTARTED0 field. */ #define PWM_INTENCLR_SEQSTARTED0_Msk (0x1UL << PWM_INTENCLR_SEQSTARTED0_Pos) /*!< Bit mask of SEQSTARTED0 field. */ -#define PWM_INTENCLR_SEQSTARTED0_Disabled (0UL) /*!< Read: Disabled */ -#define PWM_INTENCLR_SEQSTARTED0_Enabled (1UL) /*!< Read: Enabled */ -#define PWM_INTENCLR_SEQSTARTED0_Clear (1UL) /*!< Disable */ +#define PWM_INTENCLR_SEQSTARTED0_Disabled (0x0UL) /*!< Read: Disabled */ +#define PWM_INTENCLR_SEQSTARTED0_Enabled (0x1UL) /*!< Read: Enabled */ +#define PWM_INTENCLR_SEQSTARTED0_Clear (0x1UL) /*!< Disable */ /* Bit 1 : Write '1' to disable interrupt for event STOPPED */ #define PWM_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ #define PWM_INTENCLR_STOPPED_Msk (0x1UL << PWM_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ -#define PWM_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */ -#define PWM_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */ -#define PWM_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */ +#define PWM_INTENCLR_STOPPED_Disabled (0x0UL) /*!< Read: Disabled */ +#define PWM_INTENCLR_STOPPED_Enabled (0x1UL) /*!< Read: Enabled */ +#define PWM_INTENCLR_STOPPED_Clear (0x1UL) /*!< Disable */ /* Register: PWM_ENABLE */ /* Description: PWM module enable register */ @@ -5485,8 +5485,8 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 0 : Enable or disable PWM module */ #define PWM_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ #define PWM_ENABLE_ENABLE_Msk (0x1UL << PWM_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ -#define PWM_ENABLE_ENABLE_Disabled (0UL) /*!< Disabled */ -#define PWM_ENABLE_ENABLE_Enabled (1UL) /*!< Enable */ +#define PWM_ENABLE_ENABLE_Disabled (0x0UL) /*!< Disabled */ +#define PWM_ENABLE_ENABLE_Enabled (0x1UL) /*!< Enable */ /* Register: PWM_MODE */ /* Description: Selects operating mode of the wave counter */ @@ -5494,8 +5494,8 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 0 : Selects up mode or up-and-down mode for the counter */ #define PWM_MODE_UPDOWN_Pos (0UL) /*!< Position of UPDOWN field. */ #define PWM_MODE_UPDOWN_Msk (0x1UL << PWM_MODE_UPDOWN_Pos) /*!< Bit mask of UPDOWN field. */ -#define PWM_MODE_UPDOWN_Up (0UL) /*!< Up counter, edge-aligned PWM duty cycle */ -#define PWM_MODE_UPDOWN_UpAndDown (1UL) /*!< Up and down counter, center-aligned PWM duty cycle */ +#define PWM_MODE_UPDOWN_Up (0x0UL) /*!< Up counter, edge-aligned PWM duty cycle */ +#define PWM_MODE_UPDOWN_UpAndDown (0x1UL) /*!< Up and down counter, center-aligned PWM duty cycle */ /* Register: PWM_COUNTERTOP */ /* Description: Value up to which the pulse generator counter counts */ @@ -5510,14 +5510,14 @@ POSSIBILITY OF SUCH DAMAGE. /* Bits 2..0 : Prescaler of PWM_CLK */ #define PWM_PRESCALER_PRESCALER_Pos (0UL) /*!< Position of PRESCALER field. */ #define PWM_PRESCALER_PRESCALER_Msk (0x7UL << PWM_PRESCALER_PRESCALER_Pos) /*!< Bit mask of PRESCALER field. */ -#define PWM_PRESCALER_PRESCALER_DIV_1 (0UL) /*!< Divide by 1 (16 MHz) */ -#define PWM_PRESCALER_PRESCALER_DIV_2 (1UL) /*!< Divide by 2 (8 MHz) */ -#define PWM_PRESCALER_PRESCALER_DIV_4 (2UL) /*!< Divide by 4 (4 MHz) */ -#define PWM_PRESCALER_PRESCALER_DIV_8 (3UL) /*!< Divide by 8 (2 MHz) */ -#define PWM_PRESCALER_PRESCALER_DIV_16 (4UL) /*!< Divide by 16 (1 MHz) */ -#define PWM_PRESCALER_PRESCALER_DIV_32 (5UL) /*!< Divide by 32 (500 kHz) */ -#define PWM_PRESCALER_PRESCALER_DIV_64 (6UL) /*!< Divide by 64 (250 kHz) */ -#define PWM_PRESCALER_PRESCALER_DIV_128 (7UL) /*!< Divide by 128 (125 kHz) */ +#define PWM_PRESCALER_PRESCALER_DIV_1 (0x0UL) /*!< Divide by 1 (16 MHz) */ +#define PWM_PRESCALER_PRESCALER_DIV_2 (0x1UL) /*!< Divide by 2 (8 MHz) */ +#define PWM_PRESCALER_PRESCALER_DIV_4 (0x2UL) /*!< Divide by 4 (4 MHz) */ +#define PWM_PRESCALER_PRESCALER_DIV_8 (0x3UL) /*!< Divide by 8 (2 MHz) */ +#define PWM_PRESCALER_PRESCALER_DIV_16 (0x4UL) /*!< Divide by 16 (1 MHz) */ +#define PWM_PRESCALER_PRESCALER_DIV_32 (0x5UL) /*!< Divide by 32 (500 kHz) */ +#define PWM_PRESCALER_PRESCALER_DIV_64 (0x6UL) /*!< Divide by 64 (250 kHz) */ +#define PWM_PRESCALER_PRESCALER_DIV_128 (0x7UL) /*!< Divide by 128 (125 kHz) */ /* Register: PWM_DECODER */ /* Description: Configuration of the decoder */ @@ -5525,16 +5525,16 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 8 : Selects source for advancing the active sequence */ #define PWM_DECODER_MODE_Pos (8UL) /*!< Position of MODE field. */ #define PWM_DECODER_MODE_Msk (0x1UL << PWM_DECODER_MODE_Pos) /*!< Bit mask of MODE field. */ -#define PWM_DECODER_MODE_RefreshCount (0UL) /*!< SEQ[n].REFRESH is used to determine loading internal compare registers */ -#define PWM_DECODER_MODE_NextStep (1UL) /*!< NEXTSTEP task causes a new value to be loaded to internal compare registers */ +#define PWM_DECODER_MODE_RefreshCount (0x0UL) /*!< SEQ[n].REFRESH is used to determine loading internal compare registers */ +#define PWM_DECODER_MODE_NextStep (0x1UL) /*!< NEXTSTEP task causes a new value to be loaded to internal compare registers */ /* Bits 1..0 : How a sequence is read from RAM and spread to the compare register */ #define PWM_DECODER_LOAD_Pos (0UL) /*!< Position of LOAD field. */ #define PWM_DECODER_LOAD_Msk (0x3UL << PWM_DECODER_LOAD_Pos) /*!< Bit mask of LOAD field. */ -#define PWM_DECODER_LOAD_Common (0UL) /*!< 1st half word (16-bit) used in all PWM channels 0..3 */ -#define PWM_DECODER_LOAD_Grouped (1UL) /*!< 1st half word (16-bit) used in channel 0..1; 2nd word in channel 2..3 */ -#define PWM_DECODER_LOAD_Individual (2UL) /*!< 1st half word (16-bit) in ch.0; 2nd in ch.1; ...; 4th in ch.3 */ -#define PWM_DECODER_LOAD_WaveForm (3UL) /*!< 1st half word (16-bit) in ch.0; 2nd in ch.1; ...; 4th in COUNTERTOP */ +#define PWM_DECODER_LOAD_Common (0x0UL) /*!< 1st half word (16-bit) used in all PWM channels 0..3 */ +#define PWM_DECODER_LOAD_Grouped (0x1UL) /*!< 1st half word (16-bit) used in channel 0..1; 2nd word in channel 2..3 */ +#define PWM_DECODER_LOAD_Individual (0x2UL) /*!< 1st half word (16-bit) in ch.0; 2nd in ch.1; ...; 4th in ch.3 */ +#define PWM_DECODER_LOAD_WaveForm (0x3UL) /*!< 1st half word (16-bit) in ch.0; 2nd in ch.1; ...; 4th in COUNTERTOP */ /* Register: PWM_LOOP */ /* Description: Number of playbacks of a loop */ @@ -5542,7 +5542,7 @@ POSSIBILITY OF SUCH DAMAGE. /* Bits 15..0 : Number of playbacks of pattern cycles */ #define PWM_LOOP_CNT_Pos (0UL) /*!< Position of CNT field. */ #define PWM_LOOP_CNT_Msk (0xFFFFUL << PWM_LOOP_CNT_Pos) /*!< Bit mask of CNT field. */ -#define PWM_LOOP_CNT_Disabled (0UL) /*!< Looping disabled (stop at the end of the sequence) */ +#define PWM_LOOP_CNT_Disabled (0x0000UL) /*!< Looping disabled (stop at the end of the sequence) */ /* Register: PWM_SEQ_PTR */ /* Description: Description cluster: Beginning address in RAM of this sequence */ @@ -5557,7 +5557,7 @@ POSSIBILITY OF SUCH DAMAGE. /* Bits 14..0 : Number of values (duty cycles) in this sequence */ #define PWM_SEQ_CNT_CNT_Pos (0UL) /*!< Position of CNT field. */ #define PWM_SEQ_CNT_CNT_Msk (0x7FFFUL << PWM_SEQ_CNT_CNT_Pos) /*!< Bit mask of CNT field. */ -#define PWM_SEQ_CNT_CNT_Disabled (0UL) /*!< Sequence is disabled, and shall not be started as it is empty */ +#define PWM_SEQ_CNT_CNT_Disabled (0x0000UL) /*!< Sequence is disabled, and shall not be started as it is empty */ /* Register: PWM_SEQ_REFRESH */ /* Description: Description cluster: Number of additional PWM periods between samples loaded into compare register */ @@ -5565,7 +5565,7 @@ POSSIBILITY OF SUCH DAMAGE. /* Bits 23..0 : Number of additional PWM periods between samples loaded into compare register (load every REFRESH.CNT+1 PWM periods) */ #define PWM_SEQ_REFRESH_CNT_Pos (0UL) /*!< Position of CNT field. */ #define PWM_SEQ_REFRESH_CNT_Msk (0xFFFFFFUL << PWM_SEQ_REFRESH_CNT_Pos) /*!< Bit mask of CNT field. */ -#define PWM_SEQ_REFRESH_CNT_Continuous (0UL) /*!< Update every PWM period */ +#define PWM_SEQ_REFRESH_CNT_Continuous (0x000000UL) /*!< Update every PWM period */ /* Register: PWM_SEQ_ENDDELAY */ /* Description: Description cluster: Time added after the sequence */ @@ -5580,8 +5580,8 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 31 : Connection */ #define PWM_PSEL_OUT_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ #define PWM_PSEL_OUT_CONNECT_Msk (0x1UL << PWM_PSEL_OUT_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ -#define PWM_PSEL_OUT_CONNECT_Connected (0UL) /*!< Connect */ -#define PWM_PSEL_OUT_CONNECT_Disconnected (1UL) /*!< Disconnect */ +#define PWM_PSEL_OUT_CONNECT_Connected (0x0UL) /*!< Connect */ +#define PWM_PSEL_OUT_CONNECT_Disconnected (0x1UL) /*!< Disconnect */ /* Bits 4..0 : Pin number */ #define PWM_PSEL_OUT_PIN_Pos (0UL) /*!< Position of PIN field. */ @@ -5597,7 +5597,7 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 0 : Enable System OFF mode */ #define REGULATORS_SYSTEMOFF_SYSTEMOFF_Pos (0UL) /*!< Position of SYSTEMOFF field. */ #define REGULATORS_SYSTEMOFF_SYSTEMOFF_Msk (0x1UL << REGULATORS_SYSTEMOFF_SYSTEMOFF_Pos) /*!< Bit mask of SYSTEMOFF field. */ -#define REGULATORS_SYSTEMOFF_SYSTEMOFF_Enable (1UL) /*!< Enable System OFF mode */ +#define REGULATORS_SYSTEMOFF_SYSTEMOFF_Enable (0x1UL) /*!< Enable System OFF mode */ /* Register: REGULATORS_EXTPOFCON */ /* Description: External power failure warning configuration */ @@ -5605,8 +5605,8 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 0 : Enable or disable external power failure warning */ #define REGULATORS_EXTPOFCON_POF_Pos (0UL) /*!< Position of POF field. */ #define REGULATORS_EXTPOFCON_POF_Msk (0x1UL << REGULATORS_EXTPOFCON_POF_Pos) /*!< Bit mask of POF field. */ -#define REGULATORS_EXTPOFCON_POF_Disabled (0UL) /*!< Disable */ -#define REGULATORS_EXTPOFCON_POF_Enabled (1UL) /*!< Enable */ +#define REGULATORS_EXTPOFCON_POF_Disabled (0x0UL) /*!< Disable */ +#define REGULATORS_EXTPOFCON_POF_Enabled (0x1UL) /*!< Enable */ /* Register: REGULATORS_DCDCEN */ /* Description: Enable DC/DC mode of the main voltage regulator. */ @@ -5614,8 +5614,8 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 0 : Enable DC/DC converter */ #define REGULATORS_DCDCEN_DCDCEN_Pos (0UL) /*!< Position of DCDCEN field. */ #define REGULATORS_DCDCEN_DCDCEN_Msk (0x1UL << REGULATORS_DCDCEN_DCDCEN_Pos) /*!< Bit mask of DCDCEN field. */ -#define REGULATORS_DCDCEN_DCDCEN_Disabled (0UL) /*!< DC/DC mode is disabled */ -#define REGULATORS_DCDCEN_DCDCEN_Enabled (1UL) /*!< DC/DC mode is enabled */ +#define REGULATORS_DCDCEN_DCDCEN_Disabled (0x0UL) /*!< DC/DC mode is disabled */ +#define REGULATORS_DCDCEN_DCDCEN_Enabled (0x1UL) /*!< DC/DC mode is enabled */ /* Peripheral: RTC */ @@ -5627,7 +5627,7 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 0 : Start RTC counter */ #define RTC_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */ #define RTC_TASKS_START_TASKS_START_Msk (0x1UL << RTC_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */ -#define RTC_TASKS_START_TASKS_START_Trigger (1UL) /*!< Trigger task */ +#define RTC_TASKS_START_TASKS_START_Trigger (0x1UL) /*!< Trigger task */ /* Register: RTC_TASKS_STOP */ /* Description: Stop RTC counter */ @@ -5635,7 +5635,7 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 0 : Stop RTC counter */ #define RTC_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */ #define RTC_TASKS_STOP_TASKS_STOP_Msk (0x1UL << RTC_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */ -#define RTC_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */ +#define RTC_TASKS_STOP_TASKS_STOP_Trigger (0x1UL) /*!< Trigger task */ /* Register: RTC_TASKS_CLEAR */ /* Description: Clear RTC counter */ @@ -5643,7 +5643,7 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 0 : Clear RTC counter */ #define RTC_TASKS_CLEAR_TASKS_CLEAR_Pos (0UL) /*!< Position of TASKS_CLEAR field. */ #define RTC_TASKS_CLEAR_TASKS_CLEAR_Msk (0x1UL << RTC_TASKS_CLEAR_TASKS_CLEAR_Pos) /*!< Bit mask of TASKS_CLEAR field. */ -#define RTC_TASKS_CLEAR_TASKS_CLEAR_Trigger (1UL) /*!< Trigger task */ +#define RTC_TASKS_CLEAR_TASKS_CLEAR_Trigger (0x1UL) /*!< Trigger task */ /* Register: RTC_TASKS_TRIGOVRFLW */ /* Description: Set counter to 0xFFFFF0 */ @@ -5651,7 +5651,7 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 0 : Set counter to 0xFFFFF0 */ #define RTC_TASKS_TRIGOVRFLW_TASKS_TRIGOVRFLW_Pos (0UL) /*!< Position of TASKS_TRIGOVRFLW field. */ #define RTC_TASKS_TRIGOVRFLW_TASKS_TRIGOVRFLW_Msk (0x1UL << RTC_TASKS_TRIGOVRFLW_TASKS_TRIGOVRFLW_Pos) /*!< Bit mask of TASKS_TRIGOVRFLW field. */ -#define RTC_TASKS_TRIGOVRFLW_TASKS_TRIGOVRFLW_Trigger (1UL) /*!< Trigger task */ +#define RTC_TASKS_TRIGOVRFLW_TASKS_TRIGOVRFLW_Trigger (0x1UL) /*!< Trigger task */ /* Register: RTC_SUBSCRIBE_START */ /* Description: Subscribe configuration for task START */ @@ -5659,8 +5659,8 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 31 : */ #define RTC_SUBSCRIBE_START_EN_Pos (31UL) /*!< Position of EN field. */ #define RTC_SUBSCRIBE_START_EN_Msk (0x1UL << RTC_SUBSCRIBE_START_EN_Pos) /*!< Bit mask of EN field. */ -#define RTC_SUBSCRIBE_START_EN_Disabled (0UL) /*!< Disable subscription */ -#define RTC_SUBSCRIBE_START_EN_Enabled (1UL) /*!< Enable subscription */ +#define RTC_SUBSCRIBE_START_EN_Disabled (0x0UL) /*!< Disable subscription */ +#define RTC_SUBSCRIBE_START_EN_Enabled (0x1UL) /*!< Enable subscription */ /* Bits 7..0 : DPPI channel that task START will subscribe to */ #define RTC_SUBSCRIBE_START_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ @@ -5672,8 +5672,8 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 31 : */ #define RTC_SUBSCRIBE_STOP_EN_Pos (31UL) /*!< Position of EN field. */ #define RTC_SUBSCRIBE_STOP_EN_Msk (0x1UL << RTC_SUBSCRIBE_STOP_EN_Pos) /*!< Bit mask of EN field. */ -#define RTC_SUBSCRIBE_STOP_EN_Disabled (0UL) /*!< Disable subscription */ -#define RTC_SUBSCRIBE_STOP_EN_Enabled (1UL) /*!< Enable subscription */ +#define RTC_SUBSCRIBE_STOP_EN_Disabled (0x0UL) /*!< Disable subscription */ +#define RTC_SUBSCRIBE_STOP_EN_Enabled (0x1UL) /*!< Enable subscription */ /* Bits 7..0 : DPPI channel that task STOP will subscribe to */ #define RTC_SUBSCRIBE_STOP_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ @@ -5685,8 +5685,8 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 31 : */ #define RTC_SUBSCRIBE_CLEAR_EN_Pos (31UL) /*!< Position of EN field. */ #define RTC_SUBSCRIBE_CLEAR_EN_Msk (0x1UL << RTC_SUBSCRIBE_CLEAR_EN_Pos) /*!< Bit mask of EN field. */ -#define RTC_SUBSCRIBE_CLEAR_EN_Disabled (0UL) /*!< Disable subscription */ -#define RTC_SUBSCRIBE_CLEAR_EN_Enabled (1UL) /*!< Enable subscription */ +#define RTC_SUBSCRIBE_CLEAR_EN_Disabled (0x0UL) /*!< Disable subscription */ +#define RTC_SUBSCRIBE_CLEAR_EN_Enabled (0x1UL) /*!< Enable subscription */ /* Bits 7..0 : DPPI channel that task CLEAR will subscribe to */ #define RTC_SUBSCRIBE_CLEAR_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ @@ -5698,8 +5698,8 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 31 : */ #define RTC_SUBSCRIBE_TRIGOVRFLW_EN_Pos (31UL) /*!< Position of EN field. */ #define RTC_SUBSCRIBE_TRIGOVRFLW_EN_Msk (0x1UL << RTC_SUBSCRIBE_TRIGOVRFLW_EN_Pos) /*!< Bit mask of EN field. */ -#define RTC_SUBSCRIBE_TRIGOVRFLW_EN_Disabled (0UL) /*!< Disable subscription */ -#define RTC_SUBSCRIBE_TRIGOVRFLW_EN_Enabled (1UL) /*!< Enable subscription */ +#define RTC_SUBSCRIBE_TRIGOVRFLW_EN_Disabled (0x0UL) /*!< Disable subscription */ +#define RTC_SUBSCRIBE_TRIGOVRFLW_EN_Enabled (0x1UL) /*!< Enable subscription */ /* Bits 7..0 : DPPI channel that task TRIGOVRFLW will subscribe to */ #define RTC_SUBSCRIBE_TRIGOVRFLW_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ @@ -5711,8 +5711,8 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 0 : Event on counter increment */ #define RTC_EVENTS_TICK_EVENTS_TICK_Pos (0UL) /*!< Position of EVENTS_TICK field. */ #define RTC_EVENTS_TICK_EVENTS_TICK_Msk (0x1UL << RTC_EVENTS_TICK_EVENTS_TICK_Pos) /*!< Bit mask of EVENTS_TICK field. */ -#define RTC_EVENTS_TICK_EVENTS_TICK_NotGenerated (0UL) /*!< Event not generated */ -#define RTC_EVENTS_TICK_EVENTS_TICK_Generated (1UL) /*!< Event generated */ +#define RTC_EVENTS_TICK_EVENTS_TICK_NotGenerated (0x0UL) /*!< Event not generated */ +#define RTC_EVENTS_TICK_EVENTS_TICK_Generated (0x1UL) /*!< Event generated */ /* Register: RTC_EVENTS_OVRFLW */ /* Description: Event on counter overflow */ @@ -5720,8 +5720,8 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 0 : Event on counter overflow */ #define RTC_EVENTS_OVRFLW_EVENTS_OVRFLW_Pos (0UL) /*!< Position of EVENTS_OVRFLW field. */ #define RTC_EVENTS_OVRFLW_EVENTS_OVRFLW_Msk (0x1UL << RTC_EVENTS_OVRFLW_EVENTS_OVRFLW_Pos) /*!< Bit mask of EVENTS_OVRFLW field. */ -#define RTC_EVENTS_OVRFLW_EVENTS_OVRFLW_NotGenerated (0UL) /*!< Event not generated */ -#define RTC_EVENTS_OVRFLW_EVENTS_OVRFLW_Generated (1UL) /*!< Event generated */ +#define RTC_EVENTS_OVRFLW_EVENTS_OVRFLW_NotGenerated (0x0UL) /*!< Event not generated */ +#define RTC_EVENTS_OVRFLW_EVENTS_OVRFLW_Generated (0x1UL) /*!< Event generated */ /* Register: RTC_EVENTS_COMPARE */ /* Description: Description collection: Compare event on CC[n] match */ @@ -5729,8 +5729,8 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 0 : Compare event on CC[n] match */ #define RTC_EVENTS_COMPARE_EVENTS_COMPARE_Pos (0UL) /*!< Position of EVENTS_COMPARE field. */ #define RTC_EVENTS_COMPARE_EVENTS_COMPARE_Msk (0x1UL << RTC_EVENTS_COMPARE_EVENTS_COMPARE_Pos) /*!< Bit mask of EVENTS_COMPARE field. */ -#define RTC_EVENTS_COMPARE_EVENTS_COMPARE_NotGenerated (0UL) /*!< Event not generated */ -#define RTC_EVENTS_COMPARE_EVENTS_COMPARE_Generated (1UL) /*!< Event generated */ +#define RTC_EVENTS_COMPARE_EVENTS_COMPARE_NotGenerated (0x0UL) /*!< Event not generated */ +#define RTC_EVENTS_COMPARE_EVENTS_COMPARE_Generated (0x1UL) /*!< Event generated */ /* Register: RTC_PUBLISH_TICK */ /* Description: Publish configuration for event TICK */ @@ -5738,8 +5738,8 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 31 : */ #define RTC_PUBLISH_TICK_EN_Pos (31UL) /*!< Position of EN field. */ #define RTC_PUBLISH_TICK_EN_Msk (0x1UL << RTC_PUBLISH_TICK_EN_Pos) /*!< Bit mask of EN field. */ -#define RTC_PUBLISH_TICK_EN_Disabled (0UL) /*!< Disable publishing */ -#define RTC_PUBLISH_TICK_EN_Enabled (1UL) /*!< Enable publishing */ +#define RTC_PUBLISH_TICK_EN_Disabled (0x0UL) /*!< Disable publishing */ +#define RTC_PUBLISH_TICK_EN_Enabled (0x1UL) /*!< Enable publishing */ /* Bits 7..0 : DPPI channel that event TICK will publish to */ #define RTC_PUBLISH_TICK_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ @@ -5751,8 +5751,8 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 31 : */ #define RTC_PUBLISH_OVRFLW_EN_Pos (31UL) /*!< Position of EN field. */ #define RTC_PUBLISH_OVRFLW_EN_Msk (0x1UL << RTC_PUBLISH_OVRFLW_EN_Pos) /*!< Bit mask of EN field. */ -#define RTC_PUBLISH_OVRFLW_EN_Disabled (0UL) /*!< Disable publishing */ -#define RTC_PUBLISH_OVRFLW_EN_Enabled (1UL) /*!< Enable publishing */ +#define RTC_PUBLISH_OVRFLW_EN_Disabled (0x0UL) /*!< Disable publishing */ +#define RTC_PUBLISH_OVRFLW_EN_Enabled (0x1UL) /*!< Enable publishing */ /* Bits 7..0 : DPPI channel that event OVRFLW will publish to */ #define RTC_PUBLISH_OVRFLW_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ @@ -5764,8 +5764,8 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 31 : */ #define RTC_PUBLISH_COMPARE_EN_Pos (31UL) /*!< Position of EN field. */ #define RTC_PUBLISH_COMPARE_EN_Msk (0x1UL << RTC_PUBLISH_COMPARE_EN_Pos) /*!< Bit mask of EN field. */ -#define RTC_PUBLISH_COMPARE_EN_Disabled (0UL) /*!< Disable publishing */ -#define RTC_PUBLISH_COMPARE_EN_Enabled (1UL) /*!< Enable publishing */ +#define RTC_PUBLISH_COMPARE_EN_Disabled (0x0UL) /*!< Disable publishing */ +#define RTC_PUBLISH_COMPARE_EN_Enabled (0x1UL) /*!< Enable publishing */ /* Bits 7..0 : DPPI channel that event COMPARE[n] will publish to */ #define RTC_PUBLISH_COMPARE_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ @@ -5777,44 +5777,44 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 19 : Write '1' to enable interrupt for event COMPARE[3] */ #define RTC_INTENSET_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */ #define RTC_INTENSET_COMPARE3_Msk (0x1UL << RTC_INTENSET_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */ -#define RTC_INTENSET_COMPARE3_Disabled (0UL) /*!< Read: Disabled */ -#define RTC_INTENSET_COMPARE3_Enabled (1UL) /*!< Read: Enabled */ -#define RTC_INTENSET_COMPARE3_Set (1UL) /*!< Enable */ +#define RTC_INTENSET_COMPARE3_Disabled (0x0UL) /*!< Read: Disabled */ +#define RTC_INTENSET_COMPARE3_Enabled (0x1UL) /*!< Read: Enabled */ +#define RTC_INTENSET_COMPARE3_Set (0x1UL) /*!< Enable */ /* Bit 18 : Write '1' to enable interrupt for event COMPARE[2] */ #define RTC_INTENSET_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */ #define RTC_INTENSET_COMPARE2_Msk (0x1UL << RTC_INTENSET_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */ -#define RTC_INTENSET_COMPARE2_Disabled (0UL) /*!< Read: Disabled */ -#define RTC_INTENSET_COMPARE2_Enabled (1UL) /*!< Read: Enabled */ -#define RTC_INTENSET_COMPARE2_Set (1UL) /*!< Enable */ +#define RTC_INTENSET_COMPARE2_Disabled (0x0UL) /*!< Read: Disabled */ +#define RTC_INTENSET_COMPARE2_Enabled (0x1UL) /*!< Read: Enabled */ +#define RTC_INTENSET_COMPARE2_Set (0x1UL) /*!< Enable */ /* Bit 17 : Write '1' to enable interrupt for event COMPARE[1] */ #define RTC_INTENSET_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */ #define RTC_INTENSET_COMPARE1_Msk (0x1UL << RTC_INTENSET_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */ -#define RTC_INTENSET_COMPARE1_Disabled (0UL) /*!< Read: Disabled */ -#define RTC_INTENSET_COMPARE1_Enabled (1UL) /*!< Read: Enabled */ -#define RTC_INTENSET_COMPARE1_Set (1UL) /*!< Enable */ +#define RTC_INTENSET_COMPARE1_Disabled (0x0UL) /*!< Read: Disabled */ +#define RTC_INTENSET_COMPARE1_Enabled (0x1UL) /*!< Read: Enabled */ +#define RTC_INTENSET_COMPARE1_Set (0x1UL) /*!< Enable */ /* Bit 16 : Write '1' to enable interrupt for event COMPARE[0] */ #define RTC_INTENSET_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */ #define RTC_INTENSET_COMPARE0_Msk (0x1UL << RTC_INTENSET_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */ -#define RTC_INTENSET_COMPARE0_Disabled (0UL) /*!< Read: Disabled */ -#define RTC_INTENSET_COMPARE0_Enabled (1UL) /*!< Read: Enabled */ -#define RTC_INTENSET_COMPARE0_Set (1UL) /*!< Enable */ +#define RTC_INTENSET_COMPARE0_Disabled (0x0UL) /*!< Read: Disabled */ +#define RTC_INTENSET_COMPARE0_Enabled (0x1UL) /*!< Read: Enabled */ +#define RTC_INTENSET_COMPARE0_Set (0x1UL) /*!< Enable */ /* Bit 1 : Write '1' to enable interrupt for event OVRFLW */ #define RTC_INTENSET_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */ #define RTC_INTENSET_OVRFLW_Msk (0x1UL << RTC_INTENSET_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */ -#define RTC_INTENSET_OVRFLW_Disabled (0UL) /*!< Read: Disabled */ -#define RTC_INTENSET_OVRFLW_Enabled (1UL) /*!< Read: Enabled */ -#define RTC_INTENSET_OVRFLW_Set (1UL) /*!< Enable */ +#define RTC_INTENSET_OVRFLW_Disabled (0x0UL) /*!< Read: Disabled */ +#define RTC_INTENSET_OVRFLW_Enabled (0x1UL) /*!< Read: Enabled */ +#define RTC_INTENSET_OVRFLW_Set (0x1UL) /*!< Enable */ /* Bit 0 : Write '1' to enable interrupt for event TICK */ #define RTC_INTENSET_TICK_Pos (0UL) /*!< Position of TICK field. */ #define RTC_INTENSET_TICK_Msk (0x1UL << RTC_INTENSET_TICK_Pos) /*!< Bit mask of TICK field. */ -#define RTC_INTENSET_TICK_Disabled (0UL) /*!< Read: Disabled */ -#define RTC_INTENSET_TICK_Enabled (1UL) /*!< Read: Enabled */ -#define RTC_INTENSET_TICK_Set (1UL) /*!< Enable */ +#define RTC_INTENSET_TICK_Disabled (0x0UL) /*!< Read: Disabled */ +#define RTC_INTENSET_TICK_Enabled (0x1UL) /*!< Read: Enabled */ +#define RTC_INTENSET_TICK_Set (0x1UL) /*!< Enable */ /* Register: RTC_INTENCLR */ /* Description: Disable interrupt */ @@ -5822,44 +5822,44 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 19 : Write '1' to disable interrupt for event COMPARE[3] */ #define RTC_INTENCLR_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */ #define RTC_INTENCLR_COMPARE3_Msk (0x1UL << RTC_INTENCLR_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */ -#define RTC_INTENCLR_COMPARE3_Disabled (0UL) /*!< Read: Disabled */ -#define RTC_INTENCLR_COMPARE3_Enabled (1UL) /*!< Read: Enabled */ -#define RTC_INTENCLR_COMPARE3_Clear (1UL) /*!< Disable */ +#define RTC_INTENCLR_COMPARE3_Disabled (0x0UL) /*!< Read: Disabled */ +#define RTC_INTENCLR_COMPARE3_Enabled (0x1UL) /*!< Read: Enabled */ +#define RTC_INTENCLR_COMPARE3_Clear (0x1UL) /*!< Disable */ /* Bit 18 : Write '1' to disable interrupt for event COMPARE[2] */ #define RTC_INTENCLR_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */ #define RTC_INTENCLR_COMPARE2_Msk (0x1UL << RTC_INTENCLR_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */ -#define RTC_INTENCLR_COMPARE2_Disabled (0UL) /*!< Read: Disabled */ -#define RTC_INTENCLR_COMPARE2_Enabled (1UL) /*!< Read: Enabled */ -#define RTC_INTENCLR_COMPARE2_Clear (1UL) /*!< Disable */ +#define RTC_INTENCLR_COMPARE2_Disabled (0x0UL) /*!< Read: Disabled */ +#define RTC_INTENCLR_COMPARE2_Enabled (0x1UL) /*!< Read: Enabled */ +#define RTC_INTENCLR_COMPARE2_Clear (0x1UL) /*!< Disable */ /* Bit 17 : Write '1' to disable interrupt for event COMPARE[1] */ #define RTC_INTENCLR_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */ #define RTC_INTENCLR_COMPARE1_Msk (0x1UL << RTC_INTENCLR_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */ -#define RTC_INTENCLR_COMPARE1_Disabled (0UL) /*!< Read: Disabled */ -#define RTC_INTENCLR_COMPARE1_Enabled (1UL) /*!< Read: Enabled */ -#define RTC_INTENCLR_COMPARE1_Clear (1UL) /*!< Disable */ +#define RTC_INTENCLR_COMPARE1_Disabled (0x0UL) /*!< Read: Disabled */ +#define RTC_INTENCLR_COMPARE1_Enabled (0x1UL) /*!< Read: Enabled */ +#define RTC_INTENCLR_COMPARE1_Clear (0x1UL) /*!< Disable */ /* Bit 16 : Write '1' to disable interrupt for event COMPARE[0] */ #define RTC_INTENCLR_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */ #define RTC_INTENCLR_COMPARE0_Msk (0x1UL << RTC_INTENCLR_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */ -#define RTC_INTENCLR_COMPARE0_Disabled (0UL) /*!< Read: Disabled */ -#define RTC_INTENCLR_COMPARE0_Enabled (1UL) /*!< Read: Enabled */ -#define RTC_INTENCLR_COMPARE0_Clear (1UL) /*!< Disable */ +#define RTC_INTENCLR_COMPARE0_Disabled (0x0UL) /*!< Read: Disabled */ +#define RTC_INTENCLR_COMPARE0_Enabled (0x1UL) /*!< Read: Enabled */ +#define RTC_INTENCLR_COMPARE0_Clear (0x1UL) /*!< Disable */ /* Bit 1 : Write '1' to disable interrupt for event OVRFLW */ #define RTC_INTENCLR_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */ #define RTC_INTENCLR_OVRFLW_Msk (0x1UL << RTC_INTENCLR_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */ -#define RTC_INTENCLR_OVRFLW_Disabled (0UL) /*!< Read: Disabled */ -#define RTC_INTENCLR_OVRFLW_Enabled (1UL) /*!< Read: Enabled */ -#define RTC_INTENCLR_OVRFLW_Clear (1UL) /*!< Disable */ +#define RTC_INTENCLR_OVRFLW_Disabled (0x0UL) /*!< Read: Disabled */ +#define RTC_INTENCLR_OVRFLW_Enabled (0x1UL) /*!< Read: Enabled */ +#define RTC_INTENCLR_OVRFLW_Clear (0x1UL) /*!< Disable */ /* Bit 0 : Write '1' to disable interrupt for event TICK */ #define RTC_INTENCLR_TICK_Pos (0UL) /*!< Position of TICK field. */ #define RTC_INTENCLR_TICK_Msk (0x1UL << RTC_INTENCLR_TICK_Pos) /*!< Bit mask of TICK field. */ -#define RTC_INTENCLR_TICK_Disabled (0UL) /*!< Read: Disabled */ -#define RTC_INTENCLR_TICK_Enabled (1UL) /*!< Read: Enabled */ -#define RTC_INTENCLR_TICK_Clear (1UL) /*!< Disable */ +#define RTC_INTENCLR_TICK_Disabled (0x0UL) /*!< Read: Disabled */ +#define RTC_INTENCLR_TICK_Enabled (0x1UL) /*!< Read: Enabled */ +#define RTC_INTENCLR_TICK_Clear (0x1UL) /*!< Disable */ /* Register: RTC_EVTEN */ /* Description: Enable or disable event routing */ @@ -5867,38 +5867,38 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 19 : Enable or disable event routing for event COMPARE[3] */ #define RTC_EVTEN_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */ #define RTC_EVTEN_COMPARE3_Msk (0x1UL << RTC_EVTEN_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */ -#define RTC_EVTEN_COMPARE3_Disabled (0UL) /*!< Disable */ -#define RTC_EVTEN_COMPARE3_Enabled (1UL) /*!< Enable */ +#define RTC_EVTEN_COMPARE3_Disabled (0x0UL) /*!< Disable */ +#define RTC_EVTEN_COMPARE3_Enabled (0x1UL) /*!< Enable */ /* Bit 18 : Enable or disable event routing for event COMPARE[2] */ #define RTC_EVTEN_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */ #define RTC_EVTEN_COMPARE2_Msk (0x1UL << RTC_EVTEN_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */ -#define RTC_EVTEN_COMPARE2_Disabled (0UL) /*!< Disable */ -#define RTC_EVTEN_COMPARE2_Enabled (1UL) /*!< Enable */ +#define RTC_EVTEN_COMPARE2_Disabled (0x0UL) /*!< Disable */ +#define RTC_EVTEN_COMPARE2_Enabled (0x1UL) /*!< Enable */ /* Bit 17 : Enable or disable event routing for event COMPARE[1] */ #define RTC_EVTEN_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */ #define RTC_EVTEN_COMPARE1_Msk (0x1UL << RTC_EVTEN_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */ -#define RTC_EVTEN_COMPARE1_Disabled (0UL) /*!< Disable */ -#define RTC_EVTEN_COMPARE1_Enabled (1UL) /*!< Enable */ +#define RTC_EVTEN_COMPARE1_Disabled (0x0UL) /*!< Disable */ +#define RTC_EVTEN_COMPARE1_Enabled (0x1UL) /*!< Enable */ /* Bit 16 : Enable or disable event routing for event COMPARE[0] */ #define RTC_EVTEN_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */ #define RTC_EVTEN_COMPARE0_Msk (0x1UL << RTC_EVTEN_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */ -#define RTC_EVTEN_COMPARE0_Disabled (0UL) /*!< Disable */ -#define RTC_EVTEN_COMPARE0_Enabled (1UL) /*!< Enable */ +#define RTC_EVTEN_COMPARE0_Disabled (0x0UL) /*!< Disable */ +#define RTC_EVTEN_COMPARE0_Enabled (0x1UL) /*!< Enable */ /* Bit 1 : Enable or disable event routing for event OVRFLW */ #define RTC_EVTEN_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */ #define RTC_EVTEN_OVRFLW_Msk (0x1UL << RTC_EVTEN_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */ -#define RTC_EVTEN_OVRFLW_Disabled (0UL) /*!< Disable */ -#define RTC_EVTEN_OVRFLW_Enabled (1UL) /*!< Enable */ +#define RTC_EVTEN_OVRFLW_Disabled (0x0UL) /*!< Disable */ +#define RTC_EVTEN_OVRFLW_Enabled (0x1UL) /*!< Enable */ /* Bit 0 : Enable or disable event routing for event TICK */ #define RTC_EVTEN_TICK_Pos (0UL) /*!< Position of TICK field. */ #define RTC_EVTEN_TICK_Msk (0x1UL << RTC_EVTEN_TICK_Pos) /*!< Bit mask of TICK field. */ -#define RTC_EVTEN_TICK_Disabled (0UL) /*!< Disable */ -#define RTC_EVTEN_TICK_Enabled (1UL) /*!< Enable */ +#define RTC_EVTEN_TICK_Disabled (0x0UL) /*!< Disable */ +#define RTC_EVTEN_TICK_Enabled (0x1UL) /*!< Enable */ /* Register: RTC_EVTENSET */ /* Description: Enable event routing */ @@ -5906,44 +5906,44 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 19 : Write '1' to enable event routing for event COMPARE[3] */ #define RTC_EVTENSET_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */ #define RTC_EVTENSET_COMPARE3_Msk (0x1UL << RTC_EVTENSET_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */ -#define RTC_EVTENSET_COMPARE3_Disabled (0UL) /*!< Read: Disabled */ -#define RTC_EVTENSET_COMPARE3_Enabled (1UL) /*!< Read: Enabled */ -#define RTC_EVTENSET_COMPARE3_Set (1UL) /*!< Enable */ +#define RTC_EVTENSET_COMPARE3_Disabled (0x0UL) /*!< Read: Disabled */ +#define RTC_EVTENSET_COMPARE3_Enabled (0x1UL) /*!< Read: Enabled */ +#define RTC_EVTENSET_COMPARE3_Set (0x1UL) /*!< Enable */ /* Bit 18 : Write '1' to enable event routing for event COMPARE[2] */ #define RTC_EVTENSET_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */ #define RTC_EVTENSET_COMPARE2_Msk (0x1UL << RTC_EVTENSET_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */ -#define RTC_EVTENSET_COMPARE2_Disabled (0UL) /*!< Read: Disabled */ -#define RTC_EVTENSET_COMPARE2_Enabled (1UL) /*!< Read: Enabled */ -#define RTC_EVTENSET_COMPARE2_Set (1UL) /*!< Enable */ +#define RTC_EVTENSET_COMPARE2_Disabled (0x0UL) /*!< Read: Disabled */ +#define RTC_EVTENSET_COMPARE2_Enabled (0x1UL) /*!< Read: Enabled */ +#define RTC_EVTENSET_COMPARE2_Set (0x1UL) /*!< Enable */ /* Bit 17 : Write '1' to enable event routing for event COMPARE[1] */ #define RTC_EVTENSET_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */ #define RTC_EVTENSET_COMPARE1_Msk (0x1UL << RTC_EVTENSET_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */ -#define RTC_EVTENSET_COMPARE1_Disabled (0UL) /*!< Read: Disabled */ -#define RTC_EVTENSET_COMPARE1_Enabled (1UL) /*!< Read: Enabled */ -#define RTC_EVTENSET_COMPARE1_Set (1UL) /*!< Enable */ +#define RTC_EVTENSET_COMPARE1_Disabled (0x0UL) /*!< Read: Disabled */ +#define RTC_EVTENSET_COMPARE1_Enabled (0x1UL) /*!< Read: Enabled */ +#define RTC_EVTENSET_COMPARE1_Set (0x1UL) /*!< Enable */ /* Bit 16 : Write '1' to enable event routing for event COMPARE[0] */ #define RTC_EVTENSET_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */ #define RTC_EVTENSET_COMPARE0_Msk (0x1UL << RTC_EVTENSET_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */ -#define RTC_EVTENSET_COMPARE0_Disabled (0UL) /*!< Read: Disabled */ -#define RTC_EVTENSET_COMPARE0_Enabled (1UL) /*!< Read: Enabled */ -#define RTC_EVTENSET_COMPARE0_Set (1UL) /*!< Enable */ +#define RTC_EVTENSET_COMPARE0_Disabled (0x0UL) /*!< Read: Disabled */ +#define RTC_EVTENSET_COMPARE0_Enabled (0x1UL) /*!< Read: Enabled */ +#define RTC_EVTENSET_COMPARE0_Set (0x1UL) /*!< Enable */ /* Bit 1 : Write '1' to enable event routing for event OVRFLW */ #define RTC_EVTENSET_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */ #define RTC_EVTENSET_OVRFLW_Msk (0x1UL << RTC_EVTENSET_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */ -#define RTC_EVTENSET_OVRFLW_Disabled (0UL) /*!< Read: Disabled */ -#define RTC_EVTENSET_OVRFLW_Enabled (1UL) /*!< Read: Enabled */ -#define RTC_EVTENSET_OVRFLW_Set (1UL) /*!< Enable */ +#define RTC_EVTENSET_OVRFLW_Disabled (0x0UL) /*!< Read: Disabled */ +#define RTC_EVTENSET_OVRFLW_Enabled (0x1UL) /*!< Read: Enabled */ +#define RTC_EVTENSET_OVRFLW_Set (0x1UL) /*!< Enable */ /* Bit 0 : Write '1' to enable event routing for event TICK */ #define RTC_EVTENSET_TICK_Pos (0UL) /*!< Position of TICK field. */ #define RTC_EVTENSET_TICK_Msk (0x1UL << RTC_EVTENSET_TICK_Pos) /*!< Bit mask of TICK field. */ -#define RTC_EVTENSET_TICK_Disabled (0UL) /*!< Read: Disabled */ -#define RTC_EVTENSET_TICK_Enabled (1UL) /*!< Read: Enabled */ -#define RTC_EVTENSET_TICK_Set (1UL) /*!< Enable */ +#define RTC_EVTENSET_TICK_Disabled (0x0UL) /*!< Read: Disabled */ +#define RTC_EVTENSET_TICK_Enabled (0x1UL) /*!< Read: Enabled */ +#define RTC_EVTENSET_TICK_Set (0x1UL) /*!< Enable */ /* Register: RTC_EVTENCLR */ /* Description: Disable event routing */ @@ -5951,44 +5951,44 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 19 : Write '1' to disable event routing for event COMPARE[3] */ #define RTC_EVTENCLR_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */ #define RTC_EVTENCLR_COMPARE3_Msk (0x1UL << RTC_EVTENCLR_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */ -#define RTC_EVTENCLR_COMPARE3_Disabled (0UL) /*!< Read: Disabled */ -#define RTC_EVTENCLR_COMPARE3_Enabled (1UL) /*!< Read: Enabled */ -#define RTC_EVTENCLR_COMPARE3_Clear (1UL) /*!< Disable */ +#define RTC_EVTENCLR_COMPARE3_Disabled (0x0UL) /*!< Read: Disabled */ +#define RTC_EVTENCLR_COMPARE3_Enabled (0x1UL) /*!< Read: Enabled */ +#define RTC_EVTENCLR_COMPARE3_Clear (0x1UL) /*!< Disable */ /* Bit 18 : Write '1' to disable event routing for event COMPARE[2] */ #define RTC_EVTENCLR_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */ #define RTC_EVTENCLR_COMPARE2_Msk (0x1UL << RTC_EVTENCLR_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */ -#define RTC_EVTENCLR_COMPARE2_Disabled (0UL) /*!< Read: Disabled */ -#define RTC_EVTENCLR_COMPARE2_Enabled (1UL) /*!< Read: Enabled */ -#define RTC_EVTENCLR_COMPARE2_Clear (1UL) /*!< Disable */ +#define RTC_EVTENCLR_COMPARE2_Disabled (0x0UL) /*!< Read: Disabled */ +#define RTC_EVTENCLR_COMPARE2_Enabled (0x1UL) /*!< Read: Enabled */ +#define RTC_EVTENCLR_COMPARE2_Clear (0x1UL) /*!< Disable */ /* Bit 17 : Write '1' to disable event routing for event COMPARE[1] */ #define RTC_EVTENCLR_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */ #define RTC_EVTENCLR_COMPARE1_Msk (0x1UL << RTC_EVTENCLR_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */ -#define RTC_EVTENCLR_COMPARE1_Disabled (0UL) /*!< Read: Disabled */ -#define RTC_EVTENCLR_COMPARE1_Enabled (1UL) /*!< Read: Enabled */ -#define RTC_EVTENCLR_COMPARE1_Clear (1UL) /*!< Disable */ +#define RTC_EVTENCLR_COMPARE1_Disabled (0x0UL) /*!< Read: Disabled */ +#define RTC_EVTENCLR_COMPARE1_Enabled (0x1UL) /*!< Read: Enabled */ +#define RTC_EVTENCLR_COMPARE1_Clear (0x1UL) /*!< Disable */ /* Bit 16 : Write '1' to disable event routing for event COMPARE[0] */ #define RTC_EVTENCLR_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */ #define RTC_EVTENCLR_COMPARE0_Msk (0x1UL << RTC_EVTENCLR_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */ -#define RTC_EVTENCLR_COMPARE0_Disabled (0UL) /*!< Read: Disabled */ -#define RTC_EVTENCLR_COMPARE0_Enabled (1UL) /*!< Read: Enabled */ -#define RTC_EVTENCLR_COMPARE0_Clear (1UL) /*!< Disable */ +#define RTC_EVTENCLR_COMPARE0_Disabled (0x0UL) /*!< Read: Disabled */ +#define RTC_EVTENCLR_COMPARE0_Enabled (0x1UL) /*!< Read: Enabled */ +#define RTC_EVTENCLR_COMPARE0_Clear (0x1UL) /*!< Disable */ /* Bit 1 : Write '1' to disable event routing for event OVRFLW */ #define RTC_EVTENCLR_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */ #define RTC_EVTENCLR_OVRFLW_Msk (0x1UL << RTC_EVTENCLR_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */ -#define RTC_EVTENCLR_OVRFLW_Disabled (0UL) /*!< Read: Disabled */ -#define RTC_EVTENCLR_OVRFLW_Enabled (1UL) /*!< Read: Enabled */ -#define RTC_EVTENCLR_OVRFLW_Clear (1UL) /*!< Disable */ +#define RTC_EVTENCLR_OVRFLW_Disabled (0x0UL) /*!< Read: Disabled */ +#define RTC_EVTENCLR_OVRFLW_Enabled (0x1UL) /*!< Read: Enabled */ +#define RTC_EVTENCLR_OVRFLW_Clear (0x1UL) /*!< Disable */ /* Bit 0 : Write '1' to disable event routing for event TICK */ #define RTC_EVTENCLR_TICK_Pos (0UL) /*!< Position of TICK field. */ #define RTC_EVTENCLR_TICK_Msk (0x1UL << RTC_EVTENCLR_TICK_Pos) /*!< Bit mask of TICK field. */ -#define RTC_EVTENCLR_TICK_Disabled (0UL) /*!< Read: Disabled */ -#define RTC_EVTENCLR_TICK_Enabled (1UL) /*!< Read: Enabled */ -#define RTC_EVTENCLR_TICK_Clear (1UL) /*!< Disable */ +#define RTC_EVTENCLR_TICK_Disabled (0x0UL) /*!< Read: Disabled */ +#define RTC_EVTENCLR_TICK_Enabled (0x1UL) /*!< Read: Enabled */ +#define RTC_EVTENCLR_TICK_Clear (0x1UL) /*!< Disable */ /* Register: RTC_COUNTER */ /* Description: Current counter value */ @@ -6021,7 +6021,7 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 0 : Start the ADC and prepare the result buffer in RAM */ #define SAADC_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */ #define SAADC_TASKS_START_TASKS_START_Msk (0x1UL << SAADC_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */ -#define SAADC_TASKS_START_TASKS_START_Trigger (1UL) /*!< Trigger task */ +#define SAADC_TASKS_START_TASKS_START_Trigger (0x1UL) /*!< Trigger task */ /* Register: SAADC_TASKS_SAMPLE */ /* Description: Take one ADC sample, if scan is enabled all channels are sampled */ @@ -6029,7 +6029,7 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 0 : Take one ADC sample, if scan is enabled all channels are sampled */ #define SAADC_TASKS_SAMPLE_TASKS_SAMPLE_Pos (0UL) /*!< Position of TASKS_SAMPLE field. */ #define SAADC_TASKS_SAMPLE_TASKS_SAMPLE_Msk (0x1UL << SAADC_TASKS_SAMPLE_TASKS_SAMPLE_Pos) /*!< Bit mask of TASKS_SAMPLE field. */ -#define SAADC_TASKS_SAMPLE_TASKS_SAMPLE_Trigger (1UL) /*!< Trigger task */ +#define SAADC_TASKS_SAMPLE_TASKS_SAMPLE_Trigger (0x1UL) /*!< Trigger task */ /* Register: SAADC_TASKS_STOP */ /* Description: Stop the ADC and terminate any on-going conversion */ @@ -6037,7 +6037,7 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 0 : Stop the ADC and terminate any on-going conversion */ #define SAADC_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */ #define SAADC_TASKS_STOP_TASKS_STOP_Msk (0x1UL << SAADC_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */ -#define SAADC_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */ +#define SAADC_TASKS_STOP_TASKS_STOP_Trigger (0x1UL) /*!< Trigger task */ /* Register: SAADC_TASKS_CALIBRATEOFFSET */ /* Description: Starts offset auto-calibration */ @@ -6045,7 +6045,7 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 0 : Starts offset auto-calibration */ #define SAADC_TASKS_CALIBRATEOFFSET_TASKS_CALIBRATEOFFSET_Pos (0UL) /*!< Position of TASKS_CALIBRATEOFFSET field. */ #define SAADC_TASKS_CALIBRATEOFFSET_TASKS_CALIBRATEOFFSET_Msk (0x1UL << SAADC_TASKS_CALIBRATEOFFSET_TASKS_CALIBRATEOFFSET_Pos) /*!< Bit mask of TASKS_CALIBRATEOFFSET field. */ -#define SAADC_TASKS_CALIBRATEOFFSET_TASKS_CALIBRATEOFFSET_Trigger (1UL) /*!< Trigger task */ +#define SAADC_TASKS_CALIBRATEOFFSET_TASKS_CALIBRATEOFFSET_Trigger (0x1UL) /*!< Trigger task */ /* Register: SAADC_SUBSCRIBE_START */ /* Description: Subscribe configuration for task START */ @@ -6053,8 +6053,8 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 31 : */ #define SAADC_SUBSCRIBE_START_EN_Pos (31UL) /*!< Position of EN field. */ #define SAADC_SUBSCRIBE_START_EN_Msk (0x1UL << SAADC_SUBSCRIBE_START_EN_Pos) /*!< Bit mask of EN field. */ -#define SAADC_SUBSCRIBE_START_EN_Disabled (0UL) /*!< Disable subscription */ -#define SAADC_SUBSCRIBE_START_EN_Enabled (1UL) /*!< Enable subscription */ +#define SAADC_SUBSCRIBE_START_EN_Disabled (0x0UL) /*!< Disable subscription */ +#define SAADC_SUBSCRIBE_START_EN_Enabled (0x1UL) /*!< Enable subscription */ /* Bits 7..0 : DPPI channel that task START will subscribe to */ #define SAADC_SUBSCRIBE_START_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ @@ -6066,8 +6066,8 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 31 : */ #define SAADC_SUBSCRIBE_SAMPLE_EN_Pos (31UL) /*!< Position of EN field. */ #define SAADC_SUBSCRIBE_SAMPLE_EN_Msk (0x1UL << SAADC_SUBSCRIBE_SAMPLE_EN_Pos) /*!< Bit mask of EN field. */ -#define SAADC_SUBSCRIBE_SAMPLE_EN_Disabled (0UL) /*!< Disable subscription */ -#define SAADC_SUBSCRIBE_SAMPLE_EN_Enabled (1UL) /*!< Enable subscription */ +#define SAADC_SUBSCRIBE_SAMPLE_EN_Disabled (0x0UL) /*!< Disable subscription */ +#define SAADC_SUBSCRIBE_SAMPLE_EN_Enabled (0x1UL) /*!< Enable subscription */ /* Bits 7..0 : DPPI channel that task SAMPLE will subscribe to */ #define SAADC_SUBSCRIBE_SAMPLE_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ @@ -6079,8 +6079,8 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 31 : */ #define SAADC_SUBSCRIBE_STOP_EN_Pos (31UL) /*!< Position of EN field. */ #define SAADC_SUBSCRIBE_STOP_EN_Msk (0x1UL << SAADC_SUBSCRIBE_STOP_EN_Pos) /*!< Bit mask of EN field. */ -#define SAADC_SUBSCRIBE_STOP_EN_Disabled (0UL) /*!< Disable subscription */ -#define SAADC_SUBSCRIBE_STOP_EN_Enabled (1UL) /*!< Enable subscription */ +#define SAADC_SUBSCRIBE_STOP_EN_Disabled (0x0UL) /*!< Disable subscription */ +#define SAADC_SUBSCRIBE_STOP_EN_Enabled (0x1UL) /*!< Enable subscription */ /* Bits 7..0 : DPPI channel that task STOP will subscribe to */ #define SAADC_SUBSCRIBE_STOP_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ @@ -6092,8 +6092,8 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 31 : */ #define SAADC_SUBSCRIBE_CALIBRATEOFFSET_EN_Pos (31UL) /*!< Position of EN field. */ #define SAADC_SUBSCRIBE_CALIBRATEOFFSET_EN_Msk (0x1UL << SAADC_SUBSCRIBE_CALIBRATEOFFSET_EN_Pos) /*!< Bit mask of EN field. */ -#define SAADC_SUBSCRIBE_CALIBRATEOFFSET_EN_Disabled (0UL) /*!< Disable subscription */ -#define SAADC_SUBSCRIBE_CALIBRATEOFFSET_EN_Enabled (1UL) /*!< Enable subscription */ +#define SAADC_SUBSCRIBE_CALIBRATEOFFSET_EN_Disabled (0x0UL) /*!< Disable subscription */ +#define SAADC_SUBSCRIBE_CALIBRATEOFFSET_EN_Enabled (0x1UL) /*!< Enable subscription */ /* Bits 7..0 : DPPI channel that task CALIBRATEOFFSET will subscribe to */ #define SAADC_SUBSCRIBE_CALIBRATEOFFSET_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ @@ -6105,8 +6105,8 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 0 : The ADC has started */ #define SAADC_EVENTS_STARTED_EVENTS_STARTED_Pos (0UL) /*!< Position of EVENTS_STARTED field. */ #define SAADC_EVENTS_STARTED_EVENTS_STARTED_Msk (0x1UL << SAADC_EVENTS_STARTED_EVENTS_STARTED_Pos) /*!< Bit mask of EVENTS_STARTED field. */ -#define SAADC_EVENTS_STARTED_EVENTS_STARTED_NotGenerated (0UL) /*!< Event not generated */ -#define SAADC_EVENTS_STARTED_EVENTS_STARTED_Generated (1UL) /*!< Event generated */ +#define SAADC_EVENTS_STARTED_EVENTS_STARTED_NotGenerated (0x0UL) /*!< Event not generated */ +#define SAADC_EVENTS_STARTED_EVENTS_STARTED_Generated (0x1UL) /*!< Event generated */ /* Register: SAADC_EVENTS_END */ /* Description: The ADC has filled up the Result buffer */ @@ -6114,8 +6114,8 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 0 : The ADC has filled up the Result buffer */ #define SAADC_EVENTS_END_EVENTS_END_Pos (0UL) /*!< Position of EVENTS_END field. */ #define SAADC_EVENTS_END_EVENTS_END_Msk (0x1UL << SAADC_EVENTS_END_EVENTS_END_Pos) /*!< Bit mask of EVENTS_END field. */ -#define SAADC_EVENTS_END_EVENTS_END_NotGenerated (0UL) /*!< Event not generated */ -#define SAADC_EVENTS_END_EVENTS_END_Generated (1UL) /*!< Event generated */ +#define SAADC_EVENTS_END_EVENTS_END_NotGenerated (0x0UL) /*!< Event not generated */ +#define SAADC_EVENTS_END_EVENTS_END_Generated (0x1UL) /*!< Event generated */ /* Register: SAADC_EVENTS_DONE */ /* Description: A conversion task has been completed. Depending on the mode, multiple conversions might be needed for a result to be transferred to RAM. */ @@ -6123,8 +6123,8 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 0 : A conversion task has been completed. Depending on the mode, multiple conversions might be needed for a result to be transferred to RAM. */ #define SAADC_EVENTS_DONE_EVENTS_DONE_Pos (0UL) /*!< Position of EVENTS_DONE field. */ #define SAADC_EVENTS_DONE_EVENTS_DONE_Msk (0x1UL << SAADC_EVENTS_DONE_EVENTS_DONE_Pos) /*!< Bit mask of EVENTS_DONE field. */ -#define SAADC_EVENTS_DONE_EVENTS_DONE_NotGenerated (0UL) /*!< Event not generated */ -#define SAADC_EVENTS_DONE_EVENTS_DONE_Generated (1UL) /*!< Event generated */ +#define SAADC_EVENTS_DONE_EVENTS_DONE_NotGenerated (0x0UL) /*!< Event not generated */ +#define SAADC_EVENTS_DONE_EVENTS_DONE_Generated (0x1UL) /*!< Event generated */ /* Register: SAADC_EVENTS_RESULTDONE */ /* Description: A result is ready to get transferred to RAM. */ @@ -6132,8 +6132,8 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 0 : A result is ready to get transferred to RAM. */ #define SAADC_EVENTS_RESULTDONE_EVENTS_RESULTDONE_Pos (0UL) /*!< Position of EVENTS_RESULTDONE field. */ #define SAADC_EVENTS_RESULTDONE_EVENTS_RESULTDONE_Msk (0x1UL << SAADC_EVENTS_RESULTDONE_EVENTS_RESULTDONE_Pos) /*!< Bit mask of EVENTS_RESULTDONE field. */ -#define SAADC_EVENTS_RESULTDONE_EVENTS_RESULTDONE_NotGenerated (0UL) /*!< Event not generated */ -#define SAADC_EVENTS_RESULTDONE_EVENTS_RESULTDONE_Generated (1UL) /*!< Event generated */ +#define SAADC_EVENTS_RESULTDONE_EVENTS_RESULTDONE_NotGenerated (0x0UL) /*!< Event not generated */ +#define SAADC_EVENTS_RESULTDONE_EVENTS_RESULTDONE_Generated (0x1UL) /*!< Event generated */ /* Register: SAADC_EVENTS_CALIBRATEDONE */ /* Description: Calibration is complete */ @@ -6141,8 +6141,8 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 0 : Calibration is complete */ #define SAADC_EVENTS_CALIBRATEDONE_EVENTS_CALIBRATEDONE_Pos (0UL) /*!< Position of EVENTS_CALIBRATEDONE field. */ #define SAADC_EVENTS_CALIBRATEDONE_EVENTS_CALIBRATEDONE_Msk (0x1UL << SAADC_EVENTS_CALIBRATEDONE_EVENTS_CALIBRATEDONE_Pos) /*!< Bit mask of EVENTS_CALIBRATEDONE field. */ -#define SAADC_EVENTS_CALIBRATEDONE_EVENTS_CALIBRATEDONE_NotGenerated (0UL) /*!< Event not generated */ -#define SAADC_EVENTS_CALIBRATEDONE_EVENTS_CALIBRATEDONE_Generated (1UL) /*!< Event generated */ +#define SAADC_EVENTS_CALIBRATEDONE_EVENTS_CALIBRATEDONE_NotGenerated (0x0UL) /*!< Event not generated */ +#define SAADC_EVENTS_CALIBRATEDONE_EVENTS_CALIBRATEDONE_Generated (0x1UL) /*!< Event generated */ /* Register: SAADC_EVENTS_STOPPED */ /* Description: The ADC has stopped */ @@ -6150,8 +6150,8 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 0 : The ADC has stopped */ #define SAADC_EVENTS_STOPPED_EVENTS_STOPPED_Pos (0UL) /*!< Position of EVENTS_STOPPED field. */ #define SAADC_EVENTS_STOPPED_EVENTS_STOPPED_Msk (0x1UL << SAADC_EVENTS_STOPPED_EVENTS_STOPPED_Pos) /*!< Bit mask of EVENTS_STOPPED field. */ -#define SAADC_EVENTS_STOPPED_EVENTS_STOPPED_NotGenerated (0UL) /*!< Event not generated */ -#define SAADC_EVENTS_STOPPED_EVENTS_STOPPED_Generated (1UL) /*!< Event generated */ +#define SAADC_EVENTS_STOPPED_EVENTS_STOPPED_NotGenerated (0x0UL) /*!< Event not generated */ +#define SAADC_EVENTS_STOPPED_EVENTS_STOPPED_Generated (0x1UL) /*!< Event generated */ /* Register: SAADC_EVENTS_CH_LIMITH */ /* Description: Description cluster: Last results is equal or above CH[n].LIMIT.HIGH */ @@ -6159,8 +6159,8 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 0 : Last results is equal or above CH[n].LIMIT.HIGH */ #define SAADC_EVENTS_CH_LIMITH_LIMITH_Pos (0UL) /*!< Position of LIMITH field. */ #define SAADC_EVENTS_CH_LIMITH_LIMITH_Msk (0x1UL << SAADC_EVENTS_CH_LIMITH_LIMITH_Pos) /*!< Bit mask of LIMITH field. */ -#define SAADC_EVENTS_CH_LIMITH_LIMITH_NotGenerated (0UL) /*!< Event not generated */ -#define SAADC_EVENTS_CH_LIMITH_LIMITH_Generated (1UL) /*!< Event generated */ +#define SAADC_EVENTS_CH_LIMITH_LIMITH_NotGenerated (0x0UL) /*!< Event not generated */ +#define SAADC_EVENTS_CH_LIMITH_LIMITH_Generated (0x1UL) /*!< Event generated */ /* Register: SAADC_EVENTS_CH_LIMITL */ /* Description: Description cluster: Last results is equal or below CH[n].LIMIT.LOW */ @@ -6168,8 +6168,8 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 0 : Last results is equal or below CH[n].LIMIT.LOW */ #define SAADC_EVENTS_CH_LIMITL_LIMITL_Pos (0UL) /*!< Position of LIMITL field. */ #define SAADC_EVENTS_CH_LIMITL_LIMITL_Msk (0x1UL << SAADC_EVENTS_CH_LIMITL_LIMITL_Pos) /*!< Bit mask of LIMITL field. */ -#define SAADC_EVENTS_CH_LIMITL_LIMITL_NotGenerated (0UL) /*!< Event not generated */ -#define SAADC_EVENTS_CH_LIMITL_LIMITL_Generated (1UL) /*!< Event generated */ +#define SAADC_EVENTS_CH_LIMITL_LIMITL_NotGenerated (0x0UL) /*!< Event not generated */ +#define SAADC_EVENTS_CH_LIMITL_LIMITL_Generated (0x1UL) /*!< Event generated */ /* Register: SAADC_PUBLISH_STARTED */ /* Description: Publish configuration for event STARTED */ @@ -6177,8 +6177,8 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 31 : */ #define SAADC_PUBLISH_STARTED_EN_Pos (31UL) /*!< Position of EN field. */ #define SAADC_PUBLISH_STARTED_EN_Msk (0x1UL << SAADC_PUBLISH_STARTED_EN_Pos) /*!< Bit mask of EN field. */ -#define SAADC_PUBLISH_STARTED_EN_Disabled (0UL) /*!< Disable publishing */ -#define SAADC_PUBLISH_STARTED_EN_Enabled (1UL) /*!< Enable publishing */ +#define SAADC_PUBLISH_STARTED_EN_Disabled (0x0UL) /*!< Disable publishing */ +#define SAADC_PUBLISH_STARTED_EN_Enabled (0x1UL) /*!< Enable publishing */ /* Bits 7..0 : DPPI channel that event STARTED will publish to */ #define SAADC_PUBLISH_STARTED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ @@ -6190,8 +6190,8 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 31 : */ #define SAADC_PUBLISH_END_EN_Pos (31UL) /*!< Position of EN field. */ #define SAADC_PUBLISH_END_EN_Msk (0x1UL << SAADC_PUBLISH_END_EN_Pos) /*!< Bit mask of EN field. */ -#define SAADC_PUBLISH_END_EN_Disabled (0UL) /*!< Disable publishing */ -#define SAADC_PUBLISH_END_EN_Enabled (1UL) /*!< Enable publishing */ +#define SAADC_PUBLISH_END_EN_Disabled (0x0UL) /*!< Disable publishing */ +#define SAADC_PUBLISH_END_EN_Enabled (0x1UL) /*!< Enable publishing */ /* Bits 7..0 : DPPI channel that event END will publish to */ #define SAADC_PUBLISH_END_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ @@ -6203,8 +6203,8 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 31 : */ #define SAADC_PUBLISH_DONE_EN_Pos (31UL) /*!< Position of EN field. */ #define SAADC_PUBLISH_DONE_EN_Msk (0x1UL << SAADC_PUBLISH_DONE_EN_Pos) /*!< Bit mask of EN field. */ -#define SAADC_PUBLISH_DONE_EN_Disabled (0UL) /*!< Disable publishing */ -#define SAADC_PUBLISH_DONE_EN_Enabled (1UL) /*!< Enable publishing */ +#define SAADC_PUBLISH_DONE_EN_Disabled (0x0UL) /*!< Disable publishing */ +#define SAADC_PUBLISH_DONE_EN_Enabled (0x1UL) /*!< Enable publishing */ /* Bits 7..0 : DPPI channel that event DONE will publish to */ #define SAADC_PUBLISH_DONE_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ @@ -6216,8 +6216,8 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 31 : */ #define SAADC_PUBLISH_RESULTDONE_EN_Pos (31UL) /*!< Position of EN field. */ #define SAADC_PUBLISH_RESULTDONE_EN_Msk (0x1UL << SAADC_PUBLISH_RESULTDONE_EN_Pos) /*!< Bit mask of EN field. */ -#define SAADC_PUBLISH_RESULTDONE_EN_Disabled (0UL) /*!< Disable publishing */ -#define SAADC_PUBLISH_RESULTDONE_EN_Enabled (1UL) /*!< Enable publishing */ +#define SAADC_PUBLISH_RESULTDONE_EN_Disabled (0x0UL) /*!< Disable publishing */ +#define SAADC_PUBLISH_RESULTDONE_EN_Enabled (0x1UL) /*!< Enable publishing */ /* Bits 7..0 : DPPI channel that event RESULTDONE will publish to */ #define SAADC_PUBLISH_RESULTDONE_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ @@ -6229,8 +6229,8 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 31 : */ #define SAADC_PUBLISH_CALIBRATEDONE_EN_Pos (31UL) /*!< Position of EN field. */ #define SAADC_PUBLISH_CALIBRATEDONE_EN_Msk (0x1UL << SAADC_PUBLISH_CALIBRATEDONE_EN_Pos) /*!< Bit mask of EN field. */ -#define SAADC_PUBLISH_CALIBRATEDONE_EN_Disabled (0UL) /*!< Disable publishing */ -#define SAADC_PUBLISH_CALIBRATEDONE_EN_Enabled (1UL) /*!< Enable publishing */ +#define SAADC_PUBLISH_CALIBRATEDONE_EN_Disabled (0x0UL) /*!< Disable publishing */ +#define SAADC_PUBLISH_CALIBRATEDONE_EN_Enabled (0x1UL) /*!< Enable publishing */ /* Bits 7..0 : DPPI channel that event CALIBRATEDONE will publish to */ #define SAADC_PUBLISH_CALIBRATEDONE_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ @@ -6242,8 +6242,8 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 31 : */ #define SAADC_PUBLISH_STOPPED_EN_Pos (31UL) /*!< Position of EN field. */ #define SAADC_PUBLISH_STOPPED_EN_Msk (0x1UL << SAADC_PUBLISH_STOPPED_EN_Pos) /*!< Bit mask of EN field. */ -#define SAADC_PUBLISH_STOPPED_EN_Disabled (0UL) /*!< Disable publishing */ -#define SAADC_PUBLISH_STOPPED_EN_Enabled (1UL) /*!< Enable publishing */ +#define SAADC_PUBLISH_STOPPED_EN_Disabled (0x0UL) /*!< Disable publishing */ +#define SAADC_PUBLISH_STOPPED_EN_Enabled (0x1UL) /*!< Enable publishing */ /* Bits 7..0 : DPPI channel that event STOPPED will publish to */ #define SAADC_PUBLISH_STOPPED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ @@ -6255,8 +6255,8 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 31 : */ #define SAADC_PUBLISH_CH_LIMITH_EN_Pos (31UL) /*!< Position of EN field. */ #define SAADC_PUBLISH_CH_LIMITH_EN_Msk (0x1UL << SAADC_PUBLISH_CH_LIMITH_EN_Pos) /*!< Bit mask of EN field. */ -#define SAADC_PUBLISH_CH_LIMITH_EN_Disabled (0UL) /*!< Disable publishing */ -#define SAADC_PUBLISH_CH_LIMITH_EN_Enabled (1UL) /*!< Enable publishing */ +#define SAADC_PUBLISH_CH_LIMITH_EN_Disabled (0x0UL) /*!< Disable publishing */ +#define SAADC_PUBLISH_CH_LIMITH_EN_Enabled (0x1UL) /*!< Enable publishing */ /* Bits 7..0 : DPPI channel that event CH[n].LIMITH will publish to */ #define SAADC_PUBLISH_CH_LIMITH_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ @@ -6268,8 +6268,8 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 31 : */ #define SAADC_PUBLISH_CH_LIMITL_EN_Pos (31UL) /*!< Position of EN field. */ #define SAADC_PUBLISH_CH_LIMITL_EN_Msk (0x1UL << SAADC_PUBLISH_CH_LIMITL_EN_Pos) /*!< Bit mask of EN field. */ -#define SAADC_PUBLISH_CH_LIMITL_EN_Disabled (0UL) /*!< Disable publishing */ -#define SAADC_PUBLISH_CH_LIMITL_EN_Enabled (1UL) /*!< Enable publishing */ +#define SAADC_PUBLISH_CH_LIMITL_EN_Disabled (0x0UL) /*!< Disable publishing */ +#define SAADC_PUBLISH_CH_LIMITL_EN_Enabled (0x1UL) /*!< Enable publishing */ /* Bits 7..0 : DPPI channel that event CH[n].LIMITL will publish to */ #define SAADC_PUBLISH_CH_LIMITL_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ @@ -6281,134 +6281,134 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 21 : Enable or disable interrupt for event CH7LIMITL */ #define SAADC_INTEN_CH7LIMITL_Pos (21UL) /*!< Position of CH7LIMITL field. */ #define SAADC_INTEN_CH7LIMITL_Msk (0x1UL << SAADC_INTEN_CH7LIMITL_Pos) /*!< Bit mask of CH7LIMITL field. */ -#define SAADC_INTEN_CH7LIMITL_Disabled (0UL) /*!< Disable */ -#define SAADC_INTEN_CH7LIMITL_Enabled (1UL) /*!< Enable */ +#define SAADC_INTEN_CH7LIMITL_Disabled (0x0UL) /*!< Disable */ +#define SAADC_INTEN_CH7LIMITL_Enabled (0x1UL) /*!< Enable */ /* Bit 20 : Enable or disable interrupt for event CH7LIMITH */ #define SAADC_INTEN_CH7LIMITH_Pos (20UL) /*!< Position of CH7LIMITH field. */ #define SAADC_INTEN_CH7LIMITH_Msk (0x1UL << SAADC_INTEN_CH7LIMITH_Pos) /*!< Bit mask of CH7LIMITH field. */ -#define SAADC_INTEN_CH7LIMITH_Disabled (0UL) /*!< Disable */ -#define SAADC_INTEN_CH7LIMITH_Enabled (1UL) /*!< Enable */ +#define SAADC_INTEN_CH7LIMITH_Disabled (0x0UL) /*!< Disable */ +#define SAADC_INTEN_CH7LIMITH_Enabled (0x1UL) /*!< Enable */ /* Bit 19 : Enable or disable interrupt for event CH6LIMITL */ #define SAADC_INTEN_CH6LIMITL_Pos (19UL) /*!< Position of CH6LIMITL field. */ #define SAADC_INTEN_CH6LIMITL_Msk (0x1UL << SAADC_INTEN_CH6LIMITL_Pos) /*!< Bit mask of CH6LIMITL field. */ -#define SAADC_INTEN_CH6LIMITL_Disabled (0UL) /*!< Disable */ -#define SAADC_INTEN_CH6LIMITL_Enabled (1UL) /*!< Enable */ +#define SAADC_INTEN_CH6LIMITL_Disabled (0x0UL) /*!< Disable */ +#define SAADC_INTEN_CH6LIMITL_Enabled (0x1UL) /*!< Enable */ /* Bit 18 : Enable or disable interrupt for event CH6LIMITH */ #define SAADC_INTEN_CH6LIMITH_Pos (18UL) /*!< Position of CH6LIMITH field. */ #define SAADC_INTEN_CH6LIMITH_Msk (0x1UL << SAADC_INTEN_CH6LIMITH_Pos) /*!< Bit mask of CH6LIMITH field. */ -#define SAADC_INTEN_CH6LIMITH_Disabled (0UL) /*!< Disable */ -#define SAADC_INTEN_CH6LIMITH_Enabled (1UL) /*!< Enable */ +#define SAADC_INTEN_CH6LIMITH_Disabled (0x0UL) /*!< Disable */ +#define SAADC_INTEN_CH6LIMITH_Enabled (0x1UL) /*!< Enable */ /* Bit 17 : Enable or disable interrupt for event CH5LIMITL */ #define SAADC_INTEN_CH5LIMITL_Pos (17UL) /*!< Position of CH5LIMITL field. */ #define SAADC_INTEN_CH5LIMITL_Msk (0x1UL << SAADC_INTEN_CH5LIMITL_Pos) /*!< Bit mask of CH5LIMITL field. */ -#define SAADC_INTEN_CH5LIMITL_Disabled (0UL) /*!< Disable */ -#define SAADC_INTEN_CH5LIMITL_Enabled (1UL) /*!< Enable */ +#define SAADC_INTEN_CH5LIMITL_Disabled (0x0UL) /*!< Disable */ +#define SAADC_INTEN_CH5LIMITL_Enabled (0x1UL) /*!< Enable */ /* Bit 16 : Enable or disable interrupt for event CH5LIMITH */ #define SAADC_INTEN_CH5LIMITH_Pos (16UL) /*!< Position of CH5LIMITH field. */ #define SAADC_INTEN_CH5LIMITH_Msk (0x1UL << SAADC_INTEN_CH5LIMITH_Pos) /*!< Bit mask of CH5LIMITH field. */ -#define SAADC_INTEN_CH5LIMITH_Disabled (0UL) /*!< Disable */ -#define SAADC_INTEN_CH5LIMITH_Enabled (1UL) /*!< Enable */ +#define SAADC_INTEN_CH5LIMITH_Disabled (0x0UL) /*!< Disable */ +#define SAADC_INTEN_CH5LIMITH_Enabled (0x1UL) /*!< Enable */ /* Bit 15 : Enable or disable interrupt for event CH4LIMITL */ #define SAADC_INTEN_CH4LIMITL_Pos (15UL) /*!< Position of CH4LIMITL field. */ #define SAADC_INTEN_CH4LIMITL_Msk (0x1UL << SAADC_INTEN_CH4LIMITL_Pos) /*!< Bit mask of CH4LIMITL field. */ -#define SAADC_INTEN_CH4LIMITL_Disabled (0UL) /*!< Disable */ -#define SAADC_INTEN_CH4LIMITL_Enabled (1UL) /*!< Enable */ +#define SAADC_INTEN_CH4LIMITL_Disabled (0x0UL) /*!< Disable */ +#define SAADC_INTEN_CH4LIMITL_Enabled (0x1UL) /*!< Enable */ /* Bit 14 : Enable or disable interrupt for event CH4LIMITH */ #define SAADC_INTEN_CH4LIMITH_Pos (14UL) /*!< Position of CH4LIMITH field. */ #define SAADC_INTEN_CH4LIMITH_Msk (0x1UL << SAADC_INTEN_CH4LIMITH_Pos) /*!< Bit mask of CH4LIMITH field. */ -#define SAADC_INTEN_CH4LIMITH_Disabled (0UL) /*!< Disable */ -#define SAADC_INTEN_CH4LIMITH_Enabled (1UL) /*!< Enable */ +#define SAADC_INTEN_CH4LIMITH_Disabled (0x0UL) /*!< Disable */ +#define SAADC_INTEN_CH4LIMITH_Enabled (0x1UL) /*!< Enable */ /* Bit 13 : Enable or disable interrupt for event CH3LIMITL */ #define SAADC_INTEN_CH3LIMITL_Pos (13UL) /*!< Position of CH3LIMITL field. */ #define SAADC_INTEN_CH3LIMITL_Msk (0x1UL << SAADC_INTEN_CH3LIMITL_Pos) /*!< Bit mask of CH3LIMITL field. */ -#define SAADC_INTEN_CH3LIMITL_Disabled (0UL) /*!< Disable */ -#define SAADC_INTEN_CH3LIMITL_Enabled (1UL) /*!< Enable */ +#define SAADC_INTEN_CH3LIMITL_Disabled (0x0UL) /*!< Disable */ +#define SAADC_INTEN_CH3LIMITL_Enabled (0x1UL) /*!< Enable */ /* Bit 12 : Enable or disable interrupt for event CH3LIMITH */ #define SAADC_INTEN_CH3LIMITH_Pos (12UL) /*!< Position of CH3LIMITH field. */ #define SAADC_INTEN_CH3LIMITH_Msk (0x1UL << SAADC_INTEN_CH3LIMITH_Pos) /*!< Bit mask of CH3LIMITH field. */ -#define SAADC_INTEN_CH3LIMITH_Disabled (0UL) /*!< Disable */ -#define SAADC_INTEN_CH3LIMITH_Enabled (1UL) /*!< Enable */ +#define SAADC_INTEN_CH3LIMITH_Disabled (0x0UL) /*!< Disable */ +#define SAADC_INTEN_CH3LIMITH_Enabled (0x1UL) /*!< Enable */ /* Bit 11 : Enable or disable interrupt for event CH2LIMITL */ #define SAADC_INTEN_CH2LIMITL_Pos (11UL) /*!< Position of CH2LIMITL field. */ #define SAADC_INTEN_CH2LIMITL_Msk (0x1UL << SAADC_INTEN_CH2LIMITL_Pos) /*!< Bit mask of CH2LIMITL field. */ -#define SAADC_INTEN_CH2LIMITL_Disabled (0UL) /*!< Disable */ -#define SAADC_INTEN_CH2LIMITL_Enabled (1UL) /*!< Enable */ +#define SAADC_INTEN_CH2LIMITL_Disabled (0x0UL) /*!< Disable */ +#define SAADC_INTEN_CH2LIMITL_Enabled (0x1UL) /*!< Enable */ /* Bit 10 : Enable or disable interrupt for event CH2LIMITH */ #define SAADC_INTEN_CH2LIMITH_Pos (10UL) /*!< Position of CH2LIMITH field. */ #define SAADC_INTEN_CH2LIMITH_Msk (0x1UL << SAADC_INTEN_CH2LIMITH_Pos) /*!< Bit mask of CH2LIMITH field. */ -#define SAADC_INTEN_CH2LIMITH_Disabled (0UL) /*!< Disable */ -#define SAADC_INTEN_CH2LIMITH_Enabled (1UL) /*!< Enable */ +#define SAADC_INTEN_CH2LIMITH_Disabled (0x0UL) /*!< Disable */ +#define SAADC_INTEN_CH2LIMITH_Enabled (0x1UL) /*!< Enable */ /* Bit 9 : Enable or disable interrupt for event CH1LIMITL */ #define SAADC_INTEN_CH1LIMITL_Pos (9UL) /*!< Position of CH1LIMITL field. */ #define SAADC_INTEN_CH1LIMITL_Msk (0x1UL << SAADC_INTEN_CH1LIMITL_Pos) /*!< Bit mask of CH1LIMITL field. */ -#define SAADC_INTEN_CH1LIMITL_Disabled (0UL) /*!< Disable */ -#define SAADC_INTEN_CH1LIMITL_Enabled (1UL) /*!< Enable */ +#define SAADC_INTEN_CH1LIMITL_Disabled (0x0UL) /*!< Disable */ +#define SAADC_INTEN_CH1LIMITL_Enabled (0x1UL) /*!< Enable */ /* Bit 8 : Enable or disable interrupt for event CH1LIMITH */ #define SAADC_INTEN_CH1LIMITH_Pos (8UL) /*!< Position of CH1LIMITH field. */ #define SAADC_INTEN_CH1LIMITH_Msk (0x1UL << SAADC_INTEN_CH1LIMITH_Pos) /*!< Bit mask of CH1LIMITH field. */ -#define SAADC_INTEN_CH1LIMITH_Disabled (0UL) /*!< Disable */ -#define SAADC_INTEN_CH1LIMITH_Enabled (1UL) /*!< Enable */ +#define SAADC_INTEN_CH1LIMITH_Disabled (0x0UL) /*!< Disable */ +#define SAADC_INTEN_CH1LIMITH_Enabled (0x1UL) /*!< Enable */ /* Bit 7 : Enable or disable interrupt for event CH0LIMITL */ #define SAADC_INTEN_CH0LIMITL_Pos (7UL) /*!< Position of CH0LIMITL field. */ #define SAADC_INTEN_CH0LIMITL_Msk (0x1UL << SAADC_INTEN_CH0LIMITL_Pos) /*!< Bit mask of CH0LIMITL field. */ -#define SAADC_INTEN_CH0LIMITL_Disabled (0UL) /*!< Disable */ -#define SAADC_INTEN_CH0LIMITL_Enabled (1UL) /*!< Enable */ +#define SAADC_INTEN_CH0LIMITL_Disabled (0x0UL) /*!< Disable */ +#define SAADC_INTEN_CH0LIMITL_Enabled (0x1UL) /*!< Enable */ /* Bit 6 : Enable or disable interrupt for event CH0LIMITH */ #define SAADC_INTEN_CH0LIMITH_Pos (6UL) /*!< Position of CH0LIMITH field. */ #define SAADC_INTEN_CH0LIMITH_Msk (0x1UL << SAADC_INTEN_CH0LIMITH_Pos) /*!< Bit mask of CH0LIMITH field. */ -#define SAADC_INTEN_CH0LIMITH_Disabled (0UL) /*!< Disable */ -#define SAADC_INTEN_CH0LIMITH_Enabled (1UL) /*!< Enable */ +#define SAADC_INTEN_CH0LIMITH_Disabled (0x0UL) /*!< Disable */ +#define SAADC_INTEN_CH0LIMITH_Enabled (0x1UL) /*!< Enable */ /* Bit 5 : Enable or disable interrupt for event STOPPED */ #define SAADC_INTEN_STOPPED_Pos (5UL) /*!< Position of STOPPED field. */ #define SAADC_INTEN_STOPPED_Msk (0x1UL << SAADC_INTEN_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ -#define SAADC_INTEN_STOPPED_Disabled (0UL) /*!< Disable */ -#define SAADC_INTEN_STOPPED_Enabled (1UL) /*!< Enable */ +#define SAADC_INTEN_STOPPED_Disabled (0x0UL) /*!< Disable */ +#define SAADC_INTEN_STOPPED_Enabled (0x1UL) /*!< Enable */ /* Bit 4 : Enable or disable interrupt for event CALIBRATEDONE */ #define SAADC_INTEN_CALIBRATEDONE_Pos (4UL) /*!< Position of CALIBRATEDONE field. */ #define SAADC_INTEN_CALIBRATEDONE_Msk (0x1UL << SAADC_INTEN_CALIBRATEDONE_Pos) /*!< Bit mask of CALIBRATEDONE field. */ -#define SAADC_INTEN_CALIBRATEDONE_Disabled (0UL) /*!< Disable */ -#define SAADC_INTEN_CALIBRATEDONE_Enabled (1UL) /*!< Enable */ +#define SAADC_INTEN_CALIBRATEDONE_Disabled (0x0UL) /*!< Disable */ +#define SAADC_INTEN_CALIBRATEDONE_Enabled (0x1UL) /*!< Enable */ /* Bit 3 : Enable or disable interrupt for event RESULTDONE */ #define SAADC_INTEN_RESULTDONE_Pos (3UL) /*!< Position of RESULTDONE field. */ #define SAADC_INTEN_RESULTDONE_Msk (0x1UL << SAADC_INTEN_RESULTDONE_Pos) /*!< Bit mask of RESULTDONE field. */ -#define SAADC_INTEN_RESULTDONE_Disabled (0UL) /*!< Disable */ -#define SAADC_INTEN_RESULTDONE_Enabled (1UL) /*!< Enable */ +#define SAADC_INTEN_RESULTDONE_Disabled (0x0UL) /*!< Disable */ +#define SAADC_INTEN_RESULTDONE_Enabled (0x1UL) /*!< Enable */ /* Bit 2 : Enable or disable interrupt for event DONE */ #define SAADC_INTEN_DONE_Pos (2UL) /*!< Position of DONE field. */ #define SAADC_INTEN_DONE_Msk (0x1UL << SAADC_INTEN_DONE_Pos) /*!< Bit mask of DONE field. */ -#define SAADC_INTEN_DONE_Disabled (0UL) /*!< Disable */ -#define SAADC_INTEN_DONE_Enabled (1UL) /*!< Enable */ +#define SAADC_INTEN_DONE_Disabled (0x0UL) /*!< Disable */ +#define SAADC_INTEN_DONE_Enabled (0x1UL) /*!< Enable */ /* Bit 1 : Enable or disable interrupt for event END */ #define SAADC_INTEN_END_Pos (1UL) /*!< Position of END field. */ #define SAADC_INTEN_END_Msk (0x1UL << SAADC_INTEN_END_Pos) /*!< Bit mask of END field. */ -#define SAADC_INTEN_END_Disabled (0UL) /*!< Disable */ -#define SAADC_INTEN_END_Enabled (1UL) /*!< Enable */ +#define SAADC_INTEN_END_Disabled (0x0UL) /*!< Disable */ +#define SAADC_INTEN_END_Enabled (0x1UL) /*!< Enable */ /* Bit 0 : Enable or disable interrupt for event STARTED */ #define SAADC_INTEN_STARTED_Pos (0UL) /*!< Position of STARTED field. */ #define SAADC_INTEN_STARTED_Msk (0x1UL << SAADC_INTEN_STARTED_Pos) /*!< Bit mask of STARTED field. */ -#define SAADC_INTEN_STARTED_Disabled (0UL) /*!< Disable */ -#define SAADC_INTEN_STARTED_Enabled (1UL) /*!< Enable */ +#define SAADC_INTEN_STARTED_Disabled (0x0UL) /*!< Disable */ +#define SAADC_INTEN_STARTED_Enabled (0x1UL) /*!< Enable */ /* Register: SAADC_INTENSET */ /* Description: Enable interrupt */ @@ -6416,156 +6416,156 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 21 : Write '1' to enable interrupt for event CH7LIMITL */ #define SAADC_INTENSET_CH7LIMITL_Pos (21UL) /*!< Position of CH7LIMITL field. */ #define SAADC_INTENSET_CH7LIMITL_Msk (0x1UL << SAADC_INTENSET_CH7LIMITL_Pos) /*!< Bit mask of CH7LIMITL field. */ -#define SAADC_INTENSET_CH7LIMITL_Disabled (0UL) /*!< Read: Disabled */ -#define SAADC_INTENSET_CH7LIMITL_Enabled (1UL) /*!< Read: Enabled */ -#define SAADC_INTENSET_CH7LIMITL_Set (1UL) /*!< Enable */ +#define SAADC_INTENSET_CH7LIMITL_Disabled (0x0UL) /*!< Read: Disabled */ +#define SAADC_INTENSET_CH7LIMITL_Enabled (0x1UL) /*!< Read: Enabled */ +#define SAADC_INTENSET_CH7LIMITL_Set (0x1UL) /*!< Enable */ /* Bit 20 : Write '1' to enable interrupt for event CH7LIMITH */ #define SAADC_INTENSET_CH7LIMITH_Pos (20UL) /*!< Position of CH7LIMITH field. */ #define SAADC_INTENSET_CH7LIMITH_Msk (0x1UL << SAADC_INTENSET_CH7LIMITH_Pos) /*!< Bit mask of CH7LIMITH field. */ -#define SAADC_INTENSET_CH7LIMITH_Disabled (0UL) /*!< Read: Disabled */ -#define SAADC_INTENSET_CH7LIMITH_Enabled (1UL) /*!< Read: Enabled */ -#define SAADC_INTENSET_CH7LIMITH_Set (1UL) /*!< Enable */ +#define SAADC_INTENSET_CH7LIMITH_Disabled (0x0UL) /*!< Read: Disabled */ +#define SAADC_INTENSET_CH7LIMITH_Enabled (0x1UL) /*!< Read: Enabled */ +#define SAADC_INTENSET_CH7LIMITH_Set (0x1UL) /*!< Enable */ /* Bit 19 : Write '1' to enable interrupt for event CH6LIMITL */ #define SAADC_INTENSET_CH6LIMITL_Pos (19UL) /*!< Position of CH6LIMITL field. */ #define SAADC_INTENSET_CH6LIMITL_Msk (0x1UL << SAADC_INTENSET_CH6LIMITL_Pos) /*!< Bit mask of CH6LIMITL field. */ -#define SAADC_INTENSET_CH6LIMITL_Disabled (0UL) /*!< Read: Disabled */ -#define SAADC_INTENSET_CH6LIMITL_Enabled (1UL) /*!< Read: Enabled */ -#define SAADC_INTENSET_CH6LIMITL_Set (1UL) /*!< Enable */ +#define SAADC_INTENSET_CH6LIMITL_Disabled (0x0UL) /*!< Read: Disabled */ +#define SAADC_INTENSET_CH6LIMITL_Enabled (0x1UL) /*!< Read: Enabled */ +#define SAADC_INTENSET_CH6LIMITL_Set (0x1UL) /*!< Enable */ /* Bit 18 : Write '1' to enable interrupt for event CH6LIMITH */ #define SAADC_INTENSET_CH6LIMITH_Pos (18UL) /*!< Position of CH6LIMITH field. */ #define SAADC_INTENSET_CH6LIMITH_Msk (0x1UL << SAADC_INTENSET_CH6LIMITH_Pos) /*!< Bit mask of CH6LIMITH field. */ -#define SAADC_INTENSET_CH6LIMITH_Disabled (0UL) /*!< Read: Disabled */ -#define SAADC_INTENSET_CH6LIMITH_Enabled (1UL) /*!< Read: Enabled */ -#define SAADC_INTENSET_CH6LIMITH_Set (1UL) /*!< Enable */ +#define SAADC_INTENSET_CH6LIMITH_Disabled (0x0UL) /*!< Read: Disabled */ +#define SAADC_INTENSET_CH6LIMITH_Enabled (0x1UL) /*!< Read: Enabled */ +#define SAADC_INTENSET_CH6LIMITH_Set (0x1UL) /*!< Enable */ /* Bit 17 : Write '1' to enable interrupt for event CH5LIMITL */ #define SAADC_INTENSET_CH5LIMITL_Pos (17UL) /*!< Position of CH5LIMITL field. */ #define SAADC_INTENSET_CH5LIMITL_Msk (0x1UL << SAADC_INTENSET_CH5LIMITL_Pos) /*!< Bit mask of CH5LIMITL field. */ -#define SAADC_INTENSET_CH5LIMITL_Disabled (0UL) /*!< Read: Disabled */ -#define SAADC_INTENSET_CH5LIMITL_Enabled (1UL) /*!< Read: Enabled */ -#define SAADC_INTENSET_CH5LIMITL_Set (1UL) /*!< Enable */ +#define SAADC_INTENSET_CH5LIMITL_Disabled (0x0UL) /*!< Read: Disabled */ +#define SAADC_INTENSET_CH5LIMITL_Enabled (0x1UL) /*!< Read: Enabled */ +#define SAADC_INTENSET_CH5LIMITL_Set (0x1UL) /*!< Enable */ /* Bit 16 : Write '1' to enable interrupt for event CH5LIMITH */ #define SAADC_INTENSET_CH5LIMITH_Pos (16UL) /*!< Position of CH5LIMITH field. */ #define SAADC_INTENSET_CH5LIMITH_Msk (0x1UL << SAADC_INTENSET_CH5LIMITH_Pos) /*!< Bit mask of CH5LIMITH field. */ -#define SAADC_INTENSET_CH5LIMITH_Disabled (0UL) /*!< Read: Disabled */ -#define SAADC_INTENSET_CH5LIMITH_Enabled (1UL) /*!< Read: Enabled */ -#define SAADC_INTENSET_CH5LIMITH_Set (1UL) /*!< Enable */ +#define SAADC_INTENSET_CH5LIMITH_Disabled (0x0UL) /*!< Read: Disabled */ +#define SAADC_INTENSET_CH5LIMITH_Enabled (0x1UL) /*!< Read: Enabled */ +#define SAADC_INTENSET_CH5LIMITH_Set (0x1UL) /*!< Enable */ /* Bit 15 : Write '1' to enable interrupt for event CH4LIMITL */ #define SAADC_INTENSET_CH4LIMITL_Pos (15UL) /*!< Position of CH4LIMITL field. */ #define SAADC_INTENSET_CH4LIMITL_Msk (0x1UL << SAADC_INTENSET_CH4LIMITL_Pos) /*!< Bit mask of CH4LIMITL field. */ -#define SAADC_INTENSET_CH4LIMITL_Disabled (0UL) /*!< Read: Disabled */ -#define SAADC_INTENSET_CH4LIMITL_Enabled (1UL) /*!< Read: Enabled */ -#define SAADC_INTENSET_CH4LIMITL_Set (1UL) /*!< Enable */ +#define SAADC_INTENSET_CH4LIMITL_Disabled (0x0UL) /*!< Read: Disabled */ +#define SAADC_INTENSET_CH4LIMITL_Enabled (0x1UL) /*!< Read: Enabled */ +#define SAADC_INTENSET_CH4LIMITL_Set (0x1UL) /*!< Enable */ /* Bit 14 : Write '1' to enable interrupt for event CH4LIMITH */ #define SAADC_INTENSET_CH4LIMITH_Pos (14UL) /*!< Position of CH4LIMITH field. */ #define SAADC_INTENSET_CH4LIMITH_Msk (0x1UL << SAADC_INTENSET_CH4LIMITH_Pos) /*!< Bit mask of CH4LIMITH field. */ -#define SAADC_INTENSET_CH4LIMITH_Disabled (0UL) /*!< Read: Disabled */ -#define SAADC_INTENSET_CH4LIMITH_Enabled (1UL) /*!< Read: Enabled */ -#define SAADC_INTENSET_CH4LIMITH_Set (1UL) /*!< Enable */ +#define SAADC_INTENSET_CH4LIMITH_Disabled (0x0UL) /*!< Read: Disabled */ +#define SAADC_INTENSET_CH4LIMITH_Enabled (0x1UL) /*!< Read: Enabled */ +#define SAADC_INTENSET_CH4LIMITH_Set (0x1UL) /*!< Enable */ /* Bit 13 : Write '1' to enable interrupt for event CH3LIMITL */ #define SAADC_INTENSET_CH3LIMITL_Pos (13UL) /*!< Position of CH3LIMITL field. */ #define SAADC_INTENSET_CH3LIMITL_Msk (0x1UL << SAADC_INTENSET_CH3LIMITL_Pos) /*!< Bit mask of CH3LIMITL field. */ -#define SAADC_INTENSET_CH3LIMITL_Disabled (0UL) /*!< Read: Disabled */ -#define SAADC_INTENSET_CH3LIMITL_Enabled (1UL) /*!< Read: Enabled */ -#define SAADC_INTENSET_CH3LIMITL_Set (1UL) /*!< Enable */ +#define SAADC_INTENSET_CH3LIMITL_Disabled (0x0UL) /*!< Read: Disabled */ +#define SAADC_INTENSET_CH3LIMITL_Enabled (0x1UL) /*!< Read: Enabled */ +#define SAADC_INTENSET_CH3LIMITL_Set (0x1UL) /*!< Enable */ /* Bit 12 : Write '1' to enable interrupt for event CH3LIMITH */ #define SAADC_INTENSET_CH3LIMITH_Pos (12UL) /*!< Position of CH3LIMITH field. */ #define SAADC_INTENSET_CH3LIMITH_Msk (0x1UL << SAADC_INTENSET_CH3LIMITH_Pos) /*!< Bit mask of CH3LIMITH field. */ -#define SAADC_INTENSET_CH3LIMITH_Disabled (0UL) /*!< Read: Disabled */ -#define SAADC_INTENSET_CH3LIMITH_Enabled (1UL) /*!< Read: Enabled */ -#define SAADC_INTENSET_CH3LIMITH_Set (1UL) /*!< Enable */ +#define SAADC_INTENSET_CH3LIMITH_Disabled (0x0UL) /*!< Read: Disabled */ +#define SAADC_INTENSET_CH3LIMITH_Enabled (0x1UL) /*!< Read: Enabled */ +#define SAADC_INTENSET_CH3LIMITH_Set (0x1UL) /*!< Enable */ /* Bit 11 : Write '1' to enable interrupt for event CH2LIMITL */ #define SAADC_INTENSET_CH2LIMITL_Pos (11UL) /*!< Position of CH2LIMITL field. */ #define SAADC_INTENSET_CH2LIMITL_Msk (0x1UL << SAADC_INTENSET_CH2LIMITL_Pos) /*!< Bit mask of CH2LIMITL field. */ -#define SAADC_INTENSET_CH2LIMITL_Disabled (0UL) /*!< Read: Disabled */ -#define SAADC_INTENSET_CH2LIMITL_Enabled (1UL) /*!< Read: Enabled */ -#define SAADC_INTENSET_CH2LIMITL_Set (1UL) /*!< Enable */ +#define SAADC_INTENSET_CH2LIMITL_Disabled (0x0UL) /*!< Read: Disabled */ +#define SAADC_INTENSET_CH2LIMITL_Enabled (0x1UL) /*!< Read: Enabled */ +#define SAADC_INTENSET_CH2LIMITL_Set (0x1UL) /*!< Enable */ /* Bit 10 : Write '1' to enable interrupt for event CH2LIMITH */ #define SAADC_INTENSET_CH2LIMITH_Pos (10UL) /*!< Position of CH2LIMITH field. */ #define SAADC_INTENSET_CH2LIMITH_Msk (0x1UL << SAADC_INTENSET_CH2LIMITH_Pos) /*!< Bit mask of CH2LIMITH field. */ -#define SAADC_INTENSET_CH2LIMITH_Disabled (0UL) /*!< Read: Disabled */ -#define SAADC_INTENSET_CH2LIMITH_Enabled (1UL) /*!< Read: Enabled */ -#define SAADC_INTENSET_CH2LIMITH_Set (1UL) /*!< Enable */ +#define SAADC_INTENSET_CH2LIMITH_Disabled (0x0UL) /*!< Read: Disabled */ +#define SAADC_INTENSET_CH2LIMITH_Enabled (0x1UL) /*!< Read: Enabled */ +#define SAADC_INTENSET_CH2LIMITH_Set (0x1UL) /*!< Enable */ /* Bit 9 : Write '1' to enable interrupt for event CH1LIMITL */ #define SAADC_INTENSET_CH1LIMITL_Pos (9UL) /*!< Position of CH1LIMITL field. */ #define SAADC_INTENSET_CH1LIMITL_Msk (0x1UL << SAADC_INTENSET_CH1LIMITL_Pos) /*!< Bit mask of CH1LIMITL field. */ -#define SAADC_INTENSET_CH1LIMITL_Disabled (0UL) /*!< Read: Disabled */ -#define SAADC_INTENSET_CH1LIMITL_Enabled (1UL) /*!< Read: Enabled */ -#define SAADC_INTENSET_CH1LIMITL_Set (1UL) /*!< Enable */ +#define SAADC_INTENSET_CH1LIMITL_Disabled (0x0UL) /*!< Read: Disabled */ +#define SAADC_INTENSET_CH1LIMITL_Enabled (0x1UL) /*!< Read: Enabled */ +#define SAADC_INTENSET_CH1LIMITL_Set (0x1UL) /*!< Enable */ /* Bit 8 : Write '1' to enable interrupt for event CH1LIMITH */ #define SAADC_INTENSET_CH1LIMITH_Pos (8UL) /*!< Position of CH1LIMITH field. */ #define SAADC_INTENSET_CH1LIMITH_Msk (0x1UL << SAADC_INTENSET_CH1LIMITH_Pos) /*!< Bit mask of CH1LIMITH field. */ -#define SAADC_INTENSET_CH1LIMITH_Disabled (0UL) /*!< Read: Disabled */ -#define SAADC_INTENSET_CH1LIMITH_Enabled (1UL) /*!< Read: Enabled */ -#define SAADC_INTENSET_CH1LIMITH_Set (1UL) /*!< Enable */ +#define SAADC_INTENSET_CH1LIMITH_Disabled (0x0UL) /*!< Read: Disabled */ +#define SAADC_INTENSET_CH1LIMITH_Enabled (0x1UL) /*!< Read: Enabled */ +#define SAADC_INTENSET_CH1LIMITH_Set (0x1UL) /*!< Enable */ /* Bit 7 : Write '1' to enable interrupt for event CH0LIMITL */ #define SAADC_INTENSET_CH0LIMITL_Pos (7UL) /*!< Position of CH0LIMITL field. */ #define SAADC_INTENSET_CH0LIMITL_Msk (0x1UL << SAADC_INTENSET_CH0LIMITL_Pos) /*!< Bit mask of CH0LIMITL field. */ -#define SAADC_INTENSET_CH0LIMITL_Disabled (0UL) /*!< Read: Disabled */ -#define SAADC_INTENSET_CH0LIMITL_Enabled (1UL) /*!< Read: Enabled */ -#define SAADC_INTENSET_CH0LIMITL_Set (1UL) /*!< Enable */ +#define SAADC_INTENSET_CH0LIMITL_Disabled (0x0UL) /*!< Read: Disabled */ +#define SAADC_INTENSET_CH0LIMITL_Enabled (0x1UL) /*!< Read: Enabled */ +#define SAADC_INTENSET_CH0LIMITL_Set (0x1UL) /*!< Enable */ /* Bit 6 : Write '1' to enable interrupt for event CH0LIMITH */ #define SAADC_INTENSET_CH0LIMITH_Pos (6UL) /*!< Position of CH0LIMITH field. */ #define SAADC_INTENSET_CH0LIMITH_Msk (0x1UL << SAADC_INTENSET_CH0LIMITH_Pos) /*!< Bit mask of CH0LIMITH field. */ -#define SAADC_INTENSET_CH0LIMITH_Disabled (0UL) /*!< Read: Disabled */ -#define SAADC_INTENSET_CH0LIMITH_Enabled (1UL) /*!< Read: Enabled */ -#define SAADC_INTENSET_CH0LIMITH_Set (1UL) /*!< Enable */ +#define SAADC_INTENSET_CH0LIMITH_Disabled (0x0UL) /*!< Read: Disabled */ +#define SAADC_INTENSET_CH0LIMITH_Enabled (0x1UL) /*!< Read: Enabled */ +#define SAADC_INTENSET_CH0LIMITH_Set (0x1UL) /*!< Enable */ /* Bit 5 : Write '1' to enable interrupt for event STOPPED */ #define SAADC_INTENSET_STOPPED_Pos (5UL) /*!< Position of STOPPED field. */ #define SAADC_INTENSET_STOPPED_Msk (0x1UL << SAADC_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ -#define SAADC_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */ -#define SAADC_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */ -#define SAADC_INTENSET_STOPPED_Set (1UL) /*!< Enable */ +#define SAADC_INTENSET_STOPPED_Disabled (0x0UL) /*!< Read: Disabled */ +#define SAADC_INTENSET_STOPPED_Enabled (0x1UL) /*!< Read: Enabled */ +#define SAADC_INTENSET_STOPPED_Set (0x1UL) /*!< Enable */ /* Bit 4 : Write '1' to enable interrupt for event CALIBRATEDONE */ #define SAADC_INTENSET_CALIBRATEDONE_Pos (4UL) /*!< Position of CALIBRATEDONE field. */ #define SAADC_INTENSET_CALIBRATEDONE_Msk (0x1UL << SAADC_INTENSET_CALIBRATEDONE_Pos) /*!< Bit mask of CALIBRATEDONE field. */ -#define SAADC_INTENSET_CALIBRATEDONE_Disabled (0UL) /*!< Read: Disabled */ -#define SAADC_INTENSET_CALIBRATEDONE_Enabled (1UL) /*!< Read: Enabled */ -#define SAADC_INTENSET_CALIBRATEDONE_Set (1UL) /*!< Enable */ +#define SAADC_INTENSET_CALIBRATEDONE_Disabled (0x0UL) /*!< Read: Disabled */ +#define SAADC_INTENSET_CALIBRATEDONE_Enabled (0x1UL) /*!< Read: Enabled */ +#define SAADC_INTENSET_CALIBRATEDONE_Set (0x1UL) /*!< Enable */ /* Bit 3 : Write '1' to enable interrupt for event RESULTDONE */ #define SAADC_INTENSET_RESULTDONE_Pos (3UL) /*!< Position of RESULTDONE field. */ #define SAADC_INTENSET_RESULTDONE_Msk (0x1UL << SAADC_INTENSET_RESULTDONE_Pos) /*!< Bit mask of RESULTDONE field. */ -#define SAADC_INTENSET_RESULTDONE_Disabled (0UL) /*!< Read: Disabled */ -#define SAADC_INTENSET_RESULTDONE_Enabled (1UL) /*!< Read: Enabled */ -#define SAADC_INTENSET_RESULTDONE_Set (1UL) /*!< Enable */ +#define SAADC_INTENSET_RESULTDONE_Disabled (0x0UL) /*!< Read: Disabled */ +#define SAADC_INTENSET_RESULTDONE_Enabled (0x1UL) /*!< Read: Enabled */ +#define SAADC_INTENSET_RESULTDONE_Set (0x1UL) /*!< Enable */ /* Bit 2 : Write '1' to enable interrupt for event DONE */ #define SAADC_INTENSET_DONE_Pos (2UL) /*!< Position of DONE field. */ #define SAADC_INTENSET_DONE_Msk (0x1UL << SAADC_INTENSET_DONE_Pos) /*!< Bit mask of DONE field. */ -#define SAADC_INTENSET_DONE_Disabled (0UL) /*!< Read: Disabled */ -#define SAADC_INTENSET_DONE_Enabled (1UL) /*!< Read: Enabled */ -#define SAADC_INTENSET_DONE_Set (1UL) /*!< Enable */ +#define SAADC_INTENSET_DONE_Disabled (0x0UL) /*!< Read: Disabled */ +#define SAADC_INTENSET_DONE_Enabled (0x1UL) /*!< Read: Enabled */ +#define SAADC_INTENSET_DONE_Set (0x1UL) /*!< Enable */ /* Bit 1 : Write '1' to enable interrupt for event END */ #define SAADC_INTENSET_END_Pos (1UL) /*!< Position of END field. */ #define SAADC_INTENSET_END_Msk (0x1UL << SAADC_INTENSET_END_Pos) /*!< Bit mask of END field. */ -#define SAADC_INTENSET_END_Disabled (0UL) /*!< Read: Disabled */ -#define SAADC_INTENSET_END_Enabled (1UL) /*!< Read: Enabled */ -#define SAADC_INTENSET_END_Set (1UL) /*!< Enable */ +#define SAADC_INTENSET_END_Disabled (0x0UL) /*!< Read: Disabled */ +#define SAADC_INTENSET_END_Enabled (0x1UL) /*!< Read: Enabled */ +#define SAADC_INTENSET_END_Set (0x1UL) /*!< Enable */ /* Bit 0 : Write '1' to enable interrupt for event STARTED */ #define SAADC_INTENSET_STARTED_Pos (0UL) /*!< Position of STARTED field. */ #define SAADC_INTENSET_STARTED_Msk (0x1UL << SAADC_INTENSET_STARTED_Pos) /*!< Bit mask of STARTED field. */ -#define SAADC_INTENSET_STARTED_Disabled (0UL) /*!< Read: Disabled */ -#define SAADC_INTENSET_STARTED_Enabled (1UL) /*!< Read: Enabled */ -#define SAADC_INTENSET_STARTED_Set (1UL) /*!< Enable */ +#define SAADC_INTENSET_STARTED_Disabled (0x0UL) /*!< Read: Disabled */ +#define SAADC_INTENSET_STARTED_Enabled (0x1UL) /*!< Read: Enabled */ +#define SAADC_INTENSET_STARTED_Set (0x1UL) /*!< Enable */ /* Register: SAADC_INTENCLR */ /* Description: Disable interrupt */ @@ -6573,156 +6573,156 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 21 : Write '1' to disable interrupt for event CH7LIMITL */ #define SAADC_INTENCLR_CH7LIMITL_Pos (21UL) /*!< Position of CH7LIMITL field. */ #define SAADC_INTENCLR_CH7LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH7LIMITL_Pos) /*!< Bit mask of CH7LIMITL field. */ -#define SAADC_INTENCLR_CH7LIMITL_Disabled (0UL) /*!< Read: Disabled */ -#define SAADC_INTENCLR_CH7LIMITL_Enabled (1UL) /*!< Read: Enabled */ -#define SAADC_INTENCLR_CH7LIMITL_Clear (1UL) /*!< Disable */ +#define SAADC_INTENCLR_CH7LIMITL_Disabled (0x0UL) /*!< Read: Disabled */ +#define SAADC_INTENCLR_CH7LIMITL_Enabled (0x1UL) /*!< Read: Enabled */ +#define SAADC_INTENCLR_CH7LIMITL_Clear (0x1UL) /*!< Disable */ /* Bit 20 : Write '1' to disable interrupt for event CH7LIMITH */ #define SAADC_INTENCLR_CH7LIMITH_Pos (20UL) /*!< Position of CH7LIMITH field. */ #define SAADC_INTENCLR_CH7LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH7LIMITH_Pos) /*!< Bit mask of CH7LIMITH field. */ -#define SAADC_INTENCLR_CH7LIMITH_Disabled (0UL) /*!< Read: Disabled */ -#define SAADC_INTENCLR_CH7LIMITH_Enabled (1UL) /*!< Read: Enabled */ -#define SAADC_INTENCLR_CH7LIMITH_Clear (1UL) /*!< Disable */ +#define SAADC_INTENCLR_CH7LIMITH_Disabled (0x0UL) /*!< Read: Disabled */ +#define SAADC_INTENCLR_CH7LIMITH_Enabled (0x1UL) /*!< Read: Enabled */ +#define SAADC_INTENCLR_CH7LIMITH_Clear (0x1UL) /*!< Disable */ /* Bit 19 : Write '1' to disable interrupt for event CH6LIMITL */ #define SAADC_INTENCLR_CH6LIMITL_Pos (19UL) /*!< Position of CH6LIMITL field. */ #define SAADC_INTENCLR_CH6LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH6LIMITL_Pos) /*!< Bit mask of CH6LIMITL field. */ -#define SAADC_INTENCLR_CH6LIMITL_Disabled (0UL) /*!< Read: Disabled */ -#define SAADC_INTENCLR_CH6LIMITL_Enabled (1UL) /*!< Read: Enabled */ -#define SAADC_INTENCLR_CH6LIMITL_Clear (1UL) /*!< Disable */ +#define SAADC_INTENCLR_CH6LIMITL_Disabled (0x0UL) /*!< Read: Disabled */ +#define SAADC_INTENCLR_CH6LIMITL_Enabled (0x1UL) /*!< Read: Enabled */ +#define SAADC_INTENCLR_CH6LIMITL_Clear (0x1UL) /*!< Disable */ /* Bit 18 : Write '1' to disable interrupt for event CH6LIMITH */ #define SAADC_INTENCLR_CH6LIMITH_Pos (18UL) /*!< Position of CH6LIMITH field. */ #define SAADC_INTENCLR_CH6LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH6LIMITH_Pos) /*!< Bit mask of CH6LIMITH field. */ -#define SAADC_INTENCLR_CH6LIMITH_Disabled (0UL) /*!< Read: Disabled */ -#define SAADC_INTENCLR_CH6LIMITH_Enabled (1UL) /*!< Read: Enabled */ -#define SAADC_INTENCLR_CH6LIMITH_Clear (1UL) /*!< Disable */ +#define SAADC_INTENCLR_CH6LIMITH_Disabled (0x0UL) /*!< Read: Disabled */ +#define SAADC_INTENCLR_CH6LIMITH_Enabled (0x1UL) /*!< Read: Enabled */ +#define SAADC_INTENCLR_CH6LIMITH_Clear (0x1UL) /*!< Disable */ /* Bit 17 : Write '1' to disable interrupt for event CH5LIMITL */ #define SAADC_INTENCLR_CH5LIMITL_Pos (17UL) /*!< Position of CH5LIMITL field. */ #define SAADC_INTENCLR_CH5LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH5LIMITL_Pos) /*!< Bit mask of CH5LIMITL field. */ -#define SAADC_INTENCLR_CH5LIMITL_Disabled (0UL) /*!< Read: Disabled */ -#define SAADC_INTENCLR_CH5LIMITL_Enabled (1UL) /*!< Read: Enabled */ -#define SAADC_INTENCLR_CH5LIMITL_Clear (1UL) /*!< Disable */ +#define SAADC_INTENCLR_CH5LIMITL_Disabled (0x0UL) /*!< Read: Disabled */ +#define SAADC_INTENCLR_CH5LIMITL_Enabled (0x1UL) /*!< Read: Enabled */ +#define SAADC_INTENCLR_CH5LIMITL_Clear (0x1UL) /*!< Disable */ /* Bit 16 : Write '1' to disable interrupt for event CH5LIMITH */ #define SAADC_INTENCLR_CH5LIMITH_Pos (16UL) /*!< Position of CH5LIMITH field. */ #define SAADC_INTENCLR_CH5LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH5LIMITH_Pos) /*!< Bit mask of CH5LIMITH field. */ -#define SAADC_INTENCLR_CH5LIMITH_Disabled (0UL) /*!< Read: Disabled */ -#define SAADC_INTENCLR_CH5LIMITH_Enabled (1UL) /*!< Read: Enabled */ -#define SAADC_INTENCLR_CH5LIMITH_Clear (1UL) /*!< Disable */ +#define SAADC_INTENCLR_CH5LIMITH_Disabled (0x0UL) /*!< Read: Disabled */ +#define SAADC_INTENCLR_CH5LIMITH_Enabled (0x1UL) /*!< Read: Enabled */ +#define SAADC_INTENCLR_CH5LIMITH_Clear (0x1UL) /*!< Disable */ /* Bit 15 : Write '1' to disable interrupt for event CH4LIMITL */ #define SAADC_INTENCLR_CH4LIMITL_Pos (15UL) /*!< Position of CH4LIMITL field. */ #define SAADC_INTENCLR_CH4LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH4LIMITL_Pos) /*!< Bit mask of CH4LIMITL field. */ -#define SAADC_INTENCLR_CH4LIMITL_Disabled (0UL) /*!< Read: Disabled */ -#define SAADC_INTENCLR_CH4LIMITL_Enabled (1UL) /*!< Read: Enabled */ -#define SAADC_INTENCLR_CH4LIMITL_Clear (1UL) /*!< Disable */ +#define SAADC_INTENCLR_CH4LIMITL_Disabled (0x0UL) /*!< Read: Disabled */ +#define SAADC_INTENCLR_CH4LIMITL_Enabled (0x1UL) /*!< Read: Enabled */ +#define SAADC_INTENCLR_CH4LIMITL_Clear (0x1UL) /*!< Disable */ /* Bit 14 : Write '1' to disable interrupt for event CH4LIMITH */ #define SAADC_INTENCLR_CH4LIMITH_Pos (14UL) /*!< Position of CH4LIMITH field. */ #define SAADC_INTENCLR_CH4LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH4LIMITH_Pos) /*!< Bit mask of CH4LIMITH field. */ -#define SAADC_INTENCLR_CH4LIMITH_Disabled (0UL) /*!< Read: Disabled */ -#define SAADC_INTENCLR_CH4LIMITH_Enabled (1UL) /*!< Read: Enabled */ -#define SAADC_INTENCLR_CH4LIMITH_Clear (1UL) /*!< Disable */ +#define SAADC_INTENCLR_CH4LIMITH_Disabled (0x0UL) /*!< Read: Disabled */ +#define SAADC_INTENCLR_CH4LIMITH_Enabled (0x1UL) /*!< Read: Enabled */ +#define SAADC_INTENCLR_CH4LIMITH_Clear (0x1UL) /*!< Disable */ /* Bit 13 : Write '1' to disable interrupt for event CH3LIMITL */ #define SAADC_INTENCLR_CH3LIMITL_Pos (13UL) /*!< Position of CH3LIMITL field. */ #define SAADC_INTENCLR_CH3LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH3LIMITL_Pos) /*!< Bit mask of CH3LIMITL field. */ -#define SAADC_INTENCLR_CH3LIMITL_Disabled (0UL) /*!< Read: Disabled */ -#define SAADC_INTENCLR_CH3LIMITL_Enabled (1UL) /*!< Read: Enabled */ -#define SAADC_INTENCLR_CH3LIMITL_Clear (1UL) /*!< Disable */ +#define SAADC_INTENCLR_CH3LIMITL_Disabled (0x0UL) /*!< Read: Disabled */ +#define SAADC_INTENCLR_CH3LIMITL_Enabled (0x1UL) /*!< Read: Enabled */ +#define SAADC_INTENCLR_CH3LIMITL_Clear (0x1UL) /*!< Disable */ /* Bit 12 : Write '1' to disable interrupt for event CH3LIMITH */ #define SAADC_INTENCLR_CH3LIMITH_Pos (12UL) /*!< Position of CH3LIMITH field. */ #define SAADC_INTENCLR_CH3LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH3LIMITH_Pos) /*!< Bit mask of CH3LIMITH field. */ -#define SAADC_INTENCLR_CH3LIMITH_Disabled (0UL) /*!< Read: Disabled */ -#define SAADC_INTENCLR_CH3LIMITH_Enabled (1UL) /*!< Read: Enabled */ -#define SAADC_INTENCLR_CH3LIMITH_Clear (1UL) /*!< Disable */ +#define SAADC_INTENCLR_CH3LIMITH_Disabled (0x0UL) /*!< Read: Disabled */ +#define SAADC_INTENCLR_CH3LIMITH_Enabled (0x1UL) /*!< Read: Enabled */ +#define SAADC_INTENCLR_CH3LIMITH_Clear (0x1UL) /*!< Disable */ /* Bit 11 : Write '1' to disable interrupt for event CH2LIMITL */ #define SAADC_INTENCLR_CH2LIMITL_Pos (11UL) /*!< Position of CH2LIMITL field. */ #define SAADC_INTENCLR_CH2LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH2LIMITL_Pos) /*!< Bit mask of CH2LIMITL field. */ -#define SAADC_INTENCLR_CH2LIMITL_Disabled (0UL) /*!< Read: Disabled */ -#define SAADC_INTENCLR_CH2LIMITL_Enabled (1UL) /*!< Read: Enabled */ -#define SAADC_INTENCLR_CH2LIMITL_Clear (1UL) /*!< Disable */ +#define SAADC_INTENCLR_CH2LIMITL_Disabled (0x0UL) /*!< Read: Disabled */ +#define SAADC_INTENCLR_CH2LIMITL_Enabled (0x1UL) /*!< Read: Enabled */ +#define SAADC_INTENCLR_CH2LIMITL_Clear (0x1UL) /*!< Disable */ /* Bit 10 : Write '1' to disable interrupt for event CH2LIMITH */ #define SAADC_INTENCLR_CH2LIMITH_Pos (10UL) /*!< Position of CH2LIMITH field. */ #define SAADC_INTENCLR_CH2LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH2LIMITH_Pos) /*!< Bit mask of CH2LIMITH field. */ -#define SAADC_INTENCLR_CH2LIMITH_Disabled (0UL) /*!< Read: Disabled */ -#define SAADC_INTENCLR_CH2LIMITH_Enabled (1UL) /*!< Read: Enabled */ -#define SAADC_INTENCLR_CH2LIMITH_Clear (1UL) /*!< Disable */ +#define SAADC_INTENCLR_CH2LIMITH_Disabled (0x0UL) /*!< Read: Disabled */ +#define SAADC_INTENCLR_CH2LIMITH_Enabled (0x1UL) /*!< Read: Enabled */ +#define SAADC_INTENCLR_CH2LIMITH_Clear (0x1UL) /*!< Disable */ /* Bit 9 : Write '1' to disable interrupt for event CH1LIMITL */ #define SAADC_INTENCLR_CH1LIMITL_Pos (9UL) /*!< Position of CH1LIMITL field. */ #define SAADC_INTENCLR_CH1LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH1LIMITL_Pos) /*!< Bit mask of CH1LIMITL field. */ -#define SAADC_INTENCLR_CH1LIMITL_Disabled (0UL) /*!< Read: Disabled */ -#define SAADC_INTENCLR_CH1LIMITL_Enabled (1UL) /*!< Read: Enabled */ -#define SAADC_INTENCLR_CH1LIMITL_Clear (1UL) /*!< Disable */ +#define SAADC_INTENCLR_CH1LIMITL_Disabled (0x0UL) /*!< Read: Disabled */ +#define SAADC_INTENCLR_CH1LIMITL_Enabled (0x1UL) /*!< Read: Enabled */ +#define SAADC_INTENCLR_CH1LIMITL_Clear (0x1UL) /*!< Disable */ /* Bit 8 : Write '1' to disable interrupt for event CH1LIMITH */ #define SAADC_INTENCLR_CH1LIMITH_Pos (8UL) /*!< Position of CH1LIMITH field. */ #define SAADC_INTENCLR_CH1LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH1LIMITH_Pos) /*!< Bit mask of CH1LIMITH field. */ -#define SAADC_INTENCLR_CH1LIMITH_Disabled (0UL) /*!< Read: Disabled */ -#define SAADC_INTENCLR_CH1LIMITH_Enabled (1UL) /*!< Read: Enabled */ -#define SAADC_INTENCLR_CH1LIMITH_Clear (1UL) /*!< Disable */ +#define SAADC_INTENCLR_CH1LIMITH_Disabled (0x0UL) /*!< Read: Disabled */ +#define SAADC_INTENCLR_CH1LIMITH_Enabled (0x1UL) /*!< Read: Enabled */ +#define SAADC_INTENCLR_CH1LIMITH_Clear (0x1UL) /*!< Disable */ /* Bit 7 : Write '1' to disable interrupt for event CH0LIMITL */ #define SAADC_INTENCLR_CH0LIMITL_Pos (7UL) /*!< Position of CH0LIMITL field. */ #define SAADC_INTENCLR_CH0LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH0LIMITL_Pos) /*!< Bit mask of CH0LIMITL field. */ -#define SAADC_INTENCLR_CH0LIMITL_Disabled (0UL) /*!< Read: Disabled */ -#define SAADC_INTENCLR_CH0LIMITL_Enabled (1UL) /*!< Read: Enabled */ -#define SAADC_INTENCLR_CH0LIMITL_Clear (1UL) /*!< Disable */ +#define SAADC_INTENCLR_CH0LIMITL_Disabled (0x0UL) /*!< Read: Disabled */ +#define SAADC_INTENCLR_CH0LIMITL_Enabled (0x1UL) /*!< Read: Enabled */ +#define SAADC_INTENCLR_CH0LIMITL_Clear (0x1UL) /*!< Disable */ /* Bit 6 : Write '1' to disable interrupt for event CH0LIMITH */ #define SAADC_INTENCLR_CH0LIMITH_Pos (6UL) /*!< Position of CH0LIMITH field. */ #define SAADC_INTENCLR_CH0LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH0LIMITH_Pos) /*!< Bit mask of CH0LIMITH field. */ -#define SAADC_INTENCLR_CH0LIMITH_Disabled (0UL) /*!< Read: Disabled */ -#define SAADC_INTENCLR_CH0LIMITH_Enabled (1UL) /*!< Read: Enabled */ -#define SAADC_INTENCLR_CH0LIMITH_Clear (1UL) /*!< Disable */ +#define SAADC_INTENCLR_CH0LIMITH_Disabled (0x0UL) /*!< Read: Disabled */ +#define SAADC_INTENCLR_CH0LIMITH_Enabled (0x1UL) /*!< Read: Enabled */ +#define SAADC_INTENCLR_CH0LIMITH_Clear (0x1UL) /*!< Disable */ /* Bit 5 : Write '1' to disable interrupt for event STOPPED */ #define SAADC_INTENCLR_STOPPED_Pos (5UL) /*!< Position of STOPPED field. */ #define SAADC_INTENCLR_STOPPED_Msk (0x1UL << SAADC_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ -#define SAADC_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */ -#define SAADC_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */ -#define SAADC_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */ +#define SAADC_INTENCLR_STOPPED_Disabled (0x0UL) /*!< Read: Disabled */ +#define SAADC_INTENCLR_STOPPED_Enabled (0x1UL) /*!< Read: Enabled */ +#define SAADC_INTENCLR_STOPPED_Clear (0x1UL) /*!< Disable */ /* Bit 4 : Write '1' to disable interrupt for event CALIBRATEDONE */ #define SAADC_INTENCLR_CALIBRATEDONE_Pos (4UL) /*!< Position of CALIBRATEDONE field. */ #define SAADC_INTENCLR_CALIBRATEDONE_Msk (0x1UL << SAADC_INTENCLR_CALIBRATEDONE_Pos) /*!< Bit mask of CALIBRATEDONE field. */ -#define SAADC_INTENCLR_CALIBRATEDONE_Disabled (0UL) /*!< Read: Disabled */ -#define SAADC_INTENCLR_CALIBRATEDONE_Enabled (1UL) /*!< Read: Enabled */ -#define SAADC_INTENCLR_CALIBRATEDONE_Clear (1UL) /*!< Disable */ +#define SAADC_INTENCLR_CALIBRATEDONE_Disabled (0x0UL) /*!< Read: Disabled */ +#define SAADC_INTENCLR_CALIBRATEDONE_Enabled (0x1UL) /*!< Read: Enabled */ +#define SAADC_INTENCLR_CALIBRATEDONE_Clear (0x1UL) /*!< Disable */ /* Bit 3 : Write '1' to disable interrupt for event RESULTDONE */ #define SAADC_INTENCLR_RESULTDONE_Pos (3UL) /*!< Position of RESULTDONE field. */ #define SAADC_INTENCLR_RESULTDONE_Msk (0x1UL << SAADC_INTENCLR_RESULTDONE_Pos) /*!< Bit mask of RESULTDONE field. */ -#define SAADC_INTENCLR_RESULTDONE_Disabled (0UL) /*!< Read: Disabled */ -#define SAADC_INTENCLR_RESULTDONE_Enabled (1UL) /*!< Read: Enabled */ -#define SAADC_INTENCLR_RESULTDONE_Clear (1UL) /*!< Disable */ +#define SAADC_INTENCLR_RESULTDONE_Disabled (0x0UL) /*!< Read: Disabled */ +#define SAADC_INTENCLR_RESULTDONE_Enabled (0x1UL) /*!< Read: Enabled */ +#define SAADC_INTENCLR_RESULTDONE_Clear (0x1UL) /*!< Disable */ /* Bit 2 : Write '1' to disable interrupt for event DONE */ #define SAADC_INTENCLR_DONE_Pos (2UL) /*!< Position of DONE field. */ #define SAADC_INTENCLR_DONE_Msk (0x1UL << SAADC_INTENCLR_DONE_Pos) /*!< Bit mask of DONE field. */ -#define SAADC_INTENCLR_DONE_Disabled (0UL) /*!< Read: Disabled */ -#define SAADC_INTENCLR_DONE_Enabled (1UL) /*!< Read: Enabled */ -#define SAADC_INTENCLR_DONE_Clear (1UL) /*!< Disable */ +#define SAADC_INTENCLR_DONE_Disabled (0x0UL) /*!< Read: Disabled */ +#define SAADC_INTENCLR_DONE_Enabled (0x1UL) /*!< Read: Enabled */ +#define SAADC_INTENCLR_DONE_Clear (0x1UL) /*!< Disable */ /* Bit 1 : Write '1' to disable interrupt for event END */ #define SAADC_INTENCLR_END_Pos (1UL) /*!< Position of END field. */ #define SAADC_INTENCLR_END_Msk (0x1UL << SAADC_INTENCLR_END_Pos) /*!< Bit mask of END field. */ -#define SAADC_INTENCLR_END_Disabled (0UL) /*!< Read: Disabled */ -#define SAADC_INTENCLR_END_Enabled (1UL) /*!< Read: Enabled */ -#define SAADC_INTENCLR_END_Clear (1UL) /*!< Disable */ +#define SAADC_INTENCLR_END_Disabled (0x0UL) /*!< Read: Disabled */ +#define SAADC_INTENCLR_END_Enabled (0x1UL) /*!< Read: Enabled */ +#define SAADC_INTENCLR_END_Clear (0x1UL) /*!< Disable */ /* Bit 0 : Write '1' to disable interrupt for event STARTED */ #define SAADC_INTENCLR_STARTED_Pos (0UL) /*!< Position of STARTED field. */ #define SAADC_INTENCLR_STARTED_Msk (0x1UL << SAADC_INTENCLR_STARTED_Pos) /*!< Bit mask of STARTED field. */ -#define SAADC_INTENCLR_STARTED_Disabled (0UL) /*!< Read: Disabled */ -#define SAADC_INTENCLR_STARTED_Enabled (1UL) /*!< Read: Enabled */ -#define SAADC_INTENCLR_STARTED_Clear (1UL) /*!< Disable */ +#define SAADC_INTENCLR_STARTED_Disabled (0x0UL) /*!< Read: Disabled */ +#define SAADC_INTENCLR_STARTED_Enabled (0x1UL) /*!< Read: Enabled */ +#define SAADC_INTENCLR_STARTED_Clear (0x1UL) /*!< Disable */ /* Register: SAADC_STATUS */ /* Description: Status */ @@ -6730,8 +6730,8 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 0 : Status */ #define SAADC_STATUS_STATUS_Pos (0UL) /*!< Position of STATUS field. */ #define SAADC_STATUS_STATUS_Msk (0x1UL << SAADC_STATUS_STATUS_Pos) /*!< Bit mask of STATUS field. */ -#define SAADC_STATUS_STATUS_Ready (0UL) /*!< ADC is ready. No on-going conversion. */ -#define SAADC_STATUS_STATUS_Busy (1UL) /*!< ADC is busy. Single conversion in progress. */ +#define SAADC_STATUS_STATUS_Ready (0x0UL) /*!< ADC is ready. No on-going conversion. */ +#define SAADC_STATUS_STATUS_Busy (0x1UL) /*!< ADC is busy. Single conversion in progress. */ /* Register: SAADC_ENABLE */ /* Description: Enable or disable ADC */ @@ -6739,8 +6739,8 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 0 : Enable or disable ADC */ #define SAADC_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ #define SAADC_ENABLE_ENABLE_Msk (0x1UL << SAADC_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ -#define SAADC_ENABLE_ENABLE_Disabled (0UL) /*!< Disable ADC */ -#define SAADC_ENABLE_ENABLE_Enabled (1UL) /*!< Enable ADC */ +#define SAADC_ENABLE_ENABLE_Disabled (0x0UL) /*!< Disable ADC */ +#define SAADC_ENABLE_ENABLE_Enabled (0x1UL) /*!< Enable ADC */ /* Register: SAADC_CH_PSELP */ /* Description: Description cluster: Input positive pin selection for CH[n] */ @@ -6748,16 +6748,16 @@ POSSIBILITY OF SUCH DAMAGE. /* Bits 4..0 : Analog positive input channel */ #define SAADC_CH_PSELP_PSELP_Pos (0UL) /*!< Position of PSELP field. */ #define SAADC_CH_PSELP_PSELP_Msk (0x1FUL << SAADC_CH_PSELP_PSELP_Pos) /*!< Bit mask of PSELP field. */ -#define SAADC_CH_PSELP_PSELP_NC (0UL) /*!< Not connected */ -#define SAADC_CH_PSELP_PSELP_AnalogInput0 (1UL) /*!< AIN0 */ -#define SAADC_CH_PSELP_PSELP_AnalogInput1 (2UL) /*!< AIN1 */ -#define SAADC_CH_PSELP_PSELP_AnalogInput2 (3UL) /*!< AIN2 */ -#define SAADC_CH_PSELP_PSELP_AnalogInput3 (4UL) /*!< AIN3 */ -#define SAADC_CH_PSELP_PSELP_AnalogInput4 (5UL) /*!< AIN4 */ -#define SAADC_CH_PSELP_PSELP_AnalogInput5 (6UL) /*!< AIN5 */ -#define SAADC_CH_PSELP_PSELP_AnalogInput6 (7UL) /*!< AIN6 */ -#define SAADC_CH_PSELP_PSELP_AnalogInput7 (8UL) /*!< AIN7 */ -#define SAADC_CH_PSELP_PSELP_VDDGPIO (9UL) /*!< VDD_GPIO */ +#define SAADC_CH_PSELP_PSELP_NC (0x00UL) /*!< Not connected */ +#define SAADC_CH_PSELP_PSELP_AnalogInput0 (0x01UL) /*!< AIN0 */ +#define SAADC_CH_PSELP_PSELP_AnalogInput1 (0x02UL) /*!< AIN1 */ +#define SAADC_CH_PSELP_PSELP_AnalogInput2 (0x03UL) /*!< AIN2 */ +#define SAADC_CH_PSELP_PSELP_AnalogInput3 (0x04UL) /*!< AIN3 */ +#define SAADC_CH_PSELP_PSELP_AnalogInput4 (0x05UL) /*!< AIN4 */ +#define SAADC_CH_PSELP_PSELP_AnalogInput5 (0x06UL) /*!< AIN5 */ +#define SAADC_CH_PSELP_PSELP_AnalogInput6 (0x07UL) /*!< AIN6 */ +#define SAADC_CH_PSELP_PSELP_AnalogInput7 (0x08UL) /*!< AIN7 */ +#define SAADC_CH_PSELP_PSELP_VDDGPIO (0x09UL) /*!< VDD_GPIO */ /* Register: SAADC_CH_PSELN */ /* Description: Description cluster: Input negative pin selection for CH[n] */ @@ -6765,16 +6765,16 @@ POSSIBILITY OF SUCH DAMAGE. /* Bits 4..0 : Analog negative input, enables differential channel */ #define SAADC_CH_PSELN_PSELN_Pos (0UL) /*!< Position of PSELN field. */ #define SAADC_CH_PSELN_PSELN_Msk (0x1FUL << SAADC_CH_PSELN_PSELN_Pos) /*!< Bit mask of PSELN field. */ -#define SAADC_CH_PSELN_PSELN_NC (0UL) /*!< Not connected */ -#define SAADC_CH_PSELN_PSELN_AnalogInput0 (1UL) /*!< AIN0 */ -#define SAADC_CH_PSELN_PSELN_AnalogInput1 (2UL) /*!< AIN1 */ -#define SAADC_CH_PSELN_PSELN_AnalogInput2 (3UL) /*!< AIN2 */ -#define SAADC_CH_PSELN_PSELN_AnalogInput3 (4UL) /*!< AIN3 */ -#define SAADC_CH_PSELN_PSELN_AnalogInput4 (5UL) /*!< AIN4 */ -#define SAADC_CH_PSELN_PSELN_AnalogInput5 (6UL) /*!< AIN5 */ -#define SAADC_CH_PSELN_PSELN_AnalogInput6 (7UL) /*!< AIN6 */ -#define SAADC_CH_PSELN_PSELN_AnalogInput7 (8UL) /*!< AIN7 */ -#define SAADC_CH_PSELN_PSELN_VDD_GPIO (9UL) /*!< VDD_GPIO */ +#define SAADC_CH_PSELN_PSELN_NC (0x00UL) /*!< Not connected */ +#define SAADC_CH_PSELN_PSELN_AnalogInput0 (0x01UL) /*!< AIN0 */ +#define SAADC_CH_PSELN_PSELN_AnalogInput1 (0x02UL) /*!< AIN1 */ +#define SAADC_CH_PSELN_PSELN_AnalogInput2 (0x03UL) /*!< AIN2 */ +#define SAADC_CH_PSELN_PSELN_AnalogInput3 (0x04UL) /*!< AIN3 */ +#define SAADC_CH_PSELN_PSELN_AnalogInput4 (0x05UL) /*!< AIN4 */ +#define SAADC_CH_PSELN_PSELN_AnalogInput5 (0x06UL) /*!< AIN5 */ +#define SAADC_CH_PSELN_PSELN_AnalogInput6 (0x07UL) /*!< AIN6 */ +#define SAADC_CH_PSELN_PSELN_AnalogInput7 (0x08UL) /*!< AIN7 */ +#define SAADC_CH_PSELN_PSELN_VDD_GPIO (0x09UL) /*!< VDD_GPIO */ /* Register: SAADC_CH_CONFIG */ /* Description: Description cluster: Input configuration for CH[n] */ @@ -6782,58 +6782,58 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 24 : Enable burst mode */ #define SAADC_CH_CONFIG_BURST_Pos (24UL) /*!< Position of BURST field. */ #define SAADC_CH_CONFIG_BURST_Msk (0x1UL << SAADC_CH_CONFIG_BURST_Pos) /*!< Bit mask of BURST field. */ -#define SAADC_CH_CONFIG_BURST_Disabled (0UL) /*!< Burst mode is disabled (normal operation) */ -#define SAADC_CH_CONFIG_BURST_Enabled (1UL) /*!< Burst mode is enabled. SAADC takes 2^OVERSAMPLE number of samples as fast as it can, and sends the average to Data RAM. */ +#define SAADC_CH_CONFIG_BURST_Disabled (0x0UL) /*!< Burst mode is disabled (normal operation) */ +#define SAADC_CH_CONFIG_BURST_Enabled (0x1UL) /*!< Burst mode is enabled. SAADC takes 2^OVERSAMPLE number of samples as fast as it can, and sends the average to Data RAM. */ /* Bit 20 : Enable differential mode */ #define SAADC_CH_CONFIG_MODE_Pos (20UL) /*!< Position of MODE field. */ #define SAADC_CH_CONFIG_MODE_Msk (0x1UL << SAADC_CH_CONFIG_MODE_Pos) /*!< Bit mask of MODE field. */ -#define SAADC_CH_CONFIG_MODE_SE (0UL) /*!< Single ended, PSELN will be ignored, negative input to ADC shorted to GND */ -#define SAADC_CH_CONFIG_MODE_Diff (1UL) /*!< Differential */ +#define SAADC_CH_CONFIG_MODE_SE (0x0UL) /*!< Single ended, PSELN will be ignored, negative input to ADC shorted to GND */ +#define SAADC_CH_CONFIG_MODE_Diff (0x1UL) /*!< Differential */ /* Bits 18..16 : Acquisition time, the time the ADC uses to sample the input voltage */ #define SAADC_CH_CONFIG_TACQ_Pos (16UL) /*!< Position of TACQ field. */ #define SAADC_CH_CONFIG_TACQ_Msk (0x7UL << SAADC_CH_CONFIG_TACQ_Pos) /*!< Bit mask of TACQ field. */ -#define SAADC_CH_CONFIG_TACQ_3us (0UL) /*!< 3 us */ -#define SAADC_CH_CONFIG_TACQ_5us (1UL) /*!< 5 us */ -#define SAADC_CH_CONFIG_TACQ_10us (2UL) /*!< 10 us */ -#define SAADC_CH_CONFIG_TACQ_15us (3UL) /*!< 15 us */ -#define SAADC_CH_CONFIG_TACQ_20us (4UL) /*!< 20 us */ -#define SAADC_CH_CONFIG_TACQ_40us (5UL) /*!< 40 us */ +#define SAADC_CH_CONFIG_TACQ_3us (0x0UL) /*!< 3 us */ +#define SAADC_CH_CONFIG_TACQ_5us (0x1UL) /*!< 5 us */ +#define SAADC_CH_CONFIG_TACQ_10us (0x2UL) /*!< 10 us */ +#define SAADC_CH_CONFIG_TACQ_15us (0x3UL) /*!< 15 us */ +#define SAADC_CH_CONFIG_TACQ_20us (0x4UL) /*!< 20 us */ +#define SAADC_CH_CONFIG_TACQ_40us (0x5UL) /*!< 40 us */ /* Bit 12 : Reference control */ #define SAADC_CH_CONFIG_REFSEL_Pos (12UL) /*!< Position of REFSEL field. */ #define SAADC_CH_CONFIG_REFSEL_Msk (0x1UL << SAADC_CH_CONFIG_REFSEL_Pos) /*!< Bit mask of REFSEL field. */ -#define SAADC_CH_CONFIG_REFSEL_Internal (0UL) /*!< Internal reference (0.6 V) */ -#define SAADC_CH_CONFIG_REFSEL_VDD1_4 (1UL) /*!< VDD_GPIO/4 as reference */ +#define SAADC_CH_CONFIG_REFSEL_Internal (0x0UL) /*!< Internal reference (0.6 V) */ +#define SAADC_CH_CONFIG_REFSEL_VDD1_4 (0x1UL) /*!< VDD_GPIO/4 as reference */ /* Bits 10..8 : Gain control */ #define SAADC_CH_CONFIG_GAIN_Pos (8UL) /*!< Position of GAIN field. */ #define SAADC_CH_CONFIG_GAIN_Msk (0x7UL << SAADC_CH_CONFIG_GAIN_Pos) /*!< Bit mask of GAIN field. */ -#define SAADC_CH_CONFIG_GAIN_Gain1_6 (0UL) /*!< 1/6 */ -#define SAADC_CH_CONFIG_GAIN_Gain1_5 (1UL) /*!< 1/5 */ -#define SAADC_CH_CONFIG_GAIN_Gain1_4 (2UL) /*!< 1/4 */ -#define SAADC_CH_CONFIG_GAIN_Gain1_3 (3UL) /*!< 1/3 */ -#define SAADC_CH_CONFIG_GAIN_Gain1_2 (4UL) /*!< 1/2 */ -#define SAADC_CH_CONFIG_GAIN_Gain1 (5UL) /*!< 1 */ -#define SAADC_CH_CONFIG_GAIN_Gain2 (6UL) /*!< 2 */ -#define SAADC_CH_CONFIG_GAIN_Gain4 (7UL) /*!< 4 */ +#define SAADC_CH_CONFIG_GAIN_Gain1_6 (0x0UL) /*!< 1/6 */ +#define SAADC_CH_CONFIG_GAIN_Gain1_5 (0x1UL) /*!< 1/5 */ +#define SAADC_CH_CONFIG_GAIN_Gain1_4 (0x2UL) /*!< 1/4 */ +#define SAADC_CH_CONFIG_GAIN_Gain1_3 (0x3UL) /*!< 1/3 */ +#define SAADC_CH_CONFIG_GAIN_Gain1_2 (0x4UL) /*!< 1/2 */ +#define SAADC_CH_CONFIG_GAIN_Gain1 (0x5UL) /*!< 1 */ +#define SAADC_CH_CONFIG_GAIN_Gain2 (0x6UL) /*!< 2 */ +#define SAADC_CH_CONFIG_GAIN_Gain4 (0x7UL) /*!< 4 */ /* Bits 5..4 : Negative channel resistor control */ #define SAADC_CH_CONFIG_RESN_Pos (4UL) /*!< Position of RESN field. */ #define SAADC_CH_CONFIG_RESN_Msk (0x3UL << SAADC_CH_CONFIG_RESN_Pos) /*!< Bit mask of RESN field. */ -#define SAADC_CH_CONFIG_RESN_Bypass (0UL) /*!< Bypass resistor ladder */ -#define SAADC_CH_CONFIG_RESN_Pulldown (1UL) /*!< Pull-down to GND */ -#define SAADC_CH_CONFIG_RESN_Pullup (2UL) /*!< Pull-up to VDD_GPIO */ -#define SAADC_CH_CONFIG_RESN_VDD1_2 (3UL) /*!< Set input at VDD_GPIO/2 */ +#define SAADC_CH_CONFIG_RESN_Bypass (0x0UL) /*!< Bypass resistor ladder */ +#define SAADC_CH_CONFIG_RESN_Pulldown (0x1UL) /*!< Pull-down to GND */ +#define SAADC_CH_CONFIG_RESN_Pullup (0x2UL) /*!< Pull-up to VDD_GPIO */ +#define SAADC_CH_CONFIG_RESN_VDD1_2 (0x3UL) /*!< Set input at VDD_GPIO/2 */ /* Bits 1..0 : Positive channel resistor control */ #define SAADC_CH_CONFIG_RESP_Pos (0UL) /*!< Position of RESP field. */ #define SAADC_CH_CONFIG_RESP_Msk (0x3UL << SAADC_CH_CONFIG_RESP_Pos) /*!< Bit mask of RESP field. */ -#define SAADC_CH_CONFIG_RESP_Bypass (0UL) /*!< Bypass resistor ladder */ -#define SAADC_CH_CONFIG_RESP_Pulldown (1UL) /*!< Pull-down to GND */ -#define SAADC_CH_CONFIG_RESP_Pullup (2UL) /*!< Pull-up to VDD_GPIO */ -#define SAADC_CH_CONFIG_RESP_VDD1_2 (3UL) /*!< Set input at VDD_GPIO/2 */ +#define SAADC_CH_CONFIG_RESP_Bypass (0x0UL) /*!< Bypass resistor ladder */ +#define SAADC_CH_CONFIG_RESP_Pulldown (0x1UL) /*!< Pull-down to GND */ +#define SAADC_CH_CONFIG_RESP_Pullup (0x2UL) /*!< Pull-up to VDD_GPIO */ +#define SAADC_CH_CONFIG_RESP_VDD1_2 (0x3UL) /*!< Set input at VDD_GPIO/2 */ /* Register: SAADC_CH_LIMIT */ /* Description: Description cluster: High/low limits for event monitoring a channel */ @@ -6852,10 +6852,10 @@ POSSIBILITY OF SUCH DAMAGE. /* Bits 2..0 : Set the resolution */ #define SAADC_RESOLUTION_VAL_Pos (0UL) /*!< Position of VAL field. */ #define SAADC_RESOLUTION_VAL_Msk (0x7UL << SAADC_RESOLUTION_VAL_Pos) /*!< Bit mask of VAL field. */ -#define SAADC_RESOLUTION_VAL_8bit (0UL) /*!< 8 bit */ -#define SAADC_RESOLUTION_VAL_10bit (1UL) /*!< 10 bit */ -#define SAADC_RESOLUTION_VAL_12bit (2UL) /*!< 12 bit */ -#define SAADC_RESOLUTION_VAL_14bit (3UL) /*!< 14 bit */ +#define SAADC_RESOLUTION_VAL_8bit (0x0UL) /*!< 8 bit */ +#define SAADC_RESOLUTION_VAL_10bit (0x1UL) /*!< 10 bit */ +#define SAADC_RESOLUTION_VAL_12bit (0x2UL) /*!< 12 bit */ +#define SAADC_RESOLUTION_VAL_14bit (0x3UL) /*!< 14 bit */ /* Register: SAADC_OVERSAMPLE */ /* Description: Oversampling configuration. OVERSAMPLE should not be combined with SCAN. The RESOLUTION is applied before averaging, thus for high OVERSAMPLE a higher RESOLUTION should be used. */ @@ -6863,15 +6863,15 @@ POSSIBILITY OF SUCH DAMAGE. /* Bits 3..0 : Oversample control */ #define SAADC_OVERSAMPLE_OVERSAMPLE_Pos (0UL) /*!< Position of OVERSAMPLE field. */ #define SAADC_OVERSAMPLE_OVERSAMPLE_Msk (0xFUL << SAADC_OVERSAMPLE_OVERSAMPLE_Pos) /*!< Bit mask of OVERSAMPLE field. */ -#define SAADC_OVERSAMPLE_OVERSAMPLE_Bypass (0UL) /*!< Bypass oversampling */ -#define SAADC_OVERSAMPLE_OVERSAMPLE_Over2x (1UL) /*!< Oversample 2x */ -#define SAADC_OVERSAMPLE_OVERSAMPLE_Over4x (2UL) /*!< Oversample 4x */ -#define SAADC_OVERSAMPLE_OVERSAMPLE_Over8x (3UL) /*!< Oversample 8x */ -#define SAADC_OVERSAMPLE_OVERSAMPLE_Over16x (4UL) /*!< Oversample 16x */ -#define SAADC_OVERSAMPLE_OVERSAMPLE_Over32x (5UL) /*!< Oversample 32x */ -#define SAADC_OVERSAMPLE_OVERSAMPLE_Over64x (6UL) /*!< Oversample 64x */ -#define SAADC_OVERSAMPLE_OVERSAMPLE_Over128x (7UL) /*!< Oversample 128x */ -#define SAADC_OVERSAMPLE_OVERSAMPLE_Over256x (8UL) /*!< Oversample 256x */ +#define SAADC_OVERSAMPLE_OVERSAMPLE_Bypass (0x0UL) /*!< Bypass oversampling */ +#define SAADC_OVERSAMPLE_OVERSAMPLE_Over2x (0x1UL) /*!< Oversample 2x */ +#define SAADC_OVERSAMPLE_OVERSAMPLE_Over4x (0x2UL) /*!< Oversample 4x */ +#define SAADC_OVERSAMPLE_OVERSAMPLE_Over8x (0x3UL) /*!< Oversample 8x */ +#define SAADC_OVERSAMPLE_OVERSAMPLE_Over16x (0x4UL) /*!< Oversample 16x */ +#define SAADC_OVERSAMPLE_OVERSAMPLE_Over32x (0x5UL) /*!< Oversample 32x */ +#define SAADC_OVERSAMPLE_OVERSAMPLE_Over64x (0x6UL) /*!< Oversample 64x */ +#define SAADC_OVERSAMPLE_OVERSAMPLE_Over128x (0x7UL) /*!< Oversample 128x */ +#define SAADC_OVERSAMPLE_OVERSAMPLE_Over256x (0x8UL) /*!< Oversample 256x */ /* Register: SAADC_SAMPLERATE */ /* Description: Controls normal or continuous sample rate */ @@ -6879,8 +6879,8 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 12 : Select mode for sample rate control */ #define SAADC_SAMPLERATE_MODE_Pos (12UL) /*!< Position of MODE field. */ #define SAADC_SAMPLERATE_MODE_Msk (0x1UL << SAADC_SAMPLERATE_MODE_Pos) /*!< Bit mask of MODE field. */ -#define SAADC_SAMPLERATE_MODE_Task (0UL) /*!< Rate is controlled from SAMPLE task */ -#define SAADC_SAMPLERATE_MODE_Timers (1UL) /*!< Rate is controlled from local timer (use CC to control the rate) */ +#define SAADC_SAMPLERATE_MODE_Task (0x0UL) /*!< Rate is controlled from SAMPLE task */ +#define SAADC_SAMPLERATE_MODE_Timers (0x1UL) /*!< Rate is controlled from local timer (use CC to control the rate) */ /* Bits 10..0 : Capture and compare value. Sample rate is 16 MHz/CC */ #define SAADC_SAMPLERATE_CC_Pos (0UL) /*!< Position of CC field. */ @@ -6917,7 +6917,7 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 0 : Start SPI transaction */ #define SPIM_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */ #define SPIM_TASKS_START_TASKS_START_Msk (0x1UL << SPIM_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */ -#define SPIM_TASKS_START_TASKS_START_Trigger (1UL) /*!< Trigger task */ +#define SPIM_TASKS_START_TASKS_START_Trigger (0x1UL) /*!< Trigger task */ /* Register: SPIM_TASKS_STOP */ /* Description: Stop SPI transaction */ @@ -6925,7 +6925,7 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 0 : Stop SPI transaction */ #define SPIM_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */ #define SPIM_TASKS_STOP_TASKS_STOP_Msk (0x1UL << SPIM_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */ -#define SPIM_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */ +#define SPIM_TASKS_STOP_TASKS_STOP_Trigger (0x1UL) /*!< Trigger task */ /* Register: SPIM_TASKS_SUSPEND */ /* Description: Suspend SPI transaction */ @@ -6933,7 +6933,7 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 0 : Suspend SPI transaction */ #define SPIM_TASKS_SUSPEND_TASKS_SUSPEND_Pos (0UL) /*!< Position of TASKS_SUSPEND field. */ #define SPIM_TASKS_SUSPEND_TASKS_SUSPEND_Msk (0x1UL << SPIM_TASKS_SUSPEND_TASKS_SUSPEND_Pos) /*!< Bit mask of TASKS_SUSPEND field. */ -#define SPIM_TASKS_SUSPEND_TASKS_SUSPEND_Trigger (1UL) /*!< Trigger task */ +#define SPIM_TASKS_SUSPEND_TASKS_SUSPEND_Trigger (0x1UL) /*!< Trigger task */ /* Register: SPIM_TASKS_RESUME */ /* Description: Resume SPI transaction */ @@ -6941,7 +6941,7 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 0 : Resume SPI transaction */ #define SPIM_TASKS_RESUME_TASKS_RESUME_Pos (0UL) /*!< Position of TASKS_RESUME field. */ #define SPIM_TASKS_RESUME_TASKS_RESUME_Msk (0x1UL << SPIM_TASKS_RESUME_TASKS_RESUME_Pos) /*!< Bit mask of TASKS_RESUME field. */ -#define SPIM_TASKS_RESUME_TASKS_RESUME_Trigger (1UL) /*!< Trigger task */ +#define SPIM_TASKS_RESUME_TASKS_RESUME_Trigger (0x1UL) /*!< Trigger task */ /* Register: SPIM_SUBSCRIBE_START */ /* Description: Subscribe configuration for task START */ @@ -6949,8 +6949,8 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 31 : */ #define SPIM_SUBSCRIBE_START_EN_Pos (31UL) /*!< Position of EN field. */ #define SPIM_SUBSCRIBE_START_EN_Msk (0x1UL << SPIM_SUBSCRIBE_START_EN_Pos) /*!< Bit mask of EN field. */ -#define SPIM_SUBSCRIBE_START_EN_Disabled (0UL) /*!< Disable subscription */ -#define SPIM_SUBSCRIBE_START_EN_Enabled (1UL) /*!< Enable subscription */ +#define SPIM_SUBSCRIBE_START_EN_Disabled (0x0UL) /*!< Disable subscription */ +#define SPIM_SUBSCRIBE_START_EN_Enabled (0x1UL) /*!< Enable subscription */ /* Bits 7..0 : DPPI channel that task START will subscribe to */ #define SPIM_SUBSCRIBE_START_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ @@ -6962,8 +6962,8 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 31 : */ #define SPIM_SUBSCRIBE_STOP_EN_Pos (31UL) /*!< Position of EN field. */ #define SPIM_SUBSCRIBE_STOP_EN_Msk (0x1UL << SPIM_SUBSCRIBE_STOP_EN_Pos) /*!< Bit mask of EN field. */ -#define SPIM_SUBSCRIBE_STOP_EN_Disabled (0UL) /*!< Disable subscription */ -#define SPIM_SUBSCRIBE_STOP_EN_Enabled (1UL) /*!< Enable subscription */ +#define SPIM_SUBSCRIBE_STOP_EN_Disabled (0x0UL) /*!< Disable subscription */ +#define SPIM_SUBSCRIBE_STOP_EN_Enabled (0x1UL) /*!< Enable subscription */ /* Bits 7..0 : DPPI channel that task STOP will subscribe to */ #define SPIM_SUBSCRIBE_STOP_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ @@ -6975,8 +6975,8 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 31 : */ #define SPIM_SUBSCRIBE_SUSPEND_EN_Pos (31UL) /*!< Position of EN field. */ #define SPIM_SUBSCRIBE_SUSPEND_EN_Msk (0x1UL << SPIM_SUBSCRIBE_SUSPEND_EN_Pos) /*!< Bit mask of EN field. */ -#define SPIM_SUBSCRIBE_SUSPEND_EN_Disabled (0UL) /*!< Disable subscription */ -#define SPIM_SUBSCRIBE_SUSPEND_EN_Enabled (1UL) /*!< Enable subscription */ +#define SPIM_SUBSCRIBE_SUSPEND_EN_Disabled (0x0UL) /*!< Disable subscription */ +#define SPIM_SUBSCRIBE_SUSPEND_EN_Enabled (0x1UL) /*!< Enable subscription */ /* Bits 7..0 : DPPI channel that task SUSPEND will subscribe to */ #define SPIM_SUBSCRIBE_SUSPEND_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ @@ -6988,8 +6988,8 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 31 : */ #define SPIM_SUBSCRIBE_RESUME_EN_Pos (31UL) /*!< Position of EN field. */ #define SPIM_SUBSCRIBE_RESUME_EN_Msk (0x1UL << SPIM_SUBSCRIBE_RESUME_EN_Pos) /*!< Bit mask of EN field. */ -#define SPIM_SUBSCRIBE_RESUME_EN_Disabled (0UL) /*!< Disable subscription */ -#define SPIM_SUBSCRIBE_RESUME_EN_Enabled (1UL) /*!< Enable subscription */ +#define SPIM_SUBSCRIBE_RESUME_EN_Disabled (0x0UL) /*!< Disable subscription */ +#define SPIM_SUBSCRIBE_RESUME_EN_Enabled (0x1UL) /*!< Enable subscription */ /* Bits 7..0 : DPPI channel that task RESUME will subscribe to */ #define SPIM_SUBSCRIBE_RESUME_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ @@ -7001,8 +7001,8 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 0 : SPI transaction has stopped */ #define SPIM_EVENTS_STOPPED_EVENTS_STOPPED_Pos (0UL) /*!< Position of EVENTS_STOPPED field. */ #define SPIM_EVENTS_STOPPED_EVENTS_STOPPED_Msk (0x1UL << SPIM_EVENTS_STOPPED_EVENTS_STOPPED_Pos) /*!< Bit mask of EVENTS_STOPPED field. */ -#define SPIM_EVENTS_STOPPED_EVENTS_STOPPED_NotGenerated (0UL) /*!< Event not generated */ -#define SPIM_EVENTS_STOPPED_EVENTS_STOPPED_Generated (1UL) /*!< Event generated */ +#define SPIM_EVENTS_STOPPED_EVENTS_STOPPED_NotGenerated (0x0UL) /*!< Event not generated */ +#define SPIM_EVENTS_STOPPED_EVENTS_STOPPED_Generated (0x1UL) /*!< Event generated */ /* Register: SPIM_EVENTS_ENDRX */ /* Description: End of RXD buffer reached */ @@ -7010,8 +7010,8 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 0 : End of RXD buffer reached */ #define SPIM_EVENTS_ENDRX_EVENTS_ENDRX_Pos (0UL) /*!< Position of EVENTS_ENDRX field. */ #define SPIM_EVENTS_ENDRX_EVENTS_ENDRX_Msk (0x1UL << SPIM_EVENTS_ENDRX_EVENTS_ENDRX_Pos) /*!< Bit mask of EVENTS_ENDRX field. */ -#define SPIM_EVENTS_ENDRX_EVENTS_ENDRX_NotGenerated (0UL) /*!< Event not generated */ -#define SPIM_EVENTS_ENDRX_EVENTS_ENDRX_Generated (1UL) /*!< Event generated */ +#define SPIM_EVENTS_ENDRX_EVENTS_ENDRX_NotGenerated (0x0UL) /*!< Event not generated */ +#define SPIM_EVENTS_ENDRX_EVENTS_ENDRX_Generated (0x1UL) /*!< Event generated */ /* Register: SPIM_EVENTS_END */ /* Description: End of RXD buffer and TXD buffer reached */ @@ -7019,8 +7019,8 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 0 : End of RXD buffer and TXD buffer reached */ #define SPIM_EVENTS_END_EVENTS_END_Pos (0UL) /*!< Position of EVENTS_END field. */ #define SPIM_EVENTS_END_EVENTS_END_Msk (0x1UL << SPIM_EVENTS_END_EVENTS_END_Pos) /*!< Bit mask of EVENTS_END field. */ -#define SPIM_EVENTS_END_EVENTS_END_NotGenerated (0UL) /*!< Event not generated */ -#define SPIM_EVENTS_END_EVENTS_END_Generated (1UL) /*!< Event generated */ +#define SPIM_EVENTS_END_EVENTS_END_NotGenerated (0x0UL) /*!< Event not generated */ +#define SPIM_EVENTS_END_EVENTS_END_Generated (0x1UL) /*!< Event generated */ /* Register: SPIM_EVENTS_ENDTX */ /* Description: End of TXD buffer reached */ @@ -7028,8 +7028,8 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 0 : End of TXD buffer reached */ #define SPIM_EVENTS_ENDTX_EVENTS_ENDTX_Pos (0UL) /*!< Position of EVENTS_ENDTX field. */ #define SPIM_EVENTS_ENDTX_EVENTS_ENDTX_Msk (0x1UL << SPIM_EVENTS_ENDTX_EVENTS_ENDTX_Pos) /*!< Bit mask of EVENTS_ENDTX field. */ -#define SPIM_EVENTS_ENDTX_EVENTS_ENDTX_NotGenerated (0UL) /*!< Event not generated */ -#define SPIM_EVENTS_ENDTX_EVENTS_ENDTX_Generated (1UL) /*!< Event generated */ +#define SPIM_EVENTS_ENDTX_EVENTS_ENDTX_NotGenerated (0x0UL) /*!< Event not generated */ +#define SPIM_EVENTS_ENDTX_EVENTS_ENDTX_Generated (0x1UL) /*!< Event generated */ /* Register: SPIM_EVENTS_STARTED */ /* Description: Transaction started */ @@ -7037,8 +7037,8 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 0 : Transaction started */ #define SPIM_EVENTS_STARTED_EVENTS_STARTED_Pos (0UL) /*!< Position of EVENTS_STARTED field. */ #define SPIM_EVENTS_STARTED_EVENTS_STARTED_Msk (0x1UL << SPIM_EVENTS_STARTED_EVENTS_STARTED_Pos) /*!< Bit mask of EVENTS_STARTED field. */ -#define SPIM_EVENTS_STARTED_EVENTS_STARTED_NotGenerated (0UL) /*!< Event not generated */ -#define SPIM_EVENTS_STARTED_EVENTS_STARTED_Generated (1UL) /*!< Event generated */ +#define SPIM_EVENTS_STARTED_EVENTS_STARTED_NotGenerated (0x0UL) /*!< Event not generated */ +#define SPIM_EVENTS_STARTED_EVENTS_STARTED_Generated (0x1UL) /*!< Event generated */ /* Register: SPIM_PUBLISH_STOPPED */ /* Description: Publish configuration for event STOPPED */ @@ -7046,8 +7046,8 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 31 : */ #define SPIM_PUBLISH_STOPPED_EN_Pos (31UL) /*!< Position of EN field. */ #define SPIM_PUBLISH_STOPPED_EN_Msk (0x1UL << SPIM_PUBLISH_STOPPED_EN_Pos) /*!< Bit mask of EN field. */ -#define SPIM_PUBLISH_STOPPED_EN_Disabled (0UL) /*!< Disable publishing */ -#define SPIM_PUBLISH_STOPPED_EN_Enabled (1UL) /*!< Enable publishing */ +#define SPIM_PUBLISH_STOPPED_EN_Disabled (0x0UL) /*!< Disable publishing */ +#define SPIM_PUBLISH_STOPPED_EN_Enabled (0x1UL) /*!< Enable publishing */ /* Bits 7..0 : DPPI channel that event STOPPED will publish to */ #define SPIM_PUBLISH_STOPPED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ @@ -7059,8 +7059,8 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 31 : */ #define SPIM_PUBLISH_ENDRX_EN_Pos (31UL) /*!< Position of EN field. */ #define SPIM_PUBLISH_ENDRX_EN_Msk (0x1UL << SPIM_PUBLISH_ENDRX_EN_Pos) /*!< Bit mask of EN field. */ -#define SPIM_PUBLISH_ENDRX_EN_Disabled (0UL) /*!< Disable publishing */ -#define SPIM_PUBLISH_ENDRX_EN_Enabled (1UL) /*!< Enable publishing */ +#define SPIM_PUBLISH_ENDRX_EN_Disabled (0x0UL) /*!< Disable publishing */ +#define SPIM_PUBLISH_ENDRX_EN_Enabled (0x1UL) /*!< Enable publishing */ /* Bits 7..0 : DPPI channel that event ENDRX will publish to */ #define SPIM_PUBLISH_ENDRX_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ @@ -7072,8 +7072,8 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 31 : */ #define SPIM_PUBLISH_END_EN_Pos (31UL) /*!< Position of EN field. */ #define SPIM_PUBLISH_END_EN_Msk (0x1UL << SPIM_PUBLISH_END_EN_Pos) /*!< Bit mask of EN field. */ -#define SPIM_PUBLISH_END_EN_Disabled (0UL) /*!< Disable publishing */ -#define SPIM_PUBLISH_END_EN_Enabled (1UL) /*!< Enable publishing */ +#define SPIM_PUBLISH_END_EN_Disabled (0x0UL) /*!< Disable publishing */ +#define SPIM_PUBLISH_END_EN_Enabled (0x1UL) /*!< Enable publishing */ /* Bits 7..0 : DPPI channel that event END will publish to */ #define SPIM_PUBLISH_END_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ @@ -7085,8 +7085,8 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 31 : */ #define SPIM_PUBLISH_ENDTX_EN_Pos (31UL) /*!< Position of EN field. */ #define SPIM_PUBLISH_ENDTX_EN_Msk (0x1UL << SPIM_PUBLISH_ENDTX_EN_Pos) /*!< Bit mask of EN field. */ -#define SPIM_PUBLISH_ENDTX_EN_Disabled (0UL) /*!< Disable publishing */ -#define SPIM_PUBLISH_ENDTX_EN_Enabled (1UL) /*!< Enable publishing */ +#define SPIM_PUBLISH_ENDTX_EN_Disabled (0x0UL) /*!< Disable publishing */ +#define SPIM_PUBLISH_ENDTX_EN_Enabled (0x1UL) /*!< Enable publishing */ /* Bits 7..0 : DPPI channel that event ENDTX will publish to */ #define SPIM_PUBLISH_ENDTX_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ @@ -7098,8 +7098,8 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 31 : */ #define SPIM_PUBLISH_STARTED_EN_Pos (31UL) /*!< Position of EN field. */ #define SPIM_PUBLISH_STARTED_EN_Msk (0x1UL << SPIM_PUBLISH_STARTED_EN_Pos) /*!< Bit mask of EN field. */ -#define SPIM_PUBLISH_STARTED_EN_Disabled (0UL) /*!< Disable publishing */ -#define SPIM_PUBLISH_STARTED_EN_Enabled (1UL) /*!< Enable publishing */ +#define SPIM_PUBLISH_STARTED_EN_Disabled (0x0UL) /*!< Disable publishing */ +#define SPIM_PUBLISH_STARTED_EN_Enabled (0x1UL) /*!< Enable publishing */ /* Bits 7..0 : DPPI channel that event STARTED will publish to */ #define SPIM_PUBLISH_STARTED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ @@ -7111,8 +7111,8 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 17 : Shortcut between event END and task START */ #define SPIM_SHORTS_END_START_Pos (17UL) /*!< Position of END_START field. */ #define SPIM_SHORTS_END_START_Msk (0x1UL << SPIM_SHORTS_END_START_Pos) /*!< Bit mask of END_START field. */ -#define SPIM_SHORTS_END_START_Disabled (0UL) /*!< Disable shortcut */ -#define SPIM_SHORTS_END_START_Enabled (1UL) /*!< Enable shortcut */ +#define SPIM_SHORTS_END_START_Disabled (0x0UL) /*!< Disable shortcut */ +#define SPIM_SHORTS_END_START_Enabled (0x1UL) /*!< Enable shortcut */ /* Register: SPIM_INTENSET */ /* Description: Enable interrupt */ @@ -7120,37 +7120,37 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 19 : Write '1' to enable interrupt for event STARTED */ #define SPIM_INTENSET_STARTED_Pos (19UL) /*!< Position of STARTED field. */ #define SPIM_INTENSET_STARTED_Msk (0x1UL << SPIM_INTENSET_STARTED_Pos) /*!< Bit mask of STARTED field. */ -#define SPIM_INTENSET_STARTED_Disabled (0UL) /*!< Read: Disabled */ -#define SPIM_INTENSET_STARTED_Enabled (1UL) /*!< Read: Enabled */ -#define SPIM_INTENSET_STARTED_Set (1UL) /*!< Enable */ +#define SPIM_INTENSET_STARTED_Disabled (0x0UL) /*!< Read: Disabled */ +#define SPIM_INTENSET_STARTED_Enabled (0x1UL) /*!< Read: Enabled */ +#define SPIM_INTENSET_STARTED_Set (0x1UL) /*!< Enable */ /* Bit 8 : Write '1' to enable interrupt for event ENDTX */ #define SPIM_INTENSET_ENDTX_Pos (8UL) /*!< Position of ENDTX field. */ #define SPIM_INTENSET_ENDTX_Msk (0x1UL << SPIM_INTENSET_ENDTX_Pos) /*!< Bit mask of ENDTX field. */ -#define SPIM_INTENSET_ENDTX_Disabled (0UL) /*!< Read: Disabled */ -#define SPIM_INTENSET_ENDTX_Enabled (1UL) /*!< Read: Enabled */ -#define SPIM_INTENSET_ENDTX_Set (1UL) /*!< Enable */ +#define SPIM_INTENSET_ENDTX_Disabled (0x0UL) /*!< Read: Disabled */ +#define SPIM_INTENSET_ENDTX_Enabled (0x1UL) /*!< Read: Enabled */ +#define SPIM_INTENSET_ENDTX_Set (0x1UL) /*!< Enable */ /* Bit 6 : Write '1' to enable interrupt for event END */ #define SPIM_INTENSET_END_Pos (6UL) /*!< Position of END field. */ #define SPIM_INTENSET_END_Msk (0x1UL << SPIM_INTENSET_END_Pos) /*!< Bit mask of END field. */ -#define SPIM_INTENSET_END_Disabled (0UL) /*!< Read: Disabled */ -#define SPIM_INTENSET_END_Enabled (1UL) /*!< Read: Enabled */ -#define SPIM_INTENSET_END_Set (1UL) /*!< Enable */ +#define SPIM_INTENSET_END_Disabled (0x0UL) /*!< Read: Disabled */ +#define SPIM_INTENSET_END_Enabled (0x1UL) /*!< Read: Enabled */ +#define SPIM_INTENSET_END_Set (0x1UL) /*!< Enable */ /* Bit 4 : Write '1' to enable interrupt for event ENDRX */ #define SPIM_INTENSET_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */ #define SPIM_INTENSET_ENDRX_Msk (0x1UL << SPIM_INTENSET_ENDRX_Pos) /*!< Bit mask of ENDRX field. */ -#define SPIM_INTENSET_ENDRX_Disabled (0UL) /*!< Read: Disabled */ -#define SPIM_INTENSET_ENDRX_Enabled (1UL) /*!< Read: Enabled */ -#define SPIM_INTENSET_ENDRX_Set (1UL) /*!< Enable */ +#define SPIM_INTENSET_ENDRX_Disabled (0x0UL) /*!< Read: Disabled */ +#define SPIM_INTENSET_ENDRX_Enabled (0x1UL) /*!< Read: Enabled */ +#define SPIM_INTENSET_ENDRX_Set (0x1UL) /*!< Enable */ /* Bit 1 : Write '1' to enable interrupt for event STOPPED */ #define SPIM_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ #define SPIM_INTENSET_STOPPED_Msk (0x1UL << SPIM_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ -#define SPIM_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */ -#define SPIM_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */ -#define SPIM_INTENSET_STOPPED_Set (1UL) /*!< Enable */ +#define SPIM_INTENSET_STOPPED_Disabled (0x0UL) /*!< Read: Disabled */ +#define SPIM_INTENSET_STOPPED_Enabled (0x1UL) /*!< Read: Enabled */ +#define SPIM_INTENSET_STOPPED_Set (0x1UL) /*!< Enable */ /* Register: SPIM_INTENCLR */ /* Description: Disable interrupt */ @@ -7158,37 +7158,37 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 19 : Write '1' to disable interrupt for event STARTED */ #define SPIM_INTENCLR_STARTED_Pos (19UL) /*!< Position of STARTED field. */ #define SPIM_INTENCLR_STARTED_Msk (0x1UL << SPIM_INTENCLR_STARTED_Pos) /*!< Bit mask of STARTED field. */ -#define SPIM_INTENCLR_STARTED_Disabled (0UL) /*!< Read: Disabled */ -#define SPIM_INTENCLR_STARTED_Enabled (1UL) /*!< Read: Enabled */ -#define SPIM_INTENCLR_STARTED_Clear (1UL) /*!< Disable */ +#define SPIM_INTENCLR_STARTED_Disabled (0x0UL) /*!< Read: Disabled */ +#define SPIM_INTENCLR_STARTED_Enabled (0x1UL) /*!< Read: Enabled */ +#define SPIM_INTENCLR_STARTED_Clear (0x1UL) /*!< Disable */ /* Bit 8 : Write '1' to disable interrupt for event ENDTX */ #define SPIM_INTENCLR_ENDTX_Pos (8UL) /*!< Position of ENDTX field. */ #define SPIM_INTENCLR_ENDTX_Msk (0x1UL << SPIM_INTENCLR_ENDTX_Pos) /*!< Bit mask of ENDTX field. */ -#define SPIM_INTENCLR_ENDTX_Disabled (0UL) /*!< Read: Disabled */ -#define SPIM_INTENCLR_ENDTX_Enabled (1UL) /*!< Read: Enabled */ -#define SPIM_INTENCLR_ENDTX_Clear (1UL) /*!< Disable */ +#define SPIM_INTENCLR_ENDTX_Disabled (0x0UL) /*!< Read: Disabled */ +#define SPIM_INTENCLR_ENDTX_Enabled (0x1UL) /*!< Read: Enabled */ +#define SPIM_INTENCLR_ENDTX_Clear (0x1UL) /*!< Disable */ /* Bit 6 : Write '1' to disable interrupt for event END */ #define SPIM_INTENCLR_END_Pos (6UL) /*!< Position of END field. */ #define SPIM_INTENCLR_END_Msk (0x1UL << SPIM_INTENCLR_END_Pos) /*!< Bit mask of END field. */ -#define SPIM_INTENCLR_END_Disabled (0UL) /*!< Read: Disabled */ -#define SPIM_INTENCLR_END_Enabled (1UL) /*!< Read: Enabled */ -#define SPIM_INTENCLR_END_Clear (1UL) /*!< Disable */ +#define SPIM_INTENCLR_END_Disabled (0x0UL) /*!< Read: Disabled */ +#define SPIM_INTENCLR_END_Enabled (0x1UL) /*!< Read: Enabled */ +#define SPIM_INTENCLR_END_Clear (0x1UL) /*!< Disable */ /* Bit 4 : Write '1' to disable interrupt for event ENDRX */ #define SPIM_INTENCLR_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */ #define SPIM_INTENCLR_ENDRX_Msk (0x1UL << SPIM_INTENCLR_ENDRX_Pos) /*!< Bit mask of ENDRX field. */ -#define SPIM_INTENCLR_ENDRX_Disabled (0UL) /*!< Read: Disabled */ -#define SPIM_INTENCLR_ENDRX_Enabled (1UL) /*!< Read: Enabled */ -#define SPIM_INTENCLR_ENDRX_Clear (1UL) /*!< Disable */ +#define SPIM_INTENCLR_ENDRX_Disabled (0x0UL) /*!< Read: Disabled */ +#define SPIM_INTENCLR_ENDRX_Enabled (0x1UL) /*!< Read: Enabled */ +#define SPIM_INTENCLR_ENDRX_Clear (0x1UL) /*!< Disable */ /* Bit 1 : Write '1' to disable interrupt for event STOPPED */ #define SPIM_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ #define SPIM_INTENCLR_STOPPED_Msk (0x1UL << SPIM_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ -#define SPIM_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */ -#define SPIM_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */ -#define SPIM_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */ +#define SPIM_INTENCLR_STOPPED_Disabled (0x0UL) /*!< Read: Disabled */ +#define SPIM_INTENCLR_STOPPED_Enabled (0x1UL) /*!< Read: Enabled */ +#define SPIM_INTENCLR_STOPPED_Clear (0x1UL) /*!< Disable */ /* Register: SPIM_ENABLE */ /* Description: Enable SPIM */ @@ -7196,8 +7196,8 @@ POSSIBILITY OF SUCH DAMAGE. /* Bits 3..0 : Enable or disable SPIM */ #define SPIM_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ #define SPIM_ENABLE_ENABLE_Msk (0xFUL << SPIM_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ -#define SPIM_ENABLE_ENABLE_Disabled (0UL) /*!< Disable SPIM */ -#define SPIM_ENABLE_ENABLE_Enabled (7UL) /*!< Enable SPIM */ +#define SPIM_ENABLE_ENABLE_Disabled (0x0UL) /*!< Disable SPIM */ +#define SPIM_ENABLE_ENABLE_Enabled (0x7UL) /*!< Enable SPIM */ /* Register: SPIM_PSEL_SCK */ /* Description: Pin select for SCK */ @@ -7205,8 +7205,8 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 31 : Connection */ #define SPIM_PSEL_SCK_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ #define SPIM_PSEL_SCK_CONNECT_Msk (0x1UL << SPIM_PSEL_SCK_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ -#define SPIM_PSEL_SCK_CONNECT_Connected (0UL) /*!< Connect */ -#define SPIM_PSEL_SCK_CONNECT_Disconnected (1UL) /*!< Disconnect */ +#define SPIM_PSEL_SCK_CONNECT_Connected (0x0UL) /*!< Connect */ +#define SPIM_PSEL_SCK_CONNECT_Disconnected (0x1UL) /*!< Disconnect */ /* Bits 4..0 : Pin number */ #define SPIM_PSEL_SCK_PIN_Pos (0UL) /*!< Position of PIN field. */ @@ -7218,8 +7218,8 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 31 : Connection */ #define SPIM_PSEL_MOSI_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ #define SPIM_PSEL_MOSI_CONNECT_Msk (0x1UL << SPIM_PSEL_MOSI_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ -#define SPIM_PSEL_MOSI_CONNECT_Connected (0UL) /*!< Connect */ -#define SPIM_PSEL_MOSI_CONNECT_Disconnected (1UL) /*!< Disconnect */ +#define SPIM_PSEL_MOSI_CONNECT_Connected (0x0UL) /*!< Connect */ +#define SPIM_PSEL_MOSI_CONNECT_Disconnected (0x1UL) /*!< Disconnect */ /* Bits 4..0 : Pin number */ #define SPIM_PSEL_MOSI_PIN_Pos (0UL) /*!< Position of PIN field. */ @@ -7231,8 +7231,8 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 31 : Connection */ #define SPIM_PSEL_MISO_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ #define SPIM_PSEL_MISO_CONNECT_Msk (0x1UL << SPIM_PSEL_MISO_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ -#define SPIM_PSEL_MISO_CONNECT_Connected (0UL) /*!< Connect */ -#define SPIM_PSEL_MISO_CONNECT_Disconnected (1UL) /*!< Disconnect */ +#define SPIM_PSEL_MISO_CONNECT_Connected (0x0UL) /*!< Connect */ +#define SPIM_PSEL_MISO_CONNECT_Disconnected (0x1UL) /*!< Disconnect */ /* Bits 4..0 : Pin number */ #define SPIM_PSEL_MISO_PIN_Pos (0UL) /*!< Position of PIN field. */ @@ -7279,8 +7279,8 @@ POSSIBILITY OF SUCH DAMAGE. /* Bits 1..0 : List type */ #define SPIM_RXD_LIST_LIST_Pos (0UL) /*!< Position of LIST field. */ #define SPIM_RXD_LIST_LIST_Msk (0x3UL << SPIM_RXD_LIST_LIST_Pos) /*!< Bit mask of LIST field. */ -#define SPIM_RXD_LIST_LIST_Disabled (0UL) /*!< Disable EasyDMA list */ -#define SPIM_RXD_LIST_LIST_ArrayList (1UL) /*!< Use array list */ +#define SPIM_RXD_LIST_LIST_Disabled (0x0UL) /*!< Disable EasyDMA list */ +#define SPIM_RXD_LIST_LIST_ArrayList (0x1UL) /*!< Use array list */ /* Register: SPIM_TXD_PTR */ /* Description: Data pointer */ @@ -7309,8 +7309,8 @@ POSSIBILITY OF SUCH DAMAGE. /* Bits 1..0 : List type */ #define SPIM_TXD_LIST_LIST_Pos (0UL) /*!< Position of LIST field. */ #define SPIM_TXD_LIST_LIST_Msk (0x3UL << SPIM_TXD_LIST_LIST_Pos) /*!< Bit mask of LIST field. */ -#define SPIM_TXD_LIST_LIST_Disabled (0UL) /*!< Disable EasyDMA list */ -#define SPIM_TXD_LIST_LIST_ArrayList (1UL) /*!< Use array list */ +#define SPIM_TXD_LIST_LIST_Disabled (0x0UL) /*!< Disable EasyDMA list */ +#define SPIM_TXD_LIST_LIST_ArrayList (0x1UL) /*!< Use array list */ /* Register: SPIM_CONFIG */ /* Description: Configuration register */ @@ -7318,20 +7318,20 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 2 : Serial clock (SCK) polarity */ #define SPIM_CONFIG_CPOL_Pos (2UL) /*!< Position of CPOL field. */ #define SPIM_CONFIG_CPOL_Msk (0x1UL << SPIM_CONFIG_CPOL_Pos) /*!< Bit mask of CPOL field. */ -#define SPIM_CONFIG_CPOL_ActiveHigh (0UL) /*!< Active high */ -#define SPIM_CONFIG_CPOL_ActiveLow (1UL) /*!< Active low */ +#define SPIM_CONFIG_CPOL_ActiveHigh (0x0UL) /*!< Active high */ +#define SPIM_CONFIG_CPOL_ActiveLow (0x1UL) /*!< Active low */ /* Bit 1 : Serial clock (SCK) phase */ #define SPIM_CONFIG_CPHA_Pos (1UL) /*!< Position of CPHA field. */ #define SPIM_CONFIG_CPHA_Msk (0x1UL << SPIM_CONFIG_CPHA_Pos) /*!< Bit mask of CPHA field. */ -#define SPIM_CONFIG_CPHA_Leading (0UL) /*!< Sample on leading edge of clock, shift serial data on trailing edge */ -#define SPIM_CONFIG_CPHA_Trailing (1UL) /*!< Sample on trailing edge of clock, shift serial data on leading edge */ +#define SPIM_CONFIG_CPHA_Leading (0x0UL) /*!< Sample on leading edge of clock, shift serial data on trailing edge */ +#define SPIM_CONFIG_CPHA_Trailing (0x1UL) /*!< Sample on trailing edge of clock, shift serial data on leading edge */ /* Bit 0 : Bit order */ #define SPIM_CONFIG_ORDER_Pos (0UL) /*!< Position of ORDER field. */ #define SPIM_CONFIG_ORDER_Msk (0x1UL << SPIM_CONFIG_ORDER_Pos) /*!< Bit mask of ORDER field. */ -#define SPIM_CONFIG_ORDER_MsbFirst (0UL) /*!< Most significant bit shifted out first */ -#define SPIM_CONFIG_ORDER_LsbFirst (1UL) /*!< Least significant bit shifted out first */ +#define SPIM_CONFIG_ORDER_MsbFirst (0x0UL) /*!< Most significant bit shifted out first */ +#define SPIM_CONFIG_ORDER_LsbFirst (0x1UL) /*!< Least significant bit shifted out first */ /* Register: SPIM_ORC */ /* Description: Over-read character. Character clocked out in case an over-read of the TXD buffer. */ @@ -7350,7 +7350,7 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 0 : Acquire SPI semaphore */ #define SPIS_TASKS_ACQUIRE_TASKS_ACQUIRE_Pos (0UL) /*!< Position of TASKS_ACQUIRE field. */ #define SPIS_TASKS_ACQUIRE_TASKS_ACQUIRE_Msk (0x1UL << SPIS_TASKS_ACQUIRE_TASKS_ACQUIRE_Pos) /*!< Bit mask of TASKS_ACQUIRE field. */ -#define SPIS_TASKS_ACQUIRE_TASKS_ACQUIRE_Trigger (1UL) /*!< Trigger task */ +#define SPIS_TASKS_ACQUIRE_TASKS_ACQUIRE_Trigger (0x1UL) /*!< Trigger task */ /* Register: SPIS_TASKS_RELEASE */ /* Description: Release SPI semaphore, enabling the SPI slave to acquire it */ @@ -7358,7 +7358,7 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 0 : Release SPI semaphore, enabling the SPI slave to acquire it */ #define SPIS_TASKS_RELEASE_TASKS_RELEASE_Pos (0UL) /*!< Position of TASKS_RELEASE field. */ #define SPIS_TASKS_RELEASE_TASKS_RELEASE_Msk (0x1UL << SPIS_TASKS_RELEASE_TASKS_RELEASE_Pos) /*!< Bit mask of TASKS_RELEASE field. */ -#define SPIS_TASKS_RELEASE_TASKS_RELEASE_Trigger (1UL) /*!< Trigger task */ +#define SPIS_TASKS_RELEASE_TASKS_RELEASE_Trigger (0x1UL) /*!< Trigger task */ /* Register: SPIS_SUBSCRIBE_ACQUIRE */ /* Description: Subscribe configuration for task ACQUIRE */ @@ -7366,8 +7366,8 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 31 : */ #define SPIS_SUBSCRIBE_ACQUIRE_EN_Pos (31UL) /*!< Position of EN field. */ #define SPIS_SUBSCRIBE_ACQUIRE_EN_Msk (0x1UL << SPIS_SUBSCRIBE_ACQUIRE_EN_Pos) /*!< Bit mask of EN field. */ -#define SPIS_SUBSCRIBE_ACQUIRE_EN_Disabled (0UL) /*!< Disable subscription */ -#define SPIS_SUBSCRIBE_ACQUIRE_EN_Enabled (1UL) /*!< Enable subscription */ +#define SPIS_SUBSCRIBE_ACQUIRE_EN_Disabled (0x0UL) /*!< Disable subscription */ +#define SPIS_SUBSCRIBE_ACQUIRE_EN_Enabled (0x1UL) /*!< Enable subscription */ /* Bits 7..0 : DPPI channel that task ACQUIRE will subscribe to */ #define SPIS_SUBSCRIBE_ACQUIRE_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ @@ -7379,8 +7379,8 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 31 : */ #define SPIS_SUBSCRIBE_RELEASE_EN_Pos (31UL) /*!< Position of EN field. */ #define SPIS_SUBSCRIBE_RELEASE_EN_Msk (0x1UL << SPIS_SUBSCRIBE_RELEASE_EN_Pos) /*!< Bit mask of EN field. */ -#define SPIS_SUBSCRIBE_RELEASE_EN_Disabled (0UL) /*!< Disable subscription */ -#define SPIS_SUBSCRIBE_RELEASE_EN_Enabled (1UL) /*!< Enable subscription */ +#define SPIS_SUBSCRIBE_RELEASE_EN_Disabled (0x0UL) /*!< Disable subscription */ +#define SPIS_SUBSCRIBE_RELEASE_EN_Enabled (0x1UL) /*!< Enable subscription */ /* Bits 7..0 : DPPI channel that task RELEASE will subscribe to */ #define SPIS_SUBSCRIBE_RELEASE_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ @@ -7392,8 +7392,8 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 0 : Granted transaction completed */ #define SPIS_EVENTS_END_EVENTS_END_Pos (0UL) /*!< Position of EVENTS_END field. */ #define SPIS_EVENTS_END_EVENTS_END_Msk (0x1UL << SPIS_EVENTS_END_EVENTS_END_Pos) /*!< Bit mask of EVENTS_END field. */ -#define SPIS_EVENTS_END_EVENTS_END_NotGenerated (0UL) /*!< Event not generated */ -#define SPIS_EVENTS_END_EVENTS_END_Generated (1UL) /*!< Event generated */ +#define SPIS_EVENTS_END_EVENTS_END_NotGenerated (0x0UL) /*!< Event not generated */ +#define SPIS_EVENTS_END_EVENTS_END_Generated (0x1UL) /*!< Event generated */ /* Register: SPIS_EVENTS_ENDRX */ /* Description: End of RXD buffer reached */ @@ -7401,8 +7401,8 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 0 : End of RXD buffer reached */ #define SPIS_EVENTS_ENDRX_EVENTS_ENDRX_Pos (0UL) /*!< Position of EVENTS_ENDRX field. */ #define SPIS_EVENTS_ENDRX_EVENTS_ENDRX_Msk (0x1UL << SPIS_EVENTS_ENDRX_EVENTS_ENDRX_Pos) /*!< Bit mask of EVENTS_ENDRX field. */ -#define SPIS_EVENTS_ENDRX_EVENTS_ENDRX_NotGenerated (0UL) /*!< Event not generated */ -#define SPIS_EVENTS_ENDRX_EVENTS_ENDRX_Generated (1UL) /*!< Event generated */ +#define SPIS_EVENTS_ENDRX_EVENTS_ENDRX_NotGenerated (0x0UL) /*!< Event not generated */ +#define SPIS_EVENTS_ENDRX_EVENTS_ENDRX_Generated (0x1UL) /*!< Event generated */ /* Register: SPIS_EVENTS_ACQUIRED */ /* Description: Semaphore acquired */ @@ -7410,8 +7410,8 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 0 : Semaphore acquired */ #define SPIS_EVENTS_ACQUIRED_EVENTS_ACQUIRED_Pos (0UL) /*!< Position of EVENTS_ACQUIRED field. */ #define SPIS_EVENTS_ACQUIRED_EVENTS_ACQUIRED_Msk (0x1UL << SPIS_EVENTS_ACQUIRED_EVENTS_ACQUIRED_Pos) /*!< Bit mask of EVENTS_ACQUIRED field. */ -#define SPIS_EVENTS_ACQUIRED_EVENTS_ACQUIRED_NotGenerated (0UL) /*!< Event not generated */ -#define SPIS_EVENTS_ACQUIRED_EVENTS_ACQUIRED_Generated (1UL) /*!< Event generated */ +#define SPIS_EVENTS_ACQUIRED_EVENTS_ACQUIRED_NotGenerated (0x0UL) /*!< Event not generated */ +#define SPIS_EVENTS_ACQUIRED_EVENTS_ACQUIRED_Generated (0x1UL) /*!< Event generated */ /* Register: SPIS_PUBLISH_END */ /* Description: Publish configuration for event END */ @@ -7419,8 +7419,8 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 31 : */ #define SPIS_PUBLISH_END_EN_Pos (31UL) /*!< Position of EN field. */ #define SPIS_PUBLISH_END_EN_Msk (0x1UL << SPIS_PUBLISH_END_EN_Pos) /*!< Bit mask of EN field. */ -#define SPIS_PUBLISH_END_EN_Disabled (0UL) /*!< Disable publishing */ -#define SPIS_PUBLISH_END_EN_Enabled (1UL) /*!< Enable publishing */ +#define SPIS_PUBLISH_END_EN_Disabled (0x0UL) /*!< Disable publishing */ +#define SPIS_PUBLISH_END_EN_Enabled (0x1UL) /*!< Enable publishing */ /* Bits 7..0 : DPPI channel that event END will publish to */ #define SPIS_PUBLISH_END_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ @@ -7432,8 +7432,8 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 31 : */ #define SPIS_PUBLISH_ENDRX_EN_Pos (31UL) /*!< Position of EN field. */ #define SPIS_PUBLISH_ENDRX_EN_Msk (0x1UL << SPIS_PUBLISH_ENDRX_EN_Pos) /*!< Bit mask of EN field. */ -#define SPIS_PUBLISH_ENDRX_EN_Disabled (0UL) /*!< Disable publishing */ -#define SPIS_PUBLISH_ENDRX_EN_Enabled (1UL) /*!< Enable publishing */ +#define SPIS_PUBLISH_ENDRX_EN_Disabled (0x0UL) /*!< Disable publishing */ +#define SPIS_PUBLISH_ENDRX_EN_Enabled (0x1UL) /*!< Enable publishing */ /* Bits 7..0 : DPPI channel that event ENDRX will publish to */ #define SPIS_PUBLISH_ENDRX_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ @@ -7445,8 +7445,8 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 31 : */ #define SPIS_PUBLISH_ACQUIRED_EN_Pos (31UL) /*!< Position of EN field. */ #define SPIS_PUBLISH_ACQUIRED_EN_Msk (0x1UL << SPIS_PUBLISH_ACQUIRED_EN_Pos) /*!< Bit mask of EN field. */ -#define SPIS_PUBLISH_ACQUIRED_EN_Disabled (0UL) /*!< Disable publishing */ -#define SPIS_PUBLISH_ACQUIRED_EN_Enabled (1UL) /*!< Enable publishing */ +#define SPIS_PUBLISH_ACQUIRED_EN_Disabled (0x0UL) /*!< Disable publishing */ +#define SPIS_PUBLISH_ACQUIRED_EN_Enabled (0x1UL) /*!< Enable publishing */ /* Bits 7..0 : DPPI channel that event ACQUIRED will publish to */ #define SPIS_PUBLISH_ACQUIRED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ @@ -7458,8 +7458,8 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 2 : Shortcut between event END and task ACQUIRE */ #define SPIS_SHORTS_END_ACQUIRE_Pos (2UL) /*!< Position of END_ACQUIRE field. */ #define SPIS_SHORTS_END_ACQUIRE_Msk (0x1UL << SPIS_SHORTS_END_ACQUIRE_Pos) /*!< Bit mask of END_ACQUIRE field. */ -#define SPIS_SHORTS_END_ACQUIRE_Disabled (0UL) /*!< Disable shortcut */ -#define SPIS_SHORTS_END_ACQUIRE_Enabled (1UL) /*!< Enable shortcut */ +#define SPIS_SHORTS_END_ACQUIRE_Disabled (0x0UL) /*!< Disable shortcut */ +#define SPIS_SHORTS_END_ACQUIRE_Enabled (0x1UL) /*!< Enable shortcut */ /* Register: SPIS_INTENSET */ /* Description: Enable interrupt */ @@ -7467,23 +7467,23 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 10 : Write '1' to enable interrupt for event ACQUIRED */ #define SPIS_INTENSET_ACQUIRED_Pos (10UL) /*!< Position of ACQUIRED field. */ #define SPIS_INTENSET_ACQUIRED_Msk (0x1UL << SPIS_INTENSET_ACQUIRED_Pos) /*!< Bit mask of ACQUIRED field. */ -#define SPIS_INTENSET_ACQUIRED_Disabled (0UL) /*!< Read: Disabled */ -#define SPIS_INTENSET_ACQUIRED_Enabled (1UL) /*!< Read: Enabled */ -#define SPIS_INTENSET_ACQUIRED_Set (1UL) /*!< Enable */ +#define SPIS_INTENSET_ACQUIRED_Disabled (0x0UL) /*!< Read: Disabled */ +#define SPIS_INTENSET_ACQUIRED_Enabled (0x1UL) /*!< Read: Enabled */ +#define SPIS_INTENSET_ACQUIRED_Set (0x1UL) /*!< Enable */ /* Bit 4 : Write '1' to enable interrupt for event ENDRX */ #define SPIS_INTENSET_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */ #define SPIS_INTENSET_ENDRX_Msk (0x1UL << SPIS_INTENSET_ENDRX_Pos) /*!< Bit mask of ENDRX field. */ -#define SPIS_INTENSET_ENDRX_Disabled (0UL) /*!< Read: Disabled */ -#define SPIS_INTENSET_ENDRX_Enabled (1UL) /*!< Read: Enabled */ -#define SPIS_INTENSET_ENDRX_Set (1UL) /*!< Enable */ +#define SPIS_INTENSET_ENDRX_Disabled (0x0UL) /*!< Read: Disabled */ +#define SPIS_INTENSET_ENDRX_Enabled (0x1UL) /*!< Read: Enabled */ +#define SPIS_INTENSET_ENDRX_Set (0x1UL) /*!< Enable */ /* Bit 1 : Write '1' to enable interrupt for event END */ #define SPIS_INTENSET_END_Pos (1UL) /*!< Position of END field. */ #define SPIS_INTENSET_END_Msk (0x1UL << SPIS_INTENSET_END_Pos) /*!< Bit mask of END field. */ -#define SPIS_INTENSET_END_Disabled (0UL) /*!< Read: Disabled */ -#define SPIS_INTENSET_END_Enabled (1UL) /*!< Read: Enabled */ -#define SPIS_INTENSET_END_Set (1UL) /*!< Enable */ +#define SPIS_INTENSET_END_Disabled (0x0UL) /*!< Read: Disabled */ +#define SPIS_INTENSET_END_Enabled (0x1UL) /*!< Read: Enabled */ +#define SPIS_INTENSET_END_Set (0x1UL) /*!< Enable */ /* Register: SPIS_INTENCLR */ /* Description: Disable interrupt */ @@ -7491,23 +7491,23 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 10 : Write '1' to disable interrupt for event ACQUIRED */ #define SPIS_INTENCLR_ACQUIRED_Pos (10UL) /*!< Position of ACQUIRED field. */ #define SPIS_INTENCLR_ACQUIRED_Msk (0x1UL << SPIS_INTENCLR_ACQUIRED_Pos) /*!< Bit mask of ACQUIRED field. */ -#define SPIS_INTENCLR_ACQUIRED_Disabled (0UL) /*!< Read: Disabled */ -#define SPIS_INTENCLR_ACQUIRED_Enabled (1UL) /*!< Read: Enabled */ -#define SPIS_INTENCLR_ACQUIRED_Clear (1UL) /*!< Disable */ +#define SPIS_INTENCLR_ACQUIRED_Disabled (0x0UL) /*!< Read: Disabled */ +#define SPIS_INTENCLR_ACQUIRED_Enabled (0x1UL) /*!< Read: Enabled */ +#define SPIS_INTENCLR_ACQUIRED_Clear (0x1UL) /*!< Disable */ /* Bit 4 : Write '1' to disable interrupt for event ENDRX */ #define SPIS_INTENCLR_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */ #define SPIS_INTENCLR_ENDRX_Msk (0x1UL << SPIS_INTENCLR_ENDRX_Pos) /*!< Bit mask of ENDRX field. */ -#define SPIS_INTENCLR_ENDRX_Disabled (0UL) /*!< Read: Disabled */ -#define SPIS_INTENCLR_ENDRX_Enabled (1UL) /*!< Read: Enabled */ -#define SPIS_INTENCLR_ENDRX_Clear (1UL) /*!< Disable */ +#define SPIS_INTENCLR_ENDRX_Disabled (0x0UL) /*!< Read: Disabled */ +#define SPIS_INTENCLR_ENDRX_Enabled (0x1UL) /*!< Read: Enabled */ +#define SPIS_INTENCLR_ENDRX_Clear (0x1UL) /*!< Disable */ /* Bit 1 : Write '1' to disable interrupt for event END */ #define SPIS_INTENCLR_END_Pos (1UL) /*!< Position of END field. */ #define SPIS_INTENCLR_END_Msk (0x1UL << SPIS_INTENCLR_END_Pos) /*!< Bit mask of END field. */ -#define SPIS_INTENCLR_END_Disabled (0UL) /*!< Read: Disabled */ -#define SPIS_INTENCLR_END_Enabled (1UL) /*!< Read: Enabled */ -#define SPIS_INTENCLR_END_Clear (1UL) /*!< Disable */ +#define SPIS_INTENCLR_END_Disabled (0x0UL) /*!< Read: Disabled */ +#define SPIS_INTENCLR_END_Enabled (0x1UL) /*!< Read: Enabled */ +#define SPIS_INTENCLR_END_Clear (0x1UL) /*!< Disable */ /* Register: SPIS_SEMSTAT */ /* Description: Semaphore status register */ @@ -7515,10 +7515,10 @@ POSSIBILITY OF SUCH DAMAGE. /* Bits 1..0 : Semaphore status */ #define SPIS_SEMSTAT_SEMSTAT_Pos (0UL) /*!< Position of SEMSTAT field. */ #define SPIS_SEMSTAT_SEMSTAT_Msk (0x3UL << SPIS_SEMSTAT_SEMSTAT_Pos) /*!< Bit mask of SEMSTAT field. */ -#define SPIS_SEMSTAT_SEMSTAT_Free (0UL) /*!< Semaphore is free */ -#define SPIS_SEMSTAT_SEMSTAT_CPU (1UL) /*!< Semaphore is assigned to CPU */ -#define SPIS_SEMSTAT_SEMSTAT_SPIS (2UL) /*!< Semaphore is assigned to SPI slave */ -#define SPIS_SEMSTAT_SEMSTAT_CPUPending (3UL) /*!< Semaphore is assigned to SPI but a handover to the CPU is pending */ +#define SPIS_SEMSTAT_SEMSTAT_Free (0x0UL) /*!< Semaphore is free */ +#define SPIS_SEMSTAT_SEMSTAT_CPU (0x1UL) /*!< Semaphore is assigned to CPU */ +#define SPIS_SEMSTAT_SEMSTAT_SPIS (0x2UL) /*!< Semaphore is assigned to SPI slave */ +#define SPIS_SEMSTAT_SEMSTAT_CPUPending (0x3UL) /*!< Semaphore is assigned to SPI but a handover to the CPU is pending */ /* Register: SPIS_STATUS */ /* Description: Status from last transaction */ @@ -7526,16 +7526,16 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 1 : RX buffer overflow detected, and prevented */ #define SPIS_STATUS_OVERFLOW_Pos (1UL) /*!< Position of OVERFLOW field. */ #define SPIS_STATUS_OVERFLOW_Msk (0x1UL << SPIS_STATUS_OVERFLOW_Pos) /*!< Bit mask of OVERFLOW field. */ -#define SPIS_STATUS_OVERFLOW_NotPresent (0UL) /*!< Read: error not present */ -#define SPIS_STATUS_OVERFLOW_Present (1UL) /*!< Read: error present */ -#define SPIS_STATUS_OVERFLOW_Clear (1UL) /*!< Write: clear error on writing '1' */ +#define SPIS_STATUS_OVERFLOW_NotPresent (0x0UL) /*!< Read: error not present */ +#define SPIS_STATUS_OVERFLOW_Present (0x1UL) /*!< Read: error present */ +#define SPIS_STATUS_OVERFLOW_Clear (0x1UL) /*!< Write: clear error on writing '1' */ /* Bit 0 : TX buffer over-read detected, and prevented */ #define SPIS_STATUS_OVERREAD_Pos (0UL) /*!< Position of OVERREAD field. */ #define SPIS_STATUS_OVERREAD_Msk (0x1UL << SPIS_STATUS_OVERREAD_Pos) /*!< Bit mask of OVERREAD field. */ -#define SPIS_STATUS_OVERREAD_NotPresent (0UL) /*!< Read: error not present */ -#define SPIS_STATUS_OVERREAD_Present (1UL) /*!< Read: error present */ -#define SPIS_STATUS_OVERREAD_Clear (1UL) /*!< Write: clear error on writing '1' */ +#define SPIS_STATUS_OVERREAD_NotPresent (0x0UL) /*!< Read: error not present */ +#define SPIS_STATUS_OVERREAD_Present (0x1UL) /*!< Read: error present */ +#define SPIS_STATUS_OVERREAD_Clear (0x1UL) /*!< Write: clear error on writing '1' */ /* Register: SPIS_ENABLE */ /* Description: Enable SPI slave */ @@ -7543,8 +7543,8 @@ POSSIBILITY OF SUCH DAMAGE. /* Bits 3..0 : Enable or disable SPI slave */ #define SPIS_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ #define SPIS_ENABLE_ENABLE_Msk (0xFUL << SPIS_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ -#define SPIS_ENABLE_ENABLE_Disabled (0UL) /*!< Disable SPI slave */ -#define SPIS_ENABLE_ENABLE_Enabled (2UL) /*!< Enable SPI slave */ +#define SPIS_ENABLE_ENABLE_Disabled (0x0UL) /*!< Disable SPI slave */ +#define SPIS_ENABLE_ENABLE_Enabled (0x2UL) /*!< Enable SPI slave */ /* Register: SPIS_PSEL_SCK */ /* Description: Pin select for SCK */ @@ -7552,8 +7552,8 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 31 : Connection */ #define SPIS_PSEL_SCK_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ #define SPIS_PSEL_SCK_CONNECT_Msk (0x1UL << SPIS_PSEL_SCK_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ -#define SPIS_PSEL_SCK_CONNECT_Connected (0UL) /*!< Connect */ -#define SPIS_PSEL_SCK_CONNECT_Disconnected (1UL) /*!< Disconnect */ +#define SPIS_PSEL_SCK_CONNECT_Connected (0x0UL) /*!< Connect */ +#define SPIS_PSEL_SCK_CONNECT_Disconnected (0x1UL) /*!< Disconnect */ /* Bits 4..0 : Pin number */ #define SPIS_PSEL_SCK_PIN_Pos (0UL) /*!< Position of PIN field. */ @@ -7565,8 +7565,8 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 31 : Connection */ #define SPIS_PSEL_MISO_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ #define SPIS_PSEL_MISO_CONNECT_Msk (0x1UL << SPIS_PSEL_MISO_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ -#define SPIS_PSEL_MISO_CONNECT_Connected (0UL) /*!< Connect */ -#define SPIS_PSEL_MISO_CONNECT_Disconnected (1UL) /*!< Disconnect */ +#define SPIS_PSEL_MISO_CONNECT_Connected (0x0UL) /*!< Connect */ +#define SPIS_PSEL_MISO_CONNECT_Disconnected (0x1UL) /*!< Disconnect */ /* Bits 4..0 : Pin number */ #define SPIS_PSEL_MISO_PIN_Pos (0UL) /*!< Position of PIN field. */ @@ -7578,8 +7578,8 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 31 : Connection */ #define SPIS_PSEL_MOSI_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ #define SPIS_PSEL_MOSI_CONNECT_Msk (0x1UL << SPIS_PSEL_MOSI_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ -#define SPIS_PSEL_MOSI_CONNECT_Connected (0UL) /*!< Connect */ -#define SPIS_PSEL_MOSI_CONNECT_Disconnected (1UL) /*!< Disconnect */ +#define SPIS_PSEL_MOSI_CONNECT_Connected (0x0UL) /*!< Connect */ +#define SPIS_PSEL_MOSI_CONNECT_Disconnected (0x1UL) /*!< Disconnect */ /* Bits 4..0 : Pin number */ #define SPIS_PSEL_MOSI_PIN_Pos (0UL) /*!< Position of PIN field. */ @@ -7591,8 +7591,8 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 31 : Connection */ #define SPIS_PSEL_CSN_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ #define SPIS_PSEL_CSN_CONNECT_Msk (0x1UL << SPIS_PSEL_CSN_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ -#define SPIS_PSEL_CSN_CONNECT_Connected (0UL) /*!< Connect */ -#define SPIS_PSEL_CSN_CONNECT_Disconnected (1UL) /*!< Disconnect */ +#define SPIS_PSEL_CSN_CONNECT_Connected (0x0UL) /*!< Connect */ +#define SPIS_PSEL_CSN_CONNECT_Disconnected (0x1UL) /*!< Disconnect */ /* Bits 4..0 : Pin number */ #define SPIS_PSEL_CSN_PIN_Pos (0UL) /*!< Position of PIN field. */ @@ -7625,8 +7625,8 @@ POSSIBILITY OF SUCH DAMAGE. /* Bits 1..0 : List type */ #define SPIS_RXD_LIST_LIST_Pos (0UL) /*!< Position of LIST field. */ #define SPIS_RXD_LIST_LIST_Msk (0x3UL << SPIS_RXD_LIST_LIST_Pos) /*!< Bit mask of LIST field. */ -#define SPIS_RXD_LIST_LIST_Disabled (0UL) /*!< Disable EasyDMA list */ -#define SPIS_RXD_LIST_LIST_ArrayList (1UL) /*!< Use array list */ +#define SPIS_RXD_LIST_LIST_Disabled (0x0UL) /*!< Disable EasyDMA list */ +#define SPIS_RXD_LIST_LIST_ArrayList (0x1UL) /*!< Use array list */ /* Register: SPIS_TXD_PTR */ /* Description: TXD data pointer */ @@ -7655,8 +7655,8 @@ POSSIBILITY OF SUCH DAMAGE. /* Bits 1..0 : List type */ #define SPIS_TXD_LIST_LIST_Pos (0UL) /*!< Position of LIST field. */ #define SPIS_TXD_LIST_LIST_Msk (0x3UL << SPIS_TXD_LIST_LIST_Pos) /*!< Bit mask of LIST field. */ -#define SPIS_TXD_LIST_LIST_Disabled (0UL) /*!< Disable EasyDMA list */ -#define SPIS_TXD_LIST_LIST_ArrayList (1UL) /*!< Use array list */ +#define SPIS_TXD_LIST_LIST_Disabled (0x0UL) /*!< Disable EasyDMA list */ +#define SPIS_TXD_LIST_LIST_ArrayList (0x1UL) /*!< Use array list */ /* Register: SPIS_CONFIG */ /* Description: Configuration register */ @@ -7664,20 +7664,20 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 2 : Serial clock (SCK) polarity */ #define SPIS_CONFIG_CPOL_Pos (2UL) /*!< Position of CPOL field. */ #define SPIS_CONFIG_CPOL_Msk (0x1UL << SPIS_CONFIG_CPOL_Pos) /*!< Bit mask of CPOL field. */ -#define SPIS_CONFIG_CPOL_ActiveHigh (0UL) /*!< Active high */ -#define SPIS_CONFIG_CPOL_ActiveLow (1UL) /*!< Active low */ +#define SPIS_CONFIG_CPOL_ActiveHigh (0x0UL) /*!< Active high */ +#define SPIS_CONFIG_CPOL_ActiveLow (0x1UL) /*!< Active low */ /* Bit 1 : Serial clock (SCK) phase */ #define SPIS_CONFIG_CPHA_Pos (1UL) /*!< Position of CPHA field. */ #define SPIS_CONFIG_CPHA_Msk (0x1UL << SPIS_CONFIG_CPHA_Pos) /*!< Bit mask of CPHA field. */ -#define SPIS_CONFIG_CPHA_Leading (0UL) /*!< Sample on leading edge of clock, shift serial data on trailing edge */ -#define SPIS_CONFIG_CPHA_Trailing (1UL) /*!< Sample on trailing edge of clock, shift serial data on leading edge */ +#define SPIS_CONFIG_CPHA_Leading (0x0UL) /*!< Sample on leading edge of clock, shift serial data on trailing edge */ +#define SPIS_CONFIG_CPHA_Trailing (0x1UL) /*!< Sample on trailing edge of clock, shift serial data on leading edge */ /* Bit 0 : Bit order */ #define SPIS_CONFIG_ORDER_Pos (0UL) /*!< Position of ORDER field. */ #define SPIS_CONFIG_ORDER_Msk (0x1UL << SPIS_CONFIG_ORDER_Pos) /*!< Bit mask of ORDER field. */ -#define SPIS_CONFIG_ORDER_MsbFirst (0UL) /*!< Most significant bit shifted out first */ -#define SPIS_CONFIG_ORDER_LsbFirst (1UL) /*!< Least significant bit shifted out first */ +#define SPIS_CONFIG_ORDER_MsbFirst (0x0UL) /*!< Most significant bit shifted out first */ +#define SPIS_CONFIG_ORDER_LsbFirst (0x1UL) /*!< Least significant bit shifted out first */ /* Register: SPIS_DEF */ /* Description: Default character. Character clocked out in case of an ignored transaction. */ @@ -7703,8 +7703,8 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 0 : A security violation has been detected for the RAM memory space */ #define SPU_EVENTS_RAMACCERR_EVENTS_RAMACCERR_Pos (0UL) /*!< Position of EVENTS_RAMACCERR field. */ #define SPU_EVENTS_RAMACCERR_EVENTS_RAMACCERR_Msk (0x1UL << SPU_EVENTS_RAMACCERR_EVENTS_RAMACCERR_Pos) /*!< Bit mask of EVENTS_RAMACCERR field. */ -#define SPU_EVENTS_RAMACCERR_EVENTS_RAMACCERR_NotGenerated (0UL) /*!< Event not generated */ -#define SPU_EVENTS_RAMACCERR_EVENTS_RAMACCERR_Generated (1UL) /*!< Event generated */ +#define SPU_EVENTS_RAMACCERR_EVENTS_RAMACCERR_NotGenerated (0x0UL) /*!< Event not generated */ +#define SPU_EVENTS_RAMACCERR_EVENTS_RAMACCERR_Generated (0x1UL) /*!< Event generated */ /* Register: SPU_EVENTS_FLASHACCERR */ /* Description: A security violation has been detected for the flash memory space */ @@ -7712,8 +7712,8 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 0 : A security violation has been detected for the flash memory space */ #define SPU_EVENTS_FLASHACCERR_EVENTS_FLASHACCERR_Pos (0UL) /*!< Position of EVENTS_FLASHACCERR field. */ #define SPU_EVENTS_FLASHACCERR_EVENTS_FLASHACCERR_Msk (0x1UL << SPU_EVENTS_FLASHACCERR_EVENTS_FLASHACCERR_Pos) /*!< Bit mask of EVENTS_FLASHACCERR field. */ -#define SPU_EVENTS_FLASHACCERR_EVENTS_FLASHACCERR_NotGenerated (0UL) /*!< Event not generated */ -#define SPU_EVENTS_FLASHACCERR_EVENTS_FLASHACCERR_Generated (1UL) /*!< Event generated */ +#define SPU_EVENTS_FLASHACCERR_EVENTS_FLASHACCERR_NotGenerated (0x0UL) /*!< Event not generated */ +#define SPU_EVENTS_FLASHACCERR_EVENTS_FLASHACCERR_Generated (0x1UL) /*!< Event generated */ /* Register: SPU_EVENTS_PERIPHACCERR */ /* Description: A security violation has been detected on one or several peripherals */ @@ -7721,8 +7721,8 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 0 : A security violation has been detected on one or several peripherals */ #define SPU_EVENTS_PERIPHACCERR_EVENTS_PERIPHACCERR_Pos (0UL) /*!< Position of EVENTS_PERIPHACCERR field. */ #define SPU_EVENTS_PERIPHACCERR_EVENTS_PERIPHACCERR_Msk (0x1UL << SPU_EVENTS_PERIPHACCERR_EVENTS_PERIPHACCERR_Pos) /*!< Bit mask of EVENTS_PERIPHACCERR field. */ -#define SPU_EVENTS_PERIPHACCERR_EVENTS_PERIPHACCERR_NotGenerated (0UL) /*!< Event not generated */ -#define SPU_EVENTS_PERIPHACCERR_EVENTS_PERIPHACCERR_Generated (1UL) /*!< Event generated */ +#define SPU_EVENTS_PERIPHACCERR_EVENTS_PERIPHACCERR_NotGenerated (0x0UL) /*!< Event not generated */ +#define SPU_EVENTS_PERIPHACCERR_EVENTS_PERIPHACCERR_Generated (0x1UL) /*!< Event generated */ /* Register: SPU_PUBLISH_RAMACCERR */ /* Description: Publish configuration for event RAMACCERR */ @@ -7730,8 +7730,8 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 31 : */ #define SPU_PUBLISH_RAMACCERR_EN_Pos (31UL) /*!< Position of EN field. */ #define SPU_PUBLISH_RAMACCERR_EN_Msk (0x1UL << SPU_PUBLISH_RAMACCERR_EN_Pos) /*!< Bit mask of EN field. */ -#define SPU_PUBLISH_RAMACCERR_EN_Disabled (0UL) /*!< Disable publishing */ -#define SPU_PUBLISH_RAMACCERR_EN_Enabled (1UL) /*!< Enable publishing */ +#define SPU_PUBLISH_RAMACCERR_EN_Disabled (0x0UL) /*!< Disable publishing */ +#define SPU_PUBLISH_RAMACCERR_EN_Enabled (0x1UL) /*!< Enable publishing */ /* Bits 7..0 : DPPI channel that event RAMACCERR will publish to */ #define SPU_PUBLISH_RAMACCERR_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ @@ -7743,8 +7743,8 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 31 : */ #define SPU_PUBLISH_FLASHACCERR_EN_Pos (31UL) /*!< Position of EN field. */ #define SPU_PUBLISH_FLASHACCERR_EN_Msk (0x1UL << SPU_PUBLISH_FLASHACCERR_EN_Pos) /*!< Bit mask of EN field. */ -#define SPU_PUBLISH_FLASHACCERR_EN_Disabled (0UL) /*!< Disable publishing */ -#define SPU_PUBLISH_FLASHACCERR_EN_Enabled (1UL) /*!< Enable publishing */ +#define SPU_PUBLISH_FLASHACCERR_EN_Disabled (0x0UL) /*!< Disable publishing */ +#define SPU_PUBLISH_FLASHACCERR_EN_Enabled (0x1UL) /*!< Enable publishing */ /* Bits 7..0 : DPPI channel that event FLASHACCERR will publish to */ #define SPU_PUBLISH_FLASHACCERR_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ @@ -7756,8 +7756,8 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 31 : */ #define SPU_PUBLISH_PERIPHACCERR_EN_Pos (31UL) /*!< Position of EN field. */ #define SPU_PUBLISH_PERIPHACCERR_EN_Msk (0x1UL << SPU_PUBLISH_PERIPHACCERR_EN_Pos) /*!< Bit mask of EN field. */ -#define SPU_PUBLISH_PERIPHACCERR_EN_Disabled (0UL) /*!< Disable publishing */ -#define SPU_PUBLISH_PERIPHACCERR_EN_Enabled (1UL) /*!< Enable publishing */ +#define SPU_PUBLISH_PERIPHACCERR_EN_Disabled (0x0UL) /*!< Disable publishing */ +#define SPU_PUBLISH_PERIPHACCERR_EN_Enabled (0x1UL) /*!< Enable publishing */ /* Bits 7..0 : DPPI channel that event PERIPHACCERR will publish to */ #define SPU_PUBLISH_PERIPHACCERR_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ @@ -7769,20 +7769,20 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 2 : Enable or disable interrupt for event PERIPHACCERR */ #define SPU_INTEN_PERIPHACCERR_Pos (2UL) /*!< Position of PERIPHACCERR field. */ #define SPU_INTEN_PERIPHACCERR_Msk (0x1UL << SPU_INTEN_PERIPHACCERR_Pos) /*!< Bit mask of PERIPHACCERR field. */ -#define SPU_INTEN_PERIPHACCERR_Disabled (0UL) /*!< Disable */ -#define SPU_INTEN_PERIPHACCERR_Enabled (1UL) /*!< Enable */ +#define SPU_INTEN_PERIPHACCERR_Disabled (0x0UL) /*!< Disable */ +#define SPU_INTEN_PERIPHACCERR_Enabled (0x1UL) /*!< Enable */ /* Bit 1 : Enable or disable interrupt for event FLASHACCERR */ #define SPU_INTEN_FLASHACCERR_Pos (1UL) /*!< Position of FLASHACCERR field. */ #define SPU_INTEN_FLASHACCERR_Msk (0x1UL << SPU_INTEN_FLASHACCERR_Pos) /*!< Bit mask of FLASHACCERR field. */ -#define SPU_INTEN_FLASHACCERR_Disabled (0UL) /*!< Disable */ -#define SPU_INTEN_FLASHACCERR_Enabled (1UL) /*!< Enable */ +#define SPU_INTEN_FLASHACCERR_Disabled (0x0UL) /*!< Disable */ +#define SPU_INTEN_FLASHACCERR_Enabled (0x1UL) /*!< Enable */ /* Bit 0 : Enable or disable interrupt for event RAMACCERR */ #define SPU_INTEN_RAMACCERR_Pos (0UL) /*!< Position of RAMACCERR field. */ #define SPU_INTEN_RAMACCERR_Msk (0x1UL << SPU_INTEN_RAMACCERR_Pos) /*!< Bit mask of RAMACCERR field. */ -#define SPU_INTEN_RAMACCERR_Disabled (0UL) /*!< Disable */ -#define SPU_INTEN_RAMACCERR_Enabled (1UL) /*!< Enable */ +#define SPU_INTEN_RAMACCERR_Disabled (0x0UL) /*!< Disable */ +#define SPU_INTEN_RAMACCERR_Enabled (0x1UL) /*!< Enable */ /* Register: SPU_INTENSET */ /* Description: Enable interrupt */ @@ -7790,23 +7790,23 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 2 : Write '1' to enable interrupt for event PERIPHACCERR */ #define SPU_INTENSET_PERIPHACCERR_Pos (2UL) /*!< Position of PERIPHACCERR field. */ #define SPU_INTENSET_PERIPHACCERR_Msk (0x1UL << SPU_INTENSET_PERIPHACCERR_Pos) /*!< Bit mask of PERIPHACCERR field. */ -#define SPU_INTENSET_PERIPHACCERR_Disabled (0UL) /*!< Read: Disabled */ -#define SPU_INTENSET_PERIPHACCERR_Enabled (1UL) /*!< Read: Enabled */ -#define SPU_INTENSET_PERIPHACCERR_Set (1UL) /*!< Enable */ +#define SPU_INTENSET_PERIPHACCERR_Disabled (0x0UL) /*!< Read: Disabled */ +#define SPU_INTENSET_PERIPHACCERR_Enabled (0x1UL) /*!< Read: Enabled */ +#define SPU_INTENSET_PERIPHACCERR_Set (0x1UL) /*!< Enable */ /* Bit 1 : Write '1' to enable interrupt for event FLASHACCERR */ #define SPU_INTENSET_FLASHACCERR_Pos (1UL) /*!< Position of FLASHACCERR field. */ #define SPU_INTENSET_FLASHACCERR_Msk (0x1UL << SPU_INTENSET_FLASHACCERR_Pos) /*!< Bit mask of FLASHACCERR field. */ -#define SPU_INTENSET_FLASHACCERR_Disabled (0UL) /*!< Read: Disabled */ -#define SPU_INTENSET_FLASHACCERR_Enabled (1UL) /*!< Read: Enabled */ -#define SPU_INTENSET_FLASHACCERR_Set (1UL) /*!< Enable */ +#define SPU_INTENSET_FLASHACCERR_Disabled (0x0UL) /*!< Read: Disabled */ +#define SPU_INTENSET_FLASHACCERR_Enabled (0x1UL) /*!< Read: Enabled */ +#define SPU_INTENSET_FLASHACCERR_Set (0x1UL) /*!< Enable */ /* Bit 0 : Write '1' to enable interrupt for event RAMACCERR */ #define SPU_INTENSET_RAMACCERR_Pos (0UL) /*!< Position of RAMACCERR field. */ #define SPU_INTENSET_RAMACCERR_Msk (0x1UL << SPU_INTENSET_RAMACCERR_Pos) /*!< Bit mask of RAMACCERR field. */ -#define SPU_INTENSET_RAMACCERR_Disabled (0UL) /*!< Read: Disabled */ -#define SPU_INTENSET_RAMACCERR_Enabled (1UL) /*!< Read: Enabled */ -#define SPU_INTENSET_RAMACCERR_Set (1UL) /*!< Enable */ +#define SPU_INTENSET_RAMACCERR_Disabled (0x0UL) /*!< Read: Disabled */ +#define SPU_INTENSET_RAMACCERR_Enabled (0x1UL) /*!< Read: Enabled */ +#define SPU_INTENSET_RAMACCERR_Set (0x1UL) /*!< Enable */ /* Register: SPU_INTENCLR */ /* Description: Disable interrupt */ @@ -7814,23 +7814,23 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 2 : Write '1' to disable interrupt for event PERIPHACCERR */ #define SPU_INTENCLR_PERIPHACCERR_Pos (2UL) /*!< Position of PERIPHACCERR field. */ #define SPU_INTENCLR_PERIPHACCERR_Msk (0x1UL << SPU_INTENCLR_PERIPHACCERR_Pos) /*!< Bit mask of PERIPHACCERR field. */ -#define SPU_INTENCLR_PERIPHACCERR_Disabled (0UL) /*!< Read: Disabled */ -#define SPU_INTENCLR_PERIPHACCERR_Enabled (1UL) /*!< Read: Enabled */ -#define SPU_INTENCLR_PERIPHACCERR_Clear (1UL) /*!< Disable */ +#define SPU_INTENCLR_PERIPHACCERR_Disabled (0x0UL) /*!< Read: Disabled */ +#define SPU_INTENCLR_PERIPHACCERR_Enabled (0x1UL) /*!< Read: Enabled */ +#define SPU_INTENCLR_PERIPHACCERR_Clear (0x1UL) /*!< Disable */ /* Bit 1 : Write '1' to disable interrupt for event FLASHACCERR */ #define SPU_INTENCLR_FLASHACCERR_Pos (1UL) /*!< Position of FLASHACCERR field. */ #define SPU_INTENCLR_FLASHACCERR_Msk (0x1UL << SPU_INTENCLR_FLASHACCERR_Pos) /*!< Bit mask of FLASHACCERR field. */ -#define SPU_INTENCLR_FLASHACCERR_Disabled (0UL) /*!< Read: Disabled */ -#define SPU_INTENCLR_FLASHACCERR_Enabled (1UL) /*!< Read: Enabled */ -#define SPU_INTENCLR_FLASHACCERR_Clear (1UL) /*!< Disable */ +#define SPU_INTENCLR_FLASHACCERR_Disabled (0x0UL) /*!< Read: Disabled */ +#define SPU_INTENCLR_FLASHACCERR_Enabled (0x1UL) /*!< Read: Enabled */ +#define SPU_INTENCLR_FLASHACCERR_Clear (0x1UL) /*!< Disable */ /* Bit 0 : Write '1' to disable interrupt for event RAMACCERR */ #define SPU_INTENCLR_RAMACCERR_Pos (0UL) /*!< Position of RAMACCERR field. */ #define SPU_INTENCLR_RAMACCERR_Msk (0x1UL << SPU_INTENCLR_RAMACCERR_Pos) /*!< Bit mask of RAMACCERR field. */ -#define SPU_INTENCLR_RAMACCERR_Disabled (0UL) /*!< Read: Disabled */ -#define SPU_INTENCLR_RAMACCERR_Enabled (1UL) /*!< Read: Enabled */ -#define SPU_INTENCLR_RAMACCERR_Clear (1UL) /*!< Disable */ +#define SPU_INTENCLR_RAMACCERR_Disabled (0x0UL) /*!< Read: Disabled */ +#define SPU_INTENCLR_RAMACCERR_Enabled (0x1UL) /*!< Read: Enabled */ +#define SPU_INTENCLR_RAMACCERR_Clear (0x1UL) /*!< Disable */ /* Register: SPU_CAP */ /* Description: Show implemented features for the current device */ @@ -7838,8 +7838,8 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 0 : Show ARM TrustZone status */ #define SPU_CAP_TZM_Pos (0UL) /*!< Position of TZM field. */ #define SPU_CAP_TZM_Msk (0x1UL << SPU_CAP_TZM_Pos) /*!< Bit mask of TZM field. */ -#define SPU_CAP_TZM_NotAvailable (0UL) /*!< ARM TrustZone support not available */ -#define SPU_CAP_TZM_Enabled (1UL) /*!< ARM TrustZone support is available */ +#define SPU_CAP_TZM_NotAvailable (0x0UL) /*!< ARM TrustZone support not available */ +#define SPU_CAP_TZM_Enabled (0x1UL) /*!< ARM TrustZone support is available */ /* Register: SPU_EXTDOMAIN_PERM */ /* Description: Description cluster: Access for bus access generated from the external domain n List capabilities of the external domain n */ @@ -7847,21 +7847,21 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 8 : */ #define SPU_EXTDOMAIN_PERM_LOCK_Pos (8UL) /*!< Position of LOCK field. */ #define SPU_EXTDOMAIN_PERM_LOCK_Msk (0x1UL << SPU_EXTDOMAIN_PERM_LOCK_Pos) /*!< Bit mask of LOCK field. */ -#define SPU_EXTDOMAIN_PERM_LOCK_Unlocked (0UL) /*!< This register can be updated */ -#define SPU_EXTDOMAIN_PERM_LOCK_Locked (1UL) /*!< The content of this register can't be changed until the next reset */ +#define SPU_EXTDOMAIN_PERM_LOCK_Unlocked (0x0UL) /*!< This register can be updated */ +#define SPU_EXTDOMAIN_PERM_LOCK_Locked (0x1UL) /*!< The content of this register can't be changed until the next reset */ /* Bit 4 : Peripheral security mapping */ #define SPU_EXTDOMAIN_PERM_SECATTR_Pos (4UL) /*!< Position of SECATTR field. */ #define SPU_EXTDOMAIN_PERM_SECATTR_Msk (0x1UL << SPU_EXTDOMAIN_PERM_SECATTR_Pos) /*!< Bit mask of SECATTR field. */ -#define SPU_EXTDOMAIN_PERM_SECATTR_NonSecure (0UL) /*!< Bus accesses from this domain have the non-secure attribute set */ -#define SPU_EXTDOMAIN_PERM_SECATTR_Secure (1UL) /*!< Bus accesses from this domain have secure attribute set */ +#define SPU_EXTDOMAIN_PERM_SECATTR_NonSecure (0x0UL) /*!< Bus accesses from this domain have the non-secure attribute set */ +#define SPU_EXTDOMAIN_PERM_SECATTR_Secure (0x1UL) /*!< Bus accesses from this domain have secure attribute set */ /* Bits 1..0 : Define configuration capabilities for TrustZone Cortex-M secure attribute */ #define SPU_EXTDOMAIN_PERM_SECUREMAPPING_Pos (0UL) /*!< Position of SECUREMAPPING field. */ #define SPU_EXTDOMAIN_PERM_SECUREMAPPING_Msk (0x3UL << SPU_EXTDOMAIN_PERM_SECUREMAPPING_Pos) /*!< Bit mask of SECUREMAPPING field. */ -#define SPU_EXTDOMAIN_PERM_SECUREMAPPING_NonSecure (0UL) /*!< The bus access from this external domain always have the non-secure attribute set */ -#define SPU_EXTDOMAIN_PERM_SECUREMAPPING_Secure (1UL) /*!< The bus access from this external domain always have the secure attribute set */ -#define SPU_EXTDOMAIN_PERM_SECUREMAPPING_UserSelectable (2UL) /*!< Non-secure or secure attribute for bus access from this domain is defined by the EXTDOMAIN[n].PERM register */ +#define SPU_EXTDOMAIN_PERM_SECUREMAPPING_NonSecure (0x0UL) /*!< The bus access from this external domain always have the non-secure attribute set */ +#define SPU_EXTDOMAIN_PERM_SECUREMAPPING_Secure (0x1UL) /*!< The bus access from this external domain always have the secure attribute set */ +#define SPU_EXTDOMAIN_PERM_SECUREMAPPING_UserSelectable (0x2UL) /*!< Non-secure or secure attribute for bus access from this domain is defined by the EXTDOMAIN[n].PERM register */ /* Register: SPU_DPPI_PERM */ /* Description: Description cluster: Select between secure and non-secure attribute for the DPPI channels. */ @@ -7869,98 +7869,98 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 15 : Select secure attribute. */ #define SPU_DPPI_PERM_CHANNEL15_Pos (15UL) /*!< Position of CHANNEL15 field. */ #define SPU_DPPI_PERM_CHANNEL15_Msk (0x1UL << SPU_DPPI_PERM_CHANNEL15_Pos) /*!< Bit mask of CHANNEL15 field. */ -#define SPU_DPPI_PERM_CHANNEL15_NonSecure (0UL) /*!< Channel15 has its non-secure attribute set */ -#define SPU_DPPI_PERM_CHANNEL15_Secure (1UL) /*!< Channel15 has its secure attribute set */ +#define SPU_DPPI_PERM_CHANNEL15_NonSecure (0x0UL) /*!< Channel15 has its non-secure attribute set */ +#define SPU_DPPI_PERM_CHANNEL15_Secure (0x1UL) /*!< Channel15 has its secure attribute set */ /* Bit 14 : Select secure attribute. */ #define SPU_DPPI_PERM_CHANNEL14_Pos (14UL) /*!< Position of CHANNEL14 field. */ #define SPU_DPPI_PERM_CHANNEL14_Msk (0x1UL << SPU_DPPI_PERM_CHANNEL14_Pos) /*!< Bit mask of CHANNEL14 field. */ -#define SPU_DPPI_PERM_CHANNEL14_NonSecure (0UL) /*!< Channel14 has its non-secure attribute set */ -#define SPU_DPPI_PERM_CHANNEL14_Secure (1UL) /*!< Channel14 has its secure attribute set */ +#define SPU_DPPI_PERM_CHANNEL14_NonSecure (0x0UL) /*!< Channel14 has its non-secure attribute set */ +#define SPU_DPPI_PERM_CHANNEL14_Secure (0x1UL) /*!< Channel14 has its secure attribute set */ /* Bit 13 : Select secure attribute. */ #define SPU_DPPI_PERM_CHANNEL13_Pos (13UL) /*!< Position of CHANNEL13 field. */ #define SPU_DPPI_PERM_CHANNEL13_Msk (0x1UL << SPU_DPPI_PERM_CHANNEL13_Pos) /*!< Bit mask of CHANNEL13 field. */ -#define SPU_DPPI_PERM_CHANNEL13_NonSecure (0UL) /*!< Channel13 has its non-secure attribute set */ -#define SPU_DPPI_PERM_CHANNEL13_Secure (1UL) /*!< Channel13 has its secure attribute set */ +#define SPU_DPPI_PERM_CHANNEL13_NonSecure (0x0UL) /*!< Channel13 has its non-secure attribute set */ +#define SPU_DPPI_PERM_CHANNEL13_Secure (0x1UL) /*!< Channel13 has its secure attribute set */ /* Bit 12 : Select secure attribute. */ #define SPU_DPPI_PERM_CHANNEL12_Pos (12UL) /*!< Position of CHANNEL12 field. */ #define SPU_DPPI_PERM_CHANNEL12_Msk (0x1UL << SPU_DPPI_PERM_CHANNEL12_Pos) /*!< Bit mask of CHANNEL12 field. */ -#define SPU_DPPI_PERM_CHANNEL12_NonSecure (0UL) /*!< Channel12 has its non-secure attribute set */ -#define SPU_DPPI_PERM_CHANNEL12_Secure (1UL) /*!< Channel12 has its secure attribute set */ +#define SPU_DPPI_PERM_CHANNEL12_NonSecure (0x0UL) /*!< Channel12 has its non-secure attribute set */ +#define SPU_DPPI_PERM_CHANNEL12_Secure (0x1UL) /*!< Channel12 has its secure attribute set */ /* Bit 11 : Select secure attribute. */ #define SPU_DPPI_PERM_CHANNEL11_Pos (11UL) /*!< Position of CHANNEL11 field. */ #define SPU_DPPI_PERM_CHANNEL11_Msk (0x1UL << SPU_DPPI_PERM_CHANNEL11_Pos) /*!< Bit mask of CHANNEL11 field. */ -#define SPU_DPPI_PERM_CHANNEL11_NonSecure (0UL) /*!< Channel11 has its non-secure attribute set */ -#define SPU_DPPI_PERM_CHANNEL11_Secure (1UL) /*!< Channel11 has its secure attribute set */ +#define SPU_DPPI_PERM_CHANNEL11_NonSecure (0x0UL) /*!< Channel11 has its non-secure attribute set */ +#define SPU_DPPI_PERM_CHANNEL11_Secure (0x1UL) /*!< Channel11 has its secure attribute set */ /* Bit 10 : Select secure attribute. */ #define SPU_DPPI_PERM_CHANNEL10_Pos (10UL) /*!< Position of CHANNEL10 field. */ #define SPU_DPPI_PERM_CHANNEL10_Msk (0x1UL << SPU_DPPI_PERM_CHANNEL10_Pos) /*!< Bit mask of CHANNEL10 field. */ -#define SPU_DPPI_PERM_CHANNEL10_NonSecure (0UL) /*!< Channel10 has its non-secure attribute set */ -#define SPU_DPPI_PERM_CHANNEL10_Secure (1UL) /*!< Channel10 has its secure attribute set */ +#define SPU_DPPI_PERM_CHANNEL10_NonSecure (0x0UL) /*!< Channel10 has its non-secure attribute set */ +#define SPU_DPPI_PERM_CHANNEL10_Secure (0x1UL) /*!< Channel10 has its secure attribute set */ /* Bit 9 : Select secure attribute. */ #define SPU_DPPI_PERM_CHANNEL9_Pos (9UL) /*!< Position of CHANNEL9 field. */ #define SPU_DPPI_PERM_CHANNEL9_Msk (0x1UL << SPU_DPPI_PERM_CHANNEL9_Pos) /*!< Bit mask of CHANNEL9 field. */ -#define SPU_DPPI_PERM_CHANNEL9_NonSecure (0UL) /*!< Channel9 has its non-secure attribute set */ -#define SPU_DPPI_PERM_CHANNEL9_Secure (1UL) /*!< Channel9 has its secure attribute set */ +#define SPU_DPPI_PERM_CHANNEL9_NonSecure (0x0UL) /*!< Channel9 has its non-secure attribute set */ +#define SPU_DPPI_PERM_CHANNEL9_Secure (0x1UL) /*!< Channel9 has its secure attribute set */ /* Bit 8 : Select secure attribute. */ #define SPU_DPPI_PERM_CHANNEL8_Pos (8UL) /*!< Position of CHANNEL8 field. */ #define SPU_DPPI_PERM_CHANNEL8_Msk (0x1UL << SPU_DPPI_PERM_CHANNEL8_Pos) /*!< Bit mask of CHANNEL8 field. */ -#define SPU_DPPI_PERM_CHANNEL8_NonSecure (0UL) /*!< Channel8 has its non-secure attribute set */ -#define SPU_DPPI_PERM_CHANNEL8_Secure (1UL) /*!< Channel8 has its secure attribute set */ +#define SPU_DPPI_PERM_CHANNEL8_NonSecure (0x0UL) /*!< Channel8 has its non-secure attribute set */ +#define SPU_DPPI_PERM_CHANNEL8_Secure (0x1UL) /*!< Channel8 has its secure attribute set */ /* Bit 7 : Select secure attribute. */ #define SPU_DPPI_PERM_CHANNEL7_Pos (7UL) /*!< Position of CHANNEL7 field. */ #define SPU_DPPI_PERM_CHANNEL7_Msk (0x1UL << SPU_DPPI_PERM_CHANNEL7_Pos) /*!< Bit mask of CHANNEL7 field. */ -#define SPU_DPPI_PERM_CHANNEL7_NonSecure (0UL) /*!< Channel7 has its non-secure attribute set */ -#define SPU_DPPI_PERM_CHANNEL7_Secure (1UL) /*!< Channel7 has its secure attribute set */ +#define SPU_DPPI_PERM_CHANNEL7_NonSecure (0x0UL) /*!< Channel7 has its non-secure attribute set */ +#define SPU_DPPI_PERM_CHANNEL7_Secure (0x1UL) /*!< Channel7 has its secure attribute set */ /* Bit 6 : Select secure attribute. */ #define SPU_DPPI_PERM_CHANNEL6_Pos (6UL) /*!< Position of CHANNEL6 field. */ #define SPU_DPPI_PERM_CHANNEL6_Msk (0x1UL << SPU_DPPI_PERM_CHANNEL6_Pos) /*!< Bit mask of CHANNEL6 field. */ -#define SPU_DPPI_PERM_CHANNEL6_NonSecure (0UL) /*!< Channel6 has its non-secure attribute set */ -#define SPU_DPPI_PERM_CHANNEL6_Secure (1UL) /*!< Channel6 has its secure attribute set */ +#define SPU_DPPI_PERM_CHANNEL6_NonSecure (0x0UL) /*!< Channel6 has its non-secure attribute set */ +#define SPU_DPPI_PERM_CHANNEL6_Secure (0x1UL) /*!< Channel6 has its secure attribute set */ /* Bit 5 : Select secure attribute. */ #define SPU_DPPI_PERM_CHANNEL5_Pos (5UL) /*!< Position of CHANNEL5 field. */ #define SPU_DPPI_PERM_CHANNEL5_Msk (0x1UL << SPU_DPPI_PERM_CHANNEL5_Pos) /*!< Bit mask of CHANNEL5 field. */ -#define SPU_DPPI_PERM_CHANNEL5_NonSecure (0UL) /*!< Channel5 has its non-secure attribute set */ -#define SPU_DPPI_PERM_CHANNEL5_Secure (1UL) /*!< Channel5 has its secure attribute set */ +#define SPU_DPPI_PERM_CHANNEL5_NonSecure (0x0UL) /*!< Channel5 has its non-secure attribute set */ +#define SPU_DPPI_PERM_CHANNEL5_Secure (0x1UL) /*!< Channel5 has its secure attribute set */ /* Bit 4 : Select secure attribute. */ #define SPU_DPPI_PERM_CHANNEL4_Pos (4UL) /*!< Position of CHANNEL4 field. */ #define SPU_DPPI_PERM_CHANNEL4_Msk (0x1UL << SPU_DPPI_PERM_CHANNEL4_Pos) /*!< Bit mask of CHANNEL4 field. */ -#define SPU_DPPI_PERM_CHANNEL4_NonSecure (0UL) /*!< Channel4 has its non-secure attribute set */ -#define SPU_DPPI_PERM_CHANNEL4_Secure (1UL) /*!< Channel4 has its secure attribute set */ +#define SPU_DPPI_PERM_CHANNEL4_NonSecure (0x0UL) /*!< Channel4 has its non-secure attribute set */ +#define SPU_DPPI_PERM_CHANNEL4_Secure (0x1UL) /*!< Channel4 has its secure attribute set */ /* Bit 3 : Select secure attribute. */ #define SPU_DPPI_PERM_CHANNEL3_Pos (3UL) /*!< Position of CHANNEL3 field. */ #define SPU_DPPI_PERM_CHANNEL3_Msk (0x1UL << SPU_DPPI_PERM_CHANNEL3_Pos) /*!< Bit mask of CHANNEL3 field. */ -#define SPU_DPPI_PERM_CHANNEL3_NonSecure (0UL) /*!< Channel3 has its non-secure attribute set */ -#define SPU_DPPI_PERM_CHANNEL3_Secure (1UL) /*!< Channel3 has its secure attribute set */ +#define SPU_DPPI_PERM_CHANNEL3_NonSecure (0x0UL) /*!< Channel3 has its non-secure attribute set */ +#define SPU_DPPI_PERM_CHANNEL3_Secure (0x1UL) /*!< Channel3 has its secure attribute set */ /* Bit 2 : Select secure attribute. */ #define SPU_DPPI_PERM_CHANNEL2_Pos (2UL) /*!< Position of CHANNEL2 field. */ #define SPU_DPPI_PERM_CHANNEL2_Msk (0x1UL << SPU_DPPI_PERM_CHANNEL2_Pos) /*!< Bit mask of CHANNEL2 field. */ -#define SPU_DPPI_PERM_CHANNEL2_NonSecure (0UL) /*!< Channel2 has its non-secure attribute set */ -#define SPU_DPPI_PERM_CHANNEL2_Secure (1UL) /*!< Channel2 has its secure attribute set */ +#define SPU_DPPI_PERM_CHANNEL2_NonSecure (0x0UL) /*!< Channel2 has its non-secure attribute set */ +#define SPU_DPPI_PERM_CHANNEL2_Secure (0x1UL) /*!< Channel2 has its secure attribute set */ /* Bit 1 : Select secure attribute. */ #define SPU_DPPI_PERM_CHANNEL1_Pos (1UL) /*!< Position of CHANNEL1 field. */ #define SPU_DPPI_PERM_CHANNEL1_Msk (0x1UL << SPU_DPPI_PERM_CHANNEL1_Pos) /*!< Bit mask of CHANNEL1 field. */ -#define SPU_DPPI_PERM_CHANNEL1_NonSecure (0UL) /*!< Channel1 has its non-secure attribute set */ -#define SPU_DPPI_PERM_CHANNEL1_Secure (1UL) /*!< Channel1 has its secure attribute set */ +#define SPU_DPPI_PERM_CHANNEL1_NonSecure (0x0UL) /*!< Channel1 has its non-secure attribute set */ +#define SPU_DPPI_PERM_CHANNEL1_Secure (0x1UL) /*!< Channel1 has its secure attribute set */ /* Bit 0 : Select secure attribute. */ #define SPU_DPPI_PERM_CHANNEL0_Pos (0UL) /*!< Position of CHANNEL0 field. */ #define SPU_DPPI_PERM_CHANNEL0_Msk (0x1UL << SPU_DPPI_PERM_CHANNEL0_Pos) /*!< Bit mask of CHANNEL0 field. */ -#define SPU_DPPI_PERM_CHANNEL0_NonSecure (0UL) /*!< Channel0 has its non-secure attribute set */ -#define SPU_DPPI_PERM_CHANNEL0_Secure (1UL) /*!< Channel0 has its secure attribute set */ +#define SPU_DPPI_PERM_CHANNEL0_NonSecure (0x0UL) /*!< Channel0 has its non-secure attribute set */ +#define SPU_DPPI_PERM_CHANNEL0_Secure (0x1UL) /*!< Channel0 has its secure attribute set */ /* Register: SPU_DPPI_LOCK */ /* Description: Description cluster: Prevent further modification of the corresponding PERM register */ @@ -7968,8 +7968,8 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 0 : */ #define SPU_DPPI_LOCK_LOCK_Pos (0UL) /*!< Position of LOCK field. */ #define SPU_DPPI_LOCK_LOCK_Msk (0x1UL << SPU_DPPI_LOCK_LOCK_Pos) /*!< Bit mask of LOCK field. */ -#define SPU_DPPI_LOCK_LOCK_Unlocked (0UL) /*!< DPPI[n].PERM register content can be changed */ -#define SPU_DPPI_LOCK_LOCK_Locked (1UL) /*!< DPPI[n].PERM register can't be changed until next reset */ +#define SPU_DPPI_LOCK_LOCK_Unlocked (0x0UL) /*!< DPPI[n].PERM register content can be changed */ +#define SPU_DPPI_LOCK_LOCK_Locked (0x1UL) /*!< DPPI[n].PERM register can't be changed until next reset */ /* Register: SPU_GPIOPORT_PERM */ /* Description: Description cluster: Select between secure and non-secure attribute for pins 0 to 31 of port n. */ @@ -7977,194 +7977,194 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 31 : Select secure attribute attribute for PIN 31. */ #define SPU_GPIOPORT_PERM_PIN31_Pos (31UL) /*!< Position of PIN31 field. */ #define SPU_GPIOPORT_PERM_PIN31_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN31_Pos) /*!< Bit mask of PIN31 field. */ -#define SPU_GPIOPORT_PERM_PIN31_NonSecure (0UL) /*!< Pin 31 has its non-secure attribute set */ -#define SPU_GPIOPORT_PERM_PIN31_Secure (1UL) /*!< Pin 31 has its secure attribute set */ +#define SPU_GPIOPORT_PERM_PIN31_NonSecure (0x0UL) /*!< Pin 31 has its non-secure attribute set */ +#define SPU_GPIOPORT_PERM_PIN31_Secure (0x1UL) /*!< Pin 31 has its secure attribute set */ /* Bit 30 : Select secure attribute attribute for PIN 30. */ #define SPU_GPIOPORT_PERM_PIN30_Pos (30UL) /*!< Position of PIN30 field. */ #define SPU_GPIOPORT_PERM_PIN30_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN30_Pos) /*!< Bit mask of PIN30 field. */ -#define SPU_GPIOPORT_PERM_PIN30_NonSecure (0UL) /*!< Pin 30 has its non-secure attribute set */ -#define SPU_GPIOPORT_PERM_PIN30_Secure (1UL) /*!< Pin 30 has its secure attribute set */ +#define SPU_GPIOPORT_PERM_PIN30_NonSecure (0x0UL) /*!< Pin 30 has its non-secure attribute set */ +#define SPU_GPIOPORT_PERM_PIN30_Secure (0x1UL) /*!< Pin 30 has its secure attribute set */ /* Bit 29 : Select secure attribute attribute for PIN 29. */ #define SPU_GPIOPORT_PERM_PIN29_Pos (29UL) /*!< Position of PIN29 field. */ #define SPU_GPIOPORT_PERM_PIN29_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN29_Pos) /*!< Bit mask of PIN29 field. */ -#define SPU_GPIOPORT_PERM_PIN29_NonSecure (0UL) /*!< Pin 29 has its non-secure attribute set */ -#define SPU_GPIOPORT_PERM_PIN29_Secure (1UL) /*!< Pin 29 has its secure attribute set */ +#define SPU_GPIOPORT_PERM_PIN29_NonSecure (0x0UL) /*!< Pin 29 has its non-secure attribute set */ +#define SPU_GPIOPORT_PERM_PIN29_Secure (0x1UL) /*!< Pin 29 has its secure attribute set */ /* Bit 28 : Select secure attribute attribute for PIN 28. */ #define SPU_GPIOPORT_PERM_PIN28_Pos (28UL) /*!< Position of PIN28 field. */ #define SPU_GPIOPORT_PERM_PIN28_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN28_Pos) /*!< Bit mask of PIN28 field. */ -#define SPU_GPIOPORT_PERM_PIN28_NonSecure (0UL) /*!< Pin 28 has its non-secure attribute set */ -#define SPU_GPIOPORT_PERM_PIN28_Secure (1UL) /*!< Pin 28 has its secure attribute set */ +#define SPU_GPIOPORT_PERM_PIN28_NonSecure (0x0UL) /*!< Pin 28 has its non-secure attribute set */ +#define SPU_GPIOPORT_PERM_PIN28_Secure (0x1UL) /*!< Pin 28 has its secure attribute set */ /* Bit 27 : Select secure attribute attribute for PIN 27. */ #define SPU_GPIOPORT_PERM_PIN27_Pos (27UL) /*!< Position of PIN27 field. */ #define SPU_GPIOPORT_PERM_PIN27_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN27_Pos) /*!< Bit mask of PIN27 field. */ -#define SPU_GPIOPORT_PERM_PIN27_NonSecure (0UL) /*!< Pin 27 has its non-secure attribute set */ -#define SPU_GPIOPORT_PERM_PIN27_Secure (1UL) /*!< Pin 27 has its secure attribute set */ +#define SPU_GPIOPORT_PERM_PIN27_NonSecure (0x0UL) /*!< Pin 27 has its non-secure attribute set */ +#define SPU_GPIOPORT_PERM_PIN27_Secure (0x1UL) /*!< Pin 27 has its secure attribute set */ /* Bit 26 : Select secure attribute attribute for PIN 26. */ #define SPU_GPIOPORT_PERM_PIN26_Pos (26UL) /*!< Position of PIN26 field. */ #define SPU_GPIOPORT_PERM_PIN26_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN26_Pos) /*!< Bit mask of PIN26 field. */ -#define SPU_GPIOPORT_PERM_PIN26_NonSecure (0UL) /*!< Pin 26 has its non-secure attribute set */ -#define SPU_GPIOPORT_PERM_PIN26_Secure (1UL) /*!< Pin 26 has its secure attribute set */ +#define SPU_GPIOPORT_PERM_PIN26_NonSecure (0x0UL) /*!< Pin 26 has its non-secure attribute set */ +#define SPU_GPIOPORT_PERM_PIN26_Secure (0x1UL) /*!< Pin 26 has its secure attribute set */ /* Bit 25 : Select secure attribute attribute for PIN 25. */ #define SPU_GPIOPORT_PERM_PIN25_Pos (25UL) /*!< Position of PIN25 field. */ #define SPU_GPIOPORT_PERM_PIN25_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN25_Pos) /*!< Bit mask of PIN25 field. */ -#define SPU_GPIOPORT_PERM_PIN25_NonSecure (0UL) /*!< Pin 25 has its non-secure attribute set */ -#define SPU_GPIOPORT_PERM_PIN25_Secure (1UL) /*!< Pin 25 has its secure attribute set */ +#define SPU_GPIOPORT_PERM_PIN25_NonSecure (0x0UL) /*!< Pin 25 has its non-secure attribute set */ +#define SPU_GPIOPORT_PERM_PIN25_Secure (0x1UL) /*!< Pin 25 has its secure attribute set */ /* Bit 24 : Select secure attribute attribute for PIN 24. */ #define SPU_GPIOPORT_PERM_PIN24_Pos (24UL) /*!< Position of PIN24 field. */ #define SPU_GPIOPORT_PERM_PIN24_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN24_Pos) /*!< Bit mask of PIN24 field. */ -#define SPU_GPIOPORT_PERM_PIN24_NonSecure (0UL) /*!< Pin 24 has its non-secure attribute set */ -#define SPU_GPIOPORT_PERM_PIN24_Secure (1UL) /*!< Pin 24 has its secure attribute set */ +#define SPU_GPIOPORT_PERM_PIN24_NonSecure (0x0UL) /*!< Pin 24 has its non-secure attribute set */ +#define SPU_GPIOPORT_PERM_PIN24_Secure (0x1UL) /*!< Pin 24 has its secure attribute set */ /* Bit 23 : Select secure attribute attribute for PIN 23. */ #define SPU_GPIOPORT_PERM_PIN23_Pos (23UL) /*!< Position of PIN23 field. */ #define SPU_GPIOPORT_PERM_PIN23_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN23_Pos) /*!< Bit mask of PIN23 field. */ -#define SPU_GPIOPORT_PERM_PIN23_NonSecure (0UL) /*!< Pin 23 has its non-secure attribute set */ -#define SPU_GPIOPORT_PERM_PIN23_Secure (1UL) /*!< Pin 23 has its secure attribute set */ +#define SPU_GPIOPORT_PERM_PIN23_NonSecure (0x0UL) /*!< Pin 23 has its non-secure attribute set */ +#define SPU_GPIOPORT_PERM_PIN23_Secure (0x1UL) /*!< Pin 23 has its secure attribute set */ /* Bit 22 : Select secure attribute attribute for PIN 22. */ #define SPU_GPIOPORT_PERM_PIN22_Pos (22UL) /*!< Position of PIN22 field. */ #define SPU_GPIOPORT_PERM_PIN22_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN22_Pos) /*!< Bit mask of PIN22 field. */ -#define SPU_GPIOPORT_PERM_PIN22_NonSecure (0UL) /*!< Pin 22 has its non-secure attribute set */ -#define SPU_GPIOPORT_PERM_PIN22_Secure (1UL) /*!< Pin 22 has its secure attribute set */ +#define SPU_GPIOPORT_PERM_PIN22_NonSecure (0x0UL) /*!< Pin 22 has its non-secure attribute set */ +#define SPU_GPIOPORT_PERM_PIN22_Secure (0x1UL) /*!< Pin 22 has its secure attribute set */ /* Bit 21 : Select secure attribute attribute for PIN 21. */ #define SPU_GPIOPORT_PERM_PIN21_Pos (21UL) /*!< Position of PIN21 field. */ #define SPU_GPIOPORT_PERM_PIN21_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN21_Pos) /*!< Bit mask of PIN21 field. */ -#define SPU_GPIOPORT_PERM_PIN21_NonSecure (0UL) /*!< Pin 21 has its non-secure attribute set */ -#define SPU_GPIOPORT_PERM_PIN21_Secure (1UL) /*!< Pin 21 has its secure attribute set */ +#define SPU_GPIOPORT_PERM_PIN21_NonSecure (0x0UL) /*!< Pin 21 has its non-secure attribute set */ +#define SPU_GPIOPORT_PERM_PIN21_Secure (0x1UL) /*!< Pin 21 has its secure attribute set */ /* Bit 20 : Select secure attribute attribute for PIN 20. */ #define SPU_GPIOPORT_PERM_PIN20_Pos (20UL) /*!< Position of PIN20 field. */ #define SPU_GPIOPORT_PERM_PIN20_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN20_Pos) /*!< Bit mask of PIN20 field. */ -#define SPU_GPIOPORT_PERM_PIN20_NonSecure (0UL) /*!< Pin 20 has its non-secure attribute set */ -#define SPU_GPIOPORT_PERM_PIN20_Secure (1UL) /*!< Pin 20 has its secure attribute set */ +#define SPU_GPIOPORT_PERM_PIN20_NonSecure (0x0UL) /*!< Pin 20 has its non-secure attribute set */ +#define SPU_GPIOPORT_PERM_PIN20_Secure (0x1UL) /*!< Pin 20 has its secure attribute set */ /* Bit 19 : Select secure attribute attribute for PIN 19. */ #define SPU_GPIOPORT_PERM_PIN19_Pos (19UL) /*!< Position of PIN19 field. */ #define SPU_GPIOPORT_PERM_PIN19_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN19_Pos) /*!< Bit mask of PIN19 field. */ -#define SPU_GPIOPORT_PERM_PIN19_NonSecure (0UL) /*!< Pin 19 has its non-secure attribute set */ -#define SPU_GPIOPORT_PERM_PIN19_Secure (1UL) /*!< Pin 19 has its secure attribute set */ +#define SPU_GPIOPORT_PERM_PIN19_NonSecure (0x0UL) /*!< Pin 19 has its non-secure attribute set */ +#define SPU_GPIOPORT_PERM_PIN19_Secure (0x1UL) /*!< Pin 19 has its secure attribute set */ /* Bit 18 : Select secure attribute attribute for PIN 18. */ #define SPU_GPIOPORT_PERM_PIN18_Pos (18UL) /*!< Position of PIN18 field. */ #define SPU_GPIOPORT_PERM_PIN18_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN18_Pos) /*!< Bit mask of PIN18 field. */ -#define SPU_GPIOPORT_PERM_PIN18_NonSecure (0UL) /*!< Pin 18 has its non-secure attribute set */ -#define SPU_GPIOPORT_PERM_PIN18_Secure (1UL) /*!< Pin 18 has its secure attribute set */ +#define SPU_GPIOPORT_PERM_PIN18_NonSecure (0x0UL) /*!< Pin 18 has its non-secure attribute set */ +#define SPU_GPIOPORT_PERM_PIN18_Secure (0x1UL) /*!< Pin 18 has its secure attribute set */ /* Bit 17 : Select secure attribute attribute for PIN 17. */ #define SPU_GPIOPORT_PERM_PIN17_Pos (17UL) /*!< Position of PIN17 field. */ #define SPU_GPIOPORT_PERM_PIN17_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN17_Pos) /*!< Bit mask of PIN17 field. */ -#define SPU_GPIOPORT_PERM_PIN17_NonSecure (0UL) /*!< Pin 17 has its non-secure attribute set */ -#define SPU_GPIOPORT_PERM_PIN17_Secure (1UL) /*!< Pin 17 has its secure attribute set */ +#define SPU_GPIOPORT_PERM_PIN17_NonSecure (0x0UL) /*!< Pin 17 has its non-secure attribute set */ +#define SPU_GPIOPORT_PERM_PIN17_Secure (0x1UL) /*!< Pin 17 has its secure attribute set */ /* Bit 16 : Select secure attribute attribute for PIN 16. */ #define SPU_GPIOPORT_PERM_PIN16_Pos (16UL) /*!< Position of PIN16 field. */ #define SPU_GPIOPORT_PERM_PIN16_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN16_Pos) /*!< Bit mask of PIN16 field. */ -#define SPU_GPIOPORT_PERM_PIN16_NonSecure (0UL) /*!< Pin 16 has its non-secure attribute set */ -#define SPU_GPIOPORT_PERM_PIN16_Secure (1UL) /*!< Pin 16 has its secure attribute set */ +#define SPU_GPIOPORT_PERM_PIN16_NonSecure (0x0UL) /*!< Pin 16 has its non-secure attribute set */ +#define SPU_GPIOPORT_PERM_PIN16_Secure (0x1UL) /*!< Pin 16 has its secure attribute set */ /* Bit 15 : Select secure attribute attribute for PIN 15. */ #define SPU_GPIOPORT_PERM_PIN15_Pos (15UL) /*!< Position of PIN15 field. */ #define SPU_GPIOPORT_PERM_PIN15_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN15_Pos) /*!< Bit mask of PIN15 field. */ -#define SPU_GPIOPORT_PERM_PIN15_NonSecure (0UL) /*!< Pin 15 has its non-secure attribute set */ -#define SPU_GPIOPORT_PERM_PIN15_Secure (1UL) /*!< Pin 15 has its secure attribute set */ +#define SPU_GPIOPORT_PERM_PIN15_NonSecure (0x0UL) /*!< Pin 15 has its non-secure attribute set */ +#define SPU_GPIOPORT_PERM_PIN15_Secure (0x1UL) /*!< Pin 15 has its secure attribute set */ /* Bit 14 : Select secure attribute attribute for PIN 14. */ #define SPU_GPIOPORT_PERM_PIN14_Pos (14UL) /*!< Position of PIN14 field. */ #define SPU_GPIOPORT_PERM_PIN14_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN14_Pos) /*!< Bit mask of PIN14 field. */ -#define SPU_GPIOPORT_PERM_PIN14_NonSecure (0UL) /*!< Pin 14 has its non-secure attribute set */ -#define SPU_GPIOPORT_PERM_PIN14_Secure (1UL) /*!< Pin 14 has its secure attribute set */ +#define SPU_GPIOPORT_PERM_PIN14_NonSecure (0x0UL) /*!< Pin 14 has its non-secure attribute set */ +#define SPU_GPIOPORT_PERM_PIN14_Secure (0x1UL) /*!< Pin 14 has its secure attribute set */ /* Bit 13 : Select secure attribute attribute for PIN 13. */ #define SPU_GPIOPORT_PERM_PIN13_Pos (13UL) /*!< Position of PIN13 field. */ #define SPU_GPIOPORT_PERM_PIN13_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN13_Pos) /*!< Bit mask of PIN13 field. */ -#define SPU_GPIOPORT_PERM_PIN13_NonSecure (0UL) /*!< Pin 13 has its non-secure attribute set */ -#define SPU_GPIOPORT_PERM_PIN13_Secure (1UL) /*!< Pin 13 has its secure attribute set */ +#define SPU_GPIOPORT_PERM_PIN13_NonSecure (0x0UL) /*!< Pin 13 has its non-secure attribute set */ +#define SPU_GPIOPORT_PERM_PIN13_Secure (0x1UL) /*!< Pin 13 has its secure attribute set */ /* Bit 12 : Select secure attribute attribute for PIN 12. */ #define SPU_GPIOPORT_PERM_PIN12_Pos (12UL) /*!< Position of PIN12 field. */ #define SPU_GPIOPORT_PERM_PIN12_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN12_Pos) /*!< Bit mask of PIN12 field. */ -#define SPU_GPIOPORT_PERM_PIN12_NonSecure (0UL) /*!< Pin 12 has its non-secure attribute set */ -#define SPU_GPIOPORT_PERM_PIN12_Secure (1UL) /*!< Pin 12 has its secure attribute set */ +#define SPU_GPIOPORT_PERM_PIN12_NonSecure (0x0UL) /*!< Pin 12 has its non-secure attribute set */ +#define SPU_GPIOPORT_PERM_PIN12_Secure (0x1UL) /*!< Pin 12 has its secure attribute set */ /* Bit 11 : Select secure attribute attribute for PIN 11. */ #define SPU_GPIOPORT_PERM_PIN11_Pos (11UL) /*!< Position of PIN11 field. */ #define SPU_GPIOPORT_PERM_PIN11_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN11_Pos) /*!< Bit mask of PIN11 field. */ -#define SPU_GPIOPORT_PERM_PIN11_NonSecure (0UL) /*!< Pin 11 has its non-secure attribute set */ -#define SPU_GPIOPORT_PERM_PIN11_Secure (1UL) /*!< Pin 11 has its secure attribute set */ +#define SPU_GPIOPORT_PERM_PIN11_NonSecure (0x0UL) /*!< Pin 11 has its non-secure attribute set */ +#define SPU_GPIOPORT_PERM_PIN11_Secure (0x1UL) /*!< Pin 11 has its secure attribute set */ /* Bit 10 : Select secure attribute attribute for PIN 10. */ #define SPU_GPIOPORT_PERM_PIN10_Pos (10UL) /*!< Position of PIN10 field. */ #define SPU_GPIOPORT_PERM_PIN10_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN10_Pos) /*!< Bit mask of PIN10 field. */ -#define SPU_GPIOPORT_PERM_PIN10_NonSecure (0UL) /*!< Pin 10 has its non-secure attribute set */ -#define SPU_GPIOPORT_PERM_PIN10_Secure (1UL) /*!< Pin 10 has its secure attribute set */ +#define SPU_GPIOPORT_PERM_PIN10_NonSecure (0x0UL) /*!< Pin 10 has its non-secure attribute set */ +#define SPU_GPIOPORT_PERM_PIN10_Secure (0x1UL) /*!< Pin 10 has its secure attribute set */ /* Bit 9 : Select secure attribute attribute for PIN 9. */ #define SPU_GPIOPORT_PERM_PIN9_Pos (9UL) /*!< Position of PIN9 field. */ #define SPU_GPIOPORT_PERM_PIN9_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN9_Pos) /*!< Bit mask of PIN9 field. */ -#define SPU_GPIOPORT_PERM_PIN9_NonSecure (0UL) /*!< Pin 9 has its non-secure attribute set */ -#define SPU_GPIOPORT_PERM_PIN9_Secure (1UL) /*!< Pin 9 has its secure attribute set */ +#define SPU_GPIOPORT_PERM_PIN9_NonSecure (0x0UL) /*!< Pin 9 has its non-secure attribute set */ +#define SPU_GPIOPORT_PERM_PIN9_Secure (0x1UL) /*!< Pin 9 has its secure attribute set */ /* Bit 8 : Select secure attribute attribute for PIN 8. */ #define SPU_GPIOPORT_PERM_PIN8_Pos (8UL) /*!< Position of PIN8 field. */ #define SPU_GPIOPORT_PERM_PIN8_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN8_Pos) /*!< Bit mask of PIN8 field. */ -#define SPU_GPIOPORT_PERM_PIN8_NonSecure (0UL) /*!< Pin 8 has its non-secure attribute set */ -#define SPU_GPIOPORT_PERM_PIN8_Secure (1UL) /*!< Pin 8 has its secure attribute set */ +#define SPU_GPIOPORT_PERM_PIN8_NonSecure (0x0UL) /*!< Pin 8 has its non-secure attribute set */ +#define SPU_GPIOPORT_PERM_PIN8_Secure (0x1UL) /*!< Pin 8 has its secure attribute set */ /* Bit 7 : Select secure attribute attribute for PIN 7. */ #define SPU_GPIOPORT_PERM_PIN7_Pos (7UL) /*!< Position of PIN7 field. */ #define SPU_GPIOPORT_PERM_PIN7_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN7_Pos) /*!< Bit mask of PIN7 field. */ -#define SPU_GPIOPORT_PERM_PIN7_NonSecure (0UL) /*!< Pin 7 has its non-secure attribute set */ -#define SPU_GPIOPORT_PERM_PIN7_Secure (1UL) /*!< Pin 7 has its secure attribute set */ +#define SPU_GPIOPORT_PERM_PIN7_NonSecure (0x0UL) /*!< Pin 7 has its non-secure attribute set */ +#define SPU_GPIOPORT_PERM_PIN7_Secure (0x1UL) /*!< Pin 7 has its secure attribute set */ /* Bit 6 : Select secure attribute attribute for PIN 6. */ #define SPU_GPIOPORT_PERM_PIN6_Pos (6UL) /*!< Position of PIN6 field. */ #define SPU_GPIOPORT_PERM_PIN6_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN6_Pos) /*!< Bit mask of PIN6 field. */ -#define SPU_GPIOPORT_PERM_PIN6_NonSecure (0UL) /*!< Pin 6 has its non-secure attribute set */ -#define SPU_GPIOPORT_PERM_PIN6_Secure (1UL) /*!< Pin 6 has its secure attribute set */ +#define SPU_GPIOPORT_PERM_PIN6_NonSecure (0x0UL) /*!< Pin 6 has its non-secure attribute set */ +#define SPU_GPIOPORT_PERM_PIN6_Secure (0x1UL) /*!< Pin 6 has its secure attribute set */ /* Bit 5 : Select secure attribute attribute for PIN 5. */ #define SPU_GPIOPORT_PERM_PIN5_Pos (5UL) /*!< Position of PIN5 field. */ #define SPU_GPIOPORT_PERM_PIN5_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN5_Pos) /*!< Bit mask of PIN5 field. */ -#define SPU_GPIOPORT_PERM_PIN5_NonSecure (0UL) /*!< Pin 5 has its non-secure attribute set */ -#define SPU_GPIOPORT_PERM_PIN5_Secure (1UL) /*!< Pin 5 has its secure attribute set */ +#define SPU_GPIOPORT_PERM_PIN5_NonSecure (0x0UL) /*!< Pin 5 has its non-secure attribute set */ +#define SPU_GPIOPORT_PERM_PIN5_Secure (0x1UL) /*!< Pin 5 has its secure attribute set */ /* Bit 4 : Select secure attribute attribute for PIN 4. */ #define SPU_GPIOPORT_PERM_PIN4_Pos (4UL) /*!< Position of PIN4 field. */ #define SPU_GPIOPORT_PERM_PIN4_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN4_Pos) /*!< Bit mask of PIN4 field. */ -#define SPU_GPIOPORT_PERM_PIN4_NonSecure (0UL) /*!< Pin 4 has its non-secure attribute set */ -#define SPU_GPIOPORT_PERM_PIN4_Secure (1UL) /*!< Pin 4 has its secure attribute set */ +#define SPU_GPIOPORT_PERM_PIN4_NonSecure (0x0UL) /*!< Pin 4 has its non-secure attribute set */ +#define SPU_GPIOPORT_PERM_PIN4_Secure (0x1UL) /*!< Pin 4 has its secure attribute set */ /* Bit 3 : Select secure attribute attribute for PIN 3. */ #define SPU_GPIOPORT_PERM_PIN3_Pos (3UL) /*!< Position of PIN3 field. */ #define SPU_GPIOPORT_PERM_PIN3_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN3_Pos) /*!< Bit mask of PIN3 field. */ -#define SPU_GPIOPORT_PERM_PIN3_NonSecure (0UL) /*!< Pin 3 has its non-secure attribute set */ -#define SPU_GPIOPORT_PERM_PIN3_Secure (1UL) /*!< Pin 3 has its secure attribute set */ +#define SPU_GPIOPORT_PERM_PIN3_NonSecure (0x0UL) /*!< Pin 3 has its non-secure attribute set */ +#define SPU_GPIOPORT_PERM_PIN3_Secure (0x1UL) /*!< Pin 3 has its secure attribute set */ /* Bit 2 : Select secure attribute attribute for PIN 2. */ #define SPU_GPIOPORT_PERM_PIN2_Pos (2UL) /*!< Position of PIN2 field. */ #define SPU_GPIOPORT_PERM_PIN2_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN2_Pos) /*!< Bit mask of PIN2 field. */ -#define SPU_GPIOPORT_PERM_PIN2_NonSecure (0UL) /*!< Pin 2 has its non-secure attribute set */ -#define SPU_GPIOPORT_PERM_PIN2_Secure (1UL) /*!< Pin 2 has its secure attribute set */ +#define SPU_GPIOPORT_PERM_PIN2_NonSecure (0x0UL) /*!< Pin 2 has its non-secure attribute set */ +#define SPU_GPIOPORT_PERM_PIN2_Secure (0x1UL) /*!< Pin 2 has its secure attribute set */ /* Bit 1 : Select secure attribute attribute for PIN 1. */ #define SPU_GPIOPORT_PERM_PIN1_Pos (1UL) /*!< Position of PIN1 field. */ #define SPU_GPIOPORT_PERM_PIN1_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN1_Pos) /*!< Bit mask of PIN1 field. */ -#define SPU_GPIOPORT_PERM_PIN1_NonSecure (0UL) /*!< Pin 1 has its non-secure attribute set */ -#define SPU_GPIOPORT_PERM_PIN1_Secure (1UL) /*!< Pin 1 has its secure attribute set */ +#define SPU_GPIOPORT_PERM_PIN1_NonSecure (0x0UL) /*!< Pin 1 has its non-secure attribute set */ +#define SPU_GPIOPORT_PERM_PIN1_Secure (0x1UL) /*!< Pin 1 has its secure attribute set */ /* Bit 0 : Select secure attribute attribute for PIN 0. */ #define SPU_GPIOPORT_PERM_PIN0_Pos (0UL) /*!< Position of PIN0 field. */ #define SPU_GPIOPORT_PERM_PIN0_Msk (0x1UL << SPU_GPIOPORT_PERM_PIN0_Pos) /*!< Bit mask of PIN0 field. */ -#define SPU_GPIOPORT_PERM_PIN0_NonSecure (0UL) /*!< Pin 0 has its non-secure attribute set */ -#define SPU_GPIOPORT_PERM_PIN0_Secure (1UL) /*!< Pin 0 has its secure attribute set */ +#define SPU_GPIOPORT_PERM_PIN0_NonSecure (0x0UL) /*!< Pin 0 has its non-secure attribute set */ +#define SPU_GPIOPORT_PERM_PIN0_Secure (0x1UL) /*!< Pin 0 has its secure attribute set */ /* Register: SPU_GPIOPORT_LOCK */ /* Description: Description cluster: Prevent further modification of the corresponding PERM register */ @@ -8172,8 +8172,8 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 0 : */ #define SPU_GPIOPORT_LOCK_LOCK_Pos (0UL) /*!< Position of LOCK field. */ #define SPU_GPIOPORT_LOCK_LOCK_Msk (0x1UL << SPU_GPIOPORT_LOCK_LOCK_Pos) /*!< Bit mask of LOCK field. */ -#define SPU_GPIOPORT_LOCK_LOCK_Unlocked (0UL) /*!< GPIOPORT[n].PERM register content can be changed */ -#define SPU_GPIOPORT_LOCK_LOCK_Locked (1UL) /*!< GPIOPORT[n].PERM register can't be changed until next reset */ +#define SPU_GPIOPORT_LOCK_LOCK_Unlocked (0x0UL) /*!< GPIOPORT[n].PERM register content can be changed */ +#define SPU_GPIOPORT_LOCK_LOCK_Locked (0x1UL) /*!< GPIOPORT[n].PERM register can't be changed until next reset */ /* Register: SPU_FLASHNSC_REGION */ /* Description: Description cluster: Define which flash region can contain the non-secure callable (NSC) region n */ @@ -8181,8 +8181,8 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 8 : */ #define SPU_FLASHNSC_REGION_LOCK_Pos (8UL) /*!< Position of LOCK field. */ #define SPU_FLASHNSC_REGION_LOCK_Msk (0x1UL << SPU_FLASHNSC_REGION_LOCK_Pos) /*!< Bit mask of LOCK field. */ -#define SPU_FLASHNSC_REGION_LOCK_Unlocked (0UL) /*!< This register can be updated */ -#define SPU_FLASHNSC_REGION_LOCK_Locked (1UL) /*!< The content of this register can't be changed until the next reset */ +#define SPU_FLASHNSC_REGION_LOCK_Unlocked (0x0UL) /*!< This register can be updated */ +#define SPU_FLASHNSC_REGION_LOCK_Locked (0x1UL) /*!< The content of this register can't be changed until the next reset */ /* Bits 4..0 : Region number */ #define SPU_FLASHNSC_REGION_REGION_Pos (0UL) /*!< Position of REGION field. */ @@ -8194,21 +8194,21 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 8 : */ #define SPU_FLASHNSC_SIZE_LOCK_Pos (8UL) /*!< Position of LOCK field. */ #define SPU_FLASHNSC_SIZE_LOCK_Msk (0x1UL << SPU_FLASHNSC_SIZE_LOCK_Pos) /*!< Bit mask of LOCK field. */ -#define SPU_FLASHNSC_SIZE_LOCK_Unlocked (0UL) /*!< This register can be updated */ -#define SPU_FLASHNSC_SIZE_LOCK_Locked (1UL) /*!< The content of this register can't be changed until the next reset */ +#define SPU_FLASHNSC_SIZE_LOCK_Unlocked (0x0UL) /*!< This register can be updated */ +#define SPU_FLASHNSC_SIZE_LOCK_Locked (0x1UL) /*!< The content of this register can't be changed until the next reset */ /* Bits 3..0 : Size of the non-secure callable (NSC) region n */ #define SPU_FLASHNSC_SIZE_SIZE_Pos (0UL) /*!< Position of SIZE field. */ #define SPU_FLASHNSC_SIZE_SIZE_Msk (0xFUL << SPU_FLASHNSC_SIZE_SIZE_Pos) /*!< Bit mask of SIZE field. */ -#define SPU_FLASHNSC_SIZE_SIZE_Disabled (0UL) /*!< The region n is not defined as a non-secure callable region. Normal security attributes (secure or non-secure) are enforced. */ -#define SPU_FLASHNSC_SIZE_SIZE_32 (1UL) /*!< The region n is defined as non-secure callable with a 32-byte size */ -#define SPU_FLASHNSC_SIZE_SIZE_64 (2UL) /*!< The region n is defined as non-secure callable with a 64-byte size */ -#define SPU_FLASHNSC_SIZE_SIZE_128 (3UL) /*!< The region n is defined as non-secure callable with a 128-byte size */ -#define SPU_FLASHNSC_SIZE_SIZE_256 (4UL) /*!< The region n is defined as non-secure callable with a 256-byte size */ -#define SPU_FLASHNSC_SIZE_SIZE_512 (5UL) /*!< The region n is defined as non-secure callable with a 512-byte size */ -#define SPU_FLASHNSC_SIZE_SIZE_1024 (6UL) /*!< The region n is defined as non-secure callable with a 1024-byte size */ -#define SPU_FLASHNSC_SIZE_SIZE_2048 (7UL) /*!< The region n is defined as non-secure callable with a 2048-byte size */ -#define SPU_FLASHNSC_SIZE_SIZE_4096 (8UL) /*!< The region n is defined as non-secure callable with a 4096-byte size */ +#define SPU_FLASHNSC_SIZE_SIZE_Disabled (0x0UL) /*!< The region n is not defined as a non-secure callable region. Normal security attributes (secure or non-secure) are enforced. */ +#define SPU_FLASHNSC_SIZE_SIZE_32 (0x1UL) /*!< The region n is defined as non-secure callable with a 32-byte size */ +#define SPU_FLASHNSC_SIZE_SIZE_64 (0x2UL) /*!< The region n is defined as non-secure callable with a 64-byte size */ +#define SPU_FLASHNSC_SIZE_SIZE_128 (0x3UL) /*!< The region n is defined as non-secure callable with a 128-byte size */ +#define SPU_FLASHNSC_SIZE_SIZE_256 (0x4UL) /*!< The region n is defined as non-secure callable with a 256-byte size */ +#define SPU_FLASHNSC_SIZE_SIZE_512 (0x5UL) /*!< The region n is defined as non-secure callable with a 512-byte size */ +#define SPU_FLASHNSC_SIZE_SIZE_1024 (0x6UL) /*!< The region n is defined as non-secure callable with a 1024-byte size */ +#define SPU_FLASHNSC_SIZE_SIZE_2048 (0x7UL) /*!< The region n is defined as non-secure callable with a 2048-byte size */ +#define SPU_FLASHNSC_SIZE_SIZE_4096 (0x8UL) /*!< The region n is defined as non-secure callable with a 4096-byte size */ /* Register: SPU_RAMNSC_REGION */ /* Description: Description cluster: Define which RAM region can contain the non-secure callable (NSC) region n */ @@ -8216,8 +8216,8 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 8 : */ #define SPU_RAMNSC_REGION_LOCK_Pos (8UL) /*!< Position of LOCK field. */ #define SPU_RAMNSC_REGION_LOCK_Msk (0x1UL << SPU_RAMNSC_REGION_LOCK_Pos) /*!< Bit mask of LOCK field. */ -#define SPU_RAMNSC_REGION_LOCK_Unlocked (0UL) /*!< This register can be updated */ -#define SPU_RAMNSC_REGION_LOCK_Locked (1UL) /*!< The content of this register can't be changed until the next reset */ +#define SPU_RAMNSC_REGION_LOCK_Unlocked (0x0UL) /*!< This register can be updated */ +#define SPU_RAMNSC_REGION_LOCK_Locked (0x1UL) /*!< The content of this register can't be changed until the next reset */ /* Bits 4..0 : Region number */ #define SPU_RAMNSC_REGION_REGION_Pos (0UL) /*!< Position of REGION field. */ @@ -8229,21 +8229,21 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 8 : */ #define SPU_RAMNSC_SIZE_LOCK_Pos (8UL) /*!< Position of LOCK field. */ #define SPU_RAMNSC_SIZE_LOCK_Msk (0x1UL << SPU_RAMNSC_SIZE_LOCK_Pos) /*!< Bit mask of LOCK field. */ -#define SPU_RAMNSC_SIZE_LOCK_Unlocked (0UL) /*!< This register can be updated */ -#define SPU_RAMNSC_SIZE_LOCK_Locked (1UL) /*!< The content of this register can't be changed until the next reset */ +#define SPU_RAMNSC_SIZE_LOCK_Unlocked (0x0UL) /*!< This register can be updated */ +#define SPU_RAMNSC_SIZE_LOCK_Locked (0x1UL) /*!< The content of this register can't be changed until the next reset */ /* Bits 3..0 : Size of the non-secure callable (NSC) region n */ #define SPU_RAMNSC_SIZE_SIZE_Pos (0UL) /*!< Position of SIZE field. */ #define SPU_RAMNSC_SIZE_SIZE_Msk (0xFUL << SPU_RAMNSC_SIZE_SIZE_Pos) /*!< Bit mask of SIZE field. */ -#define SPU_RAMNSC_SIZE_SIZE_Disabled (0UL) /*!< The region n is not defined as a non-secure callable region. Normal security attributes (secure or non-secure) are enforced. */ -#define SPU_RAMNSC_SIZE_SIZE_32 (1UL) /*!< The region n is defined as non-secure callable with a 32-byte size */ -#define SPU_RAMNSC_SIZE_SIZE_64 (2UL) /*!< The region n is defined as non-secure callable with a 64-byte size */ -#define SPU_RAMNSC_SIZE_SIZE_128 (3UL) /*!< The region n is defined as non-secure callable with a 128-byte size */ -#define SPU_RAMNSC_SIZE_SIZE_256 (4UL) /*!< The region n is defined as non-secure callable with a 256-byte size */ -#define SPU_RAMNSC_SIZE_SIZE_512 (5UL) /*!< The region n is defined as non-secure callable with a 512-byte size */ -#define SPU_RAMNSC_SIZE_SIZE_1024 (6UL) /*!< The region n is defined as non-secure callable with a 1024-byte size */ -#define SPU_RAMNSC_SIZE_SIZE_2048 (7UL) /*!< The region n is defined as non-secure callable with a 2048-byte size */ -#define SPU_RAMNSC_SIZE_SIZE_4096 (8UL) /*!< The region n is defined as non-secure callable with a 4096-byte size */ +#define SPU_RAMNSC_SIZE_SIZE_Disabled (0x0UL) /*!< The region n is not defined as a non-secure callable region. Normal security attributes (secure or non-secure) are enforced. */ +#define SPU_RAMNSC_SIZE_SIZE_32 (0x1UL) /*!< The region n is defined as non-secure callable with a 32-byte size */ +#define SPU_RAMNSC_SIZE_SIZE_64 (0x2UL) /*!< The region n is defined as non-secure callable with a 64-byte size */ +#define SPU_RAMNSC_SIZE_SIZE_128 (0x3UL) /*!< The region n is defined as non-secure callable with a 128-byte size */ +#define SPU_RAMNSC_SIZE_SIZE_256 (0x4UL) /*!< The region n is defined as non-secure callable with a 256-byte size */ +#define SPU_RAMNSC_SIZE_SIZE_512 (0x5UL) /*!< The region n is defined as non-secure callable with a 512-byte size */ +#define SPU_RAMNSC_SIZE_SIZE_1024 (0x6UL) /*!< The region n is defined as non-secure callable with a 1024-byte size */ +#define SPU_RAMNSC_SIZE_SIZE_2048 (0x7UL) /*!< The region n is defined as non-secure callable with a 2048-byte size */ +#define SPU_RAMNSC_SIZE_SIZE_4096 (0x8UL) /*!< The region n is defined as non-secure callable with a 4096-byte size */ /* Register: SPU_FLASHREGION_PERM */ /* Description: Description cluster: Access permissions for flash region n */ @@ -8251,32 +8251,32 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 8 : */ #define SPU_FLASHREGION_PERM_LOCK_Pos (8UL) /*!< Position of LOCK field. */ #define SPU_FLASHREGION_PERM_LOCK_Msk (0x1UL << SPU_FLASHREGION_PERM_LOCK_Pos) /*!< Bit mask of LOCK field. */ -#define SPU_FLASHREGION_PERM_LOCK_Unlocked (0UL) /*!< This register can be updated */ -#define SPU_FLASHREGION_PERM_LOCK_Locked (1UL) /*!< The content of this register can't be changed until the next reset */ +#define SPU_FLASHREGION_PERM_LOCK_Unlocked (0x0UL) /*!< This register can be updated */ +#define SPU_FLASHREGION_PERM_LOCK_Locked (0x1UL) /*!< The content of this register can't be changed until the next reset */ /* Bit 4 : Security attribute for flash region n */ #define SPU_FLASHREGION_PERM_SECATTR_Pos (4UL) /*!< Position of SECATTR field. */ #define SPU_FLASHREGION_PERM_SECATTR_Msk (0x1UL << SPU_FLASHREGION_PERM_SECATTR_Pos) /*!< Bit mask of SECATTR field. */ -#define SPU_FLASHREGION_PERM_SECATTR_Non_Secure (0UL) /*!< Flash region n security attribute is non-secure */ -#define SPU_FLASHREGION_PERM_SECATTR_Secure (1UL) /*!< Flash region n security attribute is secure */ +#define SPU_FLASHREGION_PERM_SECATTR_Non_Secure (0x0UL) /*!< Flash region n security attribute is non-secure */ +#define SPU_FLASHREGION_PERM_SECATTR_Secure (0x1UL) /*!< Flash region n security attribute is secure */ /* Bit 2 : Configure read permissions for flash region n */ #define SPU_FLASHREGION_PERM_READ_Pos (2UL) /*!< Position of READ field. */ #define SPU_FLASHREGION_PERM_READ_Msk (0x1UL << SPU_FLASHREGION_PERM_READ_Pos) /*!< Bit mask of READ field. */ -#define SPU_FLASHREGION_PERM_READ_Disable (0UL) /*!< Block read operation from flash region n */ -#define SPU_FLASHREGION_PERM_READ_Enable (1UL) /*!< Allow read operation from flash region n */ +#define SPU_FLASHREGION_PERM_READ_Disable (0x0UL) /*!< Block read operation from flash region n */ +#define SPU_FLASHREGION_PERM_READ_Enable (0x1UL) /*!< Allow read operation from flash region n */ /* Bit 1 : Configure write permission for flash region n */ #define SPU_FLASHREGION_PERM_WRITE_Pos (1UL) /*!< Position of WRITE field. */ #define SPU_FLASHREGION_PERM_WRITE_Msk (0x1UL << SPU_FLASHREGION_PERM_WRITE_Pos) /*!< Bit mask of WRITE field. */ -#define SPU_FLASHREGION_PERM_WRITE_Disable (0UL) /*!< Block write operation to region n */ -#define SPU_FLASHREGION_PERM_WRITE_Enable (1UL) /*!< Allow write operation to region n */ +#define SPU_FLASHREGION_PERM_WRITE_Disable (0x0UL) /*!< Block write operation to region n */ +#define SPU_FLASHREGION_PERM_WRITE_Enable (0x1UL) /*!< Allow write operation to region n */ /* Bit 0 : Configure instruction fetch permissions from flash region n */ #define SPU_FLASHREGION_PERM_EXECUTE_Pos (0UL) /*!< Position of EXECUTE field. */ #define SPU_FLASHREGION_PERM_EXECUTE_Msk (0x1UL << SPU_FLASHREGION_PERM_EXECUTE_Pos) /*!< Bit mask of EXECUTE field. */ -#define SPU_FLASHREGION_PERM_EXECUTE_Disable (0UL) /*!< Block instruction fetches from flash region n */ -#define SPU_FLASHREGION_PERM_EXECUTE_Enable (1UL) /*!< Allow instruction fetches from flash region n */ +#define SPU_FLASHREGION_PERM_EXECUTE_Disable (0x0UL) /*!< Block instruction fetches from flash region n */ +#define SPU_FLASHREGION_PERM_EXECUTE_Enable (0x1UL) /*!< Allow instruction fetches from flash region n */ /* Register: SPU_RAMREGION_PERM */ /* Description: Description cluster: Access permissions for RAM region n */ @@ -8284,32 +8284,32 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 8 : */ #define SPU_RAMREGION_PERM_LOCK_Pos (8UL) /*!< Position of LOCK field. */ #define SPU_RAMREGION_PERM_LOCK_Msk (0x1UL << SPU_RAMREGION_PERM_LOCK_Pos) /*!< Bit mask of LOCK field. */ -#define SPU_RAMREGION_PERM_LOCK_Unlocked (0UL) /*!< This register can be updated */ -#define SPU_RAMREGION_PERM_LOCK_Locked (1UL) /*!< The content of this register can't be changed until the next reset */ +#define SPU_RAMREGION_PERM_LOCK_Unlocked (0x0UL) /*!< This register can be updated */ +#define SPU_RAMREGION_PERM_LOCK_Locked (0x1UL) /*!< The content of this register can't be changed until the next reset */ /* Bit 4 : Security attribute for RAM region n */ #define SPU_RAMREGION_PERM_SECATTR_Pos (4UL) /*!< Position of SECATTR field. */ #define SPU_RAMREGION_PERM_SECATTR_Msk (0x1UL << SPU_RAMREGION_PERM_SECATTR_Pos) /*!< Bit mask of SECATTR field. */ -#define SPU_RAMREGION_PERM_SECATTR_Non_Secure (0UL) /*!< RAM region n security attribute is non-secure */ -#define SPU_RAMREGION_PERM_SECATTR_Secure (1UL) /*!< RAM region n security attribute is secure */ +#define SPU_RAMREGION_PERM_SECATTR_Non_Secure (0x0UL) /*!< RAM region n security attribute is non-secure */ +#define SPU_RAMREGION_PERM_SECATTR_Secure (0x1UL) /*!< RAM region n security attribute is secure */ /* Bit 2 : Configure read permissions for RAM region n */ #define SPU_RAMREGION_PERM_READ_Pos (2UL) /*!< Position of READ field. */ #define SPU_RAMREGION_PERM_READ_Msk (0x1UL << SPU_RAMREGION_PERM_READ_Pos) /*!< Bit mask of READ field. */ -#define SPU_RAMREGION_PERM_READ_Disable (0UL) /*!< Block read operation from RAM region n */ -#define SPU_RAMREGION_PERM_READ_Enable (1UL) /*!< Allow read operation from RAM region n */ +#define SPU_RAMREGION_PERM_READ_Disable (0x0UL) /*!< Block read operation from RAM region n */ +#define SPU_RAMREGION_PERM_READ_Enable (0x1UL) /*!< Allow read operation from RAM region n */ /* Bit 1 : Configure write permission for RAM region n */ #define SPU_RAMREGION_PERM_WRITE_Pos (1UL) /*!< Position of WRITE field. */ #define SPU_RAMREGION_PERM_WRITE_Msk (0x1UL << SPU_RAMREGION_PERM_WRITE_Pos) /*!< Bit mask of WRITE field. */ -#define SPU_RAMREGION_PERM_WRITE_Disable (0UL) /*!< Block write operation to RAM region n */ -#define SPU_RAMREGION_PERM_WRITE_Enable (1UL) /*!< Allow write operation to RAM region n */ +#define SPU_RAMREGION_PERM_WRITE_Disable (0x0UL) /*!< Block write operation to RAM region n */ +#define SPU_RAMREGION_PERM_WRITE_Enable (0x1UL) /*!< Allow write operation to RAM region n */ /* Bit 0 : Configure instruction fetch permissions from RAM region n */ #define SPU_RAMREGION_PERM_EXECUTE_Pos (0UL) /*!< Position of EXECUTE field. */ #define SPU_RAMREGION_PERM_EXECUTE_Msk (0x1UL << SPU_RAMREGION_PERM_EXECUTE_Pos) /*!< Bit mask of EXECUTE field. */ -#define SPU_RAMREGION_PERM_EXECUTE_Disable (0UL) /*!< Block instruction fetches from RAM region n */ -#define SPU_RAMREGION_PERM_EXECUTE_Enable (1UL) /*!< Allow instruction fetches from RAM region n */ +#define SPU_RAMREGION_PERM_EXECUTE_Disable (0x0UL) /*!< Block instruction fetches from RAM region n */ +#define SPU_RAMREGION_PERM_EXECUTE_Enable (0x1UL) /*!< Allow instruction fetches from RAM region n */ /* Register: SPU_PERIPHID_PERM */ /* Description: Description cluster: List capabilities and access permissions for the peripheral with ID n */ @@ -8317,41 +8317,41 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 31 : Indicate if a peripheral is present with ID n */ #define SPU_PERIPHID_PERM_PRESENT_Pos (31UL) /*!< Position of PRESENT field. */ #define SPU_PERIPHID_PERM_PRESENT_Msk (0x1UL << SPU_PERIPHID_PERM_PRESENT_Pos) /*!< Bit mask of PRESENT field. */ -#define SPU_PERIPHID_PERM_PRESENT_NotPresent (0UL) /*!< Peripheral is not present */ -#define SPU_PERIPHID_PERM_PRESENT_IsPresent (1UL) /*!< Peripheral is present */ +#define SPU_PERIPHID_PERM_PRESENT_NotPresent (0x0UL) /*!< Peripheral is not present */ +#define SPU_PERIPHID_PERM_PRESENT_IsPresent (0x1UL) /*!< Peripheral is present */ /* Bit 8 : */ #define SPU_PERIPHID_PERM_LOCK_Pos (8UL) /*!< Position of LOCK field. */ #define SPU_PERIPHID_PERM_LOCK_Msk (0x1UL << SPU_PERIPHID_PERM_LOCK_Pos) /*!< Bit mask of LOCK field. */ -#define SPU_PERIPHID_PERM_LOCK_Unlocked (0UL) /*!< This register can be updated */ -#define SPU_PERIPHID_PERM_LOCK_Locked (1UL) /*!< The content of this register can't be changed until the next reset */ +#define SPU_PERIPHID_PERM_LOCK_Unlocked (0x0UL) /*!< This register can be updated */ +#define SPU_PERIPHID_PERM_LOCK_Locked (0x1UL) /*!< The content of this register can't be changed until the next reset */ /* Bit 5 : Security attribution for the DMA transfer */ #define SPU_PERIPHID_PERM_DMASEC_Pos (5UL) /*!< Position of DMASEC field. */ #define SPU_PERIPHID_PERM_DMASEC_Msk (0x1UL << SPU_PERIPHID_PERM_DMASEC_Pos) /*!< Bit mask of DMASEC field. */ -#define SPU_PERIPHID_PERM_DMASEC_NonSecure (0UL) /*!< DMA transfers initiated by this peripheral have the non-secure attribute set */ -#define SPU_PERIPHID_PERM_DMASEC_Secure (1UL) /*!< DMA transfers initiated by this peripheral have the secure attribute set */ +#define SPU_PERIPHID_PERM_DMASEC_NonSecure (0x0UL) /*!< DMA transfers initiated by this peripheral have the non-secure attribute set */ +#define SPU_PERIPHID_PERM_DMASEC_Secure (0x1UL) /*!< DMA transfers initiated by this peripheral have the secure attribute set */ /* Bit 4 : Peripheral security mapping */ #define SPU_PERIPHID_PERM_SECATTR_Pos (4UL) /*!< Position of SECATTR field. */ #define SPU_PERIPHID_PERM_SECATTR_Msk (0x1UL << SPU_PERIPHID_PERM_SECATTR_Pos) /*!< Bit mask of SECATTR field. */ -#define SPU_PERIPHID_PERM_SECATTR_NonSecure (0UL) /*!< If SECUREMAPPING == UserSelectable: Peripheral is mapped in non-secure peripheral address space. If SECUREMAPPING == Split: Peripheral is mapped in non-secure and secure peripheral address space. */ -#define SPU_PERIPHID_PERM_SECATTR_Secure (1UL) /*!< Peripheral is mapped in secure peripheral address space */ +#define SPU_PERIPHID_PERM_SECATTR_NonSecure (0x0UL) /*!< If SECUREMAPPING == UserSelectable: Peripheral is mapped in non-secure peripheral address space. If SECUREMAPPING == Split: Peripheral is mapped in non-secure and secure peripheral address space. */ +#define SPU_PERIPHID_PERM_SECATTR_Secure (0x1UL) /*!< Peripheral is mapped in secure peripheral address space */ /* Bits 3..2 : Indicate if the peripheral has DMA capabilities and if DMA transfer can be assigned to a different security attribute than the peripheral itself */ #define SPU_PERIPHID_PERM_DMA_Pos (2UL) /*!< Position of DMA field. */ #define SPU_PERIPHID_PERM_DMA_Msk (0x3UL << SPU_PERIPHID_PERM_DMA_Pos) /*!< Bit mask of DMA field. */ -#define SPU_PERIPHID_PERM_DMA_NoDMA (0UL) /*!< Peripheral has no DMA capability */ -#define SPU_PERIPHID_PERM_DMA_NoSeparateAttribute (1UL) /*!< Peripheral has DMA and DMA transfers always have the same security attribute as assigned to the peripheral */ -#define SPU_PERIPHID_PERM_DMA_SeparateAttribute (2UL) /*!< Peripheral has DMA and DMA transfers can have a different security attribute than the one assigned to the peripheral */ +#define SPU_PERIPHID_PERM_DMA_NoDMA (0x0UL) /*!< Peripheral has no DMA capability */ +#define SPU_PERIPHID_PERM_DMA_NoSeparateAttribute (0x1UL) /*!< Peripheral has DMA and DMA transfers always have the same security attribute as assigned to the peripheral */ +#define SPU_PERIPHID_PERM_DMA_SeparateAttribute (0x2UL) /*!< Peripheral has DMA and DMA transfers can have a different security attribute than the one assigned to the peripheral */ /* Bits 1..0 : Define configuration capabilities for TrustZone Cortex-M secure attribute */ #define SPU_PERIPHID_PERM_SECUREMAPPING_Pos (0UL) /*!< Position of SECUREMAPPING field. */ #define SPU_PERIPHID_PERM_SECUREMAPPING_Msk (0x3UL << SPU_PERIPHID_PERM_SECUREMAPPING_Pos) /*!< Bit mask of SECUREMAPPING field. */ -#define SPU_PERIPHID_PERM_SECUREMAPPING_NonSecure (0UL) /*!< This peripheral is always accessible as a non-secure peripheral */ -#define SPU_PERIPHID_PERM_SECUREMAPPING_Secure (1UL) /*!< This peripheral is always accessible as a secure peripheral */ -#define SPU_PERIPHID_PERM_SECUREMAPPING_UserSelectable (2UL) /*!< Non-secure or secure attribute for this peripheral is defined by the PERIPHID[n].PERM register */ -#define SPU_PERIPHID_PERM_SECUREMAPPING_Split (3UL) /*!< This peripheral implements the split security mechanism. Non-secure or secure attribute for this peripheral is defined by the PERIPHID[n].PERM register. */ +#define SPU_PERIPHID_PERM_SECUREMAPPING_NonSecure (0x0UL) /*!< This peripheral is always accessible as a non-secure peripheral */ +#define SPU_PERIPHID_PERM_SECUREMAPPING_Secure (0x1UL) /*!< This peripheral is always accessible as a secure peripheral */ +#define SPU_PERIPHID_PERM_SECUREMAPPING_UserSelectable (0x2UL) /*!< Non-secure or secure attribute for this peripheral is defined by the PERIPHID[n].PERM register */ +#define SPU_PERIPHID_PERM_SECUREMAPPING_Split (0x3UL) /*!< This peripheral implements the split security mechanism. Non-secure or secure attribute for this peripheral is defined by the PERIPHID[n].PERM register. */ /* Peripheral: TAD */ @@ -8363,7 +8363,7 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 0 : Start all trace and debug clocks. */ #define TAD_TASKS_CLOCKSTART_TASKS_CLOCKSTART_Pos (0UL) /*!< Position of TASKS_CLOCKSTART field. */ #define TAD_TASKS_CLOCKSTART_TASKS_CLOCKSTART_Msk (0x1UL << TAD_TASKS_CLOCKSTART_TASKS_CLOCKSTART_Pos) /*!< Bit mask of TASKS_CLOCKSTART field. */ -#define TAD_TASKS_CLOCKSTART_TASKS_CLOCKSTART_Trigger (1UL) /*!< Trigger task */ +#define TAD_TASKS_CLOCKSTART_TASKS_CLOCKSTART_Trigger (0x1UL) /*!< Trigger task */ /* Register: TAD_TASKS_CLOCKSTOP */ /* Description: Stop all trace and debug clocks. */ @@ -8371,7 +8371,7 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 0 : Stop all trace and debug clocks. */ #define TAD_TASKS_CLOCKSTOP_TASKS_CLOCKSTOP_Pos (0UL) /*!< Position of TASKS_CLOCKSTOP field. */ #define TAD_TASKS_CLOCKSTOP_TASKS_CLOCKSTOP_Msk (0x1UL << TAD_TASKS_CLOCKSTOP_TASKS_CLOCKSTOP_Pos) /*!< Bit mask of TASKS_CLOCKSTOP field. */ -#define TAD_TASKS_CLOCKSTOP_TASKS_CLOCKSTOP_Trigger (1UL) /*!< Trigger task */ +#define TAD_TASKS_CLOCKSTOP_TASKS_CLOCKSTOP_Trigger (0x1UL) /*!< Trigger task */ /* Register: TAD_ENABLE */ /* Description: Enable debug domain and aquire selected GPIOs */ @@ -8379,8 +8379,8 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 0 : */ #define TAD_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ #define TAD_ENABLE_ENABLE_Msk (0x1UL << TAD_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ -#define TAD_ENABLE_ENABLE_DISABLED (0UL) /*!< Disable debug domain and release selected GPIOs */ -#define TAD_ENABLE_ENABLE_ENABLED (1UL) /*!< Enable debug domain and aquire selected GPIOs */ +#define TAD_ENABLE_ENABLE_DISABLED (0x0UL) /*!< Disable debug domain and release selected GPIOs */ +#define TAD_ENABLE_ENABLE_ENABLED (0x1UL) /*!< Enable debug domain and aquire selected GPIOs */ /* Register: TAD_PSEL_TRACECLK */ /* Description: Pin configuration for TRACECLK */ @@ -8388,13 +8388,13 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 31 : Connection */ #define TAD_PSEL_TRACECLK_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ #define TAD_PSEL_TRACECLK_CONNECT_Msk (0x1UL << TAD_PSEL_TRACECLK_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ -#define TAD_PSEL_TRACECLK_CONNECT_Connected (0UL) /*!< Connect */ -#define TAD_PSEL_TRACECLK_CONNECT_Disconnected (1UL) /*!< Disconnect */ +#define TAD_PSEL_TRACECLK_CONNECT_Connected (0x0UL) /*!< Connect */ +#define TAD_PSEL_TRACECLK_CONNECT_Disconnected (0x1UL) /*!< Disconnect */ /* Bits 4..0 : Pin number */ #define TAD_PSEL_TRACECLK_PIN_Pos (0UL) /*!< Position of PIN field. */ #define TAD_PSEL_TRACECLK_PIN_Msk (0x1FUL << TAD_PSEL_TRACECLK_PIN_Pos) /*!< Bit mask of PIN field. */ -#define TAD_PSEL_TRACECLK_PIN_Traceclk (21UL) /*!< TRACECLK pin */ +#define TAD_PSEL_TRACECLK_PIN_Traceclk (0x15UL) /*!< TRACECLK pin */ /* Register: TAD_PSEL_TRACEDATA0 */ /* Description: Pin configuration for TRACEDATA[0] */ @@ -8402,13 +8402,13 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 31 : Connection */ #define TAD_PSEL_TRACEDATA0_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ #define TAD_PSEL_TRACEDATA0_CONNECT_Msk (0x1UL << TAD_PSEL_TRACEDATA0_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ -#define TAD_PSEL_TRACEDATA0_CONNECT_Connected (0UL) /*!< Connect */ -#define TAD_PSEL_TRACEDATA0_CONNECT_Disconnected (1UL) /*!< Disconnect */ +#define TAD_PSEL_TRACEDATA0_CONNECT_Connected (0x0UL) /*!< Connect */ +#define TAD_PSEL_TRACEDATA0_CONNECT_Disconnected (0x1UL) /*!< Disconnect */ /* Bits 4..0 : Pin number */ #define TAD_PSEL_TRACEDATA0_PIN_Pos (0UL) /*!< Position of PIN field. */ #define TAD_PSEL_TRACEDATA0_PIN_Msk (0x1FUL << TAD_PSEL_TRACEDATA0_PIN_Pos) /*!< Bit mask of PIN field. */ -#define TAD_PSEL_TRACEDATA0_PIN_Tracedata0 (22UL) /*!< TRACEDATA0 pin */ +#define TAD_PSEL_TRACEDATA0_PIN_Tracedata0 (0x16UL) /*!< TRACEDATA0 pin */ /* Register: TAD_PSEL_TRACEDATA1 */ /* Description: Pin configuration for TRACEDATA[1] */ @@ -8416,13 +8416,13 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 31 : Connection */ #define TAD_PSEL_TRACEDATA1_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ #define TAD_PSEL_TRACEDATA1_CONNECT_Msk (0x1UL << TAD_PSEL_TRACEDATA1_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ -#define TAD_PSEL_TRACEDATA1_CONNECT_Connected (0UL) /*!< Connect */ -#define TAD_PSEL_TRACEDATA1_CONNECT_Disconnected (1UL) /*!< Disconnect */ +#define TAD_PSEL_TRACEDATA1_CONNECT_Connected (0x0UL) /*!< Connect */ +#define TAD_PSEL_TRACEDATA1_CONNECT_Disconnected (0x1UL) /*!< Disconnect */ /* Bits 4..0 : Pin number */ #define TAD_PSEL_TRACEDATA1_PIN_Pos (0UL) /*!< Position of PIN field. */ #define TAD_PSEL_TRACEDATA1_PIN_Msk (0x1FUL << TAD_PSEL_TRACEDATA1_PIN_Pos) /*!< Bit mask of PIN field. */ -#define TAD_PSEL_TRACEDATA1_PIN_Tracedata1 (23UL) /*!< TRACEDATA1 pin */ +#define TAD_PSEL_TRACEDATA1_PIN_Tracedata1 (0x17UL) /*!< TRACEDATA1 pin */ /* Register: TAD_PSEL_TRACEDATA2 */ /* Description: Pin configuration for TRACEDATA[2] */ @@ -8430,13 +8430,13 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 31 : Connection */ #define TAD_PSEL_TRACEDATA2_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ #define TAD_PSEL_TRACEDATA2_CONNECT_Msk (0x1UL << TAD_PSEL_TRACEDATA2_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ -#define TAD_PSEL_TRACEDATA2_CONNECT_Connected (0UL) /*!< Connect */ -#define TAD_PSEL_TRACEDATA2_CONNECT_Disconnected (1UL) /*!< Disconnect */ +#define TAD_PSEL_TRACEDATA2_CONNECT_Connected (0x0UL) /*!< Connect */ +#define TAD_PSEL_TRACEDATA2_CONNECT_Disconnected (0x1UL) /*!< Disconnect */ /* Bits 4..0 : Pin number */ #define TAD_PSEL_TRACEDATA2_PIN_Pos (0UL) /*!< Position of PIN field. */ #define TAD_PSEL_TRACEDATA2_PIN_Msk (0x1FUL << TAD_PSEL_TRACEDATA2_PIN_Pos) /*!< Bit mask of PIN field. */ -#define TAD_PSEL_TRACEDATA2_PIN_Tracedata2 (24UL) /*!< TRACEDATA2 pin */ +#define TAD_PSEL_TRACEDATA2_PIN_Tracedata2 (0x18UL) /*!< TRACEDATA2 pin */ /* Register: TAD_PSEL_TRACEDATA3 */ /* Description: Pin configuration for TRACEDATA[3] */ @@ -8444,13 +8444,13 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 31 : Connection */ #define TAD_PSEL_TRACEDATA3_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ #define TAD_PSEL_TRACEDATA3_CONNECT_Msk (0x1UL << TAD_PSEL_TRACEDATA3_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ -#define TAD_PSEL_TRACEDATA3_CONNECT_Connected (0UL) /*!< Connect */ -#define TAD_PSEL_TRACEDATA3_CONNECT_Disconnected (1UL) /*!< Disconnect */ +#define TAD_PSEL_TRACEDATA3_CONNECT_Connected (0x0UL) /*!< Connect */ +#define TAD_PSEL_TRACEDATA3_CONNECT_Disconnected (0x1UL) /*!< Disconnect */ /* Bits 4..0 : Pin number */ #define TAD_PSEL_TRACEDATA3_PIN_Pos (0UL) /*!< Position of PIN field. */ #define TAD_PSEL_TRACEDATA3_PIN_Msk (0x1FUL << TAD_PSEL_TRACEDATA3_PIN_Pos) /*!< Bit mask of PIN field. */ -#define TAD_PSEL_TRACEDATA3_PIN_Tracedata3 (25UL) /*!< TRACEDATA3 pin */ +#define TAD_PSEL_TRACEDATA3_PIN_Tracedata3 (0x19UL) /*!< TRACEDATA3 pin */ /* Register: TAD_TRACEPORTSPEED */ /* Description: Clocking options for the Trace Port debug interface Reset behavior is the same as debug components */ @@ -8458,10 +8458,10 @@ POSSIBILITY OF SUCH DAMAGE. /* Bits 1..0 : Speed of Trace Port clock. Note that the TRACECLK pin output will be divided again by two from the Trace Port clock. */ #define TAD_TRACEPORTSPEED_TRACEPORTSPEED_Pos (0UL) /*!< Position of TRACEPORTSPEED field. */ #define TAD_TRACEPORTSPEED_TRACEPORTSPEED_Msk (0x3UL << TAD_TRACEPORTSPEED_TRACEPORTSPEED_Pos) /*!< Bit mask of TRACEPORTSPEED field. */ -#define TAD_TRACEPORTSPEED_TRACEPORTSPEED_32MHz (0UL) /*!< Trace Port clock is: 32MHz */ -#define TAD_TRACEPORTSPEED_TRACEPORTSPEED_16MHz (1UL) /*!< Trace Port clock is: 16MHz */ -#define TAD_TRACEPORTSPEED_TRACEPORTSPEED_8MHz (2UL) /*!< Trace Port clock is: 8MHz */ -#define TAD_TRACEPORTSPEED_TRACEPORTSPEED_4MHz (3UL) /*!< Trace Port clock is: 4MHz */ +#define TAD_TRACEPORTSPEED_TRACEPORTSPEED_32MHz (0x0UL) /*!< Trace Port clock is: 32MHz */ +#define TAD_TRACEPORTSPEED_TRACEPORTSPEED_16MHz (0x1UL) /*!< Trace Port clock is: 16MHz */ +#define TAD_TRACEPORTSPEED_TRACEPORTSPEED_8MHz (0x2UL) /*!< Trace Port clock is: 8MHz */ +#define TAD_TRACEPORTSPEED_TRACEPORTSPEED_4MHz (0x3UL) /*!< Trace Port clock is: 4MHz */ /* Peripheral: TIMER */ @@ -8473,7 +8473,7 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 0 : Start Timer */ #define TIMER_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */ #define TIMER_TASKS_START_TASKS_START_Msk (0x1UL << TIMER_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */ -#define TIMER_TASKS_START_TASKS_START_Trigger (1UL) /*!< Trigger task */ +#define TIMER_TASKS_START_TASKS_START_Trigger (0x1UL) /*!< Trigger task */ /* Register: TIMER_TASKS_STOP */ /* Description: Stop Timer */ @@ -8481,7 +8481,7 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 0 : Stop Timer */ #define TIMER_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */ #define TIMER_TASKS_STOP_TASKS_STOP_Msk (0x1UL << TIMER_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */ -#define TIMER_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */ +#define TIMER_TASKS_STOP_TASKS_STOP_Trigger (0x1UL) /*!< Trigger task */ /* Register: TIMER_TASKS_COUNT */ /* Description: Increment Timer (Counter mode only) */ @@ -8489,7 +8489,7 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 0 : Increment Timer (Counter mode only) */ #define TIMER_TASKS_COUNT_TASKS_COUNT_Pos (0UL) /*!< Position of TASKS_COUNT field. */ #define TIMER_TASKS_COUNT_TASKS_COUNT_Msk (0x1UL << TIMER_TASKS_COUNT_TASKS_COUNT_Pos) /*!< Bit mask of TASKS_COUNT field. */ -#define TIMER_TASKS_COUNT_TASKS_COUNT_Trigger (1UL) /*!< Trigger task */ +#define TIMER_TASKS_COUNT_TASKS_COUNT_Trigger (0x1UL) /*!< Trigger task */ /* Register: TIMER_TASKS_CLEAR */ /* Description: Clear time */ @@ -8497,7 +8497,7 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 0 : Clear time */ #define TIMER_TASKS_CLEAR_TASKS_CLEAR_Pos (0UL) /*!< Position of TASKS_CLEAR field. */ #define TIMER_TASKS_CLEAR_TASKS_CLEAR_Msk (0x1UL << TIMER_TASKS_CLEAR_TASKS_CLEAR_Pos) /*!< Bit mask of TASKS_CLEAR field. */ -#define TIMER_TASKS_CLEAR_TASKS_CLEAR_Trigger (1UL) /*!< Trigger task */ +#define TIMER_TASKS_CLEAR_TASKS_CLEAR_Trigger (0x1UL) /*!< Trigger task */ /* Register: TIMER_TASKS_SHUTDOWN */ /* Description: Deprecated register - Shut down timer */ @@ -8505,7 +8505,7 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 0 : Deprecated field - Shut down timer */ #define TIMER_TASKS_SHUTDOWN_TASKS_SHUTDOWN_Pos (0UL) /*!< Position of TASKS_SHUTDOWN field. */ #define TIMER_TASKS_SHUTDOWN_TASKS_SHUTDOWN_Msk (0x1UL << TIMER_TASKS_SHUTDOWN_TASKS_SHUTDOWN_Pos) /*!< Bit mask of TASKS_SHUTDOWN field. */ -#define TIMER_TASKS_SHUTDOWN_TASKS_SHUTDOWN_Trigger (1UL) /*!< Trigger task */ +#define TIMER_TASKS_SHUTDOWN_TASKS_SHUTDOWN_Trigger (0x1UL) /*!< Trigger task */ /* Register: TIMER_TASKS_CAPTURE */ /* Description: Description collection: Capture Timer value to CC[n] register */ @@ -8513,7 +8513,7 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 0 : Capture Timer value to CC[n] register */ #define TIMER_TASKS_CAPTURE_TASKS_CAPTURE_Pos (0UL) /*!< Position of TASKS_CAPTURE field. */ #define TIMER_TASKS_CAPTURE_TASKS_CAPTURE_Msk (0x1UL << TIMER_TASKS_CAPTURE_TASKS_CAPTURE_Pos) /*!< Bit mask of TASKS_CAPTURE field. */ -#define TIMER_TASKS_CAPTURE_TASKS_CAPTURE_Trigger (1UL) /*!< Trigger task */ +#define TIMER_TASKS_CAPTURE_TASKS_CAPTURE_Trigger (0x1UL) /*!< Trigger task */ /* Register: TIMER_SUBSCRIBE_START */ /* Description: Subscribe configuration for task START */ @@ -8521,8 +8521,8 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 31 : */ #define TIMER_SUBSCRIBE_START_EN_Pos (31UL) /*!< Position of EN field. */ #define TIMER_SUBSCRIBE_START_EN_Msk (0x1UL << TIMER_SUBSCRIBE_START_EN_Pos) /*!< Bit mask of EN field. */ -#define TIMER_SUBSCRIBE_START_EN_Disabled (0UL) /*!< Disable subscription */ -#define TIMER_SUBSCRIBE_START_EN_Enabled (1UL) /*!< Enable subscription */ +#define TIMER_SUBSCRIBE_START_EN_Disabled (0x0UL) /*!< Disable subscription */ +#define TIMER_SUBSCRIBE_START_EN_Enabled (0x1UL) /*!< Enable subscription */ /* Bits 7..0 : DPPI channel that task START will subscribe to */ #define TIMER_SUBSCRIBE_START_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ @@ -8534,8 +8534,8 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 31 : */ #define TIMER_SUBSCRIBE_STOP_EN_Pos (31UL) /*!< Position of EN field. */ #define TIMER_SUBSCRIBE_STOP_EN_Msk (0x1UL << TIMER_SUBSCRIBE_STOP_EN_Pos) /*!< Bit mask of EN field. */ -#define TIMER_SUBSCRIBE_STOP_EN_Disabled (0UL) /*!< Disable subscription */ -#define TIMER_SUBSCRIBE_STOP_EN_Enabled (1UL) /*!< Enable subscription */ +#define TIMER_SUBSCRIBE_STOP_EN_Disabled (0x0UL) /*!< Disable subscription */ +#define TIMER_SUBSCRIBE_STOP_EN_Enabled (0x1UL) /*!< Enable subscription */ /* Bits 7..0 : DPPI channel that task STOP will subscribe to */ #define TIMER_SUBSCRIBE_STOP_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ @@ -8547,8 +8547,8 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 31 : */ #define TIMER_SUBSCRIBE_COUNT_EN_Pos (31UL) /*!< Position of EN field. */ #define TIMER_SUBSCRIBE_COUNT_EN_Msk (0x1UL << TIMER_SUBSCRIBE_COUNT_EN_Pos) /*!< Bit mask of EN field. */ -#define TIMER_SUBSCRIBE_COUNT_EN_Disabled (0UL) /*!< Disable subscription */ -#define TIMER_SUBSCRIBE_COUNT_EN_Enabled (1UL) /*!< Enable subscription */ +#define TIMER_SUBSCRIBE_COUNT_EN_Disabled (0x0UL) /*!< Disable subscription */ +#define TIMER_SUBSCRIBE_COUNT_EN_Enabled (0x1UL) /*!< Enable subscription */ /* Bits 7..0 : DPPI channel that task COUNT will subscribe to */ #define TIMER_SUBSCRIBE_COUNT_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ @@ -8560,8 +8560,8 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 31 : */ #define TIMER_SUBSCRIBE_CLEAR_EN_Pos (31UL) /*!< Position of EN field. */ #define TIMER_SUBSCRIBE_CLEAR_EN_Msk (0x1UL << TIMER_SUBSCRIBE_CLEAR_EN_Pos) /*!< Bit mask of EN field. */ -#define TIMER_SUBSCRIBE_CLEAR_EN_Disabled (0UL) /*!< Disable subscription */ -#define TIMER_SUBSCRIBE_CLEAR_EN_Enabled (1UL) /*!< Enable subscription */ +#define TIMER_SUBSCRIBE_CLEAR_EN_Disabled (0x0UL) /*!< Disable subscription */ +#define TIMER_SUBSCRIBE_CLEAR_EN_Enabled (0x1UL) /*!< Enable subscription */ /* Bits 7..0 : DPPI channel that task CLEAR will subscribe to */ #define TIMER_SUBSCRIBE_CLEAR_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ @@ -8573,8 +8573,8 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 31 : */ #define TIMER_SUBSCRIBE_SHUTDOWN_EN_Pos (31UL) /*!< Position of EN field. */ #define TIMER_SUBSCRIBE_SHUTDOWN_EN_Msk (0x1UL << TIMER_SUBSCRIBE_SHUTDOWN_EN_Pos) /*!< Bit mask of EN field. */ -#define TIMER_SUBSCRIBE_SHUTDOWN_EN_Disabled (0UL) /*!< Disable subscription */ -#define TIMER_SUBSCRIBE_SHUTDOWN_EN_Enabled (1UL) /*!< Enable subscription */ +#define TIMER_SUBSCRIBE_SHUTDOWN_EN_Disabled (0x0UL) /*!< Disable subscription */ +#define TIMER_SUBSCRIBE_SHUTDOWN_EN_Enabled (0x1UL) /*!< Enable subscription */ /* Bits 7..0 : DPPI channel that task SHUTDOWN will subscribe to */ #define TIMER_SUBSCRIBE_SHUTDOWN_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ @@ -8586,8 +8586,8 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 31 : */ #define TIMER_SUBSCRIBE_CAPTURE_EN_Pos (31UL) /*!< Position of EN field. */ #define TIMER_SUBSCRIBE_CAPTURE_EN_Msk (0x1UL << TIMER_SUBSCRIBE_CAPTURE_EN_Pos) /*!< Bit mask of EN field. */ -#define TIMER_SUBSCRIBE_CAPTURE_EN_Disabled (0UL) /*!< Disable subscription */ -#define TIMER_SUBSCRIBE_CAPTURE_EN_Enabled (1UL) /*!< Enable subscription */ +#define TIMER_SUBSCRIBE_CAPTURE_EN_Disabled (0x0UL) /*!< Disable subscription */ +#define TIMER_SUBSCRIBE_CAPTURE_EN_Enabled (0x1UL) /*!< Enable subscription */ /* Bits 7..0 : DPPI channel that task CAPTURE[n] will subscribe to */ #define TIMER_SUBSCRIBE_CAPTURE_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ @@ -8599,8 +8599,8 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 0 : Compare event on CC[n] match */ #define TIMER_EVENTS_COMPARE_EVENTS_COMPARE_Pos (0UL) /*!< Position of EVENTS_COMPARE field. */ #define TIMER_EVENTS_COMPARE_EVENTS_COMPARE_Msk (0x1UL << TIMER_EVENTS_COMPARE_EVENTS_COMPARE_Pos) /*!< Bit mask of EVENTS_COMPARE field. */ -#define TIMER_EVENTS_COMPARE_EVENTS_COMPARE_NotGenerated (0UL) /*!< Event not generated */ -#define TIMER_EVENTS_COMPARE_EVENTS_COMPARE_Generated (1UL) /*!< Event generated */ +#define TIMER_EVENTS_COMPARE_EVENTS_COMPARE_NotGenerated (0x0UL) /*!< Event not generated */ +#define TIMER_EVENTS_COMPARE_EVENTS_COMPARE_Generated (0x1UL) /*!< Event generated */ /* Register: TIMER_PUBLISH_COMPARE */ /* Description: Description collection: Publish configuration for event COMPARE[n] */ @@ -8608,8 +8608,8 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 31 : */ #define TIMER_PUBLISH_COMPARE_EN_Pos (31UL) /*!< Position of EN field. */ #define TIMER_PUBLISH_COMPARE_EN_Msk (0x1UL << TIMER_PUBLISH_COMPARE_EN_Pos) /*!< Bit mask of EN field. */ -#define TIMER_PUBLISH_COMPARE_EN_Disabled (0UL) /*!< Disable publishing */ -#define TIMER_PUBLISH_COMPARE_EN_Enabled (1UL) /*!< Enable publishing */ +#define TIMER_PUBLISH_COMPARE_EN_Disabled (0x0UL) /*!< Disable publishing */ +#define TIMER_PUBLISH_COMPARE_EN_Enabled (0x1UL) /*!< Enable publishing */ /* Bits 7..0 : DPPI channel that event COMPARE[n] will publish to */ #define TIMER_PUBLISH_COMPARE_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ @@ -8621,74 +8621,74 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 13 : Shortcut between event COMPARE[5] and task STOP */ #define TIMER_SHORTS_COMPARE5_STOP_Pos (13UL) /*!< Position of COMPARE5_STOP field. */ #define TIMER_SHORTS_COMPARE5_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE5_STOP_Pos) /*!< Bit mask of COMPARE5_STOP field. */ -#define TIMER_SHORTS_COMPARE5_STOP_Disabled (0UL) /*!< Disable shortcut */ -#define TIMER_SHORTS_COMPARE5_STOP_Enabled (1UL) /*!< Enable shortcut */ +#define TIMER_SHORTS_COMPARE5_STOP_Disabled (0x0UL) /*!< Disable shortcut */ +#define TIMER_SHORTS_COMPARE5_STOP_Enabled (0x1UL) /*!< Enable shortcut */ /* Bit 12 : Shortcut between event COMPARE[4] and task STOP */ #define TIMER_SHORTS_COMPARE4_STOP_Pos (12UL) /*!< Position of COMPARE4_STOP field. */ #define TIMER_SHORTS_COMPARE4_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE4_STOP_Pos) /*!< Bit mask of COMPARE4_STOP field. */ -#define TIMER_SHORTS_COMPARE4_STOP_Disabled (0UL) /*!< Disable shortcut */ -#define TIMER_SHORTS_COMPARE4_STOP_Enabled (1UL) /*!< Enable shortcut */ +#define TIMER_SHORTS_COMPARE4_STOP_Disabled (0x0UL) /*!< Disable shortcut */ +#define TIMER_SHORTS_COMPARE4_STOP_Enabled (0x1UL) /*!< Enable shortcut */ /* Bit 11 : Shortcut between event COMPARE[3] and task STOP */ #define TIMER_SHORTS_COMPARE3_STOP_Pos (11UL) /*!< Position of COMPARE3_STOP field. */ #define TIMER_SHORTS_COMPARE3_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE3_STOP_Pos) /*!< Bit mask of COMPARE3_STOP field. */ -#define TIMER_SHORTS_COMPARE3_STOP_Disabled (0UL) /*!< Disable shortcut */ -#define TIMER_SHORTS_COMPARE3_STOP_Enabled (1UL) /*!< Enable shortcut */ +#define TIMER_SHORTS_COMPARE3_STOP_Disabled (0x0UL) /*!< Disable shortcut */ +#define TIMER_SHORTS_COMPARE3_STOP_Enabled (0x1UL) /*!< Enable shortcut */ /* Bit 10 : Shortcut between event COMPARE[2] and task STOP */ #define TIMER_SHORTS_COMPARE2_STOP_Pos (10UL) /*!< Position of COMPARE2_STOP field. */ #define TIMER_SHORTS_COMPARE2_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE2_STOP_Pos) /*!< Bit mask of COMPARE2_STOP field. */ -#define TIMER_SHORTS_COMPARE2_STOP_Disabled (0UL) /*!< Disable shortcut */ -#define TIMER_SHORTS_COMPARE2_STOP_Enabled (1UL) /*!< Enable shortcut */ +#define TIMER_SHORTS_COMPARE2_STOP_Disabled (0x0UL) /*!< Disable shortcut */ +#define TIMER_SHORTS_COMPARE2_STOP_Enabled (0x1UL) /*!< Enable shortcut */ /* Bit 9 : Shortcut between event COMPARE[1] and task STOP */ #define TIMER_SHORTS_COMPARE1_STOP_Pos (9UL) /*!< Position of COMPARE1_STOP field. */ #define TIMER_SHORTS_COMPARE1_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE1_STOP_Pos) /*!< Bit mask of COMPARE1_STOP field. */ -#define TIMER_SHORTS_COMPARE1_STOP_Disabled (0UL) /*!< Disable shortcut */ -#define TIMER_SHORTS_COMPARE1_STOP_Enabled (1UL) /*!< Enable shortcut */ +#define TIMER_SHORTS_COMPARE1_STOP_Disabled (0x0UL) /*!< Disable shortcut */ +#define TIMER_SHORTS_COMPARE1_STOP_Enabled (0x1UL) /*!< Enable shortcut */ /* Bit 8 : Shortcut between event COMPARE[0] and task STOP */ #define TIMER_SHORTS_COMPARE0_STOP_Pos (8UL) /*!< Position of COMPARE0_STOP field. */ #define TIMER_SHORTS_COMPARE0_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE0_STOP_Pos) /*!< Bit mask of COMPARE0_STOP field. */ -#define TIMER_SHORTS_COMPARE0_STOP_Disabled (0UL) /*!< Disable shortcut */ -#define TIMER_SHORTS_COMPARE0_STOP_Enabled (1UL) /*!< Enable shortcut */ +#define TIMER_SHORTS_COMPARE0_STOP_Disabled (0x0UL) /*!< Disable shortcut */ +#define TIMER_SHORTS_COMPARE0_STOP_Enabled (0x1UL) /*!< Enable shortcut */ /* Bit 5 : Shortcut between event COMPARE[5] and task CLEAR */ #define TIMER_SHORTS_COMPARE5_CLEAR_Pos (5UL) /*!< Position of COMPARE5_CLEAR field. */ #define TIMER_SHORTS_COMPARE5_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE5_CLEAR_Pos) /*!< Bit mask of COMPARE5_CLEAR field. */ -#define TIMER_SHORTS_COMPARE5_CLEAR_Disabled (0UL) /*!< Disable shortcut */ -#define TIMER_SHORTS_COMPARE5_CLEAR_Enabled (1UL) /*!< Enable shortcut */ +#define TIMER_SHORTS_COMPARE5_CLEAR_Disabled (0x0UL) /*!< Disable shortcut */ +#define TIMER_SHORTS_COMPARE5_CLEAR_Enabled (0x1UL) /*!< Enable shortcut */ /* Bit 4 : Shortcut between event COMPARE[4] and task CLEAR */ #define TIMER_SHORTS_COMPARE4_CLEAR_Pos (4UL) /*!< Position of COMPARE4_CLEAR field. */ #define TIMER_SHORTS_COMPARE4_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE4_CLEAR_Pos) /*!< Bit mask of COMPARE4_CLEAR field. */ -#define TIMER_SHORTS_COMPARE4_CLEAR_Disabled (0UL) /*!< Disable shortcut */ -#define TIMER_SHORTS_COMPARE4_CLEAR_Enabled (1UL) /*!< Enable shortcut */ +#define TIMER_SHORTS_COMPARE4_CLEAR_Disabled (0x0UL) /*!< Disable shortcut */ +#define TIMER_SHORTS_COMPARE4_CLEAR_Enabled (0x1UL) /*!< Enable shortcut */ /* Bit 3 : Shortcut between event COMPARE[3] and task CLEAR */ #define TIMER_SHORTS_COMPARE3_CLEAR_Pos (3UL) /*!< Position of COMPARE3_CLEAR field. */ #define TIMER_SHORTS_COMPARE3_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE3_CLEAR_Pos) /*!< Bit mask of COMPARE3_CLEAR field. */ -#define TIMER_SHORTS_COMPARE3_CLEAR_Disabled (0UL) /*!< Disable shortcut */ -#define TIMER_SHORTS_COMPARE3_CLEAR_Enabled (1UL) /*!< Enable shortcut */ +#define TIMER_SHORTS_COMPARE3_CLEAR_Disabled (0x0UL) /*!< Disable shortcut */ +#define TIMER_SHORTS_COMPARE3_CLEAR_Enabled (0x1UL) /*!< Enable shortcut */ /* Bit 2 : Shortcut between event COMPARE[2] and task CLEAR */ #define TIMER_SHORTS_COMPARE2_CLEAR_Pos (2UL) /*!< Position of COMPARE2_CLEAR field. */ #define TIMER_SHORTS_COMPARE2_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE2_CLEAR_Pos) /*!< Bit mask of COMPARE2_CLEAR field. */ -#define TIMER_SHORTS_COMPARE2_CLEAR_Disabled (0UL) /*!< Disable shortcut */ -#define TIMER_SHORTS_COMPARE2_CLEAR_Enabled (1UL) /*!< Enable shortcut */ +#define TIMER_SHORTS_COMPARE2_CLEAR_Disabled (0x0UL) /*!< Disable shortcut */ +#define TIMER_SHORTS_COMPARE2_CLEAR_Enabled (0x1UL) /*!< Enable shortcut */ /* Bit 1 : Shortcut between event COMPARE[1] and task CLEAR */ #define TIMER_SHORTS_COMPARE1_CLEAR_Pos (1UL) /*!< Position of COMPARE1_CLEAR field. */ #define TIMER_SHORTS_COMPARE1_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE1_CLEAR_Pos) /*!< Bit mask of COMPARE1_CLEAR field. */ -#define TIMER_SHORTS_COMPARE1_CLEAR_Disabled (0UL) /*!< Disable shortcut */ -#define TIMER_SHORTS_COMPARE1_CLEAR_Enabled (1UL) /*!< Enable shortcut */ +#define TIMER_SHORTS_COMPARE1_CLEAR_Disabled (0x0UL) /*!< Disable shortcut */ +#define TIMER_SHORTS_COMPARE1_CLEAR_Enabled (0x1UL) /*!< Enable shortcut */ /* Bit 0 : Shortcut between event COMPARE[0] and task CLEAR */ #define TIMER_SHORTS_COMPARE0_CLEAR_Pos (0UL) /*!< Position of COMPARE0_CLEAR field. */ #define TIMER_SHORTS_COMPARE0_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE0_CLEAR_Pos) /*!< Bit mask of COMPARE0_CLEAR field. */ -#define TIMER_SHORTS_COMPARE0_CLEAR_Disabled (0UL) /*!< Disable shortcut */ -#define TIMER_SHORTS_COMPARE0_CLEAR_Enabled (1UL) /*!< Enable shortcut */ +#define TIMER_SHORTS_COMPARE0_CLEAR_Disabled (0x0UL) /*!< Disable shortcut */ +#define TIMER_SHORTS_COMPARE0_CLEAR_Enabled (0x1UL) /*!< Enable shortcut */ /* Register: TIMER_INTENSET */ /* Description: Enable interrupt */ @@ -8696,44 +8696,44 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 21 : Write '1' to enable interrupt for event COMPARE[5] */ #define TIMER_INTENSET_COMPARE5_Pos (21UL) /*!< Position of COMPARE5 field. */ #define TIMER_INTENSET_COMPARE5_Msk (0x1UL << TIMER_INTENSET_COMPARE5_Pos) /*!< Bit mask of COMPARE5 field. */ -#define TIMER_INTENSET_COMPARE5_Disabled (0UL) /*!< Read: Disabled */ -#define TIMER_INTENSET_COMPARE5_Enabled (1UL) /*!< Read: Enabled */ -#define TIMER_INTENSET_COMPARE5_Set (1UL) /*!< Enable */ +#define TIMER_INTENSET_COMPARE5_Disabled (0x0UL) /*!< Read: Disabled */ +#define TIMER_INTENSET_COMPARE5_Enabled (0x1UL) /*!< Read: Enabled */ +#define TIMER_INTENSET_COMPARE5_Set (0x1UL) /*!< Enable */ /* Bit 20 : Write '1' to enable interrupt for event COMPARE[4] */ #define TIMER_INTENSET_COMPARE4_Pos (20UL) /*!< Position of COMPARE4 field. */ #define TIMER_INTENSET_COMPARE4_Msk (0x1UL << TIMER_INTENSET_COMPARE4_Pos) /*!< Bit mask of COMPARE4 field. */ -#define TIMER_INTENSET_COMPARE4_Disabled (0UL) /*!< Read: Disabled */ -#define TIMER_INTENSET_COMPARE4_Enabled (1UL) /*!< Read: Enabled */ -#define TIMER_INTENSET_COMPARE4_Set (1UL) /*!< Enable */ +#define TIMER_INTENSET_COMPARE4_Disabled (0x0UL) /*!< Read: Disabled */ +#define TIMER_INTENSET_COMPARE4_Enabled (0x1UL) /*!< Read: Enabled */ +#define TIMER_INTENSET_COMPARE4_Set (0x1UL) /*!< Enable */ /* Bit 19 : Write '1' to enable interrupt for event COMPARE[3] */ #define TIMER_INTENSET_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */ #define TIMER_INTENSET_COMPARE3_Msk (0x1UL << TIMER_INTENSET_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */ -#define TIMER_INTENSET_COMPARE3_Disabled (0UL) /*!< Read: Disabled */ -#define TIMER_INTENSET_COMPARE3_Enabled (1UL) /*!< Read: Enabled */ -#define TIMER_INTENSET_COMPARE3_Set (1UL) /*!< Enable */ +#define TIMER_INTENSET_COMPARE3_Disabled (0x0UL) /*!< Read: Disabled */ +#define TIMER_INTENSET_COMPARE3_Enabled (0x1UL) /*!< Read: Enabled */ +#define TIMER_INTENSET_COMPARE3_Set (0x1UL) /*!< Enable */ /* Bit 18 : Write '1' to enable interrupt for event COMPARE[2] */ #define TIMER_INTENSET_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */ #define TIMER_INTENSET_COMPARE2_Msk (0x1UL << TIMER_INTENSET_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */ -#define TIMER_INTENSET_COMPARE2_Disabled (0UL) /*!< Read: Disabled */ -#define TIMER_INTENSET_COMPARE2_Enabled (1UL) /*!< Read: Enabled */ -#define TIMER_INTENSET_COMPARE2_Set (1UL) /*!< Enable */ +#define TIMER_INTENSET_COMPARE2_Disabled (0x0UL) /*!< Read: Disabled */ +#define TIMER_INTENSET_COMPARE2_Enabled (0x1UL) /*!< Read: Enabled */ +#define TIMER_INTENSET_COMPARE2_Set (0x1UL) /*!< Enable */ /* Bit 17 : Write '1' to enable interrupt for event COMPARE[1] */ #define TIMER_INTENSET_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */ #define TIMER_INTENSET_COMPARE1_Msk (0x1UL << TIMER_INTENSET_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */ -#define TIMER_INTENSET_COMPARE1_Disabled (0UL) /*!< Read: Disabled */ -#define TIMER_INTENSET_COMPARE1_Enabled (1UL) /*!< Read: Enabled */ -#define TIMER_INTENSET_COMPARE1_Set (1UL) /*!< Enable */ +#define TIMER_INTENSET_COMPARE1_Disabled (0x0UL) /*!< Read: Disabled */ +#define TIMER_INTENSET_COMPARE1_Enabled (0x1UL) /*!< Read: Enabled */ +#define TIMER_INTENSET_COMPARE1_Set (0x1UL) /*!< Enable */ /* Bit 16 : Write '1' to enable interrupt for event COMPARE[0] */ #define TIMER_INTENSET_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */ #define TIMER_INTENSET_COMPARE0_Msk (0x1UL << TIMER_INTENSET_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */ -#define TIMER_INTENSET_COMPARE0_Disabled (0UL) /*!< Read: Disabled */ -#define TIMER_INTENSET_COMPARE0_Enabled (1UL) /*!< Read: Enabled */ -#define TIMER_INTENSET_COMPARE0_Set (1UL) /*!< Enable */ +#define TIMER_INTENSET_COMPARE0_Disabled (0x0UL) /*!< Read: Disabled */ +#define TIMER_INTENSET_COMPARE0_Enabled (0x1UL) /*!< Read: Enabled */ +#define TIMER_INTENSET_COMPARE0_Set (0x1UL) /*!< Enable */ /* Register: TIMER_INTENCLR */ /* Description: Disable interrupt */ @@ -8741,44 +8741,44 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 21 : Write '1' to disable interrupt for event COMPARE[5] */ #define TIMER_INTENCLR_COMPARE5_Pos (21UL) /*!< Position of COMPARE5 field. */ #define TIMER_INTENCLR_COMPARE5_Msk (0x1UL << TIMER_INTENCLR_COMPARE5_Pos) /*!< Bit mask of COMPARE5 field. */ -#define TIMER_INTENCLR_COMPARE5_Disabled (0UL) /*!< Read: Disabled */ -#define TIMER_INTENCLR_COMPARE5_Enabled (1UL) /*!< Read: Enabled */ -#define TIMER_INTENCLR_COMPARE5_Clear (1UL) /*!< Disable */ +#define TIMER_INTENCLR_COMPARE5_Disabled (0x0UL) /*!< Read: Disabled */ +#define TIMER_INTENCLR_COMPARE5_Enabled (0x1UL) /*!< Read: Enabled */ +#define TIMER_INTENCLR_COMPARE5_Clear (0x1UL) /*!< Disable */ /* Bit 20 : Write '1' to disable interrupt for event COMPARE[4] */ #define TIMER_INTENCLR_COMPARE4_Pos (20UL) /*!< Position of COMPARE4 field. */ #define TIMER_INTENCLR_COMPARE4_Msk (0x1UL << TIMER_INTENCLR_COMPARE4_Pos) /*!< Bit mask of COMPARE4 field. */ -#define TIMER_INTENCLR_COMPARE4_Disabled (0UL) /*!< Read: Disabled */ -#define TIMER_INTENCLR_COMPARE4_Enabled (1UL) /*!< Read: Enabled */ -#define TIMER_INTENCLR_COMPARE4_Clear (1UL) /*!< Disable */ +#define TIMER_INTENCLR_COMPARE4_Disabled (0x0UL) /*!< Read: Disabled */ +#define TIMER_INTENCLR_COMPARE4_Enabled (0x1UL) /*!< Read: Enabled */ +#define TIMER_INTENCLR_COMPARE4_Clear (0x1UL) /*!< Disable */ /* Bit 19 : Write '1' to disable interrupt for event COMPARE[3] */ #define TIMER_INTENCLR_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */ #define TIMER_INTENCLR_COMPARE3_Msk (0x1UL << TIMER_INTENCLR_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */ -#define TIMER_INTENCLR_COMPARE3_Disabled (0UL) /*!< Read: Disabled */ -#define TIMER_INTENCLR_COMPARE3_Enabled (1UL) /*!< Read: Enabled */ -#define TIMER_INTENCLR_COMPARE3_Clear (1UL) /*!< Disable */ +#define TIMER_INTENCLR_COMPARE3_Disabled (0x0UL) /*!< Read: Disabled */ +#define TIMER_INTENCLR_COMPARE3_Enabled (0x1UL) /*!< Read: Enabled */ +#define TIMER_INTENCLR_COMPARE3_Clear (0x1UL) /*!< Disable */ /* Bit 18 : Write '1' to disable interrupt for event COMPARE[2] */ #define TIMER_INTENCLR_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */ #define TIMER_INTENCLR_COMPARE2_Msk (0x1UL << TIMER_INTENCLR_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */ -#define TIMER_INTENCLR_COMPARE2_Disabled (0UL) /*!< Read: Disabled */ -#define TIMER_INTENCLR_COMPARE2_Enabled (1UL) /*!< Read: Enabled */ -#define TIMER_INTENCLR_COMPARE2_Clear (1UL) /*!< Disable */ +#define TIMER_INTENCLR_COMPARE2_Disabled (0x0UL) /*!< Read: Disabled */ +#define TIMER_INTENCLR_COMPARE2_Enabled (0x1UL) /*!< Read: Enabled */ +#define TIMER_INTENCLR_COMPARE2_Clear (0x1UL) /*!< Disable */ /* Bit 17 : Write '1' to disable interrupt for event COMPARE[1] */ #define TIMER_INTENCLR_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */ #define TIMER_INTENCLR_COMPARE1_Msk (0x1UL << TIMER_INTENCLR_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */ -#define TIMER_INTENCLR_COMPARE1_Disabled (0UL) /*!< Read: Disabled */ -#define TIMER_INTENCLR_COMPARE1_Enabled (1UL) /*!< Read: Enabled */ -#define TIMER_INTENCLR_COMPARE1_Clear (1UL) /*!< Disable */ +#define TIMER_INTENCLR_COMPARE1_Disabled (0x0UL) /*!< Read: Disabled */ +#define TIMER_INTENCLR_COMPARE1_Enabled (0x1UL) /*!< Read: Enabled */ +#define TIMER_INTENCLR_COMPARE1_Clear (0x1UL) /*!< Disable */ /* Bit 16 : Write '1' to disable interrupt for event COMPARE[0] */ #define TIMER_INTENCLR_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */ #define TIMER_INTENCLR_COMPARE0_Msk (0x1UL << TIMER_INTENCLR_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */ -#define TIMER_INTENCLR_COMPARE0_Disabled (0UL) /*!< Read: Disabled */ -#define TIMER_INTENCLR_COMPARE0_Enabled (1UL) /*!< Read: Enabled */ -#define TIMER_INTENCLR_COMPARE0_Clear (1UL) /*!< Disable */ +#define TIMER_INTENCLR_COMPARE0_Disabled (0x0UL) /*!< Read: Disabled */ +#define TIMER_INTENCLR_COMPARE0_Enabled (0x1UL) /*!< Read: Enabled */ +#define TIMER_INTENCLR_COMPARE0_Clear (0x1UL) /*!< Disable */ /* Register: TIMER_MODE */ /* Description: Timer mode selection */ @@ -8786,9 +8786,9 @@ POSSIBILITY OF SUCH DAMAGE. /* Bits 1..0 : Timer mode */ #define TIMER_MODE_MODE_Pos (0UL) /*!< Position of MODE field. */ #define TIMER_MODE_MODE_Msk (0x3UL << TIMER_MODE_MODE_Pos) /*!< Bit mask of MODE field. */ -#define TIMER_MODE_MODE_Timer (0UL) /*!< Select Timer mode */ -#define TIMER_MODE_MODE_Counter (1UL) /*!< Deprecated enumerator - Select Counter mode */ -#define TIMER_MODE_MODE_LowPowerCounter (2UL) /*!< Select Low Power Counter mode */ +#define TIMER_MODE_MODE_Timer (0x0UL) /*!< Select Timer mode */ +#define TIMER_MODE_MODE_Counter (0x1UL) /*!< Deprecated enumerator - Select Counter mode */ +#define TIMER_MODE_MODE_LowPowerCounter (0x2UL) /*!< Select Low Power Counter mode */ /* Register: TIMER_BITMODE */ /* Description: Configure the number of bits used by the TIMER */ @@ -8796,10 +8796,10 @@ POSSIBILITY OF SUCH DAMAGE. /* Bits 1..0 : Timer bit width */ #define TIMER_BITMODE_BITMODE_Pos (0UL) /*!< Position of BITMODE field. */ #define TIMER_BITMODE_BITMODE_Msk (0x3UL << TIMER_BITMODE_BITMODE_Pos) /*!< Bit mask of BITMODE field. */ -#define TIMER_BITMODE_BITMODE_16Bit (0UL) /*!< 16 bit timer bit width */ -#define TIMER_BITMODE_BITMODE_08Bit (1UL) /*!< 8 bit timer bit width */ -#define TIMER_BITMODE_BITMODE_24Bit (2UL) /*!< 24 bit timer bit width */ -#define TIMER_BITMODE_BITMODE_32Bit (3UL) /*!< 32 bit timer bit width */ +#define TIMER_BITMODE_BITMODE_16Bit (0x0UL) /*!< 16 bit timer bit width */ +#define TIMER_BITMODE_BITMODE_08Bit (0x1UL) /*!< 8 bit timer bit width */ +#define TIMER_BITMODE_BITMODE_24Bit (0x2UL) /*!< 24 bit timer bit width */ +#define TIMER_BITMODE_BITMODE_32Bit (0x3UL) /*!< 32 bit timer bit width */ /* Register: TIMER_PRESCALER */ /* Description: Timer prescaler register */ @@ -8814,8 +8814,8 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 0 : Enable one-shot operation */ #define TIMER_ONESHOTEN_ONESHOTEN_Pos (0UL) /*!< Position of ONESHOTEN field. */ #define TIMER_ONESHOTEN_ONESHOTEN_Msk (0x1UL << TIMER_ONESHOTEN_ONESHOTEN_Pos) /*!< Bit mask of ONESHOTEN field. */ -#define TIMER_ONESHOTEN_ONESHOTEN_Disable (0UL) /*!< Disable one-shot operation */ -#define TIMER_ONESHOTEN_ONESHOTEN_Enable (1UL) /*!< Enable one-shot operation */ +#define TIMER_ONESHOTEN_ONESHOTEN_Disable (0x0UL) /*!< Disable one-shot operation */ +#define TIMER_ONESHOTEN_ONESHOTEN_Enable (0x1UL) /*!< Enable one-shot operation */ /* Register: TIMER_CC */ /* Description: Description collection: Capture/Compare register n */ @@ -8834,7 +8834,7 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 0 : Start TWI receive sequence */ #define TWIM_TASKS_STARTRX_TASKS_STARTRX_Pos (0UL) /*!< Position of TASKS_STARTRX field. */ #define TWIM_TASKS_STARTRX_TASKS_STARTRX_Msk (0x1UL << TWIM_TASKS_STARTRX_TASKS_STARTRX_Pos) /*!< Bit mask of TASKS_STARTRX field. */ -#define TWIM_TASKS_STARTRX_TASKS_STARTRX_Trigger (1UL) /*!< Trigger task */ +#define TWIM_TASKS_STARTRX_TASKS_STARTRX_Trigger (0x1UL) /*!< Trigger task */ /* Register: TWIM_TASKS_STARTTX */ /* Description: Start TWI transmit sequence */ @@ -8842,7 +8842,7 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 0 : Start TWI transmit sequence */ #define TWIM_TASKS_STARTTX_TASKS_STARTTX_Pos (0UL) /*!< Position of TASKS_STARTTX field. */ #define TWIM_TASKS_STARTTX_TASKS_STARTTX_Msk (0x1UL << TWIM_TASKS_STARTTX_TASKS_STARTTX_Pos) /*!< Bit mask of TASKS_STARTTX field. */ -#define TWIM_TASKS_STARTTX_TASKS_STARTTX_Trigger (1UL) /*!< Trigger task */ +#define TWIM_TASKS_STARTTX_TASKS_STARTTX_Trigger (0x1UL) /*!< Trigger task */ /* Register: TWIM_TASKS_STOP */ /* Description: Stop TWI transaction. Must be issued while the TWI master is not suspended. */ @@ -8850,7 +8850,7 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 0 : Stop TWI transaction. Must be issued while the TWI master is not suspended. */ #define TWIM_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */ #define TWIM_TASKS_STOP_TASKS_STOP_Msk (0x1UL << TWIM_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */ -#define TWIM_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */ +#define TWIM_TASKS_STOP_TASKS_STOP_Trigger (0x1UL) /*!< Trigger task */ /* Register: TWIM_TASKS_SUSPEND */ /* Description: Suspend TWI transaction */ @@ -8858,7 +8858,7 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 0 : Suspend TWI transaction */ #define TWIM_TASKS_SUSPEND_TASKS_SUSPEND_Pos (0UL) /*!< Position of TASKS_SUSPEND field. */ #define TWIM_TASKS_SUSPEND_TASKS_SUSPEND_Msk (0x1UL << TWIM_TASKS_SUSPEND_TASKS_SUSPEND_Pos) /*!< Bit mask of TASKS_SUSPEND field. */ -#define TWIM_TASKS_SUSPEND_TASKS_SUSPEND_Trigger (1UL) /*!< Trigger task */ +#define TWIM_TASKS_SUSPEND_TASKS_SUSPEND_Trigger (0x1UL) /*!< Trigger task */ /* Register: TWIM_TASKS_RESUME */ /* Description: Resume TWI transaction */ @@ -8866,7 +8866,7 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 0 : Resume TWI transaction */ #define TWIM_TASKS_RESUME_TASKS_RESUME_Pos (0UL) /*!< Position of TASKS_RESUME field. */ #define TWIM_TASKS_RESUME_TASKS_RESUME_Msk (0x1UL << TWIM_TASKS_RESUME_TASKS_RESUME_Pos) /*!< Bit mask of TASKS_RESUME field. */ -#define TWIM_TASKS_RESUME_TASKS_RESUME_Trigger (1UL) /*!< Trigger task */ +#define TWIM_TASKS_RESUME_TASKS_RESUME_Trigger (0x1UL) /*!< Trigger task */ /* Register: TWIM_SUBSCRIBE_STARTRX */ /* Description: Subscribe configuration for task STARTRX */ @@ -8874,8 +8874,8 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 31 : */ #define TWIM_SUBSCRIBE_STARTRX_EN_Pos (31UL) /*!< Position of EN field. */ #define TWIM_SUBSCRIBE_STARTRX_EN_Msk (0x1UL << TWIM_SUBSCRIBE_STARTRX_EN_Pos) /*!< Bit mask of EN field. */ -#define TWIM_SUBSCRIBE_STARTRX_EN_Disabled (0UL) /*!< Disable subscription */ -#define TWIM_SUBSCRIBE_STARTRX_EN_Enabled (1UL) /*!< Enable subscription */ +#define TWIM_SUBSCRIBE_STARTRX_EN_Disabled (0x0UL) /*!< Disable subscription */ +#define TWIM_SUBSCRIBE_STARTRX_EN_Enabled (0x1UL) /*!< Enable subscription */ /* Bits 7..0 : DPPI channel that task STARTRX will subscribe to */ #define TWIM_SUBSCRIBE_STARTRX_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ @@ -8887,8 +8887,8 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 31 : */ #define TWIM_SUBSCRIBE_STARTTX_EN_Pos (31UL) /*!< Position of EN field. */ #define TWIM_SUBSCRIBE_STARTTX_EN_Msk (0x1UL << TWIM_SUBSCRIBE_STARTTX_EN_Pos) /*!< Bit mask of EN field. */ -#define TWIM_SUBSCRIBE_STARTTX_EN_Disabled (0UL) /*!< Disable subscription */ -#define TWIM_SUBSCRIBE_STARTTX_EN_Enabled (1UL) /*!< Enable subscription */ +#define TWIM_SUBSCRIBE_STARTTX_EN_Disabled (0x0UL) /*!< Disable subscription */ +#define TWIM_SUBSCRIBE_STARTTX_EN_Enabled (0x1UL) /*!< Enable subscription */ /* Bits 7..0 : DPPI channel that task STARTTX will subscribe to */ #define TWIM_SUBSCRIBE_STARTTX_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ @@ -8900,8 +8900,8 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 31 : */ #define TWIM_SUBSCRIBE_STOP_EN_Pos (31UL) /*!< Position of EN field. */ #define TWIM_SUBSCRIBE_STOP_EN_Msk (0x1UL << TWIM_SUBSCRIBE_STOP_EN_Pos) /*!< Bit mask of EN field. */ -#define TWIM_SUBSCRIBE_STOP_EN_Disabled (0UL) /*!< Disable subscription */ -#define TWIM_SUBSCRIBE_STOP_EN_Enabled (1UL) /*!< Enable subscription */ +#define TWIM_SUBSCRIBE_STOP_EN_Disabled (0x0UL) /*!< Disable subscription */ +#define TWIM_SUBSCRIBE_STOP_EN_Enabled (0x1UL) /*!< Enable subscription */ /* Bits 7..0 : DPPI channel that task STOP will subscribe to */ #define TWIM_SUBSCRIBE_STOP_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ @@ -8913,8 +8913,8 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 31 : */ #define TWIM_SUBSCRIBE_SUSPEND_EN_Pos (31UL) /*!< Position of EN field. */ #define TWIM_SUBSCRIBE_SUSPEND_EN_Msk (0x1UL << TWIM_SUBSCRIBE_SUSPEND_EN_Pos) /*!< Bit mask of EN field. */ -#define TWIM_SUBSCRIBE_SUSPEND_EN_Disabled (0UL) /*!< Disable subscription */ -#define TWIM_SUBSCRIBE_SUSPEND_EN_Enabled (1UL) /*!< Enable subscription */ +#define TWIM_SUBSCRIBE_SUSPEND_EN_Disabled (0x0UL) /*!< Disable subscription */ +#define TWIM_SUBSCRIBE_SUSPEND_EN_Enabled (0x1UL) /*!< Enable subscription */ /* Bits 7..0 : DPPI channel that task SUSPEND will subscribe to */ #define TWIM_SUBSCRIBE_SUSPEND_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ @@ -8926,8 +8926,8 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 31 : */ #define TWIM_SUBSCRIBE_RESUME_EN_Pos (31UL) /*!< Position of EN field. */ #define TWIM_SUBSCRIBE_RESUME_EN_Msk (0x1UL << TWIM_SUBSCRIBE_RESUME_EN_Pos) /*!< Bit mask of EN field. */ -#define TWIM_SUBSCRIBE_RESUME_EN_Disabled (0UL) /*!< Disable subscription */ -#define TWIM_SUBSCRIBE_RESUME_EN_Enabled (1UL) /*!< Enable subscription */ +#define TWIM_SUBSCRIBE_RESUME_EN_Disabled (0x0UL) /*!< Disable subscription */ +#define TWIM_SUBSCRIBE_RESUME_EN_Enabled (0x1UL) /*!< Enable subscription */ /* Bits 7..0 : DPPI channel that task RESUME will subscribe to */ #define TWIM_SUBSCRIBE_RESUME_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ @@ -8939,8 +8939,8 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 0 : TWI stopped */ #define TWIM_EVENTS_STOPPED_EVENTS_STOPPED_Pos (0UL) /*!< Position of EVENTS_STOPPED field. */ #define TWIM_EVENTS_STOPPED_EVENTS_STOPPED_Msk (0x1UL << TWIM_EVENTS_STOPPED_EVENTS_STOPPED_Pos) /*!< Bit mask of EVENTS_STOPPED field. */ -#define TWIM_EVENTS_STOPPED_EVENTS_STOPPED_NotGenerated (0UL) /*!< Event not generated */ -#define TWIM_EVENTS_STOPPED_EVENTS_STOPPED_Generated (1UL) /*!< Event generated */ +#define TWIM_EVENTS_STOPPED_EVENTS_STOPPED_NotGenerated (0x0UL) /*!< Event not generated */ +#define TWIM_EVENTS_STOPPED_EVENTS_STOPPED_Generated (0x1UL) /*!< Event generated */ /* Register: TWIM_EVENTS_ERROR */ /* Description: TWI error */ @@ -8948,8 +8948,8 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 0 : TWI error */ #define TWIM_EVENTS_ERROR_EVENTS_ERROR_Pos (0UL) /*!< Position of EVENTS_ERROR field. */ #define TWIM_EVENTS_ERROR_EVENTS_ERROR_Msk (0x1UL << TWIM_EVENTS_ERROR_EVENTS_ERROR_Pos) /*!< Bit mask of EVENTS_ERROR field. */ -#define TWIM_EVENTS_ERROR_EVENTS_ERROR_NotGenerated (0UL) /*!< Event not generated */ -#define TWIM_EVENTS_ERROR_EVENTS_ERROR_Generated (1UL) /*!< Event generated */ +#define TWIM_EVENTS_ERROR_EVENTS_ERROR_NotGenerated (0x0UL) /*!< Event not generated */ +#define TWIM_EVENTS_ERROR_EVENTS_ERROR_Generated (0x1UL) /*!< Event generated */ /* Register: TWIM_EVENTS_SUSPENDED */ /* Description: SUSPEND task has been issued, TWI traffic is now suspended. */ @@ -8957,8 +8957,8 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 0 : SUSPEND task has been issued, TWI traffic is now suspended. */ #define TWIM_EVENTS_SUSPENDED_EVENTS_SUSPENDED_Pos (0UL) /*!< Position of EVENTS_SUSPENDED field. */ #define TWIM_EVENTS_SUSPENDED_EVENTS_SUSPENDED_Msk (0x1UL << TWIM_EVENTS_SUSPENDED_EVENTS_SUSPENDED_Pos) /*!< Bit mask of EVENTS_SUSPENDED field. */ -#define TWIM_EVENTS_SUSPENDED_EVENTS_SUSPENDED_NotGenerated (0UL) /*!< Event not generated */ -#define TWIM_EVENTS_SUSPENDED_EVENTS_SUSPENDED_Generated (1UL) /*!< Event generated */ +#define TWIM_EVENTS_SUSPENDED_EVENTS_SUSPENDED_NotGenerated (0x0UL) /*!< Event not generated */ +#define TWIM_EVENTS_SUSPENDED_EVENTS_SUSPENDED_Generated (0x1UL) /*!< Event generated */ /* Register: TWIM_EVENTS_RXSTARTED */ /* Description: Receive sequence started */ @@ -8966,8 +8966,8 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 0 : Receive sequence started */ #define TWIM_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Pos (0UL) /*!< Position of EVENTS_RXSTARTED field. */ #define TWIM_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Msk (0x1UL << TWIM_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Pos) /*!< Bit mask of EVENTS_RXSTARTED field. */ -#define TWIM_EVENTS_RXSTARTED_EVENTS_RXSTARTED_NotGenerated (0UL) /*!< Event not generated */ -#define TWIM_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Generated (1UL) /*!< Event generated */ +#define TWIM_EVENTS_RXSTARTED_EVENTS_RXSTARTED_NotGenerated (0x0UL) /*!< Event not generated */ +#define TWIM_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Generated (0x1UL) /*!< Event generated */ /* Register: TWIM_EVENTS_TXSTARTED */ /* Description: Transmit sequence started */ @@ -8975,8 +8975,8 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 0 : Transmit sequence started */ #define TWIM_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Pos (0UL) /*!< Position of EVENTS_TXSTARTED field. */ #define TWIM_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Msk (0x1UL << TWIM_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Pos) /*!< Bit mask of EVENTS_TXSTARTED field. */ -#define TWIM_EVENTS_TXSTARTED_EVENTS_TXSTARTED_NotGenerated (0UL) /*!< Event not generated */ -#define TWIM_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Generated (1UL) /*!< Event generated */ +#define TWIM_EVENTS_TXSTARTED_EVENTS_TXSTARTED_NotGenerated (0x0UL) /*!< Event not generated */ +#define TWIM_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Generated (0x1UL) /*!< Event generated */ /* Register: TWIM_EVENTS_LASTRX */ /* Description: Byte boundary, starting to receive the last byte */ @@ -8984,8 +8984,8 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 0 : Byte boundary, starting to receive the last byte */ #define TWIM_EVENTS_LASTRX_EVENTS_LASTRX_Pos (0UL) /*!< Position of EVENTS_LASTRX field. */ #define TWIM_EVENTS_LASTRX_EVENTS_LASTRX_Msk (0x1UL << TWIM_EVENTS_LASTRX_EVENTS_LASTRX_Pos) /*!< Bit mask of EVENTS_LASTRX field. */ -#define TWIM_EVENTS_LASTRX_EVENTS_LASTRX_NotGenerated (0UL) /*!< Event not generated */ -#define TWIM_EVENTS_LASTRX_EVENTS_LASTRX_Generated (1UL) /*!< Event generated */ +#define TWIM_EVENTS_LASTRX_EVENTS_LASTRX_NotGenerated (0x0UL) /*!< Event not generated */ +#define TWIM_EVENTS_LASTRX_EVENTS_LASTRX_Generated (0x1UL) /*!< Event generated */ /* Register: TWIM_EVENTS_LASTTX */ /* Description: Byte boundary, starting to transmit the last byte */ @@ -8993,8 +8993,8 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 0 : Byte boundary, starting to transmit the last byte */ #define TWIM_EVENTS_LASTTX_EVENTS_LASTTX_Pos (0UL) /*!< Position of EVENTS_LASTTX field. */ #define TWIM_EVENTS_LASTTX_EVENTS_LASTTX_Msk (0x1UL << TWIM_EVENTS_LASTTX_EVENTS_LASTTX_Pos) /*!< Bit mask of EVENTS_LASTTX field. */ -#define TWIM_EVENTS_LASTTX_EVENTS_LASTTX_NotGenerated (0UL) /*!< Event not generated */ -#define TWIM_EVENTS_LASTTX_EVENTS_LASTTX_Generated (1UL) /*!< Event generated */ +#define TWIM_EVENTS_LASTTX_EVENTS_LASTTX_NotGenerated (0x0UL) /*!< Event not generated */ +#define TWIM_EVENTS_LASTTX_EVENTS_LASTTX_Generated (0x1UL) /*!< Event generated */ /* Register: TWIM_PUBLISH_STOPPED */ /* Description: Publish configuration for event STOPPED */ @@ -9002,8 +9002,8 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 31 : */ #define TWIM_PUBLISH_STOPPED_EN_Pos (31UL) /*!< Position of EN field. */ #define TWIM_PUBLISH_STOPPED_EN_Msk (0x1UL << TWIM_PUBLISH_STOPPED_EN_Pos) /*!< Bit mask of EN field. */ -#define TWIM_PUBLISH_STOPPED_EN_Disabled (0UL) /*!< Disable publishing */ -#define TWIM_PUBLISH_STOPPED_EN_Enabled (1UL) /*!< Enable publishing */ +#define TWIM_PUBLISH_STOPPED_EN_Disabled (0x0UL) /*!< Disable publishing */ +#define TWIM_PUBLISH_STOPPED_EN_Enabled (0x1UL) /*!< Enable publishing */ /* Bits 7..0 : DPPI channel that event STOPPED will publish to */ #define TWIM_PUBLISH_STOPPED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ @@ -9015,8 +9015,8 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 31 : */ #define TWIM_PUBLISH_ERROR_EN_Pos (31UL) /*!< Position of EN field. */ #define TWIM_PUBLISH_ERROR_EN_Msk (0x1UL << TWIM_PUBLISH_ERROR_EN_Pos) /*!< Bit mask of EN field. */ -#define TWIM_PUBLISH_ERROR_EN_Disabled (0UL) /*!< Disable publishing */ -#define TWIM_PUBLISH_ERROR_EN_Enabled (1UL) /*!< Enable publishing */ +#define TWIM_PUBLISH_ERROR_EN_Disabled (0x0UL) /*!< Disable publishing */ +#define TWIM_PUBLISH_ERROR_EN_Enabled (0x1UL) /*!< Enable publishing */ /* Bits 7..0 : DPPI channel that event ERROR will publish to */ #define TWIM_PUBLISH_ERROR_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ @@ -9028,8 +9028,8 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 31 : */ #define TWIM_PUBLISH_SUSPENDED_EN_Pos (31UL) /*!< Position of EN field. */ #define TWIM_PUBLISH_SUSPENDED_EN_Msk (0x1UL << TWIM_PUBLISH_SUSPENDED_EN_Pos) /*!< Bit mask of EN field. */ -#define TWIM_PUBLISH_SUSPENDED_EN_Disabled (0UL) /*!< Disable publishing */ -#define TWIM_PUBLISH_SUSPENDED_EN_Enabled (1UL) /*!< Enable publishing */ +#define TWIM_PUBLISH_SUSPENDED_EN_Disabled (0x0UL) /*!< Disable publishing */ +#define TWIM_PUBLISH_SUSPENDED_EN_Enabled (0x1UL) /*!< Enable publishing */ /* Bits 7..0 : DPPI channel that event SUSPENDED will publish to */ #define TWIM_PUBLISH_SUSPENDED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ @@ -9041,8 +9041,8 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 31 : */ #define TWIM_PUBLISH_RXSTARTED_EN_Pos (31UL) /*!< Position of EN field. */ #define TWIM_PUBLISH_RXSTARTED_EN_Msk (0x1UL << TWIM_PUBLISH_RXSTARTED_EN_Pos) /*!< Bit mask of EN field. */ -#define TWIM_PUBLISH_RXSTARTED_EN_Disabled (0UL) /*!< Disable publishing */ -#define TWIM_PUBLISH_RXSTARTED_EN_Enabled (1UL) /*!< Enable publishing */ +#define TWIM_PUBLISH_RXSTARTED_EN_Disabled (0x0UL) /*!< Disable publishing */ +#define TWIM_PUBLISH_RXSTARTED_EN_Enabled (0x1UL) /*!< Enable publishing */ /* Bits 7..0 : DPPI channel that event RXSTARTED will publish to */ #define TWIM_PUBLISH_RXSTARTED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ @@ -9054,8 +9054,8 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 31 : */ #define TWIM_PUBLISH_TXSTARTED_EN_Pos (31UL) /*!< Position of EN field. */ #define TWIM_PUBLISH_TXSTARTED_EN_Msk (0x1UL << TWIM_PUBLISH_TXSTARTED_EN_Pos) /*!< Bit mask of EN field. */ -#define TWIM_PUBLISH_TXSTARTED_EN_Disabled (0UL) /*!< Disable publishing */ -#define TWIM_PUBLISH_TXSTARTED_EN_Enabled (1UL) /*!< Enable publishing */ +#define TWIM_PUBLISH_TXSTARTED_EN_Disabled (0x0UL) /*!< Disable publishing */ +#define TWIM_PUBLISH_TXSTARTED_EN_Enabled (0x1UL) /*!< Enable publishing */ /* Bits 7..0 : DPPI channel that event TXSTARTED will publish to */ #define TWIM_PUBLISH_TXSTARTED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ @@ -9067,8 +9067,8 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 31 : */ #define TWIM_PUBLISH_LASTRX_EN_Pos (31UL) /*!< Position of EN field. */ #define TWIM_PUBLISH_LASTRX_EN_Msk (0x1UL << TWIM_PUBLISH_LASTRX_EN_Pos) /*!< Bit mask of EN field. */ -#define TWIM_PUBLISH_LASTRX_EN_Disabled (0UL) /*!< Disable publishing */ -#define TWIM_PUBLISH_LASTRX_EN_Enabled (1UL) /*!< Enable publishing */ +#define TWIM_PUBLISH_LASTRX_EN_Disabled (0x0UL) /*!< Disable publishing */ +#define TWIM_PUBLISH_LASTRX_EN_Enabled (0x1UL) /*!< Enable publishing */ /* Bits 7..0 : DPPI channel that event LASTRX will publish to */ #define TWIM_PUBLISH_LASTRX_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ @@ -9080,8 +9080,8 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 31 : */ #define TWIM_PUBLISH_LASTTX_EN_Pos (31UL) /*!< Position of EN field. */ #define TWIM_PUBLISH_LASTTX_EN_Msk (0x1UL << TWIM_PUBLISH_LASTTX_EN_Pos) /*!< Bit mask of EN field. */ -#define TWIM_PUBLISH_LASTTX_EN_Disabled (0UL) /*!< Disable publishing */ -#define TWIM_PUBLISH_LASTTX_EN_Enabled (1UL) /*!< Enable publishing */ +#define TWIM_PUBLISH_LASTTX_EN_Disabled (0x0UL) /*!< Disable publishing */ +#define TWIM_PUBLISH_LASTTX_EN_Enabled (0x1UL) /*!< Enable publishing */ /* Bits 7..0 : DPPI channel that event LASTTX will publish to */ #define TWIM_PUBLISH_LASTTX_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ @@ -9093,32 +9093,32 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 12 : Shortcut between event LASTRX and task STOP */ #define TWIM_SHORTS_LASTRX_STOP_Pos (12UL) /*!< Position of LASTRX_STOP field. */ #define TWIM_SHORTS_LASTRX_STOP_Msk (0x1UL << TWIM_SHORTS_LASTRX_STOP_Pos) /*!< Bit mask of LASTRX_STOP field. */ -#define TWIM_SHORTS_LASTRX_STOP_Disabled (0UL) /*!< Disable shortcut */ -#define TWIM_SHORTS_LASTRX_STOP_Enabled (1UL) /*!< Enable shortcut */ +#define TWIM_SHORTS_LASTRX_STOP_Disabled (0x0UL) /*!< Disable shortcut */ +#define TWIM_SHORTS_LASTRX_STOP_Enabled (0x1UL) /*!< Enable shortcut */ /* Bit 10 : Shortcut between event LASTRX and task STARTTX */ #define TWIM_SHORTS_LASTRX_STARTTX_Pos (10UL) /*!< Position of LASTRX_STARTTX field. */ #define TWIM_SHORTS_LASTRX_STARTTX_Msk (0x1UL << TWIM_SHORTS_LASTRX_STARTTX_Pos) /*!< Bit mask of LASTRX_STARTTX field. */ -#define TWIM_SHORTS_LASTRX_STARTTX_Disabled (0UL) /*!< Disable shortcut */ -#define TWIM_SHORTS_LASTRX_STARTTX_Enabled (1UL) /*!< Enable shortcut */ +#define TWIM_SHORTS_LASTRX_STARTTX_Disabled (0x0UL) /*!< Disable shortcut */ +#define TWIM_SHORTS_LASTRX_STARTTX_Enabled (0x1UL) /*!< Enable shortcut */ /* Bit 9 : Shortcut between event LASTTX and task STOP */ #define TWIM_SHORTS_LASTTX_STOP_Pos (9UL) /*!< Position of LASTTX_STOP field. */ #define TWIM_SHORTS_LASTTX_STOP_Msk (0x1UL << TWIM_SHORTS_LASTTX_STOP_Pos) /*!< Bit mask of LASTTX_STOP field. */ -#define TWIM_SHORTS_LASTTX_STOP_Disabled (0UL) /*!< Disable shortcut */ -#define TWIM_SHORTS_LASTTX_STOP_Enabled (1UL) /*!< Enable shortcut */ +#define TWIM_SHORTS_LASTTX_STOP_Disabled (0x0UL) /*!< Disable shortcut */ +#define TWIM_SHORTS_LASTTX_STOP_Enabled (0x1UL) /*!< Enable shortcut */ /* Bit 8 : Shortcut between event LASTTX and task SUSPEND */ #define TWIM_SHORTS_LASTTX_SUSPEND_Pos (8UL) /*!< Position of LASTTX_SUSPEND field. */ #define TWIM_SHORTS_LASTTX_SUSPEND_Msk (0x1UL << TWIM_SHORTS_LASTTX_SUSPEND_Pos) /*!< Bit mask of LASTTX_SUSPEND field. */ -#define TWIM_SHORTS_LASTTX_SUSPEND_Disabled (0UL) /*!< Disable shortcut */ -#define TWIM_SHORTS_LASTTX_SUSPEND_Enabled (1UL) /*!< Enable shortcut */ +#define TWIM_SHORTS_LASTTX_SUSPEND_Disabled (0x0UL) /*!< Disable shortcut */ +#define TWIM_SHORTS_LASTTX_SUSPEND_Enabled (0x1UL) /*!< Enable shortcut */ /* Bit 7 : Shortcut between event LASTTX and task STARTRX */ #define TWIM_SHORTS_LASTTX_STARTRX_Pos (7UL) /*!< Position of LASTTX_STARTRX field. */ #define TWIM_SHORTS_LASTTX_STARTRX_Msk (0x1UL << TWIM_SHORTS_LASTTX_STARTRX_Pos) /*!< Bit mask of LASTTX_STARTRX field. */ -#define TWIM_SHORTS_LASTTX_STARTRX_Disabled (0UL) /*!< Disable shortcut */ -#define TWIM_SHORTS_LASTTX_STARTRX_Enabled (1UL) /*!< Enable shortcut */ +#define TWIM_SHORTS_LASTTX_STARTRX_Disabled (0x0UL) /*!< Disable shortcut */ +#define TWIM_SHORTS_LASTTX_STARTRX_Enabled (0x1UL) /*!< Enable shortcut */ /* Register: TWIM_INTEN */ /* Description: Enable or disable interrupt */ @@ -9126,44 +9126,44 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 24 : Enable or disable interrupt for event LASTTX */ #define TWIM_INTEN_LASTTX_Pos (24UL) /*!< Position of LASTTX field. */ #define TWIM_INTEN_LASTTX_Msk (0x1UL << TWIM_INTEN_LASTTX_Pos) /*!< Bit mask of LASTTX field. */ -#define TWIM_INTEN_LASTTX_Disabled (0UL) /*!< Disable */ -#define TWIM_INTEN_LASTTX_Enabled (1UL) /*!< Enable */ +#define TWIM_INTEN_LASTTX_Disabled (0x0UL) /*!< Disable */ +#define TWIM_INTEN_LASTTX_Enabled (0x1UL) /*!< Enable */ /* Bit 23 : Enable or disable interrupt for event LASTRX */ #define TWIM_INTEN_LASTRX_Pos (23UL) /*!< Position of LASTRX field. */ #define TWIM_INTEN_LASTRX_Msk (0x1UL << TWIM_INTEN_LASTRX_Pos) /*!< Bit mask of LASTRX field. */ -#define TWIM_INTEN_LASTRX_Disabled (0UL) /*!< Disable */ -#define TWIM_INTEN_LASTRX_Enabled (1UL) /*!< Enable */ +#define TWIM_INTEN_LASTRX_Disabled (0x0UL) /*!< Disable */ +#define TWIM_INTEN_LASTRX_Enabled (0x1UL) /*!< Enable */ /* Bit 20 : Enable or disable interrupt for event TXSTARTED */ #define TWIM_INTEN_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */ #define TWIM_INTEN_TXSTARTED_Msk (0x1UL << TWIM_INTEN_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */ -#define TWIM_INTEN_TXSTARTED_Disabled (0UL) /*!< Disable */ -#define TWIM_INTEN_TXSTARTED_Enabled (1UL) /*!< Enable */ +#define TWIM_INTEN_TXSTARTED_Disabled (0x0UL) /*!< Disable */ +#define TWIM_INTEN_TXSTARTED_Enabled (0x1UL) /*!< Enable */ /* Bit 19 : Enable or disable interrupt for event RXSTARTED */ #define TWIM_INTEN_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */ #define TWIM_INTEN_RXSTARTED_Msk (0x1UL << TWIM_INTEN_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */ -#define TWIM_INTEN_RXSTARTED_Disabled (0UL) /*!< Disable */ -#define TWIM_INTEN_RXSTARTED_Enabled (1UL) /*!< Enable */ +#define TWIM_INTEN_RXSTARTED_Disabled (0x0UL) /*!< Disable */ +#define TWIM_INTEN_RXSTARTED_Enabled (0x1UL) /*!< Enable */ /* Bit 18 : Enable or disable interrupt for event SUSPENDED */ #define TWIM_INTEN_SUSPENDED_Pos (18UL) /*!< Position of SUSPENDED field. */ #define TWIM_INTEN_SUSPENDED_Msk (0x1UL << TWIM_INTEN_SUSPENDED_Pos) /*!< Bit mask of SUSPENDED field. */ -#define TWIM_INTEN_SUSPENDED_Disabled (0UL) /*!< Disable */ -#define TWIM_INTEN_SUSPENDED_Enabled (1UL) /*!< Enable */ +#define TWIM_INTEN_SUSPENDED_Disabled (0x0UL) /*!< Disable */ +#define TWIM_INTEN_SUSPENDED_Enabled (0x1UL) /*!< Enable */ /* Bit 9 : Enable or disable interrupt for event ERROR */ #define TWIM_INTEN_ERROR_Pos (9UL) /*!< Position of ERROR field. */ #define TWIM_INTEN_ERROR_Msk (0x1UL << TWIM_INTEN_ERROR_Pos) /*!< Bit mask of ERROR field. */ -#define TWIM_INTEN_ERROR_Disabled (0UL) /*!< Disable */ -#define TWIM_INTEN_ERROR_Enabled (1UL) /*!< Enable */ +#define TWIM_INTEN_ERROR_Disabled (0x0UL) /*!< Disable */ +#define TWIM_INTEN_ERROR_Enabled (0x1UL) /*!< Enable */ /* Bit 1 : Enable or disable interrupt for event STOPPED */ #define TWIM_INTEN_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ #define TWIM_INTEN_STOPPED_Msk (0x1UL << TWIM_INTEN_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ -#define TWIM_INTEN_STOPPED_Disabled (0UL) /*!< Disable */ -#define TWIM_INTEN_STOPPED_Enabled (1UL) /*!< Enable */ +#define TWIM_INTEN_STOPPED_Disabled (0x0UL) /*!< Disable */ +#define TWIM_INTEN_STOPPED_Enabled (0x1UL) /*!< Enable */ /* Register: TWIM_INTENSET */ /* Description: Enable interrupt */ @@ -9171,51 +9171,51 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 24 : Write '1' to enable interrupt for event LASTTX */ #define TWIM_INTENSET_LASTTX_Pos (24UL) /*!< Position of LASTTX field. */ #define TWIM_INTENSET_LASTTX_Msk (0x1UL << TWIM_INTENSET_LASTTX_Pos) /*!< Bit mask of LASTTX field. */ -#define TWIM_INTENSET_LASTTX_Disabled (0UL) /*!< Read: Disabled */ -#define TWIM_INTENSET_LASTTX_Enabled (1UL) /*!< Read: Enabled */ -#define TWIM_INTENSET_LASTTX_Set (1UL) /*!< Enable */ +#define TWIM_INTENSET_LASTTX_Disabled (0x0UL) /*!< Read: Disabled */ +#define TWIM_INTENSET_LASTTX_Enabled (0x1UL) /*!< Read: Enabled */ +#define TWIM_INTENSET_LASTTX_Set (0x1UL) /*!< Enable */ /* Bit 23 : Write '1' to enable interrupt for event LASTRX */ #define TWIM_INTENSET_LASTRX_Pos (23UL) /*!< Position of LASTRX field. */ #define TWIM_INTENSET_LASTRX_Msk (0x1UL << TWIM_INTENSET_LASTRX_Pos) /*!< Bit mask of LASTRX field. */ -#define TWIM_INTENSET_LASTRX_Disabled (0UL) /*!< Read: Disabled */ -#define TWIM_INTENSET_LASTRX_Enabled (1UL) /*!< Read: Enabled */ -#define TWIM_INTENSET_LASTRX_Set (1UL) /*!< Enable */ +#define TWIM_INTENSET_LASTRX_Disabled (0x0UL) /*!< Read: Disabled */ +#define TWIM_INTENSET_LASTRX_Enabled (0x1UL) /*!< Read: Enabled */ +#define TWIM_INTENSET_LASTRX_Set (0x1UL) /*!< Enable */ /* Bit 20 : Write '1' to enable interrupt for event TXSTARTED */ #define TWIM_INTENSET_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */ #define TWIM_INTENSET_TXSTARTED_Msk (0x1UL << TWIM_INTENSET_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */ -#define TWIM_INTENSET_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */ -#define TWIM_INTENSET_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */ -#define TWIM_INTENSET_TXSTARTED_Set (1UL) /*!< Enable */ +#define TWIM_INTENSET_TXSTARTED_Disabled (0x0UL) /*!< Read: Disabled */ +#define TWIM_INTENSET_TXSTARTED_Enabled (0x1UL) /*!< Read: Enabled */ +#define TWIM_INTENSET_TXSTARTED_Set (0x1UL) /*!< Enable */ /* Bit 19 : Write '1' to enable interrupt for event RXSTARTED */ #define TWIM_INTENSET_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */ #define TWIM_INTENSET_RXSTARTED_Msk (0x1UL << TWIM_INTENSET_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */ -#define TWIM_INTENSET_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */ -#define TWIM_INTENSET_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */ -#define TWIM_INTENSET_RXSTARTED_Set (1UL) /*!< Enable */ +#define TWIM_INTENSET_RXSTARTED_Disabled (0x0UL) /*!< Read: Disabled */ +#define TWIM_INTENSET_RXSTARTED_Enabled (0x1UL) /*!< Read: Enabled */ +#define TWIM_INTENSET_RXSTARTED_Set (0x1UL) /*!< Enable */ /* Bit 18 : Write '1' to enable interrupt for event SUSPENDED */ #define TWIM_INTENSET_SUSPENDED_Pos (18UL) /*!< Position of SUSPENDED field. */ #define TWIM_INTENSET_SUSPENDED_Msk (0x1UL << TWIM_INTENSET_SUSPENDED_Pos) /*!< Bit mask of SUSPENDED field. */ -#define TWIM_INTENSET_SUSPENDED_Disabled (0UL) /*!< Read: Disabled */ -#define TWIM_INTENSET_SUSPENDED_Enabled (1UL) /*!< Read: Enabled */ -#define TWIM_INTENSET_SUSPENDED_Set (1UL) /*!< Enable */ +#define TWIM_INTENSET_SUSPENDED_Disabled (0x0UL) /*!< Read: Disabled */ +#define TWIM_INTENSET_SUSPENDED_Enabled (0x1UL) /*!< Read: Enabled */ +#define TWIM_INTENSET_SUSPENDED_Set (0x1UL) /*!< Enable */ /* Bit 9 : Write '1' to enable interrupt for event ERROR */ #define TWIM_INTENSET_ERROR_Pos (9UL) /*!< Position of ERROR field. */ #define TWIM_INTENSET_ERROR_Msk (0x1UL << TWIM_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */ -#define TWIM_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */ -#define TWIM_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */ -#define TWIM_INTENSET_ERROR_Set (1UL) /*!< Enable */ +#define TWIM_INTENSET_ERROR_Disabled (0x0UL) /*!< Read: Disabled */ +#define TWIM_INTENSET_ERROR_Enabled (0x1UL) /*!< Read: Enabled */ +#define TWIM_INTENSET_ERROR_Set (0x1UL) /*!< Enable */ /* Bit 1 : Write '1' to enable interrupt for event STOPPED */ #define TWIM_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ #define TWIM_INTENSET_STOPPED_Msk (0x1UL << TWIM_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ -#define TWIM_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */ -#define TWIM_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */ -#define TWIM_INTENSET_STOPPED_Set (1UL) /*!< Enable */ +#define TWIM_INTENSET_STOPPED_Disabled (0x0UL) /*!< Read: Disabled */ +#define TWIM_INTENSET_STOPPED_Enabled (0x1UL) /*!< Read: Enabled */ +#define TWIM_INTENSET_STOPPED_Set (0x1UL) /*!< Enable */ /* Register: TWIM_INTENCLR */ /* Description: Disable interrupt */ @@ -9223,51 +9223,51 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 24 : Write '1' to disable interrupt for event LASTTX */ #define TWIM_INTENCLR_LASTTX_Pos (24UL) /*!< Position of LASTTX field. */ #define TWIM_INTENCLR_LASTTX_Msk (0x1UL << TWIM_INTENCLR_LASTTX_Pos) /*!< Bit mask of LASTTX field. */ -#define TWIM_INTENCLR_LASTTX_Disabled (0UL) /*!< Read: Disabled */ -#define TWIM_INTENCLR_LASTTX_Enabled (1UL) /*!< Read: Enabled */ -#define TWIM_INTENCLR_LASTTX_Clear (1UL) /*!< Disable */ +#define TWIM_INTENCLR_LASTTX_Disabled (0x0UL) /*!< Read: Disabled */ +#define TWIM_INTENCLR_LASTTX_Enabled (0x1UL) /*!< Read: Enabled */ +#define TWIM_INTENCLR_LASTTX_Clear (0x1UL) /*!< Disable */ /* Bit 23 : Write '1' to disable interrupt for event LASTRX */ #define TWIM_INTENCLR_LASTRX_Pos (23UL) /*!< Position of LASTRX field. */ #define TWIM_INTENCLR_LASTRX_Msk (0x1UL << TWIM_INTENCLR_LASTRX_Pos) /*!< Bit mask of LASTRX field. */ -#define TWIM_INTENCLR_LASTRX_Disabled (0UL) /*!< Read: Disabled */ -#define TWIM_INTENCLR_LASTRX_Enabled (1UL) /*!< Read: Enabled */ -#define TWIM_INTENCLR_LASTRX_Clear (1UL) /*!< Disable */ +#define TWIM_INTENCLR_LASTRX_Disabled (0x0UL) /*!< Read: Disabled */ +#define TWIM_INTENCLR_LASTRX_Enabled (0x1UL) /*!< Read: Enabled */ +#define TWIM_INTENCLR_LASTRX_Clear (0x1UL) /*!< Disable */ /* Bit 20 : Write '1' to disable interrupt for event TXSTARTED */ #define TWIM_INTENCLR_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */ #define TWIM_INTENCLR_TXSTARTED_Msk (0x1UL << TWIM_INTENCLR_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */ -#define TWIM_INTENCLR_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */ -#define TWIM_INTENCLR_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */ -#define TWIM_INTENCLR_TXSTARTED_Clear (1UL) /*!< Disable */ +#define TWIM_INTENCLR_TXSTARTED_Disabled (0x0UL) /*!< Read: Disabled */ +#define TWIM_INTENCLR_TXSTARTED_Enabled (0x1UL) /*!< Read: Enabled */ +#define TWIM_INTENCLR_TXSTARTED_Clear (0x1UL) /*!< Disable */ /* Bit 19 : Write '1' to disable interrupt for event RXSTARTED */ #define TWIM_INTENCLR_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */ #define TWIM_INTENCLR_RXSTARTED_Msk (0x1UL << TWIM_INTENCLR_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */ -#define TWIM_INTENCLR_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */ -#define TWIM_INTENCLR_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */ -#define TWIM_INTENCLR_RXSTARTED_Clear (1UL) /*!< Disable */ +#define TWIM_INTENCLR_RXSTARTED_Disabled (0x0UL) /*!< Read: Disabled */ +#define TWIM_INTENCLR_RXSTARTED_Enabled (0x1UL) /*!< Read: Enabled */ +#define TWIM_INTENCLR_RXSTARTED_Clear (0x1UL) /*!< Disable */ /* Bit 18 : Write '1' to disable interrupt for event SUSPENDED */ #define TWIM_INTENCLR_SUSPENDED_Pos (18UL) /*!< Position of SUSPENDED field. */ #define TWIM_INTENCLR_SUSPENDED_Msk (0x1UL << TWIM_INTENCLR_SUSPENDED_Pos) /*!< Bit mask of SUSPENDED field. */ -#define TWIM_INTENCLR_SUSPENDED_Disabled (0UL) /*!< Read: Disabled */ -#define TWIM_INTENCLR_SUSPENDED_Enabled (1UL) /*!< Read: Enabled */ -#define TWIM_INTENCLR_SUSPENDED_Clear (1UL) /*!< Disable */ +#define TWIM_INTENCLR_SUSPENDED_Disabled (0x0UL) /*!< Read: Disabled */ +#define TWIM_INTENCLR_SUSPENDED_Enabled (0x1UL) /*!< Read: Enabled */ +#define TWIM_INTENCLR_SUSPENDED_Clear (0x1UL) /*!< Disable */ /* Bit 9 : Write '1' to disable interrupt for event ERROR */ #define TWIM_INTENCLR_ERROR_Pos (9UL) /*!< Position of ERROR field. */ #define TWIM_INTENCLR_ERROR_Msk (0x1UL << TWIM_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */ -#define TWIM_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */ -#define TWIM_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */ -#define TWIM_INTENCLR_ERROR_Clear (1UL) /*!< Disable */ +#define TWIM_INTENCLR_ERROR_Disabled (0x0UL) /*!< Read: Disabled */ +#define TWIM_INTENCLR_ERROR_Enabled (0x1UL) /*!< Read: Enabled */ +#define TWIM_INTENCLR_ERROR_Clear (0x1UL) /*!< Disable */ /* Bit 1 : Write '1' to disable interrupt for event STOPPED */ #define TWIM_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ #define TWIM_INTENCLR_STOPPED_Msk (0x1UL << TWIM_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ -#define TWIM_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */ -#define TWIM_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */ -#define TWIM_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */ +#define TWIM_INTENCLR_STOPPED_Disabled (0x0UL) /*!< Read: Disabled */ +#define TWIM_INTENCLR_STOPPED_Enabled (0x1UL) /*!< Read: Enabled */ +#define TWIM_INTENCLR_STOPPED_Clear (0x1UL) /*!< Disable */ /* Register: TWIM_ERRORSRC */ /* Description: Error source */ @@ -9275,20 +9275,20 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 2 : NACK received after sending a data byte (write '1' to clear) */ #define TWIM_ERRORSRC_DNACK_Pos (2UL) /*!< Position of DNACK field. */ #define TWIM_ERRORSRC_DNACK_Msk (0x1UL << TWIM_ERRORSRC_DNACK_Pos) /*!< Bit mask of DNACK field. */ -#define TWIM_ERRORSRC_DNACK_NotReceived (0UL) /*!< Error did not occur */ -#define TWIM_ERRORSRC_DNACK_Received (1UL) /*!< Error occurred */ +#define TWIM_ERRORSRC_DNACK_NotReceived (0x0UL) /*!< Error did not occur */ +#define TWIM_ERRORSRC_DNACK_Received (0x1UL) /*!< Error occurred */ /* Bit 1 : NACK received after sending the address (write '1' to clear) */ #define TWIM_ERRORSRC_ANACK_Pos (1UL) /*!< Position of ANACK field. */ #define TWIM_ERRORSRC_ANACK_Msk (0x1UL << TWIM_ERRORSRC_ANACK_Pos) /*!< Bit mask of ANACK field. */ -#define TWIM_ERRORSRC_ANACK_NotReceived (0UL) /*!< Error did not occur */ -#define TWIM_ERRORSRC_ANACK_Received (1UL) /*!< Error occurred */ +#define TWIM_ERRORSRC_ANACK_NotReceived (0x0UL) /*!< Error did not occur */ +#define TWIM_ERRORSRC_ANACK_Received (0x1UL) /*!< Error occurred */ /* Bit 0 : Overrun error */ #define TWIM_ERRORSRC_OVERRUN_Pos (0UL) /*!< Position of OVERRUN field. */ #define TWIM_ERRORSRC_OVERRUN_Msk (0x1UL << TWIM_ERRORSRC_OVERRUN_Pos) /*!< Bit mask of OVERRUN field. */ -#define TWIM_ERRORSRC_OVERRUN_NotReceived (0UL) /*!< Error did not occur */ -#define TWIM_ERRORSRC_OVERRUN_Received (1UL) /*!< Error occurred */ +#define TWIM_ERRORSRC_OVERRUN_NotReceived (0x0UL) /*!< Error did not occur */ +#define TWIM_ERRORSRC_OVERRUN_Received (0x1UL) /*!< Error occurred */ /* Register: TWIM_ENABLE */ /* Description: Enable TWIM */ @@ -9296,8 +9296,8 @@ POSSIBILITY OF SUCH DAMAGE. /* Bits 3..0 : Enable or disable TWIM */ #define TWIM_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ #define TWIM_ENABLE_ENABLE_Msk (0xFUL << TWIM_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ -#define TWIM_ENABLE_ENABLE_Disabled (0UL) /*!< Disable TWIM */ -#define TWIM_ENABLE_ENABLE_Enabled (6UL) /*!< Enable TWIM */ +#define TWIM_ENABLE_ENABLE_Disabled (0x0UL) /*!< Disable TWIM */ +#define TWIM_ENABLE_ENABLE_Enabled (0x6UL) /*!< Enable TWIM */ /* Register: TWIM_PSEL_SCL */ /* Description: Pin select for SCL signal */ @@ -9305,8 +9305,8 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 31 : Connection */ #define TWIM_PSEL_SCL_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ #define TWIM_PSEL_SCL_CONNECT_Msk (0x1UL << TWIM_PSEL_SCL_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ -#define TWIM_PSEL_SCL_CONNECT_Connected (0UL) /*!< Connect */ -#define TWIM_PSEL_SCL_CONNECT_Disconnected (1UL) /*!< Disconnect */ +#define TWIM_PSEL_SCL_CONNECT_Connected (0x0UL) /*!< Connect */ +#define TWIM_PSEL_SCL_CONNECT_Disconnected (0x1UL) /*!< Disconnect */ /* Bits 4..0 : Pin number */ #define TWIM_PSEL_SCL_PIN_Pos (0UL) /*!< Position of PIN field. */ @@ -9318,8 +9318,8 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 31 : Connection */ #define TWIM_PSEL_SDA_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ #define TWIM_PSEL_SDA_CONNECT_Msk (0x1UL << TWIM_PSEL_SDA_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ -#define TWIM_PSEL_SDA_CONNECT_Connected (0UL) /*!< Connect */ -#define TWIM_PSEL_SDA_CONNECT_Disconnected (1UL) /*!< Disconnect */ +#define TWIM_PSEL_SDA_CONNECT_Connected (0x0UL) /*!< Connect */ +#define TWIM_PSEL_SDA_CONNECT_Disconnected (0x1UL) /*!< Disconnect */ /* Bits 4..0 : Pin number */ #define TWIM_PSEL_SDA_PIN_Pos (0UL) /*!< Position of PIN field. */ @@ -9362,8 +9362,8 @@ POSSIBILITY OF SUCH DAMAGE. /* Bits 1..0 : List type */ #define TWIM_RXD_LIST_LIST_Pos (0UL) /*!< Position of LIST field. */ #define TWIM_RXD_LIST_LIST_Msk (0x3UL << TWIM_RXD_LIST_LIST_Pos) /*!< Bit mask of LIST field. */ -#define TWIM_RXD_LIST_LIST_Disabled (0UL) /*!< Disable EasyDMA list */ -#define TWIM_RXD_LIST_LIST_ArrayList (1UL) /*!< Use array list */ +#define TWIM_RXD_LIST_LIST_Disabled (0x0UL) /*!< Disable EasyDMA list */ +#define TWIM_RXD_LIST_LIST_ArrayList (0x1UL) /*!< Use array list */ /* Register: TWIM_TXD_PTR */ /* Description: Data pointer */ @@ -9392,8 +9392,8 @@ POSSIBILITY OF SUCH DAMAGE. /* Bits 1..0 : List type */ #define TWIM_TXD_LIST_LIST_Pos (0UL) /*!< Position of LIST field. */ #define TWIM_TXD_LIST_LIST_Msk (0x3UL << TWIM_TXD_LIST_LIST_Pos) /*!< Bit mask of LIST field. */ -#define TWIM_TXD_LIST_LIST_Disabled (0UL) /*!< Disable EasyDMA list */ -#define TWIM_TXD_LIST_LIST_ArrayList (1UL) /*!< Use array list */ +#define TWIM_TXD_LIST_LIST_Disabled (0x0UL) /*!< Disable EasyDMA list */ +#define TWIM_TXD_LIST_LIST_ArrayList (0x1UL) /*!< Use array list */ /* Register: TWIM_ADDRESS */ /* Description: Address used in the TWI transfer */ @@ -9412,7 +9412,7 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 0 : Stop TWI transaction */ #define TWIS_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */ #define TWIS_TASKS_STOP_TASKS_STOP_Msk (0x1UL << TWIS_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */ -#define TWIS_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */ +#define TWIS_TASKS_STOP_TASKS_STOP_Trigger (0x1UL) /*!< Trigger task */ /* Register: TWIS_TASKS_SUSPEND */ /* Description: Suspend TWI transaction */ @@ -9420,7 +9420,7 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 0 : Suspend TWI transaction */ #define TWIS_TASKS_SUSPEND_TASKS_SUSPEND_Pos (0UL) /*!< Position of TASKS_SUSPEND field. */ #define TWIS_TASKS_SUSPEND_TASKS_SUSPEND_Msk (0x1UL << TWIS_TASKS_SUSPEND_TASKS_SUSPEND_Pos) /*!< Bit mask of TASKS_SUSPEND field. */ -#define TWIS_TASKS_SUSPEND_TASKS_SUSPEND_Trigger (1UL) /*!< Trigger task */ +#define TWIS_TASKS_SUSPEND_TASKS_SUSPEND_Trigger (0x1UL) /*!< Trigger task */ /* Register: TWIS_TASKS_RESUME */ /* Description: Resume TWI transaction */ @@ -9428,7 +9428,7 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 0 : Resume TWI transaction */ #define TWIS_TASKS_RESUME_TASKS_RESUME_Pos (0UL) /*!< Position of TASKS_RESUME field. */ #define TWIS_TASKS_RESUME_TASKS_RESUME_Msk (0x1UL << TWIS_TASKS_RESUME_TASKS_RESUME_Pos) /*!< Bit mask of TASKS_RESUME field. */ -#define TWIS_TASKS_RESUME_TASKS_RESUME_Trigger (1UL) /*!< Trigger task */ +#define TWIS_TASKS_RESUME_TASKS_RESUME_Trigger (0x1UL) /*!< Trigger task */ /* Register: TWIS_TASKS_PREPARERX */ /* Description: Prepare the TWI slave to respond to a write command */ @@ -9436,7 +9436,7 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 0 : Prepare the TWI slave to respond to a write command */ #define TWIS_TASKS_PREPARERX_TASKS_PREPARERX_Pos (0UL) /*!< Position of TASKS_PREPARERX field. */ #define TWIS_TASKS_PREPARERX_TASKS_PREPARERX_Msk (0x1UL << TWIS_TASKS_PREPARERX_TASKS_PREPARERX_Pos) /*!< Bit mask of TASKS_PREPARERX field. */ -#define TWIS_TASKS_PREPARERX_TASKS_PREPARERX_Trigger (1UL) /*!< Trigger task */ +#define TWIS_TASKS_PREPARERX_TASKS_PREPARERX_Trigger (0x1UL) /*!< Trigger task */ /* Register: TWIS_TASKS_PREPARETX */ /* Description: Prepare the TWI slave to respond to a read command */ @@ -9444,7 +9444,7 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 0 : Prepare the TWI slave to respond to a read command */ #define TWIS_TASKS_PREPARETX_TASKS_PREPARETX_Pos (0UL) /*!< Position of TASKS_PREPARETX field. */ #define TWIS_TASKS_PREPARETX_TASKS_PREPARETX_Msk (0x1UL << TWIS_TASKS_PREPARETX_TASKS_PREPARETX_Pos) /*!< Bit mask of TASKS_PREPARETX field. */ -#define TWIS_TASKS_PREPARETX_TASKS_PREPARETX_Trigger (1UL) /*!< Trigger task */ +#define TWIS_TASKS_PREPARETX_TASKS_PREPARETX_Trigger (0x1UL) /*!< Trigger task */ /* Register: TWIS_SUBSCRIBE_STOP */ /* Description: Subscribe configuration for task STOP */ @@ -9452,8 +9452,8 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 31 : */ #define TWIS_SUBSCRIBE_STOP_EN_Pos (31UL) /*!< Position of EN field. */ #define TWIS_SUBSCRIBE_STOP_EN_Msk (0x1UL << TWIS_SUBSCRIBE_STOP_EN_Pos) /*!< Bit mask of EN field. */ -#define TWIS_SUBSCRIBE_STOP_EN_Disabled (0UL) /*!< Disable subscription */ -#define TWIS_SUBSCRIBE_STOP_EN_Enabled (1UL) /*!< Enable subscription */ +#define TWIS_SUBSCRIBE_STOP_EN_Disabled (0x0UL) /*!< Disable subscription */ +#define TWIS_SUBSCRIBE_STOP_EN_Enabled (0x1UL) /*!< Enable subscription */ /* Bits 7..0 : DPPI channel that task STOP will subscribe to */ #define TWIS_SUBSCRIBE_STOP_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ @@ -9465,8 +9465,8 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 31 : */ #define TWIS_SUBSCRIBE_SUSPEND_EN_Pos (31UL) /*!< Position of EN field. */ #define TWIS_SUBSCRIBE_SUSPEND_EN_Msk (0x1UL << TWIS_SUBSCRIBE_SUSPEND_EN_Pos) /*!< Bit mask of EN field. */ -#define TWIS_SUBSCRIBE_SUSPEND_EN_Disabled (0UL) /*!< Disable subscription */ -#define TWIS_SUBSCRIBE_SUSPEND_EN_Enabled (1UL) /*!< Enable subscription */ +#define TWIS_SUBSCRIBE_SUSPEND_EN_Disabled (0x0UL) /*!< Disable subscription */ +#define TWIS_SUBSCRIBE_SUSPEND_EN_Enabled (0x1UL) /*!< Enable subscription */ /* Bits 7..0 : DPPI channel that task SUSPEND will subscribe to */ #define TWIS_SUBSCRIBE_SUSPEND_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ @@ -9478,8 +9478,8 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 31 : */ #define TWIS_SUBSCRIBE_RESUME_EN_Pos (31UL) /*!< Position of EN field. */ #define TWIS_SUBSCRIBE_RESUME_EN_Msk (0x1UL << TWIS_SUBSCRIBE_RESUME_EN_Pos) /*!< Bit mask of EN field. */ -#define TWIS_SUBSCRIBE_RESUME_EN_Disabled (0UL) /*!< Disable subscription */ -#define TWIS_SUBSCRIBE_RESUME_EN_Enabled (1UL) /*!< Enable subscription */ +#define TWIS_SUBSCRIBE_RESUME_EN_Disabled (0x0UL) /*!< Disable subscription */ +#define TWIS_SUBSCRIBE_RESUME_EN_Enabled (0x1UL) /*!< Enable subscription */ /* Bits 7..0 : DPPI channel that task RESUME will subscribe to */ #define TWIS_SUBSCRIBE_RESUME_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ @@ -9491,8 +9491,8 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 31 : */ #define TWIS_SUBSCRIBE_PREPARERX_EN_Pos (31UL) /*!< Position of EN field. */ #define TWIS_SUBSCRIBE_PREPARERX_EN_Msk (0x1UL << TWIS_SUBSCRIBE_PREPARERX_EN_Pos) /*!< Bit mask of EN field. */ -#define TWIS_SUBSCRIBE_PREPARERX_EN_Disabled (0UL) /*!< Disable subscription */ -#define TWIS_SUBSCRIBE_PREPARERX_EN_Enabled (1UL) /*!< Enable subscription */ +#define TWIS_SUBSCRIBE_PREPARERX_EN_Disabled (0x0UL) /*!< Disable subscription */ +#define TWIS_SUBSCRIBE_PREPARERX_EN_Enabled (0x1UL) /*!< Enable subscription */ /* Bits 7..0 : DPPI channel that task PREPARERX will subscribe to */ #define TWIS_SUBSCRIBE_PREPARERX_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ @@ -9504,8 +9504,8 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 31 : */ #define TWIS_SUBSCRIBE_PREPARETX_EN_Pos (31UL) /*!< Position of EN field. */ #define TWIS_SUBSCRIBE_PREPARETX_EN_Msk (0x1UL << TWIS_SUBSCRIBE_PREPARETX_EN_Pos) /*!< Bit mask of EN field. */ -#define TWIS_SUBSCRIBE_PREPARETX_EN_Disabled (0UL) /*!< Disable subscription */ -#define TWIS_SUBSCRIBE_PREPARETX_EN_Enabled (1UL) /*!< Enable subscription */ +#define TWIS_SUBSCRIBE_PREPARETX_EN_Disabled (0x0UL) /*!< Disable subscription */ +#define TWIS_SUBSCRIBE_PREPARETX_EN_Enabled (0x1UL) /*!< Enable subscription */ /* Bits 7..0 : DPPI channel that task PREPARETX will subscribe to */ #define TWIS_SUBSCRIBE_PREPARETX_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ @@ -9517,8 +9517,8 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 0 : TWI stopped */ #define TWIS_EVENTS_STOPPED_EVENTS_STOPPED_Pos (0UL) /*!< Position of EVENTS_STOPPED field. */ #define TWIS_EVENTS_STOPPED_EVENTS_STOPPED_Msk (0x1UL << TWIS_EVENTS_STOPPED_EVENTS_STOPPED_Pos) /*!< Bit mask of EVENTS_STOPPED field. */ -#define TWIS_EVENTS_STOPPED_EVENTS_STOPPED_NotGenerated (0UL) /*!< Event not generated */ -#define TWIS_EVENTS_STOPPED_EVENTS_STOPPED_Generated (1UL) /*!< Event generated */ +#define TWIS_EVENTS_STOPPED_EVENTS_STOPPED_NotGenerated (0x0UL) /*!< Event not generated */ +#define TWIS_EVENTS_STOPPED_EVENTS_STOPPED_Generated (0x1UL) /*!< Event generated */ /* Register: TWIS_EVENTS_ERROR */ /* Description: TWI error */ @@ -9526,8 +9526,8 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 0 : TWI error */ #define TWIS_EVENTS_ERROR_EVENTS_ERROR_Pos (0UL) /*!< Position of EVENTS_ERROR field. */ #define TWIS_EVENTS_ERROR_EVENTS_ERROR_Msk (0x1UL << TWIS_EVENTS_ERROR_EVENTS_ERROR_Pos) /*!< Bit mask of EVENTS_ERROR field. */ -#define TWIS_EVENTS_ERROR_EVENTS_ERROR_NotGenerated (0UL) /*!< Event not generated */ -#define TWIS_EVENTS_ERROR_EVENTS_ERROR_Generated (1UL) /*!< Event generated */ +#define TWIS_EVENTS_ERROR_EVENTS_ERROR_NotGenerated (0x0UL) /*!< Event not generated */ +#define TWIS_EVENTS_ERROR_EVENTS_ERROR_Generated (0x1UL) /*!< Event generated */ /* Register: TWIS_EVENTS_RXSTARTED */ /* Description: Receive sequence started */ @@ -9535,8 +9535,8 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 0 : Receive sequence started */ #define TWIS_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Pos (0UL) /*!< Position of EVENTS_RXSTARTED field. */ #define TWIS_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Msk (0x1UL << TWIS_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Pos) /*!< Bit mask of EVENTS_RXSTARTED field. */ -#define TWIS_EVENTS_RXSTARTED_EVENTS_RXSTARTED_NotGenerated (0UL) /*!< Event not generated */ -#define TWIS_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Generated (1UL) /*!< Event generated */ +#define TWIS_EVENTS_RXSTARTED_EVENTS_RXSTARTED_NotGenerated (0x0UL) /*!< Event not generated */ +#define TWIS_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Generated (0x1UL) /*!< Event generated */ /* Register: TWIS_EVENTS_TXSTARTED */ /* Description: Transmit sequence started */ @@ -9544,8 +9544,8 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 0 : Transmit sequence started */ #define TWIS_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Pos (0UL) /*!< Position of EVENTS_TXSTARTED field. */ #define TWIS_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Msk (0x1UL << TWIS_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Pos) /*!< Bit mask of EVENTS_TXSTARTED field. */ -#define TWIS_EVENTS_TXSTARTED_EVENTS_TXSTARTED_NotGenerated (0UL) /*!< Event not generated */ -#define TWIS_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Generated (1UL) /*!< Event generated */ +#define TWIS_EVENTS_TXSTARTED_EVENTS_TXSTARTED_NotGenerated (0x0UL) /*!< Event not generated */ +#define TWIS_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Generated (0x1UL) /*!< Event generated */ /* Register: TWIS_EVENTS_WRITE */ /* Description: Write command received */ @@ -9553,8 +9553,8 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 0 : Write command received */ #define TWIS_EVENTS_WRITE_EVENTS_WRITE_Pos (0UL) /*!< Position of EVENTS_WRITE field. */ #define TWIS_EVENTS_WRITE_EVENTS_WRITE_Msk (0x1UL << TWIS_EVENTS_WRITE_EVENTS_WRITE_Pos) /*!< Bit mask of EVENTS_WRITE field. */ -#define TWIS_EVENTS_WRITE_EVENTS_WRITE_NotGenerated (0UL) /*!< Event not generated */ -#define TWIS_EVENTS_WRITE_EVENTS_WRITE_Generated (1UL) /*!< Event generated */ +#define TWIS_EVENTS_WRITE_EVENTS_WRITE_NotGenerated (0x0UL) /*!< Event not generated */ +#define TWIS_EVENTS_WRITE_EVENTS_WRITE_Generated (0x1UL) /*!< Event generated */ /* Register: TWIS_EVENTS_READ */ /* Description: Read command received */ @@ -9562,8 +9562,8 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 0 : Read command received */ #define TWIS_EVENTS_READ_EVENTS_READ_Pos (0UL) /*!< Position of EVENTS_READ field. */ #define TWIS_EVENTS_READ_EVENTS_READ_Msk (0x1UL << TWIS_EVENTS_READ_EVENTS_READ_Pos) /*!< Bit mask of EVENTS_READ field. */ -#define TWIS_EVENTS_READ_EVENTS_READ_NotGenerated (0UL) /*!< Event not generated */ -#define TWIS_EVENTS_READ_EVENTS_READ_Generated (1UL) /*!< Event generated */ +#define TWIS_EVENTS_READ_EVENTS_READ_NotGenerated (0x0UL) /*!< Event not generated */ +#define TWIS_EVENTS_READ_EVENTS_READ_Generated (0x1UL) /*!< Event generated */ /* Register: TWIS_PUBLISH_STOPPED */ /* Description: Publish configuration for event STOPPED */ @@ -9571,8 +9571,8 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 31 : */ #define TWIS_PUBLISH_STOPPED_EN_Pos (31UL) /*!< Position of EN field. */ #define TWIS_PUBLISH_STOPPED_EN_Msk (0x1UL << TWIS_PUBLISH_STOPPED_EN_Pos) /*!< Bit mask of EN field. */ -#define TWIS_PUBLISH_STOPPED_EN_Disabled (0UL) /*!< Disable publishing */ -#define TWIS_PUBLISH_STOPPED_EN_Enabled (1UL) /*!< Enable publishing */ +#define TWIS_PUBLISH_STOPPED_EN_Disabled (0x0UL) /*!< Disable publishing */ +#define TWIS_PUBLISH_STOPPED_EN_Enabled (0x1UL) /*!< Enable publishing */ /* Bits 7..0 : DPPI channel that event STOPPED will publish to */ #define TWIS_PUBLISH_STOPPED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ @@ -9584,8 +9584,8 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 31 : */ #define TWIS_PUBLISH_ERROR_EN_Pos (31UL) /*!< Position of EN field. */ #define TWIS_PUBLISH_ERROR_EN_Msk (0x1UL << TWIS_PUBLISH_ERROR_EN_Pos) /*!< Bit mask of EN field. */ -#define TWIS_PUBLISH_ERROR_EN_Disabled (0UL) /*!< Disable publishing */ -#define TWIS_PUBLISH_ERROR_EN_Enabled (1UL) /*!< Enable publishing */ +#define TWIS_PUBLISH_ERROR_EN_Disabled (0x0UL) /*!< Disable publishing */ +#define TWIS_PUBLISH_ERROR_EN_Enabled (0x1UL) /*!< Enable publishing */ /* Bits 7..0 : DPPI channel that event ERROR will publish to */ #define TWIS_PUBLISH_ERROR_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ @@ -9597,8 +9597,8 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 31 : */ #define TWIS_PUBLISH_RXSTARTED_EN_Pos (31UL) /*!< Position of EN field. */ #define TWIS_PUBLISH_RXSTARTED_EN_Msk (0x1UL << TWIS_PUBLISH_RXSTARTED_EN_Pos) /*!< Bit mask of EN field. */ -#define TWIS_PUBLISH_RXSTARTED_EN_Disabled (0UL) /*!< Disable publishing */ -#define TWIS_PUBLISH_RXSTARTED_EN_Enabled (1UL) /*!< Enable publishing */ +#define TWIS_PUBLISH_RXSTARTED_EN_Disabled (0x0UL) /*!< Disable publishing */ +#define TWIS_PUBLISH_RXSTARTED_EN_Enabled (0x1UL) /*!< Enable publishing */ /* Bits 7..0 : DPPI channel that event RXSTARTED will publish to */ #define TWIS_PUBLISH_RXSTARTED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ @@ -9610,8 +9610,8 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 31 : */ #define TWIS_PUBLISH_TXSTARTED_EN_Pos (31UL) /*!< Position of EN field. */ #define TWIS_PUBLISH_TXSTARTED_EN_Msk (0x1UL << TWIS_PUBLISH_TXSTARTED_EN_Pos) /*!< Bit mask of EN field. */ -#define TWIS_PUBLISH_TXSTARTED_EN_Disabled (0UL) /*!< Disable publishing */ -#define TWIS_PUBLISH_TXSTARTED_EN_Enabled (1UL) /*!< Enable publishing */ +#define TWIS_PUBLISH_TXSTARTED_EN_Disabled (0x0UL) /*!< Disable publishing */ +#define TWIS_PUBLISH_TXSTARTED_EN_Enabled (0x1UL) /*!< Enable publishing */ /* Bits 7..0 : DPPI channel that event TXSTARTED will publish to */ #define TWIS_PUBLISH_TXSTARTED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ @@ -9623,8 +9623,8 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 31 : */ #define TWIS_PUBLISH_WRITE_EN_Pos (31UL) /*!< Position of EN field. */ #define TWIS_PUBLISH_WRITE_EN_Msk (0x1UL << TWIS_PUBLISH_WRITE_EN_Pos) /*!< Bit mask of EN field. */ -#define TWIS_PUBLISH_WRITE_EN_Disabled (0UL) /*!< Disable publishing */ -#define TWIS_PUBLISH_WRITE_EN_Enabled (1UL) /*!< Enable publishing */ +#define TWIS_PUBLISH_WRITE_EN_Disabled (0x0UL) /*!< Disable publishing */ +#define TWIS_PUBLISH_WRITE_EN_Enabled (0x1UL) /*!< Enable publishing */ /* Bits 7..0 : DPPI channel that event WRITE will publish to */ #define TWIS_PUBLISH_WRITE_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ @@ -9636,8 +9636,8 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 31 : */ #define TWIS_PUBLISH_READ_EN_Pos (31UL) /*!< Position of EN field. */ #define TWIS_PUBLISH_READ_EN_Msk (0x1UL << TWIS_PUBLISH_READ_EN_Pos) /*!< Bit mask of EN field. */ -#define TWIS_PUBLISH_READ_EN_Disabled (0UL) /*!< Disable publishing */ -#define TWIS_PUBLISH_READ_EN_Enabled (1UL) /*!< Enable publishing */ +#define TWIS_PUBLISH_READ_EN_Disabled (0x0UL) /*!< Disable publishing */ +#define TWIS_PUBLISH_READ_EN_Enabled (0x1UL) /*!< Enable publishing */ /* Bits 7..0 : DPPI channel that event READ will publish to */ #define TWIS_PUBLISH_READ_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ @@ -9649,14 +9649,14 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 14 : Shortcut between event READ and task SUSPEND */ #define TWIS_SHORTS_READ_SUSPEND_Pos (14UL) /*!< Position of READ_SUSPEND field. */ #define TWIS_SHORTS_READ_SUSPEND_Msk (0x1UL << TWIS_SHORTS_READ_SUSPEND_Pos) /*!< Bit mask of READ_SUSPEND field. */ -#define TWIS_SHORTS_READ_SUSPEND_Disabled (0UL) /*!< Disable shortcut */ -#define TWIS_SHORTS_READ_SUSPEND_Enabled (1UL) /*!< Enable shortcut */ +#define TWIS_SHORTS_READ_SUSPEND_Disabled (0x0UL) /*!< Disable shortcut */ +#define TWIS_SHORTS_READ_SUSPEND_Enabled (0x1UL) /*!< Enable shortcut */ /* Bit 13 : Shortcut between event WRITE and task SUSPEND */ #define TWIS_SHORTS_WRITE_SUSPEND_Pos (13UL) /*!< Position of WRITE_SUSPEND field. */ #define TWIS_SHORTS_WRITE_SUSPEND_Msk (0x1UL << TWIS_SHORTS_WRITE_SUSPEND_Pos) /*!< Bit mask of WRITE_SUSPEND field. */ -#define TWIS_SHORTS_WRITE_SUSPEND_Disabled (0UL) /*!< Disable shortcut */ -#define TWIS_SHORTS_WRITE_SUSPEND_Enabled (1UL) /*!< Enable shortcut */ +#define TWIS_SHORTS_WRITE_SUSPEND_Disabled (0x0UL) /*!< Disable shortcut */ +#define TWIS_SHORTS_WRITE_SUSPEND_Enabled (0x1UL) /*!< Enable shortcut */ /* Register: TWIS_INTEN */ /* Description: Enable or disable interrupt */ @@ -9664,38 +9664,38 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 26 : Enable or disable interrupt for event READ */ #define TWIS_INTEN_READ_Pos (26UL) /*!< Position of READ field. */ #define TWIS_INTEN_READ_Msk (0x1UL << TWIS_INTEN_READ_Pos) /*!< Bit mask of READ field. */ -#define TWIS_INTEN_READ_Disabled (0UL) /*!< Disable */ -#define TWIS_INTEN_READ_Enabled (1UL) /*!< Enable */ +#define TWIS_INTEN_READ_Disabled (0x0UL) /*!< Disable */ +#define TWIS_INTEN_READ_Enabled (0x1UL) /*!< Enable */ /* Bit 25 : Enable or disable interrupt for event WRITE */ #define TWIS_INTEN_WRITE_Pos (25UL) /*!< Position of WRITE field. */ #define TWIS_INTEN_WRITE_Msk (0x1UL << TWIS_INTEN_WRITE_Pos) /*!< Bit mask of WRITE field. */ -#define TWIS_INTEN_WRITE_Disabled (0UL) /*!< Disable */ -#define TWIS_INTEN_WRITE_Enabled (1UL) /*!< Enable */ +#define TWIS_INTEN_WRITE_Disabled (0x0UL) /*!< Disable */ +#define TWIS_INTEN_WRITE_Enabled (0x1UL) /*!< Enable */ /* Bit 20 : Enable or disable interrupt for event TXSTARTED */ #define TWIS_INTEN_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */ #define TWIS_INTEN_TXSTARTED_Msk (0x1UL << TWIS_INTEN_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */ -#define TWIS_INTEN_TXSTARTED_Disabled (0UL) /*!< Disable */ -#define TWIS_INTEN_TXSTARTED_Enabled (1UL) /*!< Enable */ +#define TWIS_INTEN_TXSTARTED_Disabled (0x0UL) /*!< Disable */ +#define TWIS_INTEN_TXSTARTED_Enabled (0x1UL) /*!< Enable */ /* Bit 19 : Enable or disable interrupt for event RXSTARTED */ #define TWIS_INTEN_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */ #define TWIS_INTEN_RXSTARTED_Msk (0x1UL << TWIS_INTEN_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */ -#define TWIS_INTEN_RXSTARTED_Disabled (0UL) /*!< Disable */ -#define TWIS_INTEN_RXSTARTED_Enabled (1UL) /*!< Enable */ +#define TWIS_INTEN_RXSTARTED_Disabled (0x0UL) /*!< Disable */ +#define TWIS_INTEN_RXSTARTED_Enabled (0x1UL) /*!< Enable */ /* Bit 9 : Enable or disable interrupt for event ERROR */ #define TWIS_INTEN_ERROR_Pos (9UL) /*!< Position of ERROR field. */ #define TWIS_INTEN_ERROR_Msk (0x1UL << TWIS_INTEN_ERROR_Pos) /*!< Bit mask of ERROR field. */ -#define TWIS_INTEN_ERROR_Disabled (0UL) /*!< Disable */ -#define TWIS_INTEN_ERROR_Enabled (1UL) /*!< Enable */ +#define TWIS_INTEN_ERROR_Disabled (0x0UL) /*!< Disable */ +#define TWIS_INTEN_ERROR_Enabled (0x1UL) /*!< Enable */ /* Bit 1 : Enable or disable interrupt for event STOPPED */ #define TWIS_INTEN_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ #define TWIS_INTEN_STOPPED_Msk (0x1UL << TWIS_INTEN_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ -#define TWIS_INTEN_STOPPED_Disabled (0UL) /*!< Disable */ -#define TWIS_INTEN_STOPPED_Enabled (1UL) /*!< Enable */ +#define TWIS_INTEN_STOPPED_Disabled (0x0UL) /*!< Disable */ +#define TWIS_INTEN_STOPPED_Enabled (0x1UL) /*!< Enable */ /* Register: TWIS_INTENSET */ /* Description: Enable interrupt */ @@ -9703,44 +9703,44 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 26 : Write '1' to enable interrupt for event READ */ #define TWIS_INTENSET_READ_Pos (26UL) /*!< Position of READ field. */ #define TWIS_INTENSET_READ_Msk (0x1UL << TWIS_INTENSET_READ_Pos) /*!< Bit mask of READ field. */ -#define TWIS_INTENSET_READ_Disabled (0UL) /*!< Read: Disabled */ -#define TWIS_INTENSET_READ_Enabled (1UL) /*!< Read: Enabled */ -#define TWIS_INTENSET_READ_Set (1UL) /*!< Enable */ +#define TWIS_INTENSET_READ_Disabled (0x0UL) /*!< Read: Disabled */ +#define TWIS_INTENSET_READ_Enabled (0x1UL) /*!< Read: Enabled */ +#define TWIS_INTENSET_READ_Set (0x1UL) /*!< Enable */ /* Bit 25 : Write '1' to enable interrupt for event WRITE */ #define TWIS_INTENSET_WRITE_Pos (25UL) /*!< Position of WRITE field. */ #define TWIS_INTENSET_WRITE_Msk (0x1UL << TWIS_INTENSET_WRITE_Pos) /*!< Bit mask of WRITE field. */ -#define TWIS_INTENSET_WRITE_Disabled (0UL) /*!< Read: Disabled */ -#define TWIS_INTENSET_WRITE_Enabled (1UL) /*!< Read: Enabled */ -#define TWIS_INTENSET_WRITE_Set (1UL) /*!< Enable */ +#define TWIS_INTENSET_WRITE_Disabled (0x0UL) /*!< Read: Disabled */ +#define TWIS_INTENSET_WRITE_Enabled (0x1UL) /*!< Read: Enabled */ +#define TWIS_INTENSET_WRITE_Set (0x1UL) /*!< Enable */ /* Bit 20 : Write '1' to enable interrupt for event TXSTARTED */ #define TWIS_INTENSET_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */ #define TWIS_INTENSET_TXSTARTED_Msk (0x1UL << TWIS_INTENSET_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */ -#define TWIS_INTENSET_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */ -#define TWIS_INTENSET_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */ -#define TWIS_INTENSET_TXSTARTED_Set (1UL) /*!< Enable */ +#define TWIS_INTENSET_TXSTARTED_Disabled (0x0UL) /*!< Read: Disabled */ +#define TWIS_INTENSET_TXSTARTED_Enabled (0x1UL) /*!< Read: Enabled */ +#define TWIS_INTENSET_TXSTARTED_Set (0x1UL) /*!< Enable */ /* Bit 19 : Write '1' to enable interrupt for event RXSTARTED */ #define TWIS_INTENSET_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */ #define TWIS_INTENSET_RXSTARTED_Msk (0x1UL << TWIS_INTENSET_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */ -#define TWIS_INTENSET_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */ -#define TWIS_INTENSET_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */ -#define TWIS_INTENSET_RXSTARTED_Set (1UL) /*!< Enable */ +#define TWIS_INTENSET_RXSTARTED_Disabled (0x0UL) /*!< Read: Disabled */ +#define TWIS_INTENSET_RXSTARTED_Enabled (0x1UL) /*!< Read: Enabled */ +#define TWIS_INTENSET_RXSTARTED_Set (0x1UL) /*!< Enable */ /* Bit 9 : Write '1' to enable interrupt for event ERROR */ #define TWIS_INTENSET_ERROR_Pos (9UL) /*!< Position of ERROR field. */ #define TWIS_INTENSET_ERROR_Msk (0x1UL << TWIS_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */ -#define TWIS_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */ -#define TWIS_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */ -#define TWIS_INTENSET_ERROR_Set (1UL) /*!< Enable */ +#define TWIS_INTENSET_ERROR_Disabled (0x0UL) /*!< Read: Disabled */ +#define TWIS_INTENSET_ERROR_Enabled (0x1UL) /*!< Read: Enabled */ +#define TWIS_INTENSET_ERROR_Set (0x1UL) /*!< Enable */ /* Bit 1 : Write '1' to enable interrupt for event STOPPED */ #define TWIS_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ #define TWIS_INTENSET_STOPPED_Msk (0x1UL << TWIS_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ -#define TWIS_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */ -#define TWIS_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */ -#define TWIS_INTENSET_STOPPED_Set (1UL) /*!< Enable */ +#define TWIS_INTENSET_STOPPED_Disabled (0x0UL) /*!< Read: Disabled */ +#define TWIS_INTENSET_STOPPED_Enabled (0x1UL) /*!< Read: Enabled */ +#define TWIS_INTENSET_STOPPED_Set (0x1UL) /*!< Enable */ /* Register: TWIS_INTENCLR */ /* Description: Disable interrupt */ @@ -9748,44 +9748,44 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 26 : Write '1' to disable interrupt for event READ */ #define TWIS_INTENCLR_READ_Pos (26UL) /*!< Position of READ field. */ #define TWIS_INTENCLR_READ_Msk (0x1UL << TWIS_INTENCLR_READ_Pos) /*!< Bit mask of READ field. */ -#define TWIS_INTENCLR_READ_Disabled (0UL) /*!< Read: Disabled */ -#define TWIS_INTENCLR_READ_Enabled (1UL) /*!< Read: Enabled */ -#define TWIS_INTENCLR_READ_Clear (1UL) /*!< Disable */ +#define TWIS_INTENCLR_READ_Disabled (0x0UL) /*!< Read: Disabled */ +#define TWIS_INTENCLR_READ_Enabled (0x1UL) /*!< Read: Enabled */ +#define TWIS_INTENCLR_READ_Clear (0x1UL) /*!< Disable */ /* Bit 25 : Write '1' to disable interrupt for event WRITE */ #define TWIS_INTENCLR_WRITE_Pos (25UL) /*!< Position of WRITE field. */ #define TWIS_INTENCLR_WRITE_Msk (0x1UL << TWIS_INTENCLR_WRITE_Pos) /*!< Bit mask of WRITE field. */ -#define TWIS_INTENCLR_WRITE_Disabled (0UL) /*!< Read: Disabled */ -#define TWIS_INTENCLR_WRITE_Enabled (1UL) /*!< Read: Enabled */ -#define TWIS_INTENCLR_WRITE_Clear (1UL) /*!< Disable */ +#define TWIS_INTENCLR_WRITE_Disabled (0x0UL) /*!< Read: Disabled */ +#define TWIS_INTENCLR_WRITE_Enabled (0x1UL) /*!< Read: Enabled */ +#define TWIS_INTENCLR_WRITE_Clear (0x1UL) /*!< Disable */ /* Bit 20 : Write '1' to disable interrupt for event TXSTARTED */ #define TWIS_INTENCLR_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */ #define TWIS_INTENCLR_TXSTARTED_Msk (0x1UL << TWIS_INTENCLR_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */ -#define TWIS_INTENCLR_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */ -#define TWIS_INTENCLR_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */ -#define TWIS_INTENCLR_TXSTARTED_Clear (1UL) /*!< Disable */ +#define TWIS_INTENCLR_TXSTARTED_Disabled (0x0UL) /*!< Read: Disabled */ +#define TWIS_INTENCLR_TXSTARTED_Enabled (0x1UL) /*!< Read: Enabled */ +#define TWIS_INTENCLR_TXSTARTED_Clear (0x1UL) /*!< Disable */ /* Bit 19 : Write '1' to disable interrupt for event RXSTARTED */ #define TWIS_INTENCLR_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */ #define TWIS_INTENCLR_RXSTARTED_Msk (0x1UL << TWIS_INTENCLR_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */ -#define TWIS_INTENCLR_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */ -#define TWIS_INTENCLR_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */ -#define TWIS_INTENCLR_RXSTARTED_Clear (1UL) /*!< Disable */ +#define TWIS_INTENCLR_RXSTARTED_Disabled (0x0UL) /*!< Read: Disabled */ +#define TWIS_INTENCLR_RXSTARTED_Enabled (0x1UL) /*!< Read: Enabled */ +#define TWIS_INTENCLR_RXSTARTED_Clear (0x1UL) /*!< Disable */ /* Bit 9 : Write '1' to disable interrupt for event ERROR */ #define TWIS_INTENCLR_ERROR_Pos (9UL) /*!< Position of ERROR field. */ #define TWIS_INTENCLR_ERROR_Msk (0x1UL << TWIS_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */ -#define TWIS_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */ -#define TWIS_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */ -#define TWIS_INTENCLR_ERROR_Clear (1UL) /*!< Disable */ +#define TWIS_INTENCLR_ERROR_Disabled (0x0UL) /*!< Read: Disabled */ +#define TWIS_INTENCLR_ERROR_Enabled (0x1UL) /*!< Read: Enabled */ +#define TWIS_INTENCLR_ERROR_Clear (0x1UL) /*!< Disable */ /* Bit 1 : Write '1' to disable interrupt for event STOPPED */ #define TWIS_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ #define TWIS_INTENCLR_STOPPED_Msk (0x1UL << TWIS_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ -#define TWIS_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */ -#define TWIS_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */ -#define TWIS_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */ +#define TWIS_INTENCLR_STOPPED_Disabled (0x0UL) /*!< Read: Disabled */ +#define TWIS_INTENCLR_STOPPED_Enabled (0x1UL) /*!< Read: Enabled */ +#define TWIS_INTENCLR_STOPPED_Clear (0x1UL) /*!< Disable */ /* Register: TWIS_ERRORSRC */ /* Description: Error source */ @@ -9793,25 +9793,25 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 3 : TX buffer over-read detected, and prevented */ #define TWIS_ERRORSRC_OVERREAD_Pos (3UL) /*!< Position of OVERREAD field. */ #define TWIS_ERRORSRC_OVERREAD_Msk (0x1UL << TWIS_ERRORSRC_OVERREAD_Pos) /*!< Bit mask of OVERREAD field. */ -#define TWIS_ERRORSRC_OVERREAD_NotDetected (0UL) /*!< Error did not occur */ -#define TWIS_ERRORSRC_OVERREAD_Detected (1UL) /*!< Error occurred */ +#define TWIS_ERRORSRC_OVERREAD_NotDetected (0x0UL) /*!< Error did not occur */ +#define TWIS_ERRORSRC_OVERREAD_Detected (0x1UL) /*!< Error occurred */ /* Bit 2 : NACK sent after receiving a data byte */ #define TWIS_ERRORSRC_DNACK_Pos (2UL) /*!< Position of DNACK field. */ #define TWIS_ERRORSRC_DNACK_Msk (0x1UL << TWIS_ERRORSRC_DNACK_Pos) /*!< Bit mask of DNACK field. */ -#define TWIS_ERRORSRC_DNACK_NotReceived (0UL) /*!< Error did not occur */ -#define TWIS_ERRORSRC_DNACK_Received (1UL) /*!< Error occurred */ +#define TWIS_ERRORSRC_DNACK_NotReceived (0x0UL) /*!< Error did not occur */ +#define TWIS_ERRORSRC_DNACK_Received (0x1UL) /*!< Error occurred */ /* Bit 0 : RX buffer overflow detected, and prevented */ #define TWIS_ERRORSRC_OVERFLOW_Pos (0UL) /*!< Position of OVERFLOW field. */ #define TWIS_ERRORSRC_OVERFLOW_Msk (0x1UL << TWIS_ERRORSRC_OVERFLOW_Pos) /*!< Bit mask of OVERFLOW field. */ -#define TWIS_ERRORSRC_OVERFLOW_NotDetected (0UL) /*!< Error did not occur */ -#define TWIS_ERRORSRC_OVERFLOW_Detected (1UL) /*!< Error occurred */ +#define TWIS_ERRORSRC_OVERFLOW_NotDetected (0x0UL) /*!< Error did not occur */ +#define TWIS_ERRORSRC_OVERFLOW_Detected (0x1UL) /*!< Error occurred */ /* Register: TWIS_MATCH */ /* Description: Status register indicating which address had a match */ -/* Bit 0 : Indication of which address in {ADDRESS} that matched the incoming address */ +/* Bit 0 : Indication of which address in ADDRESS that matched the incoming address */ #define TWIS_MATCH_MATCH_Pos (0UL) /*!< Position of MATCH field. */ #define TWIS_MATCH_MATCH_Msk (0x1UL << TWIS_MATCH_MATCH_Pos) /*!< Bit mask of MATCH field. */ @@ -9821,8 +9821,8 @@ POSSIBILITY OF SUCH DAMAGE. /* Bits 3..0 : Enable or disable TWIS */ #define TWIS_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ #define TWIS_ENABLE_ENABLE_Msk (0xFUL << TWIS_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ -#define TWIS_ENABLE_ENABLE_Disabled (0UL) /*!< Disable TWIS */ -#define TWIS_ENABLE_ENABLE_Enabled (9UL) /*!< Enable TWIS */ +#define TWIS_ENABLE_ENABLE_Disabled (0x0UL) /*!< Disable TWIS */ +#define TWIS_ENABLE_ENABLE_Enabled (0x9UL) /*!< Enable TWIS */ /* Register: TWIS_PSEL_SCL */ /* Description: Pin select for SCL signal */ @@ -9830,8 +9830,8 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 31 : Connection */ #define TWIS_PSEL_SCL_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ #define TWIS_PSEL_SCL_CONNECT_Msk (0x1UL << TWIS_PSEL_SCL_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ -#define TWIS_PSEL_SCL_CONNECT_Connected (0UL) /*!< Connect */ -#define TWIS_PSEL_SCL_CONNECT_Disconnected (1UL) /*!< Disconnect */ +#define TWIS_PSEL_SCL_CONNECT_Connected (0x0UL) /*!< Connect */ +#define TWIS_PSEL_SCL_CONNECT_Disconnected (0x1UL) /*!< Disconnect */ /* Bits 4..0 : Pin number */ #define TWIS_PSEL_SCL_PIN_Pos (0UL) /*!< Position of PIN field. */ @@ -9843,8 +9843,8 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 31 : Connection */ #define TWIS_PSEL_SDA_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ #define TWIS_PSEL_SDA_CONNECT_Msk (0x1UL << TWIS_PSEL_SDA_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ -#define TWIS_PSEL_SDA_CONNECT_Connected (0UL) /*!< Connect */ -#define TWIS_PSEL_SDA_CONNECT_Disconnected (1UL) /*!< Disconnect */ +#define TWIS_PSEL_SDA_CONNECT_Connected (0x0UL) /*!< Connect */ +#define TWIS_PSEL_SDA_CONNECT_Disconnected (0x1UL) /*!< Disconnect */ /* Bits 4..0 : Pin number */ #define TWIS_PSEL_SDA_PIN_Pos (0UL) /*!< Position of PIN field. */ @@ -9877,8 +9877,8 @@ POSSIBILITY OF SUCH DAMAGE. /* Bits 1..0 : List type */ #define TWIS_RXD_LIST_LIST_Pos (0UL) /*!< Position of LIST field. */ #define TWIS_RXD_LIST_LIST_Msk (0x3UL << TWIS_RXD_LIST_LIST_Pos) /*!< Bit mask of LIST field. */ -#define TWIS_RXD_LIST_LIST_Disabled (0UL) /*!< Disable EasyDMA list */ -#define TWIS_RXD_LIST_LIST_ArrayList (1UL) /*!< Use array list */ +#define TWIS_RXD_LIST_LIST_Disabled (0x0UL) /*!< Disable EasyDMA list */ +#define TWIS_RXD_LIST_LIST_ArrayList (0x1UL) /*!< Use array list */ /* Register: TWIS_TXD_PTR */ /* Description: TXD Data pointer */ @@ -9907,8 +9907,8 @@ POSSIBILITY OF SUCH DAMAGE. /* Bits 1..0 : List type */ #define TWIS_TXD_LIST_LIST_Pos (0UL) /*!< Position of LIST field. */ #define TWIS_TXD_LIST_LIST_Msk (0x3UL << TWIS_TXD_LIST_LIST_Pos) /*!< Bit mask of LIST field. */ -#define TWIS_TXD_LIST_LIST_Disabled (0UL) /*!< Disable EasyDMA list */ -#define TWIS_TXD_LIST_LIST_ArrayList (1UL) /*!< Use array list */ +#define TWIS_TXD_LIST_LIST_Disabled (0x0UL) /*!< Disable EasyDMA list */ +#define TWIS_TXD_LIST_LIST_ArrayList (0x1UL) /*!< Use array list */ /* Register: TWIS_ADDRESS */ /* Description: Description collection: TWI slave address n */ @@ -9923,14 +9923,14 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 1 : Enable or disable address matching on ADDRESS[1] */ #define TWIS_CONFIG_ADDRESS1_Pos (1UL) /*!< Position of ADDRESS1 field. */ #define TWIS_CONFIG_ADDRESS1_Msk (0x1UL << TWIS_CONFIG_ADDRESS1_Pos) /*!< Bit mask of ADDRESS1 field. */ -#define TWIS_CONFIG_ADDRESS1_Disabled (0UL) /*!< Disabled */ -#define TWIS_CONFIG_ADDRESS1_Enabled (1UL) /*!< Enabled */ +#define TWIS_CONFIG_ADDRESS1_Disabled (0x0UL) /*!< Disabled */ +#define TWIS_CONFIG_ADDRESS1_Enabled (0x1UL) /*!< Enabled */ /* Bit 0 : Enable or disable address matching on ADDRESS[0] */ #define TWIS_CONFIG_ADDRESS0_Pos (0UL) /*!< Position of ADDRESS0 field. */ #define TWIS_CONFIG_ADDRESS0_Msk (0x1UL << TWIS_CONFIG_ADDRESS0_Pos) /*!< Bit mask of ADDRESS0 field. */ -#define TWIS_CONFIG_ADDRESS0_Disabled (0UL) /*!< Disabled */ -#define TWIS_CONFIG_ADDRESS0_Enabled (1UL) /*!< Enabled */ +#define TWIS_CONFIG_ADDRESS0_Disabled (0x0UL) /*!< Disabled */ +#define TWIS_CONFIG_ADDRESS0_Enabled (0x1UL) /*!< Enabled */ /* Register: TWIS_ORC */ /* Description: Over-read character. Character sent out in case of an over-read of the transmit buffer. */ @@ -9949,7 +9949,7 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 0 : Start UART receiver */ #define UARTE_TASKS_STARTRX_TASKS_STARTRX_Pos (0UL) /*!< Position of TASKS_STARTRX field. */ #define UARTE_TASKS_STARTRX_TASKS_STARTRX_Msk (0x1UL << UARTE_TASKS_STARTRX_TASKS_STARTRX_Pos) /*!< Bit mask of TASKS_STARTRX field. */ -#define UARTE_TASKS_STARTRX_TASKS_STARTRX_Trigger (1UL) /*!< Trigger task */ +#define UARTE_TASKS_STARTRX_TASKS_STARTRX_Trigger (0x1UL) /*!< Trigger task */ /* Register: UARTE_TASKS_STOPRX */ /* Description: Stop UART receiver */ @@ -9957,7 +9957,7 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 0 : Stop UART receiver */ #define UARTE_TASKS_STOPRX_TASKS_STOPRX_Pos (0UL) /*!< Position of TASKS_STOPRX field. */ #define UARTE_TASKS_STOPRX_TASKS_STOPRX_Msk (0x1UL << UARTE_TASKS_STOPRX_TASKS_STOPRX_Pos) /*!< Bit mask of TASKS_STOPRX field. */ -#define UARTE_TASKS_STOPRX_TASKS_STOPRX_Trigger (1UL) /*!< Trigger task */ +#define UARTE_TASKS_STOPRX_TASKS_STOPRX_Trigger (0x1UL) /*!< Trigger task */ /* Register: UARTE_TASKS_STARTTX */ /* Description: Start UART transmitter */ @@ -9965,7 +9965,7 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 0 : Start UART transmitter */ #define UARTE_TASKS_STARTTX_TASKS_STARTTX_Pos (0UL) /*!< Position of TASKS_STARTTX field. */ #define UARTE_TASKS_STARTTX_TASKS_STARTTX_Msk (0x1UL << UARTE_TASKS_STARTTX_TASKS_STARTTX_Pos) /*!< Bit mask of TASKS_STARTTX field. */ -#define UARTE_TASKS_STARTTX_TASKS_STARTTX_Trigger (1UL) /*!< Trigger task */ +#define UARTE_TASKS_STARTTX_TASKS_STARTTX_Trigger (0x1UL) /*!< Trigger task */ /* Register: UARTE_TASKS_STOPTX */ /* Description: Stop UART transmitter */ @@ -9973,7 +9973,7 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 0 : Stop UART transmitter */ #define UARTE_TASKS_STOPTX_TASKS_STOPTX_Pos (0UL) /*!< Position of TASKS_STOPTX field. */ #define UARTE_TASKS_STOPTX_TASKS_STOPTX_Msk (0x1UL << UARTE_TASKS_STOPTX_TASKS_STOPTX_Pos) /*!< Bit mask of TASKS_STOPTX field. */ -#define UARTE_TASKS_STOPTX_TASKS_STOPTX_Trigger (1UL) /*!< Trigger task */ +#define UARTE_TASKS_STOPTX_TASKS_STOPTX_Trigger (0x1UL) /*!< Trigger task */ /* Register: UARTE_TASKS_FLUSHRX */ /* Description: Flush RX FIFO into RX buffer */ @@ -9981,7 +9981,7 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 0 : Flush RX FIFO into RX buffer */ #define UARTE_TASKS_FLUSHRX_TASKS_FLUSHRX_Pos (0UL) /*!< Position of TASKS_FLUSHRX field. */ #define UARTE_TASKS_FLUSHRX_TASKS_FLUSHRX_Msk (0x1UL << UARTE_TASKS_FLUSHRX_TASKS_FLUSHRX_Pos) /*!< Bit mask of TASKS_FLUSHRX field. */ -#define UARTE_TASKS_FLUSHRX_TASKS_FLUSHRX_Trigger (1UL) /*!< Trigger task */ +#define UARTE_TASKS_FLUSHRX_TASKS_FLUSHRX_Trigger (0x1UL) /*!< Trigger task */ /* Register: UARTE_SUBSCRIBE_STARTRX */ /* Description: Subscribe configuration for task STARTRX */ @@ -9989,8 +9989,8 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 31 : */ #define UARTE_SUBSCRIBE_STARTRX_EN_Pos (31UL) /*!< Position of EN field. */ #define UARTE_SUBSCRIBE_STARTRX_EN_Msk (0x1UL << UARTE_SUBSCRIBE_STARTRX_EN_Pos) /*!< Bit mask of EN field. */ -#define UARTE_SUBSCRIBE_STARTRX_EN_Disabled (0UL) /*!< Disable subscription */ -#define UARTE_SUBSCRIBE_STARTRX_EN_Enabled (1UL) /*!< Enable subscription */ +#define UARTE_SUBSCRIBE_STARTRX_EN_Disabled (0x0UL) /*!< Disable subscription */ +#define UARTE_SUBSCRIBE_STARTRX_EN_Enabled (0x1UL) /*!< Enable subscription */ /* Bits 7..0 : DPPI channel that task STARTRX will subscribe to */ #define UARTE_SUBSCRIBE_STARTRX_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ @@ -10002,8 +10002,8 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 31 : */ #define UARTE_SUBSCRIBE_STOPRX_EN_Pos (31UL) /*!< Position of EN field. */ #define UARTE_SUBSCRIBE_STOPRX_EN_Msk (0x1UL << UARTE_SUBSCRIBE_STOPRX_EN_Pos) /*!< Bit mask of EN field. */ -#define UARTE_SUBSCRIBE_STOPRX_EN_Disabled (0UL) /*!< Disable subscription */ -#define UARTE_SUBSCRIBE_STOPRX_EN_Enabled (1UL) /*!< Enable subscription */ +#define UARTE_SUBSCRIBE_STOPRX_EN_Disabled (0x0UL) /*!< Disable subscription */ +#define UARTE_SUBSCRIBE_STOPRX_EN_Enabled (0x1UL) /*!< Enable subscription */ /* Bits 7..0 : DPPI channel that task STOPRX will subscribe to */ #define UARTE_SUBSCRIBE_STOPRX_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ @@ -10015,8 +10015,8 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 31 : */ #define UARTE_SUBSCRIBE_STARTTX_EN_Pos (31UL) /*!< Position of EN field. */ #define UARTE_SUBSCRIBE_STARTTX_EN_Msk (0x1UL << UARTE_SUBSCRIBE_STARTTX_EN_Pos) /*!< Bit mask of EN field. */ -#define UARTE_SUBSCRIBE_STARTTX_EN_Disabled (0UL) /*!< Disable subscription */ -#define UARTE_SUBSCRIBE_STARTTX_EN_Enabled (1UL) /*!< Enable subscription */ +#define UARTE_SUBSCRIBE_STARTTX_EN_Disabled (0x0UL) /*!< Disable subscription */ +#define UARTE_SUBSCRIBE_STARTTX_EN_Enabled (0x1UL) /*!< Enable subscription */ /* Bits 7..0 : DPPI channel that task STARTTX will subscribe to */ #define UARTE_SUBSCRIBE_STARTTX_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ @@ -10028,8 +10028,8 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 31 : */ #define UARTE_SUBSCRIBE_STOPTX_EN_Pos (31UL) /*!< Position of EN field. */ #define UARTE_SUBSCRIBE_STOPTX_EN_Msk (0x1UL << UARTE_SUBSCRIBE_STOPTX_EN_Pos) /*!< Bit mask of EN field. */ -#define UARTE_SUBSCRIBE_STOPTX_EN_Disabled (0UL) /*!< Disable subscription */ -#define UARTE_SUBSCRIBE_STOPTX_EN_Enabled (1UL) /*!< Enable subscription */ +#define UARTE_SUBSCRIBE_STOPTX_EN_Disabled (0x0UL) /*!< Disable subscription */ +#define UARTE_SUBSCRIBE_STOPTX_EN_Enabled (0x1UL) /*!< Enable subscription */ /* Bits 7..0 : DPPI channel that task STOPTX will subscribe to */ #define UARTE_SUBSCRIBE_STOPTX_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ @@ -10041,8 +10041,8 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 31 : */ #define UARTE_SUBSCRIBE_FLUSHRX_EN_Pos (31UL) /*!< Position of EN field. */ #define UARTE_SUBSCRIBE_FLUSHRX_EN_Msk (0x1UL << UARTE_SUBSCRIBE_FLUSHRX_EN_Pos) /*!< Bit mask of EN field. */ -#define UARTE_SUBSCRIBE_FLUSHRX_EN_Disabled (0UL) /*!< Disable subscription */ -#define UARTE_SUBSCRIBE_FLUSHRX_EN_Enabled (1UL) /*!< Enable subscription */ +#define UARTE_SUBSCRIBE_FLUSHRX_EN_Disabled (0x0UL) /*!< Disable subscription */ +#define UARTE_SUBSCRIBE_FLUSHRX_EN_Enabled (0x1UL) /*!< Enable subscription */ /* Bits 7..0 : DPPI channel that task FLUSHRX will subscribe to */ #define UARTE_SUBSCRIBE_FLUSHRX_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ @@ -10054,8 +10054,8 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 0 : CTS is activated (set low). Clear To Send. */ #define UARTE_EVENTS_CTS_EVENTS_CTS_Pos (0UL) /*!< Position of EVENTS_CTS field. */ #define UARTE_EVENTS_CTS_EVENTS_CTS_Msk (0x1UL << UARTE_EVENTS_CTS_EVENTS_CTS_Pos) /*!< Bit mask of EVENTS_CTS field. */ -#define UARTE_EVENTS_CTS_EVENTS_CTS_NotGenerated (0UL) /*!< Event not generated */ -#define UARTE_EVENTS_CTS_EVENTS_CTS_Generated (1UL) /*!< Event generated */ +#define UARTE_EVENTS_CTS_EVENTS_CTS_NotGenerated (0x0UL) /*!< Event not generated */ +#define UARTE_EVENTS_CTS_EVENTS_CTS_Generated (0x1UL) /*!< Event generated */ /* Register: UARTE_EVENTS_NCTS */ /* Description: CTS is deactivated (set high). Not Clear To Send. */ @@ -10063,8 +10063,8 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 0 : CTS is deactivated (set high). Not Clear To Send. */ #define UARTE_EVENTS_NCTS_EVENTS_NCTS_Pos (0UL) /*!< Position of EVENTS_NCTS field. */ #define UARTE_EVENTS_NCTS_EVENTS_NCTS_Msk (0x1UL << UARTE_EVENTS_NCTS_EVENTS_NCTS_Pos) /*!< Bit mask of EVENTS_NCTS field. */ -#define UARTE_EVENTS_NCTS_EVENTS_NCTS_NotGenerated (0UL) /*!< Event not generated */ -#define UARTE_EVENTS_NCTS_EVENTS_NCTS_Generated (1UL) /*!< Event generated */ +#define UARTE_EVENTS_NCTS_EVENTS_NCTS_NotGenerated (0x0UL) /*!< Event not generated */ +#define UARTE_EVENTS_NCTS_EVENTS_NCTS_Generated (0x1UL) /*!< Event generated */ /* Register: UARTE_EVENTS_RXDRDY */ /* Description: Data received in RXD (but potentially not yet transferred to Data RAM) */ @@ -10072,8 +10072,8 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 0 : Data received in RXD (but potentially not yet transferred to Data RAM) */ #define UARTE_EVENTS_RXDRDY_EVENTS_RXDRDY_Pos (0UL) /*!< Position of EVENTS_RXDRDY field. */ #define UARTE_EVENTS_RXDRDY_EVENTS_RXDRDY_Msk (0x1UL << UARTE_EVENTS_RXDRDY_EVENTS_RXDRDY_Pos) /*!< Bit mask of EVENTS_RXDRDY field. */ -#define UARTE_EVENTS_RXDRDY_EVENTS_RXDRDY_NotGenerated (0UL) /*!< Event not generated */ -#define UARTE_EVENTS_RXDRDY_EVENTS_RXDRDY_Generated (1UL) /*!< Event generated */ +#define UARTE_EVENTS_RXDRDY_EVENTS_RXDRDY_NotGenerated (0x0UL) /*!< Event not generated */ +#define UARTE_EVENTS_RXDRDY_EVENTS_RXDRDY_Generated (0x1UL) /*!< Event generated */ /* Register: UARTE_EVENTS_ENDRX */ /* Description: Receive buffer is filled up */ @@ -10081,8 +10081,8 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 0 : Receive buffer is filled up */ #define UARTE_EVENTS_ENDRX_EVENTS_ENDRX_Pos (0UL) /*!< Position of EVENTS_ENDRX field. */ #define UARTE_EVENTS_ENDRX_EVENTS_ENDRX_Msk (0x1UL << UARTE_EVENTS_ENDRX_EVENTS_ENDRX_Pos) /*!< Bit mask of EVENTS_ENDRX field. */ -#define UARTE_EVENTS_ENDRX_EVENTS_ENDRX_NotGenerated (0UL) /*!< Event not generated */ -#define UARTE_EVENTS_ENDRX_EVENTS_ENDRX_Generated (1UL) /*!< Event generated */ +#define UARTE_EVENTS_ENDRX_EVENTS_ENDRX_NotGenerated (0x0UL) /*!< Event not generated */ +#define UARTE_EVENTS_ENDRX_EVENTS_ENDRX_Generated (0x1UL) /*!< Event generated */ /* Register: UARTE_EVENTS_TXDRDY */ /* Description: Data sent from TXD */ @@ -10090,8 +10090,8 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 0 : Data sent from TXD */ #define UARTE_EVENTS_TXDRDY_EVENTS_TXDRDY_Pos (0UL) /*!< Position of EVENTS_TXDRDY field. */ #define UARTE_EVENTS_TXDRDY_EVENTS_TXDRDY_Msk (0x1UL << UARTE_EVENTS_TXDRDY_EVENTS_TXDRDY_Pos) /*!< Bit mask of EVENTS_TXDRDY field. */ -#define UARTE_EVENTS_TXDRDY_EVENTS_TXDRDY_NotGenerated (0UL) /*!< Event not generated */ -#define UARTE_EVENTS_TXDRDY_EVENTS_TXDRDY_Generated (1UL) /*!< Event generated */ +#define UARTE_EVENTS_TXDRDY_EVENTS_TXDRDY_NotGenerated (0x0UL) /*!< Event not generated */ +#define UARTE_EVENTS_TXDRDY_EVENTS_TXDRDY_Generated (0x1UL) /*!< Event generated */ /* Register: UARTE_EVENTS_ENDTX */ /* Description: Last TX byte transmitted */ @@ -10099,8 +10099,8 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 0 : Last TX byte transmitted */ #define UARTE_EVENTS_ENDTX_EVENTS_ENDTX_Pos (0UL) /*!< Position of EVENTS_ENDTX field. */ #define UARTE_EVENTS_ENDTX_EVENTS_ENDTX_Msk (0x1UL << UARTE_EVENTS_ENDTX_EVENTS_ENDTX_Pos) /*!< Bit mask of EVENTS_ENDTX field. */ -#define UARTE_EVENTS_ENDTX_EVENTS_ENDTX_NotGenerated (0UL) /*!< Event not generated */ -#define UARTE_EVENTS_ENDTX_EVENTS_ENDTX_Generated (1UL) /*!< Event generated */ +#define UARTE_EVENTS_ENDTX_EVENTS_ENDTX_NotGenerated (0x0UL) /*!< Event not generated */ +#define UARTE_EVENTS_ENDTX_EVENTS_ENDTX_Generated (0x1UL) /*!< Event generated */ /* Register: UARTE_EVENTS_ERROR */ /* Description: Error detected */ @@ -10108,8 +10108,8 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 0 : Error detected */ #define UARTE_EVENTS_ERROR_EVENTS_ERROR_Pos (0UL) /*!< Position of EVENTS_ERROR field. */ #define UARTE_EVENTS_ERROR_EVENTS_ERROR_Msk (0x1UL << UARTE_EVENTS_ERROR_EVENTS_ERROR_Pos) /*!< Bit mask of EVENTS_ERROR field. */ -#define UARTE_EVENTS_ERROR_EVENTS_ERROR_NotGenerated (0UL) /*!< Event not generated */ -#define UARTE_EVENTS_ERROR_EVENTS_ERROR_Generated (1UL) /*!< Event generated */ +#define UARTE_EVENTS_ERROR_EVENTS_ERROR_NotGenerated (0x0UL) /*!< Event not generated */ +#define UARTE_EVENTS_ERROR_EVENTS_ERROR_Generated (0x1UL) /*!< Event generated */ /* Register: UARTE_EVENTS_RXTO */ /* Description: Receiver timeout */ @@ -10117,8 +10117,8 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 0 : Receiver timeout */ #define UARTE_EVENTS_RXTO_EVENTS_RXTO_Pos (0UL) /*!< Position of EVENTS_RXTO field. */ #define UARTE_EVENTS_RXTO_EVENTS_RXTO_Msk (0x1UL << UARTE_EVENTS_RXTO_EVENTS_RXTO_Pos) /*!< Bit mask of EVENTS_RXTO field. */ -#define UARTE_EVENTS_RXTO_EVENTS_RXTO_NotGenerated (0UL) /*!< Event not generated */ -#define UARTE_EVENTS_RXTO_EVENTS_RXTO_Generated (1UL) /*!< Event generated */ +#define UARTE_EVENTS_RXTO_EVENTS_RXTO_NotGenerated (0x0UL) /*!< Event not generated */ +#define UARTE_EVENTS_RXTO_EVENTS_RXTO_Generated (0x1UL) /*!< Event generated */ /* Register: UARTE_EVENTS_RXSTARTED */ /* Description: UART receiver has started */ @@ -10126,8 +10126,8 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 0 : UART receiver has started */ #define UARTE_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Pos (0UL) /*!< Position of EVENTS_RXSTARTED field. */ #define UARTE_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Msk (0x1UL << UARTE_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Pos) /*!< Bit mask of EVENTS_RXSTARTED field. */ -#define UARTE_EVENTS_RXSTARTED_EVENTS_RXSTARTED_NotGenerated (0UL) /*!< Event not generated */ -#define UARTE_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Generated (1UL) /*!< Event generated */ +#define UARTE_EVENTS_RXSTARTED_EVENTS_RXSTARTED_NotGenerated (0x0UL) /*!< Event not generated */ +#define UARTE_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Generated (0x1UL) /*!< Event generated */ /* Register: UARTE_EVENTS_TXSTARTED */ /* Description: UART transmitter has started */ @@ -10135,8 +10135,8 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 0 : UART transmitter has started */ #define UARTE_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Pos (0UL) /*!< Position of EVENTS_TXSTARTED field. */ #define UARTE_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Msk (0x1UL << UARTE_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Pos) /*!< Bit mask of EVENTS_TXSTARTED field. */ -#define UARTE_EVENTS_TXSTARTED_EVENTS_TXSTARTED_NotGenerated (0UL) /*!< Event not generated */ -#define UARTE_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Generated (1UL) /*!< Event generated */ +#define UARTE_EVENTS_TXSTARTED_EVENTS_TXSTARTED_NotGenerated (0x0UL) /*!< Event not generated */ +#define UARTE_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Generated (0x1UL) /*!< Event generated */ /* Register: UARTE_EVENTS_TXSTOPPED */ /* Description: Transmitter stopped */ @@ -10144,8 +10144,8 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 0 : Transmitter stopped */ #define UARTE_EVENTS_TXSTOPPED_EVENTS_TXSTOPPED_Pos (0UL) /*!< Position of EVENTS_TXSTOPPED field. */ #define UARTE_EVENTS_TXSTOPPED_EVENTS_TXSTOPPED_Msk (0x1UL << UARTE_EVENTS_TXSTOPPED_EVENTS_TXSTOPPED_Pos) /*!< Bit mask of EVENTS_TXSTOPPED field. */ -#define UARTE_EVENTS_TXSTOPPED_EVENTS_TXSTOPPED_NotGenerated (0UL) /*!< Event not generated */ -#define UARTE_EVENTS_TXSTOPPED_EVENTS_TXSTOPPED_Generated (1UL) /*!< Event generated */ +#define UARTE_EVENTS_TXSTOPPED_EVENTS_TXSTOPPED_NotGenerated (0x0UL) /*!< Event not generated */ +#define UARTE_EVENTS_TXSTOPPED_EVENTS_TXSTOPPED_Generated (0x1UL) /*!< Event generated */ /* Register: UARTE_PUBLISH_CTS */ /* Description: Publish configuration for event CTS */ @@ -10153,8 +10153,8 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 31 : */ #define UARTE_PUBLISH_CTS_EN_Pos (31UL) /*!< Position of EN field. */ #define UARTE_PUBLISH_CTS_EN_Msk (0x1UL << UARTE_PUBLISH_CTS_EN_Pos) /*!< Bit mask of EN field. */ -#define UARTE_PUBLISH_CTS_EN_Disabled (0UL) /*!< Disable publishing */ -#define UARTE_PUBLISH_CTS_EN_Enabled (1UL) /*!< Enable publishing */ +#define UARTE_PUBLISH_CTS_EN_Disabled (0x0UL) /*!< Disable publishing */ +#define UARTE_PUBLISH_CTS_EN_Enabled (0x1UL) /*!< Enable publishing */ /* Bits 7..0 : DPPI channel that event CTS will publish to */ #define UARTE_PUBLISH_CTS_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ @@ -10166,8 +10166,8 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 31 : */ #define UARTE_PUBLISH_NCTS_EN_Pos (31UL) /*!< Position of EN field. */ #define UARTE_PUBLISH_NCTS_EN_Msk (0x1UL << UARTE_PUBLISH_NCTS_EN_Pos) /*!< Bit mask of EN field. */ -#define UARTE_PUBLISH_NCTS_EN_Disabled (0UL) /*!< Disable publishing */ -#define UARTE_PUBLISH_NCTS_EN_Enabled (1UL) /*!< Enable publishing */ +#define UARTE_PUBLISH_NCTS_EN_Disabled (0x0UL) /*!< Disable publishing */ +#define UARTE_PUBLISH_NCTS_EN_Enabled (0x1UL) /*!< Enable publishing */ /* Bits 7..0 : DPPI channel that event NCTS will publish to */ #define UARTE_PUBLISH_NCTS_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ @@ -10179,8 +10179,8 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 31 : */ #define UARTE_PUBLISH_RXDRDY_EN_Pos (31UL) /*!< Position of EN field. */ #define UARTE_PUBLISH_RXDRDY_EN_Msk (0x1UL << UARTE_PUBLISH_RXDRDY_EN_Pos) /*!< Bit mask of EN field. */ -#define UARTE_PUBLISH_RXDRDY_EN_Disabled (0UL) /*!< Disable publishing */ -#define UARTE_PUBLISH_RXDRDY_EN_Enabled (1UL) /*!< Enable publishing */ +#define UARTE_PUBLISH_RXDRDY_EN_Disabled (0x0UL) /*!< Disable publishing */ +#define UARTE_PUBLISH_RXDRDY_EN_Enabled (0x1UL) /*!< Enable publishing */ /* Bits 7..0 : DPPI channel that event RXDRDY will publish to */ #define UARTE_PUBLISH_RXDRDY_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ @@ -10192,8 +10192,8 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 31 : */ #define UARTE_PUBLISH_ENDRX_EN_Pos (31UL) /*!< Position of EN field. */ #define UARTE_PUBLISH_ENDRX_EN_Msk (0x1UL << UARTE_PUBLISH_ENDRX_EN_Pos) /*!< Bit mask of EN field. */ -#define UARTE_PUBLISH_ENDRX_EN_Disabled (0UL) /*!< Disable publishing */ -#define UARTE_PUBLISH_ENDRX_EN_Enabled (1UL) /*!< Enable publishing */ +#define UARTE_PUBLISH_ENDRX_EN_Disabled (0x0UL) /*!< Disable publishing */ +#define UARTE_PUBLISH_ENDRX_EN_Enabled (0x1UL) /*!< Enable publishing */ /* Bits 7..0 : DPPI channel that event ENDRX will publish to */ #define UARTE_PUBLISH_ENDRX_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ @@ -10205,8 +10205,8 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 31 : */ #define UARTE_PUBLISH_TXDRDY_EN_Pos (31UL) /*!< Position of EN field. */ #define UARTE_PUBLISH_TXDRDY_EN_Msk (0x1UL << UARTE_PUBLISH_TXDRDY_EN_Pos) /*!< Bit mask of EN field. */ -#define UARTE_PUBLISH_TXDRDY_EN_Disabled (0UL) /*!< Disable publishing */ -#define UARTE_PUBLISH_TXDRDY_EN_Enabled (1UL) /*!< Enable publishing */ +#define UARTE_PUBLISH_TXDRDY_EN_Disabled (0x0UL) /*!< Disable publishing */ +#define UARTE_PUBLISH_TXDRDY_EN_Enabled (0x1UL) /*!< Enable publishing */ /* Bits 7..0 : DPPI channel that event TXDRDY will publish to */ #define UARTE_PUBLISH_TXDRDY_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ @@ -10218,8 +10218,8 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 31 : */ #define UARTE_PUBLISH_ENDTX_EN_Pos (31UL) /*!< Position of EN field. */ #define UARTE_PUBLISH_ENDTX_EN_Msk (0x1UL << UARTE_PUBLISH_ENDTX_EN_Pos) /*!< Bit mask of EN field. */ -#define UARTE_PUBLISH_ENDTX_EN_Disabled (0UL) /*!< Disable publishing */ -#define UARTE_PUBLISH_ENDTX_EN_Enabled (1UL) /*!< Enable publishing */ +#define UARTE_PUBLISH_ENDTX_EN_Disabled (0x0UL) /*!< Disable publishing */ +#define UARTE_PUBLISH_ENDTX_EN_Enabled (0x1UL) /*!< Enable publishing */ /* Bits 7..0 : DPPI channel that event ENDTX will publish to */ #define UARTE_PUBLISH_ENDTX_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ @@ -10231,8 +10231,8 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 31 : */ #define UARTE_PUBLISH_ERROR_EN_Pos (31UL) /*!< Position of EN field. */ #define UARTE_PUBLISH_ERROR_EN_Msk (0x1UL << UARTE_PUBLISH_ERROR_EN_Pos) /*!< Bit mask of EN field. */ -#define UARTE_PUBLISH_ERROR_EN_Disabled (0UL) /*!< Disable publishing */ -#define UARTE_PUBLISH_ERROR_EN_Enabled (1UL) /*!< Enable publishing */ +#define UARTE_PUBLISH_ERROR_EN_Disabled (0x0UL) /*!< Disable publishing */ +#define UARTE_PUBLISH_ERROR_EN_Enabled (0x1UL) /*!< Enable publishing */ /* Bits 7..0 : DPPI channel that event ERROR will publish to */ #define UARTE_PUBLISH_ERROR_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ @@ -10244,8 +10244,8 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 31 : */ #define UARTE_PUBLISH_RXTO_EN_Pos (31UL) /*!< Position of EN field. */ #define UARTE_PUBLISH_RXTO_EN_Msk (0x1UL << UARTE_PUBLISH_RXTO_EN_Pos) /*!< Bit mask of EN field. */ -#define UARTE_PUBLISH_RXTO_EN_Disabled (0UL) /*!< Disable publishing */ -#define UARTE_PUBLISH_RXTO_EN_Enabled (1UL) /*!< Enable publishing */ +#define UARTE_PUBLISH_RXTO_EN_Disabled (0x0UL) /*!< Disable publishing */ +#define UARTE_PUBLISH_RXTO_EN_Enabled (0x1UL) /*!< Enable publishing */ /* Bits 7..0 : DPPI channel that event RXTO will publish to */ #define UARTE_PUBLISH_RXTO_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ @@ -10257,8 +10257,8 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 31 : */ #define UARTE_PUBLISH_RXSTARTED_EN_Pos (31UL) /*!< Position of EN field. */ #define UARTE_PUBLISH_RXSTARTED_EN_Msk (0x1UL << UARTE_PUBLISH_RXSTARTED_EN_Pos) /*!< Bit mask of EN field. */ -#define UARTE_PUBLISH_RXSTARTED_EN_Disabled (0UL) /*!< Disable publishing */ -#define UARTE_PUBLISH_RXSTARTED_EN_Enabled (1UL) /*!< Enable publishing */ +#define UARTE_PUBLISH_RXSTARTED_EN_Disabled (0x0UL) /*!< Disable publishing */ +#define UARTE_PUBLISH_RXSTARTED_EN_Enabled (0x1UL) /*!< Enable publishing */ /* Bits 7..0 : DPPI channel that event RXSTARTED will publish to */ #define UARTE_PUBLISH_RXSTARTED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ @@ -10270,8 +10270,8 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 31 : */ #define UARTE_PUBLISH_TXSTARTED_EN_Pos (31UL) /*!< Position of EN field. */ #define UARTE_PUBLISH_TXSTARTED_EN_Msk (0x1UL << UARTE_PUBLISH_TXSTARTED_EN_Pos) /*!< Bit mask of EN field. */ -#define UARTE_PUBLISH_TXSTARTED_EN_Disabled (0UL) /*!< Disable publishing */ -#define UARTE_PUBLISH_TXSTARTED_EN_Enabled (1UL) /*!< Enable publishing */ +#define UARTE_PUBLISH_TXSTARTED_EN_Disabled (0x0UL) /*!< Disable publishing */ +#define UARTE_PUBLISH_TXSTARTED_EN_Enabled (0x1UL) /*!< Enable publishing */ /* Bits 7..0 : DPPI channel that event TXSTARTED will publish to */ #define UARTE_PUBLISH_TXSTARTED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ @@ -10283,8 +10283,8 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 31 : */ #define UARTE_PUBLISH_TXSTOPPED_EN_Pos (31UL) /*!< Position of EN field. */ #define UARTE_PUBLISH_TXSTOPPED_EN_Msk (0x1UL << UARTE_PUBLISH_TXSTOPPED_EN_Pos) /*!< Bit mask of EN field. */ -#define UARTE_PUBLISH_TXSTOPPED_EN_Disabled (0UL) /*!< Disable publishing */ -#define UARTE_PUBLISH_TXSTOPPED_EN_Enabled (1UL) /*!< Enable publishing */ +#define UARTE_PUBLISH_TXSTOPPED_EN_Disabled (0x0UL) /*!< Disable publishing */ +#define UARTE_PUBLISH_TXSTOPPED_EN_Enabled (0x1UL) /*!< Enable publishing */ /* Bits 7..0 : DPPI channel that event TXSTOPPED will publish to */ #define UARTE_PUBLISH_TXSTOPPED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ @@ -10296,14 +10296,14 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 6 : Shortcut between event ENDRX and task STOPRX */ #define UARTE_SHORTS_ENDRX_STOPRX_Pos (6UL) /*!< Position of ENDRX_STOPRX field. */ #define UARTE_SHORTS_ENDRX_STOPRX_Msk (0x1UL << UARTE_SHORTS_ENDRX_STOPRX_Pos) /*!< Bit mask of ENDRX_STOPRX field. */ -#define UARTE_SHORTS_ENDRX_STOPRX_Disabled (0UL) /*!< Disable shortcut */ -#define UARTE_SHORTS_ENDRX_STOPRX_Enabled (1UL) /*!< Enable shortcut */ +#define UARTE_SHORTS_ENDRX_STOPRX_Disabled (0x0UL) /*!< Disable shortcut */ +#define UARTE_SHORTS_ENDRX_STOPRX_Enabled (0x1UL) /*!< Enable shortcut */ /* Bit 5 : Shortcut between event ENDRX and task STARTRX */ #define UARTE_SHORTS_ENDRX_STARTRX_Pos (5UL) /*!< Position of ENDRX_STARTRX field. */ #define UARTE_SHORTS_ENDRX_STARTRX_Msk (0x1UL << UARTE_SHORTS_ENDRX_STARTRX_Pos) /*!< Bit mask of ENDRX_STARTRX field. */ -#define UARTE_SHORTS_ENDRX_STARTRX_Disabled (0UL) /*!< Disable shortcut */ -#define UARTE_SHORTS_ENDRX_STARTRX_Enabled (1UL) /*!< Enable shortcut */ +#define UARTE_SHORTS_ENDRX_STARTRX_Disabled (0x0UL) /*!< Disable shortcut */ +#define UARTE_SHORTS_ENDRX_STARTRX_Enabled (0x1UL) /*!< Enable shortcut */ /* Register: UARTE_INTEN */ /* Description: Enable or disable interrupt */ @@ -10311,68 +10311,68 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 22 : Enable or disable interrupt for event TXSTOPPED */ #define UARTE_INTEN_TXSTOPPED_Pos (22UL) /*!< Position of TXSTOPPED field. */ #define UARTE_INTEN_TXSTOPPED_Msk (0x1UL << UARTE_INTEN_TXSTOPPED_Pos) /*!< Bit mask of TXSTOPPED field. */ -#define UARTE_INTEN_TXSTOPPED_Disabled (0UL) /*!< Disable */ -#define UARTE_INTEN_TXSTOPPED_Enabled (1UL) /*!< Enable */ +#define UARTE_INTEN_TXSTOPPED_Disabled (0x0UL) /*!< Disable */ +#define UARTE_INTEN_TXSTOPPED_Enabled (0x1UL) /*!< Enable */ /* Bit 20 : Enable or disable interrupt for event TXSTARTED */ #define UARTE_INTEN_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */ #define UARTE_INTEN_TXSTARTED_Msk (0x1UL << UARTE_INTEN_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */ -#define UARTE_INTEN_TXSTARTED_Disabled (0UL) /*!< Disable */ -#define UARTE_INTEN_TXSTARTED_Enabled (1UL) /*!< Enable */ +#define UARTE_INTEN_TXSTARTED_Disabled (0x0UL) /*!< Disable */ +#define UARTE_INTEN_TXSTARTED_Enabled (0x1UL) /*!< Enable */ /* Bit 19 : Enable or disable interrupt for event RXSTARTED */ #define UARTE_INTEN_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */ #define UARTE_INTEN_RXSTARTED_Msk (0x1UL << UARTE_INTEN_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */ -#define UARTE_INTEN_RXSTARTED_Disabled (0UL) /*!< Disable */ -#define UARTE_INTEN_RXSTARTED_Enabled (1UL) /*!< Enable */ +#define UARTE_INTEN_RXSTARTED_Disabled (0x0UL) /*!< Disable */ +#define UARTE_INTEN_RXSTARTED_Enabled (0x1UL) /*!< Enable */ /* Bit 17 : Enable or disable interrupt for event RXTO */ #define UARTE_INTEN_RXTO_Pos (17UL) /*!< Position of RXTO field. */ #define UARTE_INTEN_RXTO_Msk (0x1UL << UARTE_INTEN_RXTO_Pos) /*!< Bit mask of RXTO field. */ -#define UARTE_INTEN_RXTO_Disabled (0UL) /*!< Disable */ -#define UARTE_INTEN_RXTO_Enabled (1UL) /*!< Enable */ +#define UARTE_INTEN_RXTO_Disabled (0x0UL) /*!< Disable */ +#define UARTE_INTEN_RXTO_Enabled (0x1UL) /*!< Enable */ /* Bit 9 : Enable or disable interrupt for event ERROR */ #define UARTE_INTEN_ERROR_Pos (9UL) /*!< Position of ERROR field. */ #define UARTE_INTEN_ERROR_Msk (0x1UL << UARTE_INTEN_ERROR_Pos) /*!< Bit mask of ERROR field. */ -#define UARTE_INTEN_ERROR_Disabled (0UL) /*!< Disable */ -#define UARTE_INTEN_ERROR_Enabled (1UL) /*!< Enable */ +#define UARTE_INTEN_ERROR_Disabled (0x0UL) /*!< Disable */ +#define UARTE_INTEN_ERROR_Enabled (0x1UL) /*!< Enable */ /* Bit 8 : Enable or disable interrupt for event ENDTX */ #define UARTE_INTEN_ENDTX_Pos (8UL) /*!< Position of ENDTX field. */ #define UARTE_INTEN_ENDTX_Msk (0x1UL << UARTE_INTEN_ENDTX_Pos) /*!< Bit mask of ENDTX field. */ -#define UARTE_INTEN_ENDTX_Disabled (0UL) /*!< Disable */ -#define UARTE_INTEN_ENDTX_Enabled (1UL) /*!< Enable */ +#define UARTE_INTEN_ENDTX_Disabled (0x0UL) /*!< Disable */ +#define UARTE_INTEN_ENDTX_Enabled (0x1UL) /*!< Enable */ /* Bit 7 : Enable or disable interrupt for event TXDRDY */ #define UARTE_INTEN_TXDRDY_Pos (7UL) /*!< Position of TXDRDY field. */ #define UARTE_INTEN_TXDRDY_Msk (0x1UL << UARTE_INTEN_TXDRDY_Pos) /*!< Bit mask of TXDRDY field. */ -#define UARTE_INTEN_TXDRDY_Disabled (0UL) /*!< Disable */ -#define UARTE_INTEN_TXDRDY_Enabled (1UL) /*!< Enable */ +#define UARTE_INTEN_TXDRDY_Disabled (0x0UL) /*!< Disable */ +#define UARTE_INTEN_TXDRDY_Enabled (0x1UL) /*!< Enable */ /* Bit 4 : Enable or disable interrupt for event ENDRX */ #define UARTE_INTEN_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */ #define UARTE_INTEN_ENDRX_Msk (0x1UL << UARTE_INTEN_ENDRX_Pos) /*!< Bit mask of ENDRX field. */ -#define UARTE_INTEN_ENDRX_Disabled (0UL) /*!< Disable */ -#define UARTE_INTEN_ENDRX_Enabled (1UL) /*!< Enable */ +#define UARTE_INTEN_ENDRX_Disabled (0x0UL) /*!< Disable */ +#define UARTE_INTEN_ENDRX_Enabled (0x1UL) /*!< Enable */ /* Bit 2 : Enable or disable interrupt for event RXDRDY */ #define UARTE_INTEN_RXDRDY_Pos (2UL) /*!< Position of RXDRDY field. */ #define UARTE_INTEN_RXDRDY_Msk (0x1UL << UARTE_INTEN_RXDRDY_Pos) /*!< Bit mask of RXDRDY field. */ -#define UARTE_INTEN_RXDRDY_Disabled (0UL) /*!< Disable */ -#define UARTE_INTEN_RXDRDY_Enabled (1UL) /*!< Enable */ +#define UARTE_INTEN_RXDRDY_Disabled (0x0UL) /*!< Disable */ +#define UARTE_INTEN_RXDRDY_Enabled (0x1UL) /*!< Enable */ /* Bit 1 : Enable or disable interrupt for event NCTS */ #define UARTE_INTEN_NCTS_Pos (1UL) /*!< Position of NCTS field. */ #define UARTE_INTEN_NCTS_Msk (0x1UL << UARTE_INTEN_NCTS_Pos) /*!< Bit mask of NCTS field. */ -#define UARTE_INTEN_NCTS_Disabled (0UL) /*!< Disable */ -#define UARTE_INTEN_NCTS_Enabled (1UL) /*!< Enable */ +#define UARTE_INTEN_NCTS_Disabled (0x0UL) /*!< Disable */ +#define UARTE_INTEN_NCTS_Enabled (0x1UL) /*!< Enable */ /* Bit 0 : Enable or disable interrupt for event CTS */ #define UARTE_INTEN_CTS_Pos (0UL) /*!< Position of CTS field. */ #define UARTE_INTEN_CTS_Msk (0x1UL << UARTE_INTEN_CTS_Pos) /*!< Bit mask of CTS field. */ -#define UARTE_INTEN_CTS_Disabled (0UL) /*!< Disable */ -#define UARTE_INTEN_CTS_Enabled (1UL) /*!< Enable */ +#define UARTE_INTEN_CTS_Disabled (0x0UL) /*!< Disable */ +#define UARTE_INTEN_CTS_Enabled (0x1UL) /*!< Enable */ /* Register: UARTE_INTENSET */ /* Description: Enable interrupt */ @@ -10380,79 +10380,79 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 22 : Write '1' to enable interrupt for event TXSTOPPED */ #define UARTE_INTENSET_TXSTOPPED_Pos (22UL) /*!< Position of TXSTOPPED field. */ #define UARTE_INTENSET_TXSTOPPED_Msk (0x1UL << UARTE_INTENSET_TXSTOPPED_Pos) /*!< Bit mask of TXSTOPPED field. */ -#define UARTE_INTENSET_TXSTOPPED_Disabled (0UL) /*!< Read: Disabled */ -#define UARTE_INTENSET_TXSTOPPED_Enabled (1UL) /*!< Read: Enabled */ -#define UARTE_INTENSET_TXSTOPPED_Set (1UL) /*!< Enable */ +#define UARTE_INTENSET_TXSTOPPED_Disabled (0x0UL) /*!< Read: Disabled */ +#define UARTE_INTENSET_TXSTOPPED_Enabled (0x1UL) /*!< Read: Enabled */ +#define UARTE_INTENSET_TXSTOPPED_Set (0x1UL) /*!< Enable */ /* Bit 20 : Write '1' to enable interrupt for event TXSTARTED */ #define UARTE_INTENSET_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */ #define UARTE_INTENSET_TXSTARTED_Msk (0x1UL << UARTE_INTENSET_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */ -#define UARTE_INTENSET_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */ -#define UARTE_INTENSET_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */ -#define UARTE_INTENSET_TXSTARTED_Set (1UL) /*!< Enable */ +#define UARTE_INTENSET_TXSTARTED_Disabled (0x0UL) /*!< Read: Disabled */ +#define UARTE_INTENSET_TXSTARTED_Enabled (0x1UL) /*!< Read: Enabled */ +#define UARTE_INTENSET_TXSTARTED_Set (0x1UL) /*!< Enable */ /* Bit 19 : Write '1' to enable interrupt for event RXSTARTED */ #define UARTE_INTENSET_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */ #define UARTE_INTENSET_RXSTARTED_Msk (0x1UL << UARTE_INTENSET_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */ -#define UARTE_INTENSET_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */ -#define UARTE_INTENSET_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */ -#define UARTE_INTENSET_RXSTARTED_Set (1UL) /*!< Enable */ +#define UARTE_INTENSET_RXSTARTED_Disabled (0x0UL) /*!< Read: Disabled */ +#define UARTE_INTENSET_RXSTARTED_Enabled (0x1UL) /*!< Read: Enabled */ +#define UARTE_INTENSET_RXSTARTED_Set (0x1UL) /*!< Enable */ /* Bit 17 : Write '1' to enable interrupt for event RXTO */ #define UARTE_INTENSET_RXTO_Pos (17UL) /*!< Position of RXTO field. */ #define UARTE_INTENSET_RXTO_Msk (0x1UL << UARTE_INTENSET_RXTO_Pos) /*!< Bit mask of RXTO field. */ -#define UARTE_INTENSET_RXTO_Disabled (0UL) /*!< Read: Disabled */ -#define UARTE_INTENSET_RXTO_Enabled (1UL) /*!< Read: Enabled */ -#define UARTE_INTENSET_RXTO_Set (1UL) /*!< Enable */ +#define UARTE_INTENSET_RXTO_Disabled (0x0UL) /*!< Read: Disabled */ +#define UARTE_INTENSET_RXTO_Enabled (0x1UL) /*!< Read: Enabled */ +#define UARTE_INTENSET_RXTO_Set (0x1UL) /*!< Enable */ /* Bit 9 : Write '1' to enable interrupt for event ERROR */ #define UARTE_INTENSET_ERROR_Pos (9UL) /*!< Position of ERROR field. */ #define UARTE_INTENSET_ERROR_Msk (0x1UL << UARTE_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */ -#define UARTE_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */ -#define UARTE_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */ -#define UARTE_INTENSET_ERROR_Set (1UL) /*!< Enable */ +#define UARTE_INTENSET_ERROR_Disabled (0x0UL) /*!< Read: Disabled */ +#define UARTE_INTENSET_ERROR_Enabled (0x1UL) /*!< Read: Enabled */ +#define UARTE_INTENSET_ERROR_Set (0x1UL) /*!< Enable */ /* Bit 8 : Write '1' to enable interrupt for event ENDTX */ #define UARTE_INTENSET_ENDTX_Pos (8UL) /*!< Position of ENDTX field. */ #define UARTE_INTENSET_ENDTX_Msk (0x1UL << UARTE_INTENSET_ENDTX_Pos) /*!< Bit mask of ENDTX field. */ -#define UARTE_INTENSET_ENDTX_Disabled (0UL) /*!< Read: Disabled */ -#define UARTE_INTENSET_ENDTX_Enabled (1UL) /*!< Read: Enabled */ -#define UARTE_INTENSET_ENDTX_Set (1UL) /*!< Enable */ +#define UARTE_INTENSET_ENDTX_Disabled (0x0UL) /*!< Read: Disabled */ +#define UARTE_INTENSET_ENDTX_Enabled (0x1UL) /*!< Read: Enabled */ +#define UARTE_INTENSET_ENDTX_Set (0x1UL) /*!< Enable */ /* Bit 7 : Write '1' to enable interrupt for event TXDRDY */ #define UARTE_INTENSET_TXDRDY_Pos (7UL) /*!< Position of TXDRDY field. */ #define UARTE_INTENSET_TXDRDY_Msk (0x1UL << UARTE_INTENSET_TXDRDY_Pos) /*!< Bit mask of TXDRDY field. */ -#define UARTE_INTENSET_TXDRDY_Disabled (0UL) /*!< Read: Disabled */ -#define UARTE_INTENSET_TXDRDY_Enabled (1UL) /*!< Read: Enabled */ -#define UARTE_INTENSET_TXDRDY_Set (1UL) /*!< Enable */ +#define UARTE_INTENSET_TXDRDY_Disabled (0x0UL) /*!< Read: Disabled */ +#define UARTE_INTENSET_TXDRDY_Enabled (0x1UL) /*!< Read: Enabled */ +#define UARTE_INTENSET_TXDRDY_Set (0x1UL) /*!< Enable */ /* Bit 4 : Write '1' to enable interrupt for event ENDRX */ #define UARTE_INTENSET_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */ #define UARTE_INTENSET_ENDRX_Msk (0x1UL << UARTE_INTENSET_ENDRX_Pos) /*!< Bit mask of ENDRX field. */ -#define UARTE_INTENSET_ENDRX_Disabled (0UL) /*!< Read: Disabled */ -#define UARTE_INTENSET_ENDRX_Enabled (1UL) /*!< Read: Enabled */ -#define UARTE_INTENSET_ENDRX_Set (1UL) /*!< Enable */ +#define UARTE_INTENSET_ENDRX_Disabled (0x0UL) /*!< Read: Disabled */ +#define UARTE_INTENSET_ENDRX_Enabled (0x1UL) /*!< Read: Enabled */ +#define UARTE_INTENSET_ENDRX_Set (0x1UL) /*!< Enable */ /* Bit 2 : Write '1' to enable interrupt for event RXDRDY */ #define UARTE_INTENSET_RXDRDY_Pos (2UL) /*!< Position of RXDRDY field. */ #define UARTE_INTENSET_RXDRDY_Msk (0x1UL << UARTE_INTENSET_RXDRDY_Pos) /*!< Bit mask of RXDRDY field. */ -#define UARTE_INTENSET_RXDRDY_Disabled (0UL) /*!< Read: Disabled */ -#define UARTE_INTENSET_RXDRDY_Enabled (1UL) /*!< Read: Enabled */ -#define UARTE_INTENSET_RXDRDY_Set (1UL) /*!< Enable */ +#define UARTE_INTENSET_RXDRDY_Disabled (0x0UL) /*!< Read: Disabled */ +#define UARTE_INTENSET_RXDRDY_Enabled (0x1UL) /*!< Read: Enabled */ +#define UARTE_INTENSET_RXDRDY_Set (0x1UL) /*!< Enable */ /* Bit 1 : Write '1' to enable interrupt for event NCTS */ #define UARTE_INTENSET_NCTS_Pos (1UL) /*!< Position of NCTS field. */ #define UARTE_INTENSET_NCTS_Msk (0x1UL << UARTE_INTENSET_NCTS_Pos) /*!< Bit mask of NCTS field. */ -#define UARTE_INTENSET_NCTS_Disabled (0UL) /*!< Read: Disabled */ -#define UARTE_INTENSET_NCTS_Enabled (1UL) /*!< Read: Enabled */ -#define UARTE_INTENSET_NCTS_Set (1UL) /*!< Enable */ +#define UARTE_INTENSET_NCTS_Disabled (0x0UL) /*!< Read: Disabled */ +#define UARTE_INTENSET_NCTS_Enabled (0x1UL) /*!< Read: Enabled */ +#define UARTE_INTENSET_NCTS_Set (0x1UL) /*!< Enable */ /* Bit 0 : Write '1' to enable interrupt for event CTS */ #define UARTE_INTENSET_CTS_Pos (0UL) /*!< Position of CTS field. */ #define UARTE_INTENSET_CTS_Msk (0x1UL << UARTE_INTENSET_CTS_Pos) /*!< Bit mask of CTS field. */ -#define UARTE_INTENSET_CTS_Disabled (0UL) /*!< Read: Disabled */ -#define UARTE_INTENSET_CTS_Enabled (1UL) /*!< Read: Enabled */ -#define UARTE_INTENSET_CTS_Set (1UL) /*!< Enable */ +#define UARTE_INTENSET_CTS_Disabled (0x0UL) /*!< Read: Disabled */ +#define UARTE_INTENSET_CTS_Enabled (0x1UL) /*!< Read: Enabled */ +#define UARTE_INTENSET_CTS_Set (0x1UL) /*!< Enable */ /* Register: UARTE_INTENCLR */ /* Description: Disable interrupt */ @@ -10460,79 +10460,79 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 22 : Write '1' to disable interrupt for event TXSTOPPED */ #define UARTE_INTENCLR_TXSTOPPED_Pos (22UL) /*!< Position of TXSTOPPED field. */ #define UARTE_INTENCLR_TXSTOPPED_Msk (0x1UL << UARTE_INTENCLR_TXSTOPPED_Pos) /*!< Bit mask of TXSTOPPED field. */ -#define UARTE_INTENCLR_TXSTOPPED_Disabled (0UL) /*!< Read: Disabled */ -#define UARTE_INTENCLR_TXSTOPPED_Enabled (1UL) /*!< Read: Enabled */ -#define UARTE_INTENCLR_TXSTOPPED_Clear (1UL) /*!< Disable */ +#define UARTE_INTENCLR_TXSTOPPED_Disabled (0x0UL) /*!< Read: Disabled */ +#define UARTE_INTENCLR_TXSTOPPED_Enabled (0x1UL) /*!< Read: Enabled */ +#define UARTE_INTENCLR_TXSTOPPED_Clear (0x1UL) /*!< Disable */ /* Bit 20 : Write '1' to disable interrupt for event TXSTARTED */ #define UARTE_INTENCLR_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */ #define UARTE_INTENCLR_TXSTARTED_Msk (0x1UL << UARTE_INTENCLR_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */ -#define UARTE_INTENCLR_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */ -#define UARTE_INTENCLR_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */ -#define UARTE_INTENCLR_TXSTARTED_Clear (1UL) /*!< Disable */ +#define UARTE_INTENCLR_TXSTARTED_Disabled (0x0UL) /*!< Read: Disabled */ +#define UARTE_INTENCLR_TXSTARTED_Enabled (0x1UL) /*!< Read: Enabled */ +#define UARTE_INTENCLR_TXSTARTED_Clear (0x1UL) /*!< Disable */ /* Bit 19 : Write '1' to disable interrupt for event RXSTARTED */ #define UARTE_INTENCLR_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */ #define UARTE_INTENCLR_RXSTARTED_Msk (0x1UL << UARTE_INTENCLR_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */ -#define UARTE_INTENCLR_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */ -#define UARTE_INTENCLR_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */ -#define UARTE_INTENCLR_RXSTARTED_Clear (1UL) /*!< Disable */ +#define UARTE_INTENCLR_RXSTARTED_Disabled (0x0UL) /*!< Read: Disabled */ +#define UARTE_INTENCLR_RXSTARTED_Enabled (0x1UL) /*!< Read: Enabled */ +#define UARTE_INTENCLR_RXSTARTED_Clear (0x1UL) /*!< Disable */ /* Bit 17 : Write '1' to disable interrupt for event RXTO */ #define UARTE_INTENCLR_RXTO_Pos (17UL) /*!< Position of RXTO field. */ #define UARTE_INTENCLR_RXTO_Msk (0x1UL << UARTE_INTENCLR_RXTO_Pos) /*!< Bit mask of RXTO field. */ -#define UARTE_INTENCLR_RXTO_Disabled (0UL) /*!< Read: Disabled */ -#define UARTE_INTENCLR_RXTO_Enabled (1UL) /*!< Read: Enabled */ -#define UARTE_INTENCLR_RXTO_Clear (1UL) /*!< Disable */ +#define UARTE_INTENCLR_RXTO_Disabled (0x0UL) /*!< Read: Disabled */ +#define UARTE_INTENCLR_RXTO_Enabled (0x1UL) /*!< Read: Enabled */ +#define UARTE_INTENCLR_RXTO_Clear (0x1UL) /*!< Disable */ /* Bit 9 : Write '1' to disable interrupt for event ERROR */ #define UARTE_INTENCLR_ERROR_Pos (9UL) /*!< Position of ERROR field. */ #define UARTE_INTENCLR_ERROR_Msk (0x1UL << UARTE_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */ -#define UARTE_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */ -#define UARTE_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */ -#define UARTE_INTENCLR_ERROR_Clear (1UL) /*!< Disable */ +#define UARTE_INTENCLR_ERROR_Disabled (0x0UL) /*!< Read: Disabled */ +#define UARTE_INTENCLR_ERROR_Enabled (0x1UL) /*!< Read: Enabled */ +#define UARTE_INTENCLR_ERROR_Clear (0x1UL) /*!< Disable */ /* Bit 8 : Write '1' to disable interrupt for event ENDTX */ #define UARTE_INTENCLR_ENDTX_Pos (8UL) /*!< Position of ENDTX field. */ #define UARTE_INTENCLR_ENDTX_Msk (0x1UL << UARTE_INTENCLR_ENDTX_Pos) /*!< Bit mask of ENDTX field. */ -#define UARTE_INTENCLR_ENDTX_Disabled (0UL) /*!< Read: Disabled */ -#define UARTE_INTENCLR_ENDTX_Enabled (1UL) /*!< Read: Enabled */ -#define UARTE_INTENCLR_ENDTX_Clear (1UL) /*!< Disable */ +#define UARTE_INTENCLR_ENDTX_Disabled (0x0UL) /*!< Read: Disabled */ +#define UARTE_INTENCLR_ENDTX_Enabled (0x1UL) /*!< Read: Enabled */ +#define UARTE_INTENCLR_ENDTX_Clear (0x1UL) /*!< Disable */ /* Bit 7 : Write '1' to disable interrupt for event TXDRDY */ #define UARTE_INTENCLR_TXDRDY_Pos (7UL) /*!< Position of TXDRDY field. */ #define UARTE_INTENCLR_TXDRDY_Msk (0x1UL << UARTE_INTENCLR_TXDRDY_Pos) /*!< Bit mask of TXDRDY field. */ -#define UARTE_INTENCLR_TXDRDY_Disabled (0UL) /*!< Read: Disabled */ -#define UARTE_INTENCLR_TXDRDY_Enabled (1UL) /*!< Read: Enabled */ -#define UARTE_INTENCLR_TXDRDY_Clear (1UL) /*!< Disable */ +#define UARTE_INTENCLR_TXDRDY_Disabled (0x0UL) /*!< Read: Disabled */ +#define UARTE_INTENCLR_TXDRDY_Enabled (0x1UL) /*!< Read: Enabled */ +#define UARTE_INTENCLR_TXDRDY_Clear (0x1UL) /*!< Disable */ /* Bit 4 : Write '1' to disable interrupt for event ENDRX */ #define UARTE_INTENCLR_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */ #define UARTE_INTENCLR_ENDRX_Msk (0x1UL << UARTE_INTENCLR_ENDRX_Pos) /*!< Bit mask of ENDRX field. */ -#define UARTE_INTENCLR_ENDRX_Disabled (0UL) /*!< Read: Disabled */ -#define UARTE_INTENCLR_ENDRX_Enabled (1UL) /*!< Read: Enabled */ -#define UARTE_INTENCLR_ENDRX_Clear (1UL) /*!< Disable */ +#define UARTE_INTENCLR_ENDRX_Disabled (0x0UL) /*!< Read: Disabled */ +#define UARTE_INTENCLR_ENDRX_Enabled (0x1UL) /*!< Read: Enabled */ +#define UARTE_INTENCLR_ENDRX_Clear (0x1UL) /*!< Disable */ /* Bit 2 : Write '1' to disable interrupt for event RXDRDY */ #define UARTE_INTENCLR_RXDRDY_Pos (2UL) /*!< Position of RXDRDY field. */ #define UARTE_INTENCLR_RXDRDY_Msk (0x1UL << UARTE_INTENCLR_RXDRDY_Pos) /*!< Bit mask of RXDRDY field. */ -#define UARTE_INTENCLR_RXDRDY_Disabled (0UL) /*!< Read: Disabled */ -#define UARTE_INTENCLR_RXDRDY_Enabled (1UL) /*!< Read: Enabled */ -#define UARTE_INTENCLR_RXDRDY_Clear (1UL) /*!< Disable */ +#define UARTE_INTENCLR_RXDRDY_Disabled (0x0UL) /*!< Read: Disabled */ +#define UARTE_INTENCLR_RXDRDY_Enabled (0x1UL) /*!< Read: Enabled */ +#define UARTE_INTENCLR_RXDRDY_Clear (0x1UL) /*!< Disable */ /* Bit 1 : Write '1' to disable interrupt for event NCTS */ #define UARTE_INTENCLR_NCTS_Pos (1UL) /*!< Position of NCTS field. */ #define UARTE_INTENCLR_NCTS_Msk (0x1UL << UARTE_INTENCLR_NCTS_Pos) /*!< Bit mask of NCTS field. */ -#define UARTE_INTENCLR_NCTS_Disabled (0UL) /*!< Read: Disabled */ -#define UARTE_INTENCLR_NCTS_Enabled (1UL) /*!< Read: Enabled */ -#define UARTE_INTENCLR_NCTS_Clear (1UL) /*!< Disable */ +#define UARTE_INTENCLR_NCTS_Disabled (0x0UL) /*!< Read: Disabled */ +#define UARTE_INTENCLR_NCTS_Enabled (0x1UL) /*!< Read: Enabled */ +#define UARTE_INTENCLR_NCTS_Clear (0x1UL) /*!< Disable */ /* Bit 0 : Write '1' to disable interrupt for event CTS */ #define UARTE_INTENCLR_CTS_Pos (0UL) /*!< Position of CTS field. */ #define UARTE_INTENCLR_CTS_Msk (0x1UL << UARTE_INTENCLR_CTS_Pos) /*!< Bit mask of CTS field. */ -#define UARTE_INTENCLR_CTS_Disabled (0UL) /*!< Read: Disabled */ -#define UARTE_INTENCLR_CTS_Enabled (1UL) /*!< Read: Enabled */ -#define UARTE_INTENCLR_CTS_Clear (1UL) /*!< Disable */ +#define UARTE_INTENCLR_CTS_Disabled (0x0UL) /*!< Read: Disabled */ +#define UARTE_INTENCLR_CTS_Enabled (0x1UL) /*!< Read: Enabled */ +#define UARTE_INTENCLR_CTS_Clear (0x1UL) /*!< Disable */ /* Register: UARTE_ERRORSRC */ /* Description: Error source This register is read/write one to clear. */ @@ -10540,26 +10540,26 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 3 : Break condition */ #define UARTE_ERRORSRC_BREAK_Pos (3UL) /*!< Position of BREAK field. */ #define UARTE_ERRORSRC_BREAK_Msk (0x1UL << UARTE_ERRORSRC_BREAK_Pos) /*!< Bit mask of BREAK field. */ -#define UARTE_ERRORSRC_BREAK_NotPresent (0UL) /*!< Read: error not present */ -#define UARTE_ERRORSRC_BREAK_Present (1UL) /*!< Read: error present */ +#define UARTE_ERRORSRC_BREAK_NotPresent (0x0UL) /*!< Read: error not present */ +#define UARTE_ERRORSRC_BREAK_Present (0x1UL) /*!< Read: error present */ /* Bit 2 : Framing error occurred */ #define UARTE_ERRORSRC_FRAMING_Pos (2UL) /*!< Position of FRAMING field. */ #define UARTE_ERRORSRC_FRAMING_Msk (0x1UL << UARTE_ERRORSRC_FRAMING_Pos) /*!< Bit mask of FRAMING field. */ -#define UARTE_ERRORSRC_FRAMING_NotPresent (0UL) /*!< Read: error not present */ -#define UARTE_ERRORSRC_FRAMING_Present (1UL) /*!< Read: error present */ +#define UARTE_ERRORSRC_FRAMING_NotPresent (0x0UL) /*!< Read: error not present */ +#define UARTE_ERRORSRC_FRAMING_Present (0x1UL) /*!< Read: error present */ /* Bit 1 : Parity error */ #define UARTE_ERRORSRC_PARITY_Pos (1UL) /*!< Position of PARITY field. */ #define UARTE_ERRORSRC_PARITY_Msk (0x1UL << UARTE_ERRORSRC_PARITY_Pos) /*!< Bit mask of PARITY field. */ -#define UARTE_ERRORSRC_PARITY_NotPresent (0UL) /*!< Read: error not present */ -#define UARTE_ERRORSRC_PARITY_Present (1UL) /*!< Read: error present */ +#define UARTE_ERRORSRC_PARITY_NotPresent (0x0UL) /*!< Read: error not present */ +#define UARTE_ERRORSRC_PARITY_Present (0x1UL) /*!< Read: error present */ /* Bit 0 : Overrun error */ #define UARTE_ERRORSRC_OVERRUN_Pos (0UL) /*!< Position of OVERRUN field. */ #define UARTE_ERRORSRC_OVERRUN_Msk (0x1UL << UARTE_ERRORSRC_OVERRUN_Pos) /*!< Bit mask of OVERRUN field. */ -#define UARTE_ERRORSRC_OVERRUN_NotPresent (0UL) /*!< Read: error not present */ -#define UARTE_ERRORSRC_OVERRUN_Present (1UL) /*!< Read: error present */ +#define UARTE_ERRORSRC_OVERRUN_NotPresent (0x0UL) /*!< Read: error not present */ +#define UARTE_ERRORSRC_OVERRUN_Present (0x1UL) /*!< Read: error present */ /* Register: UARTE_ENABLE */ /* Description: Enable UART */ @@ -10567,8 +10567,8 @@ POSSIBILITY OF SUCH DAMAGE. /* Bits 3..0 : Enable or disable UARTE */ #define UARTE_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ #define UARTE_ENABLE_ENABLE_Msk (0xFUL << UARTE_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ -#define UARTE_ENABLE_ENABLE_Disabled (0UL) /*!< Disable UARTE */ -#define UARTE_ENABLE_ENABLE_Enabled (8UL) /*!< Enable UARTE */ +#define UARTE_ENABLE_ENABLE_Disabled (0x0UL) /*!< Disable UARTE */ +#define UARTE_ENABLE_ENABLE_Enabled (0x8UL) /*!< Enable UARTE */ /* Register: UARTE_PSEL_RTS */ /* Description: Pin select for RTS signal */ @@ -10576,8 +10576,8 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 31 : Connection */ #define UARTE_PSEL_RTS_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ #define UARTE_PSEL_RTS_CONNECT_Msk (0x1UL << UARTE_PSEL_RTS_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ -#define UARTE_PSEL_RTS_CONNECT_Connected (0UL) /*!< Connect */ -#define UARTE_PSEL_RTS_CONNECT_Disconnected (1UL) /*!< Disconnect */ +#define UARTE_PSEL_RTS_CONNECT_Connected (0x0UL) /*!< Connect */ +#define UARTE_PSEL_RTS_CONNECT_Disconnected (0x1UL) /*!< Disconnect */ /* Bits 4..0 : Pin number */ #define UARTE_PSEL_RTS_PIN_Pos (0UL) /*!< Position of PIN field. */ @@ -10589,8 +10589,8 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 31 : Connection */ #define UARTE_PSEL_TXD_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ #define UARTE_PSEL_TXD_CONNECT_Msk (0x1UL << UARTE_PSEL_TXD_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ -#define UARTE_PSEL_TXD_CONNECT_Connected (0UL) /*!< Connect */ -#define UARTE_PSEL_TXD_CONNECT_Disconnected (1UL) /*!< Disconnect */ +#define UARTE_PSEL_TXD_CONNECT_Connected (0x0UL) /*!< Connect */ +#define UARTE_PSEL_TXD_CONNECT_Disconnected (0x1UL) /*!< Disconnect */ /* Bits 4..0 : Pin number */ #define UARTE_PSEL_TXD_PIN_Pos (0UL) /*!< Position of PIN field. */ @@ -10602,8 +10602,8 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 31 : Connection */ #define UARTE_PSEL_CTS_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ #define UARTE_PSEL_CTS_CONNECT_Msk (0x1UL << UARTE_PSEL_CTS_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ -#define UARTE_PSEL_CTS_CONNECT_Connected (0UL) /*!< Connect */ -#define UARTE_PSEL_CTS_CONNECT_Disconnected (1UL) /*!< Disconnect */ +#define UARTE_PSEL_CTS_CONNECT_Connected (0x0UL) /*!< Connect */ +#define UARTE_PSEL_CTS_CONNECT_Disconnected (0x1UL) /*!< Disconnect */ /* Bits 4..0 : Pin number */ #define UARTE_PSEL_CTS_PIN_Pos (0UL) /*!< Position of PIN field. */ @@ -10615,8 +10615,8 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 31 : Connection */ #define UARTE_PSEL_RXD_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ #define UARTE_PSEL_RXD_CONNECT_Msk (0x1UL << UARTE_PSEL_RXD_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ -#define UARTE_PSEL_RXD_CONNECT_Connected (0UL) /*!< Connect */ -#define UARTE_PSEL_RXD_CONNECT_Disconnected (1UL) /*!< Disconnect */ +#define UARTE_PSEL_RXD_CONNECT_Connected (0x0UL) /*!< Connect */ +#define UARTE_PSEL_RXD_CONNECT_Disconnected (0x1UL) /*!< Disconnect */ /* Bits 4..0 : Pin number */ #define UARTE_PSEL_RXD_PIN_Pos (0UL) /*!< Position of PIN field. */ @@ -10695,8 +10695,8 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 4 : Stop bits */ #define UARTE_CONFIG_STOP_Pos (4UL) /*!< Position of STOP field. */ #define UARTE_CONFIG_STOP_Msk (0x1UL << UARTE_CONFIG_STOP_Pos) /*!< Bit mask of STOP field. */ -#define UARTE_CONFIG_STOP_One (0UL) /*!< One stop bit */ -#define UARTE_CONFIG_STOP_Two (1UL) /*!< Two stop bits */ +#define UARTE_CONFIG_STOP_One (0x0UL) /*!< One stop bit */ +#define UARTE_CONFIG_STOP_Two (0x1UL) /*!< Two stop bits */ /* Bits 3..1 : Parity */ #define UARTE_CONFIG_PARITY_Pos (1UL) /*!< Position of PARITY field. */ @@ -10707,8 +10707,8 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 0 : Hardware flow control */ #define UARTE_CONFIG_HWFC_Pos (0UL) /*!< Position of HWFC field. */ #define UARTE_CONFIG_HWFC_Msk (0x1UL << UARTE_CONFIG_HWFC_Pos) /*!< Bit mask of HWFC field. */ -#define UARTE_CONFIG_HWFC_Disabled (0UL) /*!< Disabled */ -#define UARTE_CONFIG_HWFC_Enabled (1UL) /*!< Enabled */ +#define UARTE_CONFIG_HWFC_Disabled (0x0UL) /*!< Disabled */ +#define UARTE_CONFIG_HWFC_Enabled (0x1UL) /*!< Enabled */ /* Peripheral: UICR */ @@ -10737,8 +10737,8 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 0 : HFXO clock source selection */ #define UICR_HFXOSRC_HFXOSRC_Pos (0UL) /*!< Position of HFXOSRC field. */ #define UICR_HFXOSRC_HFXOSRC_Msk (0x1UL << UICR_HFXOSRC_HFXOSRC_Pos) /*!< Bit mask of HFXOSRC field. */ -#define UICR_HFXOSRC_HFXOSRC_TCXO (0UL) /*!< 32 MHz temperature compensated crystal oscillator (TCXO) */ -#define UICR_HFXOSRC_HFXOSRC_XTAL (1UL) /*!< 32 MHz crystal oscillator */ +#define UICR_HFXOSRC_HFXOSRC_TCXO (0x0UL) /*!< 32 MHz temperature compensated crystal oscillator (TCXO) */ +#define UICR_HFXOSRC_HFXOSRC_XTAL (0x1UL) /*!< 32 MHz crystal oscillator */ /* Register: UICR_HFXOCNT */ /* Description: HFXO startup counter */ @@ -10746,8 +10746,8 @@ POSSIBILITY OF SUCH DAMAGE. /* Bits 7..0 : HFXO startup counter. Total debounce time = HFXOCNT*64 us + 0.5 us */ #define UICR_HFXOCNT_HFXOCNT_Pos (0UL) /*!< Position of HFXOCNT field. */ #define UICR_HFXOCNT_HFXOCNT_Msk (0xFFUL << UICR_HFXOCNT_HFXOCNT_Pos) /*!< Bit mask of HFXOCNT field. */ -#define UICR_HFXOCNT_HFXOCNT_MinDebounceTime (0UL) /*!< Min debounce time = (0*64 us + 0.5 us) */ -#define UICR_HFXOCNT_HFXOCNT_MaxDebounceTime (255UL) /*!< Max debounce time = (255*64 us + 0.5 us) */ +#define UICR_HFXOCNT_HFXOCNT_MinDebounceTime (0x00UL) /*!< Min debounce time = (0*64 us + 0.5 us) */ +#define UICR_HFXOCNT_HFXOCNT_MaxDebounceTime (0xFFUL) /*!< Max debounce time = (255*64 us + 0.5 us) */ /* Register: UICR_APPNVMCPOFGUARD */ /* Description: Enable blocking NVM WRITE and aborting NVM ERASE for Application NVM in POFWARN condition . */ @@ -10755,8 +10755,8 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 0 : Enable blocking NVM WRITE and aborting NVM ERASE in POFWARN condition */ #define UICR_APPNVMCPOFGUARD_NVMCPOFGUARDEN_Pos (0UL) /*!< Position of NVMCPOFGUARDEN field. */ #define UICR_APPNVMCPOFGUARD_NVMCPOFGUARDEN_Msk (0x1UL << UICR_APPNVMCPOFGUARD_NVMCPOFGUARDEN_Pos) /*!< Bit mask of NVMCPOFGUARDEN field. */ -#define UICR_APPNVMCPOFGUARD_NVMCPOFGUARDEN_Disabled (0UL) /*!< NVM WRITE and NVM ERASE are not blocked in POFWARN condition */ -#define UICR_APPNVMCPOFGUARD_NVMCPOFGUARDEN_Enabled (1UL) /*!< NVM WRITE and NVM ERASE are blocked in POFWARN condition */ +#define UICR_APPNVMCPOFGUARD_NVMCPOFGUARDEN_Disabled (0x0UL) /*!< NVM WRITE and NVM ERASE are not blocked in POFWARN condition */ +#define UICR_APPNVMCPOFGUARD_NVMCPOFGUARDEN_Enabled (0x1UL) /*!< NVM WRITE and NVM ERASE are blocked in POFWARN condition */ /* Register: UICR_PMICCONF */ /* Description: Polarity of PMIC polarity configuration signals. */ @@ -10764,8 +10764,8 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 0 : Polarity of PMIC_FPWM signal. */ #define UICR_PMICCONF_PMICFPWMPOL_Pos (0UL) /*!< Position of PMICFPWMPOL field. */ #define UICR_PMICCONF_PMICFPWMPOL_Msk (0x1UL << UICR_PMICCONF_PMICFPWMPOL_Pos) /*!< Bit mask of PMICFPWMPOL field. */ -#define UICR_PMICCONF_PMICFPWMPOL_ActiveLow (0UL) /*!< PMIC_FPWM output signal is active-low */ -#define UICR_PMICCONF_PMICFPWMPOL_ActiveHigh (1UL) /*!< PMIC_FPWM output signal is active-high */ +#define UICR_PMICCONF_PMICFPWMPOL_ActiveLow (0x0UL) /*!< PMIC_FPWM output signal is active-low */ +#define UICR_PMICCONF_PMICFPWMPOL_ActiveHigh (0x1UL) /*!< PMIC_FPWM output signal is active-high */ /* Register: UICR_SECUREAPPROTECT */ /* Description: Secure access port protection */ @@ -10813,26 +10813,26 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 16 : Revocation state for the key slot */ #define UICR_KEYSLOT_CONFIG_PERM_STATE_Pos (16UL) /*!< Position of STATE field. */ #define UICR_KEYSLOT_CONFIG_PERM_STATE_Msk (0x1UL << UICR_KEYSLOT_CONFIG_PERM_STATE_Pos) /*!< Bit mask of STATE field. */ -#define UICR_KEYSLOT_CONFIG_PERM_STATE_Revoked (0UL) /*!< Key value registers can no longer be read or pushed */ -#define UICR_KEYSLOT_CONFIG_PERM_STATE_Active (1UL) /*!< Key value registers are readable (if enabled) and can be pushed (if enabled) */ +#define UICR_KEYSLOT_CONFIG_PERM_STATE_Revoked (0x0UL) /*!< Key value registers can no longer be read or pushed */ +#define UICR_KEYSLOT_CONFIG_PERM_STATE_Active (0x1UL) /*!< Key value registers are readable (if enabled) and can be pushed (if enabled) */ /* Bit 2 : Push permission for key slot */ #define UICR_KEYSLOT_CONFIG_PERM_PUSH_Pos (2UL) /*!< Position of PUSH field. */ #define UICR_KEYSLOT_CONFIG_PERM_PUSH_Msk (0x1UL << UICR_KEYSLOT_CONFIG_PERM_PUSH_Pos) /*!< Bit mask of PUSH field. */ -#define UICR_KEYSLOT_CONFIG_PERM_PUSH_Disabled (0UL) /*!< Disable pushing of key value registers over secure APB, but can be read if field READ is Enabled */ -#define UICR_KEYSLOT_CONFIG_PERM_PUSH_Enabled (1UL) /*!< Enable pushing of key value registers over secure APB. Register KEYSLOT.CONFIGn.DEST must contain a valid destination address! */ +#define UICR_KEYSLOT_CONFIG_PERM_PUSH_Disabled (0x0UL) /*!< Disable pushing of key value registers over secure APB, but can be read if field READ is Enabled */ +#define UICR_KEYSLOT_CONFIG_PERM_PUSH_Enabled (0x1UL) /*!< Enable pushing of key value registers over secure APB. Register KEYSLOT.CONFIGn.DEST must contain a valid destination address! */ /* Bit 1 : Read permission for key slot */ #define UICR_KEYSLOT_CONFIG_PERM_READ_Pos (1UL) /*!< Position of READ field. */ #define UICR_KEYSLOT_CONFIG_PERM_READ_Msk (0x1UL << UICR_KEYSLOT_CONFIG_PERM_READ_Pos) /*!< Bit mask of READ field. */ -#define UICR_KEYSLOT_CONFIG_PERM_READ_Disabled (0UL) /*!< Disable read from key value registers */ -#define UICR_KEYSLOT_CONFIG_PERM_READ_Enabled (1UL) /*!< Enable read from key value registers */ +#define UICR_KEYSLOT_CONFIG_PERM_READ_Disabled (0x0UL) /*!< Disable read from key value registers */ +#define UICR_KEYSLOT_CONFIG_PERM_READ_Enabled (0x1UL) /*!< Enable read from key value registers */ /* Bit 0 : Write permission for key slot */ #define UICR_KEYSLOT_CONFIG_PERM_WRITE_Pos (0UL) /*!< Position of WRITE field. */ #define UICR_KEYSLOT_CONFIG_PERM_WRITE_Msk (0x1UL << UICR_KEYSLOT_CONFIG_PERM_WRITE_Pos) /*!< Bit mask of WRITE field. */ -#define UICR_KEYSLOT_CONFIG_PERM_WRITE_Disabled (0UL) /*!< Disable write to the key value registers */ -#define UICR_KEYSLOT_CONFIG_PERM_WRITE_Enabled (1UL) /*!< Enable write to the key value registers */ +#define UICR_KEYSLOT_CONFIG_PERM_WRITE_Disabled (0x0UL) /*!< Disable write to the key value registers */ +#define UICR_KEYSLOT_CONFIG_PERM_WRITE_Enabled (0x1UL) /*!< Enable write to the key value registers */ /* Register: UICR_KEYSLOT_KEY_VALUE */ /* Description: Description collection: Define bits [31+o*32:0+o*32] of value assigned to KMU key slot. */ @@ -10851,50 +10851,50 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 19 : Keep retention on RAM section S3 of RAM n when RAM section is switched off */ #define VMC_RAM_POWER_S3RETENTION_Pos (19UL) /*!< Position of S3RETENTION field. */ #define VMC_RAM_POWER_S3RETENTION_Msk (0x1UL << VMC_RAM_POWER_S3RETENTION_Pos) /*!< Bit mask of S3RETENTION field. */ -#define VMC_RAM_POWER_S3RETENTION_Off (0UL) /*!< Off */ -#define VMC_RAM_POWER_S3RETENTION_On (1UL) /*!< On */ +#define VMC_RAM_POWER_S3RETENTION_Off (0x0UL) /*!< Off */ +#define VMC_RAM_POWER_S3RETENTION_On (0x1UL) /*!< On */ /* Bit 18 : Keep retention on RAM section S2 of RAM n when RAM section is switched off */ #define VMC_RAM_POWER_S2RETENTION_Pos (18UL) /*!< Position of S2RETENTION field. */ #define VMC_RAM_POWER_S2RETENTION_Msk (0x1UL << VMC_RAM_POWER_S2RETENTION_Pos) /*!< Bit mask of S2RETENTION field. */ -#define VMC_RAM_POWER_S2RETENTION_Off (0UL) /*!< Off */ -#define VMC_RAM_POWER_S2RETENTION_On (1UL) /*!< On */ +#define VMC_RAM_POWER_S2RETENTION_Off (0x0UL) /*!< Off */ +#define VMC_RAM_POWER_S2RETENTION_On (0x1UL) /*!< On */ /* Bit 17 : Keep retention on RAM section S1 of RAM n when RAM section is switched off */ #define VMC_RAM_POWER_S1RETENTION_Pos (17UL) /*!< Position of S1RETENTION field. */ #define VMC_RAM_POWER_S1RETENTION_Msk (0x1UL << VMC_RAM_POWER_S1RETENTION_Pos) /*!< Bit mask of S1RETENTION field. */ -#define VMC_RAM_POWER_S1RETENTION_Off (0UL) /*!< Off */ -#define VMC_RAM_POWER_S1RETENTION_On (1UL) /*!< On */ +#define VMC_RAM_POWER_S1RETENTION_Off (0x0UL) /*!< Off */ +#define VMC_RAM_POWER_S1RETENTION_On (0x1UL) /*!< On */ /* Bit 16 : Keep retention on RAM section S0 of RAM n when RAM section is switched off */ #define VMC_RAM_POWER_S0RETENTION_Pos (16UL) /*!< Position of S0RETENTION field. */ #define VMC_RAM_POWER_S0RETENTION_Msk (0x1UL << VMC_RAM_POWER_S0RETENTION_Pos) /*!< Bit mask of S0RETENTION field. */ -#define VMC_RAM_POWER_S0RETENTION_Off (0UL) /*!< Off */ -#define VMC_RAM_POWER_S0RETENTION_On (1UL) /*!< On */ +#define VMC_RAM_POWER_S0RETENTION_Off (0x0UL) /*!< Off */ +#define VMC_RAM_POWER_S0RETENTION_On (0x1UL) /*!< On */ /* Bit 3 : Keep RAM section S3 of RAM n on or off in System ON mode */ #define VMC_RAM_POWER_S3POWER_Pos (3UL) /*!< Position of S3POWER field. */ #define VMC_RAM_POWER_S3POWER_Msk (0x1UL << VMC_RAM_POWER_S3POWER_Pos) /*!< Bit mask of S3POWER field. */ -#define VMC_RAM_POWER_S3POWER_Off (0UL) /*!< Off */ -#define VMC_RAM_POWER_S3POWER_On (1UL) /*!< On */ +#define VMC_RAM_POWER_S3POWER_Off (0x0UL) /*!< Off */ +#define VMC_RAM_POWER_S3POWER_On (0x1UL) /*!< On */ /* Bit 2 : Keep RAM section S2 of RAM n on or off in System ON mode */ #define VMC_RAM_POWER_S2POWER_Pos (2UL) /*!< Position of S2POWER field. */ #define VMC_RAM_POWER_S2POWER_Msk (0x1UL << VMC_RAM_POWER_S2POWER_Pos) /*!< Bit mask of S2POWER field. */ -#define VMC_RAM_POWER_S2POWER_Off (0UL) /*!< Off */ -#define VMC_RAM_POWER_S2POWER_On (1UL) /*!< On */ +#define VMC_RAM_POWER_S2POWER_Off (0x0UL) /*!< Off */ +#define VMC_RAM_POWER_S2POWER_On (0x1UL) /*!< On */ /* Bit 1 : Keep RAM section S1 of RAM n on or off in System ON mode */ #define VMC_RAM_POWER_S1POWER_Pos (1UL) /*!< Position of S1POWER field. */ #define VMC_RAM_POWER_S1POWER_Msk (0x1UL << VMC_RAM_POWER_S1POWER_Pos) /*!< Bit mask of S1POWER field. */ -#define VMC_RAM_POWER_S1POWER_Off (0UL) /*!< Off */ -#define VMC_RAM_POWER_S1POWER_On (1UL) /*!< On */ +#define VMC_RAM_POWER_S1POWER_Off (0x0UL) /*!< Off */ +#define VMC_RAM_POWER_S1POWER_On (0x1UL) /*!< On */ /* Bit 0 : Keep RAM section S0 of RAM n on or off in System ON mode */ #define VMC_RAM_POWER_S0POWER_Pos (0UL) /*!< Position of S0POWER field. */ #define VMC_RAM_POWER_S0POWER_Msk (0x1UL << VMC_RAM_POWER_S0POWER_Pos) /*!< Bit mask of S0POWER field. */ -#define VMC_RAM_POWER_S0POWER_Off (0UL) /*!< Off */ -#define VMC_RAM_POWER_S0POWER_On (1UL) /*!< On */ +#define VMC_RAM_POWER_S0POWER_Off (0x0UL) /*!< Off */ +#define VMC_RAM_POWER_S0POWER_On (0x1UL) /*!< On */ /* Register: VMC_RAM_POWERSET */ /* Description: Description cluster: RAMn power control set register */ @@ -10902,42 +10902,42 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 19 : Keep retention on RAM section S3 of RAM n when RAM section is switched off */ #define VMC_RAM_POWERSET_S3RETENTION_Pos (19UL) /*!< Position of S3RETENTION field. */ #define VMC_RAM_POWERSET_S3RETENTION_Msk (0x1UL << VMC_RAM_POWERSET_S3RETENTION_Pos) /*!< Bit mask of S3RETENTION field. */ -#define VMC_RAM_POWERSET_S3RETENTION_On (1UL) /*!< On */ +#define VMC_RAM_POWERSET_S3RETENTION_On (0x1UL) /*!< On */ /* Bit 18 : Keep retention on RAM section S2 of RAM n when RAM section is switched off */ #define VMC_RAM_POWERSET_S2RETENTION_Pos (18UL) /*!< Position of S2RETENTION field. */ #define VMC_RAM_POWERSET_S2RETENTION_Msk (0x1UL << VMC_RAM_POWERSET_S2RETENTION_Pos) /*!< Bit mask of S2RETENTION field. */ -#define VMC_RAM_POWERSET_S2RETENTION_On (1UL) /*!< On */ +#define VMC_RAM_POWERSET_S2RETENTION_On (0x1UL) /*!< On */ /* Bit 17 : Keep retention on RAM section S1 of RAM n when RAM section is switched off */ #define VMC_RAM_POWERSET_S1RETENTION_Pos (17UL) /*!< Position of S1RETENTION field. */ #define VMC_RAM_POWERSET_S1RETENTION_Msk (0x1UL << VMC_RAM_POWERSET_S1RETENTION_Pos) /*!< Bit mask of S1RETENTION field. */ -#define VMC_RAM_POWERSET_S1RETENTION_On (1UL) /*!< On */ +#define VMC_RAM_POWERSET_S1RETENTION_On (0x1UL) /*!< On */ /* Bit 16 : Keep retention on RAM section S0 of RAM n when RAM section is switched off */ #define VMC_RAM_POWERSET_S0RETENTION_Pos (16UL) /*!< Position of S0RETENTION field. */ #define VMC_RAM_POWERSET_S0RETENTION_Msk (0x1UL << VMC_RAM_POWERSET_S0RETENTION_Pos) /*!< Bit mask of S0RETENTION field. */ -#define VMC_RAM_POWERSET_S0RETENTION_On (1UL) /*!< On */ +#define VMC_RAM_POWERSET_S0RETENTION_On (0x1UL) /*!< On */ /* Bit 3 : Keep RAM section S3 of RAM n on or off in System ON mode */ #define VMC_RAM_POWERSET_S3POWER_Pos (3UL) /*!< Position of S3POWER field. */ #define VMC_RAM_POWERSET_S3POWER_Msk (0x1UL << VMC_RAM_POWERSET_S3POWER_Pos) /*!< Bit mask of S3POWER field. */ -#define VMC_RAM_POWERSET_S3POWER_On (1UL) /*!< On */ +#define VMC_RAM_POWERSET_S3POWER_On (0x1UL) /*!< On */ /* Bit 2 : Keep RAM section S2 of RAM n on or off in System ON mode */ #define VMC_RAM_POWERSET_S2POWER_Pos (2UL) /*!< Position of S2POWER field. */ #define VMC_RAM_POWERSET_S2POWER_Msk (0x1UL << VMC_RAM_POWERSET_S2POWER_Pos) /*!< Bit mask of S2POWER field. */ -#define VMC_RAM_POWERSET_S2POWER_On (1UL) /*!< On */ +#define VMC_RAM_POWERSET_S2POWER_On (0x1UL) /*!< On */ /* Bit 1 : Keep RAM section S1 of RAM n on or off in System ON mode */ #define VMC_RAM_POWERSET_S1POWER_Pos (1UL) /*!< Position of S1POWER field. */ #define VMC_RAM_POWERSET_S1POWER_Msk (0x1UL << VMC_RAM_POWERSET_S1POWER_Pos) /*!< Bit mask of S1POWER field. */ -#define VMC_RAM_POWERSET_S1POWER_On (1UL) /*!< On */ +#define VMC_RAM_POWERSET_S1POWER_On (0x1UL) /*!< On */ /* Bit 0 : Keep RAM section S0 of RAM n on or off in System ON mode */ #define VMC_RAM_POWERSET_S0POWER_Pos (0UL) /*!< Position of S0POWER field. */ #define VMC_RAM_POWERSET_S0POWER_Msk (0x1UL << VMC_RAM_POWERSET_S0POWER_Pos) /*!< Bit mask of S0POWER field. */ -#define VMC_RAM_POWERSET_S0POWER_On (1UL) /*!< On */ +#define VMC_RAM_POWERSET_S0POWER_On (0x1UL) /*!< On */ /* Register: VMC_RAM_POWERCLR */ /* Description: Description cluster: RAMn power control clear register */ @@ -10945,42 +10945,42 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 19 : Keep retention on RAM section S3 of RAM n when RAM section is switched off */ #define VMC_RAM_POWERCLR_S3RETENTION_Pos (19UL) /*!< Position of S3RETENTION field. */ #define VMC_RAM_POWERCLR_S3RETENTION_Msk (0x1UL << VMC_RAM_POWERCLR_S3RETENTION_Pos) /*!< Bit mask of S3RETENTION field. */ -#define VMC_RAM_POWERCLR_S3RETENTION_Off (1UL) /*!< Off */ +#define VMC_RAM_POWERCLR_S3RETENTION_Off (0x1UL) /*!< Off */ /* Bit 18 : Keep retention on RAM section S2 of RAM n when RAM section is switched off */ #define VMC_RAM_POWERCLR_S2RETENTION_Pos (18UL) /*!< Position of S2RETENTION field. */ #define VMC_RAM_POWERCLR_S2RETENTION_Msk (0x1UL << VMC_RAM_POWERCLR_S2RETENTION_Pos) /*!< Bit mask of S2RETENTION field. */ -#define VMC_RAM_POWERCLR_S2RETENTION_Off (1UL) /*!< Off */ +#define VMC_RAM_POWERCLR_S2RETENTION_Off (0x1UL) /*!< Off */ /* Bit 17 : Keep retention on RAM section S1 of RAM n when RAM section is switched off */ #define VMC_RAM_POWERCLR_S1RETENTION_Pos (17UL) /*!< Position of S1RETENTION field. */ #define VMC_RAM_POWERCLR_S1RETENTION_Msk (0x1UL << VMC_RAM_POWERCLR_S1RETENTION_Pos) /*!< Bit mask of S1RETENTION field. */ -#define VMC_RAM_POWERCLR_S1RETENTION_Off (1UL) /*!< Off */ +#define VMC_RAM_POWERCLR_S1RETENTION_Off (0x1UL) /*!< Off */ /* Bit 16 : Keep retention on RAM section S0 of RAM n when RAM section is switched off */ #define VMC_RAM_POWERCLR_S0RETENTION_Pos (16UL) /*!< Position of S0RETENTION field. */ #define VMC_RAM_POWERCLR_S0RETENTION_Msk (0x1UL << VMC_RAM_POWERCLR_S0RETENTION_Pos) /*!< Bit mask of S0RETENTION field. */ -#define VMC_RAM_POWERCLR_S0RETENTION_Off (1UL) /*!< Off */ +#define VMC_RAM_POWERCLR_S0RETENTION_Off (0x1UL) /*!< Off */ /* Bit 3 : Keep RAM section S3 of RAM n on or off in System ON mode */ #define VMC_RAM_POWERCLR_S3POWER_Pos (3UL) /*!< Position of S3POWER field. */ #define VMC_RAM_POWERCLR_S3POWER_Msk (0x1UL << VMC_RAM_POWERCLR_S3POWER_Pos) /*!< Bit mask of S3POWER field. */ -#define VMC_RAM_POWERCLR_S3POWER_Off (1UL) /*!< Off */ +#define VMC_RAM_POWERCLR_S3POWER_Off (0x1UL) /*!< Off */ /* Bit 2 : Keep RAM section S2 of RAM n on or off in System ON mode */ #define VMC_RAM_POWERCLR_S2POWER_Pos (2UL) /*!< Position of S2POWER field. */ #define VMC_RAM_POWERCLR_S2POWER_Msk (0x1UL << VMC_RAM_POWERCLR_S2POWER_Pos) /*!< Bit mask of S2POWER field. */ -#define VMC_RAM_POWERCLR_S2POWER_Off (1UL) /*!< Off */ +#define VMC_RAM_POWERCLR_S2POWER_Off (0x1UL) /*!< Off */ /* Bit 1 : Keep RAM section S1 of RAM n on or off in System ON mode */ #define VMC_RAM_POWERCLR_S1POWER_Pos (1UL) /*!< Position of S1POWER field. */ #define VMC_RAM_POWERCLR_S1POWER_Msk (0x1UL << VMC_RAM_POWERCLR_S1POWER_Pos) /*!< Bit mask of S1POWER field. */ -#define VMC_RAM_POWERCLR_S1POWER_Off (1UL) /*!< Off */ +#define VMC_RAM_POWERCLR_S1POWER_Off (0x1UL) /*!< Off */ /* Bit 0 : Keep RAM section S0 of RAM n on or off in System ON mode */ #define VMC_RAM_POWERCLR_S0POWER_Pos (0UL) /*!< Position of S0POWER field. */ #define VMC_RAM_POWERCLR_S0POWER_Msk (0x1UL << VMC_RAM_POWERCLR_S0POWER_Pos) /*!< Bit mask of S0POWER field. */ -#define VMC_RAM_POWERCLR_S0POWER_Off (1UL) /*!< Off */ +#define VMC_RAM_POWERCLR_S0POWER_Off (0x1UL) /*!< Off */ /* Peripheral: WDT */ @@ -10992,7 +10992,7 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 0 : Start the watchdog */ #define WDT_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */ #define WDT_TASKS_START_TASKS_START_Msk (0x1UL << WDT_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */ -#define WDT_TASKS_START_TASKS_START_Trigger (1UL) /*!< Trigger task */ +#define WDT_TASKS_START_TASKS_START_Trigger (0x1UL) /*!< Trigger task */ /* Register: WDT_SUBSCRIBE_START */ /* Description: Subscribe configuration for task START */ @@ -11000,8 +11000,8 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 31 : */ #define WDT_SUBSCRIBE_START_EN_Pos (31UL) /*!< Position of EN field. */ #define WDT_SUBSCRIBE_START_EN_Msk (0x1UL << WDT_SUBSCRIBE_START_EN_Pos) /*!< Bit mask of EN field. */ -#define WDT_SUBSCRIBE_START_EN_Disabled (0UL) /*!< Disable subscription */ -#define WDT_SUBSCRIBE_START_EN_Enabled (1UL) /*!< Enable subscription */ +#define WDT_SUBSCRIBE_START_EN_Disabled (0x0UL) /*!< Disable subscription */ +#define WDT_SUBSCRIBE_START_EN_Enabled (0x1UL) /*!< Enable subscription */ /* Bits 7..0 : DPPI channel that task START will subscribe to */ #define WDT_SUBSCRIBE_START_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ @@ -11013,8 +11013,8 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 0 : Watchdog timeout */ #define WDT_EVENTS_TIMEOUT_EVENTS_TIMEOUT_Pos (0UL) /*!< Position of EVENTS_TIMEOUT field. */ #define WDT_EVENTS_TIMEOUT_EVENTS_TIMEOUT_Msk (0x1UL << WDT_EVENTS_TIMEOUT_EVENTS_TIMEOUT_Pos) /*!< Bit mask of EVENTS_TIMEOUT field. */ -#define WDT_EVENTS_TIMEOUT_EVENTS_TIMEOUT_NotGenerated (0UL) /*!< Event not generated */ -#define WDT_EVENTS_TIMEOUT_EVENTS_TIMEOUT_Generated (1UL) /*!< Event generated */ +#define WDT_EVENTS_TIMEOUT_EVENTS_TIMEOUT_NotGenerated (0x0UL) /*!< Event not generated */ +#define WDT_EVENTS_TIMEOUT_EVENTS_TIMEOUT_Generated (0x1UL) /*!< Event generated */ /* Register: WDT_PUBLISH_TIMEOUT */ /* Description: Publish configuration for event TIMEOUT */ @@ -11022,8 +11022,8 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 31 : */ #define WDT_PUBLISH_TIMEOUT_EN_Pos (31UL) /*!< Position of EN field. */ #define WDT_PUBLISH_TIMEOUT_EN_Msk (0x1UL << WDT_PUBLISH_TIMEOUT_EN_Pos) /*!< Bit mask of EN field. */ -#define WDT_PUBLISH_TIMEOUT_EN_Disabled (0UL) /*!< Disable publishing */ -#define WDT_PUBLISH_TIMEOUT_EN_Enabled (1UL) /*!< Enable publishing */ +#define WDT_PUBLISH_TIMEOUT_EN_Disabled (0x0UL) /*!< Disable publishing */ +#define WDT_PUBLISH_TIMEOUT_EN_Enabled (0x1UL) /*!< Enable publishing */ /* Bits 7..0 : DPPI channel that event TIMEOUT will publish to */ #define WDT_PUBLISH_TIMEOUT_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ @@ -11035,9 +11035,9 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 0 : Write '1' to enable interrupt for event TIMEOUT */ #define WDT_INTENSET_TIMEOUT_Pos (0UL) /*!< Position of TIMEOUT field. */ #define WDT_INTENSET_TIMEOUT_Msk (0x1UL << WDT_INTENSET_TIMEOUT_Pos) /*!< Bit mask of TIMEOUT field. */ -#define WDT_INTENSET_TIMEOUT_Disabled (0UL) /*!< Read: Disabled */ -#define WDT_INTENSET_TIMEOUT_Enabled (1UL) /*!< Read: Enabled */ -#define WDT_INTENSET_TIMEOUT_Set (1UL) /*!< Enable */ +#define WDT_INTENSET_TIMEOUT_Disabled (0x0UL) /*!< Read: Disabled */ +#define WDT_INTENSET_TIMEOUT_Enabled (0x1UL) /*!< Read: Enabled */ +#define WDT_INTENSET_TIMEOUT_Set (0x1UL) /*!< Enable */ /* Register: WDT_INTENCLR */ /* Description: Disable interrupt */ @@ -11045,9 +11045,9 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 0 : Write '1' to disable interrupt for event TIMEOUT */ #define WDT_INTENCLR_TIMEOUT_Pos (0UL) /*!< Position of TIMEOUT field. */ #define WDT_INTENCLR_TIMEOUT_Msk (0x1UL << WDT_INTENCLR_TIMEOUT_Pos) /*!< Bit mask of TIMEOUT field. */ -#define WDT_INTENCLR_TIMEOUT_Disabled (0UL) /*!< Read: Disabled */ -#define WDT_INTENCLR_TIMEOUT_Enabled (1UL) /*!< Read: Enabled */ -#define WDT_INTENCLR_TIMEOUT_Clear (1UL) /*!< Disable */ +#define WDT_INTENCLR_TIMEOUT_Disabled (0x0UL) /*!< Read: Disabled */ +#define WDT_INTENCLR_TIMEOUT_Enabled (0x1UL) /*!< Read: Enabled */ +#define WDT_INTENCLR_TIMEOUT_Clear (0x1UL) /*!< Disable */ /* Register: WDT_RUNSTATUS */ /* Description: Run status */ @@ -11055,8 +11055,8 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 0 : Indicates whether or not the watchdog is running */ #define WDT_RUNSTATUS_RUNSTATUSWDT_Pos (0UL) /*!< Position of RUNSTATUSWDT field. */ #define WDT_RUNSTATUS_RUNSTATUSWDT_Msk (0x1UL << WDT_RUNSTATUS_RUNSTATUSWDT_Pos) /*!< Bit mask of RUNSTATUSWDT field. */ -#define WDT_RUNSTATUS_RUNSTATUSWDT_NotRunning (0UL) /*!< Watchdog not running */ -#define WDT_RUNSTATUS_RUNSTATUSWDT_Running (1UL) /*!< Watchdog is running */ +#define WDT_RUNSTATUS_RUNSTATUSWDT_NotRunning (0x0UL) /*!< Watchdog not running */ +#define WDT_RUNSTATUS_RUNSTATUSWDT_Running (0x1UL) /*!< Watchdog is running */ /* Register: WDT_REQSTATUS */ /* Description: Request status */ @@ -11064,50 +11064,50 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 7 : Request status for RR[7] register */ #define WDT_REQSTATUS_RR7_Pos (7UL) /*!< Position of RR7 field. */ #define WDT_REQSTATUS_RR7_Msk (0x1UL << WDT_REQSTATUS_RR7_Pos) /*!< Bit mask of RR7 field. */ -#define WDT_REQSTATUS_RR7_DisabledOrRequested (0UL) /*!< RR[7] register is not enabled, or are already requesting reload */ -#define WDT_REQSTATUS_RR7_EnabledAndUnrequested (1UL) /*!< RR[7] register is enabled, and are not yet requesting reload */ +#define WDT_REQSTATUS_RR7_DisabledOrRequested (0x0UL) /*!< RR[7] register is not enabled, or are already requesting reload */ +#define WDT_REQSTATUS_RR7_EnabledAndUnrequested (0x1UL) /*!< RR[7] register is enabled, and are not yet requesting reload */ /* Bit 6 : Request status for RR[6] register */ #define WDT_REQSTATUS_RR6_Pos (6UL) /*!< Position of RR6 field. */ #define WDT_REQSTATUS_RR6_Msk (0x1UL << WDT_REQSTATUS_RR6_Pos) /*!< Bit mask of RR6 field. */ -#define WDT_REQSTATUS_RR6_DisabledOrRequested (0UL) /*!< RR[6] register is not enabled, or are already requesting reload */ -#define WDT_REQSTATUS_RR6_EnabledAndUnrequested (1UL) /*!< RR[6] register is enabled, and are not yet requesting reload */ +#define WDT_REQSTATUS_RR6_DisabledOrRequested (0x0UL) /*!< RR[6] register is not enabled, or are already requesting reload */ +#define WDT_REQSTATUS_RR6_EnabledAndUnrequested (0x1UL) /*!< RR[6] register is enabled, and are not yet requesting reload */ /* Bit 5 : Request status for RR[5] register */ #define WDT_REQSTATUS_RR5_Pos (5UL) /*!< Position of RR5 field. */ #define WDT_REQSTATUS_RR5_Msk (0x1UL << WDT_REQSTATUS_RR5_Pos) /*!< Bit mask of RR5 field. */ -#define WDT_REQSTATUS_RR5_DisabledOrRequested (0UL) /*!< RR[5] register is not enabled, or are already requesting reload */ -#define WDT_REQSTATUS_RR5_EnabledAndUnrequested (1UL) /*!< RR[5] register is enabled, and are not yet requesting reload */ +#define WDT_REQSTATUS_RR5_DisabledOrRequested (0x0UL) /*!< RR[5] register is not enabled, or are already requesting reload */ +#define WDT_REQSTATUS_RR5_EnabledAndUnrequested (0x1UL) /*!< RR[5] register is enabled, and are not yet requesting reload */ /* Bit 4 : Request status for RR[4] register */ #define WDT_REQSTATUS_RR4_Pos (4UL) /*!< Position of RR4 field. */ #define WDT_REQSTATUS_RR4_Msk (0x1UL << WDT_REQSTATUS_RR4_Pos) /*!< Bit mask of RR4 field. */ -#define WDT_REQSTATUS_RR4_DisabledOrRequested (0UL) /*!< RR[4] register is not enabled, or are already requesting reload */ -#define WDT_REQSTATUS_RR4_EnabledAndUnrequested (1UL) /*!< RR[4] register is enabled, and are not yet requesting reload */ +#define WDT_REQSTATUS_RR4_DisabledOrRequested (0x0UL) /*!< RR[4] register is not enabled, or are already requesting reload */ +#define WDT_REQSTATUS_RR4_EnabledAndUnrequested (0x1UL) /*!< RR[4] register is enabled, and are not yet requesting reload */ /* Bit 3 : Request status for RR[3] register */ #define WDT_REQSTATUS_RR3_Pos (3UL) /*!< Position of RR3 field. */ #define WDT_REQSTATUS_RR3_Msk (0x1UL << WDT_REQSTATUS_RR3_Pos) /*!< Bit mask of RR3 field. */ -#define WDT_REQSTATUS_RR3_DisabledOrRequested (0UL) /*!< RR[3] register is not enabled, or are already requesting reload */ -#define WDT_REQSTATUS_RR3_EnabledAndUnrequested (1UL) /*!< RR[3] register is enabled, and are not yet requesting reload */ +#define WDT_REQSTATUS_RR3_DisabledOrRequested (0x0UL) /*!< RR[3] register is not enabled, or are already requesting reload */ +#define WDT_REQSTATUS_RR3_EnabledAndUnrequested (0x1UL) /*!< RR[3] register is enabled, and are not yet requesting reload */ /* Bit 2 : Request status for RR[2] register */ #define WDT_REQSTATUS_RR2_Pos (2UL) /*!< Position of RR2 field. */ #define WDT_REQSTATUS_RR2_Msk (0x1UL << WDT_REQSTATUS_RR2_Pos) /*!< Bit mask of RR2 field. */ -#define WDT_REQSTATUS_RR2_DisabledOrRequested (0UL) /*!< RR[2] register is not enabled, or are already requesting reload */ -#define WDT_REQSTATUS_RR2_EnabledAndUnrequested (1UL) /*!< RR[2] register is enabled, and are not yet requesting reload */ +#define WDT_REQSTATUS_RR2_DisabledOrRequested (0x0UL) /*!< RR[2] register is not enabled, or are already requesting reload */ +#define WDT_REQSTATUS_RR2_EnabledAndUnrequested (0x1UL) /*!< RR[2] register is enabled, and are not yet requesting reload */ /* Bit 1 : Request status for RR[1] register */ #define WDT_REQSTATUS_RR1_Pos (1UL) /*!< Position of RR1 field. */ #define WDT_REQSTATUS_RR1_Msk (0x1UL << WDT_REQSTATUS_RR1_Pos) /*!< Bit mask of RR1 field. */ -#define WDT_REQSTATUS_RR1_DisabledOrRequested (0UL) /*!< RR[1] register is not enabled, or are already requesting reload */ -#define WDT_REQSTATUS_RR1_EnabledAndUnrequested (1UL) /*!< RR[1] register is enabled, and are not yet requesting reload */ +#define WDT_REQSTATUS_RR1_DisabledOrRequested (0x0UL) /*!< RR[1] register is not enabled, or are already requesting reload */ +#define WDT_REQSTATUS_RR1_EnabledAndUnrequested (0x1UL) /*!< RR[1] register is enabled, and are not yet requesting reload */ /* Bit 0 : Request status for RR[0] register */ #define WDT_REQSTATUS_RR0_Pos (0UL) /*!< Position of RR0 field. */ #define WDT_REQSTATUS_RR0_Msk (0x1UL << WDT_REQSTATUS_RR0_Pos) /*!< Bit mask of RR0 field. */ -#define WDT_REQSTATUS_RR0_DisabledOrRequested (0UL) /*!< RR[0] register is not enabled, or are already requesting reload */ -#define WDT_REQSTATUS_RR0_EnabledAndUnrequested (1UL) /*!< RR[0] register is enabled, and are not yet requesting reload */ +#define WDT_REQSTATUS_RR0_DisabledOrRequested (0x0UL) /*!< RR[0] register is not enabled, or are already requesting reload */ +#define WDT_REQSTATUS_RR0_EnabledAndUnrequested (0x1UL) /*!< RR[0] register is enabled, and are not yet requesting reload */ /* Register: WDT_CRV */ /* Description: Counter reload value */ @@ -11122,50 +11122,50 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 7 : Enable or disable RR[7] register */ #define WDT_RREN_RR7_Pos (7UL) /*!< Position of RR7 field. */ #define WDT_RREN_RR7_Msk (0x1UL << WDT_RREN_RR7_Pos) /*!< Bit mask of RR7 field. */ -#define WDT_RREN_RR7_Disabled (0UL) /*!< Disable RR[7] register */ -#define WDT_RREN_RR7_Enabled (1UL) /*!< Enable RR[7] register */ +#define WDT_RREN_RR7_Disabled (0x0UL) /*!< Disable RR[7] register */ +#define WDT_RREN_RR7_Enabled (0x1UL) /*!< Enable RR[7] register */ /* Bit 6 : Enable or disable RR[6] register */ #define WDT_RREN_RR6_Pos (6UL) /*!< Position of RR6 field. */ #define WDT_RREN_RR6_Msk (0x1UL << WDT_RREN_RR6_Pos) /*!< Bit mask of RR6 field. */ -#define WDT_RREN_RR6_Disabled (0UL) /*!< Disable RR[6] register */ -#define WDT_RREN_RR6_Enabled (1UL) /*!< Enable RR[6] register */ +#define WDT_RREN_RR6_Disabled (0x0UL) /*!< Disable RR[6] register */ +#define WDT_RREN_RR6_Enabled (0x1UL) /*!< Enable RR[6] register */ /* Bit 5 : Enable or disable RR[5] register */ #define WDT_RREN_RR5_Pos (5UL) /*!< Position of RR5 field. */ #define WDT_RREN_RR5_Msk (0x1UL << WDT_RREN_RR5_Pos) /*!< Bit mask of RR5 field. */ -#define WDT_RREN_RR5_Disabled (0UL) /*!< Disable RR[5] register */ -#define WDT_RREN_RR5_Enabled (1UL) /*!< Enable RR[5] register */ +#define WDT_RREN_RR5_Disabled (0x0UL) /*!< Disable RR[5] register */ +#define WDT_RREN_RR5_Enabled (0x1UL) /*!< Enable RR[5] register */ /* Bit 4 : Enable or disable RR[4] register */ #define WDT_RREN_RR4_Pos (4UL) /*!< Position of RR4 field. */ #define WDT_RREN_RR4_Msk (0x1UL << WDT_RREN_RR4_Pos) /*!< Bit mask of RR4 field. */ -#define WDT_RREN_RR4_Disabled (0UL) /*!< Disable RR[4] register */ -#define WDT_RREN_RR4_Enabled (1UL) /*!< Enable RR[4] register */ +#define WDT_RREN_RR4_Disabled (0x0UL) /*!< Disable RR[4] register */ +#define WDT_RREN_RR4_Enabled (0x1UL) /*!< Enable RR[4] register */ /* Bit 3 : Enable or disable RR[3] register */ #define WDT_RREN_RR3_Pos (3UL) /*!< Position of RR3 field. */ #define WDT_RREN_RR3_Msk (0x1UL << WDT_RREN_RR3_Pos) /*!< Bit mask of RR3 field. */ -#define WDT_RREN_RR3_Disabled (0UL) /*!< Disable RR[3] register */ -#define WDT_RREN_RR3_Enabled (1UL) /*!< Enable RR[3] register */ +#define WDT_RREN_RR3_Disabled (0x0UL) /*!< Disable RR[3] register */ +#define WDT_RREN_RR3_Enabled (0x1UL) /*!< Enable RR[3] register */ /* Bit 2 : Enable or disable RR[2] register */ #define WDT_RREN_RR2_Pos (2UL) /*!< Position of RR2 field. */ #define WDT_RREN_RR2_Msk (0x1UL << WDT_RREN_RR2_Pos) /*!< Bit mask of RR2 field. */ -#define WDT_RREN_RR2_Disabled (0UL) /*!< Disable RR[2] register */ -#define WDT_RREN_RR2_Enabled (1UL) /*!< Enable RR[2] register */ +#define WDT_RREN_RR2_Disabled (0x0UL) /*!< Disable RR[2] register */ +#define WDT_RREN_RR2_Enabled (0x1UL) /*!< Enable RR[2] register */ /* Bit 1 : Enable or disable RR[1] register */ #define WDT_RREN_RR1_Pos (1UL) /*!< Position of RR1 field. */ #define WDT_RREN_RR1_Msk (0x1UL << WDT_RREN_RR1_Pos) /*!< Bit mask of RR1 field. */ -#define WDT_RREN_RR1_Disabled (0UL) /*!< Disable RR[1] register */ -#define WDT_RREN_RR1_Enabled (1UL) /*!< Enable RR[1] register */ +#define WDT_RREN_RR1_Disabled (0x0UL) /*!< Disable RR[1] register */ +#define WDT_RREN_RR1_Enabled (0x1UL) /*!< Enable RR[1] register */ /* Bit 0 : Enable or disable RR[0] register */ #define WDT_RREN_RR0_Pos (0UL) /*!< Position of RR0 field. */ #define WDT_RREN_RR0_Msk (0x1UL << WDT_RREN_RR0_Pos) /*!< Bit mask of RR0 field. */ -#define WDT_RREN_RR0_Disabled (0UL) /*!< Disable RR[0] register */ -#define WDT_RREN_RR0_Enabled (1UL) /*!< Enable RR[0] register */ +#define WDT_RREN_RR0_Disabled (0x0UL) /*!< Disable RR[0] register */ +#define WDT_RREN_RR0_Enabled (0x1UL) /*!< Enable RR[0] register */ /* Register: WDT_CONFIG */ /* Description: Configuration register */ @@ -11173,14 +11173,14 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 3 : Configure the watchdog to either be paused, or kept running, while the CPU is halted by the debugger */ #define WDT_CONFIG_HALT_Pos (3UL) /*!< Position of HALT field. */ #define WDT_CONFIG_HALT_Msk (0x1UL << WDT_CONFIG_HALT_Pos) /*!< Bit mask of HALT field. */ -#define WDT_CONFIG_HALT_Pause (0UL) /*!< Pause watchdog while the CPU is halted by the debugger */ -#define WDT_CONFIG_HALT_Run (1UL) /*!< Keep the watchdog running while the CPU is halted by the debugger */ +#define WDT_CONFIG_HALT_Pause (0x0UL) /*!< Pause watchdog while the CPU is halted by the debugger */ +#define WDT_CONFIG_HALT_Run (0x1UL) /*!< Keep the watchdog running while the CPU is halted by the debugger */ /* Bit 0 : Configure the watchdog to either be paused, or kept running, while the CPU is sleeping */ #define WDT_CONFIG_SLEEP_Pos (0UL) /*!< Position of SLEEP field. */ #define WDT_CONFIG_SLEEP_Msk (0x1UL << WDT_CONFIG_SLEEP_Pos) /*!< Bit mask of SLEEP field. */ -#define WDT_CONFIG_SLEEP_Pause (0UL) /*!< Pause watchdog while the CPU is sleeping */ -#define WDT_CONFIG_SLEEP_Run (1UL) /*!< Keep the watchdog running while the CPU is sleeping */ +#define WDT_CONFIG_SLEEP_Pause (0x0UL) /*!< Pause watchdog while the CPU is sleeping */ +#define WDT_CONFIG_SLEEP_Run (0x1UL) /*!< Keep the watchdog running while the CPU is sleeping */ /* Register: WDT_RR */ /* Description: Description collection: Reload request n */ diff --git a/mdk/nrf9160.h b/mdk/nrf9160.h index 0670ad895..82c4936b1 100644 --- a/mdk/nrf9160.h +++ b/mdk/nrf9160.h @@ -32,10 +32,10 @@ POSSIBILITY OF SUCH DAMAGE. * @file nrf9160.h * @brief CMSIS HeaderFile * @version 1 - * @date 04. April 2023 - * @note Generated by SVDConv V3.3.35 on Tuesday, 04.04.2023 11:58:56 + * @date 22. June 2023 + * @note Generated by SVDConv V3.3.35 on Thursday, 22.06.2023 08:53:38 * from File 'nrf9160.svd', - * last modified on Tuesday, 04.04.2023 09:57:14 + * last modified on Thursday, 22.06.2023 06:51:54 */ diff --git a/mdk/nrf_common.ld b/mdk/nrf_common.ld index ce03fa479..65b620e19 100644 --- a/mdk/nrf_common.ld +++ b/mdk/nrf_common.ld @@ -75,8 +75,8 @@ SECTIONS /* Set the location counter to start of FLASH */ . = ALIGN(ORIGIN(FLASH), 4); - __vectors_start = .; - .vectors : { + .vectors . : { + __vectors_start = .; /* Vector table */ KEEP(*(.isr_vector)) KEEP(*(.vectors)) @@ -88,8 +88,7 @@ SECTIONS /* .ctors section (global constructor function pointers) */ . = ALIGN(4); - .ctors : - { + .ctors . : { __ctors_start = .; __CTOR_LIST__ = .; KEEP (*crtbegin*.o(.ctors)) @@ -105,8 +104,7 @@ SECTIONS /* .detors section (global destructor function pointers) */ . = ALIGN(4); - .dtors : - { + .dtors . : { __dtors_start = .; __DTOR_LIST__ = .; KEEP (*crtbegin*.o(.dtors)) @@ -122,7 +120,7 @@ SECTIONS /* .rodata section */ . = ALIGN(4); - .rodata : { + .rodata . : { . = ALIGN(4); __rodata_start = .; *(.rodata*) @@ -134,9 +132,8 @@ SECTIONS . = ALIGN(4); - __text_start = .; - .text : - { + .text . : { + __text_start = .; /* Reset handler for C startup file */ KEEP(*(.startup)) *(.startup*) @@ -194,9 +191,8 @@ SECTIONS __text_end = __text_start + __text_size; ASSERT(__text_start == __text_end || (__text_end - ORIGIN(FLASH)) <= LENGTH(FLASH) , "error: .text is too large to fit in FLASH memory segment") - .copy.table : - { - . = ALIGN(4); + . = ALIGN(4); + .copy.table . : { __copy_table_start__ = .; LONG (__data_load_start) @@ -220,9 +216,8 @@ SECTIONS __copy_table_end__ = .; } > FLASH - .zero.table : - { - . = ALIGN(4); + . = ALIGN(4); + .zero.table . : { __zero_table_start__ = .; LONG (__bss_start) @@ -271,7 +266,7 @@ SECTIONS /* .sdata section */ . = ALIGN(4); __sdata_load_start = ALIGN(__data_load_end, 4); - .sdata : AT(__sdata_load_start){ + .sdata . : AT(__sdata_load_start){ . = ALIGN(4); __sdata_start = .; *(.sdata .sdata.* .gnu.linkonce.s.*) @@ -287,7 +282,7 @@ SECTIONS /* .tdata section */ . = ALIGN(4); __tdata_load_start = ALIGN(__sdata_load_end, 4); - .tdata : AT(__tdata_load_start){ + .tdata . : AT(__tdata_load_start){ . = ALIGN(4); __tdata_start = .; *(.tdata .tdata.* .gnu.linkonce.td.*) @@ -300,10 +295,10 @@ SECTIONS ASSERT(__tdata_start == __tdata_end || (__tdata_end - ORIGIN(RAM)) <= LENGTH(RAM) , "error: .tdata is too large to fit in RAM memory segment") - /* .fast section */ + /* .fast section */ . = ALIGN(4); __fast_load_start = ALIGN(__tdata_load_end, 4); - .fast : AT(__fast_load_start){ + .fast . : AT(__fast_load_start){ . = ALIGN(4); __fast_start = .; *(.fast .fast.*) @@ -324,9 +319,8 @@ SECTIONS /* No-init section. */ . = ALIGN(4); - __noinit_start = .; PROVIDE(__noinit_start__ = .); - .noinit (NOLOAD): - { + .noinit . (NOLOAD): { + __noinit_start = .; PROVIDE(__noinit_start__ = .); *(.noinit .noinit.*) *(.no_init .no_init.*) *(.noninit .noninit.*) @@ -341,9 +335,8 @@ SECTIONS /* .bss section */ . = ALIGN(4); - __bss_start = .; PROVIDE(__bss_start__ = .); - .bss (NOLOAD): - { + .bss . (NOLOAD): { + __bss_start = .; PROVIDE(__bss_start__ = .); *(.bss* .gnu.linkonce.b.*) *(.dynbss) *(COMMON) @@ -357,9 +350,9 @@ SECTIONS /* .sbss section */ . = ALIGN(4); - __sbss_start = .; - .sbss (NOLOAD): - { + .sbss . (NOLOAD): { + __sbss_start = .; + __sbss_start__ = __sbss_start; *(.sbss .sbss.* .gnu.linkonce.sb.*) *(.sbss2 .sbss2.* .gnu.linkonce.sb2.*) *(.dynsbss) @@ -367,14 +360,15 @@ SECTIONS } > RAM __sbss_size = SIZEOF(.sbss); __sbss_end = __sbss_start + __sbss_size; + __sbss_end__ = __sbss_end; ASSERT(__sbss_start == __sbss_end || (__sbss_end - ORIGIN(RAM)) <= LENGTH(RAM) , "error: .sbss is too large to fit in RAM memory segment") /* .tbss section */ . = ALIGN(4); - __tbss_start = .; - .tbss (NOLOAD): - { + .tbss . (NOLOAD): { + __tbss_start = .; + __tbss_start__ = __tbss_start; . = ALIGN(4); *(.tbss .tbss.* .gnu.linkonce.tb.*) *(.tcommon) @@ -383,15 +377,15 @@ SECTIONS } > RAM __tbss_size = SIZEOF(.tbss); __tbss_end = __tbss_start + __tbss_size; + __tbss_end__ = __tbss_end; ASSERT(__tbss_start == __tbss_end || (__tbss_end - ORIGIN(RAM)) <= LENGTH(RAM) , "error: .tbss is too large to fit in RAM memory segment") . = ALIGN(4); . = SEGMENT_START("ldata-segment", .); . = ALIGN(4); - __heap_start = .; - .heap (COPY): - { + .heap . (COPY): { + __heap_start = .; __HeapBase = .; __heap_base = .; __end = .; @@ -407,8 +401,7 @@ SECTIONS /* .stack_dummy section doesn't contains any symbols. It is only * used for linker to calculate size of stack sections, and assign * values to stack symbols later */ - .stack_dummy (COPY): - { + .stack_dummy (COPY): { KEEP(*(.stack*)) } > RAM diff --git a/templates/nrfx_config_nrf51.h b/templates/nrfx_config_nrf51.h index 2a4c217b7..9060d2b1a 100644 --- a/templates/nrfx_config_nrf51.h +++ b/templates/nrfx_config_nrf51.h @@ -307,6 +307,57 @@ #define NRFX_PPI_CONFIG_LOG_LEVEL 3 #endif +/** + * @brief NRFX_PRS_ENABLED + * + * Boolean. Accepted values 0 and 1. + */ +#ifndef NRFX_PRS_ENABLED +#define NRFX_PRS_ENABLED 0 +#endif + +/** + * @brief NRFX_PRS_CONFIG_LOG_ENABLED + * + * Boolean. Accepted values 0 and 1. + */ +#ifndef NRFX_PRS_CONFIG_LOG_ENABLED +#define NRFX_PRS_CONFIG_LOG_ENABLED 0 +#endif + +/** + * @brief NRFX_PRS_CONFIG_LOG_LEVEL + * + * Integer value. + * Supported values: + * - Off = 0 + * - Error = 1 + * - Warning = 2 + * - Info = 3 + * - Debug = 4 + */ +#ifndef NRFX_PRS_CONFIG_LOG_LEVEL +#define NRFX_PRS_CONFIG_LOG_LEVEL 3 +#endif + +/** + * @brief NRFX_PRS_BOX_0_ENABLED + * + * Boolean. Accepted values 0 and 1. + */ +#ifndef NRFX_PRS_BOX_0_ENABLED +#define NRFX_PRS_BOX_0_ENABLED 0 +#endif + +/** + * @brief NRFX_PRS_BOX_1_ENABLED + * + * Boolean. Accepted values 0 and 1. + */ +#ifndef NRFX_PRS_BOX_1_ENABLED +#define NRFX_PRS_BOX_1_ENABLED 0 +#endif + /** * @brief NRFX_QDEC_ENABLED * diff --git a/templates/nrfx_config_nrf52805.h b/templates/nrfx_config_nrf52805.h index ac01a493b..81efe57e0 100644 --- a/templates/nrfx_config_nrf52805.h +++ b/templates/nrfx_config_nrf52805.h @@ -62,9 +62,9 @@ * * Integer value. * Supported values: - * - RC = 0 - * - XTAL = 1 - * - Synth = 2 + * - RC = 0 + * - XTAL = 1 + * - Synth = 2 * - External Low Swing = 131073 * - External Full Swing = 196609 */ diff --git a/templates/nrfx_config_nrf52810.h b/templates/nrfx_config_nrf52810.h index 1d3342f04..05064a4eb 100644 --- a/templates/nrfx_config_nrf52810.h +++ b/templates/nrfx_config_nrf52810.h @@ -62,9 +62,9 @@ * * Integer value. * Supported values: - * - RC = 0 - * - XTAL = 1 - * - Synth = 2 + * - RC = 0 + * - XTAL = 1 + * - Synth = 2 * - External Low Swing = 131073 * - External Full Swing = 196609 */ diff --git a/templates/nrfx_config_nrf52811.h b/templates/nrfx_config_nrf52811.h index bf2c147b3..4f17097f1 100644 --- a/templates/nrfx_config_nrf52811.h +++ b/templates/nrfx_config_nrf52811.h @@ -62,9 +62,9 @@ * * Integer value. * Supported values: - * - RC = 0 - * - XTAL = 1 - * - Synth = 2 + * - RC = 0 + * - XTAL = 1 + * - Synth = 2 * - External Low Swing = 131073 * - External Full Swing = 196609 */ diff --git a/templates/nrfx_config_nrf52820.h b/templates/nrfx_config_nrf52820.h index 8aab21c33..f39de0661 100644 --- a/templates/nrfx_config_nrf52820.h +++ b/templates/nrfx_config_nrf52820.h @@ -62,9 +62,9 @@ * * Integer value. * Supported values: - * - RC = 0 - * - XTAL = 1 - * - Synth = 2 + * - RC = 0 + * - XTAL = 1 + * - Synth = 2 * - External Low Swing = 131073 * - External Full Swing = 196609 */ diff --git a/templates/nrfx_config_nrf52832.h b/templates/nrfx_config_nrf52832.h index f9fb9eed9..aa968b7cc 100644 --- a/templates/nrfx_config_nrf52832.h +++ b/templates/nrfx_config_nrf52832.h @@ -62,9 +62,9 @@ * * Integer value. * Supported values: - * - RC = 0 - * - XTAL = 1 - * - Synth = 2 + * - RC = 0 + * - XTAL = 1 + * - Synth = 2 * - External Low Swing = 131073 * - External Full Swing = 196609 */ @@ -651,14 +651,7 @@ /** * @brief NRFX_PWM_NRF52_ANOMALY_109_EGU_INSTANCE - EGU instance used by the nRF52 Anomaly 109 workaround for PWM. * - * Integer value. - * Supported values: - * - EGU0 = 0 - * - EGU1 = 1 - * - EGU2 = 2 - * - EGU3 = 3 - * - EGU4 = 4 - * - EGU5 = 5 + * Integer value. Minimum: 0 Maximum: 5 */ #ifndef NRFX_PWM_NRF52_ANOMALY_109_EGU_INSTANCE #define NRFX_PWM_NRF52_ANOMALY_109_EGU_INSTANCE 5 diff --git a/templates/nrfx_config_nrf52833.h b/templates/nrfx_config_nrf52833.h index 83c5d7b3e..8d75ae37f 100644 --- a/templates/nrfx_config_nrf52833.h +++ b/templates/nrfx_config_nrf52833.h @@ -62,9 +62,9 @@ * * Integer value. * Supported values: - * - RC = 0 - * - XTAL = 1 - * - Synth = 2 + * - RC = 0 + * - XTAL = 1 + * - Synth = 2 * - External Low Swing = 131073 * - External Full Swing = 196609 */ diff --git a/templates/nrfx_config_nrf52840.h b/templates/nrfx_config_nrf52840.h index 09c06af53..08daa7797 100644 --- a/templates/nrfx_config_nrf52840.h +++ b/templates/nrfx_config_nrf52840.h @@ -62,9 +62,9 @@ * * Integer value. * Supported values: - * - RC = 0 - * - XTAL = 1 - * - Synth = 2 + * - RC = 0 + * - XTAL = 1 + * - Synth = 2 * - External Low Swing = 131073 * - External Full Swing = 196609 */ diff --git a/templates/nrfx_config_nrf91.h b/templates/nrfx_config_nrf91.h index 2a2182910..e2a8a8cca 100644 --- a/templates/nrfx_config_nrf91.h +++ b/templates/nrfx_config_nrf91.h @@ -146,8 +146,8 @@ * * Integer value. * Supported values: - * - RC = 1 - * - XTAL = 2 + * - RC = 1 + * - XTAL = 2 */ #ifndef NRFX_CLOCK_CONFIG_LF_SRC #define NRFX_CLOCK_CONFIG_LF_SRC 2 @@ -315,7 +315,7 @@ * Integer value. Minimum: 0 Maximum: 7 */ #ifndef NRFX_GPIOTE_DEFAULT_CONFIG_IRQ_PRIORITY -#define NRFX_GPIOTE_DEFAULT_CONFIG_IRQ_PRIORITY 3 +#define NRFX_GPIOTE_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY #endif /**