From 7eca6c2dc02b24cbdaa3ba0e63a7195e34ebe07c Mon Sep 17 00:00:00 2001 From: Nikodem Kastelik Date: Wed, 5 May 2021 17:12:56 +0200 Subject: [PATCH] nrfx 2.5.0 release --- .gitignore | 2 + CHANGELOG.md | 26 + LICENSE | 4 +- README.md | 4 +- doc/README.md | 44 ++ doc/drv_supp_matrix.dox | 1 - doc/generate_html_doc.bat | 2 +- doc/generate_html_doc.sh | 2 +- doc/generate_sphinx_doc.bat | 3 + doc/generate_sphinx_doc.sh | 3 + doc/main_page.dox | 7 +- doc/nrf5340.dox | 2 - doc/nrfx.doxyfile | 9 +- doc/nrfx_api.dox | 2 - doc/sphinx/_static/css/nrfx.css | 3 + doc/sphinx/api_reference.rst | 7 + doc/sphinx/changelog.rst | 1 + doc/sphinx/conf.py | 51 ++ doc/sphinx/drivers/aar/hal.rst | 6 + doc/sphinx/drivers/aar/index.rst | 9 + doc/sphinx/drivers/acl/hal.rst | 6 + doc/sphinx/drivers/acl/index.rst | 9 + doc/sphinx/drivers/adc/driver.rst | 6 + doc/sphinx/drivers/adc/hal.rst | 6 + doc/sphinx/drivers/adc/index.rst | 9 + doc/sphinx/drivers/bprot/hal.rst | 6 + doc/sphinx/drivers/bprot/index.rst | 9 + doc/sphinx/drivers/cache/hal.rst | 6 + doc/sphinx/drivers/cache/index.rst | 9 + doc/sphinx/drivers/ccm/hal.rst | 6 + doc/sphinx/drivers/ccm/index.rst | 9 + doc/sphinx/drivers/clock/driver.rst | 6 + doc/sphinx/drivers/clock/hal.rst | 6 + doc/sphinx/drivers/clock/index.rst | 10 + doc/sphinx/drivers/comp/driver.rst | 6 + doc/sphinx/drivers/comp/hal.rst | 6 + doc/sphinx/drivers/comp/index.rst | 9 + doc/sphinx/drivers/dcnf/hal.rst | 6 + doc/sphinx/drivers/dcnf/index.rst | 9 + doc/sphinx/drivers/dppi/driver.rst | 6 + doc/sphinx/drivers/dppi/hal.rst | 6 + doc/sphinx/drivers/dppi/index.rst | 10 + doc/sphinx/drivers/ecb/hal.rst | 6 + doc/sphinx/drivers/ecb/index.rst | 9 + doc/sphinx/drivers/egu/driver.rst | 6 + doc/sphinx/drivers/egu/hal.rst | 6 + doc/sphinx/drivers/egu/index.rst | 9 + doc/sphinx/drivers/ficr/hal.rst | 6 + doc/sphinx/drivers/ficr/index.rst | 9 + doc/sphinx/drivers/fpu/hal.rst | 6 + doc/sphinx/drivers/fpu/index.rst | 9 + doc/sphinx/drivers/gpio/hal.rst | 6 + doc/sphinx/drivers/gpio/index.rst | 9 + doc/sphinx/drivers/gpiote/driver.rst | 6 + doc/sphinx/drivers/gpiote/hal.rst | 6 + doc/sphinx/drivers/gpiote/index.rst | 9 + doc/sphinx/drivers/i2s/driver.rst | 6 + doc/sphinx/drivers/i2s/hal.rst | 6 + doc/sphinx/drivers/i2s/index.rst | 9 + doc/sphinx/drivers/index.rst | 7 + doc/sphinx/drivers/ipc/driver.rst | 6 + doc/sphinx/drivers/ipc/hal.rst | 6 + doc/sphinx/drivers/ipc/index.rst | 9 + doc/sphinx/drivers/kmu/hal.rst | 6 + doc/sphinx/drivers/kmu/index.rst | 9 + doc/sphinx/drivers/lpcomp/driver.rst | 6 + doc/sphinx/drivers/lpcomp/hal.rst | 6 + doc/sphinx/drivers/lpcomp/index.rst | 9 + doc/sphinx/drivers/mpu/hal.rst | 6 + doc/sphinx/drivers/mpu/index.rst | 9 + doc/sphinx/drivers/mutex/hal.rst | 6 + doc/sphinx/drivers/mutex/index.rst | 9 + doc/sphinx/drivers/mwu/hal.rst | 6 + doc/sphinx/drivers/mwu/index.rst | 9 + doc/sphinx/drivers/nfct/driver.rst | 6 + doc/sphinx/drivers/nfct/hal.rst | 6 + doc/sphinx/drivers/nfct/index.rst | 9 + doc/sphinx/drivers/nvmc/driver.rst | 6 + doc/sphinx/drivers/nvmc/hal.rst | 6 + doc/sphinx/drivers/nvmc/index.rst | 9 + doc/sphinx/drivers/oscillators/hal.rst | 6 + doc/sphinx/drivers/pdm/driver.rst | 6 + doc/sphinx/drivers/pdm/hal.rst | 6 + doc/sphinx/drivers/pdm/index.rst | 9 + doc/sphinx/drivers/power/driver.rst | 6 + doc/sphinx/drivers/power/hal.rst | 6 + doc/sphinx/drivers/power/index.rst | 15 + doc/sphinx/drivers/ppi/driver.rst | 6 + doc/sphinx/drivers/ppi/hal.rst | 6 + doc/sphinx/drivers/ppi/index.rst | 10 + doc/sphinx/drivers/pwm/driver.rst | 6 + doc/sphinx/drivers/pwm/hal.rst | 6 + doc/sphinx/drivers/pwm/index.rst | 9 + doc/sphinx/drivers/qdec/driver.rst | 6 + doc/sphinx/drivers/qdec/hal.rst | 6 + doc/sphinx/drivers/qdec/index.rst | 9 + doc/sphinx/drivers/qspi/driver.rst | 6 + doc/sphinx/drivers/qspi/hal.rst | 6 + doc/sphinx/drivers/qspi/index.rst | 9 + doc/sphinx/drivers/radio/hal.rst | 6 + doc/sphinx/drivers/radio/index.rst | 9 + doc/sphinx/drivers/regulators/hal.rst | 6 + doc/sphinx/drivers/reset/hal.rst | 6 + doc/sphinx/drivers/rng/driver.rst | 6 + doc/sphinx/drivers/rng/hal.rst | 6 + doc/sphinx/drivers/rng/index.rst | 9 + doc/sphinx/drivers/rtc/driver.rst | 6 + doc/sphinx/drivers/rtc/hal.rst | 6 + doc/sphinx/drivers/rtc/index.rst | 9 + doc/sphinx/drivers/saadc/driver.rst | 6 + doc/sphinx/drivers/saadc/hal.rst | 6 + doc/sphinx/drivers/saadc/index.rst | 9 + doc/sphinx/drivers/spi/driver.rst | 6 + doc/sphinx/drivers/spi/hal.rst | 6 + doc/sphinx/drivers/spi/index.rst | 9 + doc/sphinx/drivers/spim/driver.rst | 6 + doc/sphinx/drivers/spim/hal.rst | 6 + doc/sphinx/drivers/spim/index.rst | 9 + doc/sphinx/drivers/spis/driver.rst | 6 + doc/sphinx/drivers/spis/hal.rst | 6 + doc/sphinx/drivers/spis/index.rst | 9 + doc/sphinx/drivers/spu/hal.rst | 6 + doc/sphinx/drivers/spu/index.rst | 9 + doc/sphinx/drivers/systick/driver.rst | 6 + doc/sphinx/drivers/systick/hal.rst | 6 + doc/sphinx/drivers/systick/index.rst | 9 + doc/sphinx/drivers/temp/driver.rst | 6 + doc/sphinx/drivers/temp/hal.rst | 6 + doc/sphinx/drivers/temp/index.rst | 9 + doc/sphinx/drivers/timer/driver.rst | 6 + doc/sphinx/drivers/timer/hal.rst | 6 + doc/sphinx/drivers/timer/index.rst | 9 + doc/sphinx/drivers/twi/driver.rst | 6 + doc/sphinx/drivers/twi/hal.rst | 6 + doc/sphinx/drivers/twi/index.rst | 9 + doc/sphinx/drivers/twim/driver.rst | 6 + doc/sphinx/drivers/twim/hal.rst | 6 + doc/sphinx/drivers/twim/index.rst | 9 + doc/sphinx/drivers/twis/driver.rst | 6 + doc/sphinx/drivers/twis/hal.rst | 6 + doc/sphinx/drivers/twis/index.rst | 9 + doc/sphinx/drivers/uart/driver.rst | 6 + doc/sphinx/drivers/uart/hal.rst | 6 + doc/sphinx/drivers/uart/index.rst | 9 + doc/sphinx/drivers/uarte/driver.rst | 6 + doc/sphinx/drivers/uarte/hal.rst | 6 + doc/sphinx/drivers/uarte/index.rst | 9 + doc/sphinx/drivers/usbd/driver.rst | 6 + doc/sphinx/drivers/usbd/hal.rst | 6 + doc/sphinx/drivers/usbd/index.rst | 11 + doc/sphinx/drivers/usbreg/driver.rst | 6 + doc/sphinx/drivers/usbreg/hal.rst | 6 + doc/sphinx/drivers/vmc/hal.rst | 6 + doc/sphinx/drivers/vmc/index.rst | 9 + doc/sphinx/drivers/vreqctrl/hal.rst | 6 + doc/sphinx/drivers/wdt/driver.rst | 6 + doc/sphinx/drivers/wdt/hal.rst | 6 + doc/sphinx/drivers/wdt/index.rst | 9 + doc/sphinx/drv_supp_matrix.rst | 26 + doc/sphinx/index.rst | 14 + doc/sphinx/nrf51_series.rst | 5 + doc/sphinx/nrf52805.rst | 5 + doc/sphinx/nrf52810.rst | 5 + doc/sphinx/nrf52820.rst | 5 + doc/sphinx/nrf52832.rst | 5 + doc/sphinx/nrf52833.rst | 5 + doc/sphinx/nrf52840.rst | 5 + doc/sphinx/nrf5340.rst | 5 + doc/sphinx/nrf9160.rst | 5 + doc/sphinx/nrfx_api/atomic.rst | 6 + doc/sphinx/nrfx_api/bitmask.rst | 6 + doc/sphinx/nrfx_api/common.rst | 6 + doc/sphinx/nrfx_api/coredep.rst | 6 + doc/sphinx/nrfx_api/error_codes.rst | 6 + doc/sphinx/nrfx_api/glue.rst | 6 + doc/sphinx/nrfx_api/gppi.rst | 6 + doc/sphinx/nrfx_api/index.rst | 7 + doc/sphinx/nrfx_api/log.rst | 6 + doc/sphinx/nrfx_api/prs.rst | 6 + doc/sphinx/nrfx_api/reset_reason.rst | 6 + doc/sphinx/requirements.txt | 4 + drivers/include/nrf_bitmask.h | 4 +- drivers/include/nrfx_adc.h | 4 +- drivers/include/nrfx_clock.h | 12 +- drivers/include/nrfx_comp.h | 4 +- drivers/include/nrfx_dppi.h | 33 +- drivers/include/nrfx_egu.h | 4 +- drivers/include/nrfx_gpiote.h | 29 +- drivers/include/nrfx_i2s.h | 4 +- drivers/include/nrfx_ipc.h | 4 +- drivers/include/nrfx_lpcomp.h | 4 +- drivers/include/nrfx_nfct.h | 4 +- drivers/include/nrfx_nvmc.h | 4 +- drivers/include/nrfx_pdm.h | 4 +- drivers/include/nrfx_power.h | 4 +- drivers/include/nrfx_power_clock.h | 4 +- drivers/include/nrfx_power_compat.h | 4 +- drivers/include/nrfx_ppi.h | 32 +- drivers/include/nrfx_pwm.h | 4 +- drivers/include/nrfx_qdec.h | 4 +- drivers/include/nrfx_qspi.h | 71 +- drivers/include/nrfx_rng.h | 4 +- drivers/include/nrfx_rtc.h | 4 +- drivers/include/nrfx_saadc.h | 36 +- drivers/include/nrfx_spi.h | 4 +- drivers/include/nrfx_spim.h | 9 +- drivers/include/nrfx_spis.h | 4 +- drivers/include/nrfx_systick.h | 4 +- drivers/include/nrfx_temp.h | 4 +- drivers/include/nrfx_timer.h | 4 +- drivers/include/nrfx_twi.h | 4 +- drivers/include/nrfx_twi_twim.h | 4 +- drivers/include/nrfx_twim.h | 8 +- drivers/include/nrfx_twis.h | 4 +- drivers/include/nrfx_uart.h | 4 +- drivers/include/nrfx_uarte.h | 4 +- drivers/include/nrfx_usbd.h | 6 +- drivers/include/nrfx_usbreg.h | 4 +- drivers/include/nrfx_wdt.h | 4 +- drivers/nrfx_common.h | 4 +- drivers/nrfx_errors.h | 4 +- drivers/src/nrfx_adc.c | 4 +- drivers/src/nrfx_clock.c | 8 +- drivers/src/nrfx_comp.c | 23 +- drivers/src/nrfx_dppi.c | 82 +- drivers/src/nrfx_egu.c | 4 +- drivers/src/nrfx_gpiote.c | 15 +- drivers/src/nrfx_i2s.c | 4 +- drivers/src/nrfx_ipc.c | 4 +- drivers/src/nrfx_lpcomp.c | 4 +- drivers/src/nrfx_nfct.c | 4 +- drivers/src/nrfx_nvmc.c | 4 +- drivers/src/nrfx_pdm.c | 4 +- drivers/src/nrfx_power.c | 4 +- drivers/src/nrfx_ppi.c | 4 +- drivers/src/nrfx_pwm.c | 4 +- drivers/src/nrfx_qdec.c | 4 +- drivers/src/nrfx_qspi.c | 338 +++++++-- drivers/src/nrfx_rng.c | 4 +- drivers/src/nrfx_rtc.c | 4 +- drivers/src/nrfx_saadc.c | 82 +- drivers/src/nrfx_spi.c | 4 +- drivers/src/nrfx_spim.c | 121 ++- drivers/src/nrfx_spis.c | 4 +- drivers/src/nrfx_systick.c | 4 +- drivers/src/nrfx_temp.c | 4 +- drivers/src/nrfx_timer.c | 4 +- drivers/src/nrfx_twi.c | 4 +- drivers/src/nrfx_twi_twim.c | 4 +- drivers/src/nrfx_twim.c | 78 +- drivers/src/nrfx_twis.c | 4 +- drivers/src/nrfx_uart.c | 4 +- drivers/src/nrfx_uarte.c | 4 +- drivers/src/nrfx_usbd.c | 12 +- drivers/src/nrfx_usbd_errata.h | 4 +- drivers/src/nrfx_usbreg.c | 4 +- drivers/src/nrfx_wdt.c | 4 +- drivers/src/prs/nrfx_prs.c | 4 +- drivers/src/prs/nrfx_prs.h | 4 +- hal/nrf_aar.h | 4 +- hal/nrf_acl.h | 4 +- hal/nrf_adc.h | 4 +- hal/nrf_bprot.h | 4 +- hal/nrf_cache.h | 4 +- hal/nrf_ccm.h | 4 +- hal/nrf_clock.h | 20 +- hal/nrf_common.h | 4 +- hal/nrf_comp.h | 4 +- hal/nrf_dcnf.h | 4 +- hal/nrf_dppi.h | 16 +- hal/nrf_ecb.h | 4 +- hal/nrf_egu.h | 4 +- hal/nrf_ficr.h | 4 +- hal/nrf_fpu.h | 4 +- hal/nrf_gpio.h | 30 +- hal/nrf_gpiote.h | 4 +- hal/nrf_i2s.h | 4 +- hal/nrf_ipc.h | 4 +- hal/nrf_kmu.h | 4 +- hal/nrf_lpcomp.h | 4 +- hal/nrf_mpu.h | 4 +- hal/nrf_mutex.h | 4 +- hal/nrf_mwu.h | 4 +- hal/nrf_nfct.h | 4 +- hal/nrf_nvmc.h | 4 +- hal/nrf_oscillators.h | 6 +- hal/nrf_pdm.h | 4 +- hal/nrf_power.h | 4 +- hal/nrf_ppi.h | 4 +- hal/nrf_pwm.h | 4 +- hal/nrf_qdec.h | 25 +- hal/nrf_qspi.h | 94 ++- hal/nrf_radio.h | 7 +- hal/nrf_regulators.h | 4 +- hal/nrf_reset.h | 18 +- hal/nrf_rng.h | 4 +- hal/nrf_rtc.h | 4 +- hal/nrf_saadc.h | 4 +- hal/nrf_spi.h | 4 +- hal/nrf_spim.h | 11 +- hal/nrf_spis.h | 4 +- hal/nrf_spu.h | 4 +- hal/nrf_systick.h | 4 +- hal/nrf_temp.h | 4 +- hal/nrf_timer.h | 4 +- hal/nrf_twi.h | 4 +- hal/nrf_twim.h | 13 +- hal/nrf_twis.h | 4 +- hal/nrf_uart.h | 4 +- hal/nrf_uarte.h | 4 +- hal/nrf_usbd.h | 4 +- hal/nrf_usbreg.h | 4 +- hal/nrf_vmc.h | 4 +- hal/nrf_vreqctrl.h | 4 +- hal/nrf_wdt.h | 4 +- helpers/nrfx_gppi.h | 4 +- helpers/nrfx_reset_reason.h | 8 +- mdk/arm_startup_nrf51.s | 2 +- mdk/arm_startup_nrf52.s | 2 +- mdk/arm_startup_nrf52805.s | 2 +- mdk/arm_startup_nrf52810.s | 2 +- mdk/arm_startup_nrf52811.s | 2 +- mdk/arm_startup_nrf52820.s | 2 +- mdk/arm_startup_nrf52833.s | 2 +- mdk/arm_startup_nrf52840.s | 2 +- mdk/arm_startup_nrf5340_application.s | 26 +- mdk/arm_startup_nrf5340_network.s | 8 +- mdk/arm_startup_nrf9160.s | 2 +- mdk/compiler_abstraction.h | 26 +- mdk/gcc_startup_nrf51.S | 2 +- mdk/gcc_startup_nrf52.S | 2 +- mdk/gcc_startup_nrf52805.S | 2 +- mdk/gcc_startup_nrf52810.S | 2 +- mdk/gcc_startup_nrf52811.S | 2 +- mdk/gcc_startup_nrf52820.S | 2 +- mdk/gcc_startup_nrf52833.S | 2 +- mdk/gcc_startup_nrf52840.S | 2 +- mdk/gcc_startup_nrf5340_application.S | 18 +- mdk/gcc_startup_nrf5340_network.S | 6 +- mdk/gcc_startup_nrf9160.S | 2 +- mdk/iar_startup_nrf51.s | 2 +- mdk/iar_startup_nrf52.s | 2 +- mdk/iar_startup_nrf52805.s | 2 +- mdk/iar_startup_nrf52810.s | 2 +- mdk/iar_startup_nrf52811.s | 2 +- mdk/iar_startup_nrf52820.s | 2 +- mdk/iar_startup_nrf52833.s | 2 +- mdk/iar_startup_nrf52840.s | 2 +- mdk/iar_startup_nrf5340_application.s | 26 +- mdk/iar_startup_nrf5340_network.s | 8 +- mdk/iar_startup_nrf9160.s | 2 +- mdk/nrf.h | 10 +- mdk/nrf51.h | 10 +- mdk/nrf51.svd | 4 +- mdk/nrf51422_peripherals.h | 4 +- mdk/nrf51801_peripherals.h | 4 +- mdk/nrf51802_peripherals.h | 4 +- mdk/nrf51822_peripherals.h | 4 +- mdk/nrf51824_peripherals.h | 4 +- mdk/nrf51_bitfields.h | 4 +- mdk/nrf51_deprecated.h | 4 +- mdk/nrf51_erratas.h | 4 +- mdk/nrf51_peripherals.h | 4 +- mdk/nrf51_to_nrf52.h | 4 +- mdk/nrf51_to_nrf52810.h | 4 +- mdk/nrf51_to_nrf52840.h | 4 +- mdk/nrf52.h | 34 +- mdk/nrf52.svd | 83 +- mdk/nrf52805.h | 31 +- mdk/nrf52805.svd | 64 +- mdk/nrf52805_bitfields.h | 24 +- mdk/nrf52805_peripherals.h | 4 +- mdk/nrf52810.h | 31 +- mdk/nrf52810.svd | 64 +- mdk/nrf52810_bitfields.h | 24 +- mdk/nrf52810_name_change.h | 4 +- mdk/nrf52810_peripherals.h | 4 +- mdk/nrf52810_to_nrf52811.h | 4 +- mdk/nrf52811.h | 31 +- mdk/nrf52811.svd | 64 +- mdk/nrf52811_bitfields.h | 24 +- mdk/nrf52811_peripherals.h | 4 +- mdk/nrf52820.h | 96 ++- mdk/nrf52820.svd | 702 +++++++++-------- mdk/nrf52820_bitfields.h | 644 ++++++++-------- mdk/nrf52820_peripherals.h | 4 +- mdk/nrf52832_peripherals.h | 4 +- mdk/nrf52833.h | 104 ++- mdk/nrf52833.svd | 714 ++++++++++-------- mdk/nrf52833_bitfields.h | 658 ++++++++-------- mdk/nrf52833_peripherals.h | 4 +- mdk/nrf52833_to_nrf52820.h | 4 +- mdk/nrf52840.h | 149 ++-- mdk/nrf52840.svd | 798 +++++++++++--------- mdk/nrf52840_bitfields.h | 671 ++++++++-------- mdk/nrf52840_peripherals.h | 4 +- mdk/nrf52_bitfields.h | 35 +- mdk/nrf52_erratas.h | 733 ++++++++++++++---- mdk/nrf52_name_change.h | 4 +- mdk/nrf52_to_nrf52810.h | 4 +- mdk/nrf52_to_nrf52833.h | 4 +- mdk/nrf52_to_nrf52840.h | 4 +- mdk/nrf5340_application.h | 114 +-- mdk/nrf5340_application.svd | 683 ++++++++--------- mdk/nrf5340_application_bitfields.h | 532 +++++++------ mdk/nrf5340_application_name_change.h | 57 ++ mdk/nrf5340_application_peripherals.h | 6 +- mdk/nrf5340_network.h | 103 +-- mdk/nrf5340_network.svd | 425 +++++------ mdk/nrf5340_network_bitfields.h | 377 +++++---- mdk/nrf5340_network_name_change.h | 51 ++ mdk/nrf5340_network_peripherals.h | 4 +- mdk/nrf53_erratas.h | 144 ++-- mdk/nrf9160.h | 10 +- mdk/nrf9160.svd | 4 +- mdk/nrf9160_bitfields.h | 4 +- mdk/nrf9160_name_change.h | 4 +- mdk/nrf9160_peripherals.h | 4 +- mdk/nrf91_erratas.h | 4 +- mdk/nrf_erratas.h | 4 +- mdk/nrf_peripherals.h | 4 +- mdk/ses_startup_nrf5340_application.s | 8 +- mdk/ses_startup_nrf5340_network.s | 2 +- mdk/system_nrf.h | 2 +- mdk/system_nrf51.c | 2 +- mdk/system_nrf51.h | 2 +- mdk/system_nrf52.c | 11 +- mdk/system_nrf52.h | 2 +- mdk/system_nrf52805.c | 4 +- mdk/system_nrf52805.h | 2 +- mdk/system_nrf52810.c | 4 +- mdk/system_nrf52810.h | 2 +- mdk/system_nrf52811.c | 4 +- mdk/system_nrf52811.h | 2 +- mdk/system_nrf52820.c | 4 +- mdk/system_nrf52820.h | 2 +- mdk/system_nrf52833.c | 4 +- mdk/system_nrf52833.h | 2 +- mdk/system_nrf52840.c | 4 +- mdk/system_nrf52840.h | 2 +- mdk/system_nrf52_approtect.h | 65 ++ mdk/system_nrf5340_application.c | 6 +- mdk/system_nrf5340_application.h | 2 +- mdk/system_nrf5340_network.c | 6 +- mdk/system_nrf5340_network.h | 2 +- mdk/system_nrf53_approtect.h | 2 +- mdk/system_nrf9160.c | 2 +- mdk/system_nrf9160.h | 2 +- nrfx.h | 4 +- soc/nrfx_atomic.c | 4 +- soc/nrfx_atomic.h | 4 +- soc/nrfx_atomic_internal.h | 4 +- soc/nrfx_coredep.h | 4 +- soc/nrfx_irqs.h | 4 +- soc/nrfx_irqs_nrf51.h | 4 +- soc/nrfx_irqs_nrf52805.h | 4 +- soc/nrfx_irqs_nrf52810.h | 4 +- soc/nrfx_irqs_nrf52811.h | 4 +- soc/nrfx_irqs_nrf52820.h | 4 +- soc/nrfx_irqs_nrf52832.h | 4 +- soc/nrfx_irqs_nrf52833.h | 4 +- soc/nrfx_irqs_nrf52840.h | 4 +- soc/nrfx_irqs_nrf5340_application.h | 60 +- soc/nrfx_irqs_nrf5340_network.h | 18 +- soc/nrfx_irqs_nrf9160.h | 4 +- templates/nrfx_config.h | 4 +- templates/nrfx_config_nrf51.h | 4 +- templates/nrfx_config_nrf52805.h | 4 +- templates/nrfx_config_nrf52810.h | 4 +- templates/nrfx_config_nrf52811.h | 4 +- templates/nrfx_config_nrf52820.h | 4 +- templates/nrfx_config_nrf52832.h | 4 +- templates/nrfx_config_nrf52833.h | 4 +- templates/nrfx_config_nrf52840.h | 4 +- templates/nrfx_config_nrf5340_application.h | 4 +- templates/nrfx_config_nrf5340_network.h | 4 +- templates/nrfx_config_nrf9160.h | 4 +- templates/nrfx_glue.h | 4 +- templates/nrfx_log.h | 4 +- 479 files changed, 7871 insertions(+), 4089 deletions(-) create mode 100644 doc/README.md create mode 100644 doc/generate_sphinx_doc.bat create mode 100755 doc/generate_sphinx_doc.sh create mode 100644 doc/sphinx/_static/css/nrfx.css create mode 100644 doc/sphinx/api_reference.rst create mode 100644 doc/sphinx/changelog.rst create mode 100644 doc/sphinx/conf.py create mode 100644 doc/sphinx/drivers/aar/hal.rst create mode 100644 doc/sphinx/drivers/aar/index.rst create mode 100644 doc/sphinx/drivers/acl/hal.rst create mode 100644 doc/sphinx/drivers/acl/index.rst create mode 100644 doc/sphinx/drivers/adc/driver.rst create mode 100644 doc/sphinx/drivers/adc/hal.rst create mode 100644 doc/sphinx/drivers/adc/index.rst create mode 100644 doc/sphinx/drivers/bprot/hal.rst create mode 100644 doc/sphinx/drivers/bprot/index.rst create mode 100644 doc/sphinx/drivers/cache/hal.rst create mode 100644 doc/sphinx/drivers/cache/index.rst create mode 100644 doc/sphinx/drivers/ccm/hal.rst create mode 100644 doc/sphinx/drivers/ccm/index.rst create mode 100644 doc/sphinx/drivers/clock/driver.rst create mode 100644 doc/sphinx/drivers/clock/hal.rst create mode 100644 doc/sphinx/drivers/clock/index.rst create mode 100644 doc/sphinx/drivers/comp/driver.rst create mode 100644 doc/sphinx/drivers/comp/hal.rst create mode 100644 doc/sphinx/drivers/comp/index.rst create mode 100644 doc/sphinx/drivers/dcnf/hal.rst create mode 100644 doc/sphinx/drivers/dcnf/index.rst create mode 100644 doc/sphinx/drivers/dppi/driver.rst create mode 100644 doc/sphinx/drivers/dppi/hal.rst create mode 100644 doc/sphinx/drivers/dppi/index.rst create mode 100644 doc/sphinx/drivers/ecb/hal.rst create mode 100644 doc/sphinx/drivers/ecb/index.rst create mode 100644 doc/sphinx/drivers/egu/driver.rst create mode 100644 doc/sphinx/drivers/egu/hal.rst create mode 100644 doc/sphinx/drivers/egu/index.rst create mode 100644 doc/sphinx/drivers/ficr/hal.rst create mode 100644 doc/sphinx/drivers/ficr/index.rst create mode 100644 doc/sphinx/drivers/fpu/hal.rst create mode 100644 doc/sphinx/drivers/fpu/index.rst create mode 100644 doc/sphinx/drivers/gpio/hal.rst create mode 100644 doc/sphinx/drivers/gpio/index.rst create mode 100644 doc/sphinx/drivers/gpiote/driver.rst create mode 100644 doc/sphinx/drivers/gpiote/hal.rst create mode 100644 doc/sphinx/drivers/gpiote/index.rst create mode 100644 doc/sphinx/drivers/i2s/driver.rst create mode 100644 doc/sphinx/drivers/i2s/hal.rst create mode 100644 doc/sphinx/drivers/i2s/index.rst create mode 100644 doc/sphinx/drivers/index.rst create mode 100644 doc/sphinx/drivers/ipc/driver.rst create mode 100644 doc/sphinx/drivers/ipc/hal.rst create mode 100644 doc/sphinx/drivers/ipc/index.rst create mode 100644 doc/sphinx/drivers/kmu/hal.rst create mode 100644 doc/sphinx/drivers/kmu/index.rst create mode 100644 doc/sphinx/drivers/lpcomp/driver.rst create mode 100644 doc/sphinx/drivers/lpcomp/hal.rst create mode 100644 doc/sphinx/drivers/lpcomp/index.rst create mode 100644 doc/sphinx/drivers/mpu/hal.rst create mode 100644 doc/sphinx/drivers/mpu/index.rst create mode 100644 doc/sphinx/drivers/mutex/hal.rst create mode 100644 doc/sphinx/drivers/mutex/index.rst create mode 100644 doc/sphinx/drivers/mwu/hal.rst create mode 100644 doc/sphinx/drivers/mwu/index.rst create mode 100644 doc/sphinx/drivers/nfct/driver.rst create mode 100644 doc/sphinx/drivers/nfct/hal.rst create mode 100644 doc/sphinx/drivers/nfct/index.rst create mode 100644 doc/sphinx/drivers/nvmc/driver.rst create mode 100644 doc/sphinx/drivers/nvmc/hal.rst create mode 100644 doc/sphinx/drivers/nvmc/index.rst create mode 100644 doc/sphinx/drivers/oscillators/hal.rst create mode 100644 doc/sphinx/drivers/pdm/driver.rst create mode 100644 doc/sphinx/drivers/pdm/hal.rst create mode 100644 doc/sphinx/drivers/pdm/index.rst create mode 100644 doc/sphinx/drivers/power/driver.rst create mode 100644 doc/sphinx/drivers/power/hal.rst create mode 100644 doc/sphinx/drivers/power/index.rst create mode 100644 doc/sphinx/drivers/ppi/driver.rst create mode 100644 doc/sphinx/drivers/ppi/hal.rst create mode 100644 doc/sphinx/drivers/ppi/index.rst create mode 100644 doc/sphinx/drivers/pwm/driver.rst create mode 100644 doc/sphinx/drivers/pwm/hal.rst create mode 100644 doc/sphinx/drivers/pwm/index.rst create mode 100644 doc/sphinx/drivers/qdec/driver.rst create mode 100644 doc/sphinx/drivers/qdec/hal.rst create mode 100644 doc/sphinx/drivers/qdec/index.rst create mode 100644 doc/sphinx/drivers/qspi/driver.rst create mode 100644 doc/sphinx/drivers/qspi/hal.rst create mode 100644 doc/sphinx/drivers/qspi/index.rst create mode 100644 doc/sphinx/drivers/radio/hal.rst create mode 100644 doc/sphinx/drivers/radio/index.rst create mode 100644 doc/sphinx/drivers/regulators/hal.rst create mode 100644 doc/sphinx/drivers/reset/hal.rst create mode 100644 doc/sphinx/drivers/rng/driver.rst create mode 100644 doc/sphinx/drivers/rng/hal.rst create mode 100644 doc/sphinx/drivers/rng/index.rst create mode 100644 doc/sphinx/drivers/rtc/driver.rst create mode 100644 doc/sphinx/drivers/rtc/hal.rst create mode 100644 doc/sphinx/drivers/rtc/index.rst create mode 100644 doc/sphinx/drivers/saadc/driver.rst create mode 100644 doc/sphinx/drivers/saadc/hal.rst create mode 100644 doc/sphinx/drivers/saadc/index.rst create mode 100644 doc/sphinx/drivers/spi/driver.rst create mode 100644 doc/sphinx/drivers/spi/hal.rst create mode 100644 doc/sphinx/drivers/spi/index.rst create mode 100644 doc/sphinx/drivers/spim/driver.rst create mode 100644 doc/sphinx/drivers/spim/hal.rst create mode 100644 doc/sphinx/drivers/spim/index.rst create mode 100644 doc/sphinx/drivers/spis/driver.rst create mode 100644 doc/sphinx/drivers/spis/hal.rst create mode 100644 doc/sphinx/drivers/spis/index.rst create mode 100644 doc/sphinx/drivers/spu/hal.rst create mode 100644 doc/sphinx/drivers/spu/index.rst create mode 100644 doc/sphinx/drivers/systick/driver.rst create mode 100644 doc/sphinx/drivers/systick/hal.rst create mode 100644 doc/sphinx/drivers/systick/index.rst create mode 100644 doc/sphinx/drivers/temp/driver.rst create mode 100644 doc/sphinx/drivers/temp/hal.rst create mode 100644 doc/sphinx/drivers/temp/index.rst create mode 100644 doc/sphinx/drivers/timer/driver.rst create mode 100644 doc/sphinx/drivers/timer/hal.rst create mode 100644 doc/sphinx/drivers/timer/index.rst create mode 100644 doc/sphinx/drivers/twi/driver.rst create mode 100644 doc/sphinx/drivers/twi/hal.rst create mode 100644 doc/sphinx/drivers/twi/index.rst create mode 100644 doc/sphinx/drivers/twim/driver.rst create mode 100644 doc/sphinx/drivers/twim/hal.rst create mode 100644 doc/sphinx/drivers/twim/index.rst create mode 100644 doc/sphinx/drivers/twis/driver.rst create mode 100644 doc/sphinx/drivers/twis/hal.rst create mode 100644 doc/sphinx/drivers/twis/index.rst create mode 100644 doc/sphinx/drivers/uart/driver.rst create mode 100644 doc/sphinx/drivers/uart/hal.rst create mode 100644 doc/sphinx/drivers/uart/index.rst create mode 100644 doc/sphinx/drivers/uarte/driver.rst create mode 100644 doc/sphinx/drivers/uarte/hal.rst create mode 100644 doc/sphinx/drivers/uarte/index.rst create mode 100644 doc/sphinx/drivers/usbd/driver.rst create mode 100644 doc/sphinx/drivers/usbd/hal.rst create mode 100644 doc/sphinx/drivers/usbd/index.rst create mode 100644 doc/sphinx/drivers/usbreg/driver.rst create mode 100644 doc/sphinx/drivers/usbreg/hal.rst create mode 100644 doc/sphinx/drivers/vmc/hal.rst create mode 100644 doc/sphinx/drivers/vmc/index.rst create mode 100644 doc/sphinx/drivers/vreqctrl/hal.rst create mode 100644 doc/sphinx/drivers/wdt/driver.rst create mode 100644 doc/sphinx/drivers/wdt/hal.rst create mode 100644 doc/sphinx/drivers/wdt/index.rst create mode 100644 doc/sphinx/drv_supp_matrix.rst create mode 100644 doc/sphinx/index.rst create mode 100644 doc/sphinx/nrf51_series.rst create mode 100644 doc/sphinx/nrf52805.rst create mode 100644 doc/sphinx/nrf52810.rst create mode 100644 doc/sphinx/nrf52820.rst create mode 100644 doc/sphinx/nrf52832.rst create mode 100644 doc/sphinx/nrf52833.rst create mode 100644 doc/sphinx/nrf52840.rst create mode 100644 doc/sphinx/nrf5340.rst create mode 100644 doc/sphinx/nrf9160.rst create mode 100644 doc/sphinx/nrfx_api/atomic.rst create mode 100644 doc/sphinx/nrfx_api/bitmask.rst create mode 100644 doc/sphinx/nrfx_api/common.rst create mode 100644 doc/sphinx/nrfx_api/coredep.rst create mode 100644 doc/sphinx/nrfx_api/error_codes.rst create mode 100644 doc/sphinx/nrfx_api/glue.rst create mode 100644 doc/sphinx/nrfx_api/gppi.rst create mode 100644 doc/sphinx/nrfx_api/index.rst create mode 100644 doc/sphinx/nrfx_api/log.rst create mode 100644 doc/sphinx/nrfx_api/prs.rst create mode 100644 doc/sphinx/nrfx_api/reset_reason.rst create mode 100644 doc/sphinx/requirements.txt create mode 100644 mdk/nrf5340_application_name_change.h create mode 100644 mdk/nrf5340_network_name_change.h create mode 100644 mdk/system_nrf52_approtect.h diff --git a/.gitignore b/.gitignore index 16e737e81b..8d5c3ace3a 100644 --- a/.gitignore +++ b/.gitignore @@ -1,2 +1,4 @@ doc/html/* +doc/html_sphinx/* +doc/xml/* doc/warnings_nrfx.txt diff --git a/CHANGELOG.md b/CHANGELOG.md index 10b00d81f7..2fce3121b3 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -1,6 +1,32 @@ # Changelog All notable changes to this project are documented in this file. +## [2.5.0] - 2021-05-05 +### Added +- Added support for double-buffered transfers in the QSPI driver. +- Added support for one-by-one channel configuration in the SAADC driver. +- Added critical sections for channel allocation and deallocation in the DPPI driver. +- Added support for generating documentation in the RST format using Sphinx tool. +- Added high-drive pin configuration in the QSPI, TWIM, and SPIM drivers. +- Added report period setting of 1 sample in the QDEC HAL. +- Implemented workaround for nRF53 Series anomaly 121 in the QSPI driver. + +### Changed +- Updated MDK to version 8.40.2. +- Removed implicit channel deallocation during initialization in the GPIOTE driver. +- Restricted pins that are supported for specific configuration on nRF5340 in the QSPI, TWIM, and SPIM drivers. +- Aligned IRQ handler symbols to new naming scheme for nRF53 Series. + +### Fixed +- Fixed register access sequence in the COMP driver. +- Fixed memory corruption when uninitialized channel was freed in the GPIOTE driver. +- Fixed spurious access of DCX pin for every instance of the peripheral when extended features were enabled in the SPIM driver. +- Fixed overwrite of MCUSEL configuration in the nrf_gpio_cfg() function. +- Fixed driver behavior for zero-length transfer in the TWIM driver. +- Fixed internal state handling when transfer is aborted before finishing in the TWI and TWIM drivers. +- Corrected assertions for MPS requirements in the USBD driver. +- Corrected symbol describing maximum data payload for a full-speed isochronous endpoint in the USBD driver. + ## [2.4.0] - 2020-11-13 ### Added - Added the channel allocator feature in the GPIOTE driver. diff --git a/LICENSE b/LICENSE index 94bd0a0f4c..fef3bb0bed 100644 --- a/LICENSE +++ b/LICENSE @@ -1,6 +1,8 @@ -Copyright (c) 2017 - 2020, Nordic Semiconductor ASA +Copyright (c) 2017 - 2021, Nordic Semiconductor ASA All rights reserved. +SPDX-License-Identifier: BSD-3-Clause + Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: diff --git a/README.md b/README.md index 0772a3fac4..9e123f1362 100644 --- a/README.md +++ b/README.md @@ -42,6 +42,4 @@ SoCs, as well as startup and initialization files for them. nrfx documentation is available in the `doc\html` folder of the release package. -You can also generate documentation yourself from the source code. To do it, install doxygen -and run one of the scripts: `generate_html_doc.bat` or `generate_html_doc.sh`. Generated -documentation will be stored in the `doc\html` directory. Use `index.html` to open it. +Refer to [this guide](doc/README.md) for more details. \ No newline at end of file diff --git a/doc/README.md b/doc/README.md new file mode 100644 index 0000000000..b62aff5056 --- /dev/null +++ b/doc/README.md @@ -0,0 +1,44 @@ +# nrfx documentation + +## Doxygen + +You can generate `doxygen` based documentation by running + +```shell +doxygen nrfx.doxyfile +``` + +You may want to use the provided scripts `generate_html_doc.sh` or +`generate_html_doc.bat`. The result can be viewed by opening +`html/index.html`. + +## Sphinx + +All the necessary files to compile the Sphinx based documentation for `nrfx` +are located under `sphinx` folder. As of today the content should match with +the one produced using `doxygen` only. + +### Requirements + +You will need to have Python 3 installed as well as some dependencies, which can +be installed by running: + +```shell +pip install -r requirements.txt +``` + +### Build + +You may want to use the provided scripts `generate_sphinx_doc.sh` or +`generate_sphinx_doc.bat`. The result can be viewed by opening +`html_sphinx/index.html`. + +If you want to do it manually you can run the following commands from `doc` +directory: + +```shell +# compile doxygen documentation (required to generate XML metadata) +doxygen nrfx.doxyfile +# compile Sphinx documentation +sphinx-build -b html sphinx html_sphinx +``` \ No newline at end of file diff --git a/doc/drv_supp_matrix.dox b/doc/drv_supp_matrix.dox index ea2f1e5193..99eb621b80 100644 --- a/doc/drv_supp_matrix.dox +++ b/doc/drv_supp_matrix.dox @@ -45,7 +45,6 @@ The following matrix provides a comparative overview of which drivers are suppor | @ref nrf_qdec |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagRedCross | | @ref nrf_qspi |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagGreenTick |@tagGreenTick |@tagRedCross | | @ref nrf_radio |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagRedCross | -| @ref nrf_reset |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagGreenTick |@tagRedCross | | @ref nrf_rng |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagRedCross | | @ref nrf_rtc |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick | | @ref nrf_saadc |@tagRedCross |@tagGreenTick |@tagGreenTick |@tagRedCross |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick | diff --git a/doc/generate_html_doc.bat b/doc/generate_html_doc.bat index f63b3e794e..1a728dcd61 100644 --- a/doc/generate_html_doc.bat +++ b/doc/generate_html_doc.bat @@ -1,2 +1,2 @@ -del html\*.* /Q +del html\*.* xml\*.* /Q doxygen nrfx.doxyfile diff --git a/doc/generate_html_doc.sh b/doc/generate_html_doc.sh index 9cc608c6d2..9d65a828d2 100755 --- a/doc/generate_html_doc.sh +++ b/doc/generate_html_doc.sh @@ -1,2 +1,2 @@ -rm -rf html +rm -rf html xml doxygen nrfx.doxyfile diff --git a/doc/generate_sphinx_doc.bat b/doc/generate_sphinx_doc.bat new file mode 100644 index 0000000000..f409d7dac0 --- /dev/null +++ b/doc/generate_sphinx_doc.bat @@ -0,0 +1,3 @@ +del html\*.* xml\*.* html_sphinx\*.* /Q +doxygen nrfx.doxyfile +sphinx-build -b html sphinx html_sphinx \ No newline at end of file diff --git a/doc/generate_sphinx_doc.sh b/doc/generate_sphinx_doc.sh new file mode 100755 index 0000000000..46203db56c --- /dev/null +++ b/doc/generate_sphinx_doc.sh @@ -0,0 +1,3 @@ +rm -rf html xml html_sphinx +doxygen nrfx.doxyfile +sphinx-build -b html sphinx html_sphinx diff --git a/doc/main_page.dox b/doc/main_page.dox index 215e70952d..3bf7afd258 100644 --- a/doc/main_page.dox +++ b/doc/main_page.dox @@ -37,9 +37,10 @@ In addition, the following locations should be specified as include paths [nrfx]/mdk @endcode -@note nrfx API functions do not provide thread safety themselves. Users are responsible - for providing the proper synchronization of the nrfx function calls in a given environment - if those are to be used from different contexts. +@note Unless otherwise stated, nrfx API functions do not provide thread safety + themselves. Users are responsible for providing the proper synchronization + of the nrfx function calls in a given environment if those are to be used + from different contexts. @section nrfx_irq_handlers IRQ handlers diff --git a/doc/nrf5340.dox b/doc/nrf5340.dox index b51861d9ab..a1cbf0491e 100644 --- a/doc/nrf5340.dox +++ b/doc/nrf5340.dox @@ -60,8 +60,6 @@ For a complete overview, see @ref nrfx_drv_supp_matrix. @ref nrf_radio -@ref nrf_reset - @ref nrf_rng @ref nrf_rtc diff --git a/doc/nrfx.doxyfile b/doc/nrfx.doxyfile index bc18efe842..ba6895481b 100644 --- a/doc/nrfx.doxyfile +++ b/doc/nrfx.doxyfile @@ -40,7 +40,7 @@ PROJECT_NAME = "nrfx" ### EDIT THIS ### -PROJECT_NUMBER = "2.4" +PROJECT_NUMBER = "2.5" # Using the PROJECT_BRIEF tag one can provide an optional one line description # for a project that appears at the top of each page and should give viewer a @@ -235,8 +235,9 @@ TAB_SIZE = 4 # newlines (in the resulting output). You can put ^^ in the value part of an # alias to insert a newline as if a physical newline was in the original file. -ALIASES = tagGreenTick="@htmlonly
✔
@endhtmlonly" \ - tagRedCross="@htmlonly
✖
@endhtmlonly" +ALIASES = "tagGreenTick=\htmlonly
✔
\endhtmlonly \xmlonlyembed:rst:inline :green:`✔`\endxmlonly" \ + "tagRedCross=\htmlonly
✖
\endhtmlonly \xmlonlyembed:rst:inline :red:`✖`\endxmlonly" \ + "nRF5340pinAssignmentsURL=\"https://infocenter.nordicsemi.com/index.jsp?topic=%2Fps_nrf5340%2Fchapters%2Fpin.html\"" # This tag can be used to specify a number of word-keyword mappings (TCL only). # A mapping has the form "name=value". For example adding "class=itcl::class" @@ -1932,7 +1933,7 @@ MAN_LINKS = NO # captures the structure of the code including all documentation. # The default value is: NO. -GENERATE_XML = NO +GENERATE_XML = YES # The XML_OUTPUT tag is used to specify where the XML pages will be put. If a # relative path is entered the value of OUTPUT_DIRECTORY will be put in front of diff --git a/doc/nrfx_api.dox b/doc/nrfx_api.dox index f1496a33bc..5d88e77e68 100644 --- a/doc/nrfx_api.dox +++ b/doc/nrfx_api.dox @@ -69,8 +69,6 @@ @defgroup nrf_radio RADIO -@defgroup nrf_reset RESET - @defgroup nrf_rng RNG @defgroup nrf_rtc RTC diff --git a/doc/sphinx/_static/css/nrfx.css b/doc/sphinx/_static/css/nrfx.css new file mode 100644 index 0000000000..04d73f6fc4 --- /dev/null +++ b/doc/sphinx/_static/css/nrfx.css @@ -0,0 +1,3 @@ +:root { + --docset-color: #412ee8; +} diff --git a/doc/sphinx/api_reference.rst b/doc/sphinx/api_reference.rst new file mode 100644 index 0000000000..e4ccb6310c --- /dev/null +++ b/doc/sphinx/api_reference.rst @@ -0,0 +1,7 @@ +API Reference +============= + +.. toctree:: + + drivers/index + nrfx_api/index \ No newline at end of file diff --git a/doc/sphinx/changelog.rst b/doc/sphinx/changelog.rst new file mode 100644 index 0000000000..ab37940f47 --- /dev/null +++ b/doc/sphinx/changelog.rst @@ -0,0 +1 @@ +.. mdinclude:: ../../CHANGELOG.md diff --git a/doc/sphinx/conf.py b/doc/sphinx/conf.py new file mode 100644 index 0000000000..d89aedd414 --- /dev/null +++ b/doc/sphinx/conf.py @@ -0,0 +1,51 @@ +#!/usr/bin/env python3 + +from pathlib import Path +import re + + +CONF_DIR = Path(__file__).absolute().parent +"""conf.py directory.""" + +with open(CONF_DIR / ".." / "nrfx.doxyfile") as f: + VERSION = re.search(r'PROJECT_NUMBER\s+=\s+"(.*)"', f.read()).group(1) + +# General configuration -------------------------------------------------------- + +project = "nrfx" +copyright = "2021, Nordic Semiconductor ASA" +author = "Nordic Semiconductor" +version = VERSION + +extensions = ["breathe", "m2r2"] +source_suffix = { + ".rst": "restructuredtext", + ".md": "markdown" +} +master_doc = "index" +exclude_patterns = ["theme"] + +# Options for HTML output ------------------------------------------------------ + +html_theme = "sphinx_ncs_theme" +html_static_path = [str(CONF_DIR / "_static")] +html_last_updated_fmt = "%b %d, %Y" +html_show_sphinx = False + +# Options for Breathe ---------------------------------------------------------- + +breathe_projects = {"nrfx": str(CONF_DIR / ".." / "xml")} +breathe_default_project = "nrfx" +breathe_domain_by_extension = {"h": "c", "c": "c"} +breathe_separate_member_pages = True + +c_id_attributes = [ + "NRF_STATIC_INLINE", + "NRFX_STATIC_INLINE", + "__STATIC_INLINE", +] +cpp_id_attributes = c_id_attributes + + +def setup(app): + app.add_css_file("css/nrfx.css") diff --git a/doc/sphinx/drivers/aar/hal.rst b/doc/sphinx/drivers/aar/hal.rst new file mode 100644 index 0000000000..72ab35596f --- /dev/null +++ b/doc/sphinx/drivers/aar/hal.rst @@ -0,0 +1,6 @@ +AAR HAL +======= + +.. doxygengroup:: nrf_aar_hal + :project: nrfx + :members: diff --git a/doc/sphinx/drivers/aar/index.rst b/doc/sphinx/drivers/aar/index.rst new file mode 100644 index 0000000000..04135abf22 --- /dev/null +++ b/doc/sphinx/drivers/aar/index.rst @@ -0,0 +1,9 @@ +AAR +=== + +.. doxygengroup:: nrf_aar + +.. toctree:: + :glob: + + * \ No newline at end of file diff --git a/doc/sphinx/drivers/acl/hal.rst b/doc/sphinx/drivers/acl/hal.rst new file mode 100644 index 0000000000..9a4530c5ce --- /dev/null +++ b/doc/sphinx/drivers/acl/hal.rst @@ -0,0 +1,6 @@ +ACL HAL +======= + +.. doxygengroup:: nrf_acl_hal + :project: nrfx + :members: diff --git a/doc/sphinx/drivers/acl/index.rst b/doc/sphinx/drivers/acl/index.rst new file mode 100644 index 0000000000..c35bed2067 --- /dev/null +++ b/doc/sphinx/drivers/acl/index.rst @@ -0,0 +1,9 @@ +ACL +=== + +.. doxygengroup:: nrf_acl + +.. toctree:: + :glob: + + * \ No newline at end of file diff --git a/doc/sphinx/drivers/adc/driver.rst b/doc/sphinx/drivers/adc/driver.rst new file mode 100644 index 0000000000..f6be4e3e8a --- /dev/null +++ b/doc/sphinx/drivers/adc/driver.rst @@ -0,0 +1,6 @@ +ADC driver +========== + +.. doxygengroup:: nrfx_adc + :project: nrfx + :members: diff --git a/doc/sphinx/drivers/adc/hal.rst b/doc/sphinx/drivers/adc/hal.rst new file mode 100644 index 0000000000..5d790b141f --- /dev/null +++ b/doc/sphinx/drivers/adc/hal.rst @@ -0,0 +1,6 @@ +ADC HAL +======= + +.. doxygengroup:: nrf_adc_hal + :project: nrfx + :members: diff --git a/doc/sphinx/drivers/adc/index.rst b/doc/sphinx/drivers/adc/index.rst new file mode 100644 index 0000000000..0bdac47809 --- /dev/null +++ b/doc/sphinx/drivers/adc/index.rst @@ -0,0 +1,9 @@ +ADC +=== + +.. doxygengroup:: nrf_adc + +.. toctree:: + :glob: + + * \ No newline at end of file diff --git a/doc/sphinx/drivers/bprot/hal.rst b/doc/sphinx/drivers/bprot/hal.rst new file mode 100644 index 0000000000..6af2cb1a15 --- /dev/null +++ b/doc/sphinx/drivers/bprot/hal.rst @@ -0,0 +1,6 @@ +BPROT HAL +========= + +.. doxygengroup:: nrf_bprot_hal + :project: nrfx + :members: diff --git a/doc/sphinx/drivers/bprot/index.rst b/doc/sphinx/drivers/bprot/index.rst new file mode 100644 index 0000000000..e61df1351f --- /dev/null +++ b/doc/sphinx/drivers/bprot/index.rst @@ -0,0 +1,9 @@ +BPROT +===== + +.. doxygengroup:: nrf_bprot + +.. toctree:: + :glob: + + * \ No newline at end of file diff --git a/doc/sphinx/drivers/cache/hal.rst b/doc/sphinx/drivers/cache/hal.rst new file mode 100644 index 0000000000..09c763b2d5 --- /dev/null +++ b/doc/sphinx/drivers/cache/hal.rst @@ -0,0 +1,6 @@ +CACHE HAL +========= + +.. doxygengroup:: nrf_cache_hal + :project: nrfx + :members: diff --git a/doc/sphinx/drivers/cache/index.rst b/doc/sphinx/drivers/cache/index.rst new file mode 100644 index 0000000000..e19e177193 --- /dev/null +++ b/doc/sphinx/drivers/cache/index.rst @@ -0,0 +1,9 @@ +CACHE +===== + +.. doxygengroup:: nrf_cache + +.. toctree:: + :glob: + + * \ No newline at end of file diff --git a/doc/sphinx/drivers/ccm/hal.rst b/doc/sphinx/drivers/ccm/hal.rst new file mode 100644 index 0000000000..ab955e2d4a --- /dev/null +++ b/doc/sphinx/drivers/ccm/hal.rst @@ -0,0 +1,6 @@ +CCM HAL +======= + +.. doxygengroup:: nrf_ccm_hal + :project: nrfx + :members: diff --git a/doc/sphinx/drivers/ccm/index.rst b/doc/sphinx/drivers/ccm/index.rst new file mode 100644 index 0000000000..96b8dd5b90 --- /dev/null +++ b/doc/sphinx/drivers/ccm/index.rst @@ -0,0 +1,9 @@ +CCM +=== + +.. doxygengroup:: nrf_ccm + +.. toctree:: + :glob: + + * \ No newline at end of file diff --git a/doc/sphinx/drivers/clock/driver.rst b/doc/sphinx/drivers/clock/driver.rst new file mode 100644 index 0000000000..02736d8b02 --- /dev/null +++ b/doc/sphinx/drivers/clock/driver.rst @@ -0,0 +1,6 @@ +CLOCK driver +============ + +.. doxygengroup:: nrfx_clock + :project: nrfx + :members: diff --git a/doc/sphinx/drivers/clock/hal.rst b/doc/sphinx/drivers/clock/hal.rst new file mode 100644 index 0000000000..bfe7ca3205 --- /dev/null +++ b/doc/sphinx/drivers/clock/hal.rst @@ -0,0 +1,6 @@ +CLOCK HAL +========= + +.. doxygengroup:: nrf_clock_hal + :project: nrfx + :members: diff --git a/doc/sphinx/drivers/clock/index.rst b/doc/sphinx/drivers/clock/index.rst new file mode 100644 index 0000000000..0f96720ec3 --- /dev/null +++ b/doc/sphinx/drivers/clock/index.rst @@ -0,0 +1,10 @@ +CLOCK +===== + +.. doxygengroup:: nrf_clock + +.. toctree:: + :glob: + + * + ../oscillators/hal.rst diff --git a/doc/sphinx/drivers/comp/driver.rst b/doc/sphinx/drivers/comp/driver.rst new file mode 100644 index 0000000000..a5a2ada01d --- /dev/null +++ b/doc/sphinx/drivers/comp/driver.rst @@ -0,0 +1,6 @@ +COMP driver +=========== + +.. doxygengroup:: nrfx_comp + :project: nrfx + :members: diff --git a/doc/sphinx/drivers/comp/hal.rst b/doc/sphinx/drivers/comp/hal.rst new file mode 100644 index 0000000000..3bbd4da539 --- /dev/null +++ b/doc/sphinx/drivers/comp/hal.rst @@ -0,0 +1,6 @@ +COMP HAL +======== + +.. doxygengroup:: nrf_comp_hal + :project: nrfx + :members: diff --git a/doc/sphinx/drivers/comp/index.rst b/doc/sphinx/drivers/comp/index.rst new file mode 100644 index 0000000000..b4fb5411e8 --- /dev/null +++ b/doc/sphinx/drivers/comp/index.rst @@ -0,0 +1,9 @@ +COMP +==== + +.. doxygengroup:: nrf_comp + +.. toctree:: + :glob: + + * \ No newline at end of file diff --git a/doc/sphinx/drivers/dcnf/hal.rst b/doc/sphinx/drivers/dcnf/hal.rst new file mode 100644 index 0000000000..8498589385 --- /dev/null +++ b/doc/sphinx/drivers/dcnf/hal.rst @@ -0,0 +1,6 @@ +DCNF HAL +======== + +.. doxygengroup:: nrf_dcnf_hal + :project: nrfx + :members: diff --git a/doc/sphinx/drivers/dcnf/index.rst b/doc/sphinx/drivers/dcnf/index.rst new file mode 100644 index 0000000000..9d1bf2eda4 --- /dev/null +++ b/doc/sphinx/drivers/dcnf/index.rst @@ -0,0 +1,9 @@ +DCNF +==== + +.. doxygengroup:: nrf_dcnf + +.. toctree:: + :glob: + + * \ No newline at end of file diff --git a/doc/sphinx/drivers/dppi/driver.rst b/doc/sphinx/drivers/dppi/driver.rst new file mode 100644 index 0000000000..742afee8e3 --- /dev/null +++ b/doc/sphinx/drivers/dppi/driver.rst @@ -0,0 +1,6 @@ +DPPI driver +=========== + +.. doxygengroup:: nrfx_dppi + :project: nrfx + :members: diff --git a/doc/sphinx/drivers/dppi/hal.rst b/doc/sphinx/drivers/dppi/hal.rst new file mode 100644 index 0000000000..0122518071 --- /dev/null +++ b/doc/sphinx/drivers/dppi/hal.rst @@ -0,0 +1,6 @@ +DPPI HAL +======== + +.. doxygengroup:: nrf_dppi_hal + :project: nrfx + :members: diff --git a/doc/sphinx/drivers/dppi/index.rst b/doc/sphinx/drivers/dppi/index.rst new file mode 100644 index 0000000000..773ddbfb67 --- /dev/null +++ b/doc/sphinx/drivers/dppi/index.rst @@ -0,0 +1,10 @@ +DPPI +==== + +.. doxygengroup:: nrf_dppi + +.. toctree:: + :glob: + + ../../nrfx_api/gppi.rst + * diff --git a/doc/sphinx/drivers/ecb/hal.rst b/doc/sphinx/drivers/ecb/hal.rst new file mode 100644 index 0000000000..8d1c523f4e --- /dev/null +++ b/doc/sphinx/drivers/ecb/hal.rst @@ -0,0 +1,6 @@ +ECB HAL +======= + +.. doxygengroup:: nrf_ecb_hal + :project: nrfx + :members: diff --git a/doc/sphinx/drivers/ecb/index.rst b/doc/sphinx/drivers/ecb/index.rst new file mode 100644 index 0000000000..a7e7ebeeee --- /dev/null +++ b/doc/sphinx/drivers/ecb/index.rst @@ -0,0 +1,9 @@ +ECB +=== + +.. doxygengroup:: nrf_ecb + +.. toctree:: + :glob: + + * \ No newline at end of file diff --git a/doc/sphinx/drivers/egu/driver.rst b/doc/sphinx/drivers/egu/driver.rst new file mode 100644 index 0000000000..6abf3ac3ef --- /dev/null +++ b/doc/sphinx/drivers/egu/driver.rst @@ -0,0 +1,6 @@ +EGU driver +========== + +.. doxygengroup:: nrfx_egu + :project: nrfx + :members: diff --git a/doc/sphinx/drivers/egu/hal.rst b/doc/sphinx/drivers/egu/hal.rst new file mode 100644 index 0000000000..7f9bea7dd0 --- /dev/null +++ b/doc/sphinx/drivers/egu/hal.rst @@ -0,0 +1,6 @@ +EGU HAL +======= + +.. doxygengroup:: nrf_egu_hal + :project: nrfx + :members: diff --git a/doc/sphinx/drivers/egu/index.rst b/doc/sphinx/drivers/egu/index.rst new file mode 100644 index 0000000000..f8108a42a4 --- /dev/null +++ b/doc/sphinx/drivers/egu/index.rst @@ -0,0 +1,9 @@ +EGU +=== + +.. doxygengroup:: nrf_egu + +.. toctree:: + :glob: + + * \ No newline at end of file diff --git a/doc/sphinx/drivers/ficr/hal.rst b/doc/sphinx/drivers/ficr/hal.rst new file mode 100644 index 0000000000..dbb9ff833a --- /dev/null +++ b/doc/sphinx/drivers/ficr/hal.rst @@ -0,0 +1,6 @@ +FICR HAL +======== + +.. doxygengroup:: nrf_ficr_hal + :project: nrfx + :members: diff --git a/doc/sphinx/drivers/ficr/index.rst b/doc/sphinx/drivers/ficr/index.rst new file mode 100644 index 0000000000..dd9876a23b --- /dev/null +++ b/doc/sphinx/drivers/ficr/index.rst @@ -0,0 +1,9 @@ +FICR +==== + +.. doxygengroup:: nrf_ficr + +.. toctree:: + :glob: + + * \ No newline at end of file diff --git a/doc/sphinx/drivers/fpu/hal.rst b/doc/sphinx/drivers/fpu/hal.rst new file mode 100644 index 0000000000..4edb82d5f5 --- /dev/null +++ b/doc/sphinx/drivers/fpu/hal.rst @@ -0,0 +1,6 @@ +FPU HAL +======= + +.. doxygengroup:: nrf_fpu_hal + :project: nrfx + :members: diff --git a/doc/sphinx/drivers/fpu/index.rst b/doc/sphinx/drivers/fpu/index.rst new file mode 100644 index 0000000000..9a4ff758df --- /dev/null +++ b/doc/sphinx/drivers/fpu/index.rst @@ -0,0 +1,9 @@ +FPU +=== + +.. doxygengroup:: nrf_fpu + +.. toctree:: + :glob: + + * \ No newline at end of file diff --git a/doc/sphinx/drivers/gpio/hal.rst b/doc/sphinx/drivers/gpio/hal.rst new file mode 100644 index 0000000000..fd7e4b40da --- /dev/null +++ b/doc/sphinx/drivers/gpio/hal.rst @@ -0,0 +1,6 @@ +GPIO HAL +======== + +.. doxygengroup:: nrf_gpio_hal + :project: nrfx + :members: diff --git a/doc/sphinx/drivers/gpio/index.rst b/doc/sphinx/drivers/gpio/index.rst new file mode 100644 index 0000000000..c49d33c295 --- /dev/null +++ b/doc/sphinx/drivers/gpio/index.rst @@ -0,0 +1,9 @@ +GPIO +==== + +.. doxygengroup:: nrf_gpio + +.. toctree:: + :glob: + + * \ No newline at end of file diff --git a/doc/sphinx/drivers/gpiote/driver.rst b/doc/sphinx/drivers/gpiote/driver.rst new file mode 100644 index 0000000000..5550cbc19c --- /dev/null +++ b/doc/sphinx/drivers/gpiote/driver.rst @@ -0,0 +1,6 @@ +GPIOTE driver +============= + +.. doxygengroup:: nrfx_gpiote + :project: nrfx + :members: diff --git a/doc/sphinx/drivers/gpiote/hal.rst b/doc/sphinx/drivers/gpiote/hal.rst new file mode 100644 index 0000000000..976c36acdd --- /dev/null +++ b/doc/sphinx/drivers/gpiote/hal.rst @@ -0,0 +1,6 @@ +GPIOTE HAL +========== + +.. doxygengroup:: nrf_gpiote_hal + :project: nrfx + :members: diff --git a/doc/sphinx/drivers/gpiote/index.rst b/doc/sphinx/drivers/gpiote/index.rst new file mode 100644 index 0000000000..03217bfa74 --- /dev/null +++ b/doc/sphinx/drivers/gpiote/index.rst @@ -0,0 +1,9 @@ +GPIOTE +====== + +.. doxygengroup:: nrf_gpiote + +.. toctree:: + :glob: + + * \ No newline at end of file diff --git a/doc/sphinx/drivers/i2s/driver.rst b/doc/sphinx/drivers/i2s/driver.rst new file mode 100644 index 0000000000..98d6fef0f7 --- /dev/null +++ b/doc/sphinx/drivers/i2s/driver.rst @@ -0,0 +1,6 @@ +I2S driver +========== + +.. doxygengroup:: nrfx_i2s + :project: nrfx + :members: diff --git a/doc/sphinx/drivers/i2s/hal.rst b/doc/sphinx/drivers/i2s/hal.rst new file mode 100644 index 0000000000..fca3fd236e --- /dev/null +++ b/doc/sphinx/drivers/i2s/hal.rst @@ -0,0 +1,6 @@ +I2S HAL +======= + +.. doxygengroup:: nrf_i2s_hal + :project: nrfx + :members: diff --git a/doc/sphinx/drivers/i2s/index.rst b/doc/sphinx/drivers/i2s/index.rst new file mode 100644 index 0000000000..49823c39dd --- /dev/null +++ b/doc/sphinx/drivers/i2s/index.rst @@ -0,0 +1,9 @@ +I2S +=== + +.. doxygengroup:: nrf_i2s + +.. toctree:: + :glob: + + * \ No newline at end of file diff --git a/doc/sphinx/drivers/index.rst b/doc/sphinx/drivers/index.rst new file mode 100644 index 0000000000..1bfc63058a --- /dev/null +++ b/doc/sphinx/drivers/index.rst @@ -0,0 +1,7 @@ +Drivers +======= + +.. toctree:: + :glob: + + **/index \ No newline at end of file diff --git a/doc/sphinx/drivers/ipc/driver.rst b/doc/sphinx/drivers/ipc/driver.rst new file mode 100644 index 0000000000..0f1b25ced2 --- /dev/null +++ b/doc/sphinx/drivers/ipc/driver.rst @@ -0,0 +1,6 @@ +IPC driver +========== + +.. doxygengroup:: nrfx_ipc + :project: nrfx + :members: diff --git a/doc/sphinx/drivers/ipc/hal.rst b/doc/sphinx/drivers/ipc/hal.rst new file mode 100644 index 0000000000..67b040f85f --- /dev/null +++ b/doc/sphinx/drivers/ipc/hal.rst @@ -0,0 +1,6 @@ +IPC HAL +======= + +.. doxygengroup:: nrf_ipc_hal + :project: nrfx + :members: diff --git a/doc/sphinx/drivers/ipc/index.rst b/doc/sphinx/drivers/ipc/index.rst new file mode 100644 index 0000000000..90c08c84f5 --- /dev/null +++ b/doc/sphinx/drivers/ipc/index.rst @@ -0,0 +1,9 @@ +IPC +=== + +.. doxygengroup:: nrf_ipc + +.. toctree:: + :glob: + + * \ No newline at end of file diff --git a/doc/sphinx/drivers/kmu/hal.rst b/doc/sphinx/drivers/kmu/hal.rst new file mode 100644 index 0000000000..0af61b0ff9 --- /dev/null +++ b/doc/sphinx/drivers/kmu/hal.rst @@ -0,0 +1,6 @@ +KMU HAL +======= + +.. doxygengroup:: nrf_kmu_hal + :project: nrfx + :members: diff --git a/doc/sphinx/drivers/kmu/index.rst b/doc/sphinx/drivers/kmu/index.rst new file mode 100644 index 0000000000..ab5697a8c8 --- /dev/null +++ b/doc/sphinx/drivers/kmu/index.rst @@ -0,0 +1,9 @@ +KMU +=== + +.. doxygengroup:: nrf_kmu + +.. toctree:: + :glob: + + * \ No newline at end of file diff --git a/doc/sphinx/drivers/lpcomp/driver.rst b/doc/sphinx/drivers/lpcomp/driver.rst new file mode 100644 index 0000000000..90f3a629f6 --- /dev/null +++ b/doc/sphinx/drivers/lpcomp/driver.rst @@ -0,0 +1,6 @@ +LPCOMP driver +============= + +.. doxygengroup:: nrfx_lpcomp + :project: nrfx + :members: diff --git a/doc/sphinx/drivers/lpcomp/hal.rst b/doc/sphinx/drivers/lpcomp/hal.rst new file mode 100644 index 0000000000..606dd175d8 --- /dev/null +++ b/doc/sphinx/drivers/lpcomp/hal.rst @@ -0,0 +1,6 @@ +LPCOMP HAL +========== + +.. doxygengroup:: nrf_lpcomp_hal + :project: nrfx + :members: diff --git a/doc/sphinx/drivers/lpcomp/index.rst b/doc/sphinx/drivers/lpcomp/index.rst new file mode 100644 index 0000000000..1003b84639 --- /dev/null +++ b/doc/sphinx/drivers/lpcomp/index.rst @@ -0,0 +1,9 @@ +LPCOMP +====== + +.. doxygengroup:: nrf_lpcomp + +.. toctree:: + :glob: + + * \ No newline at end of file diff --git a/doc/sphinx/drivers/mpu/hal.rst b/doc/sphinx/drivers/mpu/hal.rst new file mode 100644 index 0000000000..8f23cbfbe4 --- /dev/null +++ b/doc/sphinx/drivers/mpu/hal.rst @@ -0,0 +1,6 @@ +MPU HAL +======= + +.. doxygengroup:: nrf_mpu_hal + :project: nrfx + :members: diff --git a/doc/sphinx/drivers/mpu/index.rst b/doc/sphinx/drivers/mpu/index.rst new file mode 100644 index 0000000000..47e5ffb0e7 --- /dev/null +++ b/doc/sphinx/drivers/mpu/index.rst @@ -0,0 +1,9 @@ +MPU +=== + +.. doxygengroup:: nrf_mpu + +.. toctree:: + :glob: + + * \ No newline at end of file diff --git a/doc/sphinx/drivers/mutex/hal.rst b/doc/sphinx/drivers/mutex/hal.rst new file mode 100644 index 0000000000..3077fef7a4 --- /dev/null +++ b/doc/sphinx/drivers/mutex/hal.rst @@ -0,0 +1,6 @@ +MUTEX HAL +========= + +.. doxygengroup:: nrf_mutex_hal + :project: nrfx + :members: diff --git a/doc/sphinx/drivers/mutex/index.rst b/doc/sphinx/drivers/mutex/index.rst new file mode 100644 index 0000000000..288004c522 --- /dev/null +++ b/doc/sphinx/drivers/mutex/index.rst @@ -0,0 +1,9 @@ +MUTEX +===== + +.. doxygengroup:: nrf_mutex + +.. toctree:: + :glob: + + * \ No newline at end of file diff --git a/doc/sphinx/drivers/mwu/hal.rst b/doc/sphinx/drivers/mwu/hal.rst new file mode 100644 index 0000000000..a3454fbc48 --- /dev/null +++ b/doc/sphinx/drivers/mwu/hal.rst @@ -0,0 +1,6 @@ +MWU HAL +======= + +.. doxygengroup:: nrf_mwu_hal + :project: nrfx + :members: diff --git a/doc/sphinx/drivers/mwu/index.rst b/doc/sphinx/drivers/mwu/index.rst new file mode 100644 index 0000000000..fea859da84 --- /dev/null +++ b/doc/sphinx/drivers/mwu/index.rst @@ -0,0 +1,9 @@ +MWU +=== + +.. doxygengroup:: nrf_mwu + +.. toctree:: + :glob: + + * \ No newline at end of file diff --git a/doc/sphinx/drivers/nfct/driver.rst b/doc/sphinx/drivers/nfct/driver.rst new file mode 100644 index 0000000000..9948fcbebe --- /dev/null +++ b/doc/sphinx/drivers/nfct/driver.rst @@ -0,0 +1,6 @@ +NFCT driver +=========== + +.. doxygengroup:: nrfx_nfct + :project: nrfx + :members: diff --git a/doc/sphinx/drivers/nfct/hal.rst b/doc/sphinx/drivers/nfct/hal.rst new file mode 100644 index 0000000000..7684f6b28c --- /dev/null +++ b/doc/sphinx/drivers/nfct/hal.rst @@ -0,0 +1,6 @@ +NFCT HAL +======== + +.. doxygengroup:: nrf_nfct_hal + :project: nrfx + :members: diff --git a/doc/sphinx/drivers/nfct/index.rst b/doc/sphinx/drivers/nfct/index.rst new file mode 100644 index 0000000000..3958600957 --- /dev/null +++ b/doc/sphinx/drivers/nfct/index.rst @@ -0,0 +1,9 @@ +NFCT +==== + +.. doxygengroup:: nrf_nfct + +.. toctree:: + :glob: + + * \ No newline at end of file diff --git a/doc/sphinx/drivers/nvmc/driver.rst b/doc/sphinx/drivers/nvmc/driver.rst new file mode 100644 index 0000000000..78e079a01b --- /dev/null +++ b/doc/sphinx/drivers/nvmc/driver.rst @@ -0,0 +1,6 @@ +NVMC driver +=========== + +.. doxygengroup:: nrfx_nvmc + :project: nrfx + :members: diff --git a/doc/sphinx/drivers/nvmc/hal.rst b/doc/sphinx/drivers/nvmc/hal.rst new file mode 100644 index 0000000000..ef49fc1184 --- /dev/null +++ b/doc/sphinx/drivers/nvmc/hal.rst @@ -0,0 +1,6 @@ +NVMC HAL +======== + +.. doxygengroup:: nrf_nvmc_hal + :project: nrfx + :members: diff --git a/doc/sphinx/drivers/nvmc/index.rst b/doc/sphinx/drivers/nvmc/index.rst new file mode 100644 index 0000000000..301a2b0da3 --- /dev/null +++ b/doc/sphinx/drivers/nvmc/index.rst @@ -0,0 +1,9 @@ +NVMC +==== + +.. doxygengroup:: nrf_nvmc + +.. toctree:: + :glob: + + * \ No newline at end of file diff --git a/doc/sphinx/drivers/oscillators/hal.rst b/doc/sphinx/drivers/oscillators/hal.rst new file mode 100644 index 0000000000..e62d5f109b --- /dev/null +++ b/doc/sphinx/drivers/oscillators/hal.rst @@ -0,0 +1,6 @@ +OSCILLATORS HAL +=============== + +.. doxygengroup:: nrf_oscillators_hal + :project: nrfx + :members: diff --git a/doc/sphinx/drivers/pdm/driver.rst b/doc/sphinx/drivers/pdm/driver.rst new file mode 100644 index 0000000000..dc7eb679ad --- /dev/null +++ b/doc/sphinx/drivers/pdm/driver.rst @@ -0,0 +1,6 @@ +PDM driver +========== + +.. doxygengroup:: nrfx_pdm + :project: nrfx + :members: diff --git a/doc/sphinx/drivers/pdm/hal.rst b/doc/sphinx/drivers/pdm/hal.rst new file mode 100644 index 0000000000..45e49f0aae --- /dev/null +++ b/doc/sphinx/drivers/pdm/hal.rst @@ -0,0 +1,6 @@ +PDM HAL +======= + +.. doxygengroup:: nrf_pdm_hal + :project: nrfx + :members: diff --git a/doc/sphinx/drivers/pdm/index.rst b/doc/sphinx/drivers/pdm/index.rst new file mode 100644 index 0000000000..c6c6afb55f --- /dev/null +++ b/doc/sphinx/drivers/pdm/index.rst @@ -0,0 +1,9 @@ +PDM +=== + +.. doxygengroup:: nrf_pdm + +.. toctree:: + :glob: + + * \ No newline at end of file diff --git a/doc/sphinx/drivers/power/driver.rst b/doc/sphinx/drivers/power/driver.rst new file mode 100644 index 0000000000..11b8a28390 --- /dev/null +++ b/doc/sphinx/drivers/power/driver.rst @@ -0,0 +1,6 @@ +POWER driver +============ + +.. doxygengroup:: nrfx_power + :project: nrfx + :members: diff --git a/doc/sphinx/drivers/power/hal.rst b/doc/sphinx/drivers/power/hal.rst new file mode 100644 index 0000000000..1d0421f2af --- /dev/null +++ b/doc/sphinx/drivers/power/hal.rst @@ -0,0 +1,6 @@ +POWER HAL +========= + +.. doxygengroup:: nrf_power_hal + :project: nrfx + :members: diff --git a/doc/sphinx/drivers/power/index.rst b/doc/sphinx/drivers/power/index.rst new file mode 100644 index 0000000000..06addf5ee9 --- /dev/null +++ b/doc/sphinx/drivers/power/index.rst @@ -0,0 +1,15 @@ +POWER +===== + +.. doxygengroup:: nrf_power + +.. toctree:: + :glob: + + ../../nrfx_api/reset_reason.rst + * + ../reset/hal.rst + ../usbreg/driver.rst + ../usbreg/hal.rst + ../regulators/hal.rst + ../vreqctrl/hal.rst diff --git a/doc/sphinx/drivers/ppi/driver.rst b/doc/sphinx/drivers/ppi/driver.rst new file mode 100644 index 0000000000..cd5bdaeeb5 --- /dev/null +++ b/doc/sphinx/drivers/ppi/driver.rst @@ -0,0 +1,6 @@ +PPI driver +========== + +.. doxygengroup:: nrfx_ppi + :project: nrfx + :members: diff --git a/doc/sphinx/drivers/ppi/hal.rst b/doc/sphinx/drivers/ppi/hal.rst new file mode 100644 index 0000000000..96ffd46d4d --- /dev/null +++ b/doc/sphinx/drivers/ppi/hal.rst @@ -0,0 +1,6 @@ +PPI HAL +======= + +.. doxygengroup:: nrf_ppi_hal + :project: nrfx + :members: diff --git a/doc/sphinx/drivers/ppi/index.rst b/doc/sphinx/drivers/ppi/index.rst new file mode 100644 index 0000000000..5a8c649807 --- /dev/null +++ b/doc/sphinx/drivers/ppi/index.rst @@ -0,0 +1,10 @@ +PPI +=== + +.. doxygengroup:: nrf_ppi + +.. toctree:: + :glob: + + ../../nrfx_api/gppi.rst + * diff --git a/doc/sphinx/drivers/pwm/driver.rst b/doc/sphinx/drivers/pwm/driver.rst new file mode 100644 index 0000000000..d914771283 --- /dev/null +++ b/doc/sphinx/drivers/pwm/driver.rst @@ -0,0 +1,6 @@ +PWM driver +========== + +.. doxygengroup:: nrfx_pwm + :project: nrfx + :members: diff --git a/doc/sphinx/drivers/pwm/hal.rst b/doc/sphinx/drivers/pwm/hal.rst new file mode 100644 index 0000000000..e0d5acfb74 --- /dev/null +++ b/doc/sphinx/drivers/pwm/hal.rst @@ -0,0 +1,6 @@ +PWM HAL +======= + +.. doxygengroup:: nrf_pwm_hal + :project: nrfx + :members: diff --git a/doc/sphinx/drivers/pwm/index.rst b/doc/sphinx/drivers/pwm/index.rst new file mode 100644 index 0000000000..f344b3ceb9 --- /dev/null +++ b/doc/sphinx/drivers/pwm/index.rst @@ -0,0 +1,9 @@ +PWM +=== + +.. doxygengroup:: nrf_pwm + +.. toctree:: + :glob: + + * \ No newline at end of file diff --git a/doc/sphinx/drivers/qdec/driver.rst b/doc/sphinx/drivers/qdec/driver.rst new file mode 100644 index 0000000000..4095df09d9 --- /dev/null +++ b/doc/sphinx/drivers/qdec/driver.rst @@ -0,0 +1,6 @@ +QDEC driver +=========== + +.. doxygengroup:: nrfx_qdec + :project: nrfx + :members: diff --git a/doc/sphinx/drivers/qdec/hal.rst b/doc/sphinx/drivers/qdec/hal.rst new file mode 100644 index 0000000000..ea8f258eb3 --- /dev/null +++ b/doc/sphinx/drivers/qdec/hal.rst @@ -0,0 +1,6 @@ +QDEC HAL +======== + +.. doxygengroup:: nrf_qdec_hal + :project: nrfx + :members: diff --git a/doc/sphinx/drivers/qdec/index.rst b/doc/sphinx/drivers/qdec/index.rst new file mode 100644 index 0000000000..e8073bfcad --- /dev/null +++ b/doc/sphinx/drivers/qdec/index.rst @@ -0,0 +1,9 @@ +QDEC +==== + +.. doxygengroup:: nrf_qdec + +.. toctree:: + :glob: + + * \ No newline at end of file diff --git a/doc/sphinx/drivers/qspi/driver.rst b/doc/sphinx/drivers/qspi/driver.rst new file mode 100644 index 0000000000..706b8ab343 --- /dev/null +++ b/doc/sphinx/drivers/qspi/driver.rst @@ -0,0 +1,6 @@ +QSPI driver +=========== + +.. doxygengroup:: nrfx_qspi + :project: nrfx + :members: diff --git a/doc/sphinx/drivers/qspi/hal.rst b/doc/sphinx/drivers/qspi/hal.rst new file mode 100644 index 0000000000..12298cfa97 --- /dev/null +++ b/doc/sphinx/drivers/qspi/hal.rst @@ -0,0 +1,6 @@ +QSPI HAL +======== + +.. doxygengroup:: nrf_qspi_hal + :project: nrfx + :members: diff --git a/doc/sphinx/drivers/qspi/index.rst b/doc/sphinx/drivers/qspi/index.rst new file mode 100644 index 0000000000..21aa0b97a7 --- /dev/null +++ b/doc/sphinx/drivers/qspi/index.rst @@ -0,0 +1,9 @@ +QSPI +==== + +.. doxygengroup:: nrf_qspi + +.. toctree:: + :glob: + + * \ No newline at end of file diff --git a/doc/sphinx/drivers/radio/hal.rst b/doc/sphinx/drivers/radio/hal.rst new file mode 100644 index 0000000000..c9b3824a2e --- /dev/null +++ b/doc/sphinx/drivers/radio/hal.rst @@ -0,0 +1,6 @@ +RADIO HAL +========= + +.. doxygengroup:: nrf_radio_hal + :project: nrfx + :members: diff --git a/doc/sphinx/drivers/radio/index.rst b/doc/sphinx/drivers/radio/index.rst new file mode 100644 index 0000000000..01759d4c2c --- /dev/null +++ b/doc/sphinx/drivers/radio/index.rst @@ -0,0 +1,9 @@ +RADIO +===== + +.. doxygengroup:: nrf_radio + +.. toctree:: + :glob: + + * \ No newline at end of file diff --git a/doc/sphinx/drivers/regulators/hal.rst b/doc/sphinx/drivers/regulators/hal.rst new file mode 100644 index 0000000000..87e73fab94 --- /dev/null +++ b/doc/sphinx/drivers/regulators/hal.rst @@ -0,0 +1,6 @@ +REGULATORS HAL +============== + +.. doxygengroup:: nrf_regulators_hal + :project: nrfx + :members: diff --git a/doc/sphinx/drivers/reset/hal.rst b/doc/sphinx/drivers/reset/hal.rst new file mode 100644 index 0000000000..072f7edb66 --- /dev/null +++ b/doc/sphinx/drivers/reset/hal.rst @@ -0,0 +1,6 @@ +RESET HAL +========= + +.. doxygengroup:: nrf_reset_hal + :project: nrfx + :members: diff --git a/doc/sphinx/drivers/rng/driver.rst b/doc/sphinx/drivers/rng/driver.rst new file mode 100644 index 0000000000..2f8ee9b0c6 --- /dev/null +++ b/doc/sphinx/drivers/rng/driver.rst @@ -0,0 +1,6 @@ +RNG driver +========== + +.. doxygengroup:: nrfx_rng + :project: nrfx + :members: diff --git a/doc/sphinx/drivers/rng/hal.rst b/doc/sphinx/drivers/rng/hal.rst new file mode 100644 index 0000000000..57179e66e5 --- /dev/null +++ b/doc/sphinx/drivers/rng/hal.rst @@ -0,0 +1,6 @@ +RNG HAL +======= + +.. doxygengroup:: nrf_rng_hal + :project: nrfx + :members: diff --git a/doc/sphinx/drivers/rng/index.rst b/doc/sphinx/drivers/rng/index.rst new file mode 100644 index 0000000000..84c3fb1d11 --- /dev/null +++ b/doc/sphinx/drivers/rng/index.rst @@ -0,0 +1,9 @@ +RNG +=== + +.. doxygengroup:: nrf_rng + +.. toctree:: + :glob: + + * \ No newline at end of file diff --git a/doc/sphinx/drivers/rtc/driver.rst b/doc/sphinx/drivers/rtc/driver.rst new file mode 100644 index 0000000000..15e1e3c505 --- /dev/null +++ b/doc/sphinx/drivers/rtc/driver.rst @@ -0,0 +1,6 @@ +RTC driver +========== + +.. doxygengroup:: nrfx_rtc + :project: nrfx + :members: diff --git a/doc/sphinx/drivers/rtc/hal.rst b/doc/sphinx/drivers/rtc/hal.rst new file mode 100644 index 0000000000..c0f7786354 --- /dev/null +++ b/doc/sphinx/drivers/rtc/hal.rst @@ -0,0 +1,6 @@ +RTC HAL +======= + +.. doxygengroup:: nrf_rtc_hal + :project: nrfx + :members: diff --git a/doc/sphinx/drivers/rtc/index.rst b/doc/sphinx/drivers/rtc/index.rst new file mode 100644 index 0000000000..6d21620ec9 --- /dev/null +++ b/doc/sphinx/drivers/rtc/index.rst @@ -0,0 +1,9 @@ +RTC +=== + +.. doxygengroup:: nrf_rtc + +.. toctree:: + :glob: + + * \ No newline at end of file diff --git a/doc/sphinx/drivers/saadc/driver.rst b/doc/sphinx/drivers/saadc/driver.rst new file mode 100644 index 0000000000..1278a93117 --- /dev/null +++ b/doc/sphinx/drivers/saadc/driver.rst @@ -0,0 +1,6 @@ +SAADC driver +============ + +.. doxygengroup:: nrfx_saadc + :project: nrfx + :members: diff --git a/doc/sphinx/drivers/saadc/hal.rst b/doc/sphinx/drivers/saadc/hal.rst new file mode 100644 index 0000000000..6de87891ab --- /dev/null +++ b/doc/sphinx/drivers/saadc/hal.rst @@ -0,0 +1,6 @@ +SAADC HAL +========= + +.. doxygengroup:: nrf_saadc_hal + :project: nrfx + :members: diff --git a/doc/sphinx/drivers/saadc/index.rst b/doc/sphinx/drivers/saadc/index.rst new file mode 100644 index 0000000000..1489a34937 --- /dev/null +++ b/doc/sphinx/drivers/saadc/index.rst @@ -0,0 +1,9 @@ +SAADC +===== + +.. doxygengroup:: nrf_saadc + +.. toctree:: + :glob: + + * \ No newline at end of file diff --git a/doc/sphinx/drivers/spi/driver.rst b/doc/sphinx/drivers/spi/driver.rst new file mode 100644 index 0000000000..f784dd256f --- /dev/null +++ b/doc/sphinx/drivers/spi/driver.rst @@ -0,0 +1,6 @@ +SPI driver +========== + +.. doxygengroup:: nrfx_spi + :project: nrfx + :members: diff --git a/doc/sphinx/drivers/spi/hal.rst b/doc/sphinx/drivers/spi/hal.rst new file mode 100644 index 0000000000..c7f4f29bcb --- /dev/null +++ b/doc/sphinx/drivers/spi/hal.rst @@ -0,0 +1,6 @@ +SPI HAL +======= + +.. doxygengroup:: nrf_spi_hal + :project: nrfx + :members: diff --git a/doc/sphinx/drivers/spi/index.rst b/doc/sphinx/drivers/spi/index.rst new file mode 100644 index 0000000000..11ee155999 --- /dev/null +++ b/doc/sphinx/drivers/spi/index.rst @@ -0,0 +1,9 @@ +SPI +=== + +.. doxygengroup:: nrf_spi + +.. toctree:: + :glob: + + * \ No newline at end of file diff --git a/doc/sphinx/drivers/spim/driver.rst b/doc/sphinx/drivers/spim/driver.rst new file mode 100644 index 0000000000..836609b4f9 --- /dev/null +++ b/doc/sphinx/drivers/spim/driver.rst @@ -0,0 +1,6 @@ +SPIM driver +=========== + +.. doxygengroup:: nrfx_spim + :project: nrfx + :members: diff --git a/doc/sphinx/drivers/spim/hal.rst b/doc/sphinx/drivers/spim/hal.rst new file mode 100644 index 0000000000..953bf24403 --- /dev/null +++ b/doc/sphinx/drivers/spim/hal.rst @@ -0,0 +1,6 @@ +SPIM HAL +======== + +.. doxygengroup:: nrf_spim_hal + :project: nrfx + :members: diff --git a/doc/sphinx/drivers/spim/index.rst b/doc/sphinx/drivers/spim/index.rst new file mode 100644 index 0000000000..086e222cd5 --- /dev/null +++ b/doc/sphinx/drivers/spim/index.rst @@ -0,0 +1,9 @@ +SPIM +==== + +.. doxygengroup:: nrf_spim + +.. toctree:: + :glob: + + * \ No newline at end of file diff --git a/doc/sphinx/drivers/spis/driver.rst b/doc/sphinx/drivers/spis/driver.rst new file mode 100644 index 0000000000..01eb56827f --- /dev/null +++ b/doc/sphinx/drivers/spis/driver.rst @@ -0,0 +1,6 @@ +SPIS driver +=========== + +.. doxygengroup:: nrfx_spis + :project: nrfx + :members: diff --git a/doc/sphinx/drivers/spis/hal.rst b/doc/sphinx/drivers/spis/hal.rst new file mode 100644 index 0000000000..792e45926d --- /dev/null +++ b/doc/sphinx/drivers/spis/hal.rst @@ -0,0 +1,6 @@ +SPIS HAL +======== + +.. doxygengroup:: nrf_spis_hal + :project: nrfx + :members: diff --git a/doc/sphinx/drivers/spis/index.rst b/doc/sphinx/drivers/spis/index.rst new file mode 100644 index 0000000000..8942c0a7cb --- /dev/null +++ b/doc/sphinx/drivers/spis/index.rst @@ -0,0 +1,9 @@ +SPIS +==== + +.. doxygengroup:: nrf_spis + +.. toctree:: + :glob: + + * \ No newline at end of file diff --git a/doc/sphinx/drivers/spu/hal.rst b/doc/sphinx/drivers/spu/hal.rst new file mode 100644 index 0000000000..b06b117fff --- /dev/null +++ b/doc/sphinx/drivers/spu/hal.rst @@ -0,0 +1,6 @@ +SPU HAL +======= + +.. doxygengroup:: nrf_spu_hal + :project: nrfx + :members: diff --git a/doc/sphinx/drivers/spu/index.rst b/doc/sphinx/drivers/spu/index.rst new file mode 100644 index 0000000000..10a7f36725 --- /dev/null +++ b/doc/sphinx/drivers/spu/index.rst @@ -0,0 +1,9 @@ +SPU +=== + +.. doxygengroup:: nrf_spu + +.. toctree:: + :glob: + + * \ No newline at end of file diff --git a/doc/sphinx/drivers/systick/driver.rst b/doc/sphinx/drivers/systick/driver.rst new file mode 100644 index 0000000000..59b7659cb0 --- /dev/null +++ b/doc/sphinx/drivers/systick/driver.rst @@ -0,0 +1,6 @@ +SYSTICK driver +============== + +.. doxygengroup:: nrfx_systick + :project: nrfx + :members: diff --git a/doc/sphinx/drivers/systick/hal.rst b/doc/sphinx/drivers/systick/hal.rst new file mode 100644 index 0000000000..88807ce18d --- /dev/null +++ b/doc/sphinx/drivers/systick/hal.rst @@ -0,0 +1,6 @@ +SYSTICK HAL +=========== + +.. doxygengroup:: nrf_systick_hal + :project: nrfx + :members: diff --git a/doc/sphinx/drivers/systick/index.rst b/doc/sphinx/drivers/systick/index.rst new file mode 100644 index 0000000000..3adbcde282 --- /dev/null +++ b/doc/sphinx/drivers/systick/index.rst @@ -0,0 +1,9 @@ +SYSTICK +======= + +.. doxygengroup:: nrf_systick + +.. toctree:: + :glob: + + * \ No newline at end of file diff --git a/doc/sphinx/drivers/temp/driver.rst b/doc/sphinx/drivers/temp/driver.rst new file mode 100644 index 0000000000..67b9761be9 --- /dev/null +++ b/doc/sphinx/drivers/temp/driver.rst @@ -0,0 +1,6 @@ +TEMP driver +=========== + +.. doxygengroup:: nrfx_temp + :project: nrfx + :members: diff --git a/doc/sphinx/drivers/temp/hal.rst b/doc/sphinx/drivers/temp/hal.rst new file mode 100644 index 0000000000..538053e6df --- /dev/null +++ b/doc/sphinx/drivers/temp/hal.rst @@ -0,0 +1,6 @@ +TEMP HAL +======== + +.. doxygengroup:: nrf_temp_hal + :project: nrfx + :members: diff --git a/doc/sphinx/drivers/temp/index.rst b/doc/sphinx/drivers/temp/index.rst new file mode 100644 index 0000000000..7b993e1ed9 --- /dev/null +++ b/doc/sphinx/drivers/temp/index.rst @@ -0,0 +1,9 @@ +TEMP +==== + +.. doxygengroup:: nrf_temp + +.. toctree:: + :glob: + + * \ No newline at end of file diff --git a/doc/sphinx/drivers/timer/driver.rst b/doc/sphinx/drivers/timer/driver.rst new file mode 100644 index 0000000000..051299e9fe --- /dev/null +++ b/doc/sphinx/drivers/timer/driver.rst @@ -0,0 +1,6 @@ +TIMER driver +============ + +.. doxygengroup:: nrfx_timer + :project: nrfx + :members: diff --git a/doc/sphinx/drivers/timer/hal.rst b/doc/sphinx/drivers/timer/hal.rst new file mode 100644 index 0000000000..d232a10fc6 --- /dev/null +++ b/doc/sphinx/drivers/timer/hal.rst @@ -0,0 +1,6 @@ +TIMER HAL +========= + +.. doxygengroup:: nrf_timer_hal + :project: nrfx + :members: diff --git a/doc/sphinx/drivers/timer/index.rst b/doc/sphinx/drivers/timer/index.rst new file mode 100644 index 0000000000..15273b3244 --- /dev/null +++ b/doc/sphinx/drivers/timer/index.rst @@ -0,0 +1,9 @@ +TIMER +===== + +.. doxygengroup:: nrf_timer + +.. toctree:: + :glob: + + * \ No newline at end of file diff --git a/doc/sphinx/drivers/twi/driver.rst b/doc/sphinx/drivers/twi/driver.rst new file mode 100644 index 0000000000..6c90acf39f --- /dev/null +++ b/doc/sphinx/drivers/twi/driver.rst @@ -0,0 +1,6 @@ +TWI driver +========== + +.. doxygengroup:: nrfx_twi + :project: nrfx + :members: diff --git a/doc/sphinx/drivers/twi/hal.rst b/doc/sphinx/drivers/twi/hal.rst new file mode 100644 index 0000000000..da841a634c --- /dev/null +++ b/doc/sphinx/drivers/twi/hal.rst @@ -0,0 +1,6 @@ +TWI HAL +======= + +.. doxygengroup:: nrf_twi_hal + :project: nrfx + :members: diff --git a/doc/sphinx/drivers/twi/index.rst b/doc/sphinx/drivers/twi/index.rst new file mode 100644 index 0000000000..fec3d3c2d5 --- /dev/null +++ b/doc/sphinx/drivers/twi/index.rst @@ -0,0 +1,9 @@ +TWI +=== + +.. doxygengroup:: nrf_twi + +.. toctree:: + :glob: + + * \ No newline at end of file diff --git a/doc/sphinx/drivers/twim/driver.rst b/doc/sphinx/drivers/twim/driver.rst new file mode 100644 index 0000000000..43d4a05ea1 --- /dev/null +++ b/doc/sphinx/drivers/twim/driver.rst @@ -0,0 +1,6 @@ +TWIM driver +=========== + +.. doxygengroup:: nrfx_twim + :project: nrfx + :members: diff --git a/doc/sphinx/drivers/twim/hal.rst b/doc/sphinx/drivers/twim/hal.rst new file mode 100644 index 0000000000..621b578d9d --- /dev/null +++ b/doc/sphinx/drivers/twim/hal.rst @@ -0,0 +1,6 @@ +TWIM HAL +======== + +.. doxygengroup:: nrf_twim_hal + :project: nrfx + :members: diff --git a/doc/sphinx/drivers/twim/index.rst b/doc/sphinx/drivers/twim/index.rst new file mode 100644 index 0000000000..e12baeb0ef --- /dev/null +++ b/doc/sphinx/drivers/twim/index.rst @@ -0,0 +1,9 @@ +TWIM +==== + +.. doxygengroup:: nrf_twim + +.. toctree:: + :glob: + + * \ No newline at end of file diff --git a/doc/sphinx/drivers/twis/driver.rst b/doc/sphinx/drivers/twis/driver.rst new file mode 100644 index 0000000000..ab8c91f999 --- /dev/null +++ b/doc/sphinx/drivers/twis/driver.rst @@ -0,0 +1,6 @@ +TWIS driver +=========== + +.. doxygengroup:: nrfx_twis + :project: nrfx + :members: diff --git a/doc/sphinx/drivers/twis/hal.rst b/doc/sphinx/drivers/twis/hal.rst new file mode 100644 index 0000000000..63272ef833 --- /dev/null +++ b/doc/sphinx/drivers/twis/hal.rst @@ -0,0 +1,6 @@ +TWIS HAL +======== + +.. doxygengroup:: nrf_twis_hal + :project: nrfx + :members: diff --git a/doc/sphinx/drivers/twis/index.rst b/doc/sphinx/drivers/twis/index.rst new file mode 100644 index 0000000000..9737960c00 --- /dev/null +++ b/doc/sphinx/drivers/twis/index.rst @@ -0,0 +1,9 @@ +TWIS +==== + +.. doxygengroup:: nrf_twis + +.. toctree:: + :glob: + + * \ No newline at end of file diff --git a/doc/sphinx/drivers/uart/driver.rst b/doc/sphinx/drivers/uart/driver.rst new file mode 100644 index 0000000000..4c450dba0f --- /dev/null +++ b/doc/sphinx/drivers/uart/driver.rst @@ -0,0 +1,6 @@ +UART driver +=========== + +.. doxygengroup:: nrfx_uart + :project: nrfx + :members: diff --git a/doc/sphinx/drivers/uart/hal.rst b/doc/sphinx/drivers/uart/hal.rst new file mode 100644 index 0000000000..28b80104e3 --- /dev/null +++ b/doc/sphinx/drivers/uart/hal.rst @@ -0,0 +1,6 @@ +UART HAL +======== + +.. doxygengroup:: nrf_uart_hal + :project: nrfx + :members: diff --git a/doc/sphinx/drivers/uart/index.rst b/doc/sphinx/drivers/uart/index.rst new file mode 100644 index 0000000000..1fb2881336 --- /dev/null +++ b/doc/sphinx/drivers/uart/index.rst @@ -0,0 +1,9 @@ +UART +==== + +.. doxygengroup:: nrf_uart + +.. toctree:: + :glob: + + * \ No newline at end of file diff --git a/doc/sphinx/drivers/uarte/driver.rst b/doc/sphinx/drivers/uarte/driver.rst new file mode 100644 index 0000000000..42880de790 --- /dev/null +++ b/doc/sphinx/drivers/uarte/driver.rst @@ -0,0 +1,6 @@ +UARTE driver +============ + +.. doxygengroup:: nrfx_uarte + :project: nrfx + :members: diff --git a/doc/sphinx/drivers/uarte/hal.rst b/doc/sphinx/drivers/uarte/hal.rst new file mode 100644 index 0000000000..a2e8dd7d94 --- /dev/null +++ b/doc/sphinx/drivers/uarte/hal.rst @@ -0,0 +1,6 @@ +UARTE HAL +========= + +.. doxygengroup:: nrf_uarte_hal + :project: nrfx + :members: diff --git a/doc/sphinx/drivers/uarte/index.rst b/doc/sphinx/drivers/uarte/index.rst new file mode 100644 index 0000000000..843a7b1862 --- /dev/null +++ b/doc/sphinx/drivers/uarte/index.rst @@ -0,0 +1,9 @@ +UARTE +===== + +.. doxygengroup:: nrf_uarte + +.. toctree:: + :glob: + + * \ No newline at end of file diff --git a/doc/sphinx/drivers/usbd/driver.rst b/doc/sphinx/drivers/usbd/driver.rst new file mode 100644 index 0000000000..4ab67f582b --- /dev/null +++ b/doc/sphinx/drivers/usbd/driver.rst @@ -0,0 +1,6 @@ +USBD driver +=========== + +.. doxygengroup:: nrfx_usbd + :project: nrfx + :members: diff --git a/doc/sphinx/drivers/usbd/hal.rst b/doc/sphinx/drivers/usbd/hal.rst new file mode 100644 index 0000000000..080ac2918b --- /dev/null +++ b/doc/sphinx/drivers/usbd/hal.rst @@ -0,0 +1,6 @@ +USBD HAL +======== + +.. doxygengroup:: nrf_usbd_hal + :project: nrfx + :members: diff --git a/doc/sphinx/drivers/usbd/index.rst b/doc/sphinx/drivers/usbd/index.rst new file mode 100644 index 0000000000..7b3302d63c --- /dev/null +++ b/doc/sphinx/drivers/usbd/index.rst @@ -0,0 +1,11 @@ +USBD +==== + +.. doxygengroup:: nrf_usbd + +.. toctree:: + :glob: + + * + ../usbreg/driver.rst + ../usbreg/hal.rst diff --git a/doc/sphinx/drivers/usbreg/driver.rst b/doc/sphinx/drivers/usbreg/driver.rst new file mode 100644 index 0000000000..913650dd43 --- /dev/null +++ b/doc/sphinx/drivers/usbreg/driver.rst @@ -0,0 +1,6 @@ +USBREG driver +============= + +.. doxygengroup:: nrfx_usbreg + :project: nrfx + :members: diff --git a/doc/sphinx/drivers/usbreg/hal.rst b/doc/sphinx/drivers/usbreg/hal.rst new file mode 100644 index 0000000000..4afd83de7c --- /dev/null +++ b/doc/sphinx/drivers/usbreg/hal.rst @@ -0,0 +1,6 @@ +USBREG HAL +========== + +.. doxygengroup:: nrf_usbreg_hal + :project: nrfx + :members: diff --git a/doc/sphinx/drivers/vmc/hal.rst b/doc/sphinx/drivers/vmc/hal.rst new file mode 100644 index 0000000000..c67e7694c9 --- /dev/null +++ b/doc/sphinx/drivers/vmc/hal.rst @@ -0,0 +1,6 @@ +VMC HAL +======= + +.. doxygengroup:: nrf_vmc_hal + :project: nrfx + :members: diff --git a/doc/sphinx/drivers/vmc/index.rst b/doc/sphinx/drivers/vmc/index.rst new file mode 100644 index 0000000000..02b65f3fbe --- /dev/null +++ b/doc/sphinx/drivers/vmc/index.rst @@ -0,0 +1,9 @@ +VMC +=== + +.. doxygengroup:: nrf_vmc + +.. toctree:: + :glob: + + * \ No newline at end of file diff --git a/doc/sphinx/drivers/vreqctrl/hal.rst b/doc/sphinx/drivers/vreqctrl/hal.rst new file mode 100644 index 0000000000..7cf39e30b2 --- /dev/null +++ b/doc/sphinx/drivers/vreqctrl/hal.rst @@ -0,0 +1,6 @@ +VREQCTRL HAL +============ + +.. doxygengroup:: nrf_vreqctrl_hal + :project: nrfx + :members: diff --git a/doc/sphinx/drivers/wdt/driver.rst b/doc/sphinx/drivers/wdt/driver.rst new file mode 100644 index 0000000000..7869a43b48 --- /dev/null +++ b/doc/sphinx/drivers/wdt/driver.rst @@ -0,0 +1,6 @@ +WDT driver +========== + +.. doxygengroup:: nrfx_wdt + :project: nrfx + :members: diff --git a/doc/sphinx/drivers/wdt/hal.rst b/doc/sphinx/drivers/wdt/hal.rst new file mode 100644 index 0000000000..28b9f2b179 --- /dev/null +++ b/doc/sphinx/drivers/wdt/hal.rst @@ -0,0 +1,6 @@ +WDT HAL +======= + +.. doxygengroup:: nrf_wdt_hal + :project: nrfx + :members: diff --git a/doc/sphinx/drivers/wdt/index.rst b/doc/sphinx/drivers/wdt/index.rst new file mode 100644 index 0000000000..dd698f70dc --- /dev/null +++ b/doc/sphinx/drivers/wdt/index.rst @@ -0,0 +1,9 @@ +WDT +=== + +.. doxygengroup:: nrf_wdt + +.. toctree:: + :glob: + + * \ No newline at end of file diff --git a/doc/sphinx/drv_supp_matrix.rst b/doc/sphinx/drv_supp_matrix.rst new file mode 100644 index 0000000000..0f8b71c89b --- /dev/null +++ b/doc/sphinx/drv_supp_matrix.rst @@ -0,0 +1,26 @@ +Driver support overview +======================= + +.. toctree:: + :hidden: + + nrf51_series + nrf52805 + nrf52810 + nrf52820 + nrf52832 + nrf52833 + nrf52840 + nrf5340 + nrf9160 + +.. role:: red +.. role:: green + +.. raw:: html + + + + +.. doxygenpage:: nrfx_drv_supp_matrix + :content-only: diff --git a/doc/sphinx/index.rst b/doc/sphinx/index.rst new file mode 100644 index 0000000000..333e14b0e0 --- /dev/null +++ b/doc/sphinx/index.rst @@ -0,0 +1,14 @@ +Introduction and configuration +============================== + +.. doxygenpage:: index + :content-only: + +.. toctree:: + :maxdepth: 2 + :caption: Contents + :hidden: + + changelog + drv_supp_matrix + api_reference \ No newline at end of file diff --git a/doc/sphinx/nrf51_series.rst b/doc/sphinx/nrf51_series.rst new file mode 100644 index 0000000000..b56c633ef5 --- /dev/null +++ b/doc/sphinx/nrf51_series.rst @@ -0,0 +1,5 @@ +nRF51 Series Drivers +==================== + +.. doxygenpage:: nrf51_series_drivers + :content-only: \ No newline at end of file diff --git a/doc/sphinx/nrf52805.rst b/doc/sphinx/nrf52805.rst new file mode 100644 index 0000000000..f790b78dda --- /dev/null +++ b/doc/sphinx/nrf52805.rst @@ -0,0 +1,5 @@ +nRF52805 Drivers +================ + +.. doxygenpage:: nrf52805_drivers + :content-only: diff --git a/doc/sphinx/nrf52810.rst b/doc/sphinx/nrf52810.rst new file mode 100644 index 0000000000..7022704675 --- /dev/null +++ b/doc/sphinx/nrf52810.rst @@ -0,0 +1,5 @@ +nRF52810/nRF52811 Drivers +========================= + +.. doxygenpage:: nrf52810_drivers + :content-only: \ No newline at end of file diff --git a/doc/sphinx/nrf52820.rst b/doc/sphinx/nrf52820.rst new file mode 100644 index 0000000000..0f089cf26b --- /dev/null +++ b/doc/sphinx/nrf52820.rst @@ -0,0 +1,5 @@ +nRF52820 Drivers +================ + +.. doxygenpage:: nrf52820_drivers + :content-only: \ No newline at end of file diff --git a/doc/sphinx/nrf52832.rst b/doc/sphinx/nrf52832.rst new file mode 100644 index 0000000000..3d1a46a12b --- /dev/null +++ b/doc/sphinx/nrf52832.rst @@ -0,0 +1,5 @@ +nRF52832 Drivers +================ + +.. doxygenpage:: nrf52832_drivers + :content-only: \ No newline at end of file diff --git a/doc/sphinx/nrf52833.rst b/doc/sphinx/nrf52833.rst new file mode 100644 index 0000000000..6e6e38d51f --- /dev/null +++ b/doc/sphinx/nrf52833.rst @@ -0,0 +1,5 @@ +nRF52833 Drivers +================ + +.. doxygenpage:: nrf52833_drivers + :content-only: \ No newline at end of file diff --git a/doc/sphinx/nrf52840.rst b/doc/sphinx/nrf52840.rst new file mode 100644 index 0000000000..a96beaa63b --- /dev/null +++ b/doc/sphinx/nrf52840.rst @@ -0,0 +1,5 @@ +nRF52840 Drivers +================ + +.. doxygenpage:: nrf52840_drivers + :content-only: \ No newline at end of file diff --git a/doc/sphinx/nrf5340.rst b/doc/sphinx/nrf5340.rst new file mode 100644 index 0000000000..0d0240991d --- /dev/null +++ b/doc/sphinx/nrf5340.rst @@ -0,0 +1,5 @@ +nRF5340 drivers +=============== + +.. doxygenpage:: nrf5340_drivers + :content-only: \ No newline at end of file diff --git a/doc/sphinx/nrf9160.rst b/doc/sphinx/nrf9160.rst new file mode 100644 index 0000000000..720254113c --- /dev/null +++ b/doc/sphinx/nrf9160.rst @@ -0,0 +1,5 @@ +nRF9160 drivers +=============== + +.. doxygenpage:: nrf9160_drivers + :content-only: \ No newline at end of file diff --git a/doc/sphinx/nrfx_api/atomic.rst b/doc/sphinx/nrfx_api/atomic.rst new file mode 100644 index 0000000000..e3d4dc1e5e --- /dev/null +++ b/doc/sphinx/nrfx_api/atomic.rst @@ -0,0 +1,6 @@ +Atomic operations API +===================== + +.. doxygengroup:: nrfx_atomic + :project: nrfx + :members: \ No newline at end of file diff --git a/doc/sphinx/nrfx_api/bitmask.rst b/doc/sphinx/nrfx_api/bitmask.rst new file mode 100644 index 0000000000..32d60b0d48 --- /dev/null +++ b/doc/sphinx/nrfx_api/bitmask.rst @@ -0,0 +1,6 @@ +Bitmask module +============== + +.. doxygengroup:: nrf_bitmask + :project: nrfx + :members: \ No newline at end of file diff --git a/doc/sphinx/nrfx_api/common.rst b/doc/sphinx/nrfx_api/common.rst new file mode 100644 index 0000000000..c672b6c05c --- /dev/null +++ b/doc/sphinx/nrfx_api/common.rst @@ -0,0 +1,6 @@ +Common module +============= + +.. doxygengroup:: nrfx_common + :project: nrfx + :members: \ No newline at end of file diff --git a/doc/sphinx/nrfx_api/coredep.rst b/doc/sphinx/nrfx_api/coredep.rst new file mode 100644 index 0000000000..553ab6d675 --- /dev/null +++ b/doc/sphinx/nrfx_api/coredep.rst @@ -0,0 +1,6 @@ +Core-dependent functionality +============================ + +.. doxygengroup:: nrfx_coredep + :project: nrfx + :members: \ No newline at end of file diff --git a/doc/sphinx/nrfx_api/error_codes.rst b/doc/sphinx/nrfx_api/error_codes.rst new file mode 100644 index 0000000000..dce39f37ea --- /dev/null +++ b/doc/sphinx/nrfx_api/error_codes.rst @@ -0,0 +1,6 @@ +Global Error Codes +================== + +.. doxygengroup:: nrfx_error_codes + :project: nrfx + :members: \ No newline at end of file diff --git a/doc/sphinx/nrfx_api/glue.rst b/doc/sphinx/nrfx_api/glue.rst new file mode 100644 index 0000000000..dc6c196158 --- /dev/null +++ b/doc/sphinx/nrfx_api/glue.rst @@ -0,0 +1,6 @@ +nrfx_glue.h +=========== + +.. doxygengroup:: nrfx_glue + :project: nrfx + :members: \ No newline at end of file diff --git a/doc/sphinx/nrfx_api/gppi.rst b/doc/sphinx/nrfx_api/gppi.rst new file mode 100644 index 0000000000..c3b557a6bc --- /dev/null +++ b/doc/sphinx/nrfx_api/gppi.rst @@ -0,0 +1,6 @@ +Generic PPI Layer +================= + +.. doxygengroup:: nrfx_gppi + :project: nrfx + :members: \ No newline at end of file diff --git a/doc/sphinx/nrfx_api/index.rst b/doc/sphinx/nrfx_api/index.rst new file mode 100644 index 0000000000..f395c96fea --- /dev/null +++ b/doc/sphinx/nrfx_api/index.rst @@ -0,0 +1,7 @@ +nrfx API +======== + +.. toctree:: + :glob: + + * \ No newline at end of file diff --git a/doc/sphinx/nrfx_api/log.rst b/doc/sphinx/nrfx_api/log.rst new file mode 100644 index 0000000000..2a86bbbde6 --- /dev/null +++ b/doc/sphinx/nrfx_api/log.rst @@ -0,0 +1,6 @@ +nrfx_log.h +========== + +.. doxygengroup:: nrfx_log + :project: nrfx + :members: \ No newline at end of file diff --git a/doc/sphinx/nrfx_api/prs.rst b/doc/sphinx/nrfx_api/prs.rst new file mode 100644 index 0000000000..6baa466a66 --- /dev/null +++ b/doc/sphinx/nrfx_api/prs.rst @@ -0,0 +1,6 @@ +Peripheral Resource Sharing (PRS) +================================= + +.. doxygengroup:: nrfx_prs + :project: nrfx + :members: \ No newline at end of file diff --git a/doc/sphinx/nrfx_api/reset_reason.rst b/doc/sphinx/nrfx_api/reset_reason.rst new file mode 100644 index 0000000000..332b9aa8a1 --- /dev/null +++ b/doc/sphinx/nrfx_api/reset_reason.rst @@ -0,0 +1,6 @@ +Generic Reset Reason layer +========================== + +.. doxygengroup:: nrfx_reset_reason + :project: nrfx + :members: \ No newline at end of file diff --git a/doc/sphinx/requirements.txt b/doc/sphinx/requirements.txt new file mode 100644 index 0000000000..36fb32cc7f --- /dev/null +++ b/doc/sphinx/requirements.txt @@ -0,0 +1,4 @@ +sphinx~=3.5 +sphinx-ncs-theme~=0.6.2 +breathe~=4.28 +m2r2~=0.2 diff --git a/drivers/include/nrf_bitmask.h b/drivers/include/nrf_bitmask.h index 3abb6ce290..19aa9f7d43 100644 --- a/drivers/include/nrf_bitmask.h +++ b/drivers/include/nrf_bitmask.h @@ -1,7 +1,9 @@ /* - * Copyright (c) 2016 - 2020, Nordic Semiconductor ASA + * Copyright (c) 2016 - 2021, Nordic Semiconductor ASA * All rights reserved. * + * SPDX-License-Identifier: BSD-3-Clause + * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * diff --git a/drivers/include/nrfx_adc.h b/drivers/include/nrfx_adc.h index 453cb7abff..4c1ae66765 100644 --- a/drivers/include/nrfx_adc.h +++ b/drivers/include/nrfx_adc.h @@ -1,7 +1,9 @@ /* - * Copyright (c) 2015 - 2020, Nordic Semiconductor ASA + * Copyright (c) 2015 - 2021, Nordic Semiconductor ASA * All rights reserved. * + * SPDX-License-Identifier: BSD-3-Clause + * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * diff --git a/drivers/include/nrfx_clock.h b/drivers/include/nrfx_clock.h index 49c5b19309..294fa5a304 100644 --- a/drivers/include/nrfx_clock.h +++ b/drivers/include/nrfx_clock.h @@ -1,7 +1,9 @@ /* - * Copyright (c) 2016 - 2020, Nordic Semiconductor ASA + * Copyright (c) 2016 - 2021, Nordic Semiconductor ASA * All rights reserved. * + * SPDX-License-Identifier: BSD-3-Clause + * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * @@ -117,7 +119,7 @@ void nrfx_clock_stop(nrf_clock_domain_t domain); */ NRFX_STATIC_INLINE bool nrfx_clock_is_running(nrf_clock_domain_t domain, void * p_clk_src); -#if NRF_CLOCK_HAS_HFCLK_DIV || NRF_CLOCK_HAS_HFCLK_192M +#if defined(CLOCK_FEATURE_HFCLK_DIVIDE_PRESENT) || NRF_CLOCK_HAS_HFCLK_192M /** * @brief Function for setting the specified clock domain divider. * @@ -269,12 +271,12 @@ NRFX_STATIC_INLINE uint32_t nrfx_clock_ppi_event_addr(nrf_clock_event_t event); #ifndef NRFX_DECLARE_ONLY -#if NRF_CLOCK_HAS_HFCLK_DIV || NRF_CLOCK_HAS_HFCLK_192M +#if defined(CLOCK_FEATURE_HFCLK_DIVIDE_PRESENT) || NRF_CLOCK_HAS_HFCLK_192M NRFX_STATIC_INLINE nrf_clock_hfclk_div_t nrfx_clock_divider_get(nrf_clock_domain_t domain) { switch (domain) { -#if NRF_CLOCK_HAS_HFCLK_DIV +#if defined(CLOCK_FEATURE_HFCLK_DIVIDE_PRESENT) case NRF_CLOCK_DOMAIN_HFCLK: return nrf_clock_hfclk_div_get(NRF_CLOCK); #endif @@ -287,7 +289,7 @@ NRFX_STATIC_INLINE nrf_clock_hfclk_div_t nrfx_clock_divider_get(nrf_clock_domain return (nrf_clock_hfclk_div_t)0; } } -#endif // NRF_CLOCK_HAS_HFCLK_DIV || NRF_CLOCK_HAS_HFCLK_192M +#endif // defined(CLOCK_FEATURE_HFCLK_DIVIDE_PRESENT) || NRF_CLOCK_HAS_HFCLK_192M NRFX_STATIC_INLINE void nrfx_clock_lfclk_start(void) { diff --git a/drivers/include/nrfx_comp.h b/drivers/include/nrfx_comp.h index d42f90148c..4d51cff439 100644 --- a/drivers/include/nrfx_comp.h +++ b/drivers/include/nrfx_comp.h @@ -1,7 +1,9 @@ /* - * Copyright (c) 2015 - 2020, Nordic Semiconductor ASA + * Copyright (c) 2015 - 2021, Nordic Semiconductor ASA * All rights reserved. * + * SPDX-License-Identifier: BSD-3-Clause + * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * diff --git a/drivers/include/nrfx_dppi.h b/drivers/include/nrfx_dppi.h index e7bc202c07..34f8df74fa 100644 --- a/drivers/include/nrfx_dppi.h +++ b/drivers/include/nrfx_dppi.h @@ -1,7 +1,9 @@ /* - * Copyright (c) 2018 - 2020, Nordic Semiconductor ASA + * Copyright (c) 2018 - 2021, Nordic Semiconductor ASA * All rights reserved. * + * SPDX-License-Identifier: BSD-3-Clause + * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * @@ -53,6 +55,11 @@ void nrfx_dppi_free(void); * @brief Function for allocating a DPPI channel. * @details This function allocates the first unused DPPI channel. * + * @note To ensure the thread safety of the operation, this function uses the + * @ref NRFX_CRITICAL_SECTION_ENTER and @ref NRFX_CRITICAL_SECTION_EXIT + * macros. No further synchronization mechanism is needed, provided the + * macros are properly implemented (see @ref nrfx_glue). + * * @param[out] p_channel Pointer to the DPPI channel number that has been allocated. * * @retval NRFX_SUCCESS The channel was successfully allocated. @@ -64,6 +71,11 @@ nrfx_err_t nrfx_dppi_channel_alloc(uint8_t * p_channel); * @brief Function for freeing a DPPI channel. * @details This function also disables the chosen channel. * + * @note To ensure the thread safety of the operation, this function uses the + * @ref NRFX_CRITICAL_SECTION_ENTER and @ref NRFX_CRITICAL_SECTION_EXIT + * macros. No further synchronization mechanism is needed, provided the + * macros are properly implemented (see @ref nrfx_glue). + * * @param[in] channel DPPI channel to be freed. * * @retval NRFX_SUCCESS The channel was successfully freed. @@ -95,6 +107,11 @@ nrfx_err_t nrfx_dppi_channel_disable(uint8_t channel); * @brief Function for allocating a DPPI channel group. * @details This function allocates the first unused DPPI group. * + * @note To ensure the thread safety of the operation, this function uses the + * @ref NRFX_CRITICAL_SECTION_ENTER and @ref NRFX_CRITICAL_SECTION_EXIT + * macros. No further synchronization mechanism is needed, provided the + * macros are properly implemented (see @ref nrfx_glue). + * * @param[out] p_group Pointer to the DPPI channel group that has been allocated. * * @retval NRFX_SUCCESS The channel group was successfully allocated. @@ -106,6 +123,11 @@ nrfx_err_t nrfx_dppi_group_alloc(nrf_dppi_channel_group_t * p_group); * @brief Function for freeing a DPPI channel group. * @details This function also disables the chosen group. * + * @note To ensure the thread safety of the operation, this function uses the + * @ref NRFX_CRITICAL_SECTION_ENTER and @ref NRFX_CRITICAL_SECTION_EXIT + * macros. No further synchronization mechanism is needed, provided the + * macros are properly implemented (see @ref nrfx_glue). + * * @param[in] group DPPI channel group to be freed. * * @retval NRFX_SUCCESS The channel group was successfully freed. @@ -119,6 +141,9 @@ nrfx_err_t nrfx_dppi_group_free(nrf_dppi_channel_group_t group); * @param[in] channel DPPI channel to be added. * @param[in] group Channel group in which to include the channel. * + * @warning Channel group configuration can be modified only if subscriptions for tasks + * associated with this group are disabled. + * * @retval NRFX_SUCCESS The channel was successfully included. * @retval NRFX_ERROR_INVALID_PARAM The specified group or channel is not allocated. */ @@ -131,6 +156,9 @@ nrfx_err_t nrfx_dppi_channel_include_in_group(uint8_t channel, * @param[in] channel DPPI channel to be removed. * @param[in] group Channel group from which to remove the channel. * + * @warning Channel group configuration can be modified only if subscriptions for tasks + * associated with this group are disabled. + * * @retval NRFX_SUCCESS The channel was successfully removed. * @retval NRFX_ERROR_INVALID_PARAM The specified group or channel is not allocated. */ @@ -142,6 +170,9 @@ nrfx_err_t nrfx_dppi_channel_remove_from_group(uint8_t channel, * * @param[in] group Channel group to be cleared. * + * @warning Channel group configuration can be modified only if subscriptions for tasks + * associated with this group are disabled. + * * @retval NRFX_SUCCESS The group was successfully cleared. * @retval NRFX_ERROR_INVALID_PARAM The specified group is not allocated. */ diff --git a/drivers/include/nrfx_egu.h b/drivers/include/nrfx_egu.h index 686e526e7d..9a57154c3f 100644 --- a/drivers/include/nrfx_egu.h +++ b/drivers/include/nrfx_egu.h @@ -1,7 +1,9 @@ /* - * Copyright (c) 2019 - 2020, Nordic Semiconductor ASA + * Copyright (c) 2019 - 2021, Nordic Semiconductor ASA * All rights reserved. * + * SPDX-License-Identifier: BSD-3-Clause + * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * diff --git a/drivers/include/nrfx_gpiote.h b/drivers/include/nrfx_gpiote.h index 8430240ac2..9048514372 100644 --- a/drivers/include/nrfx_gpiote.h +++ b/drivers/include/nrfx_gpiote.h @@ -1,7 +1,9 @@ /* - * Copyright (c) 2015 - 2020, Nordic Semiconductor ASA + * Copyright (c) 2015 - 2021, Nordic Semiconductor ASA * All rights reserved. * + * SPDX-License-Identifier: BSD-3-Clause + * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * @@ -188,8 +190,8 @@ typedef struct .task_pin = true, \ } -#if !defined (NRFX_GPIOTE_CHANNELS_USED) || defined(__NRFX_DOXYGEN__) -/** @brief Bitmask that defines GPIOTE channels that are reserved for use outside of the nrfx library. */ +#if !defined (NRFX_GPIOTE_CHANNELS_USED) && !defined(__NRFX_DOXYGEN__) +/* Bitmask that defines GPIOTE channels that are reserved for use outside of the nrfx library. */ #define NRFX_GPIOTE_CHANNELS_USED 0 #endif @@ -216,9 +218,6 @@ typedef void (*nrfx_gpiote_evt_handler_t)(nrfx_gpiote_pin_t pin, nrf_gpiote_pola /** * @brief Function for initializing the GPIOTE module. * - * @details Only static configuration is supported to prevent the shared - * resource being customized by the initiator. - * * @param[in] interrupt_priority Interrupt priority. * * @retval NRFX_SUCCESS Initialization was successful. @@ -245,9 +244,17 @@ void nrfx_gpiote_uninit(void); * @details This function allocates the first unused GPIOTE channel from * pool defined in @ref NRFX_GPIOTE_APP_CHANNELS_MASK. * + * @note To ensure the thread safety of the operation, this function uses the + * @ref NRFX_CRITICAL_SECTION_ENTER and @ref NRFX_CRITICAL_SECTION_EXIT + * macros. No further synchronization mechanism is needed, provided the + * macros are properly implemented (see @ref nrfx_glue). + * @note Routines that allocate and free the GPIOTE channels are independent + * from the rest of the driver. In particular, the driver does not need + * to be initialized when this function is called. + * * @param[out] p_channel Pointer to the GPIOTE channel that has been allocated. * - * @retval NRFX_SUCCESS The channel was successfuly allocated. + * @retval NRFX_SUCCESS The channel was successfully allocated. * @retval NRFX_ERROR_NO_MEM There is no available channel to be used. */ nrfx_err_t nrfx_gpiote_channel_alloc(uint8_t * p_channel); @@ -257,6 +264,14 @@ nrfx_err_t nrfx_gpiote_channel_alloc(uint8_t * p_channel); * @details This function frees a GPIOTE channel that was allocated using * @ref nrfx_gpiote_channel_alloc. * + * @note To ensure the thread safety of the operation, this function uses the + * @ref NRFX_CRITICAL_SECTION_ENTER and @ref NRFX_CRITICAL_SECTION_EXIT + * macros. No further synchronization mechanism is needed, provided the + * macros are properly implemented (see @ref nrfx_glue). + * @note Routines that allocate and free the GPIOTE channels are independent + * from the rest of the driver. In particular, the driver does not need + * to be initialized when this function is called. + * * @param[in] channel GPIOTE channel to be freed. * * @retval NRFX_SUCCESS The channel was successfully freed. diff --git a/drivers/include/nrfx_i2s.h b/drivers/include/nrfx_i2s.h index 698a7d6bf6..ef6a916a43 100644 --- a/drivers/include/nrfx_i2s.h +++ b/drivers/include/nrfx_i2s.h @@ -1,7 +1,9 @@ /* - * Copyright (c) 2015 - 2020, Nordic Semiconductor ASA + * Copyright (c) 2015 - 2021, Nordic Semiconductor ASA * All rights reserved. * + * SPDX-License-Identifier: BSD-3-Clause + * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * diff --git a/drivers/include/nrfx_ipc.h b/drivers/include/nrfx_ipc.h index d6331a2644..10c2031a34 100644 --- a/drivers/include/nrfx_ipc.h +++ b/drivers/include/nrfx_ipc.h @@ -1,7 +1,9 @@ /* - * Copyright (c) 2019 - 2020, Nordic Semiconductor ASA + * Copyright (c) 2019 - 2021, Nordic Semiconductor ASA * All rights reserved. * + * SPDX-License-Identifier: BSD-3-Clause + * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * diff --git a/drivers/include/nrfx_lpcomp.h b/drivers/include/nrfx_lpcomp.h index 9ec92acca9..c14a16bff4 100644 --- a/drivers/include/nrfx_lpcomp.h +++ b/drivers/include/nrfx_lpcomp.h @@ -1,7 +1,9 @@ /* - * Copyright (c) 2014 - 2020, Nordic Semiconductor ASA + * Copyright (c) 2014 - 2021, Nordic Semiconductor ASA * All rights reserved. * + * SPDX-License-Identifier: BSD-3-Clause + * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * diff --git a/drivers/include/nrfx_nfct.h b/drivers/include/nrfx_nfct.h index c1cfe12f02..b89509ba05 100644 --- a/drivers/include/nrfx_nfct.h +++ b/drivers/include/nrfx_nfct.h @@ -1,7 +1,9 @@ /* - * Copyright (c) 2018 - 2020, Nordic Semiconductor ASA + * Copyright (c) 2018 - 2021, Nordic Semiconductor ASA * All rights reserved. * + * SPDX-License-Identifier: BSD-3-Clause + * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * diff --git a/drivers/include/nrfx_nvmc.h b/drivers/include/nrfx_nvmc.h index e5fb974a5b..7f84ad57f7 100644 --- a/drivers/include/nrfx_nvmc.h +++ b/drivers/include/nrfx_nvmc.h @@ -1,7 +1,9 @@ /* - * Copyright (c) 2019 - 2020, Nordic Semiconductor ASA + * Copyright (c) 2019 - 2021, Nordic Semiconductor ASA * All rights reserved. * + * SPDX-License-Identifier: BSD-3-Clause + * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * diff --git a/drivers/include/nrfx_pdm.h b/drivers/include/nrfx_pdm.h index 3396273521..12d60a9205 100644 --- a/drivers/include/nrfx_pdm.h +++ b/drivers/include/nrfx_pdm.h @@ -1,7 +1,9 @@ /* - * Copyright (c) 2015 - 2020, Nordic Semiconductor ASA + * Copyright (c) 2015 - 2021, Nordic Semiconductor ASA * All rights reserved. * + * SPDX-License-Identifier: BSD-3-Clause + * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * diff --git a/drivers/include/nrfx_power.h b/drivers/include/nrfx_power.h index d1136e570d..42ba790662 100644 --- a/drivers/include/nrfx_power.h +++ b/drivers/include/nrfx_power.h @@ -1,7 +1,9 @@ /* - * Copyright (c) 2017 - 2020, Nordic Semiconductor ASA + * Copyright (c) 2017 - 2021, Nordic Semiconductor ASA * All rights reserved. * + * SPDX-License-Identifier: BSD-3-Clause + * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * diff --git a/drivers/include/nrfx_power_clock.h b/drivers/include/nrfx_power_clock.h index 50b4603a02..ad6fbfed17 100644 --- a/drivers/include/nrfx_power_clock.h +++ b/drivers/include/nrfx_power_clock.h @@ -1,7 +1,9 @@ /* - * Copyright (c) 2015 - 2020, Nordic Semiconductor ASA + * Copyright (c) 2015 - 2021, Nordic Semiconductor ASA * All rights reserved. * + * SPDX-License-Identifier: BSD-3-Clause + * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * diff --git a/drivers/include/nrfx_power_compat.h b/drivers/include/nrfx_power_compat.h index 508a03f537..49d73ff8af 100644 --- a/drivers/include/nrfx_power_compat.h +++ b/drivers/include/nrfx_power_compat.h @@ -1,7 +1,9 @@ /* - * Copyright (c) 2019 - 2020, Nordic Semiconductor ASA + * Copyright (c) 2019 - 2021, Nordic Semiconductor ASA * All rights reserved. * + * SPDX-License-Identifier: BSD-3-Clause + * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * diff --git a/drivers/include/nrfx_ppi.h b/drivers/include/nrfx_ppi.h index 42693bf020..4824361b28 100644 --- a/drivers/include/nrfx_ppi.h +++ b/drivers/include/nrfx_ppi.h @@ -1,7 +1,9 @@ /* - * Copyright (c) 2015 - 2020, Nordic Semiconductor ASA + * Copyright (c) 2015 - 2021, Nordic Semiconductor ASA * All rights reserved. * + * SPDX-License-Identifier: BSD-3-Clause + * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * @@ -46,13 +48,13 @@ extern "C" { #endif -#if !defined (NRFX_PPI_CHANNELS_USED) || defined(__NRFX_DOXYGEN__) -/** @brief Bitfield representing PPI channels used by external modules. */ +#if !defined (NRFX_PPI_CHANNELS_USED) && !defined(__NRFX_DOXYGEN__) +/* Bitfield representing PPI channels used by external modules. */ #define NRFX_PPI_CHANNELS_USED 0 #endif -#if !defined(NRFX_PPI_GROUPS_USED) || defined(__NRFX_DOXYGEN__) -/** @brief Bitfield representing PPI groups used by external modules. */ +#if !defined(NRFX_PPI_GROUPS_USED) && !defined(__NRFX_DOXYGEN__) +/* Bitfield representing PPI groups used by external modules. */ #define NRFX_PPI_GROUPS_USED 0 #endif @@ -80,6 +82,11 @@ void nrfx_ppi_free_all(void); * @brief Function for allocating a PPI channel. * @details This function allocates the first unused PPI channel. * + * @note To ensure the thread safety of the operation, this function uses the + * @ref NRFX_CRITICAL_SECTION_ENTER and @ref NRFX_CRITICAL_SECTION_EXIT + * macros. No further synchronization mechanism is needed, provided the + * macros are properly implemented (see @ref nrfx_glue). + * * @param[out] p_channel Pointer to the PPI channel that has been allocated. * * @retval NRFX_SUCCESS The channel was successfully allocated. @@ -91,6 +98,11 @@ nrfx_err_t nrfx_ppi_channel_alloc(nrf_ppi_channel_t * p_channel); * @brief Function for freeing a PPI channel. * @details This function also disables the chosen channel. * + * @note To ensure the thread safety of the operation, this function uses the + * @ref NRFX_CRITICAL_SECTION_ENTER and @ref NRFX_CRITICAL_SECTION_EXIT + * macros. No further synchronization mechanism is needed, provided the + * macros are properly implemented (see @ref nrfx_glue). + * * @param[in] channel PPI channel to be freed. * * @retval NRFX_SUCCESS The channel was successfully freed. @@ -149,6 +161,11 @@ nrfx_err_t nrfx_ppi_channel_disable(nrf_ppi_channel_t channel); * @brief Function for allocating a PPI channel group. * @details This function allocates the first unused PPI group. * + * @note To ensure the thread safety of the operation, this function uses the + * @ref NRFX_CRITICAL_SECTION_ENTER and @ref NRFX_CRITICAL_SECTION_EXIT + * macros. No further synchronization mechanism is needed, provided the + * macros are properly implemented (see @ref nrfx_glue). + * * @param[out] p_group Pointer to the PPI channel group that has been allocated. * * @retval NRFX_SUCCESS The channel group was successfully allocated. @@ -160,6 +177,11 @@ nrfx_err_t nrfx_ppi_group_alloc(nrf_ppi_channel_group_t * p_group); * @brief Function for freeing a PPI channel group. * @details This function also disables the chosen group. * + * @note To ensure the thread safety of the operation, this function uses the + * @ref NRFX_CRITICAL_SECTION_ENTER and @ref NRFX_CRITICAL_SECTION_EXIT + * macros. No further synchronization mechanism is needed, provided the + * macros are properly implemented (see @ref nrfx_glue). + * * @param[in] group PPI channel group to be freed. * * @retval NRFX_SUCCESS The channel group was successfully freed. diff --git a/drivers/include/nrfx_pwm.h b/drivers/include/nrfx_pwm.h index a48124edaf..0b3d43b721 100644 --- a/drivers/include/nrfx_pwm.h +++ b/drivers/include/nrfx_pwm.h @@ -1,7 +1,9 @@ /* - * Copyright (c) 2015 - 2020, Nordic Semiconductor ASA + * Copyright (c) 2015 - 2021, Nordic Semiconductor ASA * All rights reserved. * + * SPDX-License-Identifier: BSD-3-Clause + * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * diff --git a/drivers/include/nrfx_qdec.h b/drivers/include/nrfx_qdec.h index 0ac342f543..d1c61a4ee3 100644 --- a/drivers/include/nrfx_qdec.h +++ b/drivers/include/nrfx_qdec.h @@ -1,7 +1,9 @@ /* - * Copyright (c) 2015 - 2020, Nordic Semiconductor ASA + * Copyright (c) 2015 - 2021, Nordic Semiconductor ASA * All rights reserved. * + * SPDX-License-Identifier: BSD-3-Clause + * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * diff --git a/drivers/include/nrfx_qspi.h b/drivers/include/nrfx_qspi.h index fb48d0dd87..f82e36b062 100644 --- a/drivers/include/nrfx_qspi.h +++ b/drivers/include/nrfx_qspi.h @@ -1,7 +1,9 @@ /* - * Copyright (c) 2016 - 2020, Nordic Semiconductor ASA + * Copyright (c) 2016 - 2021, Nordic Semiconductor ASA * All rights reserved. * + * SPDX-License-Identifier: BSD-3-Clause + * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * @@ -124,6 +126,44 @@ typedef enum NRFX_QSPI_EVENT_DONE, /**< Transfer done. */ } nrfx_qspi_evt_t; +/** + * @brief QSPI master driver extended event types, + * obtained using @ref nrfx_qspi_event_extended_get() function. + */ +typedef enum +{ + NRFX_QSPI_EVENT_NONE, /**< No event occurence. */ + NRFX_QSPI_EVENT_WRITE_DONE, /**< Write done. */ + NRFX_QSPI_EVENT_READ_DONE, /**< Read done. */ + NRFX_QSPI_EVENT_ERASE_DONE, /**< Erase done. */ +} nrfx_qspi_evt_ext_type_t; + +/** @brief QSPI driver erase event data. */ +typedef struct +{ + uint32_t addr; /**< Erase start address. */ + nrf_qspi_erase_len_t len; /**< Erase length. */ +} nrfx_qspi_evt_ext_erase_t; + +/** @brief QSPI driver transfer event data. */ +typedef struct +{ + void * p_buffer; /**< Pointer to the data buffer associated with transfer. */ + size_t size; /**< Data buffer size. */ + uint32_t addr; /**< Transfer start address. */ +} nrfx_qspi_evt_ext_xfer_t; + +/** @brief QSPI driver extended event structure. */ +typedef struct +{ + nrfx_qspi_evt_ext_type_t type; ///< Extended event type. + union + { + nrfx_qspi_evt_ext_xfer_t xfer; ///< Data for write or read transfer event. + nrfx_qspi_evt_ext_erase_t erase; ///< Data for erase event. + } data; ///< Union to store event data. +} nrfx_qspi_evt_ext_t; + /** @brief QSPI driver event handler type. */ typedef void (*nrfx_qspi_handler_t)(nrfx_qspi_evt_t event, void * p_context); @@ -147,6 +187,10 @@ typedef void (*nrfx_qspi_handler_t)(nrfx_qspi_evt_t event, void * p_context); * will be performed in blocking mode. * @param[in] p_context Pointer to context. Use in the interrupt handler. * + * @warning On nRF5340, only the dedicated pins with @ref NRF_GPIO_PIN_MCUSEL_PERIPHERAL configuration + * are supported. See the chapter Pin assignments + * in the Product Specification. + * * @retval NRFX_SUCCESS Initialization was successful. * @retval NRFX_ERROR_TIMEOUT The peripheral cannot connect with external memory. * @retval NRFX_ERROR_INVALID_STATE The driver was already initialized. @@ -168,6 +212,9 @@ void nrfx_qspi_uninit(void); * until the operation data is being read. * - interrupt mode (with handler) - event emission occurs after the last operation * and reading of data are finished. + * In interrupt mode read operations can be double-buffered by calling the function again. + * To utilize double-buffering feature, @ref NRF_QSPI_TASK_READSTART needs to be triggered + * on @ref NRF_QSPI_EVENT_READY externally (for example by using the PPI/DPPI). * * @param[out] p_rx_buffer Pointer to the receive buffer. * @param[in] rx_buffer_length Size of the data to read. @@ -194,8 +241,11 @@ nrfx_err_t nrfx_qspi_read(void * p_rx_buffer, * and sending of operation data are finished. * To manually control operation execution in the memory device, use @ref nrfx_qspi_mem_busy_check * after executing the write function. - * Remember that an incoming event signalizes only that data was sent to the memory device and the periheral + * Remember that an incoming event signalizes only that data was sent to the memory device and the peripheral * before the write operation checked if memory was busy. + * In interrupt mode write operations can be double-buffered by calling the function again. + * To utilize double-buffering feature, @ref NRF_QSPI_TASK_WRITESTART needs to be triggered + * on @ref NRF_QSPI_EVENT_READY externally (for example by using the PPI/DPPI). * * @param[in] p_tx_buffer Pointer to the writing buffer. * @param[in] tx_buffer_length Size of the data to write. @@ -246,6 +296,23 @@ nrfx_err_t nrfx_qspi_erase(nrf_qspi_erase_len_t length, */ nrfx_err_t nrfx_qspi_chip_erase(void); +/** + * @brief Function for getting the extended event associated with finished operation. + * + * @warning This function shall be used only in the context of event handler + passed by the user during driver initialization. + * + * @return Pointer to the extended event associated with finished operation. + */ +nrfx_qspi_evt_ext_t const * nrfx_qspi_event_extended_get(void); + +/** + * @brief Function for checking whether any write or read data transfer is buffered. + * + * @return True if there is a transfer buffered, false otherwise. + */ +bool nrfx_qspi_xfer_buffered_check(void); + /** * @brief Function for getting the current driver status and status byte of memory device with * testing WIP (write in progress) bit. diff --git a/drivers/include/nrfx_rng.h b/drivers/include/nrfx_rng.h index ed9c70c73b..fc52514b79 100644 --- a/drivers/include/nrfx_rng.h +++ b/drivers/include/nrfx_rng.h @@ -1,7 +1,9 @@ /* - * Copyright (c) 2016 - 2020, Nordic Semiconductor ASA + * Copyright (c) 2016 - 2021, Nordic Semiconductor ASA * All rights reserved. * + * SPDX-License-Identifier: BSD-3-Clause + * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * diff --git a/drivers/include/nrfx_rtc.h b/drivers/include/nrfx_rtc.h index 93cabe35e5..de6339b86b 100644 --- a/drivers/include/nrfx_rtc.h +++ b/drivers/include/nrfx_rtc.h @@ -1,7 +1,9 @@ /* - * Copyright (c) 2014 - 2020, Nordic Semiconductor ASA + * Copyright (c) 2014 - 2021, Nordic Semiconductor ASA * All rights reserved. * + * SPDX-License-Identifier: BSD-3-Clause + * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * diff --git a/drivers/include/nrfx_saadc.h b/drivers/include/nrfx_saadc.h index bf1f78fc80..b7f34574fe 100644 --- a/drivers/include/nrfx_saadc.h +++ b/drivers/include/nrfx_saadc.h @@ -1,7 +1,9 @@ /* - * Copyright (c) 2015 - 2020, Nordic Semiconductor ASA + * Copyright (c) 2015 - 2021, Nordic Semiconductor ASA * All rights reserved. * + * SPDX-License-Identifier: BSD-3-Clause + * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * @@ -220,13 +222,16 @@ nrfx_err_t nrfx_saadc_init(uint8_t interrupt_priority); void nrfx_saadc_uninit(void); /** - * @brief Function for configuring the SAADC channels. + * @brief Function for configuring multiple SAADC channels. * * @note The values of the @ref nrf_saadc_channel_config_t.burst fields in channel configurations * are ignored. They will be overridden with the value suitable for the selected driver * operation mode. * @note The desired mode (simple or advanced) must be set after the channels are configured. * + * @warning This function overrides previous configuration done on any channel by + * @ref nrfx_saadc_channels_config or @ref nrfx_saadc_channel_config. + * * @param[in] p_channels Pointer to the array of channel configuration structures. * @param[in] channel_count Number of channels to be configured. * @@ -237,6 +242,33 @@ void nrfx_saadc_uninit(void); nrfx_err_t nrfx_saadc_channels_config(nrfx_saadc_channel_t const * p_channels, uint32_t channel_count); +/** + * @brief Function for configuring single SAADC channel. + * + * @note The values of the @ref nrf_saadc_channel_config_t.burst fields in channel configurations + * are ignored. They will be overridden with the value suitable for the selected driver + * operation mode. + * + * @warning This function overrides previous configuration done on specified channel by + * @ref nrfx_saadc_channels_config or @ref nrfx_saadc_channel_config. + * + * @param[in] p_channel Pointer to the channel configuration structure. + * + * @retval NRFX_SUCCESS Configuration was successful. + * @retval NRFX_ERROR_BUSY There is a conversion or calibration ongoing. + */ +nrfx_err_t nrfx_saadc_channel_config(nrfx_saadc_channel_t const * p_channel); + +/** + * @brief Function for deconfiguring the specified SAADC channels. + * + * @param[in] channel_mask Bitmask of channels to be deconfigured. + * + * @retval NRFX_SUCCESS Deconfiguration was successful. + * @retval NRFX_ERROR_BUSY There is a conversion or calibration ongoing. + */ +nrfx_err_t nrfx_saadc_channels_deconfig(uint32_t channel_mask); + /** * @brief Function for setting the SAADC driver in the simple mode. * diff --git a/drivers/include/nrfx_spi.h b/drivers/include/nrfx_spi.h index 80fab90864..155c99fed1 100644 --- a/drivers/include/nrfx_spi.h +++ b/drivers/include/nrfx_spi.h @@ -1,7 +1,9 @@ /* - * Copyright (c) 2015 - 2020, Nordic Semiconductor ASA + * Copyright (c) 2015 - 2021, Nordic Semiconductor ASA * All rights reserved. * + * SPDX-License-Identifier: BSD-3-Clause + * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * diff --git a/drivers/include/nrfx_spim.h b/drivers/include/nrfx_spim.h index ba2cdbe302..51cf5a8804 100644 --- a/drivers/include/nrfx_spim.h +++ b/drivers/include/nrfx_spim.h @@ -1,7 +1,9 @@ /* - * Copyright (c) 2015 - 2020, Nordic Semiconductor ASA + * Copyright (c) 2015 - 2021, Nordic Semiconductor ASA * All rights reserved. * + * SPDX-License-Identifier: BSD-3-Clause + * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * @@ -254,6 +256,10 @@ typedef void (* nrfx_spim_evt_handler_t)(nrfx_spim_evt_t const * p_event, * will be performed in blocking mode. * @param[in] p_context Context passed to event handler. * + * @warning On nRF5340, 32 MHz setting for SPIM4 peripheral instance is supported + * only on the dedicated pins with @ref NRF_GPIO_PIN_MCUSEL_PERIPHERAL configuration. + * See the chapter Pin assignments in the Product Specification. + * * @retval NRFX_SUCCESS Initialization was successful. * @retval NRFX_ERROR_INVALID_STATE The driver was already initialized. * @retval NRFX_ERROR_BUSY Some other peripheral with the same @@ -262,6 +268,7 @@ typedef void (* nrfx_spim_evt_handler_t)(nrfx_spim_evt_t const * p_event, * is enabled. * @retval NRFX_ERROR_NOT_SUPPORTED Requested configuration is not supported * by the SPIM instance. + * @retval NRFX_ERROR_INVALID_PARAM Requested frequency is not available on the specified pins. */ nrfx_err_t nrfx_spim_init(nrfx_spim_t const * p_instance, nrfx_spim_config_t const * p_config, diff --git a/drivers/include/nrfx_spis.h b/drivers/include/nrfx_spis.h index 9c92503352..3bd618382b 100644 --- a/drivers/include/nrfx_spis.h +++ b/drivers/include/nrfx_spis.h @@ -1,7 +1,9 @@ /* - * Copyright (c) 2015 - 2020, Nordic Semiconductor ASA + * Copyright (c) 2015 - 2021, Nordic Semiconductor ASA * All rights reserved. * + * SPDX-License-Identifier: BSD-3-Clause + * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * diff --git a/drivers/include/nrfx_systick.h b/drivers/include/nrfx_systick.h index 0d1b9e194c..1568ef30f6 100644 --- a/drivers/include/nrfx_systick.h +++ b/drivers/include/nrfx_systick.h @@ -1,7 +1,9 @@ /* - * Copyright (c) 2016 - 2020, Nordic Semiconductor ASA + * Copyright (c) 2016 - 2021, Nordic Semiconductor ASA * All rights reserved. * + * SPDX-License-Identifier: BSD-3-Clause + * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * diff --git a/drivers/include/nrfx_temp.h b/drivers/include/nrfx_temp.h index 17d962fbfa..09a780d016 100644 --- a/drivers/include/nrfx_temp.h +++ b/drivers/include/nrfx_temp.h @@ -1,7 +1,9 @@ /* - * Copyright (c) 2019 - 2020, Nordic Semiconductor ASA + * Copyright (c) 2019 - 2021, Nordic Semiconductor ASA * All rights reserved. * + * SPDX-License-Identifier: BSD-3-Clause + * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * diff --git a/drivers/include/nrfx_timer.h b/drivers/include/nrfx_timer.h index 3fcbbbbdd4..e79da2b01a 100644 --- a/drivers/include/nrfx_timer.h +++ b/drivers/include/nrfx_timer.h @@ -1,7 +1,9 @@ /* - * Copyright (c) 2015 - 2020, Nordic Semiconductor ASA + * Copyright (c) 2015 - 2021, Nordic Semiconductor ASA * All rights reserved. * + * SPDX-License-Identifier: BSD-3-Clause + * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * diff --git a/drivers/include/nrfx_twi.h b/drivers/include/nrfx_twi.h index 3595a6eab3..b754cac6d6 100644 --- a/drivers/include/nrfx_twi.h +++ b/drivers/include/nrfx_twi.h @@ -1,7 +1,9 @@ /* - * Copyright (c) 2015 - 2020, Nordic Semiconductor ASA + * Copyright (c) 2015 - 2021, Nordic Semiconductor ASA * All rights reserved. * + * SPDX-License-Identifier: BSD-3-Clause + * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * diff --git a/drivers/include/nrfx_twi_twim.h b/drivers/include/nrfx_twi_twim.h index 1f62c62d50..f10a330078 100644 --- a/drivers/include/nrfx_twi_twim.h +++ b/drivers/include/nrfx_twi_twim.h @@ -1,7 +1,9 @@ /* - * Copyright (c) 2019 - 2020, Nordic Semiconductor ASA + * Copyright (c) 2019 - 2021, Nordic Semiconductor ASA * All rights reserved. * + * SPDX-License-Identifier: BSD-3-Clause + * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * diff --git a/drivers/include/nrfx_twim.h b/drivers/include/nrfx_twim.h index 94ba0802bd..2976fab86c 100644 --- a/drivers/include/nrfx_twim.h +++ b/drivers/include/nrfx_twim.h @@ -1,7 +1,9 @@ /* - * Copyright (c) 2015 - 2020, Nordic Semiconductor ASA + * Copyright (c) 2015 - 2021, Nordic Semiconductor ASA * All rights reserved. * + * SPDX-License-Identifier: BSD-3-Clause + * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * @@ -217,8 +219,12 @@ typedef void (* nrfx_twim_evt_handler_t)(nrfx_twim_evt_t const * p_event, * @param[in] event_handler Event handler provided by the user. If NULL, blocking mode is enabled. * @param[in] p_context Context passed to event handler. * + * @warning On nRF5340, 1 MHz setting is supported only on the dedicated pins. See the chapter + * Pin assignments in the Product Specification. + * * @retval NRFX_SUCCESS Initialization was successful. * @retval NRFX_ERROR_INVALID_STATE The driver is in invalid state. + * @retval NRFX_ERROR_INVALID_PARAM Requested frequency is not available on the specified pins. * @retval NRFX_ERROR_BUSY Some other peripheral with the same * instance ID is already in use. This is * possible only if @ref nrfx_prs module diff --git a/drivers/include/nrfx_twis.h b/drivers/include/nrfx_twis.h index cc59c2e704..69782dc687 100644 --- a/drivers/include/nrfx_twis.h +++ b/drivers/include/nrfx_twis.h @@ -1,7 +1,9 @@ /* - * Copyright (c) 2015 - 2020, Nordic Semiconductor ASA + * Copyright (c) 2015 - 2021, Nordic Semiconductor ASA * All rights reserved. * + * SPDX-License-Identifier: BSD-3-Clause + * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * diff --git a/drivers/include/nrfx_uart.h b/drivers/include/nrfx_uart.h index 5cd19be434..3bd673b3b6 100644 --- a/drivers/include/nrfx_uart.h +++ b/drivers/include/nrfx_uart.h @@ -1,7 +1,9 @@ /* - * Copyright (c) 2015 - 2020, Nordic Semiconductor ASA + * Copyright (c) 2015 - 2021, Nordic Semiconductor ASA * All rights reserved. * + * SPDX-License-Identifier: BSD-3-Clause + * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * diff --git a/drivers/include/nrfx_uarte.h b/drivers/include/nrfx_uarte.h index 6346695ab9..fe6238866b 100644 --- a/drivers/include/nrfx_uarte.h +++ b/drivers/include/nrfx_uarte.h @@ -1,7 +1,9 @@ /* - * Copyright (c) 2015 - 2020, Nordic Semiconductor ASA + * Copyright (c) 2015 - 2021, Nordic Semiconductor ASA * All rights reserved. * + * SPDX-License-Identifier: BSD-3-Clause + * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * diff --git a/drivers/include/nrfx_usbd.h b/drivers/include/nrfx_usbd.h index a8e36c6d2d..26db0a47a0 100644 --- a/drivers/include/nrfx_usbd.h +++ b/drivers/include/nrfx_usbd.h @@ -1,7 +1,9 @@ /* - * Copyright (c) 2016 - 2020, Nordic Semiconductor ASA + * Copyright (c) 2016 - 2021, Nordic Semiconductor ASA * All rights reserved. * + * SPDX-License-Identifier: BSD-3-Clause + * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * @@ -60,7 +62,7 @@ extern "C" { * @sa nrf_usbd_isosplit_set * @sa nrf_usbd_isosplit_get */ -#define NRFX_USBD_ISOSIZE 1024 +#define NRFX_USBD_ISOSIZE 1023 /** * @brief The size of internal feeder buffer. diff --git a/drivers/include/nrfx_usbreg.h b/drivers/include/nrfx_usbreg.h index a9a67d0e59..4405dbdcfa 100644 --- a/drivers/include/nrfx_usbreg.h +++ b/drivers/include/nrfx_usbreg.h @@ -1,7 +1,9 @@ /* - * Copyright (c) 2019 - 2020, Nordic Semiconductor ASA + * Copyright (c) 2019 - 2021, Nordic Semiconductor ASA * All rights reserved. * + * SPDX-License-Identifier: BSD-3-Clause + * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * diff --git a/drivers/include/nrfx_wdt.h b/drivers/include/nrfx_wdt.h index 9866c29d49..9e9fc1580e 100644 --- a/drivers/include/nrfx_wdt.h +++ b/drivers/include/nrfx_wdt.h @@ -1,7 +1,9 @@ /* - * Copyright (c) 2014 - 2020, Nordic Semiconductor ASA + * Copyright (c) 2014 - 2021, Nordic Semiconductor ASA * All rights reserved. * + * SPDX-License-Identifier: BSD-3-Clause + * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * diff --git a/drivers/nrfx_common.h b/drivers/nrfx_common.h index 50ce150fce..b6d86ca3cf 100644 --- a/drivers/nrfx_common.h +++ b/drivers/nrfx_common.h @@ -1,7 +1,9 @@ /* - * Copyright (c) 2017 - 2020, Nordic Semiconductor ASA + * Copyright (c) 2017 - 2021, Nordic Semiconductor ASA * All rights reserved. * + * SPDX-License-Identifier: BSD-3-Clause + * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * diff --git a/drivers/nrfx_errors.h b/drivers/nrfx_errors.h index be360f7771..26f3f4a20b 100644 --- a/drivers/nrfx_errors.h +++ b/drivers/nrfx_errors.h @@ -1,7 +1,9 @@ /* - * Copyright (c) 2017 - 2020, Nordic Semiconductor ASA + * Copyright (c) 2017 - 2021, Nordic Semiconductor ASA * All rights reserved. * + * SPDX-License-Identifier: BSD-3-Clause + * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * diff --git a/drivers/src/nrfx_adc.c b/drivers/src/nrfx_adc.c index 512857ec55..b63724ced0 100644 --- a/drivers/src/nrfx_adc.c +++ b/drivers/src/nrfx_adc.c @@ -1,7 +1,9 @@ /* - * Copyright (c) 2015 - 2020, Nordic Semiconductor ASA + * Copyright (c) 2015 - 2021, Nordic Semiconductor ASA * All rights reserved. * + * SPDX-License-Identifier: BSD-3-Clause + * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * diff --git a/drivers/src/nrfx_clock.c b/drivers/src/nrfx_clock.c index 1d084be65f..26ffc1bb39 100644 --- a/drivers/src/nrfx_clock.c +++ b/drivers/src/nrfx_clock.c @@ -1,7 +1,9 @@ /* - * Copyright (c) 2016 - 2020, Nordic Semiconductor ASA + * Copyright (c) 2016 - 2021, Nordic Semiconductor ASA * All rights reserved. * + * SPDX-License-Identifier: BSD-3-Clause + * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * @@ -449,13 +451,13 @@ void nrfx_clock_calibration_timer_stop(void) #endif } -#if NRF_CLOCK_HAS_HFCLK_DIV || NRF_CLOCK_HAS_HFCLK192M +#if defined(CLOCK_FEATURE_HFCLK_DIVIDE_PRESENT) || NRF_CLOCK_HAS_HFCLK192M nrfx_err_t nrfx_clock_divider_set(nrf_clock_domain_t domain, nrf_clock_hfclk_div_t div) { switch(domain) { -#if NRF_CLOCK_HAS_HFCLK_DIV +#if defined(CLOCK_FEATURE_HFCLK_DIVIDE_PRESENT) case NRF_CLOCK_DOMAIN_HFCLK: switch (div) { diff --git a/drivers/src/nrfx_comp.c b/drivers/src/nrfx_comp.c index 8420577f3f..fb471007a8 100644 --- a/drivers/src/nrfx_comp.c +++ b/drivers/src/nrfx_comp.c @@ -1,7 +1,9 @@ /* - * Copyright (c) 2015 - 2020, Nordic Semiconductor ASA + * Copyright (c) 2015 - 2021, Nordic Semiconductor ASA * All rights reserved. * + * SPDX-License-Identifier: BSD-3-Clause + * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * @@ -99,15 +101,6 @@ nrfx_err_t nrfx_comp_init(nrfx_comp_config_t const * p_config, } #endif - nrf_comp_task_trigger(NRF_COMP, NRF_COMP_TASK_STOP); - nrf_comp_enable(NRF_COMP); - - // Clear events to be sure there are no leftovers. - nrf_comp_event_clear(NRF_COMP, NRF_COMP_EVENT_READY); - nrf_comp_event_clear(NRF_COMP, NRF_COMP_EVENT_DOWN); - nrf_comp_event_clear(NRF_COMP, NRF_COMP_EVENT_UP); - nrf_comp_event_clear(NRF_COMP, NRF_COMP_EVENT_CROSS); - nrf_comp_ref_set(NRF_COMP, p_config->reference); //If external source is chosen, write to appropriate register. @@ -133,6 +126,16 @@ nrfx_err_t nrfx_comp_init(nrfx_comp_config_t const * p_config, nrf_comp_input_select(NRF_COMP, p_config->input); + nrf_comp_enable(NRF_COMP); + + nrf_comp_task_trigger(NRF_COMP, NRF_COMP_TASK_STOP); + + // Clear events to be sure there are no leftovers. + nrf_comp_event_clear(NRF_COMP, NRF_COMP_EVENT_READY); + nrf_comp_event_clear(NRF_COMP, NRF_COMP_EVENT_DOWN); + nrf_comp_event_clear(NRF_COMP, NRF_COMP_EVENT_UP); + nrf_comp_event_clear(NRF_COMP, NRF_COMP_EVENT_CROSS); + NRFX_IRQ_PRIORITY_SET(nrfx_get_irq_number(NRF_COMP), p_config->interrupt_priority); NRFX_IRQ_ENABLE(nrfx_get_irq_number(NRF_COMP)); diff --git a/drivers/src/nrfx_dppi.c b/drivers/src/nrfx_dppi.c index f4727f69bc..efefb9e505 100644 --- a/drivers/src/nrfx_dppi.c +++ b/drivers/src/nrfx_dppi.c @@ -1,7 +1,9 @@ /* - * Copyright (c) 2018 - 2020, Nordic Semiconductor ASA + * Copyright (c) 2018 - 2021, Nordic Semiconductor ASA * All rights reserved. * + * SPDX-License-Identifier: BSD-3-Clause + * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * @@ -102,6 +104,7 @@ nrfx_err_t nrfx_dppi_channel_alloc(uint8_t * p_channel) { nrfx_err_t err_code; + NRFX_CRITICAL_SECTION_ENTER(); // Get mask of available DPPI channels uint32_t remaining_channels = DPPI_AVAILABLE_CHANNELS_MASK & ~(m_allocated_channels); uint8_t channel = 0; @@ -109,21 +112,32 @@ nrfx_err_t nrfx_dppi_channel_alloc(uint8_t * p_channel) if (!remaining_channels) { err_code = NRFX_ERROR_NO_MEM; - NRFX_LOG_INFO("Function: %s, error code: %s.", __func__, NRFX_LOG_ERROR_STRING_GET(err_code)); - return err_code; } - - // Find first free channel - while (!(remaining_channels & DPPI_BIT_SET(channel))) + else { - channel++; - } + // Find first free channel + while (!(remaining_channels & DPPI_BIT_SET(channel))) + { + channel++; + } - m_allocated_channels |= DPPI_BIT_SET(channel); - *p_channel = channel; + m_allocated_channels |= DPPI_BIT_SET(channel); + *p_channel = channel; - err_code = NRFX_SUCCESS; - NRFX_LOG_INFO("Allocated channel: %d.", channel); + err_code = NRFX_SUCCESS; + } + NRFX_CRITICAL_SECTION_EXIT(); + + if (err_code == NRFX_SUCCESS) + { + NRFX_LOG_INFO("Allocated channel: %d.", channel); + } + else + { + NRFX_LOG_INFO("Function: %s, error code: %s.", + __func__, + NRFX_LOG_ERROR_STRING_GET(err_code)); + } return err_code; } @@ -131,6 +145,7 @@ nrfx_err_t nrfx_dppi_channel_free(uint8_t channel) { nrfx_err_t err_code = NRFX_SUCCESS; + NRFX_CRITICAL_SECTION_ENTER(); if (!channel_is_allocated(channel)) { err_code = NRFX_ERROR_INVALID_PARAM; @@ -142,6 +157,7 @@ nrfx_err_t nrfx_dppi_channel_free(uint8_t channel) // Clear channel allocated indication. m_allocated_channels &= ~DPPI_BIT_SET(channel); } + NRFX_CRITICAL_SECTION_EXIT(); NRFX_LOG_INFO("Function: %s, error code: %s.", __func__, NRFX_LOG_ERROR_STRING_GET(err_code)); return err_code; } @@ -183,6 +199,7 @@ nrfx_err_t nrfx_dppi_group_alloc(nrf_dppi_channel_group_t * p_group) { nrfx_err_t err_code; + NRFX_CRITICAL_SECTION_ENTER(); // Get mask of available DPPI groups uint32_t remaining_groups = DPPI_AVAILABLE_GROUPS_MASK & ~(m_allocated_groups); uint8_t group_idx = NRF_DPPI_CHANNEL_GROUP0; @@ -190,22 +207,33 @@ nrfx_err_t nrfx_dppi_group_alloc(nrf_dppi_channel_group_t * p_group) if (!remaining_groups) { err_code = NRFX_ERROR_NO_MEM; - NRFX_LOG_INFO("Function: %s, error code: %s.", __func__, NRFX_LOG_ERROR_STRING_GET(err_code)); - return err_code; } - - // Find first free group - while (!(remaining_groups & DPPI_BIT_SET((nrf_dppi_channel_group_t)group_idx))) + else { - group_idx++; - } + // Find first free group + while (!(remaining_groups & DPPI_BIT_SET((nrf_dppi_channel_group_t)group_idx))) + { + group_idx++; + } + + nrf_dppi_channel_group_t group = (nrf_dppi_channel_group_t)group_idx; + m_allocated_groups |= DPPI_BIT_SET(group); + *p_group = group; - nrf_dppi_channel_group_t group = (nrf_dppi_channel_group_t)group_idx; - m_allocated_groups |= DPPI_BIT_SET(group); - *p_group = group; + err_code = NRFX_SUCCESS; + } + NRFX_CRITICAL_SECTION_EXIT(); - err_code = NRFX_SUCCESS; - NRFX_LOG_INFO("Allocated channel: %d.", group); + if (err_code == NRFX_SUCCESS) + { + NRFX_LOG_INFO("Allocated channel: %d.", *p_group); + } + else + { + NRFX_LOG_INFO("Function: %s, error code: %s.", + __func__, + NRFX_LOG_ERROR_STRING_GET(err_code)); + } return err_code; } @@ -213,6 +241,7 @@ nrfx_err_t nrfx_dppi_group_free(nrf_dppi_channel_group_t group) { nrfx_err_t err_code = NRFX_SUCCESS; + NRFX_CRITICAL_SECTION_ENTER(); if (!group_is_allocated(group)) { err_code = NRFX_ERROR_INVALID_PARAM; @@ -223,6 +252,7 @@ nrfx_err_t nrfx_dppi_group_free(nrf_dppi_channel_group_t group) // Set bit value to zero at position corresponding to the group number. m_allocated_groups &= ~DPPI_BIT_SET(group); } + NRFX_CRITICAL_SECTION_EXIT(); NRFX_LOG_INFO("Function: %s, error code: %s.", __func__, NRFX_LOG_ERROR_STRING_GET(err_code)); return err_code; } @@ -238,7 +268,9 @@ nrfx_err_t nrfx_dppi_channel_include_in_group(uint8_t channel, } else { + NRFX_CRITICAL_SECTION_ENTER(); nrf_dppi_channels_include_in_group(NRF_DPPIC, DPPI_BIT_SET(channel), group); + NRFX_CRITICAL_SECTION_EXIT(); } NRFX_LOG_INFO("Function: %s, error code: %s.", __func__, NRFX_LOG_ERROR_STRING_GET(err_code)); return err_code; @@ -255,7 +287,9 @@ nrfx_err_t nrfx_dppi_channel_remove_from_group(uint8_t channel, } else { + NRFX_CRITICAL_SECTION_ENTER(); nrf_dppi_channels_remove_from_group(NRF_DPPIC, DPPI_BIT_SET(channel), group); + NRFX_CRITICAL_SECTION_EXIT(); } NRFX_LOG_INFO("Function: %s, error code: %s.", __func__, NRFX_LOG_ERROR_STRING_GET(err_code)); return err_code; diff --git a/drivers/src/nrfx_egu.c b/drivers/src/nrfx_egu.c index 07fccaf3ed..8a8f4f783b 100644 --- a/drivers/src/nrfx_egu.c +++ b/drivers/src/nrfx_egu.c @@ -1,7 +1,9 @@ /* - * Copyright (c) 2019 - 2020, Nordic Semiconductor ASA + * Copyright (c) 2019 - 2021, Nordic Semiconductor ASA * All rights reserved. * + * SPDX-License-Identifier: BSD-3-Clause + * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * diff --git a/drivers/src/nrfx_gpiote.c b/drivers/src/nrfx_gpiote.c index 9baa4742d7..babd2106a1 100644 --- a/drivers/src/nrfx_gpiote.c +++ b/drivers/src/nrfx_gpiote.c @@ -1,7 +1,9 @@ /* - * Copyright (c) 2015 - 2020, Nordic Semiconductor ASA + * Copyright (c) 2015 - 2021, Nordic Semiconductor ASA * All rights reserved. * + * SPDX-License-Identifier: BSD-3-Clause + * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * @@ -258,7 +260,11 @@ nrfx_err_t nrfx_gpiote_init(uint8_t interrupt_priority) for (i = 0; i < (GPIOTE_CH_NUM + NRFX_GPIOTE_CONFIG_NUM_OF_LOW_POWER_EVENTS); i++) { - channel_free(i); + m_cb.handlers[i] = UNALLOCATED_HANDLER_ADDRESS; + if (i >= GPIOTE_CH_NUM) + { + m_cb.port_handlers_pins[i - GPIOTE_CH_NUM] = (int8_t)PIN_NOT_USED; + } } memset(m_cb.configured_pins, 0, sizeof(m_cb.configured_pins)); @@ -813,7 +819,10 @@ void nrfx_gpiote_in_uninit(nrfx_gpiote_pin_t pin) nrf_gpio_cfg_default(pin); pin_configured_clear(pin); } - channel_free((uint8_t)channel_port_get(pin)); + if (pin_in_use_by_gpiote(pin)) + { + channel_free((uint8_t)channel_port_get(pin)); + } pin_in_use_clear(pin); } diff --git a/drivers/src/nrfx_i2s.c b/drivers/src/nrfx_i2s.c index b58ebb555e..24108251e8 100644 --- a/drivers/src/nrfx_i2s.c +++ b/drivers/src/nrfx_i2s.c @@ -1,7 +1,9 @@ /* - * Copyright (c) 2015 - 2020, Nordic Semiconductor ASA + * Copyright (c) 2015 - 2021, Nordic Semiconductor ASA * All rights reserved. * + * SPDX-License-Identifier: BSD-3-Clause + * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * diff --git a/drivers/src/nrfx_ipc.c b/drivers/src/nrfx_ipc.c index f47b70ccc4..c6b91545e5 100644 --- a/drivers/src/nrfx_ipc.c +++ b/drivers/src/nrfx_ipc.c @@ -1,7 +1,9 @@ /* - * Copyright (c) 2019 - 2020, Nordic Semiconductor ASA + * Copyright (c) 2019 - 2021, Nordic Semiconductor ASA * All rights reserved. * + * SPDX-License-Identifier: BSD-3-Clause + * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * diff --git a/drivers/src/nrfx_lpcomp.c b/drivers/src/nrfx_lpcomp.c index 72ef20ac23..cb526a9fa4 100644 --- a/drivers/src/nrfx_lpcomp.c +++ b/drivers/src/nrfx_lpcomp.c @@ -1,7 +1,9 @@ /* - * Copyright (c) 2015 - 2020, Nordic Semiconductor ASA + * Copyright (c) 2015 - 2021, Nordic Semiconductor ASA * All rights reserved. * + * SPDX-License-Identifier: BSD-3-Clause + * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * diff --git a/drivers/src/nrfx_nfct.c b/drivers/src/nrfx_nfct.c index 75e01486bd..c31062096e 100644 --- a/drivers/src/nrfx_nfct.c +++ b/drivers/src/nrfx_nfct.c @@ -1,7 +1,9 @@ /* - * Copyright (c) 2018 - 2020, Nordic Semiconductor ASA + * Copyright (c) 2018 - 2021, Nordic Semiconductor ASA * All rights reserved. * + * SPDX-License-Identifier: BSD-3-Clause + * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * diff --git a/drivers/src/nrfx_nvmc.c b/drivers/src/nrfx_nvmc.c index 85027d7adb..53a4c2ea45 100644 --- a/drivers/src/nrfx_nvmc.c +++ b/drivers/src/nrfx_nvmc.c @@ -1,7 +1,9 @@ /* - * Copyright (c) 2019 - 2020, Nordic Semiconductor ASA + * Copyright (c) 2019 - 2021, Nordic Semiconductor ASA * All rights reserved. * + * SPDX-License-Identifier: BSD-3-Clause + * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * diff --git a/drivers/src/nrfx_pdm.c b/drivers/src/nrfx_pdm.c index f571f9898b..d76d45a6ff 100644 --- a/drivers/src/nrfx_pdm.c +++ b/drivers/src/nrfx_pdm.c @@ -1,7 +1,9 @@ /* - * Copyright (c) 2015 - 2020, Nordic Semiconductor ASA + * Copyright (c) 2015 - 2021, Nordic Semiconductor ASA * All rights reserved. * + * SPDX-License-Identifier: BSD-3-Clause + * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * diff --git a/drivers/src/nrfx_power.c b/drivers/src/nrfx_power.c index 89b57c59be..92a4b65a46 100644 --- a/drivers/src/nrfx_power.c +++ b/drivers/src/nrfx_power.c @@ -1,7 +1,9 @@ /* - * Copyright (c) 2017 - 2020, Nordic Semiconductor ASA + * Copyright (c) 2017 - 2021, Nordic Semiconductor ASA * All rights reserved. * + * SPDX-License-Identifier: BSD-3-Clause + * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * diff --git a/drivers/src/nrfx_ppi.c b/drivers/src/nrfx_ppi.c index 3cb590ab99..547b9c6025 100644 --- a/drivers/src/nrfx_ppi.c +++ b/drivers/src/nrfx_ppi.c @@ -1,7 +1,9 @@ /* - * Copyright (c) 2015 - 2020, Nordic Semiconductor ASA + * Copyright (c) 2015 - 2021, Nordic Semiconductor ASA * All rights reserved. * + * SPDX-License-Identifier: BSD-3-Clause + * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * diff --git a/drivers/src/nrfx_pwm.c b/drivers/src/nrfx_pwm.c index a7816c6be2..c47e3b060d 100644 --- a/drivers/src/nrfx_pwm.c +++ b/drivers/src/nrfx_pwm.c @@ -1,7 +1,9 @@ /* - * Copyright (c) 2015 - 2020, Nordic Semiconductor ASA + * Copyright (c) 2015 - 2021, Nordic Semiconductor ASA * All rights reserved. * + * SPDX-License-Identifier: BSD-3-Clause + * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * diff --git a/drivers/src/nrfx_qdec.c b/drivers/src/nrfx_qdec.c index 48c50788cf..40b152d79b 100644 --- a/drivers/src/nrfx_qdec.c +++ b/drivers/src/nrfx_qdec.c @@ -1,7 +1,9 @@ /* - * Copyright (c) 2015 - 2020, Nordic Semiconductor ASA + * Copyright (c) 2015 - 2021, Nordic Semiconductor ASA * All rights reserved. * + * SPDX-License-Identifier: BSD-3-Clause + * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * diff --git a/drivers/src/nrfx_qspi.c b/drivers/src/nrfx_qspi.c index 3983e8c95e..cc49196ab2 100644 --- a/drivers/src/nrfx_qspi.c +++ b/drivers/src/nrfx_qspi.c @@ -1,7 +1,9 @@ /* - * Copyright (c) 2016 - 2020, Nordic Semiconductor ASA + * Copyright (c) 2016 - 2021, Nordic Semiconductor ASA * All rights reserved. * + * SPDX-License-Identifier: BSD-3-Clause + * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * @@ -34,6 +36,7 @@ #if NRFX_CHECK(NRFX_QSPI_ENABLED) #include +#include /** @brief Command byte used to read status register. */ #define QSPI_STD_CMD_RDSR 0x05 @@ -47,40 +50,116 @@ /** @brief Default number of tries in timeout function. */ #define QSPI_DEF_WAIT_ATTEMPTS 100 +/** + * @brief Macro for initializing a QSPI pin. + * + * QSPI peripheral expects high drive pin strength. + */ +#define QSPI_PIN_INIT(_pin) nrf_gpio_cfg((_pin), \ + NRF_GPIO_PIN_DIR_INPUT, \ + NRF_GPIO_PIN_INPUT_DISCONNECT, \ + NRF_GPIO_PIN_NOPULL, \ + NRF_GPIO_PIN_H0H1, \ + NRF_GPIO_PIN_NOSENSE) + +#if !defined(USE_WORKAROUND_FOR_ANOMALY_121) && defined(NRF53_SERIES) + // ANOMALY 121 - Configuration of QSPI peripheral requires additional steps. + #define USE_WORKAROUND_FOR_ANOMALY_121 1 +#endif + +/** @brief QSPI driver states.*/ +typedef enum +{ + NRFX_QSPI_STATE_UNINITIALIZED = 0, + NRFX_QSPI_STATE_IDLE, + NRFX_QSPI_STATE_WRITE, + NRFX_QSPI_STATE_READ, + NRFX_QSPI_STATE_ERASE, + NRFX_QSPI_STATE_CINSTR, +} nrfx_qspi_state_t; + /** @brief Control block - driver instance local data. */ typedef struct { - nrfx_qspi_handler_t handler; /**< Handler. */ - nrfx_drv_state_t state; /**< Driver state. */ - volatile bool is_busy; /**< Flag indicating that an operation is currently being performed. */ - void * p_context; /**< Driver context used in interrupt. */ + nrfx_qspi_handler_t handler; /**< Handler. */ + void * p_context; /**< Driver context used in interrupt. */ + void * p_buffer_primary; /**< Pointer to the primary buffer. */ + void * p_buffer_secondary; /**< Pointer to the secondary buffer. */ + uint32_t size_primary; /**< Size of the primary buffer. */ + uint32_t size_secondary; /**< Size of the secondary buffer. */ + uint32_t addr_primary; /**< Address for the primary buffer. */ + uint32_t addr_secondary; /**< Address for the secondary buffer. */ + nrfx_qspi_evt_ext_t evt_ext; /**< Extended event. */ + nrfx_qspi_state_t state; /**< Driver state. */ } qspi_control_block_t; static qspi_control_block_t m_cb; -static nrfx_err_t qspi_task_perform(nrf_qspi_task_t task) +static nrfx_err_t qspi_xfer(void * p_buffer, + size_t length, + uint32_t address, + nrfx_qspi_state_t desired_state) { - // Wait for peripheral - if (m_cb.is_busy) + NRFX_ASSERT(m_cb.state != NRFX_QSPI_STATE_UNINITIALIZED); + NRFX_ASSERT(p_buffer != NULL); + + if (!nrfx_is_in_ram(p_buffer) || !nrfx_is_word_aligned(p_buffer)) { - return NRFX_ERROR_BUSY; + return NRFX_ERROR_INVALID_ADDR; } - nrf_qspi_event_clear(NRF_QSPI, NRF_QSPI_EVENT_READY); + if ((m_cb.state != NRFX_QSPI_STATE_IDLE) && + (m_cb.state != desired_state)) + { + return NRFX_ERROR_BUSY; + } + bool is_first_buffer = false; if (m_cb.handler) { - m_cb.is_busy = true; - nrf_qspi_int_enable(NRF_QSPI, NRF_QSPI_INT_READY_MASK); + if (m_cb.p_buffer_primary) + { + m_cb.p_buffer_secondary = p_buffer; + m_cb.size_secondary = length; + m_cb.addr_secondary = address; + } + else + { + m_cb.p_buffer_primary = p_buffer; + m_cb.size_primary = length; + m_cb.addr_primary = address; + + m_cb.state = desired_state; + is_first_buffer = true; + } } - nrf_qspi_task_trigger(NRF_QSPI, task); + nrf_qspi_task_t task; + if (desired_state == NRFX_QSPI_STATE_WRITE) + { + nrf_qspi_write_buffer_set(NRF_QSPI, p_buffer, length, address); + task = NRF_QSPI_TASK_WRITESTART; + } + else + { + nrf_qspi_read_buffer_set(NRF_QSPI, p_buffer, length, address); + task = NRF_QSPI_TASK_READSTART; + } - if (m_cb.handler == NULL) + if (!m_cb.handler) { + nrf_qspi_event_clear(NRF_QSPI, NRF_QSPI_EVENT_READY); + nrf_qspi_task_trigger(NRF_QSPI, task); while (!nrf_qspi_event_check(NRF_QSPI, NRF_QSPI_EVENT_READY)) - {}; + {} + } + else if (is_first_buffer) + { + nrf_qspi_event_clear(NRF_QSPI, NRF_QSPI_EVENT_READY); + nrf_qspi_int_enable(NRF_QSPI, NRF_QSPI_INT_READY_MASK); + nrf_qspi_task_trigger(NRF_QSPI, task); } + return NRFX_SUCCESS; } @@ -95,11 +174,67 @@ static bool qspi_pins_configure(nrf_qspi_pins_t const * p_config) return false; } +#if defined(NRF5340_XXAA) + // Check if dedicated QSPI pins are used. + enum { + QSPI_IO0_DEDICATED = NRF_GPIO_PIN_MAP(0, 13), + QSPI_IO1_DEDICATED = NRF_GPIO_PIN_MAP(0, 14), + QSPI_IO2_DEDICATED = NRF_GPIO_PIN_MAP(0, 15), + QSPI_IO3_DEDICATED = NRF_GPIO_PIN_MAP(0, 16), + QSPI_SCK_DEDICATED = NRF_GPIO_PIN_MAP(0, 17), + QSPI_CSN_DEDICATED = NRF_GPIO_PIN_MAP(0, 18) + }; + + if ((p_config->sck_pin != QSPI_SCK_DEDICATED) || + (p_config->csn_pin != QSPI_CSN_DEDICATED) || + (p_config->io0_pin != QSPI_IO0_DEDICATED) || + (p_config->io1_pin != QSPI_IO1_DEDICATED) || + (p_config->io2_pin != NRF_QSPI_PIN_NOT_CONNECTED && + p_config->io2_pin != QSPI_IO2_DEDICATED) || + (p_config->io3_pin != NRF_QSPI_PIN_NOT_CONNECTED && + p_config->io3_pin != QSPI_IO3_DEDICATED)) + { + return false; + } +#endif + + QSPI_PIN_INIT(p_config->sck_pin); + QSPI_PIN_INIT(p_config->csn_pin); + QSPI_PIN_INIT(p_config->io0_pin); + QSPI_PIN_INIT(p_config->io1_pin); + if (p_config->io2_pin != NRF_QSPI_PIN_NOT_CONNECTED) + { + QSPI_PIN_INIT(p_config->io2_pin); + } + if (p_config->io3_pin != NRF_QSPI_PIN_NOT_CONNECTED) + { + QSPI_PIN_INIT(p_config->io3_pin); + } + nrf_qspi_pins_set(NRF_QSPI, p_config); return true; } +static void qspi_pins_deconfigure(void) +{ + nrf_qspi_pins_t pins; + nrf_qspi_pins_get(NRF_QSPI, &pins); + + nrf_gpio_cfg_default(pins.sck_pin); + nrf_gpio_cfg_default(pins.csn_pin); + nrf_gpio_cfg_default(pins.io0_pin); + nrf_gpio_cfg_default(pins.io1_pin); + if (pins.io2_pin != NRF_QSPI_PIN_NOT_CONNECTED) + { + nrf_gpio_cfg_default(pins.io2_pin); + } + if (pins.io3_pin != NRF_QSPI_PIN_NOT_CONNECTED) + { + nrf_gpio_cfg_default(pins.io3_pin); + } +} + static nrfx_err_t qspi_ready_wait(void) { bool result; @@ -120,7 +255,7 @@ nrfx_err_t nrfx_qspi_init(nrfx_qspi_config_t const * p_config, void * p_context) { NRFX_ASSERT(p_config); - if (m_cb.state != NRFX_DRV_STATE_UNINITIALIZED) + if (m_cb.state != NRFX_QSPI_STATE_UNINITIALIZED) { return NRFX_ERROR_INVALID_STATE; } @@ -131,15 +266,29 @@ nrfx_err_t nrfx_qspi_init(nrfx_qspi_config_t const * p_config, } nrf_qspi_xip_offset_set(NRF_QSPI, p_config->xip_offset); + nrf_qspi_ifconfig0_set(NRF_QSPI, &p_config->prot_if); +#if NRFX_CHECK(USE_WORKAROUND_FOR_ANOMALY_121) + uint32_t regval = nrf_qspi_ifconfig0_raw_get(NRF_QSPI); + if (p_config->phy_if.sck_freq == NRF_QSPI_FREQ_DIV1) + { + regval |= ((1 << 16) | (1 << 17)); + } + else + { + regval &= ~(1 << 17); + regval |= (1 << 16); + } + nrf_qspi_ifconfig0_raw_set(NRF_QSPI, regval); + nrf_qspi_iftiming_set(NRF_QSPI, 6); +#endif nrf_qspi_ifconfig1_set(NRF_QSPI, &p_config->phy_if); - m_cb.is_busy = false; m_cb.handler = handler; m_cb.p_context = p_context; - /* QSPI interrupt is disabled because the device should be enabled in polling mode (wait for activate - task event ready)*/ + /* QSPI interrupt is disabled because the device should be enabled in polling mode + (wait for activate task event ready) */ nrf_qspi_int_disable(NRF_QSPI, NRF_QSPI_INT_READY_MASK); if (handler) @@ -148,7 +297,8 @@ nrfx_err_t nrfx_qspi_init(nrfx_qspi_config_t const * p_config, NRFX_IRQ_ENABLE(QSPI_IRQn); } - m_cb.state = NRFX_DRV_STATE_INITIALIZED; + m_cb.p_buffer_primary = NULL; + m_cb.state = NRFX_QSPI_STATE_IDLE; nrf_qspi_enable(NRF_QSPI); @@ -164,9 +314,9 @@ nrfx_err_t nrfx_qspi_cinstr_xfer(nrf_qspi_cinstr_conf_t const * p_config, void const * p_tx_buffer, void * p_rx_buffer) { - NRFX_ASSERT(m_cb.state != NRFX_DRV_STATE_UNINITIALIZED); + NRFX_ASSERT(m_cb.state != NRFX_QSPI_STATE_UNINITIALIZED); - if (m_cb.is_busy) + if (m_cb.state != NRFX_QSPI_STATE_IDLE) { return NRFX_ERROR_BUSY; } @@ -213,11 +363,11 @@ nrfx_err_t nrfx_qspi_cinstr_quick_send(uint8_t opcode, nrfx_err_t nrfx_qspi_lfm_start(nrf_qspi_cinstr_conf_t const * p_config) { - NRFX_ASSERT(m_cb.state != NRFX_DRV_STATE_UNINITIALIZED); + NRFX_ASSERT(m_cb.state != NRFX_QSPI_STATE_UNINITIALIZED); NRFX_ASSERT(!(nrf_qspi_cinstr_long_transfer_is_ongoing(NRF_QSPI))); NRFX_ASSERT(p_config->length == NRF_QSPI_CINSTR_LEN_1B); - if (m_cb.is_busy) + if (m_cb.state != NRFX_QSPI_STATE_IDLE) { return NRFX_ERROR_BUSY; } @@ -231,7 +381,7 @@ nrfx_err_t nrfx_qspi_lfm_start(nrf_qspi_cinstr_conf_t const * p_config) return NRFX_ERROR_TIMEOUT; } - m_cb.is_busy = true; + m_cb.state = NRFX_QSPI_STATE_CINSTR; return NRFX_SUCCESS; } @@ -240,7 +390,7 @@ nrfx_err_t nrfx_qspi_lfm_xfer(void const * p_tx_buffer, size_t transfer_length, bool finalize) { - NRFX_ASSERT(m_cb.state != NRFX_DRV_STATE_UNINITIALIZED); + NRFX_ASSERT(m_cb.state != NRFX_QSPI_STATE_UNINITIALIZED); NRFX_ASSERT(nrf_qspi_cinstr_long_transfer_is_ongoing(NRF_QSPI)); nrfx_err_t status = NRFX_SUCCESS; @@ -292,7 +442,7 @@ nrfx_err_t nrfx_qspi_lfm_xfer(void const * p_tx_buffer, if ((finalize) || (status == NRFX_ERROR_TIMEOUT)) { - m_cb.is_busy = false; + m_cb.state = NRFX_QSPI_STATE_IDLE; } return status; @@ -323,7 +473,9 @@ nrfx_err_t nrfx_qspi_mem_busy_check(void) void nrfx_qspi_uninit(void) { - NRFX_ASSERT(m_cb.state != NRFX_DRV_STATE_UNINITIALIZED); + NRFX_ASSERT(m_cb.state != NRFX_QSPI_STATE_UNINITIALIZED); + + NRFX_IRQ_DISABLE(QSPI_IRQn); if (nrf_qspi_cinstr_long_transfer_is_ongoing(NRF_QSPI)) { @@ -336,57 +488,57 @@ void nrfx_qspi_uninit(void) nrf_qspi_disable(NRF_QSPI); - NRFX_IRQ_DISABLE(QSPI_IRQn); - nrf_qspi_event_clear(NRF_QSPI, NRF_QSPI_EVENT_READY); - m_cb.state = NRFX_DRV_STATE_UNINITIALIZED; + qspi_pins_deconfigure(); + + m_cb.state = NRFX_QSPI_STATE_UNINITIALIZED; } nrfx_err_t nrfx_qspi_write(void const * p_tx_buffer, size_t tx_buffer_length, uint32_t dst_address) { - NRFX_ASSERT(m_cb.state != NRFX_DRV_STATE_UNINITIALIZED); - NRFX_ASSERT(p_tx_buffer != NULL); - - if (!nrfx_is_in_ram(p_tx_buffer) || !nrfx_is_word_aligned(p_tx_buffer)) - { - return NRFX_ERROR_INVALID_ADDR; - } - - nrf_qspi_write_buffer_set(NRF_QSPI, p_tx_buffer, tx_buffer_length, dst_address); - return qspi_task_perform(NRF_QSPI_TASK_WRITESTART); + return qspi_xfer((void *)p_tx_buffer, tx_buffer_length, dst_address, NRFX_QSPI_STATE_WRITE); } nrfx_err_t nrfx_qspi_read(void * p_rx_buffer, size_t rx_buffer_length, uint32_t src_address) { - NRFX_ASSERT(m_cb.state != NRFX_DRV_STATE_UNINITIALIZED); - NRFX_ASSERT(p_rx_buffer != NULL); - - if (!nrfx_is_in_ram(p_rx_buffer) || !nrfx_is_word_aligned(p_rx_buffer)) - { - return NRFX_ERROR_INVALID_ADDR; - } - - nrf_qspi_read_buffer_set(NRF_QSPI, p_rx_buffer, rx_buffer_length, src_address); - return qspi_task_perform(NRF_QSPI_TASK_READSTART); + return qspi_xfer((void *)p_rx_buffer, rx_buffer_length, src_address, NRFX_QSPI_STATE_READ); } nrfx_err_t nrfx_qspi_erase(nrf_qspi_erase_len_t length, uint32_t start_address) { - NRFX_ASSERT(m_cb.state != NRFX_DRV_STATE_UNINITIALIZED); + NRFX_ASSERT(m_cb.state != NRFX_QSPI_STATE_UNINITIALIZED); if (!nrfx_is_word_aligned((void const *)start_address)) { return NRFX_ERROR_INVALID_ADDR; } + if (m_cb.handler && m_cb.state != NRFX_QSPI_STATE_IDLE) + { + return NRFX_ERROR_BUSY; + } + m_cb.state = NRFX_QSPI_STATE_ERASE; + nrf_qspi_erase_ptr_set(NRF_QSPI, start_address, length); - return qspi_task_perform(NRF_QSPI_TASK_ERASESTART); + nrf_qspi_event_clear(NRF_QSPI, NRF_QSPI_EVENT_READY); + nrf_qspi_task_trigger(NRF_QSPI, NRF_QSPI_TASK_ERASESTART); + if (!m_cb.handler) + { + while (!nrf_qspi_event_check(NRF_QSPI, NRF_QSPI_EVENT_READY)) + {} + m_cb.state = NRFX_QSPI_STATE_IDLE; + } + else + { + nrf_qspi_int_enable(NRF_QSPI, NRF_QSPI_INT_READY_MASK); + } + return NRFX_SUCCESS; } nrfx_err_t nrfx_qspi_chip_erase(void) @@ -394,10 +546,26 @@ nrfx_err_t nrfx_qspi_chip_erase(void) return nrfx_qspi_erase(NRF_QSPI_ERASE_LEN_ALL, 0); } +nrfx_qspi_evt_ext_t const * nrfx_qspi_event_extended_get(void) +{ + NRFX_ASSERT(m_cb.state != NRFX_QSPI_STATE_UNINITIALIZED); + NRFX_ASSERT(m_cb.evt_ext.type != NRFX_QSPI_EVENT_NONE); + return &m_cb.evt_ext; +} + +bool nrfx_qspi_xfer_buffered_check(void) +{ + NRFX_ASSERT(m_cb.state != NRFX_QSPI_STATE_UNINITIALIZED); + + return (bool)m_cb.p_buffer_secondary; +} + #if NRF_QSPI_HAS_XIP_ENC nrfx_err_t nrfx_qspi_xip_encrypt(nrf_qspi_encryption_t const * p_config) { - if (m_cb.is_busy) + NRFX_ASSERT(m_cb.state != NRFX_QSPI_STATE_UNINITIALIZED); + + if (m_cb.state != NRFX_QSPI_STATE_IDLE) { return NRFX_ERROR_BUSY; } @@ -419,7 +587,9 @@ nrfx_err_t nrfx_qspi_xip_encrypt(nrf_qspi_encryption_t const * p_config) #if NRF_QSPI_HAS_DMA_ENC nrfx_err_t nrfx_qspi_dma_encrypt(nrf_qspi_encryption_t const * p_config) { - if (m_cb.is_busy) + NRFX_ASSERT(m_cb.state != NRFX_QSPI_STATE_UNINITIALIZED); + + if (m_cb.state != NRFX_QSPI_STATE_IDLE) { return NRFX_ERROR_BUSY; } @@ -438,14 +608,70 @@ nrfx_err_t nrfx_qspi_dma_encrypt(nrf_qspi_encryption_t const * p_config) } #endif +static void qspi_event_xfer_handle(nrfx_qspi_evt_ext_xfer_t * p_xfer) +{ + p_xfer->p_buffer = (uint8_t *)m_cb.p_buffer_primary; + p_xfer->size = m_cb.size_primary; + p_xfer->addr = m_cb.addr_primary; + if (m_cb.p_buffer_secondary) + { + m_cb.p_buffer_primary = m_cb.p_buffer_secondary; + m_cb.size_primary = m_cb.size_secondary; + m_cb.addr_primary = m_cb.addr_secondary; + + m_cb.p_buffer_secondary = NULL; + } + else + { + m_cb.p_buffer_primary = NULL; + } +} + +static void qspi_event_erase_handle(nrfx_qspi_evt_ext_erase_t * p_erase) +{ + p_erase->addr = nrf_qspi_erase_ptr_get(NRF_QSPI); + p_erase->len = nrf_qspi_erase_len_get(NRF_QSPI); +} + +static void qspi_extended_event_process(nrfx_qspi_evt_ext_t * p_event) +{ + switch (m_cb.state) + { + case NRFX_QSPI_STATE_WRITE: + p_event->type = NRFX_QSPI_EVENT_WRITE_DONE; + qspi_event_xfer_handle(&p_event->data.xfer); + break; + + case NRFX_QSPI_STATE_READ: + p_event->type = NRFX_QSPI_EVENT_READ_DONE; + qspi_event_xfer_handle(&p_event->data.xfer); + break; + + case NRFX_QSPI_STATE_ERASE: + p_event->type = NRFX_QSPI_EVENT_ERASE_DONE; + qspi_event_erase_handle(&p_event->data.erase); + break; + + default: + break; + } +} + void nrfx_qspi_irq_handler(void) { // Catch Event ready interrupts if (nrf_qspi_event_check(NRF_QSPI, NRF_QSPI_EVENT_READY)) { - m_cb.is_busy = false; nrf_qspi_event_clear(NRF_QSPI, NRF_QSPI_EVENT_READY); + + qspi_extended_event_process(&m_cb.evt_ext); + if (!m_cb.p_buffer_primary) + { + m_cb.state = NRFX_QSPI_STATE_IDLE; + } + m_cb.handler(NRFX_QSPI_EVENT_DONE, m_cb.p_context); + m_cb.evt_ext.type = NRFX_QSPI_EVENT_NONE; } } diff --git a/drivers/src/nrfx_rng.c b/drivers/src/nrfx_rng.c index bf5b4ef177..182280bc07 100644 --- a/drivers/src/nrfx_rng.c +++ b/drivers/src/nrfx_rng.c @@ -1,7 +1,9 @@ /* - * Copyright (c) 2016 - 2020, Nordic Semiconductor ASA + * Copyright (c) 2016 - 2021, Nordic Semiconductor ASA * All rights reserved. * + * SPDX-License-Identifier: BSD-3-Clause + * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * diff --git a/drivers/src/nrfx_rtc.c b/drivers/src/nrfx_rtc.c index 2b8374914a..6022622036 100644 --- a/drivers/src/nrfx_rtc.c +++ b/drivers/src/nrfx_rtc.c @@ -1,7 +1,9 @@ /* - * Copyright (c) 2014 - 2020, Nordic Semiconductor ASA + * Copyright (c) 2014 - 2021, Nordic Semiconductor ASA * All rights reserved. * + * SPDX-License-Identifier: BSD-3-Clause + * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * diff --git a/drivers/src/nrfx_saadc.c b/drivers/src/nrfx_saadc.c index ae41eb0fbb..c80612c131 100644 --- a/drivers/src/nrfx_saadc.c +++ b/drivers/src/nrfx_saadc.c @@ -1,7 +1,9 @@ /* - * Copyright (c) 2015 - 2020, Nordic Semiconductor ASA + * Copyright (c) 2015 - 2021, Nordic Semiconductor ASA * All rights reserved. * + * SPDX-License-Identifier: BSD-3-Clause + * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * @@ -50,6 +52,9 @@ #define INTERCEPT_SAADC_CALIBRATION_SAMPLES 1 #endif +/** @brief Bitmask of all available SAADC channels. */ +#define SAADC_ALL_CHANNELS_MASK ((1UL << SAADC_CH_NUM) - 1UL) + /** @brief SAADC driver states.*/ typedef enum { @@ -144,6 +149,30 @@ static nrfx_err_t saadc_channel_count_get(uint32_t ch_to_activate_mask, return NRFX_SUCCESS; } +static void saadc_channel_config(nrfx_saadc_channel_t const * p_channel) +{ + NRFX_ASSERT(p_channel->pin_p != NRF_SAADC_INPUT_DISABLED); + + nrf_saadc_channel_init(NRF_SAADC, p_channel->channel_index, &p_channel->channel_config); + m_cb.channels_pselp[p_channel->channel_index] = p_channel->pin_p; + m_cb.channels_pseln[p_channel->channel_index] = p_channel->pin_n; + m_cb.channels_configured |= 1U << p_channel->channel_index; +} + +static void saadc_channels_deconfig(uint32_t channel_mask) +{ + while (channel_mask) + { + uint8_t channel = __CLZ(__RBIT(channel_mask)); + + channel_mask &= ~(1 << channel); + m_cb.channels_configured &= ~(1 << channel); + + m_cb.channels_pselp[channel] = NRF_SAADC_INPUT_DISABLED; + m_cb.channels_pseln[channel] = NRF_SAADC_INPUT_DISABLED; + } +} + static bool saadc_busy_check(void) { if ((m_cb.saadc_state == NRF_SAADC_STATE_IDLE) || @@ -238,6 +267,7 @@ nrfx_err_t nrfx_saadc_init(uint8_t interrupt_priority) nrf_saadc_event_clear(NRF_SAADC, NRF_SAADC_EVENT_STOPPED); nrf_saadc_event_clear(NRF_SAADC, NRF_SAADC_EVENT_END); nrf_saadc_int_set(NRF_SAADC, 0); + saadc_channels_deconfig(SAADC_ALL_CHANNELS_MASK); NRFX_IRQ_ENABLE(SAADC_IRQn); NRFX_IRQ_PRIORITY_SET(SAADC_IRQn, interrupt_priority); @@ -259,6 +289,7 @@ nrfx_err_t nrfx_saadc_channels_config(nrfx_saadc_channel_t const * p_channels, uint32_t channel_count) { NRFX_ASSERT(m_cb.saadc_state != NRF_SAADC_STATE_UNINITIALIZED); + NRFX_ASSERT(p_channels); NRFX_ASSERT(channel_count <= SAADC_CH_NUM); if (saadc_busy_check()) @@ -266,35 +297,50 @@ nrfx_err_t nrfx_saadc_channels_config(nrfx_saadc_channel_t const * p_channels, return NRFX_ERROR_BUSY; } - m_cb.channels_configured = 0; - uint8_t i = 0; - - for (; i < SAADC_CH_NUM; i++) - { - m_cb.channels_pselp[i] = NRF_SAADC_INPUT_DISABLED; - m_cb.channels_pseln[i] = NRF_SAADC_INPUT_DISABLED; - } - - for (i = 0; i < channel_count; i++) + saadc_channels_deconfig(SAADC_ALL_CHANNELS_MASK); + for (uint8_t i = 0; i < channel_count; i++) { if (m_cb.channels_configured & (1 << p_channels[i].channel_index)) { // This channel is already configured! return NRFX_ERROR_INVALID_PARAM; } - nrf_saadc_channel_init(NRF_SAADC, - p_channels[i].channel_index, - &p_channels[i].channel_config); - NRFX_ASSERT(p_channels[i].pin_p != NRF_SAADC_INPUT_DISABLED); - m_cb.channels_pselp[p_channels[i].channel_index] = p_channels[i].pin_p; - m_cb.channels_pseln[p_channels[i].channel_index] = p_channels[i].pin_n; - m_cb.channels_configured |= 1U << p_channels[i].channel_index; + saadc_channel_config(&p_channels[i]); } return NRFX_SUCCESS; } +nrfx_err_t nrfx_saadc_channel_config(nrfx_saadc_channel_t const * p_channel) +{ + NRFX_ASSERT(m_cb.saadc_state != NRF_SAADC_STATE_UNINITIALIZED); + NRFX_ASSERT(p_channel); + + if (saadc_busy_check()) + { + return NRFX_ERROR_BUSY; + } + + saadc_channel_config(p_channel); + + return NRFX_SUCCESS; +} + +nrfx_err_t nrfx_saadc_channels_deconfig(uint32_t channel_mask) +{ + NRFX_ASSERT(m_cb.saadc_state != NRF_SAADC_STATE_UNINITIALIZED); + + if (saadc_busy_check()) + { + return NRFX_ERROR_BUSY; + } + + saadc_channels_deconfig(channel_mask); + + return NRFX_SUCCESS; +} + nrfx_err_t nrfx_saadc_simple_mode_set(uint32_t channel_mask, nrf_saadc_resolution_t resolution, nrf_saadc_oversample_t oversampling, diff --git a/drivers/src/nrfx_spi.c b/drivers/src/nrfx_spi.c index 836e0c42ce..1951a4cc7e 100644 --- a/drivers/src/nrfx_spi.c +++ b/drivers/src/nrfx_spi.c @@ -1,7 +1,9 @@ /* - * Copyright (c) 2015 - 2020, Nordic Semiconductor ASA + * Copyright (c) 2015 - 2021, Nordic Semiconductor ASA * All rights reserved. * + * SPDX-License-Identifier: BSD-3-Clause + * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * diff --git a/drivers/src/nrfx_spim.c b/drivers/src/nrfx_spim.c index 5f64315c55..28d0749e66 100644 --- a/drivers/src/nrfx_spim.c +++ b/drivers/src/nrfx_spim.c @@ -1,7 +1,9 @@ /* - * Copyright (c) 2015 - 2020, Nordic Semiconductor ASA + * Copyright (c) 2015 - 2021, Nordic Semiconductor ASA * All rights reserved. * + * SPDX-License-Identifier: BSD-3-Clause + * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * @@ -162,9 +164,14 @@ SPIM3_SUPPORTED_FREQ_VALIDATE(drv_inst_idx, freq) || \ SPIM4_SUPPORTED_FREQ_VALIDATE(drv_inst_idx, freq)) -#if defined(NRF52840_XXAA) && (NRFX_CHECK(NRFX_SPIM3_ENABLED)) +// Requested pin can either match dedicated pin or be not connected at all. +#define SPIM_DEDICATED_PIN_VALIDATE(requested_pin, supported_pin) \ + (((requested_pin) == NRFX_SPIM_PIN_NOT_USED) || ((requested_pin) == (supported_pin))) + +#if !defined(USE_WORKAROUND_FOR_ANOMALY_195) && \ + defined(NRF52840_XXAA) && NRFX_CHECK(NRFX_SPIM3_ENABLED) // Enable workaround for nRF52840 anomaly 195 (SPIM3 continues to draw current after disable). -#define USE_WORKAROUND_FOR_ANOMALY_195 +#define USE_WORKAROUND_FOR_ANOMALY_195 1 #endif @@ -285,6 +292,35 @@ nrfx_err_t nrfx_spim_init(nrfx_spim_t const * p_instance, NRF_SPIM_Type * p_spim = (NRF_SPIM_Type *)p_instance->p_reg; +#if NRF_SPIM_HAS_32_MHZ_FREQ && defined(NRF5340_XXAA_APPLICATION) + // Check if dedicated SPIM pins are used. + if ((p_spim == NRF_SPIM4) && (p_config->frequency == NRF_SPIM_FREQ_32M)) + { + enum { + SPIM_SCK_DEDICATED = NRF_GPIO_PIN_MAP(0, 8), + SPIM_MOSI_DEDICATED = NRF_GPIO_PIN_MAP(0, 9), + SPIM_MISO_DEDICATED = NRF_GPIO_PIN_MAP(0, 10), + SPIM_CSN_DEDICATED = NRF_GPIO_PIN_MAP(0, 11), + SPIM_DCX_DEDICATED = NRF_GPIO_PIN_MAP(0, 12), + }; + + if (!SPIM_DEDICATED_PIN_VALIDATE(p_config->sck_pin, SPIM_SCK_DEDICATED) || + !SPIM_DEDICATED_PIN_VALIDATE(p_config->ss_pin, SPIM_CSN_DEDICATED) || +#if NRFX_CHECK(NRFX_SPIM_EXTENDED_ENABLED) + !SPIM_DEDICATED_PIN_VALIDATE(p_config->dcx_pin, SPIM_DCX_DEDICATED) || +#endif + !SPIM_DEDICATED_PIN_VALIDATE(p_config->mosi_pin, SPIM_MOSI_DEDICATED) || + !SPIM_DEDICATED_PIN_VALIDATE(p_config->miso_pin, SPIM_MISO_DEDICATED)) + { + err_code = NRFX_ERROR_INVALID_PARAM; + NRFX_LOG_WARNING("Function: %s, error code: %s.", + __func__, + NRFX_LOG_ERROR_STRING_GET(err_code)); + return err_code; + } + } +#endif + #if NRFX_CHECK(NRFX_PRS_ENABLED) static nrfx_irq_handler_t const irq_handlers[NRFX_SPIM_ENABLED_COUNT] = { #if NRFX_CHECK(NRFX_SPIM0_ENABLED) @@ -332,18 +368,32 @@ nrfx_err_t nrfx_spim_init(nrfx_spim_t const * p_instance, { nrf_gpio_pin_set(p_config->sck_pin); } + + nrf_gpio_pin_drive_t pin_drive; + // Configure pin drive - high drive for 32 MHz clock frequency. +#if NRF_SPIM_HAS_32_MHZ_FREQ + pin_drive = (p_config->frequency == NRF_SPIM_FREQ_32M) ? NRF_GPIO_PIN_H0H1 : NRF_GPIO_PIN_S0S1; +#else + pin_drive = NRF_GPIO_PIN_S0S1; +#endif + nrf_gpio_cfg(p_config->sck_pin, NRF_GPIO_PIN_DIR_OUTPUT, NRF_GPIO_PIN_INPUT_CONNECT, NRF_GPIO_PIN_NOPULL, - NRF_GPIO_PIN_S0S1, + pin_drive, NRF_GPIO_PIN_NOSENSE); // - MOSI (optional) - output with initial value 0, if (p_config->mosi_pin != NRFX_SPIM_PIN_NOT_USED) { mosi_pin = p_config->mosi_pin; nrf_gpio_pin_clear(mosi_pin); - nrf_gpio_cfg_output(mosi_pin); + nrf_gpio_cfg(mosi_pin, + NRF_GPIO_PIN_DIR_OUTPUT, + NRF_GPIO_PIN_INPUT_DISCONNECT, + NRF_GPIO_PIN_NOPULL, + pin_drive, + NRF_GPIO_PIN_NOSENSE); } else { @@ -353,7 +403,12 @@ nrfx_err_t nrfx_spim_init(nrfx_spim_t const * p_instance, if (p_config->miso_pin != NRFX_SPIM_PIN_NOT_USED) { miso_pin = p_config->miso_pin; - nrf_gpio_cfg_input(miso_pin, p_config->miso_pull); + nrf_gpio_cfg(miso_pin, + NRF_GPIO_PIN_DIR_INPUT, + NRF_GPIO_PIN_INPUT_CONNECT, + p_config->miso_pull, + pin_drive, + NRF_GPIO_PIN_NOSENSE); } else { @@ -375,7 +430,12 @@ nrfx_err_t nrfx_spim_init(nrfx_spim_t const * p_instance, { nrf_gpio_pin_set(p_config->ss_pin); } - nrf_gpio_cfg_output(p_config->ss_pin); + nrf_gpio_cfg(p_config->ss_pin, + NRF_GPIO_PIN_DIR_OUTPUT, + NRF_GPIO_PIN_INPUT_DISCONNECT, + NRF_GPIO_PIN_NOPULL, + pin_drive, + NRF_GPIO_PIN_NOSENSE); #if NRFX_CHECK(NRFX_SPIM_EXTENDED_ENABLED) if (p_config->use_hw_ss) { @@ -395,7 +455,12 @@ nrfx_err_t nrfx_spim_init(nrfx_spim_t const * p_instance, if (p_config->dcx_pin != NRFX_SPIM_PIN_NOT_USED) { nrf_gpio_pin_set(p_config->dcx_pin); - nrf_gpio_cfg_output(p_config->dcx_pin); + nrf_gpio_cfg(p_config->dcx_pin, + NRF_GPIO_PIN_DIR_OUTPUT, + NRF_GPIO_PIN_INPUT_DISCONNECT, + NRF_GPIO_PIN_NOPULL, + pin_drive, + NRF_GPIO_PIN_NOSENSE); nrf_spim_dcx_pin_set(p_spim, p_config->dcx_pin); } @@ -403,7 +468,6 @@ nrfx_err_t nrfx_spim_init(nrfx_spim_t const * p_instance, nrf_spim_iftiming_set(p_spim, p_config->rx_delay); #endif - nrf_spim_pins_set(p_spim, p_config->sck_pin, mosi_pin, miso_pin); nrf_spim_frequency_set(p_spim, p_config->frequency); nrf_spim_configure(p_spim, p_config->mode, p_config->bit_order); @@ -427,6 +491,16 @@ nrfx_err_t nrfx_spim_init(nrfx_spim_t const * p_instance, return err_code; } +static void spim_pin_uninit(uint32_t pin) +{ + if (pin == NRF_SPIM_PIN_NOT_CONNECTED) + { + return; + } + + nrf_gpio_cfg_default(pin); +} + void nrfx_spim_uninit(nrfx_spim_t const * p_instance) { spim_control_block_t * p_cb = &m_cb[p_instance->drv_inst_idx]; @@ -446,34 +520,21 @@ void nrfx_spim_uninit(nrfx_spim_t const * p_instance) nrf_spim_disable(p_spim); - nrf_gpio_cfg_default(nrf_spim_sck_pin_get(p_spim)); - - uint32_t miso_pin = nrf_spim_miso_pin_get(p_spim); - if (miso_pin != NRF_SPIM_PIN_NOT_CONNECTED) - { - nrf_gpio_cfg_default(miso_pin); - } - - uint32_t mosi_pin = nrf_spim_mosi_pin_get(p_spim); - if (mosi_pin != NRF_SPIM_PIN_NOT_CONNECTED) + spim_pin_uninit(nrf_spim_sck_pin_get(p_spim)); + spim_pin_uninit(nrf_spim_miso_pin_get(p_spim)); + spim_pin_uninit(nrf_spim_mosi_pin_get(p_spim)); +#if NRFX_CHECK(NRFX_SPIM_EXTENDED_ENABLED) + if (SPIM_DCX_PRESENT_VALIDATE(p_instance->drv_inst_idx)) { - nrf_gpio_cfg_default(mosi_pin); + spim_pin_uninit(nrf_spim_dcx_pin_get(p_spim)); } - +#endif if (p_cb->ss_pin != NRFX_SPIM_PIN_NOT_USED) { nrf_gpio_cfg_default(p_cb->ss_pin); } -#if NRFX_CHECK(NRFX_SPIM_EXTENDED_ENABLED) - uint32_t dcx_pin = nrf_spim_dcx_pin_get(p_spim); - if (dcx_pin != NRF_SPIM_PIN_NOT_CONNECTED) - { - nrf_gpio_cfg_default(dcx_pin); - } -#endif - -#ifdef USE_WORKAROUND_FOR_ANOMALY_195 +#if NRFX_CHECK(USE_WORKAROUND_FOR_ANOMALY_195) if (p_spim == NRF_SPIM3) { *(volatile uint32_t *)0x4002F004 = 1; diff --git a/drivers/src/nrfx_spis.c b/drivers/src/nrfx_spis.c index 0ca604731f..88654a0163 100644 --- a/drivers/src/nrfx_spis.c +++ b/drivers/src/nrfx_spis.c @@ -1,7 +1,9 @@ /* - * Copyright (c) 2013 - 2020, Nordic Semiconductor ASA + * Copyright (c) 2013 - 2021, Nordic Semiconductor ASA * All rights reserved. * + * SPDX-License-Identifier: BSD-3-Clause + * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * diff --git a/drivers/src/nrfx_systick.c b/drivers/src/nrfx_systick.c index 708826adaf..8cc3cd5957 100644 --- a/drivers/src/nrfx_systick.c +++ b/drivers/src/nrfx_systick.c @@ -1,7 +1,9 @@ /* - * Copyright (c) 2016 - 2020, Nordic Semiconductor ASA + * Copyright (c) 2016 - 2021, Nordic Semiconductor ASA * All rights reserved. * + * SPDX-License-Identifier: BSD-3-Clause + * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * diff --git a/drivers/src/nrfx_temp.c b/drivers/src/nrfx_temp.c index 98ebb21256..a12554821b 100644 --- a/drivers/src/nrfx_temp.c +++ b/drivers/src/nrfx_temp.c @@ -1,7 +1,9 @@ /* - * Copyright (c) 2019 - 2020, Nordic Semiconductor ASA + * Copyright (c) 2019 - 2021, Nordic Semiconductor ASA * All rights reserved. * + * SPDX-License-Identifier: BSD-3-Clause + * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * diff --git a/drivers/src/nrfx_timer.c b/drivers/src/nrfx_timer.c index 670e8e43fe..5d990e9d0b 100644 --- a/drivers/src/nrfx_timer.c +++ b/drivers/src/nrfx_timer.c @@ -1,7 +1,9 @@ /* - * Copyright (c) 2015 - 2020, Nordic Semiconductor ASA + * Copyright (c) 2015 - 2021, Nordic Semiconductor ASA * All rights reserved. * + * SPDX-License-Identifier: BSD-3-Clause + * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * diff --git a/drivers/src/nrfx_twi.c b/drivers/src/nrfx_twi.c index 6b9df394c9..de16c25275 100644 --- a/drivers/src/nrfx_twi.c +++ b/drivers/src/nrfx_twi.c @@ -1,7 +1,9 @@ /* - * Copyright (c) 2015 - 2020, Nordic Semiconductor ASA + * Copyright (c) 2015 - 2021, Nordic Semiconductor ASA * All rights reserved. * + * SPDX-License-Identifier: BSD-3-Clause + * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * diff --git a/drivers/src/nrfx_twi_twim.c b/drivers/src/nrfx_twi_twim.c index b15f7c681e..ccb51bae0b 100644 --- a/drivers/src/nrfx_twi_twim.c +++ b/drivers/src/nrfx_twi_twim.c @@ -1,7 +1,9 @@ /* - * Copyright (c) 2019 - 2020, Nordic Semiconductor ASA + * Copyright (c) 2019 - 2021, Nordic Semiconductor ASA * All rights reserved. * + * SPDX-License-Identifier: BSD-3-Clause + * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * diff --git a/drivers/src/nrfx_twim.c b/drivers/src/nrfx_twim.c index 87e0572b2e..17927daa38 100644 --- a/drivers/src/nrfx_twim.c +++ b/drivers/src/nrfx_twim.c @@ -1,7 +1,9 @@ /* - * Copyright (c) 2015 - 2020, Nordic Semiconductor ASA + * Copyright (c) 2015 - 2021, Nordic Semiconductor ASA * All rights reserved. * + * SPDX-License-Identifier: BSD-3-Clause + * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * @@ -72,12 +74,12 @@ (type == NRFX_TWIM_XFER_TXTX ? "XFER_TXTX" : \ "UNKNOWN TRANSFER TYPE")))) -#define TWIM_PIN_INIT(_pin) nrf_gpio_cfg((_pin), \ - NRF_GPIO_PIN_DIR_INPUT, \ - NRF_GPIO_PIN_INPUT_CONNECT, \ - NRF_GPIO_PIN_PULLUP, \ - NRF_GPIO_PIN_S0D1, \ - NRF_GPIO_PIN_NOSENSE) +#define TWIM_PIN_INIT(_pin, _drive) nrf_gpio_cfg((_pin), \ + NRF_GPIO_PIN_DIR_INPUT, \ + NRF_GPIO_PIN_INPUT_CONNECT, \ + NRF_GPIO_PIN_PULLUP, \ + (_drive), \ + NRF_GPIO_PIN_NOSENSE) #define TWIMX_LENGTH_VALIDATE(peripheral, drv_inst_idx, len1, len2) \ (((drv_inst_idx) == NRFX_CONCAT_3(NRFX_, peripheral, _INST_IDX)) && \ @@ -214,6 +216,44 @@ static bool xfer_completeness_check(NRF_TWIM_Type * p_twim, twim_control_block_t return transfer_complete; } +static bool twim_pins_configure(NRF_TWIM_Type * p_twim, nrfx_twim_config_t const * p_config) +{ + nrf_gpio_pin_drive_t drive; + +#if NRF_TWIM_HAS_1000_KHZ_FREQ && defined(NRF5340_XXAA) + if (p_config->frequency >= NRF_TWIM_FREQ_1000K) + { + /* When using 1 Mbps mode, two high-speed pins have to be used with extra high drive. */ + drive = NRF_GPIO_PIN_E0E1; + + uint32_t e0e1_pin_1 = NRF_GPIO_PIN_MAP(1, 2); + uint32_t e0e1_pin_2 = NRF_GPIO_PIN_MAP(1, 3); + + /* Check whether provided pins have the extra high drive capabilities. */ + if (((p_config->scl != e0e1_pin_1) || (p_config->sda != e0e1_pin_2)) && + ((p_config->scl != e0e1_pin_2) || (p_config->sda != e0e1_pin_1))) + { + return false; + } + } + else +#endif + { + drive = NRF_GPIO_PIN_S0D1; + } + + /* To secure correct signal levels on the pins used by the TWI + master when the system is in OFF mode, and when the TWI master is + disabled, these pins must be configured in the GPIO peripheral. + */ + TWIM_PIN_INIT(p_config->scl, drive); + TWIM_PIN_INIT(p_config->sda, drive); + + nrf_twim_pins_set(p_twim, p_config->scl, p_config->sda); + + return true; +} + nrfx_err_t nrfx_twim_init(nrfx_twim_t const * p_instance, nrfx_twim_config_t const * p_config, nrfx_twim_evt_handler_t event_handler, @@ -269,17 +309,13 @@ nrfx_err_t nrfx_twim_init(nrfx_twim_t const * p_instance, p_cb->bus_frequency = (nrf_twim_frequency_t)p_config->frequency; #endif - /* To secure correct signal levels on the pins used by the TWI - master when the system is in OFF mode, and when the TWI master is - disabled, these pins must be configured in the GPIO peripheral. - */ - TWIM_PIN_INIT(p_config->scl); - TWIM_PIN_INIT(p_config->sda); - NRF_TWIM_Type * p_twim = p_instance->p_twim; - nrf_twim_pins_set(p_twim, p_config->scl, p_config->sda); - nrf_twim_frequency_set(p_twim, - (nrf_twim_frequency_t)p_config->frequency); + if (!twim_pins_configure(p_twim, p_config)) + { + return NRFX_ERROR_INVALID_PARAM; + } + + nrf_twim_frequency_set(p_twim, (nrf_twim_frequency_t)p_config->frequency); if (p_cb->handler) { @@ -384,7 +420,7 @@ static nrfx_err_t twim_xfer(twim_control_block_t * p_cb, nrf_twim_task_t start_task = NRF_TWIM_TASK_STARTTX; p_cb->error = false; - if (!nrfx_is_in_ram(p_xfer_desc->p_primary_buf)) + if (p_xfer_desc->primary_length != 0 && !nrfx_is_in_ram(p_xfer_desc->p_primary_buf)) { err_code = NRFX_ERROR_INVALID_ADDR; NRFX_LOG_WARNING("Function: %s, error code: %s.", @@ -491,6 +527,10 @@ static nrfx_err_t twim_xfer(twim_control_block_t * p_cb, if (!(flags & NRFX_TWIM_FLAG_HOLD_XFER) && (p_xfer_desc->type != NRFX_TWIM_XFER_TXTX)) { nrf_twim_task_trigger(p_twim, start_task); + if (p_xfer_desc->primary_length == 0) + { + nrf_twim_task_trigger(p_twim, NRF_TWIM_TASK_STOP); + } } if (p_cb->handler) @@ -516,7 +556,7 @@ static nrfx_err_t twim_xfer(twim_control_block_t * p_cb, p_twim->FREQUENCY = 0; nrf_twim_event_clear(p_twim, NRF_TWIM_EVENT_TXSTARTED); nrf_twim_int_enable(p_twim, NRF_TWIM_INT_TXSTARTED_MASK); - } + } else { nrf_twim_frequency_set(p_twim, p_cb->bus_frequency); diff --git a/drivers/src/nrfx_twis.c b/drivers/src/nrfx_twis.c index 83043f670c..b4f865066d 100644 --- a/drivers/src/nrfx_twis.c +++ b/drivers/src/nrfx_twis.c @@ -1,7 +1,9 @@ /* - * Copyright (c) 2015 - 2020, Nordic Semiconductor ASA + * Copyright (c) 2015 - 2021, Nordic Semiconductor ASA * All rights reserved. * + * SPDX-License-Identifier: BSD-3-Clause + * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * diff --git a/drivers/src/nrfx_uart.c b/drivers/src/nrfx_uart.c index 420db0e3a5..4b671774f7 100644 --- a/drivers/src/nrfx_uart.c +++ b/drivers/src/nrfx_uart.c @@ -1,7 +1,9 @@ /* - * Copyright (c) 2015 - 2020, Nordic Semiconductor ASA + * Copyright (c) 2015 - 2021, Nordic Semiconductor ASA * All rights reserved. * + * SPDX-License-Identifier: BSD-3-Clause + * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * diff --git a/drivers/src/nrfx_uarte.c b/drivers/src/nrfx_uarte.c index 2f626f4229..b6a6c20b6d 100644 --- a/drivers/src/nrfx_uarte.c +++ b/drivers/src/nrfx_uarte.c @@ -1,7 +1,9 @@ /* - * Copyright (c) 2015 - 2020, Nordic Semiconductor ASA + * Copyright (c) 2015 - 2021, Nordic Semiconductor ASA * All rights reserved. * + * SPDX-License-Identifier: BSD-3-Clause + * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * diff --git a/drivers/src/nrfx_usbd.c b/drivers/src/nrfx_usbd.c index 469bef239a..60e952ce48 100644 --- a/drivers/src/nrfx_usbd.c +++ b/drivers/src/nrfx_usbd.c @@ -1,7 +1,9 @@ /* - * Copyright (c) 2016 - 2020, Nordic Semiconductor ASA + * Copyright (c) 2016 - 2021, Nordic Semiconductor ASA * All rights reserved. * + * SPDX-License-Identifier: BSD-3-Clause + * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * @@ -1940,10 +1942,10 @@ void nrfx_usbd_force_bus_wakeup(void) void nrfx_usbd_ep_max_packet_size_set(nrfx_usbd_ep_t ep, uint16_t size) { - /* Only power of 2 size allowed */ - NRFX_ASSERT((size & 0x01) == 0); - /* 0 allowed only for ISO endpoints */ - NRFX_ASSERT((size != 0) || NRF_USBD_EPISO_CHECK(ep)); + /* Only the power of 2 size allowed for Control Endpoints */ + NRFX_ASSERT((((size & (size - 1)) == 0) || (NRF_USBD_EP_NR_GET(ep) != 0))); + /* Only non zero size allowed for Control Endpoints */ + NRFX_ASSERT((size != 0) || (NRF_USBD_EP_NR_GET(ep) != 0)); /* Packet size cannot be higher than maximum buffer size */ NRFX_ASSERT((NRF_USBD_EPISO_CHECK(ep) && (size <= usbd_ep_iso_capacity(ep))) || (!NRF_USBD_EPISO_CHECK(ep) && (size <= NRFX_USBD_EPSIZE))); diff --git a/drivers/src/nrfx_usbd_errata.h b/drivers/src/nrfx_usbd_errata.h index 2e1512d4e9..a75f7e3475 100644 --- a/drivers/src/nrfx_usbd_errata.h +++ b/drivers/src/nrfx_usbd_errata.h @@ -1,7 +1,9 @@ /* - * Copyright (c) 2016 - 2020, Nordic Semiconductor ASA + * Copyright (c) 2016 - 2021, Nordic Semiconductor ASA * All rights reserved. * + * SPDX-License-Identifier: BSD-3-Clause + * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * diff --git a/drivers/src/nrfx_usbreg.c b/drivers/src/nrfx_usbreg.c index abac8b4f15..533cb4a300 100644 --- a/drivers/src/nrfx_usbreg.c +++ b/drivers/src/nrfx_usbreg.c @@ -1,7 +1,9 @@ /* - * Copyright (c) 2019 - 2020, Nordic Semiconductor ASA + * Copyright (c) 2019 - 2021, Nordic Semiconductor ASA * All rights reserved. * + * SPDX-License-Identifier: BSD-3-Clause + * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * diff --git a/drivers/src/nrfx_wdt.c b/drivers/src/nrfx_wdt.c index 63dec1cd84..6324388d69 100644 --- a/drivers/src/nrfx_wdt.c +++ b/drivers/src/nrfx_wdt.c @@ -1,7 +1,9 @@ /* - * Copyright (c) 2015 - 2020, Nordic Semiconductor ASA + * Copyright (c) 2015 - 2021, Nordic Semiconductor ASA * All rights reserved. * + * SPDX-License-Identifier: BSD-3-Clause + * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * diff --git a/drivers/src/prs/nrfx_prs.c b/drivers/src/prs/nrfx_prs.c index 37de8b91fc..d1065d2284 100644 --- a/drivers/src/prs/nrfx_prs.c +++ b/drivers/src/prs/nrfx_prs.c @@ -1,7 +1,9 @@ /* - * Copyright (c) 2017 - 2020, Nordic Semiconductor ASA + * Copyright (c) 2017 - 2021, Nordic Semiconductor ASA * All rights reserved. * + * SPDX-License-Identifier: BSD-3-Clause + * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * diff --git a/drivers/src/prs/nrfx_prs.h b/drivers/src/prs/nrfx_prs.h index 90e738e347..47ab8909f6 100644 --- a/drivers/src/prs/nrfx_prs.h +++ b/drivers/src/prs/nrfx_prs.h @@ -1,7 +1,9 @@ /* - * Copyright (c) 2017 - 2020, Nordic Semiconductor ASA + * Copyright (c) 2017 - 2021, Nordic Semiconductor ASA * All rights reserved. * + * SPDX-License-Identifier: BSD-3-Clause + * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * diff --git a/hal/nrf_aar.h b/hal/nrf_aar.h index 5d62761cd2..6ca4cb56e4 100644 --- a/hal/nrf_aar.h +++ b/hal/nrf_aar.h @@ -1,7 +1,9 @@ /* - * Copyright (c) 2019 - 2020, Nordic Semiconductor ASA + * Copyright (c) 2019 - 2021, Nordic Semiconductor ASA * All rights reserved. * + * SPDX-License-Identifier: BSD-3-Clause + * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * diff --git a/hal/nrf_acl.h b/hal/nrf_acl.h index 928267fac8..4465dad8d0 100644 --- a/hal/nrf_acl.h +++ b/hal/nrf_acl.h @@ -1,7 +1,9 @@ /* - * Copyright (c) 2018 - 2020, Nordic Semiconductor ASA + * Copyright (c) 2018 - 2021, Nordic Semiconductor ASA * All rights reserved. * + * SPDX-License-Identifier: BSD-3-Clause + * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * diff --git a/hal/nrf_adc.h b/hal/nrf_adc.h index 2313130dea..f7f76815ac 100644 --- a/hal/nrf_adc.h +++ b/hal/nrf_adc.h @@ -1,7 +1,9 @@ /* - * Copyright (c) 2014 - 2020, Nordic Semiconductor ASA + * Copyright (c) 2014 - 2021, Nordic Semiconductor ASA * All rights reserved. * + * SPDX-License-Identifier: BSD-3-Clause + * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * diff --git a/hal/nrf_bprot.h b/hal/nrf_bprot.h index 18d8247a27..03ecfe4d93 100644 --- a/hal/nrf_bprot.h +++ b/hal/nrf_bprot.h @@ -1,7 +1,9 @@ /* - * Copyright (c) 2019 - 2020, Nordic Semiconductor ASA + * Copyright (c) 2019 - 2021, Nordic Semiconductor ASA * All rights reserved. * + * SPDX-License-Identifier: BSD-3-Clause + * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * diff --git a/hal/nrf_cache.h b/hal/nrf_cache.h index 28d5b79853..07a13332e7 100644 --- a/hal/nrf_cache.h +++ b/hal/nrf_cache.h @@ -1,7 +1,9 @@ /* - * Copyright (c) 2019 - 2020, Nordic Semiconductor ASA + * Copyright (c) 2019 - 2021, Nordic Semiconductor ASA * All rights reserved. * + * SPDX-License-Identifier: BSD-3-Clause + * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * diff --git a/hal/nrf_ccm.h b/hal/nrf_ccm.h index 9ba10a2fec..5f53742799 100644 --- a/hal/nrf_ccm.h +++ b/hal/nrf_ccm.h @@ -1,7 +1,9 @@ /* - * Copyright (c) 2018 - 2020, Nordic Semiconductor ASA + * Copyright (c) 2018 - 2021, Nordic Semiconductor ASA * All rights reserved. * + * SPDX-License-Identifier: BSD-3-Clause + * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * diff --git a/hal/nrf_clock.h b/hal/nrf_clock.h index 68a31d2e36..3a934d7a1c 100644 --- a/hal/nrf_clock.h +++ b/hal/nrf_clock.h @@ -1,7 +1,9 @@ /* - * Copyright (c) 2015 - 2020, Nordic Semiconductor ASA + * Copyright (c) 2015 - 2021, Nordic Semiconductor ASA * All rights reserved. * + * SPDX-License-Identifier: BSD-3-Clause + * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * @@ -84,14 +86,6 @@ extern "C" { #define NRF_CLOCK_HAS_HFCLKAUDIO 0 #endif -#if (defined(CLOCK_HFCLKCTRL_HCLK_Msk) && !defined(NRF5340_XXAA_NETWORK)) \ - || defined(__NRFX_DOXYGEN__) -/** @brief Presence of HFCLK frequency configuration. */ -#define NRF_CLOCK_HAS_HFCLK_DIV 1 -#else -#define NRF_CLOCK_HAS_HFCLK_DIV 0 -#endif - #if defined(CLOCK_LFCLKALWAYSRUN_ALWAYSRUN_Msk) || defined(__NRFX_DOXYGEN__) /** @brief Presence of ALWAYSRUN registers. */ #define NRF_CLOCK_HAS_ALWAYSRUN 1 @@ -182,7 +176,7 @@ typedef enum #endif } nrf_clock_domain_t; -#if NRF_CLOCK_HAS_HFCLK_DIV || NRF_CLOCK_HAS_HFCLK192M +#if defined(CLOCK_FEATURE_HFCLK_DIVIDE_PRESENT) || NRF_CLOCK_HAS_HFCLK192M /** * @brief High-frequency clock frequency configuration. * @details Used by HFCLKCTRL and HFCLK192MCTRL registers. @@ -195,7 +189,7 @@ typedef enum NRF_CLOCK_HFCLK_DIV_4 = CLOCK_HFCLK192MCTRL_HCLK192M_Div4, /**< Divide HFCLK192M by 4 */ #endif } nrf_clock_hfclk_div_t; -#endif // NRF_CLOCK_HAS_HFCLK_DIV || NRF_CLOCK_HAS_HFCLK192M +#endif // defined(CLOCK_FEATURE_HFCLK_DIVIDE_PRESENT) || NRF_CLOCK_HAS_HFCLK192M /** * @brief Trigger status of task LFCLKSTART/HFCLKSTART. @@ -566,7 +560,7 @@ uint16_t nrf_clock_hfclkaudio_config_get(NRF_CLOCK_Type const * p_reg); NRF_STATIC_INLINE void nrf_clock_cal_timer_timeout_set(NRF_CLOCK_Type * p_reg, uint32_t interval); #endif -#if NRF_CLOCK_HAS_HFCLK_DIV +#if defined(CLOCK_FEATURE_HFCLK_DIVIDE_PRESENT) /** * @brief Function for changing the HFCLK frequency divider. * @@ -918,7 +912,7 @@ uint16_t nrf_clock_hfclkaudio_config_get(NRF_CLOCK_Type const * p_reg) } #endif -#if NRF_CLOCK_HAS_HFCLK_DIV +#if defined(CLOCK_FEATURE_HFCLK_DIVIDE_PRESENT) NRF_STATIC_INLINE void nrf_clock_hfclk_div_set(NRF_CLOCK_Type * p_reg, nrf_clock_hfclk_div_t divider) { diff --git a/hal/nrf_common.h b/hal/nrf_common.h index 063941c940..7f0dd3d776 100644 --- a/hal/nrf_common.h +++ b/hal/nrf_common.h @@ -1,7 +1,9 @@ /* - * Copyright (c) 2020, Nordic Semiconductor ASA + * Copyright (c) 2020 - 2021, Nordic Semiconductor ASA * All rights reserved. * + * SPDX-License-Identifier: BSD-3-Clause + * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * diff --git a/hal/nrf_comp.h b/hal/nrf_comp.h index 8a0781e188..f6b2e93c0a 100644 --- a/hal/nrf_comp.h +++ b/hal/nrf_comp.h @@ -1,7 +1,9 @@ /* - * Copyright (c) 2015 - 2020, Nordic Semiconductor ASA + * Copyright (c) 2015 - 2021, Nordic Semiconductor ASA * All rights reserved. * + * SPDX-License-Identifier: BSD-3-Clause + * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * diff --git a/hal/nrf_dcnf.h b/hal/nrf_dcnf.h index 79dc7c5b4d..7a5d64cd2e 100644 --- a/hal/nrf_dcnf.h +++ b/hal/nrf_dcnf.h @@ -1,7 +1,9 @@ /* - * Copyright (c) 2019 - 2020, Nordic Semiconductor ASA + * Copyright (c) 2019 - 2021, Nordic Semiconductor ASA * All rights reserved. * + * SPDX-License-Identifier: BSD-3-Clause + * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * diff --git a/hal/nrf_dppi.h b/hal/nrf_dppi.h index 9ff7e08a12..4539ba4270 100644 --- a/hal/nrf_dppi.h +++ b/hal/nrf_dppi.h @@ -1,7 +1,9 @@ /* - * Copyright (c) 2018 - 2020, Nordic Semiconductor ASA + * Copyright (c) 2018 - 2021, Nordic Semiconductor ASA * All rights reserved. * + * SPDX-License-Identifier: BSD-3-Clause + * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * @@ -137,6 +139,9 @@ NRF_STATIC_INLINE void nrf_dppi_channels_disable_all(NRF_DPPIC_Type * p_reg); * @brief Function for setting the subscribe configuration for a given * DPPI task. * + * @warning After setting the subscription for a given task, channel group configuration + * associated with this task cannot be modified until @ref nrf_dppi_subscribe_clear is used. + * * @param[in] p_reg Pointer to the structure of registers of the peripheral. * @param[in] task Task for which to set the configuration. * @param[in] channel Channel through which to subscribe events. @@ -161,6 +166,9 @@ NRF_STATIC_INLINE void nrf_dppi_subscribe_clear(NRF_DPPIC_Type * p_reg, nrf_dppi * The bits in @p channel_mask value correspond to particular channels. It means that * writing 1 to bit 0 includes channel 0, writing 1 to bit 1 includes channel 1 etc. * + * @warning Channel group configuration can be modified only if subscriptions for tasks + * associated with this group are disabled. + * * @param[in] p_reg Pointer to the structure of registers of the peripheral. * @param[in] channel_mask Channels to be included in the group. * @param[in] channel_group Channel group. @@ -176,6 +184,9 @@ NRF_STATIC_INLINE void nrf_dppi_channels_include_in_group(NRF_DPPIC_Type * * The bits in @c channel_mask value correspond to particular channels. It means that * writing 1 to bit 0 removes channel 0, writing 1 to bit 1 removes channel 1 etc. * + * @warning Channel group configuration can be modified only if subscriptions for tasks + * associated with this group are disabled. + * * @param[in] p_reg Pointer to the structure of registers of the peripheral. * @param[in] channel_mask Channels to be removed from the group. * @param[in] channel_group Channel group. @@ -187,6 +198,9 @@ NRF_STATIC_INLINE void nrf_dppi_channels_remove_from_group(NRF_DPPIC_Type * /** * @brief Function for removing all DPPI channels from a channel group. * + * @warning Channel group configuration can be modified only if subscriptions for tasks + * associated with this group are disabled. + * * @param[in] p_reg Pointer to the structure of registers of the peripheral. * @param[in] group Channel group. */ diff --git a/hal/nrf_ecb.h b/hal/nrf_ecb.h index 8d450ae809..4c81494918 100644 --- a/hal/nrf_ecb.h +++ b/hal/nrf_ecb.h @@ -1,7 +1,9 @@ /* - * Copyright (c) 2012 - 2020, Nordic Semiconductor ASA + * Copyright (c) 2012 - 2021, Nordic Semiconductor ASA * All rights reserved. * + * SPDX-License-Identifier: BSD-3-Clause + * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * diff --git a/hal/nrf_egu.h b/hal/nrf_egu.h index bdeebead65..ffce57a812 100644 --- a/hal/nrf_egu.h +++ b/hal/nrf_egu.h @@ -1,7 +1,9 @@ /* - * Copyright (c) 2015 - 2020, Nordic Semiconductor ASA + * Copyright (c) 2015 - 2021, Nordic Semiconductor ASA * All rights reserved. * + * SPDX-License-Identifier: BSD-3-Clause + * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * diff --git a/hal/nrf_ficr.h b/hal/nrf_ficr.h index 193c83adc9..d00f8d2218 100644 --- a/hal/nrf_ficr.h +++ b/hal/nrf_ficr.h @@ -1,7 +1,9 @@ /* - * Copyright (c) 2018 - 2020, Nordic Semiconductor ASA + * Copyright (c) 2018 - 2021, Nordic Semiconductor ASA * All rights reserved. * + * SPDX-License-Identifier: BSD-3-Clause + * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * diff --git a/hal/nrf_fpu.h b/hal/nrf_fpu.h index 14bcab8199..3a40bb79f8 100644 --- a/hal/nrf_fpu.h +++ b/hal/nrf_fpu.h @@ -1,7 +1,9 @@ /* - * Copyright (c) 2019 - 2020, Nordic Semiconductor ASA + * Copyright (c) 2019 - 2021, Nordic Semiconductor ASA * All rights reserved. * + * SPDX-License-Identifier: BSD-3-Clause + * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * diff --git a/hal/nrf_gpio.h b/hal/nrf_gpio.h index cc25f509e2..0364b6da43 100644 --- a/hal/nrf_gpio.h +++ b/hal/nrf_gpio.h @@ -1,7 +1,9 @@ /* - * Copyright (c) 2015 - 2020, Nordic Semiconductor ASA + * Copyright (c) 2015 - 2021, Nordic Semiconductor ASA * All rights reserved. * + * SPDX-License-Identifier: BSD-3-Clause + * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * @@ -274,8 +276,6 @@ NRF_STATIC_INLINE void nrf_gpio_pin_dir_set(uint32_t pin_number, nrf_gpio_pin_di /** * @brief Function for setting a GPIO pin. * - * For this function to have any effect, the pin must be configured as an output. - * * @param pin_number Specifies the pin number to be set. */ NRF_STATIC_INLINE void nrf_gpio_pin_set(uint32_t pin_number); @@ -283,8 +283,6 @@ NRF_STATIC_INLINE void nrf_gpio_pin_set(uint32_t pin_number); /** * @brief Function for clearing a GPIO pin. * - * For this function to have any effect, the pin must be configured as an output. - * * @param pin_number Specifies the pin number to clear. */ NRF_STATIC_INLINE void nrf_gpio_pin_clear(uint32_t pin_number); @@ -292,8 +290,6 @@ NRF_STATIC_INLINE void nrf_gpio_pin_clear(uint32_t pin_number); /** * @brief Function for toggling a GPIO pin. * - * For this function to have any effect, the pin must be configured as an output. - * * @param pin_number Specifies the pin number to toggle. */ NRF_STATIC_INLINE void nrf_gpio_pin_toggle(uint32_t pin_number); @@ -301,8 +297,6 @@ NRF_STATIC_INLINE void nrf_gpio_pin_toggle(uint32_t pin_number); /** * @brief Function for writing a value to a GPIO pin. * - * For this function to have any effect, the pin must be configured as an output. - * * @param pin_number Specifies the pin number to write. * @param value Specifies the value to be written to the pin. * @arg 0 Clears the pin. @@ -583,11 +577,19 @@ NRF_STATIC_INLINE void nrf_gpio_cfg( { NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number); - reg->PIN_CNF[pin_number] = ((uint32_t)dir << GPIO_PIN_CNF_DIR_Pos) - | ((uint32_t)input << GPIO_PIN_CNF_INPUT_Pos) - | ((uint32_t)pull << GPIO_PIN_CNF_PULL_Pos) - | ((uint32_t)drive << GPIO_PIN_CNF_DRIVE_Pos) - | ((uint32_t)sense << GPIO_PIN_CNF_SENSE_Pos); +#if defined(GPIO_PIN_CNF_MCUSEL_Msk) + /* Preserve MCUSEL setting. */ + uint32_t cnf = reg->PIN_CNF[pin_number] & GPIO_PIN_CNF_MCUSEL_Msk; +#else + uint32_t cnf = 0; +#endif + cnf |= ((uint32_t)dir << GPIO_PIN_CNF_DIR_Pos) | + ((uint32_t)input << GPIO_PIN_CNF_INPUT_Pos) | + ((uint32_t)pull << GPIO_PIN_CNF_PULL_Pos) | + ((uint32_t)drive << GPIO_PIN_CNF_DRIVE_Pos) | + ((uint32_t)sense << GPIO_PIN_CNF_SENSE_Pos); + + reg->PIN_CNF[pin_number] = cnf; } diff --git a/hal/nrf_gpiote.h b/hal/nrf_gpiote.h index fbd8b85277..6a58ac2e9c 100644 --- a/hal/nrf_gpiote.h +++ b/hal/nrf_gpiote.h @@ -1,7 +1,9 @@ /* - * Copyright (c) 2015 - 2020, Nordic Semiconductor ASA + * Copyright (c) 2015 - 2021, Nordic Semiconductor ASA * All rights reserved. * + * SPDX-License-Identifier: BSD-3-Clause + * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * diff --git a/hal/nrf_i2s.h b/hal/nrf_i2s.h index 7744ebb6a1..c74aeb3306 100644 --- a/hal/nrf_i2s.h +++ b/hal/nrf_i2s.h @@ -1,7 +1,9 @@ /* - * Copyright (c) 2015 - 2020, Nordic Semiconductor ASA + * Copyright (c) 2015 - 2021, Nordic Semiconductor ASA * All rights reserved. * + * SPDX-License-Identifier: BSD-3-Clause + * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * diff --git a/hal/nrf_ipc.h b/hal/nrf_ipc.h index dee5b10317..1f99c1a5bd 100644 --- a/hal/nrf_ipc.h +++ b/hal/nrf_ipc.h @@ -1,7 +1,9 @@ /* - * Copyright (c) 2019 - 2020, Nordic Semiconductor ASA + * Copyright (c) 2019 - 2021, Nordic Semiconductor ASA * All rights reserved. * + * SPDX-License-Identifier: BSD-3-Clause + * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * diff --git a/hal/nrf_kmu.h b/hal/nrf_kmu.h index 979f9f6395..bcf1cf9f6a 100644 --- a/hal/nrf_kmu.h +++ b/hal/nrf_kmu.h @@ -1,7 +1,9 @@ /* - * Copyright (c) 2018 - 2020, Nordic Semiconductor ASA + * Copyright (c) 2018 - 2021, Nordic Semiconductor ASA * All rights reserved. * + * SPDX-License-Identifier: BSD-3-Clause + * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * diff --git a/hal/nrf_lpcomp.h b/hal/nrf_lpcomp.h index 200d760b9a..38d5bab009 100644 --- a/hal/nrf_lpcomp.h +++ b/hal/nrf_lpcomp.h @@ -1,7 +1,9 @@ /* - * Copyright (c) 2014 - 2020, Nordic Semiconductor ASA + * Copyright (c) 2014 - 2021, Nordic Semiconductor ASA * All rights reserved. * + * SPDX-License-Identifier: BSD-3-Clause + * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * diff --git a/hal/nrf_mpu.h b/hal/nrf_mpu.h index b4bbce2de7..f2939cb02d 100644 --- a/hal/nrf_mpu.h +++ b/hal/nrf_mpu.h @@ -1,7 +1,9 @@ /* - * Copyright (c) 2019 - 2020, Nordic Semiconductor ASA + * Copyright (c) 2019 - 2021, Nordic Semiconductor ASA * All rights reserved. * + * SPDX-License-Identifier: BSD-3-Clause + * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * diff --git a/hal/nrf_mutex.h b/hal/nrf_mutex.h index 02e1a05402..9a51700202 100644 --- a/hal/nrf_mutex.h +++ b/hal/nrf_mutex.h @@ -1,7 +1,9 @@ /* - * Copyright (c) 2019 - 2020, Nordic Semiconductor ASA + * Copyright (c) 2019 - 2021, Nordic Semiconductor ASA * All rights reserved. * + * SPDX-License-Identifier: BSD-3-Clause + * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * diff --git a/hal/nrf_mwu.h b/hal/nrf_mwu.h index b25f1e225e..876a93f880 100644 --- a/hal/nrf_mwu.h +++ b/hal/nrf_mwu.h @@ -1,7 +1,9 @@ /* - * Copyright (c) 2019 - 2020, Nordic Semiconductor ASA + * Copyright (c) 2019 - 2021, Nordic Semiconductor ASA * All rights reserved. * + * SPDX-License-Identifier: BSD-3-Clause + * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * diff --git a/hal/nrf_nfct.h b/hal/nrf_nfct.h index 2b0f655c55..d68f6f8bc1 100644 --- a/hal/nrf_nfct.h +++ b/hal/nrf_nfct.h @@ -1,7 +1,9 @@ /* - * Copyright (c) 2018 - 2020, Nordic Semiconductor ASA + * Copyright (c) 2018 - 2021, Nordic Semiconductor ASA * All rights reserved. * + * SPDX-License-Identifier: BSD-3-Clause + * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * diff --git a/hal/nrf_nvmc.h b/hal/nrf_nvmc.h index 3f0ddfd52a..d9d16a2741 100644 --- a/hal/nrf_nvmc.h +++ b/hal/nrf_nvmc.h @@ -1,7 +1,9 @@ /* - * Copyright (c) 2012 - 2020, Nordic Semiconductor ASA + * Copyright (c) 2012 - 2021, Nordic Semiconductor ASA * All rights reserved. * + * SPDX-License-Identifier: BSD-3-Clause + * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * diff --git a/hal/nrf_oscillators.h b/hal/nrf_oscillators.h index d17ac606ce..b00b1b6b4f 100644 --- a/hal/nrf_oscillators.h +++ b/hal/nrf_oscillators.h @@ -1,7 +1,9 @@ /* - * Copyright (c) 2019 - 2020, Nordic Semiconductor ASA + * Copyright (c) 2019 - 2021, Nordic Semiconductor ASA * All rights reserved. * + * SPDX-License-Identifier: BSD-3-Clause + * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * @@ -51,7 +53,7 @@ typedef enum NRF_OSCILLATORS_LFXO_CAP_EXTERNAL = OSCILLATORS_XOSC32KI_INTCAP_INTCAP_External, ///< Use external capacitors. NRF_OSCILLATORS_LFXO_CAP_6PF = OSCILLATORS_XOSC32KI_INTCAP_INTCAP_C6PF, ///< Use 6 pF internal capacitors. NRF_OSCILLATORS_LFXO_CAP_7PF = OSCILLATORS_XOSC32KI_INTCAP_INTCAP_C7PF, ///< Use 7 pF internal capacitors. - NRF_OSCILLATORS_LFXO_CAP_11PF = OSCILLATORS_XOSC32KI_INTCAP_INTCAP_C11PF, ///< Use 11 pF internal capacitors. + NRF_OSCILLATORS_LFXO_CAP_9PF = OSCILLATORS_XOSC32KI_INTCAP_INTCAP_C9PF, ///< Use 9 pF internal capacitors. } nrf_oscillators_lfxo_cap_t; /** diff --git a/hal/nrf_pdm.h b/hal/nrf_pdm.h index 0a36766f5a..fb628cbdf1 100644 --- a/hal/nrf_pdm.h +++ b/hal/nrf_pdm.h @@ -1,7 +1,9 @@ /* - * Copyright (c) 2015 - 2020, Nordic Semiconductor ASA + * Copyright (c) 2015 - 2021, Nordic Semiconductor ASA * All rights reserved. * + * SPDX-License-Identifier: BSD-3-Clause + * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * diff --git a/hal/nrf_power.h b/hal/nrf_power.h index 5fd6433f61..8c871aba2f 100644 --- a/hal/nrf_power.h +++ b/hal/nrf_power.h @@ -1,7 +1,9 @@ /* - * Copyright (c) 2017 - 2020, Nordic Semiconductor ASA + * Copyright (c) 2017 - 2021, Nordic Semiconductor ASA * All rights reserved. * + * SPDX-License-Identifier: BSD-3-Clause + * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * diff --git a/hal/nrf_ppi.h b/hal/nrf_ppi.h index 2284c35df6..e2059b0f0f 100644 --- a/hal/nrf_ppi.h +++ b/hal/nrf_ppi.h @@ -1,7 +1,9 @@ /* - * Copyright (c) 2015 - 2020, Nordic Semiconductor ASA + * Copyright (c) 2015 - 2021, Nordic Semiconductor ASA * All rights reserved. * + * SPDX-License-Identifier: BSD-3-Clause + * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * diff --git a/hal/nrf_pwm.h b/hal/nrf_pwm.h index b9fb052779..c895d5cb12 100644 --- a/hal/nrf_pwm.h +++ b/hal/nrf_pwm.h @@ -1,7 +1,9 @@ /* - * Copyright (c) 2015 - 2020, Nordic Semiconductor ASA + * Copyright (c) 2015 - 2021, Nordic Semiconductor ASA * All rights reserved. * + * SPDX-License-Identifier: BSD-3-Clause + * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * diff --git a/hal/nrf_qdec.h b/hal/nrf_qdec.h index 363d1229fd..63ec459bf9 100644 --- a/hal/nrf_qdec.h +++ b/hal/nrf_qdec.h @@ -1,7 +1,9 @@ /* - * Copyright (c) 2014 - 2020, Nordic Semiconductor ASA + * Copyright (c) 2014 - 2021, Nordic Semiconductor ASA * All rights reserved. * + * SPDX-License-Identifier: BSD-3-Clause + * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * @@ -119,15 +121,18 @@ typedef enum /** @brief Available report periods. */ typedef enum { - NRF_QDEC_REPORTPER_10 = QDEC_REPORTPER_REPORTPER_10Smpl, /**< QDEC report period 10 samples. */ - NRF_QDEC_REPORTPER_40 = QDEC_REPORTPER_REPORTPER_40Smpl, /**< QDEC report period 40 samples. */ - NRF_QDEC_REPORTPER_80 = QDEC_REPORTPER_REPORTPER_80Smpl, /**< QDEC report period 80 samples. */ - NRF_QDEC_REPORTPER_120 = QDEC_REPORTPER_REPORTPER_120Smpl, /**< QDEC report period 120 samples. */ - NRF_QDEC_REPORTPER_160 = QDEC_REPORTPER_REPORTPER_160Smpl, /**< QDEC report period 160 samples. */ - NRF_QDEC_REPORTPER_200 = QDEC_REPORTPER_REPORTPER_200Smpl, /**< QDEC report period 200 samples. */ - NRF_QDEC_REPORTPER_240 = QDEC_REPORTPER_REPORTPER_240Smpl, /**< QDEC report period 240 samples. */ - NRF_QDEC_REPORTPER_280 = QDEC_REPORTPER_REPORTPER_280Smpl, /**< QDEC report period 280 samples. */ - NRF_QDEC_REPORTPER_DISABLED /**< QDEC reporting disabled. */ +#if defined(QDEC_REPORTPER_REPORTPER_1Smpl) || defined(__NRFX_DOXYGEN__) + NRF_QDEC_REPORTPER_1 = QDEC_REPORTPER_REPORTPER_1Smpl, /**< QDEC report period 1 sample. */ +#endif + NRF_QDEC_REPORTPER_10 = QDEC_REPORTPER_REPORTPER_10Smpl, /**< QDEC report period 10 samples. */ + NRF_QDEC_REPORTPER_40 = QDEC_REPORTPER_REPORTPER_40Smpl, /**< QDEC report period 40 samples. */ + NRF_QDEC_REPORTPER_80 = QDEC_REPORTPER_REPORTPER_80Smpl, /**< QDEC report period 80 samples. */ + NRF_QDEC_REPORTPER_120 = QDEC_REPORTPER_REPORTPER_120Smpl, /**< QDEC report period 120 samples. */ + NRF_QDEC_REPORTPER_160 = QDEC_REPORTPER_REPORTPER_160Smpl, /**< QDEC report period 160 samples. */ + NRF_QDEC_REPORTPER_200 = QDEC_REPORTPER_REPORTPER_200Smpl, /**< QDEC report period 200 samples. */ + NRF_QDEC_REPORTPER_240 = QDEC_REPORTPER_REPORTPER_240Smpl, /**< QDEC report period 240 samples. */ + NRF_QDEC_REPORTPER_280 = QDEC_REPORTPER_REPORTPER_280Smpl, /**< QDEC report period 280 samples. */ + NRF_QDEC_REPORTPER_DISABLED = (QDEC_REPORTPER_REPORTPER_Msk >> QDEC_REPORTPER_REPORTPER_Pos) + 1 /**< QDEC reporting disabled. Deprecated. */ } nrf_qdec_reportper_t; /** diff --git a/hal/nrf_qspi.h b/hal/nrf_qspi.h index 4ee209e0a6..c0821c030c 100644 --- a/hal/nrf_qspi.h +++ b/hal/nrf_qspi.h @@ -1,7 +1,9 @@ /* - * Copyright (c) 2016 - 2020, Nordic Semiconductor ASA + * Copyright (c) 2016 - 2021, Nordic Semiconductor ASA * All rights reserved. * + * SPDX-License-Identifier: BSD-3-Clause + * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * @@ -395,6 +397,15 @@ NRF_STATIC_INLINE void nrf_qspi_disable(NRF_QSPI_Type * p_reg); NRF_STATIC_INLINE void nrf_qspi_pins_set(NRF_QSPI_Type * p_reg, nrf_qspi_pins_t const * p_pins); +/** + * @brief Function for getting the currently configured QSPI pins. + * + * @param[in] p_reg Pointer to the structure of registers of the peripheral. + * @param[out] p_pins Pointer to the pins configuration structure to be filled with QSPI pins. + */ +NRF_STATIC_INLINE void nrf_qspi_pins_get(NRF_QSPI_Type const * p_reg, + nrf_qspi_pins_t * p_pins); + /** * @brief Function for setting the QSPI XIPOFFSET register. * @@ -414,6 +425,23 @@ NRF_STATIC_INLINE void nrf_qspi_xip_offset_set(NRF_QSPI_Type * p_reg, NRF_STATIC_INLINE void nrf_qspi_ifconfig0_set(NRF_QSPI_Type * p_reg, nrf_qspi_prot_conf_t const * p_config); +/** + * @brief Function for setting the explicit value of the QSPI IFCONFIG0 register. + * + * @param[in] p_reg Pointer to the structure of registers of the peripheral. + * @param[in] regval Register value to be set. + */ +NRF_STATIC_INLINE void nrf_qspi_ifconfig0_raw_set(NRF_QSPI_Type * p_reg, uint32_t regval); + +/** + * @brief Function for getting the explicit value of the QSPI IFCONFIG0 register. + * + * @param[in] p_reg Pointer to the structure of registers of the peripheral. + * + * @return Value of IFCONFIG0 register. + */ +NRF_STATIC_INLINE uint32_t nrf_qspi_ifconfig0_raw_get(NRF_QSPI_Type const * p_reg); + /** * @brief Function for setting the QSPI IFCONFIG1 register. * @@ -479,6 +507,24 @@ NRF_STATIC_INLINE void nrf_qspi_erase_ptr_set(NRF_QSPI_Type * p_reg, uint32_t erase_addr, nrf_qspi_erase_len_t len); +/** + * @brief Function for getting the currently configured erase pointer. + * + * @param[in] p_reg Pointer to the structure of registers of the peripheral. + * + * @return Erase pointer. + */ +NRF_STATIC_INLINE uint32_t nrf_qspi_erase_ptr_get(NRF_QSPI_Type const * p_reg); + +/** + * @brief Function for getting the currently configured erase length. + * + * @param[in] p_reg Pointer to the structure of registers of the peripheral. + * + * @return Erase length. + */ +NRF_STATIC_INLINE nrf_qspi_erase_len_t nrf_qspi_erase_len_get(NRF_QSPI_Type const * p_reg); + /** * @brief Function for getting the peripheral status register. * @@ -624,6 +670,15 @@ NRF_STATIC_INLINE void nrf_qspi_dma_encryption_configure(NRF_QSPI_Type * NRF_STATIC_INLINE void nrf_qspi_dma_encryption_set(NRF_QSPI_Type * p_reg, bool enable); #endif +/** + * @brief Function for setting the timing related to sampling of the input serial data. + * + * @param[in] p_reg Pointer to the structure of registers of the peripheral. + * @param[in] rxdelay Number of 64 MHz cycles (15.625 ns) delay from the the rising edge of the clock + * until the input serial data is sampled. + */ +NRF_STATIC_INLINE void nrf_qspi_iftiming_set(NRF_QSPI_Type * p_reg, uint8_t rxdelay); + #ifndef NRF_DECLARE_ONLY NRF_STATIC_INLINE void nrf_qspi_task_trigger(NRF_QSPI_Type * p_reg, nrf_qspi_task_t task) @@ -693,6 +748,17 @@ NRF_STATIC_INLINE void nrf_qspi_pins_set(NRF_QSPI_Type * p_reg, nrf_qspi_pins_t p_reg->PSEL.IO3 = NRF_QSPI_PIN_VAL(p_pins->io3_pin); } +NRF_STATIC_INLINE void nrf_qspi_pins_get(NRF_QSPI_Type const * p_reg, + nrf_qspi_pins_t * p_pins) +{ + p_pins->sck_pin = (uint8_t)p_reg->PSEL.SCK; + p_pins->csn_pin = (uint8_t)p_reg->PSEL.CSN; + p_pins->io0_pin = (uint8_t)p_reg->PSEL.IO0; + p_pins->io1_pin = (uint8_t)p_reg->PSEL.IO1; + p_pins->io2_pin = (uint8_t)p_reg->PSEL.IO2; + p_pins->io3_pin = (uint8_t)p_reg->PSEL.IO3; +} + NRF_STATIC_INLINE void nrf_qspi_xip_offset_set(NRF_QSPI_Type * p_reg, uint32_t xip_offset) { @@ -710,6 +776,16 @@ NRF_STATIC_INLINE void nrf_qspi_ifconfig0_set(NRF_QSPI_Type * p_reg p_reg->IFCONFIG0 = config; } +NRF_STATIC_INLINE void nrf_qspi_ifconfig0_raw_set(NRF_QSPI_Type * p_reg, uint32_t regval) +{ + p_reg->IFCONFIG0 = regval; +} + +NRF_STATIC_INLINE uint32_t nrf_qspi_ifconfig0_raw_get(NRF_QSPI_Type const * p_reg) +{ + return p_reg->IFCONFIG0; +} + NRF_STATIC_INLINE void nrf_qspi_ifconfig1_set(NRF_QSPI_Type * p_reg, nrf_qspi_phy_conf_t const * p_config) { @@ -764,6 +840,16 @@ NRF_STATIC_INLINE void nrf_qspi_erase_ptr_set(NRF_QSPI_Type * p_reg, p_reg->ERASE.LEN = len; } +NRF_STATIC_INLINE uint32_t nrf_qspi_erase_ptr_get(NRF_QSPI_Type const * p_reg) +{ + return p_reg->ERASE.PTR; +} + +NRF_STATIC_INLINE nrf_qspi_erase_len_t nrf_qspi_erase_len_get(NRF_QSPI_Type const * p_reg) +{ + return (nrf_qspi_erase_len_t)p_reg->ERASE.LEN; +} + NRF_STATIC_INLINE uint32_t nrf_qspi_status_reg_get(NRF_QSPI_Type const * p_reg) { return p_reg->STATUS; @@ -955,6 +1041,12 @@ NRF_STATIC_INLINE void nrf_qspi_dma_encryption_set(NRF_QSPI_Type * p_reg, bool e : QSPI_DMA_ENC_ENABLE_ENABLE_Disabled << QSPI_DMA_ENC_ENABLE_ENABLE_Pos); } #endif + +NRF_STATIC_INLINE void nrf_qspi_iftiming_set(NRF_QSPI_Type * p_reg, uint8_t rxdelay) +{ + p_reg->IFTIMING = ((uint32_t)rxdelay << QSPI_IFTIMING_RXDELAY_Pos) & QSPI_IFTIMING_RXDELAY_Msk; +} + #endif // NRF_DECLARE_ONLY /** @} */ diff --git a/hal/nrf_radio.h b/hal/nrf_radio.h index d073fab7e3..ddb5f3a8f5 100644 --- a/hal/nrf_radio.h +++ b/hal/nrf_radio.h @@ -1,7 +1,9 @@ /* - * Copyright (c) 2018 - 2020, Nordic Semiconductor ASA + * Copyright (c) 2018 - 2021, Nordic Semiconductor ASA * All rights reserved. * + * SPDX-License-Identifier: BSD-3-Clause + * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * @@ -1893,7 +1895,8 @@ NRF_STATIC_INLINE void nrf_radio_cca_configure(NRF_RADIO_Type * p_reg, NRF_STATIC_INLINE void nrf_radio_power_set(NRF_RADIO_Type * p_reg, bool radio_power) { - p_reg->POWER = (uint32_t) radio_power; + p_reg->POWER = (radio_power ? RADIO_POWER_POWER_Enabled : RADIO_POWER_POWER_Disabled) + << RADIO_POWER_POWER_Pos; } #if defined(RADIO_CTESTATUS_CTETIME_Msk) diff --git a/hal/nrf_regulators.h b/hal/nrf_regulators.h index 3efb462134..7f9c379904 100644 --- a/hal/nrf_regulators.h +++ b/hal/nrf_regulators.h @@ -1,7 +1,9 @@ /* - * Copyright (c) 2018 - 2020, Nordic Semiconductor ASA + * Copyright (c) 2018 - 2021, Nordic Semiconductor ASA * All rights reserved. * + * SPDX-License-Identifier: BSD-3-Clause + * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * diff --git a/hal/nrf_reset.h b/hal/nrf_reset.h index a9e83ac633..870fd12daf 100644 --- a/hal/nrf_reset.h +++ b/hal/nrf_reset.h @@ -1,7 +1,9 @@ /* - * Copyright (c) 2019 - 2020, Nordic Semiconductor ASA + * Copyright (c) 2019 - 2021, Nordic Semiconductor ASA * All rights reserved. * + * SPDX-License-Identifier: BSD-3-Clause + * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * @@ -38,6 +40,13 @@ extern "C" { #endif +/** + * @defgroup nrf_reset_hal RESET HAL + * @{ + * @ingroup nrf_power + * @brief Hardware access layer for managing the RESET peripheral. + */ + #if defined(NRF5340_XXAA_NETWORK) || defined(__NRFX_DOXYGEN__) /** @brief Presence of Network core RESET functionality. */ #define NRF_RESET_HAS_NETWORK 1 @@ -52,13 +61,6 @@ extern "C" { #define NRF_RESET_HAS_APPLICATION 0 #endif -/** - * @defgroup nrf_reset_hal RESET HAL - * @{ - * @ingroup nrf_reset - * @brief Hardware access layer for managing the RESET peripheral. - */ - /** @brief Reset reason bit masks. */ typedef enum { diff --git a/hal/nrf_rng.h b/hal/nrf_rng.h index 08da7a2ed7..c01277ec63 100644 --- a/hal/nrf_rng.h +++ b/hal/nrf_rng.h @@ -1,7 +1,9 @@ /* - * Copyright (c) 2014 - 2020, Nordic Semiconductor ASA + * Copyright (c) 2014 - 2021, Nordic Semiconductor ASA * All rights reserved. * + * SPDX-License-Identifier: BSD-3-Clause + * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * diff --git a/hal/nrf_rtc.h b/hal/nrf_rtc.h index e184596fc1..0e1cec5e38 100644 --- a/hal/nrf_rtc.h +++ b/hal/nrf_rtc.h @@ -1,7 +1,9 @@ /* - * Copyright (c) 2014 - 2020, Nordic Semiconductor ASA + * Copyright (c) 2014 - 2021, Nordic Semiconductor ASA * All rights reserved. * + * SPDX-License-Identifier: BSD-3-Clause + * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * diff --git a/hal/nrf_saadc.h b/hal/nrf_saadc.h index 2e662f5128..4b6c66f511 100644 --- a/hal/nrf_saadc.h +++ b/hal/nrf_saadc.h @@ -1,7 +1,9 @@ /* - * Copyright (c) 2015 - 2020, Nordic Semiconductor ASA + * Copyright (c) 2015 - 2021, Nordic Semiconductor ASA * All rights reserved. * + * SPDX-License-Identifier: BSD-3-Clause + * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * diff --git a/hal/nrf_spi.h b/hal/nrf_spi.h index fd1871f383..4c4e380b0c 100644 --- a/hal/nrf_spi.h +++ b/hal/nrf_spi.h @@ -1,7 +1,9 @@ /* - * Copyright (c) 2015 - 2020, Nordic Semiconductor ASA + * Copyright (c) 2015 - 2021, Nordic Semiconductor ASA * All rights reserved. * + * SPDX-License-Identifier: BSD-3-Clause + * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * diff --git a/hal/nrf_spim.h b/hal/nrf_spim.h index c5a6a889bc..64bced046f 100644 --- a/hal/nrf_spim.h +++ b/hal/nrf_spim.h @@ -1,7 +1,9 @@ /* - * Copyright (c) 2015 - 2020, Nordic Semiconductor ASA + * Copyright (c) 2015 - 2021, Nordic Semiconductor ASA * All rights reserved. * + * SPDX-License-Identifier: BSD-3-Clause + * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * @@ -45,6 +47,13 @@ extern "C" { * @brief Hardware access layer for managing the SPIM peripheral. */ +#if defined(SPIM_FREQUENCY_FREQUENCY_M32) || defined(__NRFX_DOXYGEN__) +/** @brief Symbol indicating whether 32 MHz clock frequency is available. */ +#define NRF_SPIM_HAS_32_MHZ_FREQ 1 +#else +#define NRF_SPIM_HAS_32_MHZ_FREQ 0 +#endif + /** * @brief This value can be used as a parameter for the @ref nrf_spim_pins_set * function to specify that a given SPI signal (SCK, MOSI, or MISO) diff --git a/hal/nrf_spis.h b/hal/nrf_spis.h index 18b692b969..592410e8d8 100644 --- a/hal/nrf_spis.h +++ b/hal/nrf_spis.h @@ -1,7 +1,9 @@ /* - * Copyright (c) 2015 - 2020, Nordic Semiconductor ASA + * Copyright (c) 2015 - 2021, Nordic Semiconductor ASA * All rights reserved. * + * SPDX-License-Identifier: BSD-3-Clause + * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * diff --git a/hal/nrf_spu.h b/hal/nrf_spu.h index 86e66ff542..d2558aab98 100644 --- a/hal/nrf_spu.h +++ b/hal/nrf_spu.h @@ -1,7 +1,9 @@ /* - * Copyright (c) 2018 - 2020, Nordic Semiconductor ASA + * Copyright (c) 2018 - 2021, Nordic Semiconductor ASA * All rights reserved. * + * SPDX-License-Identifier: BSD-3-Clause + * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * diff --git a/hal/nrf_systick.h b/hal/nrf_systick.h index 826985467b..189caeb0cd 100644 --- a/hal/nrf_systick.h +++ b/hal/nrf_systick.h @@ -1,7 +1,9 @@ /* - * Copyright (c) 2016 - 2020, Nordic Semiconductor ASA + * Copyright (c) 2016 - 2021, Nordic Semiconductor ASA * All rights reserved. * + * SPDX-License-Identifier: BSD-3-Clause + * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * diff --git a/hal/nrf_temp.h b/hal/nrf_temp.h index e2aad0f301..7f1262f29d 100644 --- a/hal/nrf_temp.h +++ b/hal/nrf_temp.h @@ -1,7 +1,9 @@ /* - * Copyright (c) 2012 - 2020, Nordic Semiconductor ASA + * Copyright (c) 2012 - 2021, Nordic Semiconductor ASA * All rights reserved. * + * SPDX-License-Identifier: BSD-3-Clause + * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * diff --git a/hal/nrf_timer.h b/hal/nrf_timer.h index eda7fe2e63..64da71c586 100644 --- a/hal/nrf_timer.h +++ b/hal/nrf_timer.h @@ -1,7 +1,9 @@ /* - * Copyright (c) 2014 - 2020, Nordic Semiconductor ASA + * Copyright (c) 2014 - 2021, Nordic Semiconductor ASA * All rights reserved. * + * SPDX-License-Identifier: BSD-3-Clause + * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * diff --git a/hal/nrf_twi.h b/hal/nrf_twi.h index 107c391bb1..dd3220f779 100644 --- a/hal/nrf_twi.h +++ b/hal/nrf_twi.h @@ -1,7 +1,9 @@ /* - * Copyright (c) 2015 - 2020, Nordic Semiconductor ASA + * Copyright (c) 2015 - 2021, Nordic Semiconductor ASA * All rights reserved. * + * SPDX-License-Identifier: BSD-3-Clause + * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * diff --git a/hal/nrf_twim.h b/hal/nrf_twim.h index c5ed69b731..e3b2e2a659 100644 --- a/hal/nrf_twim.h +++ b/hal/nrf_twim.h @@ -1,7 +1,9 @@ /* - * Copyright (c) 2015 - 2020, Nordic Semiconductor ASA + * Copyright (c) 2015 - 2021, Nordic Semiconductor ASA * All rights reserved. * + * SPDX-License-Identifier: BSD-3-Clause + * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * @@ -45,6 +47,13 @@ extern "C" { * @brief Hardware access layer for managing the TWIM peripheral. */ +#if defined(TWIM_FREQUENCY_FREQUENCY_K1000) || defined(__NRFX_DOXYGEN__) +/** @brief Symbol indicating whether 1000 kHz clock frequency is available. */ +#define NRF_TWIM_HAS_1000_KHZ_FREQ 1 +#else +#define NRF_TWIM_HAS_1000_KHZ_FREQ 0 +#endif + /** @brief TWIM tasks. */ typedef enum { @@ -107,7 +116,7 @@ typedef enum NRF_TWIM_FREQ_100K = TWIM_FREQUENCY_FREQUENCY_K100, ///< 100 kbps. NRF_TWIM_FREQ_250K = TWIM_FREQUENCY_FREQUENCY_K250, ///< 250 kbps. NRF_TWIM_FREQ_400K = TWIM_FREQUENCY_FREQUENCY_K400, ///< 400 kbps. -#if defined(TWIM_FREQUENCY_FREQUENCY_K1000) || defined(__NRFX_DOXYGEN__) +#if NRF_TWIM_HAS_1000_KHZ_FREQ NRF_TWIM_FREQ_1000K = TWIM_FREQUENCY_FREQUENCY_K1000 ///< 1000 kbps. #endif } nrf_twim_frequency_t; diff --git a/hal/nrf_twis.h b/hal/nrf_twis.h index 6b5d5c34eb..45f2954941 100644 --- a/hal/nrf_twis.h +++ b/hal/nrf_twis.h @@ -1,7 +1,9 @@ /* - * Copyright (c) 2015 - 2020, Nordic Semiconductor ASA + * Copyright (c) 2015 - 2021, Nordic Semiconductor ASA * All rights reserved. * + * SPDX-License-Identifier: BSD-3-Clause + * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * diff --git a/hal/nrf_uart.h b/hal/nrf_uart.h index cbafa0a8ac..1d632d3cec 100644 --- a/hal/nrf_uart.h +++ b/hal/nrf_uart.h @@ -1,7 +1,9 @@ /* - * Copyright (c) 2015 - 2020, Nordic Semiconductor ASA + * Copyright (c) 2015 - 2021, Nordic Semiconductor ASA * All rights reserved. * + * SPDX-License-Identifier: BSD-3-Clause + * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * diff --git a/hal/nrf_uarte.h b/hal/nrf_uarte.h index fd1848d23d..3371443162 100644 --- a/hal/nrf_uarte.h +++ b/hal/nrf_uarte.h @@ -1,7 +1,9 @@ /* - * Copyright (c) 2015 - 2020, Nordic Semiconductor ASA + * Copyright (c) 2015 - 2021, Nordic Semiconductor ASA * All rights reserved. * + * SPDX-License-Identifier: BSD-3-Clause + * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * diff --git a/hal/nrf_usbd.h b/hal/nrf_usbd.h index 71c56c2eac..e0120609c4 100644 --- a/hal/nrf_usbd.h +++ b/hal/nrf_usbd.h @@ -1,7 +1,9 @@ /* - * Copyright (c) 2017 - 2020, Nordic Semiconductor ASA + * Copyright (c) 2017 - 2021, Nordic Semiconductor ASA * All rights reserved. * + * SPDX-License-Identifier: BSD-3-Clause + * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * diff --git a/hal/nrf_usbreg.h b/hal/nrf_usbreg.h index be811e1677..574d4b328b 100644 --- a/hal/nrf_usbreg.h +++ b/hal/nrf_usbreg.h @@ -1,7 +1,9 @@ /* - * Copyright (c) 2019 - 2020, Nordic Semiconductor ASA + * Copyright (c) 2019 - 2021, Nordic Semiconductor ASA * All rights reserved. * + * SPDX-License-Identifier: BSD-3-Clause + * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * diff --git a/hal/nrf_vmc.h b/hal/nrf_vmc.h index add75efc3a..54b103b73c 100644 --- a/hal/nrf_vmc.h +++ b/hal/nrf_vmc.h @@ -1,7 +1,9 @@ /* - * Copyright (c) 2018 - 2020, Nordic Semiconductor ASA + * Copyright (c) 2018 - 2021, Nordic Semiconductor ASA * All rights reserved. * + * SPDX-License-Identifier: BSD-3-Clause + * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * diff --git a/hal/nrf_vreqctrl.h b/hal/nrf_vreqctrl.h index be9d2e549e..3bcdfd30ef 100644 --- a/hal/nrf_vreqctrl.h +++ b/hal/nrf_vreqctrl.h @@ -1,7 +1,9 @@ /* - * Copyright (c) 2019 - 2020, Nordic Semiconductor ASA + * Copyright (c) 2019 - 2021, Nordic Semiconductor ASA * All rights reserved. * + * SPDX-License-Identifier: BSD-3-Clause + * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * diff --git a/hal/nrf_wdt.h b/hal/nrf_wdt.h index 8df6be8295..3343d1c7f8 100644 --- a/hal/nrf_wdt.h +++ b/hal/nrf_wdt.h @@ -1,7 +1,9 @@ /* - * Copyright (c) 2015 - 2020, Nordic Semiconductor ASA + * Copyright (c) 2015 - 2021, Nordic Semiconductor ASA * All rights reserved. * + * SPDX-License-Identifier: BSD-3-Clause + * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * diff --git a/helpers/nrfx_gppi.h b/helpers/nrfx_gppi.h index eb8b600d68..3b35bc9cb6 100644 --- a/helpers/nrfx_gppi.h +++ b/helpers/nrfx_gppi.h @@ -1,7 +1,9 @@ /* - * Copyright (c) 2019 - 2020, Nordic Semiconductor ASA + * Copyright (c) 2019 - 2021, Nordic Semiconductor ASA * All rights reserved. * + * SPDX-License-Identifier: BSD-3-Clause + * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * diff --git a/helpers/nrfx_reset_reason.h b/helpers/nrfx_reset_reason.h index 7b12be601b..c5f81b6194 100644 --- a/helpers/nrfx_reset_reason.h +++ b/helpers/nrfx_reset_reason.h @@ -1,7 +1,9 @@ /* - * Copyright (c) 2020, Nordic Semiconductor ASA + * Copyright (c) 2020 - 2021, Nordic Semiconductor ASA * All rights reserved. * + * SPDX-License-Identifier: BSD-3-Clause + * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * @@ -60,9 +62,9 @@ typedef enum NRFX_RESET_REASON_RESETPIN_MASK = RESET_RESETREAS_RESETPIN_Msk, /**< Reset from pin-reset detected. */ NRFX_RESET_REASON_DOG0_MASK = RESET_RESETREAS_DOG0_Msk, - /**< Reset from watchdog/application watchdong timer 0 detected. */ + /**< Reset from watchdog/application watchdog timer 0 detected. */ NRFX_RESET_REASON_DOG_MASK = NRFX_RESET_REASON_DOG0_MASK, - /**< Reset from watchdog/application watchdong timer 0 detected. */ + /**< Reset from watchdog/application watchdog timer 0 detected. */ NRFX_RESET_REASON_CTRLAP_MASK = RESET_RESETREAS_CTRLAP_Msk, /**< Reset from application CTRL-AP detected. */ NRFX_RESETREAS_SREQ_MASK = RESET_RESETREAS_SREQ_Msk, diff --git a/mdk/arm_startup_nrf51.s b/mdk/arm_startup_nrf51.s index 12f949a428..cad23a6595 100644 --- a/mdk/arm_startup_nrf51.s +++ b/mdk/arm_startup_nrf51.s @@ -1,4 +1,4 @@ -; Copyright (c) 2009-2020 ARM Limited. All rights reserved. +; Copyright (c) 2009-2021 ARM Limited. All rights reserved. ; ; SPDX-License-Identifier: Apache-2.0 ; diff --git a/mdk/arm_startup_nrf52.s b/mdk/arm_startup_nrf52.s index cf44298e40..269d43f6fe 100644 --- a/mdk/arm_startup_nrf52.s +++ b/mdk/arm_startup_nrf52.s @@ -1,4 +1,4 @@ -; Copyright (c) 2009-2020 ARM Limited. All rights reserved. +; Copyright (c) 2009-2021 ARM Limited. All rights reserved. ; ; SPDX-License-Identifier: Apache-2.0 ; diff --git a/mdk/arm_startup_nrf52805.s b/mdk/arm_startup_nrf52805.s index bcbbfc4508..b62f6ce323 100644 --- a/mdk/arm_startup_nrf52805.s +++ b/mdk/arm_startup_nrf52805.s @@ -1,4 +1,4 @@ -; Copyright (c) 2009-2020 ARM Limited. All rights reserved. +; Copyright (c) 2009-2021 ARM Limited. All rights reserved. ; ; SPDX-License-Identifier: Apache-2.0 ; diff --git a/mdk/arm_startup_nrf52810.s b/mdk/arm_startup_nrf52810.s index 636e8708fd..2ca0c130ee 100644 --- a/mdk/arm_startup_nrf52810.s +++ b/mdk/arm_startup_nrf52810.s @@ -1,4 +1,4 @@ -; Copyright (c) 2009-2020 ARM Limited. All rights reserved. +; Copyright (c) 2009-2021 ARM Limited. All rights reserved. ; ; SPDX-License-Identifier: Apache-2.0 ; diff --git a/mdk/arm_startup_nrf52811.s b/mdk/arm_startup_nrf52811.s index 93ec67fff6..f48fb70666 100644 --- a/mdk/arm_startup_nrf52811.s +++ b/mdk/arm_startup_nrf52811.s @@ -1,4 +1,4 @@ -; Copyright (c) 2009-2020 ARM Limited. All rights reserved. +; Copyright (c) 2009-2021 ARM Limited. All rights reserved. ; ; SPDX-License-Identifier: Apache-2.0 ; diff --git a/mdk/arm_startup_nrf52820.s b/mdk/arm_startup_nrf52820.s index 02d9a3b394..b2bfedb355 100644 --- a/mdk/arm_startup_nrf52820.s +++ b/mdk/arm_startup_nrf52820.s @@ -1,4 +1,4 @@ -; Copyright (c) 2009-2020 ARM Limited. All rights reserved. +; Copyright (c) 2009-2021 ARM Limited. All rights reserved. ; ; SPDX-License-Identifier: Apache-2.0 ; diff --git a/mdk/arm_startup_nrf52833.s b/mdk/arm_startup_nrf52833.s index 0fa7e06d82..dbfea457d0 100644 --- a/mdk/arm_startup_nrf52833.s +++ b/mdk/arm_startup_nrf52833.s @@ -1,4 +1,4 @@ -; Copyright (c) 2009-2020 ARM Limited. All rights reserved. +; Copyright (c) 2009-2021 ARM Limited. All rights reserved. ; ; SPDX-License-Identifier: Apache-2.0 ; diff --git a/mdk/arm_startup_nrf52840.s b/mdk/arm_startup_nrf52840.s index c03c46f1ee..75696a04fb 100644 --- a/mdk/arm_startup_nrf52840.s +++ b/mdk/arm_startup_nrf52840.s @@ -1,4 +1,4 @@ -; Copyright (c) 2009-2020 ARM Limited. All rights reserved. +; Copyright (c) 2009-2021 ARM Limited. All rights reserved. ; ; SPDX-License-Identifier: Apache-2.0 ; diff --git a/mdk/arm_startup_nrf5340_application.s b/mdk/arm_startup_nrf5340_application.s index c71ae351cf..dc465431cd 100644 --- a/mdk/arm_startup_nrf5340_application.s +++ b/mdk/arm_startup_nrf5340_application.s @@ -1,4 +1,4 @@ -; Copyright (c) 2009-2020 ARM Limited. All rights reserved. +; Copyright (c) 2009-2021 ARM Limited. All rights reserved. ; ; SPDX-License-Identifier: Apache-2.0 ; @@ -92,11 +92,11 @@ __Vectors DCD __initial_sp ; Top of Stack DCD CLOCK_POWER_IRQHandler DCD 0 ; Reserved DCD 0 ; Reserved - DCD SPIM0_SPIS0_TWIM0_TWIS0_UARTE0_IRQHandler - DCD SPIM1_SPIS1_TWIM1_TWIS1_UARTE1_IRQHandler + DCD SERIAL0_IRQHandler + DCD SERIAL1_IRQHandler DCD SPIM4_IRQHandler - DCD SPIM2_SPIS2_TWIM2_TWIS2_UARTE2_IRQHandler - DCD SPIM3_SPIS3_TWIM3_TWIS3_UARTE3_IRQHandler + DCD SERIAL2_IRQHandler + DCD SERIAL3_IRQHandler DCD GPIOTE0_IRQHandler DCD SAADC_IRQHandler DCD TIMER0_IRQHandler @@ -401,11 +401,11 @@ Default_Handler PROC EXPORT CACHE_IRQHandler [WEAK] EXPORT SPU_IRQHandler [WEAK] EXPORT CLOCK_POWER_IRQHandler [WEAK] - EXPORT SPIM0_SPIS0_TWIM0_TWIS0_UARTE0_IRQHandler [WEAK] - EXPORT SPIM1_SPIS1_TWIM1_TWIS1_UARTE1_IRQHandler [WEAK] + EXPORT SERIAL0_IRQHandler [WEAK] + EXPORT SERIAL1_IRQHandler [WEAK] EXPORT SPIM4_IRQHandler [WEAK] - EXPORT SPIM2_SPIS2_TWIM2_TWIS2_UARTE2_IRQHandler [WEAK] - EXPORT SPIM3_SPIS3_TWIM3_TWIS3_UARTE3_IRQHandler [WEAK] + EXPORT SERIAL2_IRQHandler [WEAK] + EXPORT SERIAL3_IRQHandler [WEAK] EXPORT GPIOTE0_IRQHandler [WEAK] EXPORT SAADC_IRQHandler [WEAK] EXPORT TIMER0_IRQHandler [WEAK] @@ -442,11 +442,11 @@ FPU_IRQHandler CACHE_IRQHandler SPU_IRQHandler CLOCK_POWER_IRQHandler -SPIM0_SPIS0_TWIM0_TWIS0_UARTE0_IRQHandler -SPIM1_SPIS1_TWIM1_TWIS1_UARTE1_IRQHandler +SERIAL0_IRQHandler +SERIAL1_IRQHandler SPIM4_IRQHandler -SPIM2_SPIS2_TWIM2_TWIS2_UARTE2_IRQHandler -SPIM3_SPIS3_TWIM3_TWIS3_UARTE3_IRQHandler +SERIAL2_IRQHandler +SERIAL3_IRQHandler GPIOTE0_IRQHandler SAADC_IRQHandler TIMER0_IRQHandler diff --git a/mdk/arm_startup_nrf5340_network.s b/mdk/arm_startup_nrf5340_network.s index 04a8d0a94a..8ae382c138 100644 --- a/mdk/arm_startup_nrf5340_network.s +++ b/mdk/arm_startup_nrf5340_network.s @@ -1,4 +1,4 @@ -; Copyright (c) 2009-2020 ARM Limited. All rights reserved. +; Copyright (c) 2009-2021 ARM Limited. All rights reserved. ; ; SPDX-License-Identifier: Apache-2.0 ; @@ -103,7 +103,7 @@ __Vectors DCD __initial_sp ; Top of Stack DCD TEMP_IRQHandler DCD RTC0_IRQHandler DCD IPC_IRQHandler - DCD SPIM0_SPIS0_TWIM0_TWIS0_UARTE0_IRQHandler + DCD SERIAL0_IRQHandler DCD EGU0_IRQHandler DCD 0 ; Reserved DCD RTC1_IRQHandler @@ -292,7 +292,7 @@ Default_Handler PROC EXPORT TEMP_IRQHandler [WEAK] EXPORT RTC0_IRQHandler [WEAK] EXPORT IPC_IRQHandler [WEAK] - EXPORT SPIM0_SPIS0_TWIM0_TWIS0_UARTE0_IRQHandler [WEAK] + EXPORT SERIAL0_IRQHandler [WEAK] EXPORT EGU0_IRQHandler [WEAK] EXPORT RTC1_IRQHandler [WEAK] EXPORT TIMER1_IRQHandler [WEAK] @@ -312,7 +312,7 @@ AAR_CCM_IRQHandler TEMP_IRQHandler RTC0_IRQHandler IPC_IRQHandler -SPIM0_SPIS0_TWIM0_TWIS0_UARTE0_IRQHandler +SERIAL0_IRQHandler EGU0_IRQHandler RTC1_IRQHandler TIMER1_IRQHandler diff --git a/mdk/arm_startup_nrf9160.s b/mdk/arm_startup_nrf9160.s index 69f1e86fae..917bf61bc8 100644 --- a/mdk/arm_startup_nrf9160.s +++ b/mdk/arm_startup_nrf9160.s @@ -1,4 +1,4 @@ -; Copyright (c) 2009-2020 ARM Limited. All rights reserved. +; Copyright (c) 2009-2021 ARM Limited. All rights reserved. ; ; SPDX-License-Identifier: Apache-2.0 ; diff --git a/mdk/compiler_abstraction.h b/mdk/compiler_abstraction.h index 00009be8d4..b687bfabea 100644 --- a/mdk/compiler_abstraction.h +++ b/mdk/compiler_abstraction.h @@ -1,6 +1,8 @@ /* -Copyright (c) 2010 - 2020, Nordic Semiconductor ASA All rights reserved. +Copyright (c) 2010 - 2021, Nordic Semiconductor ASA All rights reserved. + +SPDX-License-Identifier: BSD-3-Clause Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: @@ -126,13 +128,23 @@ POSSIBILITY OF SUCH DAMAGE. #define __WEAK __weak #endif - #ifndef __ALIGN - #define STRING_PRAGMA(x) _Pragma(#x) - #define __ALIGN(n) STRING_PRAGMA(data_alignment = n) - #endif + #if (__VER__ >= 8000000) + #ifndef __ALIGN + #define __ALIGN(n) __attribute__((aligned(x))) + #endif - #ifndef __PACKED - #define __PACKED __packed + #ifndef __PACKED + #define __PACKED __attribute__((packed, aligned(1))) + #endif + #else + #ifndef __ALIGN + #define STRING_PRAGMA(x) _Pragma(#x) + #define __ALIGN(n) STRING_PRAGMA(data_alignment = n) + #endif + + #ifndef __PACKED + #define __PACKED __packed + #endif #endif #ifndef __UNUSED diff --git a/mdk/gcc_startup_nrf51.S b/mdk/gcc_startup_nrf51.S index 4665eac6c1..ee4d592237 100644 --- a/mdk/gcc_startup_nrf51.S +++ b/mdk/gcc_startup_nrf51.S @@ -1,6 +1,6 @@ /* -Copyright (c) 2009-2020 ARM Limited. All rights reserved. +Copyright (c) 2009-2021 ARM Limited. All rights reserved. SPDX-License-Identifier: Apache-2.0 diff --git a/mdk/gcc_startup_nrf52.S b/mdk/gcc_startup_nrf52.S index 1e9997f2c0..f70dc4117f 100644 --- a/mdk/gcc_startup_nrf52.S +++ b/mdk/gcc_startup_nrf52.S @@ -1,6 +1,6 @@ /* -Copyright (c) 2009-2020 ARM Limited. All rights reserved. +Copyright (c) 2009-2021 ARM Limited. All rights reserved. SPDX-License-Identifier: Apache-2.0 diff --git a/mdk/gcc_startup_nrf52805.S b/mdk/gcc_startup_nrf52805.S index da82da7697..d904b7d45e 100644 --- a/mdk/gcc_startup_nrf52805.S +++ b/mdk/gcc_startup_nrf52805.S @@ -1,6 +1,6 @@ /* -Copyright (c) 2009-2020 ARM Limited. All rights reserved. +Copyright (c) 2009-2021 ARM Limited. All rights reserved. SPDX-License-Identifier: Apache-2.0 diff --git a/mdk/gcc_startup_nrf52810.S b/mdk/gcc_startup_nrf52810.S index dc84105e58..681a039b3a 100644 --- a/mdk/gcc_startup_nrf52810.S +++ b/mdk/gcc_startup_nrf52810.S @@ -1,6 +1,6 @@ /* -Copyright (c) 2009-2020 ARM Limited. All rights reserved. +Copyright (c) 2009-2021 ARM Limited. All rights reserved. SPDX-License-Identifier: Apache-2.0 diff --git a/mdk/gcc_startup_nrf52811.S b/mdk/gcc_startup_nrf52811.S index f6929fcc47..01f0edd625 100644 --- a/mdk/gcc_startup_nrf52811.S +++ b/mdk/gcc_startup_nrf52811.S @@ -1,6 +1,6 @@ /* -Copyright (c) 2009-2020 ARM Limited. All rights reserved. +Copyright (c) 2009-2021 ARM Limited. All rights reserved. SPDX-License-Identifier: Apache-2.0 diff --git a/mdk/gcc_startup_nrf52820.S b/mdk/gcc_startup_nrf52820.S index 8e4c2d8bc2..c2c930c51d 100644 --- a/mdk/gcc_startup_nrf52820.S +++ b/mdk/gcc_startup_nrf52820.S @@ -1,6 +1,6 @@ /* -Copyright (c) 2009-2020 ARM Limited. All rights reserved. +Copyright (c) 2009-2021 ARM Limited. All rights reserved. SPDX-License-Identifier: Apache-2.0 diff --git a/mdk/gcc_startup_nrf52833.S b/mdk/gcc_startup_nrf52833.S index 16030a7eee..7aaf8ca112 100644 --- a/mdk/gcc_startup_nrf52833.S +++ b/mdk/gcc_startup_nrf52833.S @@ -1,6 +1,6 @@ /* -Copyright (c) 2009-2020 ARM Limited. All rights reserved. +Copyright (c) 2009-2021 ARM Limited. All rights reserved. SPDX-License-Identifier: Apache-2.0 diff --git a/mdk/gcc_startup_nrf52840.S b/mdk/gcc_startup_nrf52840.S index d7f793d5a7..2fcba661cc 100644 --- a/mdk/gcc_startup_nrf52840.S +++ b/mdk/gcc_startup_nrf52840.S @@ -1,6 +1,6 @@ /* -Copyright (c) 2009-2020 ARM Limited. All rights reserved. +Copyright (c) 2009-2021 ARM Limited. All rights reserved. SPDX-License-Identifier: Apache-2.0 diff --git a/mdk/gcc_startup_nrf5340_application.S b/mdk/gcc_startup_nrf5340_application.S index a1d7ad0dc5..55d2865191 100644 --- a/mdk/gcc_startup_nrf5340_application.S +++ b/mdk/gcc_startup_nrf5340_application.S @@ -1,6 +1,6 @@ /* -Copyright (c) 2009-2020 ARM Limited. All rights reserved. +Copyright (c) 2009-2021 ARM Limited. All rights reserved. SPDX-License-Identifier: Apache-2.0 @@ -98,11 +98,11 @@ __isr_vector: .long CLOCK_POWER_IRQHandler .long 0 /*Reserved */ .long 0 /*Reserved */ - .long SPIM0_SPIS0_TWIM0_TWIS0_UARTE0_IRQHandler - .long SPIM1_SPIS1_TWIM1_TWIS1_UARTE1_IRQHandler + .long SERIAL0_IRQHandler + .long SERIAL1_IRQHandler .long SPIM4_IRQHandler - .long SPIM2_SPIS2_TWIM2_TWIS2_UARTE2_IRQHandler - .long SPIM3_SPIS3_TWIM3_TWIS3_UARTE3_IRQHandler + .long SERIAL2_IRQHandler + .long SERIAL3_IRQHandler .long GPIOTE0_IRQHandler .long SAADC_IRQHandler .long TIMER0_IRQHandler @@ -504,11 +504,11 @@ Default_Handler: IRQ CACHE_IRQHandler IRQ SPU_IRQHandler IRQ CLOCK_POWER_IRQHandler - IRQ SPIM0_SPIS0_TWIM0_TWIS0_UARTE0_IRQHandler - IRQ SPIM1_SPIS1_TWIM1_TWIS1_UARTE1_IRQHandler + IRQ SERIAL0_IRQHandler + IRQ SERIAL1_IRQHandler IRQ SPIM4_IRQHandler - IRQ SPIM2_SPIS2_TWIM2_TWIS2_UARTE2_IRQHandler - IRQ SPIM3_SPIS3_TWIM3_TWIS3_UARTE3_IRQHandler + IRQ SERIAL2_IRQHandler + IRQ SERIAL3_IRQHandler IRQ GPIOTE0_IRQHandler IRQ SAADC_IRQHandler IRQ TIMER0_IRQHandler diff --git a/mdk/gcc_startup_nrf5340_network.S b/mdk/gcc_startup_nrf5340_network.S index fcbd8cd7d6..0edb3bbc14 100644 --- a/mdk/gcc_startup_nrf5340_network.S +++ b/mdk/gcc_startup_nrf5340_network.S @@ -1,6 +1,6 @@ /* -Copyright (c) 2009-2020 ARM Limited. All rights reserved. +Copyright (c) 2009-2021 ARM Limited. All rights reserved. SPDX-License-Identifier: Apache-2.0 @@ -109,7 +109,7 @@ __isr_vector: .long TEMP_IRQHandler .long RTC0_IRQHandler .long IPC_IRQHandler - .long SPIM0_SPIS0_TWIM0_TWIS0_UARTE0_IRQHandler + .long SERIAL0_IRQHandler .long EGU0_IRQHandler .long 0 /*Reserved */ .long RTC1_IRQHandler @@ -393,7 +393,7 @@ Default_Handler: IRQ TEMP_IRQHandler IRQ RTC0_IRQHandler IRQ IPC_IRQHandler - IRQ SPIM0_SPIS0_TWIM0_TWIS0_UARTE0_IRQHandler + IRQ SERIAL0_IRQHandler IRQ EGU0_IRQHandler IRQ RTC1_IRQHandler IRQ TIMER1_IRQHandler diff --git a/mdk/gcc_startup_nrf9160.S b/mdk/gcc_startup_nrf9160.S index 81b4187289..9c310dff22 100644 --- a/mdk/gcc_startup_nrf9160.S +++ b/mdk/gcc_startup_nrf9160.S @@ -1,6 +1,6 @@ /* -Copyright (c) 2009-2020 ARM Limited. All rights reserved. +Copyright (c) 2009-2021 ARM Limited. All rights reserved. SPDX-License-Identifier: Apache-2.0 diff --git a/mdk/iar_startup_nrf51.s b/mdk/iar_startup_nrf51.s index b4da82bf35..b89dcda701 100644 --- a/mdk/iar_startup_nrf51.s +++ b/mdk/iar_startup_nrf51.s @@ -1,4 +1,4 @@ -; Copyright (c) 2009-2020 ARM Limited. All rights reserved. +; Copyright (c) 2009-2021 ARM Limited. All rights reserved. ; ; SPDX-License-Identifier: Apache-2.0 ; diff --git a/mdk/iar_startup_nrf52.s b/mdk/iar_startup_nrf52.s index 115eb567ad..cf0ee662f0 100644 --- a/mdk/iar_startup_nrf52.s +++ b/mdk/iar_startup_nrf52.s @@ -1,4 +1,4 @@ -; Copyright (c) 2009-2020 ARM Limited. All rights reserved. +; Copyright (c) 2009-2021 ARM Limited. All rights reserved. ; ; SPDX-License-Identifier: Apache-2.0 ; diff --git a/mdk/iar_startup_nrf52805.s b/mdk/iar_startup_nrf52805.s index 62508371f4..452ec356f0 100644 --- a/mdk/iar_startup_nrf52805.s +++ b/mdk/iar_startup_nrf52805.s @@ -1,4 +1,4 @@ -; Copyright (c) 2009-2020 ARM Limited. All rights reserved. +; Copyright (c) 2009-2021 ARM Limited. All rights reserved. ; ; SPDX-License-Identifier: Apache-2.0 ; diff --git a/mdk/iar_startup_nrf52810.s b/mdk/iar_startup_nrf52810.s index 3f2f25decc..d584fa76ef 100644 --- a/mdk/iar_startup_nrf52810.s +++ b/mdk/iar_startup_nrf52810.s @@ -1,4 +1,4 @@ -; Copyright (c) 2009-2020 ARM Limited. All rights reserved. +; Copyright (c) 2009-2021 ARM Limited. All rights reserved. ; ; SPDX-License-Identifier: Apache-2.0 ; diff --git a/mdk/iar_startup_nrf52811.s b/mdk/iar_startup_nrf52811.s index 69c94b76ab..87a19ec8c1 100644 --- a/mdk/iar_startup_nrf52811.s +++ b/mdk/iar_startup_nrf52811.s @@ -1,4 +1,4 @@ -; Copyright (c) 2009-2020 ARM Limited. All rights reserved. +; Copyright (c) 2009-2021 ARM Limited. All rights reserved. ; ; SPDX-License-Identifier: Apache-2.0 ; diff --git a/mdk/iar_startup_nrf52820.s b/mdk/iar_startup_nrf52820.s index 8f5cfb1b98..0d8d58cd42 100644 --- a/mdk/iar_startup_nrf52820.s +++ b/mdk/iar_startup_nrf52820.s @@ -1,4 +1,4 @@ -; Copyright (c) 2009-2020 ARM Limited. All rights reserved. +; Copyright (c) 2009-2021 ARM Limited. All rights reserved. ; ; SPDX-License-Identifier: Apache-2.0 ; diff --git a/mdk/iar_startup_nrf52833.s b/mdk/iar_startup_nrf52833.s index ac85d3692e..c1cea17fb1 100644 --- a/mdk/iar_startup_nrf52833.s +++ b/mdk/iar_startup_nrf52833.s @@ -1,4 +1,4 @@ -; Copyright (c) 2009-2020 ARM Limited. All rights reserved. +; Copyright (c) 2009-2021 ARM Limited. All rights reserved. ; ; SPDX-License-Identifier: Apache-2.0 ; diff --git a/mdk/iar_startup_nrf52840.s b/mdk/iar_startup_nrf52840.s index 7a63958934..63d783b539 100644 --- a/mdk/iar_startup_nrf52840.s +++ b/mdk/iar_startup_nrf52840.s @@ -1,4 +1,4 @@ -; Copyright (c) 2009-2020 ARM Limited. All rights reserved. +; Copyright (c) 2009-2021 ARM Limited. All rights reserved. ; ; SPDX-License-Identifier: Apache-2.0 ; diff --git a/mdk/iar_startup_nrf5340_application.s b/mdk/iar_startup_nrf5340_application.s index 8c6613580c..be2fc4b701 100644 --- a/mdk/iar_startup_nrf5340_application.s +++ b/mdk/iar_startup_nrf5340_application.s @@ -1,4 +1,4 @@ -; Copyright (c) 2009-2020 ARM Limited. All rights reserved. +; Copyright (c) 2009-2021 ARM Limited. All rights reserved. ; ; SPDX-License-Identifier: Apache-2.0 ; @@ -93,11 +93,11 @@ __vector_table DCD CLOCK_POWER_IRQHandler DCD 0 ; Reserved DCD 0 ; Reserved - DCD SPIM0_SPIS0_TWIM0_TWIS0_UARTE0_IRQHandler - DCD SPIM1_SPIS1_TWIM1_TWIS1_UARTE1_IRQHandler + DCD SERIAL0_IRQHandler + DCD SERIAL1_IRQHandler DCD SPIM4_IRQHandler - DCD SPIM2_SPIS2_TWIM2_TWIS2_UARTE2_IRQHandler - DCD SPIM3_SPIS3_TWIM3_TWIS3_UARTE3_IRQHandler + DCD SERIAL2_IRQHandler + DCD SERIAL3_IRQHandler DCD GPIOTE0_IRQHandler DCD SAADC_IRQHandler DCD TIMER0_IRQHandler @@ -419,14 +419,14 @@ SPU_IRQHandler CLOCK_POWER_IRQHandler B . - PUBWEAK SPIM0_SPIS0_TWIM0_TWIS0_UARTE0_IRQHandler + PUBWEAK SERIAL0_IRQHandler SECTION .text:CODE:REORDER:NOROOT(1) -SPIM0_SPIS0_TWIM0_TWIS0_UARTE0_IRQHandler +SERIAL0_IRQHandler B . - PUBWEAK SPIM1_SPIS1_TWIM1_TWIS1_UARTE1_IRQHandler + PUBWEAK SERIAL1_IRQHandler SECTION .text:CODE:REORDER:NOROOT(1) -SPIM1_SPIS1_TWIM1_TWIS1_UARTE1_IRQHandler +SERIAL1_IRQHandler B . PUBWEAK SPIM4_IRQHandler @@ -434,14 +434,14 @@ SPIM1_SPIS1_TWIM1_TWIS1_UARTE1_IRQHandler SPIM4_IRQHandler B . - PUBWEAK SPIM2_SPIS2_TWIM2_TWIS2_UARTE2_IRQHandler + PUBWEAK SERIAL2_IRQHandler SECTION .text:CODE:REORDER:NOROOT(1) -SPIM2_SPIS2_TWIM2_TWIS2_UARTE2_IRQHandler +SERIAL2_IRQHandler B . - PUBWEAK SPIM3_SPIS3_TWIM3_TWIS3_UARTE3_IRQHandler + PUBWEAK SERIAL3_IRQHandler SECTION .text:CODE:REORDER:NOROOT(1) -SPIM3_SPIS3_TWIM3_TWIS3_UARTE3_IRQHandler +SERIAL3_IRQHandler B . PUBWEAK GPIOTE0_IRQHandler diff --git a/mdk/iar_startup_nrf5340_network.s b/mdk/iar_startup_nrf5340_network.s index f7d9d2ba1d..ce3a9b2c99 100644 --- a/mdk/iar_startup_nrf5340_network.s +++ b/mdk/iar_startup_nrf5340_network.s @@ -1,4 +1,4 @@ -; Copyright (c) 2009-2020 ARM Limited. All rights reserved. +; Copyright (c) 2009-2021 ARM Limited. All rights reserved. ; ; SPDX-License-Identifier: Apache-2.0 ; @@ -104,7 +104,7 @@ __vector_table DCD TEMP_IRQHandler DCD RTC0_IRQHandler DCD IPC_IRQHandler - DCD SPIM0_SPIS0_TWIM0_TWIS0_UARTE0_IRQHandler + DCD SERIAL0_IRQHandler DCD EGU0_IRQHandler DCD 0 ; Reserved DCD RTC1_IRQHandler @@ -338,9 +338,9 @@ RTC0_IRQHandler IPC_IRQHandler B . - PUBWEAK SPIM0_SPIS0_TWIM0_TWIS0_UARTE0_IRQHandler + PUBWEAK SERIAL0_IRQHandler SECTION .text:CODE:REORDER:NOROOT(1) -SPIM0_SPIS0_TWIM0_TWIS0_UARTE0_IRQHandler +SERIAL0_IRQHandler B . PUBWEAK EGU0_IRQHandler diff --git a/mdk/iar_startup_nrf9160.s b/mdk/iar_startup_nrf9160.s index d0d370ae1e..e71b8dcbd5 100644 --- a/mdk/iar_startup_nrf9160.s +++ b/mdk/iar_startup_nrf9160.s @@ -1,4 +1,4 @@ -; Copyright (c) 2009-2020 ARM Limited. All rights reserved. +; Copyright (c) 2009-2021 ARM Limited. All rights reserved. ; ; SPDX-License-Identifier: Apache-2.0 ; diff --git a/mdk/nrf.h b/mdk/nrf.h index ed941bb32c..8a122273da 100644 --- a/mdk/nrf.h +++ b/mdk/nrf.h @@ -1,6 +1,8 @@ /* -Copyright (c) 2010 - 2020, Nordic Semiconductor ASA All rights reserved. +Copyright (c) 2010 - 2021, Nordic Semiconductor ASA All rights reserved. + +SPDX-License-Identifier: BSD-3-Clause Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: @@ -35,8 +37,8 @@ POSSIBILITY OF SUCH DAMAGE. /* MDK version */ #define MDK_MAJOR_VERSION 8 -#define MDK_MINOR_VERSION 37 -#define MDK_MICRO_VERSION 0 +#define MDK_MINOR_VERSION 40 +#define MDK_MICRO_VERSION 2 /* Define coprocessor domains */ @@ -167,9 +169,11 @@ POSSIBILITY OF SUCH DAMAGE. #if defined(NRF_APPLICATION) #include "nrf5340_application.h" #include "nrf5340_application_bitfields.h" + #include "nrf5340_application_name_change.h" #elif defined (NRF_NETWORK) #include "nrf5340_network.h" #include "nrf5340_network_bitfields.h" + #include "nrf5340_network_name_change.h" #endif #elif defined (NRF9160_XXAA) diff --git a/mdk/nrf51.h b/mdk/nrf51.h index 549ba372ba..0bf8fb6a38 100644 --- a/mdk/nrf51.h +++ b/mdk/nrf51.h @@ -1,5 +1,7 @@ /* - * Copyright (c) 2010 - 2020, Nordic Semiconductor ASA All rights reserved. + * Copyright (c) 2010 - 2021, Nordic Semiconductor ASA All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: @@ -30,10 +32,10 @@ * @file nrf51.h * @brief CMSIS HeaderFile * @version 522 - * @date 04. November 2020 - * @note Generated by SVDConv V3.3.35 on Wednesday, 04.11.2020 13:48:07 + * @date 29. April 2021 + * @note Generated by SVDConv V3.3.35 on Thursday, 29.04.2021 12:43:41 * from File 'nrf51.svd', - * last modified on Wednesday, 04.11.2020 12:48:00 + * last modified on Thursday, 29.04.2021 10:43:40 */ diff --git a/mdk/nrf51.svd b/mdk/nrf51.svd index 51d03376c2..1057dcd285 100644 --- a/mdk/nrf51.svd +++ b/mdk/nrf51.svd @@ -8,7 +8,9 @@ 522 nRF51 reference description for radio MCU with ARM 32-bit Cortex-M0 Microcontroller at 16MHz CPU clock -Copyright (c) 2010 - 2020, Nordic Semiconductor ASA All rights reserved.\n +Copyright (c) 2010 - 2021, Nordic Semiconductor ASA All rights reserved.\n +\n +SPDX-License-Identifier: BSD-3-Clause\n \n Redistribution and use in source and binary forms, with or without\n modification, are permitted provided that the following conditions are met:\n diff --git a/mdk/nrf51422_peripherals.h b/mdk/nrf51422_peripherals.h index 790f0b3359..e136576a47 100644 --- a/mdk/nrf51422_peripherals.h +++ b/mdk/nrf51422_peripherals.h @@ -1,6 +1,8 @@ /* -Copyright (c) 2010 - 2020, Nordic Semiconductor ASA All rights reserved. +Copyright (c) 2010 - 2021, Nordic Semiconductor ASA All rights reserved. + +SPDX-License-Identifier: BSD-3-Clause Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: diff --git a/mdk/nrf51801_peripherals.h b/mdk/nrf51801_peripherals.h index 8aa5a3b137..0b70e688d8 100644 --- a/mdk/nrf51801_peripherals.h +++ b/mdk/nrf51801_peripherals.h @@ -1,6 +1,8 @@ /* -Copyright (c) 2010 - 2020, Nordic Semiconductor ASA All rights reserved. +Copyright (c) 2010 - 2021, Nordic Semiconductor ASA All rights reserved. + +SPDX-License-Identifier: BSD-3-Clause Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: diff --git a/mdk/nrf51802_peripherals.h b/mdk/nrf51802_peripherals.h index 9a685ab633..e3578022d1 100644 --- a/mdk/nrf51802_peripherals.h +++ b/mdk/nrf51802_peripherals.h @@ -1,6 +1,8 @@ /* -Copyright (c) 2010 - 2020, Nordic Semiconductor ASA All rights reserved. +Copyright (c) 2010 - 2021, Nordic Semiconductor ASA All rights reserved. + +SPDX-License-Identifier: BSD-3-Clause Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: diff --git a/mdk/nrf51822_peripherals.h b/mdk/nrf51822_peripherals.h index 2c819c6b1d..6b4cc8e23f 100644 --- a/mdk/nrf51822_peripherals.h +++ b/mdk/nrf51822_peripherals.h @@ -1,6 +1,8 @@ /* -Copyright (c) 2010 - 2020, Nordic Semiconductor ASA All rights reserved. +Copyright (c) 2010 - 2021, Nordic Semiconductor ASA All rights reserved. + +SPDX-License-Identifier: BSD-3-Clause Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: diff --git a/mdk/nrf51824_peripherals.h b/mdk/nrf51824_peripherals.h index 63aff43135..89538986ed 100644 --- a/mdk/nrf51824_peripherals.h +++ b/mdk/nrf51824_peripherals.h @@ -1,6 +1,8 @@ /* -Copyright (c) 2010 - 2020, Nordic Semiconductor ASA All rights reserved. +Copyright (c) 2010 - 2021, Nordic Semiconductor ASA All rights reserved. + +SPDX-License-Identifier: BSD-3-Clause Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: diff --git a/mdk/nrf51_bitfields.h b/mdk/nrf51_bitfields.h index ea72479bfe..4406732a94 100644 --- a/mdk/nrf51_bitfields.h +++ b/mdk/nrf51_bitfields.h @@ -1,6 +1,8 @@ /* -Copyright (c) 2010 - 2020, Nordic Semiconductor ASA All rights reserved. +Copyright (c) 2010 - 2021, Nordic Semiconductor ASA All rights reserved. + +SPDX-License-Identifier: BSD-3-Clause Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: diff --git a/mdk/nrf51_deprecated.h b/mdk/nrf51_deprecated.h index 4342366fb5..80f2004858 100644 --- a/mdk/nrf51_deprecated.h +++ b/mdk/nrf51_deprecated.h @@ -1,6 +1,8 @@ /* -Copyright (c) 2010 - 2020, Nordic Semiconductor ASA All rights reserved. +Copyright (c) 2010 - 2021, Nordic Semiconductor ASA All rights reserved. + +SPDX-License-Identifier: BSD-3-Clause Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: diff --git a/mdk/nrf51_erratas.h b/mdk/nrf51_erratas.h index 0a4e845b0d..931ed62fa2 100644 --- a/mdk/nrf51_erratas.h +++ b/mdk/nrf51_erratas.h @@ -3,7 +3,9 @@ /* -Copyright (c) 2010 - 2020, Nordic Semiconductor ASA All rights reserved. +Copyright (c) 2010 - 2021, Nordic Semiconductor ASA All rights reserved. + +SPDX-License-Identifier: BSD-3-Clause Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: diff --git a/mdk/nrf51_peripherals.h b/mdk/nrf51_peripherals.h index d6457c0d98..967e3b6892 100644 --- a/mdk/nrf51_peripherals.h +++ b/mdk/nrf51_peripherals.h @@ -1,6 +1,8 @@ /* -Copyright (c) 2010 - 2020, Nordic Semiconductor ASA All rights reserved. +Copyright (c) 2010 - 2021, Nordic Semiconductor ASA All rights reserved. + +SPDX-License-Identifier: BSD-3-Clause Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: diff --git a/mdk/nrf51_to_nrf52.h b/mdk/nrf51_to_nrf52.h index 3a6af642f0..77a7588e78 100644 --- a/mdk/nrf51_to_nrf52.h +++ b/mdk/nrf51_to_nrf52.h @@ -1,6 +1,8 @@ /* -Copyright (c) 2010 - 2020, Nordic Semiconductor ASA All rights reserved. +Copyright (c) 2010 - 2021, Nordic Semiconductor ASA All rights reserved. + +SPDX-License-Identifier: BSD-3-Clause Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: diff --git a/mdk/nrf51_to_nrf52810.h b/mdk/nrf51_to_nrf52810.h index c4436d1185..c44b052b95 100644 --- a/mdk/nrf51_to_nrf52810.h +++ b/mdk/nrf51_to_nrf52810.h @@ -1,6 +1,8 @@ /* -Copyright (c) 2010 - 2020, Nordic Semiconductor ASA All rights reserved. +Copyright (c) 2010 - 2021, Nordic Semiconductor ASA All rights reserved. + +SPDX-License-Identifier: BSD-3-Clause Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: diff --git a/mdk/nrf51_to_nrf52840.h b/mdk/nrf51_to_nrf52840.h index 376e0c0dd9..c991d66568 100644 --- a/mdk/nrf51_to_nrf52840.h +++ b/mdk/nrf51_to_nrf52840.h @@ -1,6 +1,8 @@ /* -Copyright (c) 2010 - 2020, Nordic Semiconductor ASA All rights reserved. +Copyright (c) 2010 - 2021, Nordic Semiconductor ASA All rights reserved. + +SPDX-License-Identifier: BSD-3-Clause Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: diff --git a/mdk/nrf52.h b/mdk/nrf52.h index abfbbc192f..6aab0ea8bd 100644 --- a/mdk/nrf52.h +++ b/mdk/nrf52.h @@ -1,5 +1,7 @@ /* - * Copyright (c) 2010 - 2020, Nordic Semiconductor ASA All rights reserved. + * Copyright (c) 2010 - 2021, Nordic Semiconductor ASA All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: @@ -30,10 +32,10 @@ * @file nrf52.h * @brief CMSIS HeaderFile * @version 1 - * @date 04. November 2020 - * @note Generated by SVDConv V3.3.35 on Wednesday, 04.11.2020 13:48:08 + * @date 29. April 2021 + * @note Generated by SVDConv V3.3.35 on Thursday, 29.04.2021 12:43:45 * from File 'nrf52.svd', - * last modified on Wednesday, 04.11.2020 12:48:00 + * last modified on Thursday, 29.04.2021 10:43:40 */ @@ -752,13 +754,33 @@ typedef struct { /*!< (@ 0x10001000) UICR Structu __IM uint32_t RESERVED1[64]; __IOM uint32_t PSELRESET[2]; /*!< (@ 0x00000200) Description collection[0]: Mapping of the nRESET function (see POWER chapter for details) */ - __IOM uint32_t APPROTECT; /*!< (@ 0x00000208) Access Port protection */ + __IOM uint32_t APPROTECT; /*!< (@ 0x00000208) Access port protection */ __IOM uint32_t NFCPINS; /*!< (@ 0x0000020C) Setting of pins dedicated to NFC functionality: NFC antenna or GPIO */ } NRF_UICR_Type; /*!< Size = 528 (0x210) */ +/* =========================================================================================================================== */ +/* ================ APPROTECT ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Access Port Protection (APPROTECT) + */ + +typedef struct { /*!< (@ 0x40000000) APPROTECT Structure */ + __IM uint32_t RESERVED[340]; + __IOM uint32_t FORCEPROTECT; /*!< (@ 0x00000550) Software force enable APPROTECT mechanism until + next reset. This register can only be written + once. */ + __IM uint32_t RESERVED1; + __IOM uint32_t DISABLE; /*!< (@ 0x00000558) Software disable APPROTECT mechanism */ +} NRF_APPROTECT_Type; /*!< Size = 1372 (0x55c) */ + + + /* =========================================================================================================================== */ /* ================ BPROT ================ */ /* =========================================================================================================================== */ @@ -2268,6 +2290,7 @@ typedef struct { /*!< (@ 0x50000000) P0 Structure #define NRF_FICR_BASE 0x10000000UL #define NRF_UICR_BASE 0x10001000UL +#define NRF_APPROTECT_BASE 0x40000000UL #define NRF_BPROT_BASE 0x40000000UL #define NRF_POWER_BASE 0x40000000UL #define NRF_CLOCK_BASE 0x40000000UL @@ -2346,6 +2369,7 @@ typedef struct { /*!< (@ 0x50000000) P0 Structure #define NRF_FICR ((NRF_FICR_Type*) NRF_FICR_BASE) #define NRF_UICR ((NRF_UICR_Type*) NRF_UICR_BASE) +#define NRF_APPROTECT ((NRF_APPROTECT_Type*) NRF_APPROTECT_BASE) #define NRF_BPROT ((NRF_BPROT_Type*) NRF_BPROT_BASE) #define NRF_POWER ((NRF_POWER_Type*) NRF_POWER_BASE) #define NRF_CLOCK ((NRF_CLOCK_Type*) NRF_CLOCK_BASE) diff --git a/mdk/nrf52.svd b/mdk/nrf52.svd index da84887c89..f052a928c9 100644 --- a/mdk/nrf52.svd +++ b/mdk/nrf52.svd @@ -8,7 +8,9 @@ 1 nRF52832 reference description for radio MCU with ARM 32-bit Cortex-M4 Microcontroller -Copyright (c) 2010 - 2020, Nordic Semiconductor ASA All rights reserved.\n +Copyright (c) 2010 - 2021, Nordic Semiconductor ASA All rights reserved.\n +\n +SPDX-License-Identifier: BSD-3-Clause\n \n Redistribution and use in source and binary forms, with or without\n modification, are permitted provided that the following conditions are met:\n @@ -926,22 +928,27 @@ POSSIBILITY OF SUCH DAMAGE.\n APPROTECT - Access Port protection + Access port protection 0x208 read-write 0xFFFFFFFF PALL - Enable or disable Access Port protection. Any other value than 0xFF being written to this field will enable protection. + Enable or disable access port protection. 0 7 Disabled - Disable + Hardware disable of access port protection for devices where access port protection is controlled by hardware 0xFF + + HwDisabled + Hardware disable of access port protection for devices where access port protection is controlled by hardware and software + 0x5A + Enabled Enable @@ -966,12 +973,12 @@ POSSIBILITY OF SUCH DAMAGE.\n Disabled - Operation as GPIO pins. Same protection as normal GPIO pins + Operation as GPIO pins. Same protection as normal GPIO pins. 0 NFC - Operation as NFC antenna pins. Configures the protection for NFC operation + Operation as NFC antenna pins. Configures the protection for NFC operation. 1 @@ -980,12 +987,72 @@ POSSIBILITY OF SUCH DAMAGE.\n + + APPROTECT + Access Port Protection + APPROTECT + 0x40000000 + 32 + + 0 + 0x1000 + registers + + + + FORCEPROTECT + Software force enable APPROTECT mechanism until next reset. This register can only be written once. + 0x550 + read-write + 0xFFFFFFFF + + + FORCEPROTECT + Write 0x0 to force enable APPROTECT mechanism + 0 + 7 + + write + + Force + Software force enable APPROTECT mechanism + 0x0 + + + + + + + DISABLE + Software disable APPROTECT mechanism + 0x558 + read-write + 0x00000000 + + + DISABLE + Software disable APPROTECT mechanism + 0 + 7 + + + SwDisable + Software disable APPROTECT mechanism + 0x5A + + + + + + + BPROT Block Protect BPROT 0x40000000 32 + APPROTECT 0 0x1000 @@ -3369,7 +3436,7 @@ POSSIBILITY OF SUCH DAMAGE.\n POWER 0x40000000 32 - BPROT + APPROTECT 0 0x1000 @@ -4370,7 +4437,7 @@ POSSIBILITY OF SUCH DAMAGE.\n CLOCK 0x40000000 32 - BPROT + APPROTECT 0 0x1000 diff --git a/mdk/nrf52805.h b/mdk/nrf52805.h index 1160ed74b3..9cc4024ef6 100644 --- a/mdk/nrf52805.h +++ b/mdk/nrf52805.h @@ -1,5 +1,7 @@ /* - * Copyright (c) 2010 - 2020, Nordic Semiconductor ASA All rights reserved. + * Copyright (c) 2010 - 2021, Nordic Semiconductor ASA All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: @@ -30,10 +32,10 @@ * @file nrf52805.h * @brief CMSIS HeaderFile * @version 1 - * @date 04. November 2020 - * @note Generated by SVDConv V3.3.35 on Wednesday, 04.11.2020 13:48:07 + * @date 29. April 2021 + * @note Generated by SVDConv V3.3.35 on Thursday, 29.04.2021 12:43:42 * from File 'nrf52805.svd', - * last modified on Wednesday, 04.11.2020 12:48:00 + * last modified on Thursday, 29.04.2021 10:43:40 */ @@ -575,6 +577,25 @@ typedef struct { /*!< (@ 0x40000000) BPROT Struct +/* =========================================================================================================================== */ +/* ================ APPROTECT ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Only for emulation on devices that support hardened AP-PROTECT. (APPROTECT) + */ + +typedef struct { /*!< (@ 0x40000000) APPROTECT Structure */ + __IM uint32_t RESERVED[340]; + __IOM uint32_t FORCEPROTECT; /*!< (@ 0x00000550) Software force enable APPROTECT mechanism until + next reset. */ + __IM uint32_t RESERVED1; + __IOM uint32_t DISABLE; /*!< (@ 0x00000558) Software disable APPROTECT mechanism */ +} NRF_APPROTECT_Type; /*!< Size = 1372 (0x55c) */ + + + /* =========================================================================================================================== */ /* ================ CLOCK ================ */ /* =========================================================================================================================== */ @@ -1705,6 +1726,7 @@ typedef struct { /*!< (@ 0x4001F000) PPI Structur #define NRF_FICR_BASE 0x10000000UL #define NRF_UICR_BASE 0x10001000UL #define NRF_BPROT_BASE 0x40000000UL +#define NRF_APPROTECT_BASE 0x40000000UL #define NRF_CLOCK_BASE 0x40000000UL #define NRF_POWER_BASE 0x40000000UL #define NRF_P0_BASE 0x50000000UL @@ -1757,6 +1779,7 @@ typedef struct { /*!< (@ 0x4001F000) PPI Structur #define NRF_FICR ((NRF_FICR_Type*) NRF_FICR_BASE) #define NRF_UICR ((NRF_UICR_Type*) NRF_UICR_BASE) #define NRF_BPROT ((NRF_BPROT_Type*) NRF_BPROT_BASE) +#define NRF_APPROTECT ((NRF_APPROTECT_Type*) NRF_APPROTECT_BASE) #define NRF_CLOCK ((NRF_CLOCK_Type*) NRF_CLOCK_BASE) #define NRF_POWER ((NRF_POWER_Type*) NRF_POWER_BASE) #define NRF_P0 ((NRF_GPIO_Type*) NRF_P0_BASE) diff --git a/mdk/nrf52805.svd b/mdk/nrf52805.svd index bb09b2ea51..912d89d2a9 100644 --- a/mdk/nrf52805.svd +++ b/mdk/nrf52805.svd @@ -8,7 +8,9 @@ 1 nRF52805 reference description for radio MCU with ARM 32-bit Cortex-M4 Microcontroller -Copyright (c) 2010 - 2020, Nordic Semiconductor ASA All rights reserved.\n +Copyright (c) 2010 - 2021, Nordic Semiconductor ASA All rights reserved.\n +\n +SPDX-License-Identifier: BSD-3-Clause\n \n Redistribution and use in source and binary forms, with or without\n modification, are permitted provided that the following conditions are met:\n @@ -1699,6 +1701,66 @@ POSSIBILITY OF SUCH DAMAGE.\n + + APPROTECT + Only for emulation on devices that support hardened AP-PROTECT. + 0x40000000 + BPROT + + 0 + 0x1000 + registers + + APPROTECT + 0x20 + + + FORCEPROTECT + Software force enable APPROTECT mechanism until next reset. + 0x550 + read-writeonce + 0xFFFFFFFF + + + FORCEPROTECT + Write 0x0 to force enable APPROTECT mechanism + 0 + 7 + + write + + Force + Software force enable APPROTECT mechanism + 0x0 + + + + + + + DISABLE + Software disable APPROTECT mechanism + 0x558 + read-write + 0x00000000 + + + DISABLE + Software disable APPROTECT mechanism + 0 + 7 + + + SwDisable + Software disable APPROTECT mechanism + 0x5A + + + + + + + CLOCK Clock control diff --git a/mdk/nrf52805_bitfields.h b/mdk/nrf52805_bitfields.h index c60555c687..ac54eeedac 100644 --- a/mdk/nrf52805_bitfields.h +++ b/mdk/nrf52805_bitfields.h @@ -1,6 +1,8 @@ /* -Copyright (c) 2010 - 2020, Nordic Semiconductor ASA All rights reserved. +Copyright (c) 2010 - 2021, Nordic Semiconductor ASA All rights reserved. + +SPDX-License-Identifier: BSD-3-Clause Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: @@ -174,6 +176,26 @@ POSSIBILITY OF SUCH DAMAGE. #define AAR_SCRATCHPTR_SCRATCHPTR_Msk (0xFFFFFFFFUL << AAR_SCRATCHPTR_SCRATCHPTR_Pos) /*!< Bit mask of SCRATCHPTR field. */ +/* Peripheral: APPROTECT */ +/* Description: Only for emulation on devices that support hardened AP-PROTECT. */ + +/* Register: APPROTECT_FORCEPROTECT */ +/* Description: Software force enable APPROTECT mechanism until next reset. */ + +/* Bits 7..0 : Write 0x0 to force enable APPROTECT mechanism */ +#define APPROTECT_FORCEPROTECT_FORCEPROTECT_Pos (0UL) /*!< Position of FORCEPROTECT field. */ +#define APPROTECT_FORCEPROTECT_FORCEPROTECT_Msk (0xFFUL << APPROTECT_FORCEPROTECT_FORCEPROTECT_Pos) /*!< Bit mask of FORCEPROTECT field. */ +#define APPROTECT_FORCEPROTECT_FORCEPROTECT_Force (0x0UL) /*!< Software force enable APPROTECT mechanism */ + +/* Register: APPROTECT_DISABLE */ +/* Description: Software disable APPROTECT mechanism */ + +/* Bits 7..0 : Software disable APPROTECT mechanism */ +#define APPROTECT_DISABLE_DISABLE_Pos (0UL) /*!< Position of DISABLE field. */ +#define APPROTECT_DISABLE_DISABLE_Msk (0xFFUL << APPROTECT_DISABLE_DISABLE_Pos) /*!< Bit mask of DISABLE field. */ +#define APPROTECT_DISABLE_DISABLE_SwDisable (0x5AUL) /*!< Software disable APPROTECT mechanism */ + + /* Peripheral: BPROT */ /* Description: Block Protect */ diff --git a/mdk/nrf52805_peripherals.h b/mdk/nrf52805_peripherals.h index 43a262e472..179cd653d3 100644 --- a/mdk/nrf52805_peripherals.h +++ b/mdk/nrf52805_peripherals.h @@ -1,6 +1,8 @@ /* -Copyright (c) 2010 - 2020, Nordic Semiconductor ASA All rights reserved. +Copyright (c) 2010 - 2021, Nordic Semiconductor ASA All rights reserved. + +SPDX-License-Identifier: BSD-3-Clause Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: diff --git a/mdk/nrf52810.h b/mdk/nrf52810.h index 59c96e3208..1c0b1be603 100644 --- a/mdk/nrf52810.h +++ b/mdk/nrf52810.h @@ -1,5 +1,7 @@ /* - * Copyright (c) 2010 - 2020, Nordic Semiconductor ASA All rights reserved. + * Copyright (c) 2010 - 2021, Nordic Semiconductor ASA All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: @@ -30,10 +32,10 @@ * @file nrf52810.h * @brief CMSIS HeaderFile * @version 1 - * @date 04. November 2020 - * @note Generated by SVDConv V3.3.35 on Wednesday, 04.11.2020 13:48:07 + * @date 29. April 2021 + * @note Generated by SVDConv V3.3.35 on Thursday, 29.04.2021 12:43:43 * from File 'nrf52810.svd', - * last modified on Wednesday, 04.11.2020 12:48:01 + * last modified on Thursday, 29.04.2021 10:43:40 */ @@ -623,6 +625,25 @@ typedef struct { /*!< (@ 0x40000000) BPROT Struct +/* =========================================================================================================================== */ +/* ================ APPROTECT ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Only for emulation on devices that support hardened AP-PROTECT. (APPROTECT) + */ + +typedef struct { /*!< (@ 0x40000000) APPROTECT Structure */ + __IM uint32_t RESERVED[340]; + __IOM uint32_t FORCEPROTECT; /*!< (@ 0x00000550) Software force enable APPROTECT mechanism until + next reset. */ + __IM uint32_t RESERVED1; + __IOM uint32_t DISABLE; /*!< (@ 0x00000558) Software disable APPROTECT mechanism */ +} NRF_APPROTECT_Type; /*!< Size = 1372 (0x55c) */ + + + /* =========================================================================================================================== */ /* ================ CLOCK ================ */ /* =========================================================================================================================== */ @@ -1877,6 +1898,7 @@ typedef struct { /*!< (@ 0x4001F000) PPI Structur #define NRF_FICR_BASE 0x10000000UL #define NRF_UICR_BASE 0x10001000UL #define NRF_BPROT_BASE 0x40000000UL +#define NRF_APPROTECT_BASE 0x40000000UL #define NRF_CLOCK_BASE 0x40000000UL #define NRF_POWER_BASE 0x40000000UL #define NRF_P0_BASE 0x50000000UL @@ -1932,6 +1954,7 @@ typedef struct { /*!< (@ 0x4001F000) PPI Structur #define NRF_FICR ((NRF_FICR_Type*) NRF_FICR_BASE) #define NRF_UICR ((NRF_UICR_Type*) NRF_UICR_BASE) #define NRF_BPROT ((NRF_BPROT_Type*) NRF_BPROT_BASE) +#define NRF_APPROTECT ((NRF_APPROTECT_Type*) NRF_APPROTECT_BASE) #define NRF_CLOCK ((NRF_CLOCK_Type*) NRF_CLOCK_BASE) #define NRF_POWER ((NRF_POWER_Type*) NRF_POWER_BASE) #define NRF_P0 ((NRF_GPIO_Type*) NRF_P0_BASE) diff --git a/mdk/nrf52810.svd b/mdk/nrf52810.svd index a3f20b1f61..bb685077d2 100644 --- a/mdk/nrf52810.svd +++ b/mdk/nrf52810.svd @@ -8,7 +8,9 @@ 1 nRF52810 reference description for radio MCU with ARM 32-bit Cortex-M4 Microcontroller -Copyright (c) 2010 - 2020, Nordic Semiconductor ASA All rights reserved.\n +Copyright (c) 2010 - 2021, Nordic Semiconductor ASA All rights reserved.\n +\n +SPDX-License-Identifier: BSD-3-Clause\n \n Redistribution and use in source and binary forms, with or without\n modification, are permitted provided that the following conditions are met:\n @@ -1704,6 +1706,66 @@ POSSIBILITY OF SUCH DAMAGE.\n + + APPROTECT + Only for emulation on devices that support hardened AP-PROTECT. + 0x40000000 + BPROT + + 0 + 0x1000 + registers + + APPROTECT + 0x20 + + + FORCEPROTECT + Software force enable APPROTECT mechanism until next reset. + 0x550 + read-writeonce + 0xFFFFFFFF + + + FORCEPROTECT + Write 0x0 to force enable APPROTECT mechanism + 0 + 7 + + write + + Force + Software force enable APPROTECT mechanism + 0x0 + + + + + + + DISABLE + Software disable APPROTECT mechanism + 0x558 + read-write + 0x00000000 + + + DISABLE + Software disable APPROTECT mechanism + 0 + 7 + + + SwDisable + Software disable APPROTECT mechanism + 0x5A + + + + + + + CLOCK Clock control diff --git a/mdk/nrf52810_bitfields.h b/mdk/nrf52810_bitfields.h index 0b5111666d..c66acf1293 100644 --- a/mdk/nrf52810_bitfields.h +++ b/mdk/nrf52810_bitfields.h @@ -1,6 +1,8 @@ /* -Copyright (c) 2010 - 2020, Nordic Semiconductor ASA All rights reserved. +Copyright (c) 2010 - 2021, Nordic Semiconductor ASA All rights reserved. + +SPDX-License-Identifier: BSD-3-Clause Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: @@ -174,6 +176,26 @@ POSSIBILITY OF SUCH DAMAGE. #define AAR_SCRATCHPTR_SCRATCHPTR_Msk (0xFFFFFFFFUL << AAR_SCRATCHPTR_SCRATCHPTR_Pos) /*!< Bit mask of SCRATCHPTR field. */ +/* Peripheral: APPROTECT */ +/* Description: Only for emulation on devices that support hardened AP-PROTECT. */ + +/* Register: APPROTECT_FORCEPROTECT */ +/* Description: Software force enable APPROTECT mechanism until next reset. */ + +/* Bits 7..0 : Write 0x0 to force enable APPROTECT mechanism */ +#define APPROTECT_FORCEPROTECT_FORCEPROTECT_Pos (0UL) /*!< Position of FORCEPROTECT field. */ +#define APPROTECT_FORCEPROTECT_FORCEPROTECT_Msk (0xFFUL << APPROTECT_FORCEPROTECT_FORCEPROTECT_Pos) /*!< Bit mask of FORCEPROTECT field. */ +#define APPROTECT_FORCEPROTECT_FORCEPROTECT_Force (0x0UL) /*!< Software force enable APPROTECT mechanism */ + +/* Register: APPROTECT_DISABLE */ +/* Description: Software disable APPROTECT mechanism */ + +/* Bits 7..0 : Software disable APPROTECT mechanism */ +#define APPROTECT_DISABLE_DISABLE_Pos (0UL) /*!< Position of DISABLE field. */ +#define APPROTECT_DISABLE_DISABLE_Msk (0xFFUL << APPROTECT_DISABLE_DISABLE_Pos) /*!< Bit mask of DISABLE field. */ +#define APPROTECT_DISABLE_DISABLE_SwDisable (0x5AUL) /*!< Software disable APPROTECT mechanism */ + + /* Peripheral: BPROT */ /* Description: Block Protect */ diff --git a/mdk/nrf52810_name_change.h b/mdk/nrf52810_name_change.h index f357347463..0fd49d4ac0 100644 --- a/mdk/nrf52810_name_change.h +++ b/mdk/nrf52810_name_change.h @@ -1,6 +1,8 @@ /* -Copyright (c) 2010 - 2020, Nordic Semiconductor ASA All rights reserved. +Copyright (c) 2010 - 2021, Nordic Semiconductor ASA All rights reserved. + +SPDX-License-Identifier: BSD-3-Clause Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: diff --git a/mdk/nrf52810_peripherals.h b/mdk/nrf52810_peripherals.h index 9f39a7091c..044d12ff43 100644 --- a/mdk/nrf52810_peripherals.h +++ b/mdk/nrf52810_peripherals.h @@ -1,6 +1,8 @@ /* -Copyright (c) 2010 - 2020, Nordic Semiconductor ASA All rights reserved. +Copyright (c) 2010 - 2021, Nordic Semiconductor ASA All rights reserved. + +SPDX-License-Identifier: BSD-3-Clause Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: diff --git a/mdk/nrf52810_to_nrf52811.h b/mdk/nrf52810_to_nrf52811.h index 8e13c376d8..9d1fcf88a6 100644 --- a/mdk/nrf52810_to_nrf52811.h +++ b/mdk/nrf52810_to_nrf52811.h @@ -1,6 +1,8 @@ /* -Copyright (c) 2010 - 2020, Nordic Semiconductor ASA All rights reserved. +Copyright (c) 2010 - 2021, Nordic Semiconductor ASA All rights reserved. + +SPDX-License-Identifier: BSD-3-Clause Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: diff --git a/mdk/nrf52811.h b/mdk/nrf52811.h index 80e225b59c..330d0c678c 100644 --- a/mdk/nrf52811.h +++ b/mdk/nrf52811.h @@ -1,5 +1,7 @@ /* - * Copyright (c) 2010 - 2020, Nordic Semiconductor ASA All rights reserved. + * Copyright (c) 2010 - 2021, Nordic Semiconductor ASA All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: @@ -30,10 +32,10 @@ * @file nrf52811.h * @brief CMSIS HeaderFile * @version 1 - * @date 04. November 2020 - * @note Generated by SVDConv V3.3.35 on Wednesday, 04.11.2020 13:48:07 + * @date 29. April 2021 + * @note Generated by SVDConv V3.3.35 on Thursday, 29.04.2021 12:43:43 * from File 'nrf52811.svd', - * last modified on Wednesday, 04.11.2020 12:48:01 + * last modified on Thursday, 29.04.2021 10:43:40 */ @@ -642,6 +644,25 @@ typedef struct { /*!< (@ 0x40000000) BPROT Struct +/* =========================================================================================================================== */ +/* ================ APPROTECT ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Only for emulation on devices that support hardened AP-PROTECT. (APPROTECT) + */ + +typedef struct { /*!< (@ 0x40000000) APPROTECT Structure */ + __IM uint32_t RESERVED[340]; + __IOM uint32_t FORCEPROTECT; /*!< (@ 0x00000550) Software force enable APPROTECT mechanism until + next reset. */ + __IM uint32_t RESERVED1; + __IOM uint32_t DISABLE; /*!< (@ 0x00000558) Software disable APPROTECT mechanism */ +} NRF_APPROTECT_Type; /*!< Size = 1372 (0x55c) */ + + + /* =========================================================================================================================== */ /* ================ CLOCK ================ */ /* =========================================================================================================================== */ @@ -1945,6 +1966,7 @@ typedef struct { /*!< (@ 0x4001F000) PPI Structur #define NRF_FICR_BASE 0x10000000UL #define NRF_UICR_BASE 0x10001000UL #define NRF_BPROT_BASE 0x40000000UL +#define NRF_APPROTECT_BASE 0x40000000UL #define NRF_CLOCK_BASE 0x40000000UL #define NRF_POWER_BASE 0x40000000UL #define NRF_P0_BASE 0x50000000UL @@ -2003,6 +2025,7 @@ typedef struct { /*!< (@ 0x4001F000) PPI Structur #define NRF_FICR ((NRF_FICR_Type*) NRF_FICR_BASE) #define NRF_UICR ((NRF_UICR_Type*) NRF_UICR_BASE) #define NRF_BPROT ((NRF_BPROT_Type*) NRF_BPROT_BASE) +#define NRF_APPROTECT ((NRF_APPROTECT_Type*) NRF_APPROTECT_BASE) #define NRF_CLOCK ((NRF_CLOCK_Type*) NRF_CLOCK_BASE) #define NRF_POWER ((NRF_POWER_Type*) NRF_POWER_BASE) #define NRF_P0 ((NRF_GPIO_Type*) NRF_P0_BASE) diff --git a/mdk/nrf52811.svd b/mdk/nrf52811.svd index 34d7b79c2b..2f12943631 100644 --- a/mdk/nrf52811.svd +++ b/mdk/nrf52811.svd @@ -8,7 +8,9 @@ 1 nRF52811 reference description for radio MCU with ARM 32-bit Cortex-M4 Microcontroller -Copyright (c) 2010 - 2020, Nordic Semiconductor ASA All rights reserved.\n +Copyright (c) 2010 - 2021, Nordic Semiconductor ASA All rights reserved.\n +\n +SPDX-License-Identifier: BSD-3-Clause\n \n Redistribution and use in source and binary forms, with or without\n modification, are permitted provided that the following conditions are met:\n @@ -1704,6 +1706,66 @@ POSSIBILITY OF SUCH DAMAGE.\n + + APPROTECT + Only for emulation on devices that support hardened AP-PROTECT. + 0x40000000 + BPROT + + 0 + 0x1000 + registers + + APPROTECT + 0x20 + + + FORCEPROTECT + Software force enable APPROTECT mechanism until next reset. + 0x550 + read-writeonce + 0xFFFFFFFF + + + FORCEPROTECT + Write 0x0 to force enable APPROTECT mechanism + 0 + 7 + + write + + Force + Software force enable APPROTECT mechanism + 0x0 + + + + + + + DISABLE + Software disable APPROTECT mechanism + 0x558 + read-write + 0x00000000 + + + DISABLE + Software disable APPROTECT mechanism + 0 + 7 + + + SwDisable + Software disable APPROTECT mechanism + 0x5A + + + + + + + CLOCK Clock control diff --git a/mdk/nrf52811_bitfields.h b/mdk/nrf52811_bitfields.h index 1a7981f2d1..d24a16b31d 100644 --- a/mdk/nrf52811_bitfields.h +++ b/mdk/nrf52811_bitfields.h @@ -1,6 +1,8 @@ /* -Copyright (c) 2010 - 2020, Nordic Semiconductor ASA All rights reserved. +Copyright (c) 2010 - 2021, Nordic Semiconductor ASA All rights reserved. + +SPDX-License-Identifier: BSD-3-Clause Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: @@ -174,6 +176,26 @@ POSSIBILITY OF SUCH DAMAGE. #define AAR_SCRATCHPTR_SCRATCHPTR_Msk (0xFFFFFFFFUL << AAR_SCRATCHPTR_SCRATCHPTR_Pos) /*!< Bit mask of SCRATCHPTR field. */ +/* Peripheral: APPROTECT */ +/* Description: Only for emulation on devices that support hardened AP-PROTECT. */ + +/* Register: APPROTECT_FORCEPROTECT */ +/* Description: Software force enable APPROTECT mechanism until next reset. */ + +/* Bits 7..0 : Write 0x0 to force enable APPROTECT mechanism */ +#define APPROTECT_FORCEPROTECT_FORCEPROTECT_Pos (0UL) /*!< Position of FORCEPROTECT field. */ +#define APPROTECT_FORCEPROTECT_FORCEPROTECT_Msk (0xFFUL << APPROTECT_FORCEPROTECT_FORCEPROTECT_Pos) /*!< Bit mask of FORCEPROTECT field. */ +#define APPROTECT_FORCEPROTECT_FORCEPROTECT_Force (0x0UL) /*!< Software force enable APPROTECT mechanism */ + +/* Register: APPROTECT_DISABLE */ +/* Description: Software disable APPROTECT mechanism */ + +/* Bits 7..0 : Software disable APPROTECT mechanism */ +#define APPROTECT_DISABLE_DISABLE_Pos (0UL) /*!< Position of DISABLE field. */ +#define APPROTECT_DISABLE_DISABLE_Msk (0xFFUL << APPROTECT_DISABLE_DISABLE_Pos) /*!< Bit mask of DISABLE field. */ +#define APPROTECT_DISABLE_DISABLE_SwDisable (0x5AUL) /*!< Software disable APPROTECT mechanism */ + + /* Peripheral: BPROT */ /* Description: Block Protect */ diff --git a/mdk/nrf52811_peripherals.h b/mdk/nrf52811_peripherals.h index 46951babfd..354578c8eb 100644 --- a/mdk/nrf52811_peripherals.h +++ b/mdk/nrf52811_peripherals.h @@ -1,6 +1,8 @@ /* -Copyright (c) 2010 - 2020, Nordic Semiconductor ASA All rights reserved. +Copyright (c) 2010 - 2021, Nordic Semiconductor ASA All rights reserved. + +SPDX-License-Identifier: BSD-3-Clause Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: diff --git a/mdk/nrf52820.h b/mdk/nrf52820.h index 19206cd253..b2c42a12db 100644 --- a/mdk/nrf52820.h +++ b/mdk/nrf52820.h @@ -1,5 +1,7 @@ /* - * Copyright (c) 2010 - 2020, Nordic Semiconductor ASA All rights reserved. + * Copyright (c) 2010 - 2021, Nordic Semiconductor ASA All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: @@ -30,10 +32,10 @@ * @file nrf52820.h * @brief CMSIS HeaderFile * @version 1 - * @date 04. November 2020 - * @note Generated by SVDConv V3.3.35 on Wednesday, 04.11.2020 13:48:07 + * @date 29. April 2021 + * @note Generated by SVDConv V3.3.35 on Thursday, 29.04.2021 12:43:44 * from File 'nrf52820.svd', - * last modified on Wednesday, 04.11.2020 12:48:01 + * last modified on Thursday, 29.04.2021 10:43:41 */ @@ -470,8 +472,8 @@ typedef struct { * @brief PPI_CH [CH] (PPI Channel) */ typedef struct { - __IOM uint32_t EEP; /*!< (@ 0x00000000) Description cluster: Channel n event end-point */ - __IOM uint32_t TEP; /*!< (@ 0x00000004) Description cluster: Channel n task end-point */ + __IOM uint32_t EEP; /*!< (@ 0x00000000) Description cluster: Channel n event endpoint */ + __IOM uint32_t TEP; /*!< (@ 0x00000004) Description cluster: Channel n task endpoint */ } PPI_CH_Type; /*!< Size = 8 (0x8) */ @@ -479,7 +481,7 @@ typedef struct { * @brief PPI_FORK [FORK] (Fork) */ typedef struct { - __IOM uint32_t TEP; /*!< (@ 0x00000000) Description cluster: Channel n task end-point */ + __IOM uint32_t TEP; /*!< (@ 0x00000000) Description cluster: Channel n task endpoint */ } PPI_FORK_Type; /*!< Size = 4 (0x4) */ @@ -627,11 +629,30 @@ typedef struct { /*!< (@ 0x10001000) UICR Structu __IM uint32_t RESERVED4[60]; __IOM uint32_t REGOUT0; /*!< (@ 0x00000304) Output voltage from REG0 regulator stage. The maximum output voltage from this stage is - given as VDDH - VREG0DROP. */ + given as VDDH - V_VDDH-VDD. */ } NRF_UICR_Type; /*!< Size = 776 (0x308) */ +/* =========================================================================================================================== */ +/* ================ APPROTECT ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Access Port Protection (APPROTECT) + */ + +typedef struct { /*!< (@ 0x40000000) APPROTECT Structure */ + __IM uint32_t RESERVED[340]; + __IOM uint32_t FORCEPROTECT; /*!< (@ 0x00000550) Software force enable APPROTECT mechanism until + next reset. */ + __IM uint32_t RESERVED1; + __IOM uint32_t DISABLE; /*!< (@ 0x00000558) Software disable APPROTECT mechanism */ +} NRF_APPROTECT_Type; /*!< Size = 1372 (0x55c) */ + + + /* =========================================================================================================================== */ /* ================ CLOCK ================ */ /* =========================================================================================================================== */ @@ -755,7 +776,7 @@ typedef struct { /*!< (@ 0x50000000) P0 Structure __IOM uint32_t LATCH; /*!< (@ 0x00000520) Latch register indicating what GPIO pins that have met the criteria set in the PIN_CNF[n].SENSE registers */ - __IOM uint32_t DETECTMODE; /*!< (@ 0x00000524) Select between default DETECT signal behaviour + __IOM uint32_t DETECTMODE; /*!< (@ 0x00000524) Select between default DETECT signal behavior and LDETECT mode */ __IM uint32_t RESERVED1[118]; __IOM uint32_t PIN_CNF[32]; /*!< (@ 0x00000700) Description collection: Configuration of GPIO @@ -809,7 +830,7 @@ typedef struct { /*!< (@ 0x40001000) RADIO Struct __IOM uint32_t EVENTS_FRAMESTART; /*!< (@ 0x00000138) IEEE 802.15.4 length field received */ __IOM uint32_t EVENTS_EDEND; /*!< (@ 0x0000013C) Sampling of energy detection complete. A new ED sample is ready for readout from the - RADIO.EDSAMPLE register */ + RADIO.EDSAMPLE register. */ __IOM uint32_t EVENTS_EDSTOPPED; /*!< (@ 0x00000140) The sampling of energy detection has stopped */ __IOM uint32_t EVENTS_CCAIDLE; /*!< (@ 0x00000144) Wireless medium in idle - clear to send */ __IOM uint32_t EVENTS_CCABUSY; /*!< (@ 0x00000148) Wireless medium busy - do not send */ @@ -989,8 +1010,8 @@ typedef struct { /*!< (@ 0x40002000) UARTE0 Struc __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ __IM uint32_t RESERVED9[93]; - __IOM uint32_t ERRORSRC; /*!< (@ 0x00000480) Error source Note : this register is read / write - one to clear. */ + __IOM uint32_t ERRORSRC; /*!< (@ 0x00000480) Error source This register is read/write one + to clear. */ __IM uint32_t RESERVED10[31]; __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable UART */ __IM uint32_t RESERVED11; @@ -1212,9 +1233,8 @@ typedef struct { /*!< (@ 0x40003000) TWIM0 Struct __IM uint32_t RESERVED4[7]; __IOM uint32_t EVENTS_ERROR; /*!< (@ 0x00000124) TWI error */ __IM uint32_t RESERVED5[8]; - __IOM uint32_t EVENTS_SUSPENDED; /*!< (@ 0x00000148) Last byte has been sent out after the SUSPEND - task has been issued, TWI traffic is now - suspended. */ + __IOM uint32_t EVENTS_SUSPENDED; /*!< (@ 0x00000148) SUSPEND task has been issued, TWI traffic is + now suspended. */ __IOM uint32_t EVENTS_RXSTARTED; /*!< (@ 0x0000014C) Receive sequence started */ __IOM uint32_t EVENTS_TXSTARTED; /*!< (@ 0x00000150) Transmit sequence started */ __IM uint32_t RESERVED6[2]; @@ -1406,8 +1426,8 @@ typedef struct { /*!< (@ 0x4000B000) RTC0 Structu __IOM uint32_t EVTENCLR; /*!< (@ 0x00000348) Disable event routing */ __IM uint32_t RESERVED4[110]; __IM uint32_t COUNTER; /*!< (@ 0x00000504) Current COUNTER value */ - __IOM uint32_t PRESCALER; /*!< (@ 0x00000508) 12 bit prescaler for COUNTER frequency (32768/(PRESCALER+1)).Mu - t be written when RTC is stopped */ + __IOM uint32_t PRESCALER; /*!< (@ 0x00000508) 12 bit prescaler for COUNTER frequency (32768/(PRESCALER+1)). + Must be written when RTC is stopped. */ __IM uint32_t RESERVED5[13]; __IOM uint32_t CC[4]; /*!< (@ 0x00000540) Description collection: Compare register n */ } NRF_RTC_Type; /*!< Size = 1360 (0x550) */ @@ -1434,25 +1454,25 @@ typedef struct { /*!< (@ 0x4000C000) TEMP Structu __IM uint32_t RESERVED2[127]; __IM int32_t TEMP; /*!< (@ 0x00000508) Temperature in degC (0.25deg steps) */ __IM uint32_t RESERVED3[5]; - __IOM uint32_t A0; /*!< (@ 0x00000520) Slope of 1st piece wise linear function */ - __IOM uint32_t A1; /*!< (@ 0x00000524) Slope of 2nd piece wise linear function */ - __IOM uint32_t A2; /*!< (@ 0x00000528) Slope of 3rd piece wise linear function */ - __IOM uint32_t A3; /*!< (@ 0x0000052C) Slope of 4th piece wise linear function */ - __IOM uint32_t A4; /*!< (@ 0x00000530) Slope of 5th piece wise linear function */ - __IOM uint32_t A5; /*!< (@ 0x00000534) Slope of 6th piece wise linear function */ + __IOM uint32_t A0; /*!< (@ 0x00000520) Slope of first piecewise linear function */ + __IOM uint32_t A1; /*!< (@ 0x00000524) Slope of second piecewise linear function */ + __IOM uint32_t A2; /*!< (@ 0x00000528) Slope of third piecewise linear function */ + __IOM uint32_t A3; /*!< (@ 0x0000052C) Slope of fourth piecewise linear function */ + __IOM uint32_t A4; /*!< (@ 0x00000530) Slope of fifth piecewise linear function */ + __IOM uint32_t A5; /*!< (@ 0x00000534) Slope of sixth piecewise linear function */ __IM uint32_t RESERVED4[2]; - __IOM uint32_t B0; /*!< (@ 0x00000540) y-intercept of 1st piece wise linear function */ - __IOM uint32_t B1; /*!< (@ 0x00000544) y-intercept of 2nd piece wise linear function */ - __IOM uint32_t B2; /*!< (@ 0x00000548) y-intercept of 3rd piece wise linear function */ - __IOM uint32_t B3; /*!< (@ 0x0000054C) y-intercept of 4th piece wise linear function */ - __IOM uint32_t B4; /*!< (@ 0x00000550) y-intercept of 5th piece wise linear function */ - __IOM uint32_t B5; /*!< (@ 0x00000554) y-intercept of 6th piece wise linear function */ + __IOM uint32_t B0; /*!< (@ 0x00000540) y-intercept of first piecewise linear function */ + __IOM uint32_t B1; /*!< (@ 0x00000544) y-intercept of second piecewise linear function */ + __IOM uint32_t B2; /*!< (@ 0x00000548) y-intercept of third piecewise linear function */ + __IOM uint32_t B3; /*!< (@ 0x0000054C) y-intercept of fourth piecewise linear function */ + __IOM uint32_t B4; /*!< (@ 0x00000550) y-intercept of fifth piecewise linear function */ + __IOM uint32_t B5; /*!< (@ 0x00000554) y-intercept of sixth piecewise linear function */ __IM uint32_t RESERVED5[2]; - __IOM uint32_t T0; /*!< (@ 0x00000560) End point of 1st piece wise linear function */ - __IOM uint32_t T1; /*!< (@ 0x00000564) End point of 2nd piece wise linear function */ - __IOM uint32_t T2; /*!< (@ 0x00000568) End point of 3rd piece wise linear function */ - __IOM uint32_t T3; /*!< (@ 0x0000056C) End point of 4th piece wise linear function */ - __IOM uint32_t T4; /*!< (@ 0x00000570) End point of 5th piece wise linear function */ + __IOM uint32_t T0; /*!< (@ 0x00000560) End point of first piecewise linear function */ + __IOM uint32_t T1; /*!< (@ 0x00000564) End point of second piecewise linear function */ + __IOM uint32_t T2; /*!< (@ 0x00000568) End point of third piecewise linear function */ + __IOM uint32_t T3; /*!< (@ 0x0000056C) End point of fourth piecewise linear function */ + __IOM uint32_t T4; /*!< (@ 0x00000570) End point of fifth piecewise linear function */ } NRF_TEMP_Type; /*!< Size = 1396 (0x574) */ @@ -1553,7 +1573,7 @@ typedef struct { /*!< (@ 0x4000F000) AAR Structur */ typedef struct { /*!< (@ 0x4000F000) CCM Structure */ - __OM uint32_t TASKS_KSGEN; /*!< (@ 0x00000000) Start generation of key-stream. This operation + __OM uint32_t TASKS_KSGEN; /*!< (@ 0x00000000) Start generation of keystream. This operation will stop by itself when completed. */ __OM uint32_t TASKS_CRYPT; /*!< (@ 0x00000004) Start encryption/decryption. This operation will stop by itself when completed. */ @@ -1562,7 +1582,7 @@ typedef struct { /*!< (@ 0x4000F000) CCM Structur the contents of the RATEOVERRIDE register for any ongoing encryption/decryption */ __IM uint32_t RESERVED[60]; - __IOM uint32_t EVENTS_ENDKSGEN; /*!< (@ 0x00000100) Key-stream generation complete */ + __IOM uint32_t EVENTS_ENDKSGEN; /*!< (@ 0x00000100) Keystream generation complete */ __IOM uint32_t EVENTS_ENDCRYPT; /*!< (@ 0x00000104) Encrypt/decrypt complete */ __IOM uint32_t EVENTS_ERROR; /*!< (@ 0x00000108) Deprecated register - CCM error event */ __IM uint32_t RESERVED1[61]; @@ -1580,7 +1600,7 @@ typedef struct { /*!< (@ 0x4000F000) CCM Structur __IOM uint32_t INPTR; /*!< (@ 0x0000050C) Input pointer */ __IOM uint32_t OUTPTR; /*!< (@ 0x00000510) Output pointer */ __IOM uint32_t SCRATCHPTR; /*!< (@ 0x00000514) Pointer to data area used for temporary storage */ - __IOM uint32_t MAXPACKETSIZE; /*!< (@ 0x00000518) Length of key-stream generated when MODE.LENGTH + __IOM uint32_t MAXPACKETSIZE; /*!< (@ 0x00000518) Length of keystream generated when MODE.LENGTH = Extended. */ __IOM uint32_t RATEOVERRIDE; /*!< (@ 0x0000051C) Data rate override setting. */ } NRF_CCM_Type; /*!< Size = 1312 (0x520) */ @@ -1949,6 +1969,7 @@ typedef struct { /*!< (@ 0x40027000) USBD Structu #define NRF_FICR_BASE 0x10000000UL #define NRF_UICR_BASE 0x10001000UL +#define NRF_APPROTECT_BASE 0x40000000UL #define NRF_CLOCK_BASE 0x40000000UL #define NRF_POWER_BASE 0x40000000UL #define NRF_P0_BASE 0x50000000UL @@ -2013,6 +2034,7 @@ typedef struct { /*!< (@ 0x40027000) USBD Structu #define NRF_FICR ((NRF_FICR_Type*) NRF_FICR_BASE) #define NRF_UICR ((NRF_UICR_Type*) NRF_UICR_BASE) +#define NRF_APPROTECT ((NRF_APPROTECT_Type*) NRF_APPROTECT_BASE) #define NRF_CLOCK ((NRF_CLOCK_Type*) NRF_CLOCK_BASE) #define NRF_POWER ((NRF_POWER_Type*) NRF_POWER_BASE) #define NRF_P0 ((NRF_GPIO_Type*) NRF_P0_BASE) diff --git a/mdk/nrf52820.svd b/mdk/nrf52820.svd index 9b8c00a3b5..428c22d1e3 100644 --- a/mdk/nrf52820.svd +++ b/mdk/nrf52820.svd @@ -6,9 +6,11 @@ nrf52820 nrf52 1 - nRF52833 reference description for radio MCU with ARM 32-bit Cortex-M4 Microcontroller + nRF52820 reference description for radio MCU with ARM 32-bit Cortex-M4 Microcontroller -Copyright (c) 2010 - 2020, Nordic Semiconductor ASA All rights reserved.\n +Copyright (c) 2010 - 2021, Nordic Semiconductor ASA All rights reserved.\n +\n +SPDX-License-Identifier: BSD-3-Clause\n \n Redistribution and use in source and binary forms, with or without\n modification, are permitted provided that the following conditions are met:\n @@ -256,6 +258,21 @@ POSSIBILITY OF SUCH DAMAGE.\n AAAA 0x41414141 + + AABC + AABC + 0x41414243 + + + AAC0 + AAC0 + 0x41414330 + + + AAC1 + AAC1 + 0x41414331 + Unspecified Unspecified @@ -280,7 +297,7 @@ POSSIBILITY OF SUCH DAMAGE.\n QD - QDxx - 40-pin QFN + QDxx - 5x5 40-pin QFN 0x2007 @@ -793,9 +810,14 @@ POSSIBILITY OF SUCH DAMAGE.\n Disabled - Disable + Hardware disable of access port protection for devices where access port protection is controlled by hardware 0xFF + + HwDisabled + Hardware disable of access port protection for devices where access port protection is controlled by hardware and software + 0x5A + Enabled Enable @@ -834,7 +856,7 @@ POSSIBILITY OF SUCH DAMAGE.\n REGOUT0 - Output voltage from REG0 regulator stage. The maximum output voltage from this stage is given as VDDH - VREG0DROP. + Output voltage from REG0 regulator stage. The maximum output voltage from this stage is given as VDDH - V_VDDH-VDD. 0x304 read-write 0xFFFFFFFF @@ -886,10 +908,70 @@ POSSIBILITY OF SUCH DAMAGE.\n + + APPROTECT + Access Port Protection + 0x40000000 + + 0 + 0x1000 + registers + + APPROTECT + 0x20 + + + FORCEPROTECT + Software force enable APPROTECT mechanism until next reset. + 0x550 + read-writeonce + 0xFFFFFFFF + + + FORCEPROTECT + Write 0x0 to force enable APPROTECT mechanism + 0 + 7 + + write + + Force + Software force enable APPROTECT mechanism + 0x0 + + + + + + + DISABLE + Software disable APPROTECT mechanism + 0x558 + read-write + 0x00000000 + + + DISABLE + Software disable APPROTECT mechanism + 0 + 7 + + + SwDisable + Software disable APPROTECT mechanism + 0x5A + + + + + + + CLOCK Clock control 0x40000000 + APPROTECT 0 0x1000 @@ -1862,7 +1944,7 @@ POSSIBILITY OF SUCH DAMAGE.\n POWER Power control 0x40000000 - CLOCK + APPROTECT 0 0x1000 @@ -3761,7 +3843,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets the pin high; writing a '0' has no effect + Write: a '1' sets the pin high; a '0' has no effect 1 @@ -3788,7 +3870,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets the pin high; writing a '0' has no effect + Write: a '1' sets the pin high; a '0' has no effect 1 @@ -3815,7 +3897,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets the pin high; writing a '0' has no effect + Write: a '1' sets the pin high; a '0' has no effect 1 @@ -3842,7 +3924,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets the pin high; writing a '0' has no effect + Write: a '1' sets the pin high; a '0' has no effect 1 @@ -3869,7 +3951,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets the pin high; writing a '0' has no effect + Write: a '1' sets the pin high; a '0' has no effect 1 @@ -3896,7 +3978,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets the pin high; writing a '0' has no effect + Write: a '1' sets the pin high; a '0' has no effect 1 @@ -3923,7 +4005,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets the pin high; writing a '0' has no effect + Write: a '1' sets the pin high; a '0' has no effect 1 @@ -3950,7 +4032,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets the pin high; writing a '0' has no effect + Write: a '1' sets the pin high; a '0' has no effect 1 @@ -3977,7 +4059,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets the pin high; writing a '0' has no effect + Write: a '1' sets the pin high; a '0' has no effect 1 @@ -4004,7 +4086,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets the pin high; writing a '0' has no effect + Write: a '1' sets the pin high; a '0' has no effect 1 @@ -4031,7 +4113,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets the pin high; writing a '0' has no effect + Write: a '1' sets the pin high; a '0' has no effect 1 @@ -4058,7 +4140,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets the pin high; writing a '0' has no effect + Write: a '1' sets the pin high; a '0' has no effect 1 @@ -4085,7 +4167,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets the pin high; writing a '0' has no effect + Write: a '1' sets the pin high; a '0' has no effect 1 @@ -4112,7 +4194,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets the pin high; writing a '0' has no effect + Write: a '1' sets the pin high; a '0' has no effect 1 @@ -4139,7 +4221,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets the pin high; writing a '0' has no effect + Write: a '1' sets the pin high; a '0' has no effect 1 @@ -4166,7 +4248,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets the pin high; writing a '0' has no effect + Write: a '1' sets the pin high; a '0' has no effect 1 @@ -4193,7 +4275,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets the pin high; writing a '0' has no effect + Write: a '1' sets the pin high; a '0' has no effect 1 @@ -4220,7 +4302,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets the pin high; writing a '0' has no effect + Write: a '1' sets the pin high; a '0' has no effect 1 @@ -4247,7 +4329,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets the pin high; writing a '0' has no effect + Write: a '1' sets the pin high; a '0' has no effect 1 @@ -4274,7 +4356,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets the pin high; writing a '0' has no effect + Write: a '1' sets the pin high; a '0' has no effect 1 @@ -4301,7 +4383,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets the pin high; writing a '0' has no effect + Write: a '1' sets the pin high; a '0' has no effect 1 @@ -4328,7 +4410,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets the pin high; writing a '0' has no effect + Write: a '1' sets the pin high; a '0' has no effect 1 @@ -4355,7 +4437,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets the pin high; writing a '0' has no effect + Write: a '1' sets the pin high; a '0' has no effect 1 @@ -4382,7 +4464,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets the pin high; writing a '0' has no effect + Write: a '1' sets the pin high; a '0' has no effect 1 @@ -4409,7 +4491,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets the pin high; writing a '0' has no effect + Write: a '1' sets the pin high; a '0' has no effect 1 @@ -4436,7 +4518,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets the pin high; writing a '0' has no effect + Write: a '1' sets the pin high; a '0' has no effect 1 @@ -4463,7 +4545,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets the pin high; writing a '0' has no effect + Write: a '1' sets the pin high; a '0' has no effect 1 @@ -4490,7 +4572,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets the pin high; writing a '0' has no effect + Write: a '1' sets the pin high; a '0' has no effect 1 @@ -4517,7 +4599,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets the pin high; writing a '0' has no effect + Write: a '1' sets the pin high; a '0' has no effect 1 @@ -4544,7 +4626,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets the pin high; writing a '0' has no effect + Write: a '1' sets the pin high; a '0' has no effect 1 @@ -4571,7 +4653,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets the pin high; writing a '0' has no effect + Write: a '1' sets the pin high; a '0' has no effect 1 @@ -4598,7 +4680,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets the pin high; writing a '0' has no effect + Write: a '1' sets the pin high; a '0' has no effect 1 @@ -4634,7 +4716,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect + Write: a '1' sets the pin low; a '0' has no effect 1 @@ -4661,7 +4743,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect + Write: a '1' sets the pin low; a '0' has no effect 1 @@ -4688,7 +4770,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect + Write: a '1' sets the pin low; a '0' has no effect 1 @@ -4715,7 +4797,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect + Write: a '1' sets the pin low; a '0' has no effect 1 @@ -4742,7 +4824,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect + Write: a '1' sets the pin low; a '0' has no effect 1 @@ -4769,7 +4851,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect + Write: a '1' sets the pin low; a '0' has no effect 1 @@ -4796,7 +4878,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect + Write: a '1' sets the pin low; a '0' has no effect 1 @@ -4823,7 +4905,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect + Write: a '1' sets the pin low; a '0' has no effect 1 @@ -4850,7 +4932,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect + Write: a '1' sets the pin low; a '0' has no effect 1 @@ -4877,7 +4959,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect + Write: a '1' sets the pin low; a '0' has no effect 1 @@ -4904,7 +4986,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect + Write: a '1' sets the pin low; a '0' has no effect 1 @@ -4931,7 +5013,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect + Write: a '1' sets the pin low; a '0' has no effect 1 @@ -4958,7 +5040,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect + Write: a '1' sets the pin low; a '0' has no effect 1 @@ -4985,7 +5067,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect + Write: a '1' sets the pin low; a '0' has no effect 1 @@ -5012,7 +5094,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect + Write: a '1' sets the pin low; a '0' has no effect 1 @@ -5039,7 +5121,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect + Write: a '1' sets the pin low; a '0' has no effect 1 @@ -5066,7 +5148,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect + Write: a '1' sets the pin low; a '0' has no effect 1 @@ -5093,7 +5175,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect + Write: a '1' sets the pin low; a '0' has no effect 1 @@ -5120,7 +5202,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect + Write: a '1' sets the pin low; a '0' has no effect 1 @@ -5147,7 +5229,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect + Write: a '1' sets the pin low; a '0' has no effect 1 @@ -5174,7 +5256,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect + Write: a '1' sets the pin low; a '0' has no effect 1 @@ -5201,7 +5283,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect + Write: a '1' sets the pin low; a '0' has no effect 1 @@ -5228,7 +5310,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect + Write: a '1' sets the pin low; a '0' has no effect 1 @@ -5255,7 +5337,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect + Write: a '1' sets the pin low; a '0' has no effect 1 @@ -5282,7 +5364,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect + Write: a '1' sets the pin low; a '0' has no effect 1 @@ -5309,7 +5391,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect + Write: a '1' sets the pin low; a '0' has no effect 1 @@ -5336,7 +5418,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect + Write: a '1' sets the pin low; a '0' has no effect 1 @@ -5363,7 +5445,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect + Write: a '1' sets the pin low; a '0' has no effect 1 @@ -5390,7 +5472,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect + Write: a '1' sets the pin low; a '0' has no effect 1 @@ -5417,7 +5499,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect + Write: a '1' sets the pin low; a '0' has no effect 1 @@ -5444,7 +5526,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect + Write: a '1' sets the pin low; a '0' has no effect 1 @@ -5471,7 +5553,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect + Write: a '1' sets the pin low; a '0' has no effect 1 @@ -6675,7 +6757,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets pin to output; writing a '0' has no effect + Write: a '1' sets pin to output; a '0' has no effect 1 @@ -6702,7 +6784,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets pin to output; writing a '0' has no effect + Write: a '1' sets pin to output; a '0' has no effect 1 @@ -6729,7 +6811,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets pin to output; writing a '0' has no effect + Write: a '1' sets pin to output; a '0' has no effect 1 @@ -6756,7 +6838,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets pin to output; writing a '0' has no effect + Write: a '1' sets pin to output; a '0' has no effect 1 @@ -6783,7 +6865,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets pin to output; writing a '0' has no effect + Write: a '1' sets pin to output; a '0' has no effect 1 @@ -6810,7 +6892,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets pin to output; writing a '0' has no effect + Write: a '1' sets pin to output; a '0' has no effect 1 @@ -6837,7 +6919,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets pin to output; writing a '0' has no effect + Write: a '1' sets pin to output; a '0' has no effect 1 @@ -6864,7 +6946,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets pin to output; writing a '0' has no effect + Write: a '1' sets pin to output; a '0' has no effect 1 @@ -6891,7 +6973,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets pin to output; writing a '0' has no effect + Write: a '1' sets pin to output; a '0' has no effect 1 @@ -6918,7 +7000,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets pin to output; writing a '0' has no effect + Write: a '1' sets pin to output; a '0' has no effect 1 @@ -6945,7 +7027,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets pin to output; writing a '0' has no effect + Write: a '1' sets pin to output; a '0' has no effect 1 @@ -6972,7 +7054,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets pin to output; writing a '0' has no effect + Write: a '1' sets pin to output; a '0' has no effect 1 @@ -6999,7 +7081,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets pin to output; writing a '0' has no effect + Write: a '1' sets pin to output; a '0' has no effect 1 @@ -7026,7 +7108,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets pin to output; writing a '0' has no effect + Write: a '1' sets pin to output; a '0' has no effect 1 @@ -7053,7 +7135,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets pin to output; writing a '0' has no effect + Write: a '1' sets pin to output; a '0' has no effect 1 @@ -7080,7 +7162,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets pin to output; writing a '0' has no effect + Write: a '1' sets pin to output; a '0' has no effect 1 @@ -7107,7 +7189,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets pin to output; writing a '0' has no effect + Write: a '1' sets pin to output; a '0' has no effect 1 @@ -7134,7 +7216,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets pin to output; writing a '0' has no effect + Write: a '1' sets pin to output; a '0' has no effect 1 @@ -7161,7 +7243,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets pin to output; writing a '0' has no effect + Write: a '1' sets pin to output; a '0' has no effect 1 @@ -7188,7 +7270,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets pin to output; writing a '0' has no effect + Write: a '1' sets pin to output; a '0' has no effect 1 @@ -7215,7 +7297,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets pin to output; writing a '0' has no effect + Write: a '1' sets pin to output; a '0' has no effect 1 @@ -7242,7 +7324,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets pin to output; writing a '0' has no effect + Write: a '1' sets pin to output; a '0' has no effect 1 @@ -7269,7 +7351,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets pin to output; writing a '0' has no effect + Write: a '1' sets pin to output; a '0' has no effect 1 @@ -7296,7 +7378,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets pin to output; writing a '0' has no effect + Write: a '1' sets pin to output; a '0' has no effect 1 @@ -7323,7 +7405,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets pin to output; writing a '0' has no effect + Write: a '1' sets pin to output; a '0' has no effect 1 @@ -7350,7 +7432,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets pin to output; writing a '0' has no effect + Write: a '1' sets pin to output; a '0' has no effect 1 @@ -7377,7 +7459,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets pin to output; writing a '0' has no effect + Write: a '1' sets pin to output; a '0' has no effect 1 @@ -7404,7 +7486,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets pin to output; writing a '0' has no effect + Write: a '1' sets pin to output; a '0' has no effect 1 @@ -7431,7 +7513,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets pin to output; writing a '0' has no effect + Write: a '1' sets pin to output; a '0' has no effect 1 @@ -7458,7 +7540,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets pin to output; writing a '0' has no effect + Write: a '1' sets pin to output; a '0' has no effect 1 @@ -7485,7 +7567,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets pin to output; writing a '0' has no effect + Write: a '1' sets pin to output; a '0' has no effect 1 @@ -7512,7 +7594,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets pin to output; writing a '0' has no effect + Write: a '1' sets pin to output; a '0' has no effect 1 @@ -7548,7 +7630,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect + Write: a '1' sets pin to input; a '0' has no effect 1 @@ -7575,7 +7657,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect + Write: a '1' sets pin to input; a '0' has no effect 1 @@ -7602,7 +7684,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect + Write: a '1' sets pin to input; a '0' has no effect 1 @@ -7629,7 +7711,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect + Write: a '1' sets pin to input; a '0' has no effect 1 @@ -7656,7 +7738,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect + Write: a '1' sets pin to input; a '0' has no effect 1 @@ -7683,7 +7765,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect + Write: a '1' sets pin to input; a '0' has no effect 1 @@ -7710,7 +7792,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect + Write: a '1' sets pin to input; a '0' has no effect 1 @@ -7737,7 +7819,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect + Write: a '1' sets pin to input; a '0' has no effect 1 @@ -7764,7 +7846,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect + Write: a '1' sets pin to input; a '0' has no effect 1 @@ -7791,7 +7873,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect + Write: a '1' sets pin to input; a '0' has no effect 1 @@ -7818,7 +7900,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect + Write: a '1' sets pin to input; a '0' has no effect 1 @@ -7845,7 +7927,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect + Write: a '1' sets pin to input; a '0' has no effect 1 @@ -7872,7 +7954,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect + Write: a '1' sets pin to input; a '0' has no effect 1 @@ -7899,7 +7981,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect + Write: a '1' sets pin to input; a '0' has no effect 1 @@ -7926,7 +8008,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect + Write: a '1' sets pin to input; a '0' has no effect 1 @@ -7953,7 +8035,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect + Write: a '1' sets pin to input; a '0' has no effect 1 @@ -7980,7 +8062,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect + Write: a '1' sets pin to input; a '0' has no effect 1 @@ -8007,7 +8089,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect + Write: a '1' sets pin to input; a '0' has no effect 1 @@ -8034,7 +8116,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect + Write: a '1' sets pin to input; a '0' has no effect 1 @@ -8061,7 +8143,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect + Write: a '1' sets pin to input; a '0' has no effect 1 @@ -8088,7 +8170,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect + Write: a '1' sets pin to input; a '0' has no effect 1 @@ -8115,7 +8197,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect + Write: a '1' sets pin to input; a '0' has no effect 1 @@ -8142,7 +8224,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect + Write: a '1' sets pin to input; a '0' has no effect 1 @@ -8169,7 +8251,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect + Write: a '1' sets pin to input; a '0' has no effect 1 @@ -8196,7 +8278,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect + Write: a '1' sets pin to input; a '0' has no effect 1 @@ -8223,7 +8305,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect + Write: a '1' sets pin to input; a '0' has no effect 1 @@ -8250,7 +8332,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect + Write: a '1' sets pin to input; a '0' has no effect 1 @@ -8277,7 +8359,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect + Write: a '1' sets pin to input; a '0' has no effect 1 @@ -8304,7 +8386,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect + Write: a '1' sets pin to input; a '0' has no effect 1 @@ -8331,7 +8413,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect + Write: a '1' sets pin to input; a '0' has no effect 1 @@ -8358,7 +8440,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect + Write: a '1' sets pin to input; a '0' has no effect 1 @@ -8385,7 +8467,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect + Write: a '1' sets pin to input; a '0' has no effect 1 @@ -8978,13 +9060,13 @@ POSSIBILITY OF SUCH DAMAGE.\n DETECTMODE - Select between default DETECT signal behaviour and LDETECT mode + Select between default DETECT signal behavior and LDETECT mode 0x524 read-write DETECTMODE - Select between default DETECT signal behaviour and LDETECT mode + Select between default DETECT signal behavior and LDETECT mode 0 0 @@ -8995,7 +9077,7 @@ POSSIBILITY OF SUCH DAMAGE.\n LDETECT - Use the latched LDETECT behaviour + Use the latched LDETECT behavior 1 @@ -9748,13 +9830,13 @@ POSSIBILITY OF SUCH DAMAGE.\n EVENTS_EDEND - Sampling of energy detection complete. A new ED sample is ready for readout from the RADIO.EDSAMPLE register + Sampling of energy detection complete. A new ED sample is ready for readout from the RADIO.EDSAMPLE register. 0x13C read-write EVENTS_EDEND - Sampling of energy detection complete. A new ED sample is ready for readout from the RADIO.EDSAMPLE register + Sampling of energy detection complete. A new ED sample is ready for readout from the RADIO.EDSAMPLE register. 0 0 @@ -11952,7 +12034,7 @@ POSSIBILITY OF SUCH DAMAGE.\n MAP - Channel map selection. + Channel map selection 8 8 @@ -12120,19 +12202,19 @@ POSSIBILITY OF SUCH DAMAGE.\n LFLEN - Length on air of LENGTH field in number of bits. + Length on air of LENGTH field in number of bits 0 3 S0LEN - Length on air of S0 field in number of bytes. + Length on air of S0 field in number of bytes 8 8 S1LEN - Length on air of S1 field in number of bits. + Length on air of S1 field in number of bits 16 19 @@ -12542,7 +12624,7 @@ POSSIBILITY OF SUCH DAMAGE.\n LEN - CRC length in number of bytes. + CRC length in number of bytes For MODE Ble_LR125Kbit and Ble_LR500Kbit, only LEN set to 3 is supported 0 1 @@ -12630,7 +12712,7 @@ POSSIBILITY OF SUCH DAMAGE.\n TIFS - Interframe spacing in us + Interframe spacing in us. 0 9 @@ -12644,7 +12726,7 @@ POSSIBILITY OF SUCH DAMAGE.\n RSSISAMPLE - RSSI sample + RSSI sample. 0 6 @@ -13020,7 +13102,7 @@ POSSIBILITY OF SUCH DAMAGE.\n Fast - Fast ramp-up (tRXEN,FAST and tTXEN,FAST), see electrical specification for more information + Fast ramp-up (tRXEN,FAST and tTXEN,FAST), see electrical specifications for more information 1 @@ -13256,93 +13338,93 @@ POSSIBILITY OF SUCH DAMAGE.\n 20 - 20 in 8us unit (default) Set to 20 if parsed CTETime is larger han 20 + 20 in 8 us unit (default) Set to 20 if parsed CTETime is larger than 20 0 31 - 31 in 8us unit + 31 in 8 us unit 1 63 - 63 in 8us unit + 63 in 8 us unit 2 CTEINLINERXMODE1US - Spacing between samples for the samples in the SWITCHING period when CTEINLINEMODE is set + Spacing between samples for the samples in the SWITCHING period when CTEINLINEMODE is set. 10 12 4us - 4us + 4 us 1 2us - 2us + 2 us 2 1us - 1us + 1 us 3 500ns - 0.5us + 0.5 us 4 250ns - 0.25us + 0.25 us 5 125ns - 0.125us + 0.125 us 6 CTEINLINERXMODE2US - Spacing between samples for the samples in the SWITCHING period when CTEINLINEMODE is set + Spacing between samples for the samples in the SWITCHING period when CTEINLINEMODE is set. 13 15 4us - 4us + 4 us 1 2us - 2us + 2 us 2 1us - 1us + 1 us 3 500ns - 0.5us + 0.5 us 4 250ns - 0.25us + 0.25 us 5 125ns - 0.125us + 0.125 us 6 @@ -13400,17 +13482,17 @@ POSSIBILITY OF SUCH DAMAGE.\n 4us - 4us + 4 us 1 2us - 2us + 2 us 2 1us - 1us + 1 us 3 @@ -13423,32 +13505,32 @@ POSSIBILITY OF SUCH DAMAGE.\n 4us - 4us + 4 us 1 2us - 2us + 2 us 2 1us - 1us + 1 us 3 500ns - 0.5us + 0.5 us 4 250ns - 0.25us + 0.25 us 5 125ns - 0.125us + 0.125 us 6 @@ -13479,32 +13561,32 @@ POSSIBILITY OF SUCH DAMAGE.\n 4us - 4us + 4 us 1 2us - 2us + 2 us 2 1us - 1us + 1 us 3 500ns - 0.5us + 0.5 us 4 250ns - 0.25us + 0.25 us 5 125ns - 0.125us + 0.125 us 6 @@ -13560,7 +13642,7 @@ POSSIBILITY OF SUCH DAMAGE.\n SWITCHPATTERN - Fill array of GPIO patterns for antenna control + Fill array of GPIO patterns for antenna control. 0 7 @@ -16111,7 +16193,7 @@ POSSIBILITY OF SUCH DAMAGE.\n ERRORSRC - Error source Note : this register is read / write one to clear. + Error source This register is read/write one to clear. 0x480 read-write oneToClear @@ -16459,7 +16541,7 @@ POSSIBILITY OF SUCH DAMAGE.\n Baud1M - 1Mega baud + 1 megabaud 0x10000000 @@ -16914,7 +16996,7 @@ POSSIBILITY OF SUCH DAMAGE.\n TXD - TX data to send. Double buffered + TX data to send. Double buffered. 0 7 @@ -19922,13 +20004,13 @@ POSSIBILITY OF SUCH DAMAGE.\n EVENTS_SUSPENDED - Last byte has been sent out after the SUSPEND task has been issued, TWI traffic is now suspended. + SUSPEND task has been issued, TWI traffic is now suspended. 0x148 read-write EVENTS_SUSPENDED - Last byte has been sent out after the SUSPEND task has been issued, TWI traffic is now suspended. + SUSPEND task has been issued, TWI traffic is now suspended. 0 0 @@ -21904,7 +21986,7 @@ POSSIBILITY OF SUCH DAMAGE.\n MATCH - Which of the addresses in {ADDRESS} matched the incoming address + Indication of which address in {ADDRESS} that matched the incoming address 0 0 @@ -24871,7 +24953,7 @@ POSSIBILITY OF SUCH DAMAGE.\n PRESCALER - 12 bit prescaler for COUNTER frequency (32768/(PRESCALER+1)).Must be written when RTC is stopped + 12 bit prescaler for COUNTER frequency (32768/(PRESCALER+1)). Must be written when RTC is stopped. 0x508 read-write @@ -25072,14 +25154,14 @@ POSSIBILITY OF SUCH DAMAGE.\n A0 - Slope of 1st piece wise linear function + Slope of first piecewise linear function 0x520 read-write 0x00000326 A0 - Slope of 1st piece wise linear function + Slope of first piecewise linear function 0 11 @@ -25087,14 +25169,14 @@ POSSIBILITY OF SUCH DAMAGE.\n A1 - Slope of 2nd piece wise linear function + Slope of second piecewise linear function 0x524 read-write 0x00000348 A1 - Slope of 2nd piece wise linear function + Slope of second piecewise linear function 0 11 @@ -25102,14 +25184,14 @@ POSSIBILITY OF SUCH DAMAGE.\n A2 - Slope of 3rd piece wise linear function + Slope of third piecewise linear function 0x528 read-write 0x000003AA A2 - Slope of 3rd piece wise linear function + Slope of third piecewise linear function 0 11 @@ -25117,14 +25199,14 @@ POSSIBILITY OF SUCH DAMAGE.\n A3 - Slope of 4th piece wise linear function + Slope of fourth piecewise linear function 0x52C read-write 0x0000040E A3 - Slope of 4th piece wise linear function + Slope of fourth piecewise linear function 0 11 @@ -25132,14 +25214,14 @@ POSSIBILITY OF SUCH DAMAGE.\n A4 - Slope of 5th piece wise linear function + Slope of fifth piecewise linear function 0x530 read-write 0x000004BD A4 - Slope of 5th piece wise linear function + Slope of fifth piecewise linear function 0 11 @@ -25147,14 +25229,14 @@ POSSIBILITY OF SUCH DAMAGE.\n A5 - Slope of 6th piece wise linear function + Slope of sixth piecewise linear function 0x534 read-write 0x000005A3 A5 - Slope of 6th piece wise linear function + Slope of sixth piecewise linear function 0 11 @@ -25162,14 +25244,14 @@ POSSIBILITY OF SUCH DAMAGE.\n B0 - y-intercept of 1st piece wise linear function + y-intercept of first piecewise linear function 0x540 read-write 0x00003FEF B0 - y-intercept of 1st piece wise linear function + y-intercept of first piecewise linear function 0 13 @@ -25177,14 +25259,14 @@ POSSIBILITY OF SUCH DAMAGE.\n B1 - y-intercept of 2nd piece wise linear function + y-intercept of second piecewise linear function 0x544 read-write 0x00003FBE B1 - y-intercept of 2nd piece wise linear function + y-intercept of second piecewise linear function 0 13 @@ -25192,14 +25274,14 @@ POSSIBILITY OF SUCH DAMAGE.\n B2 - y-intercept of 3rd piece wise linear function + y-intercept of third piecewise linear function 0x548 read-write 0x00003FBE B2 - y-intercept of 3rd piece wise linear function + y-intercept of third piecewise linear function 0 13 @@ -25207,14 +25289,14 @@ POSSIBILITY OF SUCH DAMAGE.\n B3 - y-intercept of 4th piece wise linear function + y-intercept of fourth piecewise linear function 0x54C read-write 0x00000012 B3 - y-intercept of 4th piece wise linear function + y-intercept of fourth piecewise linear function 0 13 @@ -25222,14 +25304,14 @@ POSSIBILITY OF SUCH DAMAGE.\n B4 - y-intercept of 5th piece wise linear function + y-intercept of fifth piecewise linear function 0x550 read-write 0x00000124 B4 - y-intercept of 5th piece wise linear function + y-intercept of fifth piecewise linear function 0 13 @@ -25237,14 +25319,14 @@ POSSIBILITY OF SUCH DAMAGE.\n B5 - y-intercept of 6th piece wise linear function + y-intercept of sixth piecewise linear function 0x554 read-write 0x0000027C B5 - y-intercept of 6th piece wise linear function + y-intercept of sixth piecewise linear function 0 13 @@ -25252,14 +25334,14 @@ POSSIBILITY OF SUCH DAMAGE.\n T0 - End point of 1st piece wise linear function + End point of first piecewise linear function 0x560 read-write 0x000000E2 T0 - End point of 1st piece wise linear function + End point of first piecewise linear function 0 7 @@ -25267,14 +25349,14 @@ POSSIBILITY OF SUCH DAMAGE.\n T1 - End point of 2nd piece wise linear function + End point of second piecewise linear function 0x564 read-write 0x00000000 T1 - End point of 2nd piece wise linear function + End point of second piecewise linear function 0 7 @@ -25282,14 +25364,14 @@ POSSIBILITY OF SUCH DAMAGE.\n T2 - End point of 3rd piece wise linear function + End point of third piecewise linear function 0x568 read-write 0x00000019 T2 - End point of 3rd piece wise linear function + End point of third piecewise linear function 0 7 @@ -25297,14 +25379,14 @@ POSSIBILITY OF SUCH DAMAGE.\n T3 - End point of 4th piece wise linear function + End point of fourth piecewise linear function 0x56C read-write 0x0000003C T3 - End point of 4th piece wise linear function + End point of fourth piecewise linear function 0 7 @@ -25312,14 +25394,14 @@ POSSIBILITY OF SUCH DAMAGE.\n T4 - End point of 5th piece wise linear function + End point of fifth piecewise linear function 0x570 read-write 0x00000050 T4 - End point of 5th piece wise linear function + End point of fifth piecewise linear function 0 7 @@ -26162,7 +26244,7 @@ POSSIBILITY OF SUCH DAMAGE.\n NIRK - Number of Identity root keys available in the IRK data structure + Number of Identity Root Keys available in the IRK data structure 0 4 @@ -26231,13 +26313,13 @@ POSSIBILITY OF SUCH DAMAGE.\n TASKS_KSGEN - Start generation of key-stream. This operation will stop by itself when completed. + Start generation of keystream. This operation will stop by itself when completed. 0x000 write-only TASKS_KSGEN - Start generation of key-stream. This operation will stop by itself when completed. + Start generation of keystream. This operation will stop by itself when completed. 0 0 @@ -26315,13 +26397,13 @@ POSSIBILITY OF SUCH DAMAGE.\n EVENTS_ENDKSGEN - Key-stream generation complete + Keystream generation complete 0x100 read-write EVENTS_ENDKSGEN - Key-stream generation complete + Keystream generation complete 0 0 @@ -26708,12 +26790,12 @@ POSSIBILITY OF SUCH DAMAGE.\n Default - Default length. Effective length of LENGTH field in encrypted/decrypted packet is 5 bits. A key-stream for packet payloads up to 27 bytes will be generated. + Default length. Effective length of LENGTH field in encrypted/decrypted packet is 5 bits. A keystream for packet payloads up to 27 bytes will be generated. 0 Extended - Extended length. Effective length of LENGTH field in encrypted/decrypted packet is 8 bits. A key-stream for packet payloads up to MAXPACKETSIZE bytes will be generated. + Extended length. Effective length of LENGTH field in encrypted/decrypted packet is 8 bits. A keystream for packet payloads up to MAXPACKETSIZE bytes will be generated. 1 @@ -26770,7 +26852,7 @@ POSSIBILITY OF SUCH DAMAGE.\n SCRATCHPTR - Pointer to a scratch data area used for temporary storage during key-stream generation, + Pointer to a scratch data area used for temporary storage during keystream generation, MIC generation and encryption/decryption. 0 31 @@ -26779,14 +26861,14 @@ POSSIBILITY OF SUCH DAMAGE.\n MAXPACKETSIZE - Length of key-stream generated when MODE.LENGTH = Extended. + Length of keystream generated when MODE.LENGTH = Extended. 0x518 read-write 0x000000FB MAXPACKETSIZE - Length of key-stream generated when MODE.LENGTH = Extended. This value must be greater or equal to the subsequent packet payload to be encrypted/decrypted. + Length of keystream generated when MODE.LENGTH = Extended. This value must be greater or equal to the subsequent packet payload to be encrypted/decrypted. 0 7 @@ -28207,53 +28289,53 @@ POSSIBILITY OF SUCH DAMAGE.\n REPORTPER - Specifies the number of samples to be accumulated in the ACC register before the REPORTRDY and DBLRDY events can be generated + Specifies the number of samples to be accumulated in the ACC register before the REPORTRDY and DBLRDY events can be generated. 0 3 10Smpl - 10 samples / report + 10 samples/report 0 40Smpl - 40 samples / report + 40 samples/report 1 80Smpl - 80 samples / report + 80 samples/report 2 120Smpl - 120 samples / report + 120 samples/report 3 160Smpl - 160 samples / report + 160 samples/report 4 200Smpl - 200 samples / report + 200 samples/report 5 240Smpl - 240 samples / report + 240 samples/report 6 280Smpl - 280 samples / report + 280 samples/report 7 1Smpl - 1 sample / report + 1 sample/report 8 @@ -28269,7 +28351,7 @@ POSSIBILITY OF SUCH DAMAGE.\n ACC - Register accumulating all valid samples (not double transition) read from the SAMPLE register + Register accumulating all valid samples (not double transition) read from the SAMPLE register. 0 31 @@ -31684,7 +31766,7 @@ POSSIBILITY OF SUCH DAMAGE.\n CH0 - Channel 0 enable set register. Writing '0' has no effect + Channel 0 enable set register. Writing '0' has no effect. 0 0 @@ -31711,7 +31793,7 @@ POSSIBILITY OF SUCH DAMAGE.\n CH1 - Channel 1 enable set register. Writing '0' has no effect + Channel 1 enable set register. Writing '0' has no effect. 1 1 @@ -31738,7 +31820,7 @@ POSSIBILITY OF SUCH DAMAGE.\n CH2 - Channel 2 enable set register. Writing '0' has no effect + Channel 2 enable set register. Writing '0' has no effect. 2 2 @@ -31765,7 +31847,7 @@ POSSIBILITY OF SUCH DAMAGE.\n CH3 - Channel 3 enable set register. Writing '0' has no effect + Channel 3 enable set register. Writing '0' has no effect. 3 3 @@ -31792,7 +31874,7 @@ POSSIBILITY OF SUCH DAMAGE.\n CH4 - Channel 4 enable set register. Writing '0' has no effect + Channel 4 enable set register. Writing '0' has no effect. 4 4 @@ -31819,7 +31901,7 @@ POSSIBILITY OF SUCH DAMAGE.\n CH5 - Channel 5 enable set register. Writing '0' has no effect + Channel 5 enable set register. Writing '0' has no effect. 5 5 @@ -31846,7 +31928,7 @@ POSSIBILITY OF SUCH DAMAGE.\n CH6 - Channel 6 enable set register. Writing '0' has no effect + Channel 6 enable set register. Writing '0' has no effect. 6 6 @@ -31873,7 +31955,7 @@ POSSIBILITY OF SUCH DAMAGE.\n CH7 - Channel 7 enable set register. Writing '0' has no effect + Channel 7 enable set register. Writing '0' has no effect. 7 7 @@ -31900,7 +31982,7 @@ POSSIBILITY OF SUCH DAMAGE.\n CH8 - Channel 8 enable set register. Writing '0' has no effect + Channel 8 enable set register. Writing '0' has no effect. 8 8 @@ -31927,7 +32009,7 @@ POSSIBILITY OF SUCH DAMAGE.\n CH9 - Channel 9 enable set register. Writing '0' has no effect + Channel 9 enable set register. Writing '0' has no effect. 9 9 @@ -31954,7 +32036,7 @@ POSSIBILITY OF SUCH DAMAGE.\n CH10 - Channel 10 enable set register. Writing '0' has no effect + Channel 10 enable set register. Writing '0' has no effect. 10 10 @@ -31981,7 +32063,7 @@ POSSIBILITY OF SUCH DAMAGE.\n CH11 - Channel 11 enable set register. Writing '0' has no effect + Channel 11 enable set register. Writing '0' has no effect. 11 11 @@ -32008,7 +32090,7 @@ POSSIBILITY OF SUCH DAMAGE.\n CH12 - Channel 12 enable set register. Writing '0' has no effect + Channel 12 enable set register. Writing '0' has no effect. 12 12 @@ -32035,7 +32117,7 @@ POSSIBILITY OF SUCH DAMAGE.\n CH13 - Channel 13 enable set register. Writing '0' has no effect + Channel 13 enable set register. Writing '0' has no effect. 13 13 @@ -32062,7 +32144,7 @@ POSSIBILITY OF SUCH DAMAGE.\n CH14 - Channel 14 enable set register. Writing '0' has no effect + Channel 14 enable set register. Writing '0' has no effect. 14 14 @@ -32089,7 +32171,7 @@ POSSIBILITY OF SUCH DAMAGE.\n CH15 - Channel 15 enable set register. Writing '0' has no effect + Channel 15 enable set register. Writing '0' has no effect. 15 15 @@ -32116,7 +32198,7 @@ POSSIBILITY OF SUCH DAMAGE.\n CH16 - Channel 16 enable set register. Writing '0' has no effect + Channel 16 enable set register. Writing '0' has no effect. 16 16 @@ -32143,7 +32225,7 @@ POSSIBILITY OF SUCH DAMAGE.\n CH17 - Channel 17 enable set register. Writing '0' has no effect + Channel 17 enable set register. Writing '0' has no effect. 17 17 @@ -32170,7 +32252,7 @@ POSSIBILITY OF SUCH DAMAGE.\n CH18 - Channel 18 enable set register. Writing '0' has no effect + Channel 18 enable set register. Writing '0' has no effect. 18 18 @@ -32197,7 +32279,7 @@ POSSIBILITY OF SUCH DAMAGE.\n CH19 - Channel 19 enable set register. Writing '0' has no effect + Channel 19 enable set register. Writing '0' has no effect. 19 19 @@ -32224,7 +32306,7 @@ POSSIBILITY OF SUCH DAMAGE.\n CH20 - Channel 20 enable set register. Writing '0' has no effect + Channel 20 enable set register. Writing '0' has no effect. 20 20 @@ -32251,7 +32333,7 @@ POSSIBILITY OF SUCH DAMAGE.\n CH21 - Channel 21 enable set register. Writing '0' has no effect + Channel 21 enable set register. Writing '0' has no effect. 21 21 @@ -32278,7 +32360,7 @@ POSSIBILITY OF SUCH DAMAGE.\n CH22 - Channel 22 enable set register. Writing '0' has no effect + Channel 22 enable set register. Writing '0' has no effect. 22 22 @@ -32305,7 +32387,7 @@ POSSIBILITY OF SUCH DAMAGE.\n CH23 - Channel 23 enable set register. Writing '0' has no effect + Channel 23 enable set register. Writing '0' has no effect. 23 23 @@ -32332,7 +32414,7 @@ POSSIBILITY OF SUCH DAMAGE.\n CH24 - Channel 24 enable set register. Writing '0' has no effect + Channel 24 enable set register. Writing '0' has no effect. 24 24 @@ -32359,7 +32441,7 @@ POSSIBILITY OF SUCH DAMAGE.\n CH25 - Channel 25 enable set register. Writing '0' has no effect + Channel 25 enable set register. Writing '0' has no effect. 25 25 @@ -32386,7 +32468,7 @@ POSSIBILITY OF SUCH DAMAGE.\n CH26 - Channel 26 enable set register. Writing '0' has no effect + Channel 26 enable set register. Writing '0' has no effect. 26 26 @@ -32413,7 +32495,7 @@ POSSIBILITY OF SUCH DAMAGE.\n CH27 - Channel 27 enable set register. Writing '0' has no effect + Channel 27 enable set register. Writing '0' has no effect. 27 27 @@ -32440,7 +32522,7 @@ POSSIBILITY OF SUCH DAMAGE.\n CH28 - Channel 28 enable set register. Writing '0' has no effect + Channel 28 enable set register. Writing '0' has no effect. 28 28 @@ -32467,7 +32549,7 @@ POSSIBILITY OF SUCH DAMAGE.\n CH29 - Channel 29 enable set register. Writing '0' has no effect + Channel 29 enable set register. Writing '0' has no effect. 29 29 @@ -32494,7 +32576,7 @@ POSSIBILITY OF SUCH DAMAGE.\n CH30 - Channel 30 enable set register. Writing '0' has no effect + Channel 30 enable set register. Writing '0' has no effect. 30 30 @@ -32521,7 +32603,7 @@ POSSIBILITY OF SUCH DAMAGE.\n CH31 - Channel 31 enable set register. Writing '0' has no effect + Channel 31 enable set register. Writing '0' has no effect. 31 31 @@ -32557,7 +32639,7 @@ POSSIBILITY OF SUCH DAMAGE.\n CH0 - Channel 0 enable clear register. Writing '0' has no effect + Channel 0 enable clear register. Writing '0' has no effect. 0 0 @@ -32584,7 +32666,7 @@ POSSIBILITY OF SUCH DAMAGE.\n CH1 - Channel 1 enable clear register. Writing '0' has no effect + Channel 1 enable clear register. Writing '0' has no effect. 1 1 @@ -32611,7 +32693,7 @@ POSSIBILITY OF SUCH DAMAGE.\n CH2 - Channel 2 enable clear register. Writing '0' has no effect + Channel 2 enable clear register. Writing '0' has no effect. 2 2 @@ -32638,7 +32720,7 @@ POSSIBILITY OF SUCH DAMAGE.\n CH3 - Channel 3 enable clear register. Writing '0' has no effect + Channel 3 enable clear register. Writing '0' has no effect. 3 3 @@ -32665,7 +32747,7 @@ POSSIBILITY OF SUCH DAMAGE.\n CH4 - Channel 4 enable clear register. Writing '0' has no effect + Channel 4 enable clear register. Writing '0' has no effect. 4 4 @@ -32692,7 +32774,7 @@ POSSIBILITY OF SUCH DAMAGE.\n CH5 - Channel 5 enable clear register. Writing '0' has no effect + Channel 5 enable clear register. Writing '0' has no effect. 5 5 @@ -32719,7 +32801,7 @@ POSSIBILITY OF SUCH DAMAGE.\n CH6 - Channel 6 enable clear register. Writing '0' has no effect + Channel 6 enable clear register. Writing '0' has no effect. 6 6 @@ -32746,7 +32828,7 @@ POSSIBILITY OF SUCH DAMAGE.\n CH7 - Channel 7 enable clear register. Writing '0' has no effect + Channel 7 enable clear register. Writing '0' has no effect. 7 7 @@ -32773,7 +32855,7 @@ POSSIBILITY OF SUCH DAMAGE.\n CH8 - Channel 8 enable clear register. Writing '0' has no effect + Channel 8 enable clear register. Writing '0' has no effect. 8 8 @@ -32800,7 +32882,7 @@ POSSIBILITY OF SUCH DAMAGE.\n CH9 - Channel 9 enable clear register. Writing '0' has no effect + Channel 9 enable clear register. Writing '0' has no effect. 9 9 @@ -32827,7 +32909,7 @@ POSSIBILITY OF SUCH DAMAGE.\n CH10 - Channel 10 enable clear register. Writing '0' has no effect + Channel 10 enable clear register. Writing '0' has no effect. 10 10 @@ -32854,7 +32936,7 @@ POSSIBILITY OF SUCH DAMAGE.\n CH11 - Channel 11 enable clear register. Writing '0' has no effect + Channel 11 enable clear register. Writing '0' has no effect. 11 11 @@ -32881,7 +32963,7 @@ POSSIBILITY OF SUCH DAMAGE.\n CH12 - Channel 12 enable clear register. Writing '0' has no effect + Channel 12 enable clear register. Writing '0' has no effect. 12 12 @@ -32908,7 +32990,7 @@ POSSIBILITY OF SUCH DAMAGE.\n CH13 - Channel 13 enable clear register. Writing '0' has no effect + Channel 13 enable clear register. Writing '0' has no effect. 13 13 @@ -32935,7 +33017,7 @@ POSSIBILITY OF SUCH DAMAGE.\n CH14 - Channel 14 enable clear register. Writing '0' has no effect + Channel 14 enable clear register. Writing '0' has no effect. 14 14 @@ -32962,7 +33044,7 @@ POSSIBILITY OF SUCH DAMAGE.\n CH15 - Channel 15 enable clear register. Writing '0' has no effect + Channel 15 enable clear register. Writing '0' has no effect. 15 15 @@ -32989,7 +33071,7 @@ POSSIBILITY OF SUCH DAMAGE.\n CH16 - Channel 16 enable clear register. Writing '0' has no effect + Channel 16 enable clear register. Writing '0' has no effect. 16 16 @@ -33016,7 +33098,7 @@ POSSIBILITY OF SUCH DAMAGE.\n CH17 - Channel 17 enable clear register. Writing '0' has no effect + Channel 17 enable clear register. Writing '0' has no effect. 17 17 @@ -33043,7 +33125,7 @@ POSSIBILITY OF SUCH DAMAGE.\n CH18 - Channel 18 enable clear register. Writing '0' has no effect + Channel 18 enable clear register. Writing '0' has no effect. 18 18 @@ -33070,7 +33152,7 @@ POSSIBILITY OF SUCH DAMAGE.\n CH19 - Channel 19 enable clear register. Writing '0' has no effect + Channel 19 enable clear register. Writing '0' has no effect. 19 19 @@ -33097,7 +33179,7 @@ POSSIBILITY OF SUCH DAMAGE.\n CH20 - Channel 20 enable clear register. Writing '0' has no effect + Channel 20 enable clear register. Writing '0' has no effect. 20 20 @@ -33124,7 +33206,7 @@ POSSIBILITY OF SUCH DAMAGE.\n CH21 - Channel 21 enable clear register. Writing '0' has no effect + Channel 21 enable clear register. Writing '0' has no effect. 21 21 @@ -33151,7 +33233,7 @@ POSSIBILITY OF SUCH DAMAGE.\n CH22 - Channel 22 enable clear register. Writing '0' has no effect + Channel 22 enable clear register. Writing '0' has no effect. 22 22 @@ -33178,7 +33260,7 @@ POSSIBILITY OF SUCH DAMAGE.\n CH23 - Channel 23 enable clear register. Writing '0' has no effect + Channel 23 enable clear register. Writing '0' has no effect. 23 23 @@ -33205,7 +33287,7 @@ POSSIBILITY OF SUCH DAMAGE.\n CH24 - Channel 24 enable clear register. Writing '0' has no effect + Channel 24 enable clear register. Writing '0' has no effect. 24 24 @@ -33232,7 +33314,7 @@ POSSIBILITY OF SUCH DAMAGE.\n CH25 - Channel 25 enable clear register. Writing '0' has no effect + Channel 25 enable clear register. Writing '0' has no effect. 25 25 @@ -33259,7 +33341,7 @@ POSSIBILITY OF SUCH DAMAGE.\n CH26 - Channel 26 enable clear register. Writing '0' has no effect + Channel 26 enable clear register. Writing '0' has no effect. 26 26 @@ -33286,7 +33368,7 @@ POSSIBILITY OF SUCH DAMAGE.\n CH27 - Channel 27 enable clear register. Writing '0' has no effect + Channel 27 enable clear register. Writing '0' has no effect. 27 27 @@ -33313,7 +33395,7 @@ POSSIBILITY OF SUCH DAMAGE.\n CH28 - Channel 28 enable clear register. Writing '0' has no effect + Channel 28 enable clear register. Writing '0' has no effect. 28 28 @@ -33340,7 +33422,7 @@ POSSIBILITY OF SUCH DAMAGE.\n CH29 - Channel 29 enable clear register. Writing '0' has no effect + Channel 29 enable clear register. Writing '0' has no effect. 29 29 @@ -33367,7 +33449,7 @@ POSSIBILITY OF SUCH DAMAGE.\n CH30 - Channel 30 enable clear register. Writing '0' has no effect + Channel 30 enable clear register. Writing '0' has no effect. 30 30 @@ -33394,7 +33476,7 @@ POSSIBILITY OF SUCH DAMAGE.\n CH31 - Channel 31 enable clear register. Writing '0' has no effect + Channel 31 enable clear register. Writing '0' has no effect. 31 31 @@ -33431,7 +33513,7 @@ POSSIBILITY OF SUCH DAMAGE.\n 0x510 EEP - Description cluster: Channel n event end-point + Description cluster: Channel n event endpoint 0x000 read-write @@ -33445,7 +33527,7 @@ POSSIBILITY OF SUCH DAMAGE.\n TEP - Description cluster: Channel n task end-point + Description cluster: Channel n task endpoint 0x004 read-write @@ -34054,7 +34136,7 @@ POSSIBILITY OF SUCH DAMAGE.\n 0x910 TEP - Description cluster: Channel n task end-point + Description cluster: Channel n task endpoint 0x000 read-write @@ -38103,7 +38185,7 @@ POSSIBILITY OF SUCH DAMAGE.\n OneDir - Full buffer dedicated to either iso IN or OUT + Full buffer dedicated to either ISO IN or OUT 0x0000 diff --git a/mdk/nrf52820_bitfields.h b/mdk/nrf52820_bitfields.h index 9616bffa9e..3c0d24d3e0 100644 --- a/mdk/nrf52820_bitfields.h +++ b/mdk/nrf52820_bitfields.h @@ -1,6 +1,8 @@ /* -Copyright (c) 2010 - 2020, Nordic Semiconductor ASA All rights reserved. +Copyright (c) 2010 - 2021, Nordic Semiconductor ASA All rights reserved. + +SPDX-License-Identifier: BSD-3-Clause Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: @@ -148,7 +150,7 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: AAR_NIRK */ /* Description: Number of IRKs */ -/* Bits 4..0 : Number of Identity root keys available in the IRK data structure */ +/* Bits 4..0 : Number of Identity Root Keys available in the IRK data structure */ #define AAR_NIRK_NIRK_Pos (0UL) /*!< Position of NIRK field. */ #define AAR_NIRK_NIRK_Msk (0x1FUL << AAR_NIRK_NIRK_Pos) /*!< Bit mask of NIRK field. */ @@ -207,13 +209,33 @@ POSSIBILITY OF SUCH DAMAGE. #define ACL_ACL_PERM_WRITE_Disable (1UL) /*!< Block write and erase instructions to region n */ +/* Peripheral: APPROTECT */ +/* Description: Access Port Protection */ + +/* Register: APPROTECT_FORCEPROTECT */ +/* Description: Software force enable APPROTECT mechanism until next reset. */ + +/* Bits 7..0 : Write 0x0 to force enable APPROTECT mechanism */ +#define APPROTECT_FORCEPROTECT_FORCEPROTECT_Pos (0UL) /*!< Position of FORCEPROTECT field. */ +#define APPROTECT_FORCEPROTECT_FORCEPROTECT_Msk (0xFFUL << APPROTECT_FORCEPROTECT_FORCEPROTECT_Pos) /*!< Bit mask of FORCEPROTECT field. */ +#define APPROTECT_FORCEPROTECT_FORCEPROTECT_Force (0x0UL) /*!< Software force enable APPROTECT mechanism */ + +/* Register: APPROTECT_DISABLE */ +/* Description: Software disable APPROTECT mechanism */ + +/* Bits 7..0 : Software disable APPROTECT mechanism */ +#define APPROTECT_DISABLE_DISABLE_Pos (0UL) /*!< Position of DISABLE field. */ +#define APPROTECT_DISABLE_DISABLE_Msk (0xFFUL << APPROTECT_DISABLE_DISABLE_Pos) /*!< Bit mask of DISABLE field. */ +#define APPROTECT_DISABLE_DISABLE_SwDisable (0x5AUL) /*!< Software disable APPROTECT mechanism */ + + /* Peripheral: CCM */ /* Description: AES CCM Mode Encryption */ /* Register: CCM_TASKS_KSGEN */ -/* Description: Start generation of key-stream. This operation will stop by itself when completed. */ +/* Description: Start generation of keystream. This operation will stop by itself when completed. */ -/* Bit 0 : Start generation of key-stream. This operation will stop by itself when completed. */ +/* Bit 0 : Start generation of keystream. This operation will stop by itself when completed. */ #define CCM_TASKS_KSGEN_TASKS_KSGEN_Pos (0UL) /*!< Position of TASKS_KSGEN field. */ #define CCM_TASKS_KSGEN_TASKS_KSGEN_Msk (0x1UL << CCM_TASKS_KSGEN_TASKS_KSGEN_Pos) /*!< Bit mask of TASKS_KSGEN field. */ #define CCM_TASKS_KSGEN_TASKS_KSGEN_Trigger (1UL) /*!< Trigger task */ @@ -243,9 +265,9 @@ POSSIBILITY OF SUCH DAMAGE. #define CCM_TASKS_RATEOVERRIDE_TASKS_RATEOVERRIDE_Trigger (1UL) /*!< Trigger task */ /* Register: CCM_EVENTS_ENDKSGEN */ -/* Description: Key-stream generation complete */ +/* Description: Keystream generation complete */ -/* Bit 0 : Key-stream generation complete */ +/* Bit 0 : Keystream generation complete */ #define CCM_EVENTS_ENDKSGEN_EVENTS_ENDKSGEN_Pos (0UL) /*!< Position of EVENTS_ENDKSGEN field. */ #define CCM_EVENTS_ENDKSGEN_EVENTS_ENDKSGEN_Msk (0x1UL << CCM_EVENTS_ENDKSGEN_EVENTS_ENDKSGEN_Pos) /*!< Bit mask of EVENTS_ENDKSGEN field. */ #define CCM_EVENTS_ENDKSGEN_EVENTS_ENDKSGEN_NotGenerated (0UL) /*!< Event not generated */ @@ -350,8 +372,8 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 24 : Packet length configuration */ #define CCM_MODE_LENGTH_Pos (24UL) /*!< Position of LENGTH field. */ #define CCM_MODE_LENGTH_Msk (0x1UL << CCM_MODE_LENGTH_Pos) /*!< Bit mask of LENGTH field. */ -#define CCM_MODE_LENGTH_Default (0UL) /*!< Default length. Effective length of LENGTH field in encrypted/decrypted packet is 5 bits. A key-stream for packet payloads up to 27 bytes will be generated. */ -#define CCM_MODE_LENGTH_Extended (1UL) /*!< Extended length. Effective length of LENGTH field in encrypted/decrypted packet is 8 bits. A key-stream for packet payloads up to MAXPACKETSIZE bytes will be generated. */ +#define CCM_MODE_LENGTH_Default (0UL) /*!< Default length. Effective length of LENGTH field in encrypted/decrypted packet is 5 bits. A keystream for packet payloads up to 27 bytes will be generated. */ +#define CCM_MODE_LENGTH_Extended (1UL) /*!< Extended length. Effective length of LENGTH field in encrypted/decrypted packet is 8 bits. A keystream for packet payloads up to MAXPACKETSIZE bytes will be generated. */ /* Bits 17..16 : Radio data rate that the CCM shall run synchronous with */ #define CCM_MODE_DATARATE_Pos (16UL) /*!< Position of DATARATE field. */ @@ -391,15 +413,15 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: CCM_SCRATCHPTR */ /* Description: Pointer to data area used for temporary storage */ -/* Bits 31..0 : Pointer to a scratch data area used for temporary storage during key-stream generation, +/* Bits 31..0 : Pointer to a scratch data area used for temporary storage during keystream generation, MIC generation and encryption/decryption. */ #define CCM_SCRATCHPTR_SCRATCHPTR_Pos (0UL) /*!< Position of SCRATCHPTR field. */ #define CCM_SCRATCHPTR_SCRATCHPTR_Msk (0xFFFFFFFFUL << CCM_SCRATCHPTR_SCRATCHPTR_Pos) /*!< Bit mask of SCRATCHPTR field. */ /* Register: CCM_MAXPACKETSIZE */ -/* Description: Length of key-stream generated when MODE.LENGTH = Extended. */ +/* Description: Length of keystream generated when MODE.LENGTH = Extended. */ -/* Bits 7..0 : Length of key-stream generated when MODE.LENGTH = Extended. This value must be greater or equal to the subsequent packet payload to be encrypted/decrypted. */ +/* Bits 7..0 : Length of keystream generated when MODE.LENGTH = Extended. This value must be greater or equal to the subsequent packet payload to be encrypted/decrypted. */ #define CCM_MAXPACKETSIZE_MAXPACKETSIZE_Pos (0UL) /*!< Position of MAXPACKETSIZE field. */ #define CCM_MAXPACKETSIZE_MAXPACKETSIZE_Msk (0xFFUL << CCM_MAXPACKETSIZE_MAXPACKETSIZE_Pos) /*!< Bit mask of MAXPACKETSIZE field. */ @@ -1501,6 +1523,9 @@ POSSIBILITY OF SUCH DAMAGE. #define FICR_INFO_VARIANT_VARIANT_Pos (0UL) /*!< Position of VARIANT field. */ #define FICR_INFO_VARIANT_VARIANT_Msk (0xFFFFFFFFUL << FICR_INFO_VARIANT_VARIANT_Pos) /*!< Bit mask of VARIANT field. */ #define FICR_INFO_VARIANT_VARIANT_AAAA (0x41414141UL) /*!< AAAA */ +#define FICR_INFO_VARIANT_VARIANT_AABC (0x41414243UL) /*!< AABC */ +#define FICR_INFO_VARIANT_VARIANT_AAC0 (0x41414330UL) /*!< AAC0 */ +#define FICR_INFO_VARIANT_VARIANT_AAC1 (0x41414331UL) /*!< AAC1 */ #define FICR_INFO_VARIANT_VARIANT_Unspecified (0xFFFFFFFFUL) /*!< Unspecified */ /* Register: FICR_INFO_PACKAGE */ @@ -1509,7 +1534,7 @@ POSSIBILITY OF SUCH DAMAGE. /* Bits 31..0 : Package option */ #define FICR_INFO_PACKAGE_PACKAGE_Pos (0UL) /*!< Position of PACKAGE field. */ #define FICR_INFO_PACKAGE_PACKAGE_Msk (0xFFFFFFFFUL << FICR_INFO_PACKAGE_PACKAGE_Pos) /*!< Bit mask of PACKAGE field. */ -#define FICR_INFO_PACKAGE_PACKAGE_QD (0x2007UL) /*!< QDxx - 40-pin QFN */ +#define FICR_INFO_PACKAGE_PACKAGE_QD (0x2007UL) /*!< QDxx - 5x5 40-pin QFN */ #define FICR_INFO_PACKAGE_PACKAGE_Unspecified (0xFFFFFFFFUL) /*!< Unspecified */ /* Register: FICR_INFO_RAM */ @@ -2164,224 +2189,224 @@ POSSIBILITY OF SUCH DAMAGE. #define GPIO_OUTSET_PIN31_Msk (0x1UL << GPIO_OUTSET_PIN31_Pos) /*!< Bit mask of PIN31 field. */ #define GPIO_OUTSET_PIN31_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTSET_PIN31_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTSET_PIN31_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ +#define GPIO_OUTSET_PIN31_Set (1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */ /* Bit 30 : Pin 30 */ #define GPIO_OUTSET_PIN30_Pos (30UL) /*!< Position of PIN30 field. */ #define GPIO_OUTSET_PIN30_Msk (0x1UL << GPIO_OUTSET_PIN30_Pos) /*!< Bit mask of PIN30 field. */ #define GPIO_OUTSET_PIN30_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTSET_PIN30_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTSET_PIN30_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ +#define GPIO_OUTSET_PIN30_Set (1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */ /* Bit 29 : Pin 29 */ #define GPIO_OUTSET_PIN29_Pos (29UL) /*!< Position of PIN29 field. */ #define GPIO_OUTSET_PIN29_Msk (0x1UL << GPIO_OUTSET_PIN29_Pos) /*!< Bit mask of PIN29 field. */ #define GPIO_OUTSET_PIN29_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTSET_PIN29_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTSET_PIN29_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ +#define GPIO_OUTSET_PIN29_Set (1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */ /* Bit 28 : Pin 28 */ #define GPIO_OUTSET_PIN28_Pos (28UL) /*!< Position of PIN28 field. */ #define GPIO_OUTSET_PIN28_Msk (0x1UL << GPIO_OUTSET_PIN28_Pos) /*!< Bit mask of PIN28 field. */ #define GPIO_OUTSET_PIN28_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTSET_PIN28_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTSET_PIN28_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ +#define GPIO_OUTSET_PIN28_Set (1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */ /* Bit 27 : Pin 27 */ #define GPIO_OUTSET_PIN27_Pos (27UL) /*!< Position of PIN27 field. */ #define GPIO_OUTSET_PIN27_Msk (0x1UL << GPIO_OUTSET_PIN27_Pos) /*!< Bit mask of PIN27 field. */ #define GPIO_OUTSET_PIN27_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTSET_PIN27_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTSET_PIN27_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ +#define GPIO_OUTSET_PIN27_Set (1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */ /* Bit 26 : Pin 26 */ #define GPIO_OUTSET_PIN26_Pos (26UL) /*!< Position of PIN26 field. */ #define GPIO_OUTSET_PIN26_Msk (0x1UL << GPIO_OUTSET_PIN26_Pos) /*!< Bit mask of PIN26 field. */ #define GPIO_OUTSET_PIN26_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTSET_PIN26_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTSET_PIN26_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ +#define GPIO_OUTSET_PIN26_Set (1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */ /* Bit 25 : Pin 25 */ #define GPIO_OUTSET_PIN25_Pos (25UL) /*!< Position of PIN25 field. */ #define GPIO_OUTSET_PIN25_Msk (0x1UL << GPIO_OUTSET_PIN25_Pos) /*!< Bit mask of PIN25 field. */ #define GPIO_OUTSET_PIN25_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTSET_PIN25_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTSET_PIN25_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ +#define GPIO_OUTSET_PIN25_Set (1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */ /* Bit 24 : Pin 24 */ #define GPIO_OUTSET_PIN24_Pos (24UL) /*!< Position of PIN24 field. */ #define GPIO_OUTSET_PIN24_Msk (0x1UL << GPIO_OUTSET_PIN24_Pos) /*!< Bit mask of PIN24 field. */ #define GPIO_OUTSET_PIN24_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTSET_PIN24_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTSET_PIN24_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ +#define GPIO_OUTSET_PIN24_Set (1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */ /* Bit 23 : Pin 23 */ #define GPIO_OUTSET_PIN23_Pos (23UL) /*!< Position of PIN23 field. */ #define GPIO_OUTSET_PIN23_Msk (0x1UL << GPIO_OUTSET_PIN23_Pos) /*!< Bit mask of PIN23 field. */ #define GPIO_OUTSET_PIN23_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTSET_PIN23_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTSET_PIN23_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ +#define GPIO_OUTSET_PIN23_Set (1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */ /* Bit 22 : Pin 22 */ #define GPIO_OUTSET_PIN22_Pos (22UL) /*!< Position of PIN22 field. */ #define GPIO_OUTSET_PIN22_Msk (0x1UL << GPIO_OUTSET_PIN22_Pos) /*!< Bit mask of PIN22 field. */ #define GPIO_OUTSET_PIN22_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTSET_PIN22_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTSET_PIN22_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ +#define GPIO_OUTSET_PIN22_Set (1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */ /* Bit 21 : Pin 21 */ #define GPIO_OUTSET_PIN21_Pos (21UL) /*!< Position of PIN21 field. */ #define GPIO_OUTSET_PIN21_Msk (0x1UL << GPIO_OUTSET_PIN21_Pos) /*!< Bit mask of PIN21 field. */ #define GPIO_OUTSET_PIN21_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTSET_PIN21_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTSET_PIN21_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ +#define GPIO_OUTSET_PIN21_Set (1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */ /* Bit 20 : Pin 20 */ #define GPIO_OUTSET_PIN20_Pos (20UL) /*!< Position of PIN20 field. */ #define GPIO_OUTSET_PIN20_Msk (0x1UL << GPIO_OUTSET_PIN20_Pos) /*!< Bit mask of PIN20 field. */ #define GPIO_OUTSET_PIN20_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTSET_PIN20_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTSET_PIN20_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ +#define GPIO_OUTSET_PIN20_Set (1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */ /* Bit 19 : Pin 19 */ #define GPIO_OUTSET_PIN19_Pos (19UL) /*!< Position of PIN19 field. */ #define GPIO_OUTSET_PIN19_Msk (0x1UL << GPIO_OUTSET_PIN19_Pos) /*!< Bit mask of PIN19 field. */ #define GPIO_OUTSET_PIN19_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTSET_PIN19_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTSET_PIN19_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ +#define GPIO_OUTSET_PIN19_Set (1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */ /* Bit 18 : Pin 18 */ #define GPIO_OUTSET_PIN18_Pos (18UL) /*!< Position of PIN18 field. */ #define GPIO_OUTSET_PIN18_Msk (0x1UL << GPIO_OUTSET_PIN18_Pos) /*!< Bit mask of PIN18 field. */ #define GPIO_OUTSET_PIN18_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTSET_PIN18_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTSET_PIN18_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ +#define GPIO_OUTSET_PIN18_Set (1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */ /* Bit 17 : Pin 17 */ #define GPIO_OUTSET_PIN17_Pos (17UL) /*!< Position of PIN17 field. */ #define GPIO_OUTSET_PIN17_Msk (0x1UL << GPIO_OUTSET_PIN17_Pos) /*!< Bit mask of PIN17 field. */ #define GPIO_OUTSET_PIN17_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTSET_PIN17_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTSET_PIN17_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ +#define GPIO_OUTSET_PIN17_Set (1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */ /* Bit 16 : Pin 16 */ #define GPIO_OUTSET_PIN16_Pos (16UL) /*!< Position of PIN16 field. */ #define GPIO_OUTSET_PIN16_Msk (0x1UL << GPIO_OUTSET_PIN16_Pos) /*!< Bit mask of PIN16 field. */ #define GPIO_OUTSET_PIN16_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTSET_PIN16_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTSET_PIN16_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ +#define GPIO_OUTSET_PIN16_Set (1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */ /* Bit 15 : Pin 15 */ #define GPIO_OUTSET_PIN15_Pos (15UL) /*!< Position of PIN15 field. */ #define GPIO_OUTSET_PIN15_Msk (0x1UL << GPIO_OUTSET_PIN15_Pos) /*!< Bit mask of PIN15 field. */ #define GPIO_OUTSET_PIN15_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTSET_PIN15_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTSET_PIN15_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ +#define GPIO_OUTSET_PIN15_Set (1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */ /* Bit 14 : Pin 14 */ #define GPIO_OUTSET_PIN14_Pos (14UL) /*!< Position of PIN14 field. */ #define GPIO_OUTSET_PIN14_Msk (0x1UL << GPIO_OUTSET_PIN14_Pos) /*!< Bit mask of PIN14 field. */ #define GPIO_OUTSET_PIN14_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTSET_PIN14_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTSET_PIN14_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ +#define GPIO_OUTSET_PIN14_Set (1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */ /* Bit 13 : Pin 13 */ #define GPIO_OUTSET_PIN13_Pos (13UL) /*!< Position of PIN13 field. */ #define GPIO_OUTSET_PIN13_Msk (0x1UL << GPIO_OUTSET_PIN13_Pos) /*!< Bit mask of PIN13 field. */ #define GPIO_OUTSET_PIN13_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTSET_PIN13_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTSET_PIN13_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ +#define GPIO_OUTSET_PIN13_Set (1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */ /* Bit 12 : Pin 12 */ #define GPIO_OUTSET_PIN12_Pos (12UL) /*!< Position of PIN12 field. */ #define GPIO_OUTSET_PIN12_Msk (0x1UL << GPIO_OUTSET_PIN12_Pos) /*!< Bit mask of PIN12 field. */ #define GPIO_OUTSET_PIN12_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTSET_PIN12_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTSET_PIN12_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ +#define GPIO_OUTSET_PIN12_Set (1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */ /* Bit 11 : Pin 11 */ #define GPIO_OUTSET_PIN11_Pos (11UL) /*!< Position of PIN11 field. */ #define GPIO_OUTSET_PIN11_Msk (0x1UL << GPIO_OUTSET_PIN11_Pos) /*!< Bit mask of PIN11 field. */ #define GPIO_OUTSET_PIN11_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTSET_PIN11_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTSET_PIN11_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ +#define GPIO_OUTSET_PIN11_Set (1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */ /* Bit 10 : Pin 10 */ #define GPIO_OUTSET_PIN10_Pos (10UL) /*!< Position of PIN10 field. */ #define GPIO_OUTSET_PIN10_Msk (0x1UL << GPIO_OUTSET_PIN10_Pos) /*!< Bit mask of PIN10 field. */ #define GPIO_OUTSET_PIN10_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTSET_PIN10_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTSET_PIN10_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ +#define GPIO_OUTSET_PIN10_Set (1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */ /* Bit 9 : Pin 9 */ #define GPIO_OUTSET_PIN9_Pos (9UL) /*!< Position of PIN9 field. */ #define GPIO_OUTSET_PIN9_Msk (0x1UL << GPIO_OUTSET_PIN9_Pos) /*!< Bit mask of PIN9 field. */ #define GPIO_OUTSET_PIN9_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTSET_PIN9_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTSET_PIN9_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ +#define GPIO_OUTSET_PIN9_Set (1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */ /* Bit 8 : Pin 8 */ #define GPIO_OUTSET_PIN8_Pos (8UL) /*!< Position of PIN8 field. */ #define GPIO_OUTSET_PIN8_Msk (0x1UL << GPIO_OUTSET_PIN8_Pos) /*!< Bit mask of PIN8 field. */ #define GPIO_OUTSET_PIN8_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTSET_PIN8_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTSET_PIN8_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ +#define GPIO_OUTSET_PIN8_Set (1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */ /* Bit 7 : Pin 7 */ #define GPIO_OUTSET_PIN7_Pos (7UL) /*!< Position of PIN7 field. */ #define GPIO_OUTSET_PIN7_Msk (0x1UL << GPIO_OUTSET_PIN7_Pos) /*!< Bit mask of PIN7 field. */ #define GPIO_OUTSET_PIN7_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTSET_PIN7_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTSET_PIN7_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ +#define GPIO_OUTSET_PIN7_Set (1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */ /* Bit 6 : Pin 6 */ #define GPIO_OUTSET_PIN6_Pos (6UL) /*!< Position of PIN6 field. */ #define GPIO_OUTSET_PIN6_Msk (0x1UL << GPIO_OUTSET_PIN6_Pos) /*!< Bit mask of PIN6 field. */ #define GPIO_OUTSET_PIN6_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTSET_PIN6_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTSET_PIN6_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ +#define GPIO_OUTSET_PIN6_Set (1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */ /* Bit 5 : Pin 5 */ #define GPIO_OUTSET_PIN5_Pos (5UL) /*!< Position of PIN5 field. */ #define GPIO_OUTSET_PIN5_Msk (0x1UL << GPIO_OUTSET_PIN5_Pos) /*!< Bit mask of PIN5 field. */ #define GPIO_OUTSET_PIN5_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTSET_PIN5_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTSET_PIN5_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ +#define GPIO_OUTSET_PIN5_Set (1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */ /* Bit 4 : Pin 4 */ #define GPIO_OUTSET_PIN4_Pos (4UL) /*!< Position of PIN4 field. */ #define GPIO_OUTSET_PIN4_Msk (0x1UL << GPIO_OUTSET_PIN4_Pos) /*!< Bit mask of PIN4 field. */ #define GPIO_OUTSET_PIN4_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTSET_PIN4_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTSET_PIN4_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ +#define GPIO_OUTSET_PIN4_Set (1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */ /* Bit 3 : Pin 3 */ #define GPIO_OUTSET_PIN3_Pos (3UL) /*!< Position of PIN3 field. */ #define GPIO_OUTSET_PIN3_Msk (0x1UL << GPIO_OUTSET_PIN3_Pos) /*!< Bit mask of PIN3 field. */ #define GPIO_OUTSET_PIN3_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTSET_PIN3_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTSET_PIN3_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ +#define GPIO_OUTSET_PIN3_Set (1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */ /* Bit 2 : Pin 2 */ #define GPIO_OUTSET_PIN2_Pos (2UL) /*!< Position of PIN2 field. */ #define GPIO_OUTSET_PIN2_Msk (0x1UL << GPIO_OUTSET_PIN2_Pos) /*!< Bit mask of PIN2 field. */ #define GPIO_OUTSET_PIN2_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTSET_PIN2_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTSET_PIN2_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ +#define GPIO_OUTSET_PIN2_Set (1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */ /* Bit 1 : Pin 1 */ #define GPIO_OUTSET_PIN1_Pos (1UL) /*!< Position of PIN1 field. */ #define GPIO_OUTSET_PIN1_Msk (0x1UL << GPIO_OUTSET_PIN1_Pos) /*!< Bit mask of PIN1 field. */ #define GPIO_OUTSET_PIN1_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTSET_PIN1_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTSET_PIN1_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ +#define GPIO_OUTSET_PIN1_Set (1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */ /* Bit 0 : Pin 0 */ #define GPIO_OUTSET_PIN0_Pos (0UL) /*!< Position of PIN0 field. */ #define GPIO_OUTSET_PIN0_Msk (0x1UL << GPIO_OUTSET_PIN0_Pos) /*!< Bit mask of PIN0 field. */ #define GPIO_OUTSET_PIN0_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTSET_PIN0_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTSET_PIN0_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ +#define GPIO_OUTSET_PIN0_Set (1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */ /* Register: GPIO_OUTCLR */ /* Description: Clear individual bits in GPIO port */ @@ -2391,224 +2416,224 @@ POSSIBILITY OF SUCH DAMAGE. #define GPIO_OUTCLR_PIN31_Msk (0x1UL << GPIO_OUTCLR_PIN31_Pos) /*!< Bit mask of PIN31 field. */ #define GPIO_OUTCLR_PIN31_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTCLR_PIN31_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTCLR_PIN31_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ +#define GPIO_OUTCLR_PIN31_Clear (1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */ /* Bit 30 : Pin 30 */ #define GPIO_OUTCLR_PIN30_Pos (30UL) /*!< Position of PIN30 field. */ #define GPIO_OUTCLR_PIN30_Msk (0x1UL << GPIO_OUTCLR_PIN30_Pos) /*!< Bit mask of PIN30 field. */ #define GPIO_OUTCLR_PIN30_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTCLR_PIN30_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTCLR_PIN30_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ +#define GPIO_OUTCLR_PIN30_Clear (1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */ /* Bit 29 : Pin 29 */ #define GPIO_OUTCLR_PIN29_Pos (29UL) /*!< Position of PIN29 field. */ #define GPIO_OUTCLR_PIN29_Msk (0x1UL << GPIO_OUTCLR_PIN29_Pos) /*!< Bit mask of PIN29 field. */ #define GPIO_OUTCLR_PIN29_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTCLR_PIN29_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTCLR_PIN29_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ +#define GPIO_OUTCLR_PIN29_Clear (1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */ /* Bit 28 : Pin 28 */ #define GPIO_OUTCLR_PIN28_Pos (28UL) /*!< Position of PIN28 field. */ #define GPIO_OUTCLR_PIN28_Msk (0x1UL << GPIO_OUTCLR_PIN28_Pos) /*!< Bit mask of PIN28 field. */ #define GPIO_OUTCLR_PIN28_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTCLR_PIN28_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTCLR_PIN28_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ +#define GPIO_OUTCLR_PIN28_Clear (1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */ /* Bit 27 : Pin 27 */ #define GPIO_OUTCLR_PIN27_Pos (27UL) /*!< Position of PIN27 field. */ #define GPIO_OUTCLR_PIN27_Msk (0x1UL << GPIO_OUTCLR_PIN27_Pos) /*!< Bit mask of PIN27 field. */ #define GPIO_OUTCLR_PIN27_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTCLR_PIN27_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTCLR_PIN27_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ +#define GPIO_OUTCLR_PIN27_Clear (1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */ /* Bit 26 : Pin 26 */ #define GPIO_OUTCLR_PIN26_Pos (26UL) /*!< Position of PIN26 field. */ #define GPIO_OUTCLR_PIN26_Msk (0x1UL << GPIO_OUTCLR_PIN26_Pos) /*!< Bit mask of PIN26 field. */ #define GPIO_OUTCLR_PIN26_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTCLR_PIN26_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTCLR_PIN26_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ +#define GPIO_OUTCLR_PIN26_Clear (1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */ /* Bit 25 : Pin 25 */ #define GPIO_OUTCLR_PIN25_Pos (25UL) /*!< Position of PIN25 field. */ #define GPIO_OUTCLR_PIN25_Msk (0x1UL << GPIO_OUTCLR_PIN25_Pos) /*!< Bit mask of PIN25 field. */ #define GPIO_OUTCLR_PIN25_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTCLR_PIN25_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTCLR_PIN25_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ +#define GPIO_OUTCLR_PIN25_Clear (1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */ /* Bit 24 : Pin 24 */ #define GPIO_OUTCLR_PIN24_Pos (24UL) /*!< Position of PIN24 field. */ #define GPIO_OUTCLR_PIN24_Msk (0x1UL << GPIO_OUTCLR_PIN24_Pos) /*!< Bit mask of PIN24 field. */ #define GPIO_OUTCLR_PIN24_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTCLR_PIN24_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTCLR_PIN24_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ +#define GPIO_OUTCLR_PIN24_Clear (1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */ /* Bit 23 : Pin 23 */ #define GPIO_OUTCLR_PIN23_Pos (23UL) /*!< Position of PIN23 field. */ #define GPIO_OUTCLR_PIN23_Msk (0x1UL << GPIO_OUTCLR_PIN23_Pos) /*!< Bit mask of PIN23 field. */ #define GPIO_OUTCLR_PIN23_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTCLR_PIN23_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTCLR_PIN23_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ +#define GPIO_OUTCLR_PIN23_Clear (1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */ /* Bit 22 : Pin 22 */ #define GPIO_OUTCLR_PIN22_Pos (22UL) /*!< Position of PIN22 field. */ #define GPIO_OUTCLR_PIN22_Msk (0x1UL << GPIO_OUTCLR_PIN22_Pos) /*!< Bit mask of PIN22 field. */ #define GPIO_OUTCLR_PIN22_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTCLR_PIN22_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTCLR_PIN22_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ +#define GPIO_OUTCLR_PIN22_Clear (1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */ /* Bit 21 : Pin 21 */ #define GPIO_OUTCLR_PIN21_Pos (21UL) /*!< Position of PIN21 field. */ #define GPIO_OUTCLR_PIN21_Msk (0x1UL << GPIO_OUTCLR_PIN21_Pos) /*!< Bit mask of PIN21 field. */ #define GPIO_OUTCLR_PIN21_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTCLR_PIN21_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTCLR_PIN21_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ +#define GPIO_OUTCLR_PIN21_Clear (1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */ /* Bit 20 : Pin 20 */ #define GPIO_OUTCLR_PIN20_Pos (20UL) /*!< Position of PIN20 field. */ #define GPIO_OUTCLR_PIN20_Msk (0x1UL << GPIO_OUTCLR_PIN20_Pos) /*!< Bit mask of PIN20 field. */ #define GPIO_OUTCLR_PIN20_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTCLR_PIN20_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTCLR_PIN20_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ +#define GPIO_OUTCLR_PIN20_Clear (1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */ /* Bit 19 : Pin 19 */ #define GPIO_OUTCLR_PIN19_Pos (19UL) /*!< Position of PIN19 field. */ #define GPIO_OUTCLR_PIN19_Msk (0x1UL << GPIO_OUTCLR_PIN19_Pos) /*!< Bit mask of PIN19 field. */ #define GPIO_OUTCLR_PIN19_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTCLR_PIN19_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTCLR_PIN19_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ +#define GPIO_OUTCLR_PIN19_Clear (1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */ /* Bit 18 : Pin 18 */ #define GPIO_OUTCLR_PIN18_Pos (18UL) /*!< Position of PIN18 field. */ #define GPIO_OUTCLR_PIN18_Msk (0x1UL << GPIO_OUTCLR_PIN18_Pos) /*!< Bit mask of PIN18 field. */ #define GPIO_OUTCLR_PIN18_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTCLR_PIN18_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTCLR_PIN18_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ +#define GPIO_OUTCLR_PIN18_Clear (1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */ /* Bit 17 : Pin 17 */ #define GPIO_OUTCLR_PIN17_Pos (17UL) /*!< Position of PIN17 field. */ #define GPIO_OUTCLR_PIN17_Msk (0x1UL << GPIO_OUTCLR_PIN17_Pos) /*!< Bit mask of PIN17 field. */ #define GPIO_OUTCLR_PIN17_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTCLR_PIN17_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTCLR_PIN17_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ +#define GPIO_OUTCLR_PIN17_Clear (1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */ /* Bit 16 : Pin 16 */ #define GPIO_OUTCLR_PIN16_Pos (16UL) /*!< Position of PIN16 field. */ #define GPIO_OUTCLR_PIN16_Msk (0x1UL << GPIO_OUTCLR_PIN16_Pos) /*!< Bit mask of PIN16 field. */ #define GPIO_OUTCLR_PIN16_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTCLR_PIN16_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTCLR_PIN16_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ +#define GPIO_OUTCLR_PIN16_Clear (1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */ /* Bit 15 : Pin 15 */ #define GPIO_OUTCLR_PIN15_Pos (15UL) /*!< Position of PIN15 field. */ #define GPIO_OUTCLR_PIN15_Msk (0x1UL << GPIO_OUTCLR_PIN15_Pos) /*!< Bit mask of PIN15 field. */ #define GPIO_OUTCLR_PIN15_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTCLR_PIN15_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTCLR_PIN15_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ +#define GPIO_OUTCLR_PIN15_Clear (1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */ /* Bit 14 : Pin 14 */ #define GPIO_OUTCLR_PIN14_Pos (14UL) /*!< Position of PIN14 field. */ #define GPIO_OUTCLR_PIN14_Msk (0x1UL << GPIO_OUTCLR_PIN14_Pos) /*!< Bit mask of PIN14 field. */ #define GPIO_OUTCLR_PIN14_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTCLR_PIN14_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTCLR_PIN14_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ +#define GPIO_OUTCLR_PIN14_Clear (1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */ /* Bit 13 : Pin 13 */ #define GPIO_OUTCLR_PIN13_Pos (13UL) /*!< Position of PIN13 field. */ #define GPIO_OUTCLR_PIN13_Msk (0x1UL << GPIO_OUTCLR_PIN13_Pos) /*!< Bit mask of PIN13 field. */ #define GPIO_OUTCLR_PIN13_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTCLR_PIN13_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTCLR_PIN13_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ +#define GPIO_OUTCLR_PIN13_Clear (1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */ /* Bit 12 : Pin 12 */ #define GPIO_OUTCLR_PIN12_Pos (12UL) /*!< Position of PIN12 field. */ #define GPIO_OUTCLR_PIN12_Msk (0x1UL << GPIO_OUTCLR_PIN12_Pos) /*!< Bit mask of PIN12 field. */ #define GPIO_OUTCLR_PIN12_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTCLR_PIN12_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTCLR_PIN12_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ +#define GPIO_OUTCLR_PIN12_Clear (1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */ /* Bit 11 : Pin 11 */ #define GPIO_OUTCLR_PIN11_Pos (11UL) /*!< Position of PIN11 field. */ #define GPIO_OUTCLR_PIN11_Msk (0x1UL << GPIO_OUTCLR_PIN11_Pos) /*!< Bit mask of PIN11 field. */ #define GPIO_OUTCLR_PIN11_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTCLR_PIN11_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTCLR_PIN11_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ +#define GPIO_OUTCLR_PIN11_Clear (1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */ /* Bit 10 : Pin 10 */ #define GPIO_OUTCLR_PIN10_Pos (10UL) /*!< Position of PIN10 field. */ #define GPIO_OUTCLR_PIN10_Msk (0x1UL << GPIO_OUTCLR_PIN10_Pos) /*!< Bit mask of PIN10 field. */ #define GPIO_OUTCLR_PIN10_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTCLR_PIN10_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTCLR_PIN10_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ +#define GPIO_OUTCLR_PIN10_Clear (1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */ /* Bit 9 : Pin 9 */ #define GPIO_OUTCLR_PIN9_Pos (9UL) /*!< Position of PIN9 field. */ #define GPIO_OUTCLR_PIN9_Msk (0x1UL << GPIO_OUTCLR_PIN9_Pos) /*!< Bit mask of PIN9 field. */ #define GPIO_OUTCLR_PIN9_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTCLR_PIN9_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTCLR_PIN9_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ +#define GPIO_OUTCLR_PIN9_Clear (1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */ /* Bit 8 : Pin 8 */ #define GPIO_OUTCLR_PIN8_Pos (8UL) /*!< Position of PIN8 field. */ #define GPIO_OUTCLR_PIN8_Msk (0x1UL << GPIO_OUTCLR_PIN8_Pos) /*!< Bit mask of PIN8 field. */ #define GPIO_OUTCLR_PIN8_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTCLR_PIN8_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTCLR_PIN8_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ +#define GPIO_OUTCLR_PIN8_Clear (1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */ /* Bit 7 : Pin 7 */ #define GPIO_OUTCLR_PIN7_Pos (7UL) /*!< Position of PIN7 field. */ #define GPIO_OUTCLR_PIN7_Msk (0x1UL << GPIO_OUTCLR_PIN7_Pos) /*!< Bit mask of PIN7 field. */ #define GPIO_OUTCLR_PIN7_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTCLR_PIN7_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTCLR_PIN7_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ +#define GPIO_OUTCLR_PIN7_Clear (1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */ /* Bit 6 : Pin 6 */ #define GPIO_OUTCLR_PIN6_Pos (6UL) /*!< Position of PIN6 field. */ #define GPIO_OUTCLR_PIN6_Msk (0x1UL << GPIO_OUTCLR_PIN6_Pos) /*!< Bit mask of PIN6 field. */ #define GPIO_OUTCLR_PIN6_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTCLR_PIN6_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTCLR_PIN6_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ +#define GPIO_OUTCLR_PIN6_Clear (1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */ /* Bit 5 : Pin 5 */ #define GPIO_OUTCLR_PIN5_Pos (5UL) /*!< Position of PIN5 field. */ #define GPIO_OUTCLR_PIN5_Msk (0x1UL << GPIO_OUTCLR_PIN5_Pos) /*!< Bit mask of PIN5 field. */ #define GPIO_OUTCLR_PIN5_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTCLR_PIN5_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTCLR_PIN5_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ +#define GPIO_OUTCLR_PIN5_Clear (1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */ /* Bit 4 : Pin 4 */ #define GPIO_OUTCLR_PIN4_Pos (4UL) /*!< Position of PIN4 field. */ #define GPIO_OUTCLR_PIN4_Msk (0x1UL << GPIO_OUTCLR_PIN4_Pos) /*!< Bit mask of PIN4 field. */ #define GPIO_OUTCLR_PIN4_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTCLR_PIN4_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTCLR_PIN4_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ +#define GPIO_OUTCLR_PIN4_Clear (1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */ /* Bit 3 : Pin 3 */ #define GPIO_OUTCLR_PIN3_Pos (3UL) /*!< Position of PIN3 field. */ #define GPIO_OUTCLR_PIN3_Msk (0x1UL << GPIO_OUTCLR_PIN3_Pos) /*!< Bit mask of PIN3 field. */ #define GPIO_OUTCLR_PIN3_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTCLR_PIN3_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTCLR_PIN3_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ +#define GPIO_OUTCLR_PIN3_Clear (1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */ /* Bit 2 : Pin 2 */ #define GPIO_OUTCLR_PIN2_Pos (2UL) /*!< Position of PIN2 field. */ #define GPIO_OUTCLR_PIN2_Msk (0x1UL << GPIO_OUTCLR_PIN2_Pos) /*!< Bit mask of PIN2 field. */ #define GPIO_OUTCLR_PIN2_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTCLR_PIN2_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTCLR_PIN2_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ +#define GPIO_OUTCLR_PIN2_Clear (1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */ /* Bit 1 : Pin 1 */ #define GPIO_OUTCLR_PIN1_Pos (1UL) /*!< Position of PIN1 field. */ #define GPIO_OUTCLR_PIN1_Msk (0x1UL << GPIO_OUTCLR_PIN1_Pos) /*!< Bit mask of PIN1 field. */ #define GPIO_OUTCLR_PIN1_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTCLR_PIN1_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTCLR_PIN1_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ +#define GPIO_OUTCLR_PIN1_Clear (1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */ /* Bit 0 : Pin 0 */ #define GPIO_OUTCLR_PIN0_Pos (0UL) /*!< Position of PIN0 field. */ #define GPIO_OUTCLR_PIN0_Msk (0x1UL << GPIO_OUTCLR_PIN0_Pos) /*!< Bit mask of PIN0 field. */ #define GPIO_OUTCLR_PIN0_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTCLR_PIN0_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTCLR_PIN0_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ +#define GPIO_OUTCLR_PIN0_Clear (1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */ /* Register: GPIO_IN */ /* Description: Read GPIO port */ @@ -3008,224 +3033,224 @@ POSSIBILITY OF SUCH DAMAGE. #define GPIO_DIRSET_PIN31_Msk (0x1UL << GPIO_DIRSET_PIN31_Pos) /*!< Bit mask of PIN31 field. */ #define GPIO_DIRSET_PIN31_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRSET_PIN31_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRSET_PIN31_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ +#define GPIO_DIRSET_PIN31_Set (1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */ /* Bit 30 : Set as output pin 30 */ #define GPIO_DIRSET_PIN30_Pos (30UL) /*!< Position of PIN30 field. */ #define GPIO_DIRSET_PIN30_Msk (0x1UL << GPIO_DIRSET_PIN30_Pos) /*!< Bit mask of PIN30 field. */ #define GPIO_DIRSET_PIN30_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRSET_PIN30_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRSET_PIN30_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ +#define GPIO_DIRSET_PIN30_Set (1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */ /* Bit 29 : Set as output pin 29 */ #define GPIO_DIRSET_PIN29_Pos (29UL) /*!< Position of PIN29 field. */ #define GPIO_DIRSET_PIN29_Msk (0x1UL << GPIO_DIRSET_PIN29_Pos) /*!< Bit mask of PIN29 field. */ #define GPIO_DIRSET_PIN29_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRSET_PIN29_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRSET_PIN29_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ +#define GPIO_DIRSET_PIN29_Set (1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */ /* Bit 28 : Set as output pin 28 */ #define GPIO_DIRSET_PIN28_Pos (28UL) /*!< Position of PIN28 field. */ #define GPIO_DIRSET_PIN28_Msk (0x1UL << GPIO_DIRSET_PIN28_Pos) /*!< Bit mask of PIN28 field. */ #define GPIO_DIRSET_PIN28_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRSET_PIN28_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRSET_PIN28_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ +#define GPIO_DIRSET_PIN28_Set (1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */ /* Bit 27 : Set as output pin 27 */ #define GPIO_DIRSET_PIN27_Pos (27UL) /*!< Position of PIN27 field. */ #define GPIO_DIRSET_PIN27_Msk (0x1UL << GPIO_DIRSET_PIN27_Pos) /*!< Bit mask of PIN27 field. */ #define GPIO_DIRSET_PIN27_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRSET_PIN27_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRSET_PIN27_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ +#define GPIO_DIRSET_PIN27_Set (1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */ /* Bit 26 : Set as output pin 26 */ #define GPIO_DIRSET_PIN26_Pos (26UL) /*!< Position of PIN26 field. */ #define GPIO_DIRSET_PIN26_Msk (0x1UL << GPIO_DIRSET_PIN26_Pos) /*!< Bit mask of PIN26 field. */ #define GPIO_DIRSET_PIN26_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRSET_PIN26_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRSET_PIN26_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ +#define GPIO_DIRSET_PIN26_Set (1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */ /* Bit 25 : Set as output pin 25 */ #define GPIO_DIRSET_PIN25_Pos (25UL) /*!< Position of PIN25 field. */ #define GPIO_DIRSET_PIN25_Msk (0x1UL << GPIO_DIRSET_PIN25_Pos) /*!< Bit mask of PIN25 field. */ #define GPIO_DIRSET_PIN25_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRSET_PIN25_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRSET_PIN25_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ +#define GPIO_DIRSET_PIN25_Set (1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */ /* Bit 24 : Set as output pin 24 */ #define GPIO_DIRSET_PIN24_Pos (24UL) /*!< Position of PIN24 field. */ #define GPIO_DIRSET_PIN24_Msk (0x1UL << GPIO_DIRSET_PIN24_Pos) /*!< Bit mask of PIN24 field. */ #define GPIO_DIRSET_PIN24_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRSET_PIN24_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRSET_PIN24_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ +#define GPIO_DIRSET_PIN24_Set (1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */ /* Bit 23 : Set as output pin 23 */ #define GPIO_DIRSET_PIN23_Pos (23UL) /*!< Position of PIN23 field. */ #define GPIO_DIRSET_PIN23_Msk (0x1UL << GPIO_DIRSET_PIN23_Pos) /*!< Bit mask of PIN23 field. */ #define GPIO_DIRSET_PIN23_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRSET_PIN23_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRSET_PIN23_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ +#define GPIO_DIRSET_PIN23_Set (1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */ /* Bit 22 : Set as output pin 22 */ #define GPIO_DIRSET_PIN22_Pos (22UL) /*!< Position of PIN22 field. */ #define GPIO_DIRSET_PIN22_Msk (0x1UL << GPIO_DIRSET_PIN22_Pos) /*!< Bit mask of PIN22 field. */ #define GPIO_DIRSET_PIN22_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRSET_PIN22_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRSET_PIN22_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ +#define GPIO_DIRSET_PIN22_Set (1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */ /* Bit 21 : Set as output pin 21 */ #define GPIO_DIRSET_PIN21_Pos (21UL) /*!< Position of PIN21 field. */ #define GPIO_DIRSET_PIN21_Msk (0x1UL << GPIO_DIRSET_PIN21_Pos) /*!< Bit mask of PIN21 field. */ #define GPIO_DIRSET_PIN21_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRSET_PIN21_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRSET_PIN21_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ +#define GPIO_DIRSET_PIN21_Set (1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */ /* Bit 20 : Set as output pin 20 */ #define GPIO_DIRSET_PIN20_Pos (20UL) /*!< Position of PIN20 field. */ #define GPIO_DIRSET_PIN20_Msk (0x1UL << GPIO_DIRSET_PIN20_Pos) /*!< Bit mask of PIN20 field. */ #define GPIO_DIRSET_PIN20_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRSET_PIN20_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRSET_PIN20_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ +#define GPIO_DIRSET_PIN20_Set (1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */ /* Bit 19 : Set as output pin 19 */ #define GPIO_DIRSET_PIN19_Pos (19UL) /*!< Position of PIN19 field. */ #define GPIO_DIRSET_PIN19_Msk (0x1UL << GPIO_DIRSET_PIN19_Pos) /*!< Bit mask of PIN19 field. */ #define GPIO_DIRSET_PIN19_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRSET_PIN19_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRSET_PIN19_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ +#define GPIO_DIRSET_PIN19_Set (1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */ /* Bit 18 : Set as output pin 18 */ #define GPIO_DIRSET_PIN18_Pos (18UL) /*!< Position of PIN18 field. */ #define GPIO_DIRSET_PIN18_Msk (0x1UL << GPIO_DIRSET_PIN18_Pos) /*!< Bit mask of PIN18 field. */ #define GPIO_DIRSET_PIN18_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRSET_PIN18_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRSET_PIN18_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ +#define GPIO_DIRSET_PIN18_Set (1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */ /* Bit 17 : Set as output pin 17 */ #define GPIO_DIRSET_PIN17_Pos (17UL) /*!< Position of PIN17 field. */ #define GPIO_DIRSET_PIN17_Msk (0x1UL << GPIO_DIRSET_PIN17_Pos) /*!< Bit mask of PIN17 field. */ #define GPIO_DIRSET_PIN17_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRSET_PIN17_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRSET_PIN17_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ +#define GPIO_DIRSET_PIN17_Set (1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */ /* Bit 16 : Set as output pin 16 */ #define GPIO_DIRSET_PIN16_Pos (16UL) /*!< Position of PIN16 field. */ #define GPIO_DIRSET_PIN16_Msk (0x1UL << GPIO_DIRSET_PIN16_Pos) /*!< Bit mask of PIN16 field. */ #define GPIO_DIRSET_PIN16_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRSET_PIN16_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRSET_PIN16_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ +#define GPIO_DIRSET_PIN16_Set (1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */ /* Bit 15 : Set as output pin 15 */ #define GPIO_DIRSET_PIN15_Pos (15UL) /*!< Position of PIN15 field. */ #define GPIO_DIRSET_PIN15_Msk (0x1UL << GPIO_DIRSET_PIN15_Pos) /*!< Bit mask of PIN15 field. */ #define GPIO_DIRSET_PIN15_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRSET_PIN15_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRSET_PIN15_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ +#define GPIO_DIRSET_PIN15_Set (1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */ /* Bit 14 : Set as output pin 14 */ #define GPIO_DIRSET_PIN14_Pos (14UL) /*!< Position of PIN14 field. */ #define GPIO_DIRSET_PIN14_Msk (0x1UL << GPIO_DIRSET_PIN14_Pos) /*!< Bit mask of PIN14 field. */ #define GPIO_DIRSET_PIN14_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRSET_PIN14_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRSET_PIN14_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ +#define GPIO_DIRSET_PIN14_Set (1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */ /* Bit 13 : Set as output pin 13 */ #define GPIO_DIRSET_PIN13_Pos (13UL) /*!< Position of PIN13 field. */ #define GPIO_DIRSET_PIN13_Msk (0x1UL << GPIO_DIRSET_PIN13_Pos) /*!< Bit mask of PIN13 field. */ #define GPIO_DIRSET_PIN13_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRSET_PIN13_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRSET_PIN13_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ +#define GPIO_DIRSET_PIN13_Set (1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */ /* Bit 12 : Set as output pin 12 */ #define GPIO_DIRSET_PIN12_Pos (12UL) /*!< Position of PIN12 field. */ #define GPIO_DIRSET_PIN12_Msk (0x1UL << GPIO_DIRSET_PIN12_Pos) /*!< Bit mask of PIN12 field. */ #define GPIO_DIRSET_PIN12_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRSET_PIN12_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRSET_PIN12_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ +#define GPIO_DIRSET_PIN12_Set (1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */ /* Bit 11 : Set as output pin 11 */ #define GPIO_DIRSET_PIN11_Pos (11UL) /*!< Position of PIN11 field. */ #define GPIO_DIRSET_PIN11_Msk (0x1UL << GPIO_DIRSET_PIN11_Pos) /*!< Bit mask of PIN11 field. */ #define GPIO_DIRSET_PIN11_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRSET_PIN11_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRSET_PIN11_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ +#define GPIO_DIRSET_PIN11_Set (1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */ /* Bit 10 : Set as output pin 10 */ #define GPIO_DIRSET_PIN10_Pos (10UL) /*!< Position of PIN10 field. */ #define GPIO_DIRSET_PIN10_Msk (0x1UL << GPIO_DIRSET_PIN10_Pos) /*!< Bit mask of PIN10 field. */ #define GPIO_DIRSET_PIN10_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRSET_PIN10_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRSET_PIN10_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ +#define GPIO_DIRSET_PIN10_Set (1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */ /* Bit 9 : Set as output pin 9 */ #define GPIO_DIRSET_PIN9_Pos (9UL) /*!< Position of PIN9 field. */ #define GPIO_DIRSET_PIN9_Msk (0x1UL << GPIO_DIRSET_PIN9_Pos) /*!< Bit mask of PIN9 field. */ #define GPIO_DIRSET_PIN9_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRSET_PIN9_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRSET_PIN9_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ +#define GPIO_DIRSET_PIN9_Set (1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */ /* Bit 8 : Set as output pin 8 */ #define GPIO_DIRSET_PIN8_Pos (8UL) /*!< Position of PIN8 field. */ #define GPIO_DIRSET_PIN8_Msk (0x1UL << GPIO_DIRSET_PIN8_Pos) /*!< Bit mask of PIN8 field. */ #define GPIO_DIRSET_PIN8_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRSET_PIN8_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRSET_PIN8_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ +#define GPIO_DIRSET_PIN8_Set (1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */ /* Bit 7 : Set as output pin 7 */ #define GPIO_DIRSET_PIN7_Pos (7UL) /*!< Position of PIN7 field. */ #define GPIO_DIRSET_PIN7_Msk (0x1UL << GPIO_DIRSET_PIN7_Pos) /*!< Bit mask of PIN7 field. */ #define GPIO_DIRSET_PIN7_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRSET_PIN7_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRSET_PIN7_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ +#define GPIO_DIRSET_PIN7_Set (1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */ /* Bit 6 : Set as output pin 6 */ #define GPIO_DIRSET_PIN6_Pos (6UL) /*!< Position of PIN6 field. */ #define GPIO_DIRSET_PIN6_Msk (0x1UL << GPIO_DIRSET_PIN6_Pos) /*!< Bit mask of PIN6 field. */ #define GPIO_DIRSET_PIN6_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRSET_PIN6_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRSET_PIN6_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ +#define GPIO_DIRSET_PIN6_Set (1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */ /* Bit 5 : Set as output pin 5 */ #define GPIO_DIRSET_PIN5_Pos (5UL) /*!< Position of PIN5 field. */ #define GPIO_DIRSET_PIN5_Msk (0x1UL << GPIO_DIRSET_PIN5_Pos) /*!< Bit mask of PIN5 field. */ #define GPIO_DIRSET_PIN5_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRSET_PIN5_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRSET_PIN5_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ +#define GPIO_DIRSET_PIN5_Set (1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */ /* Bit 4 : Set as output pin 4 */ #define GPIO_DIRSET_PIN4_Pos (4UL) /*!< Position of PIN4 field. */ #define GPIO_DIRSET_PIN4_Msk (0x1UL << GPIO_DIRSET_PIN4_Pos) /*!< Bit mask of PIN4 field. */ #define GPIO_DIRSET_PIN4_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRSET_PIN4_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRSET_PIN4_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ +#define GPIO_DIRSET_PIN4_Set (1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */ /* Bit 3 : Set as output pin 3 */ #define GPIO_DIRSET_PIN3_Pos (3UL) /*!< Position of PIN3 field. */ #define GPIO_DIRSET_PIN3_Msk (0x1UL << GPIO_DIRSET_PIN3_Pos) /*!< Bit mask of PIN3 field. */ #define GPIO_DIRSET_PIN3_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRSET_PIN3_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRSET_PIN3_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ +#define GPIO_DIRSET_PIN3_Set (1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */ /* Bit 2 : Set as output pin 2 */ #define GPIO_DIRSET_PIN2_Pos (2UL) /*!< Position of PIN2 field. */ #define GPIO_DIRSET_PIN2_Msk (0x1UL << GPIO_DIRSET_PIN2_Pos) /*!< Bit mask of PIN2 field. */ #define GPIO_DIRSET_PIN2_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRSET_PIN2_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRSET_PIN2_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ +#define GPIO_DIRSET_PIN2_Set (1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */ /* Bit 1 : Set as output pin 1 */ #define GPIO_DIRSET_PIN1_Pos (1UL) /*!< Position of PIN1 field. */ #define GPIO_DIRSET_PIN1_Msk (0x1UL << GPIO_DIRSET_PIN1_Pos) /*!< Bit mask of PIN1 field. */ #define GPIO_DIRSET_PIN1_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRSET_PIN1_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRSET_PIN1_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ +#define GPIO_DIRSET_PIN1_Set (1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */ /* Bit 0 : Set as output pin 0 */ #define GPIO_DIRSET_PIN0_Pos (0UL) /*!< Position of PIN0 field. */ #define GPIO_DIRSET_PIN0_Msk (0x1UL << GPIO_DIRSET_PIN0_Pos) /*!< Bit mask of PIN0 field. */ #define GPIO_DIRSET_PIN0_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRSET_PIN0_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRSET_PIN0_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ +#define GPIO_DIRSET_PIN0_Set (1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */ /* Register: GPIO_DIRCLR */ /* Description: DIR clear register */ @@ -3235,224 +3260,224 @@ POSSIBILITY OF SUCH DAMAGE. #define GPIO_DIRCLR_PIN31_Msk (0x1UL << GPIO_DIRCLR_PIN31_Pos) /*!< Bit mask of PIN31 field. */ #define GPIO_DIRCLR_PIN31_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRCLR_PIN31_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRCLR_PIN31_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ +#define GPIO_DIRCLR_PIN31_Clear (1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */ /* Bit 30 : Set as input pin 30 */ #define GPIO_DIRCLR_PIN30_Pos (30UL) /*!< Position of PIN30 field. */ #define GPIO_DIRCLR_PIN30_Msk (0x1UL << GPIO_DIRCLR_PIN30_Pos) /*!< Bit mask of PIN30 field. */ #define GPIO_DIRCLR_PIN30_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRCLR_PIN30_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRCLR_PIN30_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ +#define GPIO_DIRCLR_PIN30_Clear (1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */ /* Bit 29 : Set as input pin 29 */ #define GPIO_DIRCLR_PIN29_Pos (29UL) /*!< Position of PIN29 field. */ #define GPIO_DIRCLR_PIN29_Msk (0x1UL << GPIO_DIRCLR_PIN29_Pos) /*!< Bit mask of PIN29 field. */ #define GPIO_DIRCLR_PIN29_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRCLR_PIN29_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRCLR_PIN29_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ +#define GPIO_DIRCLR_PIN29_Clear (1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */ /* Bit 28 : Set as input pin 28 */ #define GPIO_DIRCLR_PIN28_Pos (28UL) /*!< Position of PIN28 field. */ #define GPIO_DIRCLR_PIN28_Msk (0x1UL << GPIO_DIRCLR_PIN28_Pos) /*!< Bit mask of PIN28 field. */ #define GPIO_DIRCLR_PIN28_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRCLR_PIN28_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRCLR_PIN28_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ +#define GPIO_DIRCLR_PIN28_Clear (1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */ /* Bit 27 : Set as input pin 27 */ #define GPIO_DIRCLR_PIN27_Pos (27UL) /*!< Position of PIN27 field. */ #define GPIO_DIRCLR_PIN27_Msk (0x1UL << GPIO_DIRCLR_PIN27_Pos) /*!< Bit mask of PIN27 field. */ #define GPIO_DIRCLR_PIN27_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRCLR_PIN27_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRCLR_PIN27_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ +#define GPIO_DIRCLR_PIN27_Clear (1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */ /* Bit 26 : Set as input pin 26 */ #define GPIO_DIRCLR_PIN26_Pos (26UL) /*!< Position of PIN26 field. */ #define GPIO_DIRCLR_PIN26_Msk (0x1UL << GPIO_DIRCLR_PIN26_Pos) /*!< Bit mask of PIN26 field. */ #define GPIO_DIRCLR_PIN26_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRCLR_PIN26_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRCLR_PIN26_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ +#define GPIO_DIRCLR_PIN26_Clear (1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */ /* Bit 25 : Set as input pin 25 */ #define GPIO_DIRCLR_PIN25_Pos (25UL) /*!< Position of PIN25 field. */ #define GPIO_DIRCLR_PIN25_Msk (0x1UL << GPIO_DIRCLR_PIN25_Pos) /*!< Bit mask of PIN25 field. */ #define GPIO_DIRCLR_PIN25_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRCLR_PIN25_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRCLR_PIN25_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ +#define GPIO_DIRCLR_PIN25_Clear (1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */ /* Bit 24 : Set as input pin 24 */ #define GPIO_DIRCLR_PIN24_Pos (24UL) /*!< Position of PIN24 field. */ #define GPIO_DIRCLR_PIN24_Msk (0x1UL << GPIO_DIRCLR_PIN24_Pos) /*!< Bit mask of PIN24 field. */ #define GPIO_DIRCLR_PIN24_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRCLR_PIN24_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRCLR_PIN24_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ +#define GPIO_DIRCLR_PIN24_Clear (1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */ /* Bit 23 : Set as input pin 23 */ #define GPIO_DIRCLR_PIN23_Pos (23UL) /*!< Position of PIN23 field. */ #define GPIO_DIRCLR_PIN23_Msk (0x1UL << GPIO_DIRCLR_PIN23_Pos) /*!< Bit mask of PIN23 field. */ #define GPIO_DIRCLR_PIN23_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRCLR_PIN23_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRCLR_PIN23_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ +#define GPIO_DIRCLR_PIN23_Clear (1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */ /* Bit 22 : Set as input pin 22 */ #define GPIO_DIRCLR_PIN22_Pos (22UL) /*!< Position of PIN22 field. */ #define GPIO_DIRCLR_PIN22_Msk (0x1UL << GPIO_DIRCLR_PIN22_Pos) /*!< Bit mask of PIN22 field. */ #define GPIO_DIRCLR_PIN22_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRCLR_PIN22_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRCLR_PIN22_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ +#define GPIO_DIRCLR_PIN22_Clear (1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */ /* Bit 21 : Set as input pin 21 */ #define GPIO_DIRCLR_PIN21_Pos (21UL) /*!< Position of PIN21 field. */ #define GPIO_DIRCLR_PIN21_Msk (0x1UL << GPIO_DIRCLR_PIN21_Pos) /*!< Bit mask of PIN21 field. */ #define GPIO_DIRCLR_PIN21_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRCLR_PIN21_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRCLR_PIN21_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ +#define GPIO_DIRCLR_PIN21_Clear (1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */ /* Bit 20 : Set as input pin 20 */ #define GPIO_DIRCLR_PIN20_Pos (20UL) /*!< Position of PIN20 field. */ #define GPIO_DIRCLR_PIN20_Msk (0x1UL << GPIO_DIRCLR_PIN20_Pos) /*!< Bit mask of PIN20 field. */ #define GPIO_DIRCLR_PIN20_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRCLR_PIN20_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRCLR_PIN20_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ +#define GPIO_DIRCLR_PIN20_Clear (1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */ /* Bit 19 : Set as input pin 19 */ #define GPIO_DIRCLR_PIN19_Pos (19UL) /*!< Position of PIN19 field. */ #define GPIO_DIRCLR_PIN19_Msk (0x1UL << GPIO_DIRCLR_PIN19_Pos) /*!< Bit mask of PIN19 field. */ #define GPIO_DIRCLR_PIN19_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRCLR_PIN19_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRCLR_PIN19_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ +#define GPIO_DIRCLR_PIN19_Clear (1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */ /* Bit 18 : Set as input pin 18 */ #define GPIO_DIRCLR_PIN18_Pos (18UL) /*!< Position of PIN18 field. */ #define GPIO_DIRCLR_PIN18_Msk (0x1UL << GPIO_DIRCLR_PIN18_Pos) /*!< Bit mask of PIN18 field. */ #define GPIO_DIRCLR_PIN18_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRCLR_PIN18_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRCLR_PIN18_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ +#define GPIO_DIRCLR_PIN18_Clear (1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */ /* Bit 17 : Set as input pin 17 */ #define GPIO_DIRCLR_PIN17_Pos (17UL) /*!< Position of PIN17 field. */ #define GPIO_DIRCLR_PIN17_Msk (0x1UL << GPIO_DIRCLR_PIN17_Pos) /*!< Bit mask of PIN17 field. */ #define GPIO_DIRCLR_PIN17_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRCLR_PIN17_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRCLR_PIN17_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ +#define GPIO_DIRCLR_PIN17_Clear (1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */ /* Bit 16 : Set as input pin 16 */ #define GPIO_DIRCLR_PIN16_Pos (16UL) /*!< Position of PIN16 field. */ #define GPIO_DIRCLR_PIN16_Msk (0x1UL << GPIO_DIRCLR_PIN16_Pos) /*!< Bit mask of PIN16 field. */ #define GPIO_DIRCLR_PIN16_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRCLR_PIN16_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRCLR_PIN16_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ +#define GPIO_DIRCLR_PIN16_Clear (1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */ /* Bit 15 : Set as input pin 15 */ #define GPIO_DIRCLR_PIN15_Pos (15UL) /*!< Position of PIN15 field. */ #define GPIO_DIRCLR_PIN15_Msk (0x1UL << GPIO_DIRCLR_PIN15_Pos) /*!< Bit mask of PIN15 field. */ #define GPIO_DIRCLR_PIN15_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRCLR_PIN15_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRCLR_PIN15_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ +#define GPIO_DIRCLR_PIN15_Clear (1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */ /* Bit 14 : Set as input pin 14 */ #define GPIO_DIRCLR_PIN14_Pos (14UL) /*!< Position of PIN14 field. */ #define GPIO_DIRCLR_PIN14_Msk (0x1UL << GPIO_DIRCLR_PIN14_Pos) /*!< Bit mask of PIN14 field. */ #define GPIO_DIRCLR_PIN14_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRCLR_PIN14_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRCLR_PIN14_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ +#define GPIO_DIRCLR_PIN14_Clear (1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */ /* Bit 13 : Set as input pin 13 */ #define GPIO_DIRCLR_PIN13_Pos (13UL) /*!< Position of PIN13 field. */ #define GPIO_DIRCLR_PIN13_Msk (0x1UL << GPIO_DIRCLR_PIN13_Pos) /*!< Bit mask of PIN13 field. */ #define GPIO_DIRCLR_PIN13_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRCLR_PIN13_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRCLR_PIN13_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ +#define GPIO_DIRCLR_PIN13_Clear (1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */ /* Bit 12 : Set as input pin 12 */ #define GPIO_DIRCLR_PIN12_Pos (12UL) /*!< Position of PIN12 field. */ #define GPIO_DIRCLR_PIN12_Msk (0x1UL << GPIO_DIRCLR_PIN12_Pos) /*!< Bit mask of PIN12 field. */ #define GPIO_DIRCLR_PIN12_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRCLR_PIN12_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRCLR_PIN12_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ +#define GPIO_DIRCLR_PIN12_Clear (1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */ /* Bit 11 : Set as input pin 11 */ #define GPIO_DIRCLR_PIN11_Pos (11UL) /*!< Position of PIN11 field. */ #define GPIO_DIRCLR_PIN11_Msk (0x1UL << GPIO_DIRCLR_PIN11_Pos) /*!< Bit mask of PIN11 field. */ #define GPIO_DIRCLR_PIN11_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRCLR_PIN11_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRCLR_PIN11_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ +#define GPIO_DIRCLR_PIN11_Clear (1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */ /* Bit 10 : Set as input pin 10 */ #define GPIO_DIRCLR_PIN10_Pos (10UL) /*!< Position of PIN10 field. */ #define GPIO_DIRCLR_PIN10_Msk (0x1UL << GPIO_DIRCLR_PIN10_Pos) /*!< Bit mask of PIN10 field. */ #define GPIO_DIRCLR_PIN10_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRCLR_PIN10_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRCLR_PIN10_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ +#define GPIO_DIRCLR_PIN10_Clear (1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */ /* Bit 9 : Set as input pin 9 */ #define GPIO_DIRCLR_PIN9_Pos (9UL) /*!< Position of PIN9 field. */ #define GPIO_DIRCLR_PIN9_Msk (0x1UL << GPIO_DIRCLR_PIN9_Pos) /*!< Bit mask of PIN9 field. */ #define GPIO_DIRCLR_PIN9_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRCLR_PIN9_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRCLR_PIN9_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ +#define GPIO_DIRCLR_PIN9_Clear (1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */ /* Bit 8 : Set as input pin 8 */ #define GPIO_DIRCLR_PIN8_Pos (8UL) /*!< Position of PIN8 field. */ #define GPIO_DIRCLR_PIN8_Msk (0x1UL << GPIO_DIRCLR_PIN8_Pos) /*!< Bit mask of PIN8 field. */ #define GPIO_DIRCLR_PIN8_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRCLR_PIN8_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRCLR_PIN8_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ +#define GPIO_DIRCLR_PIN8_Clear (1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */ /* Bit 7 : Set as input pin 7 */ #define GPIO_DIRCLR_PIN7_Pos (7UL) /*!< Position of PIN7 field. */ #define GPIO_DIRCLR_PIN7_Msk (0x1UL << GPIO_DIRCLR_PIN7_Pos) /*!< Bit mask of PIN7 field. */ #define GPIO_DIRCLR_PIN7_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRCLR_PIN7_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRCLR_PIN7_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ +#define GPIO_DIRCLR_PIN7_Clear (1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */ /* Bit 6 : Set as input pin 6 */ #define GPIO_DIRCLR_PIN6_Pos (6UL) /*!< Position of PIN6 field. */ #define GPIO_DIRCLR_PIN6_Msk (0x1UL << GPIO_DIRCLR_PIN6_Pos) /*!< Bit mask of PIN6 field. */ #define GPIO_DIRCLR_PIN6_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRCLR_PIN6_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRCLR_PIN6_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ +#define GPIO_DIRCLR_PIN6_Clear (1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */ /* Bit 5 : Set as input pin 5 */ #define GPIO_DIRCLR_PIN5_Pos (5UL) /*!< Position of PIN5 field. */ #define GPIO_DIRCLR_PIN5_Msk (0x1UL << GPIO_DIRCLR_PIN5_Pos) /*!< Bit mask of PIN5 field. */ #define GPIO_DIRCLR_PIN5_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRCLR_PIN5_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRCLR_PIN5_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ +#define GPIO_DIRCLR_PIN5_Clear (1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */ /* Bit 4 : Set as input pin 4 */ #define GPIO_DIRCLR_PIN4_Pos (4UL) /*!< Position of PIN4 field. */ #define GPIO_DIRCLR_PIN4_Msk (0x1UL << GPIO_DIRCLR_PIN4_Pos) /*!< Bit mask of PIN4 field. */ #define GPIO_DIRCLR_PIN4_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRCLR_PIN4_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRCLR_PIN4_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ +#define GPIO_DIRCLR_PIN4_Clear (1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */ /* Bit 3 : Set as input pin 3 */ #define GPIO_DIRCLR_PIN3_Pos (3UL) /*!< Position of PIN3 field. */ #define GPIO_DIRCLR_PIN3_Msk (0x1UL << GPIO_DIRCLR_PIN3_Pos) /*!< Bit mask of PIN3 field. */ #define GPIO_DIRCLR_PIN3_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRCLR_PIN3_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRCLR_PIN3_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ +#define GPIO_DIRCLR_PIN3_Clear (1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */ /* Bit 2 : Set as input pin 2 */ #define GPIO_DIRCLR_PIN2_Pos (2UL) /*!< Position of PIN2 field. */ #define GPIO_DIRCLR_PIN2_Msk (0x1UL << GPIO_DIRCLR_PIN2_Pos) /*!< Bit mask of PIN2 field. */ #define GPIO_DIRCLR_PIN2_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRCLR_PIN2_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRCLR_PIN2_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ +#define GPIO_DIRCLR_PIN2_Clear (1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */ /* Bit 1 : Set as input pin 1 */ #define GPIO_DIRCLR_PIN1_Pos (1UL) /*!< Position of PIN1 field. */ #define GPIO_DIRCLR_PIN1_Msk (0x1UL << GPIO_DIRCLR_PIN1_Pos) /*!< Bit mask of PIN1 field. */ #define GPIO_DIRCLR_PIN1_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRCLR_PIN1_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRCLR_PIN1_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ +#define GPIO_DIRCLR_PIN1_Clear (1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */ /* Bit 0 : Set as input pin 0 */ #define GPIO_DIRCLR_PIN0_Pos (0UL) /*!< Position of PIN0 field. */ #define GPIO_DIRCLR_PIN0_Msk (0x1UL << GPIO_DIRCLR_PIN0_Pos) /*!< Bit mask of PIN0 field. */ #define GPIO_DIRCLR_PIN0_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRCLR_PIN0_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRCLR_PIN0_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ +#define GPIO_DIRCLR_PIN0_Clear (1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */ /* Register: GPIO_LATCH */ /* Description: Latch register indicating what GPIO pins that have met the criteria set in the PIN_CNF[n].SENSE registers */ @@ -3650,13 +3675,13 @@ POSSIBILITY OF SUCH DAMAGE. #define GPIO_LATCH_PIN0_Latched (1UL) /*!< Criteria has been met */ /* Register: GPIO_DETECTMODE */ -/* Description: Select between default DETECT signal behaviour and LDETECT mode */ +/* Description: Select between default DETECT signal behavior and LDETECT mode */ -/* Bit 0 : Select between default DETECT signal behaviour and LDETECT mode */ +/* Bit 0 : Select between default DETECT signal behavior and LDETECT mode */ #define GPIO_DETECTMODE_DETECTMODE_Pos (0UL) /*!< Position of DETECTMODE field. */ #define GPIO_DETECTMODE_DETECTMODE_Msk (0x1UL << GPIO_DETECTMODE_DETECTMODE_Pos) /*!< Bit mask of DETECTMODE field. */ #define GPIO_DETECTMODE_DETECTMODE_Default (0UL) /*!< DETECT directly connected to PIN DETECT signals */ -#define GPIO_DETECTMODE_DETECTMODE_LDETECT (1UL) /*!< Use the latched LDETECT behaviour */ +#define GPIO_DETECTMODE_DETECTMODE_LDETECT (1UL) /*!< Use the latched LDETECT behavior */ /* Register: GPIO_PIN_CNF */ /* Description: Description collection: Configuration of GPIO pins */ @@ -4314,224 +4339,224 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: PPI_CHENSET */ /* Description: Channel enable set register */ -/* Bit 31 : Channel 31 enable set register. Writing '0' has no effect */ +/* Bit 31 : Channel 31 enable set register. Writing '0' has no effect. */ #define PPI_CHENSET_CH31_Pos (31UL) /*!< Position of CH31 field. */ #define PPI_CHENSET_CH31_Msk (0x1UL << PPI_CHENSET_CH31_Pos) /*!< Bit mask of CH31 field. */ #define PPI_CHENSET_CH31_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENSET_CH31_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENSET_CH31_Set (1UL) /*!< Write: Enable channel */ -/* Bit 30 : Channel 30 enable set register. Writing '0' has no effect */ +/* Bit 30 : Channel 30 enable set register. Writing '0' has no effect. */ #define PPI_CHENSET_CH30_Pos (30UL) /*!< Position of CH30 field. */ #define PPI_CHENSET_CH30_Msk (0x1UL << PPI_CHENSET_CH30_Pos) /*!< Bit mask of CH30 field. */ #define PPI_CHENSET_CH30_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENSET_CH30_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENSET_CH30_Set (1UL) /*!< Write: Enable channel */ -/* Bit 29 : Channel 29 enable set register. Writing '0' has no effect */ +/* Bit 29 : Channel 29 enable set register. Writing '0' has no effect. */ #define PPI_CHENSET_CH29_Pos (29UL) /*!< Position of CH29 field. */ #define PPI_CHENSET_CH29_Msk (0x1UL << PPI_CHENSET_CH29_Pos) /*!< Bit mask of CH29 field. */ #define PPI_CHENSET_CH29_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENSET_CH29_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENSET_CH29_Set (1UL) /*!< Write: Enable channel */ -/* Bit 28 : Channel 28 enable set register. Writing '0' has no effect */ +/* Bit 28 : Channel 28 enable set register. Writing '0' has no effect. */ #define PPI_CHENSET_CH28_Pos (28UL) /*!< Position of CH28 field. */ #define PPI_CHENSET_CH28_Msk (0x1UL << PPI_CHENSET_CH28_Pos) /*!< Bit mask of CH28 field. */ #define PPI_CHENSET_CH28_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENSET_CH28_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENSET_CH28_Set (1UL) /*!< Write: Enable channel */ -/* Bit 27 : Channel 27 enable set register. Writing '0' has no effect */ +/* Bit 27 : Channel 27 enable set register. Writing '0' has no effect. */ #define PPI_CHENSET_CH27_Pos (27UL) /*!< Position of CH27 field. */ #define PPI_CHENSET_CH27_Msk (0x1UL << PPI_CHENSET_CH27_Pos) /*!< Bit mask of CH27 field. */ #define PPI_CHENSET_CH27_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENSET_CH27_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENSET_CH27_Set (1UL) /*!< Write: Enable channel */ -/* Bit 26 : Channel 26 enable set register. Writing '0' has no effect */ +/* Bit 26 : Channel 26 enable set register. Writing '0' has no effect. */ #define PPI_CHENSET_CH26_Pos (26UL) /*!< Position of CH26 field. */ #define PPI_CHENSET_CH26_Msk (0x1UL << PPI_CHENSET_CH26_Pos) /*!< Bit mask of CH26 field. */ #define PPI_CHENSET_CH26_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENSET_CH26_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENSET_CH26_Set (1UL) /*!< Write: Enable channel */ -/* Bit 25 : Channel 25 enable set register. Writing '0' has no effect */ +/* Bit 25 : Channel 25 enable set register. Writing '0' has no effect. */ #define PPI_CHENSET_CH25_Pos (25UL) /*!< Position of CH25 field. */ #define PPI_CHENSET_CH25_Msk (0x1UL << PPI_CHENSET_CH25_Pos) /*!< Bit mask of CH25 field. */ #define PPI_CHENSET_CH25_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENSET_CH25_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENSET_CH25_Set (1UL) /*!< Write: Enable channel */ -/* Bit 24 : Channel 24 enable set register. Writing '0' has no effect */ +/* Bit 24 : Channel 24 enable set register. Writing '0' has no effect. */ #define PPI_CHENSET_CH24_Pos (24UL) /*!< Position of CH24 field. */ #define PPI_CHENSET_CH24_Msk (0x1UL << PPI_CHENSET_CH24_Pos) /*!< Bit mask of CH24 field. */ #define PPI_CHENSET_CH24_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENSET_CH24_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENSET_CH24_Set (1UL) /*!< Write: Enable channel */ -/* Bit 23 : Channel 23 enable set register. Writing '0' has no effect */ +/* Bit 23 : Channel 23 enable set register. Writing '0' has no effect. */ #define PPI_CHENSET_CH23_Pos (23UL) /*!< Position of CH23 field. */ #define PPI_CHENSET_CH23_Msk (0x1UL << PPI_CHENSET_CH23_Pos) /*!< Bit mask of CH23 field. */ #define PPI_CHENSET_CH23_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENSET_CH23_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENSET_CH23_Set (1UL) /*!< Write: Enable channel */ -/* Bit 22 : Channel 22 enable set register. Writing '0' has no effect */ +/* Bit 22 : Channel 22 enable set register. Writing '0' has no effect. */ #define PPI_CHENSET_CH22_Pos (22UL) /*!< Position of CH22 field. */ #define PPI_CHENSET_CH22_Msk (0x1UL << PPI_CHENSET_CH22_Pos) /*!< Bit mask of CH22 field. */ #define PPI_CHENSET_CH22_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENSET_CH22_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENSET_CH22_Set (1UL) /*!< Write: Enable channel */ -/* Bit 21 : Channel 21 enable set register. Writing '0' has no effect */ +/* Bit 21 : Channel 21 enable set register. Writing '0' has no effect. */ #define PPI_CHENSET_CH21_Pos (21UL) /*!< Position of CH21 field. */ #define PPI_CHENSET_CH21_Msk (0x1UL << PPI_CHENSET_CH21_Pos) /*!< Bit mask of CH21 field. */ #define PPI_CHENSET_CH21_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENSET_CH21_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENSET_CH21_Set (1UL) /*!< Write: Enable channel */ -/* Bit 20 : Channel 20 enable set register. Writing '0' has no effect */ +/* Bit 20 : Channel 20 enable set register. Writing '0' has no effect. */ #define PPI_CHENSET_CH20_Pos (20UL) /*!< Position of CH20 field. */ #define PPI_CHENSET_CH20_Msk (0x1UL << PPI_CHENSET_CH20_Pos) /*!< Bit mask of CH20 field. */ #define PPI_CHENSET_CH20_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENSET_CH20_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENSET_CH20_Set (1UL) /*!< Write: Enable channel */ -/* Bit 19 : Channel 19 enable set register. Writing '0' has no effect */ +/* Bit 19 : Channel 19 enable set register. Writing '0' has no effect. */ #define PPI_CHENSET_CH19_Pos (19UL) /*!< Position of CH19 field. */ #define PPI_CHENSET_CH19_Msk (0x1UL << PPI_CHENSET_CH19_Pos) /*!< Bit mask of CH19 field. */ #define PPI_CHENSET_CH19_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENSET_CH19_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENSET_CH19_Set (1UL) /*!< Write: Enable channel */ -/* Bit 18 : Channel 18 enable set register. Writing '0' has no effect */ +/* Bit 18 : Channel 18 enable set register. Writing '0' has no effect. */ #define PPI_CHENSET_CH18_Pos (18UL) /*!< Position of CH18 field. */ #define PPI_CHENSET_CH18_Msk (0x1UL << PPI_CHENSET_CH18_Pos) /*!< Bit mask of CH18 field. */ #define PPI_CHENSET_CH18_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENSET_CH18_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENSET_CH18_Set (1UL) /*!< Write: Enable channel */ -/* Bit 17 : Channel 17 enable set register. Writing '0' has no effect */ +/* Bit 17 : Channel 17 enable set register. Writing '0' has no effect. */ #define PPI_CHENSET_CH17_Pos (17UL) /*!< Position of CH17 field. */ #define PPI_CHENSET_CH17_Msk (0x1UL << PPI_CHENSET_CH17_Pos) /*!< Bit mask of CH17 field. */ #define PPI_CHENSET_CH17_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENSET_CH17_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENSET_CH17_Set (1UL) /*!< Write: Enable channel */ -/* Bit 16 : Channel 16 enable set register. Writing '0' has no effect */ +/* Bit 16 : Channel 16 enable set register. Writing '0' has no effect. */ #define PPI_CHENSET_CH16_Pos (16UL) /*!< Position of CH16 field. */ #define PPI_CHENSET_CH16_Msk (0x1UL << PPI_CHENSET_CH16_Pos) /*!< Bit mask of CH16 field. */ #define PPI_CHENSET_CH16_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENSET_CH16_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENSET_CH16_Set (1UL) /*!< Write: Enable channel */ -/* Bit 15 : Channel 15 enable set register. Writing '0' has no effect */ +/* Bit 15 : Channel 15 enable set register. Writing '0' has no effect. */ #define PPI_CHENSET_CH15_Pos (15UL) /*!< Position of CH15 field. */ #define PPI_CHENSET_CH15_Msk (0x1UL << PPI_CHENSET_CH15_Pos) /*!< Bit mask of CH15 field. */ #define PPI_CHENSET_CH15_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENSET_CH15_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENSET_CH15_Set (1UL) /*!< Write: Enable channel */ -/* Bit 14 : Channel 14 enable set register. Writing '0' has no effect */ +/* Bit 14 : Channel 14 enable set register. Writing '0' has no effect. */ #define PPI_CHENSET_CH14_Pos (14UL) /*!< Position of CH14 field. */ #define PPI_CHENSET_CH14_Msk (0x1UL << PPI_CHENSET_CH14_Pos) /*!< Bit mask of CH14 field. */ #define PPI_CHENSET_CH14_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENSET_CH14_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENSET_CH14_Set (1UL) /*!< Write: Enable channel */ -/* Bit 13 : Channel 13 enable set register. Writing '0' has no effect */ +/* Bit 13 : Channel 13 enable set register. Writing '0' has no effect. */ #define PPI_CHENSET_CH13_Pos (13UL) /*!< Position of CH13 field. */ #define PPI_CHENSET_CH13_Msk (0x1UL << PPI_CHENSET_CH13_Pos) /*!< Bit mask of CH13 field. */ #define PPI_CHENSET_CH13_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENSET_CH13_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENSET_CH13_Set (1UL) /*!< Write: Enable channel */ -/* Bit 12 : Channel 12 enable set register. Writing '0' has no effect */ +/* Bit 12 : Channel 12 enable set register. Writing '0' has no effect. */ #define PPI_CHENSET_CH12_Pos (12UL) /*!< Position of CH12 field. */ #define PPI_CHENSET_CH12_Msk (0x1UL << PPI_CHENSET_CH12_Pos) /*!< Bit mask of CH12 field. */ #define PPI_CHENSET_CH12_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENSET_CH12_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENSET_CH12_Set (1UL) /*!< Write: Enable channel */ -/* Bit 11 : Channel 11 enable set register. Writing '0' has no effect */ +/* Bit 11 : Channel 11 enable set register. Writing '0' has no effect. */ #define PPI_CHENSET_CH11_Pos (11UL) /*!< Position of CH11 field. */ #define PPI_CHENSET_CH11_Msk (0x1UL << PPI_CHENSET_CH11_Pos) /*!< Bit mask of CH11 field. */ #define PPI_CHENSET_CH11_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENSET_CH11_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENSET_CH11_Set (1UL) /*!< Write: Enable channel */ -/* Bit 10 : Channel 10 enable set register. Writing '0' has no effect */ +/* Bit 10 : Channel 10 enable set register. Writing '0' has no effect. */ #define PPI_CHENSET_CH10_Pos (10UL) /*!< Position of CH10 field. */ #define PPI_CHENSET_CH10_Msk (0x1UL << PPI_CHENSET_CH10_Pos) /*!< Bit mask of CH10 field. */ #define PPI_CHENSET_CH10_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENSET_CH10_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENSET_CH10_Set (1UL) /*!< Write: Enable channel */ -/* Bit 9 : Channel 9 enable set register. Writing '0' has no effect */ +/* Bit 9 : Channel 9 enable set register. Writing '0' has no effect. */ #define PPI_CHENSET_CH9_Pos (9UL) /*!< Position of CH9 field. */ #define PPI_CHENSET_CH9_Msk (0x1UL << PPI_CHENSET_CH9_Pos) /*!< Bit mask of CH9 field. */ #define PPI_CHENSET_CH9_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENSET_CH9_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENSET_CH9_Set (1UL) /*!< Write: Enable channel */ -/* Bit 8 : Channel 8 enable set register. Writing '0' has no effect */ +/* Bit 8 : Channel 8 enable set register. Writing '0' has no effect. */ #define PPI_CHENSET_CH8_Pos (8UL) /*!< Position of CH8 field. */ #define PPI_CHENSET_CH8_Msk (0x1UL << PPI_CHENSET_CH8_Pos) /*!< Bit mask of CH8 field. */ #define PPI_CHENSET_CH8_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENSET_CH8_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENSET_CH8_Set (1UL) /*!< Write: Enable channel */ -/* Bit 7 : Channel 7 enable set register. Writing '0' has no effect */ +/* Bit 7 : Channel 7 enable set register. Writing '0' has no effect. */ #define PPI_CHENSET_CH7_Pos (7UL) /*!< Position of CH7 field. */ #define PPI_CHENSET_CH7_Msk (0x1UL << PPI_CHENSET_CH7_Pos) /*!< Bit mask of CH7 field. */ #define PPI_CHENSET_CH7_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENSET_CH7_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENSET_CH7_Set (1UL) /*!< Write: Enable channel */ -/* Bit 6 : Channel 6 enable set register. Writing '0' has no effect */ +/* Bit 6 : Channel 6 enable set register. Writing '0' has no effect. */ #define PPI_CHENSET_CH6_Pos (6UL) /*!< Position of CH6 field. */ #define PPI_CHENSET_CH6_Msk (0x1UL << PPI_CHENSET_CH6_Pos) /*!< Bit mask of CH6 field. */ #define PPI_CHENSET_CH6_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENSET_CH6_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENSET_CH6_Set (1UL) /*!< Write: Enable channel */ -/* Bit 5 : Channel 5 enable set register. Writing '0' has no effect */ +/* Bit 5 : Channel 5 enable set register. Writing '0' has no effect. */ #define PPI_CHENSET_CH5_Pos (5UL) /*!< Position of CH5 field. */ #define PPI_CHENSET_CH5_Msk (0x1UL << PPI_CHENSET_CH5_Pos) /*!< Bit mask of CH5 field. */ #define PPI_CHENSET_CH5_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENSET_CH5_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENSET_CH5_Set (1UL) /*!< Write: Enable channel */ -/* Bit 4 : Channel 4 enable set register. Writing '0' has no effect */ +/* Bit 4 : Channel 4 enable set register. Writing '0' has no effect. */ #define PPI_CHENSET_CH4_Pos (4UL) /*!< Position of CH4 field. */ #define PPI_CHENSET_CH4_Msk (0x1UL << PPI_CHENSET_CH4_Pos) /*!< Bit mask of CH4 field. */ #define PPI_CHENSET_CH4_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENSET_CH4_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENSET_CH4_Set (1UL) /*!< Write: Enable channel */ -/* Bit 3 : Channel 3 enable set register. Writing '0' has no effect */ +/* Bit 3 : Channel 3 enable set register. Writing '0' has no effect. */ #define PPI_CHENSET_CH3_Pos (3UL) /*!< Position of CH3 field. */ #define PPI_CHENSET_CH3_Msk (0x1UL << PPI_CHENSET_CH3_Pos) /*!< Bit mask of CH3 field. */ #define PPI_CHENSET_CH3_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENSET_CH3_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENSET_CH3_Set (1UL) /*!< Write: Enable channel */ -/* Bit 2 : Channel 2 enable set register. Writing '0' has no effect */ +/* Bit 2 : Channel 2 enable set register. Writing '0' has no effect. */ #define PPI_CHENSET_CH2_Pos (2UL) /*!< Position of CH2 field. */ #define PPI_CHENSET_CH2_Msk (0x1UL << PPI_CHENSET_CH2_Pos) /*!< Bit mask of CH2 field. */ #define PPI_CHENSET_CH2_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENSET_CH2_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENSET_CH2_Set (1UL) /*!< Write: Enable channel */ -/* Bit 1 : Channel 1 enable set register. Writing '0' has no effect */ +/* Bit 1 : Channel 1 enable set register. Writing '0' has no effect. */ #define PPI_CHENSET_CH1_Pos (1UL) /*!< Position of CH1 field. */ #define PPI_CHENSET_CH1_Msk (0x1UL << PPI_CHENSET_CH1_Pos) /*!< Bit mask of CH1 field. */ #define PPI_CHENSET_CH1_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENSET_CH1_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENSET_CH1_Set (1UL) /*!< Write: Enable channel */ -/* Bit 0 : Channel 0 enable set register. Writing '0' has no effect */ +/* Bit 0 : Channel 0 enable set register. Writing '0' has no effect. */ #define PPI_CHENSET_CH0_Pos (0UL) /*!< Position of CH0 field. */ #define PPI_CHENSET_CH0_Msk (0x1UL << PPI_CHENSET_CH0_Pos) /*!< Bit mask of CH0 field. */ #define PPI_CHENSET_CH0_Disabled (0UL) /*!< Read: channel disabled */ @@ -4541,224 +4566,224 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: PPI_CHENCLR */ /* Description: Channel enable clear register */ -/* Bit 31 : Channel 31 enable clear register. Writing '0' has no effect */ +/* Bit 31 : Channel 31 enable clear register. Writing '0' has no effect. */ #define PPI_CHENCLR_CH31_Pos (31UL) /*!< Position of CH31 field. */ #define PPI_CHENCLR_CH31_Msk (0x1UL << PPI_CHENCLR_CH31_Pos) /*!< Bit mask of CH31 field. */ #define PPI_CHENCLR_CH31_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENCLR_CH31_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENCLR_CH31_Clear (1UL) /*!< Write: disable channel */ -/* Bit 30 : Channel 30 enable clear register. Writing '0' has no effect */ +/* Bit 30 : Channel 30 enable clear register. Writing '0' has no effect. */ #define PPI_CHENCLR_CH30_Pos (30UL) /*!< Position of CH30 field. */ #define PPI_CHENCLR_CH30_Msk (0x1UL << PPI_CHENCLR_CH30_Pos) /*!< Bit mask of CH30 field. */ #define PPI_CHENCLR_CH30_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENCLR_CH30_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENCLR_CH30_Clear (1UL) /*!< Write: disable channel */ -/* Bit 29 : Channel 29 enable clear register. Writing '0' has no effect */ +/* Bit 29 : Channel 29 enable clear register. Writing '0' has no effect. */ #define PPI_CHENCLR_CH29_Pos (29UL) /*!< Position of CH29 field. */ #define PPI_CHENCLR_CH29_Msk (0x1UL << PPI_CHENCLR_CH29_Pos) /*!< Bit mask of CH29 field. */ #define PPI_CHENCLR_CH29_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENCLR_CH29_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENCLR_CH29_Clear (1UL) /*!< Write: disable channel */ -/* Bit 28 : Channel 28 enable clear register. Writing '0' has no effect */ +/* Bit 28 : Channel 28 enable clear register. Writing '0' has no effect. */ #define PPI_CHENCLR_CH28_Pos (28UL) /*!< Position of CH28 field. */ #define PPI_CHENCLR_CH28_Msk (0x1UL << PPI_CHENCLR_CH28_Pos) /*!< Bit mask of CH28 field. */ #define PPI_CHENCLR_CH28_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENCLR_CH28_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENCLR_CH28_Clear (1UL) /*!< Write: disable channel */ -/* Bit 27 : Channel 27 enable clear register. Writing '0' has no effect */ +/* Bit 27 : Channel 27 enable clear register. Writing '0' has no effect. */ #define PPI_CHENCLR_CH27_Pos (27UL) /*!< Position of CH27 field. */ #define PPI_CHENCLR_CH27_Msk (0x1UL << PPI_CHENCLR_CH27_Pos) /*!< Bit mask of CH27 field. */ #define PPI_CHENCLR_CH27_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENCLR_CH27_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENCLR_CH27_Clear (1UL) /*!< Write: disable channel */ -/* Bit 26 : Channel 26 enable clear register. Writing '0' has no effect */ +/* Bit 26 : Channel 26 enable clear register. Writing '0' has no effect. */ #define PPI_CHENCLR_CH26_Pos (26UL) /*!< Position of CH26 field. */ #define PPI_CHENCLR_CH26_Msk (0x1UL << PPI_CHENCLR_CH26_Pos) /*!< Bit mask of CH26 field. */ #define PPI_CHENCLR_CH26_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENCLR_CH26_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENCLR_CH26_Clear (1UL) /*!< Write: disable channel */ -/* Bit 25 : Channel 25 enable clear register. Writing '0' has no effect */ +/* Bit 25 : Channel 25 enable clear register. Writing '0' has no effect. */ #define PPI_CHENCLR_CH25_Pos (25UL) /*!< Position of CH25 field. */ #define PPI_CHENCLR_CH25_Msk (0x1UL << PPI_CHENCLR_CH25_Pos) /*!< Bit mask of CH25 field. */ #define PPI_CHENCLR_CH25_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENCLR_CH25_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENCLR_CH25_Clear (1UL) /*!< Write: disable channel */ -/* Bit 24 : Channel 24 enable clear register. Writing '0' has no effect */ +/* Bit 24 : Channel 24 enable clear register. Writing '0' has no effect. */ #define PPI_CHENCLR_CH24_Pos (24UL) /*!< Position of CH24 field. */ #define PPI_CHENCLR_CH24_Msk (0x1UL << PPI_CHENCLR_CH24_Pos) /*!< Bit mask of CH24 field. */ #define PPI_CHENCLR_CH24_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENCLR_CH24_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENCLR_CH24_Clear (1UL) /*!< Write: disable channel */ -/* Bit 23 : Channel 23 enable clear register. Writing '0' has no effect */ +/* Bit 23 : Channel 23 enable clear register. Writing '0' has no effect. */ #define PPI_CHENCLR_CH23_Pos (23UL) /*!< Position of CH23 field. */ #define PPI_CHENCLR_CH23_Msk (0x1UL << PPI_CHENCLR_CH23_Pos) /*!< Bit mask of CH23 field. */ #define PPI_CHENCLR_CH23_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENCLR_CH23_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENCLR_CH23_Clear (1UL) /*!< Write: disable channel */ -/* Bit 22 : Channel 22 enable clear register. Writing '0' has no effect */ +/* Bit 22 : Channel 22 enable clear register. Writing '0' has no effect. */ #define PPI_CHENCLR_CH22_Pos (22UL) /*!< Position of CH22 field. */ #define PPI_CHENCLR_CH22_Msk (0x1UL << PPI_CHENCLR_CH22_Pos) /*!< Bit mask of CH22 field. */ #define PPI_CHENCLR_CH22_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENCLR_CH22_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENCLR_CH22_Clear (1UL) /*!< Write: disable channel */ -/* Bit 21 : Channel 21 enable clear register. Writing '0' has no effect */ +/* Bit 21 : Channel 21 enable clear register. Writing '0' has no effect. */ #define PPI_CHENCLR_CH21_Pos (21UL) /*!< Position of CH21 field. */ #define PPI_CHENCLR_CH21_Msk (0x1UL << PPI_CHENCLR_CH21_Pos) /*!< Bit mask of CH21 field. */ #define PPI_CHENCLR_CH21_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENCLR_CH21_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENCLR_CH21_Clear (1UL) /*!< Write: disable channel */ -/* Bit 20 : Channel 20 enable clear register. Writing '0' has no effect */ +/* Bit 20 : Channel 20 enable clear register. Writing '0' has no effect. */ #define PPI_CHENCLR_CH20_Pos (20UL) /*!< Position of CH20 field. */ #define PPI_CHENCLR_CH20_Msk (0x1UL << PPI_CHENCLR_CH20_Pos) /*!< Bit mask of CH20 field. */ #define PPI_CHENCLR_CH20_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENCLR_CH20_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENCLR_CH20_Clear (1UL) /*!< Write: disable channel */ -/* Bit 19 : Channel 19 enable clear register. Writing '0' has no effect */ +/* Bit 19 : Channel 19 enable clear register. Writing '0' has no effect. */ #define PPI_CHENCLR_CH19_Pos (19UL) /*!< Position of CH19 field. */ #define PPI_CHENCLR_CH19_Msk (0x1UL << PPI_CHENCLR_CH19_Pos) /*!< Bit mask of CH19 field. */ #define PPI_CHENCLR_CH19_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENCLR_CH19_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENCLR_CH19_Clear (1UL) /*!< Write: disable channel */ -/* Bit 18 : Channel 18 enable clear register. Writing '0' has no effect */ +/* Bit 18 : Channel 18 enable clear register. Writing '0' has no effect. */ #define PPI_CHENCLR_CH18_Pos (18UL) /*!< Position of CH18 field. */ #define PPI_CHENCLR_CH18_Msk (0x1UL << PPI_CHENCLR_CH18_Pos) /*!< Bit mask of CH18 field. */ #define PPI_CHENCLR_CH18_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENCLR_CH18_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENCLR_CH18_Clear (1UL) /*!< Write: disable channel */ -/* Bit 17 : Channel 17 enable clear register. Writing '0' has no effect */ +/* Bit 17 : Channel 17 enable clear register. Writing '0' has no effect. */ #define PPI_CHENCLR_CH17_Pos (17UL) /*!< Position of CH17 field. */ #define PPI_CHENCLR_CH17_Msk (0x1UL << PPI_CHENCLR_CH17_Pos) /*!< Bit mask of CH17 field. */ #define PPI_CHENCLR_CH17_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENCLR_CH17_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENCLR_CH17_Clear (1UL) /*!< Write: disable channel */ -/* Bit 16 : Channel 16 enable clear register. Writing '0' has no effect */ +/* Bit 16 : Channel 16 enable clear register. Writing '0' has no effect. */ #define PPI_CHENCLR_CH16_Pos (16UL) /*!< Position of CH16 field. */ #define PPI_CHENCLR_CH16_Msk (0x1UL << PPI_CHENCLR_CH16_Pos) /*!< Bit mask of CH16 field. */ #define PPI_CHENCLR_CH16_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENCLR_CH16_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENCLR_CH16_Clear (1UL) /*!< Write: disable channel */ -/* Bit 15 : Channel 15 enable clear register. Writing '0' has no effect */ +/* Bit 15 : Channel 15 enable clear register. Writing '0' has no effect. */ #define PPI_CHENCLR_CH15_Pos (15UL) /*!< Position of CH15 field. */ #define PPI_CHENCLR_CH15_Msk (0x1UL << PPI_CHENCLR_CH15_Pos) /*!< Bit mask of CH15 field. */ #define PPI_CHENCLR_CH15_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENCLR_CH15_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENCLR_CH15_Clear (1UL) /*!< Write: disable channel */ -/* Bit 14 : Channel 14 enable clear register. Writing '0' has no effect */ +/* Bit 14 : Channel 14 enable clear register. Writing '0' has no effect. */ #define PPI_CHENCLR_CH14_Pos (14UL) /*!< Position of CH14 field. */ #define PPI_CHENCLR_CH14_Msk (0x1UL << PPI_CHENCLR_CH14_Pos) /*!< Bit mask of CH14 field. */ #define PPI_CHENCLR_CH14_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENCLR_CH14_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENCLR_CH14_Clear (1UL) /*!< Write: disable channel */ -/* Bit 13 : Channel 13 enable clear register. Writing '0' has no effect */ +/* Bit 13 : Channel 13 enable clear register. Writing '0' has no effect. */ #define PPI_CHENCLR_CH13_Pos (13UL) /*!< Position of CH13 field. */ #define PPI_CHENCLR_CH13_Msk (0x1UL << PPI_CHENCLR_CH13_Pos) /*!< Bit mask of CH13 field. */ #define PPI_CHENCLR_CH13_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENCLR_CH13_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENCLR_CH13_Clear (1UL) /*!< Write: disable channel */ -/* Bit 12 : Channel 12 enable clear register. Writing '0' has no effect */ +/* Bit 12 : Channel 12 enable clear register. Writing '0' has no effect. */ #define PPI_CHENCLR_CH12_Pos (12UL) /*!< Position of CH12 field. */ #define PPI_CHENCLR_CH12_Msk (0x1UL << PPI_CHENCLR_CH12_Pos) /*!< Bit mask of CH12 field. */ #define PPI_CHENCLR_CH12_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENCLR_CH12_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENCLR_CH12_Clear (1UL) /*!< Write: disable channel */ -/* Bit 11 : Channel 11 enable clear register. Writing '0' has no effect */ +/* Bit 11 : Channel 11 enable clear register. Writing '0' has no effect. */ #define PPI_CHENCLR_CH11_Pos (11UL) /*!< Position of CH11 field. */ #define PPI_CHENCLR_CH11_Msk (0x1UL << PPI_CHENCLR_CH11_Pos) /*!< Bit mask of CH11 field. */ #define PPI_CHENCLR_CH11_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENCLR_CH11_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENCLR_CH11_Clear (1UL) /*!< Write: disable channel */ -/* Bit 10 : Channel 10 enable clear register. Writing '0' has no effect */ +/* Bit 10 : Channel 10 enable clear register. Writing '0' has no effect. */ #define PPI_CHENCLR_CH10_Pos (10UL) /*!< Position of CH10 field. */ #define PPI_CHENCLR_CH10_Msk (0x1UL << PPI_CHENCLR_CH10_Pos) /*!< Bit mask of CH10 field. */ #define PPI_CHENCLR_CH10_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENCLR_CH10_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENCLR_CH10_Clear (1UL) /*!< Write: disable channel */ -/* Bit 9 : Channel 9 enable clear register. Writing '0' has no effect */ +/* Bit 9 : Channel 9 enable clear register. Writing '0' has no effect. */ #define PPI_CHENCLR_CH9_Pos (9UL) /*!< Position of CH9 field. */ #define PPI_CHENCLR_CH9_Msk (0x1UL << PPI_CHENCLR_CH9_Pos) /*!< Bit mask of CH9 field. */ #define PPI_CHENCLR_CH9_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENCLR_CH9_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENCLR_CH9_Clear (1UL) /*!< Write: disable channel */ -/* Bit 8 : Channel 8 enable clear register. Writing '0' has no effect */ +/* Bit 8 : Channel 8 enable clear register. Writing '0' has no effect. */ #define PPI_CHENCLR_CH8_Pos (8UL) /*!< Position of CH8 field. */ #define PPI_CHENCLR_CH8_Msk (0x1UL << PPI_CHENCLR_CH8_Pos) /*!< Bit mask of CH8 field. */ #define PPI_CHENCLR_CH8_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENCLR_CH8_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENCLR_CH8_Clear (1UL) /*!< Write: disable channel */ -/* Bit 7 : Channel 7 enable clear register. Writing '0' has no effect */ +/* Bit 7 : Channel 7 enable clear register. Writing '0' has no effect. */ #define PPI_CHENCLR_CH7_Pos (7UL) /*!< Position of CH7 field. */ #define PPI_CHENCLR_CH7_Msk (0x1UL << PPI_CHENCLR_CH7_Pos) /*!< Bit mask of CH7 field. */ #define PPI_CHENCLR_CH7_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENCLR_CH7_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENCLR_CH7_Clear (1UL) /*!< Write: disable channel */ -/* Bit 6 : Channel 6 enable clear register. Writing '0' has no effect */ +/* Bit 6 : Channel 6 enable clear register. Writing '0' has no effect. */ #define PPI_CHENCLR_CH6_Pos (6UL) /*!< Position of CH6 field. */ #define PPI_CHENCLR_CH6_Msk (0x1UL << PPI_CHENCLR_CH6_Pos) /*!< Bit mask of CH6 field. */ #define PPI_CHENCLR_CH6_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENCLR_CH6_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENCLR_CH6_Clear (1UL) /*!< Write: disable channel */ -/* Bit 5 : Channel 5 enable clear register. Writing '0' has no effect */ +/* Bit 5 : Channel 5 enable clear register. Writing '0' has no effect. */ #define PPI_CHENCLR_CH5_Pos (5UL) /*!< Position of CH5 field. */ #define PPI_CHENCLR_CH5_Msk (0x1UL << PPI_CHENCLR_CH5_Pos) /*!< Bit mask of CH5 field. */ #define PPI_CHENCLR_CH5_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENCLR_CH5_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENCLR_CH5_Clear (1UL) /*!< Write: disable channel */ -/* Bit 4 : Channel 4 enable clear register. Writing '0' has no effect */ +/* Bit 4 : Channel 4 enable clear register. Writing '0' has no effect. */ #define PPI_CHENCLR_CH4_Pos (4UL) /*!< Position of CH4 field. */ #define PPI_CHENCLR_CH4_Msk (0x1UL << PPI_CHENCLR_CH4_Pos) /*!< Bit mask of CH4 field. */ #define PPI_CHENCLR_CH4_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENCLR_CH4_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENCLR_CH4_Clear (1UL) /*!< Write: disable channel */ -/* Bit 3 : Channel 3 enable clear register. Writing '0' has no effect */ +/* Bit 3 : Channel 3 enable clear register. Writing '0' has no effect. */ #define PPI_CHENCLR_CH3_Pos (3UL) /*!< Position of CH3 field. */ #define PPI_CHENCLR_CH3_Msk (0x1UL << PPI_CHENCLR_CH3_Pos) /*!< Bit mask of CH3 field. */ #define PPI_CHENCLR_CH3_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENCLR_CH3_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENCLR_CH3_Clear (1UL) /*!< Write: disable channel */ -/* Bit 2 : Channel 2 enable clear register. Writing '0' has no effect */ +/* Bit 2 : Channel 2 enable clear register. Writing '0' has no effect. */ #define PPI_CHENCLR_CH2_Pos (2UL) /*!< Position of CH2 field. */ #define PPI_CHENCLR_CH2_Msk (0x1UL << PPI_CHENCLR_CH2_Pos) /*!< Bit mask of CH2 field. */ #define PPI_CHENCLR_CH2_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENCLR_CH2_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENCLR_CH2_Clear (1UL) /*!< Write: disable channel */ -/* Bit 1 : Channel 1 enable clear register. Writing '0' has no effect */ +/* Bit 1 : Channel 1 enable clear register. Writing '0' has no effect. */ #define PPI_CHENCLR_CH1_Pos (1UL) /*!< Position of CH1 field. */ #define PPI_CHENCLR_CH1_Msk (0x1UL << PPI_CHENCLR_CH1_Pos) /*!< Bit mask of CH1 field. */ #define PPI_CHENCLR_CH1_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENCLR_CH1_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENCLR_CH1_Clear (1UL) /*!< Write: disable channel */ -/* Bit 0 : Channel 0 enable clear register. Writing '0' has no effect */ +/* Bit 0 : Channel 0 enable clear register. Writing '0' has no effect. */ #define PPI_CHENCLR_CH0_Pos (0UL) /*!< Position of CH0 field. */ #define PPI_CHENCLR_CH0_Msk (0x1UL << PPI_CHENCLR_CH0_Pos) /*!< Bit mask of CH0 field. */ #define PPI_CHENCLR_CH0_Disabled (0UL) /*!< Read: channel disabled */ @@ -4766,14 +4791,14 @@ POSSIBILITY OF SUCH DAMAGE. #define PPI_CHENCLR_CH0_Clear (1UL) /*!< Write: disable channel */ /* Register: PPI_CH_EEP */ -/* Description: Description cluster: Channel n event end-point */ +/* Description: Description cluster: Channel n event endpoint */ /* Bits 31..0 : Pointer to event register. Accepts only addresses to registers from the Event group. */ #define PPI_CH_EEP_EEP_Pos (0UL) /*!< Position of EEP field. */ #define PPI_CH_EEP_EEP_Msk (0xFFFFFFFFUL << PPI_CH_EEP_EEP_Pos) /*!< Bit mask of EEP field. */ /* Register: PPI_CH_TEP */ -/* Description: Description cluster: Channel n task end-point */ +/* Description: Description cluster: Channel n task endpoint */ /* Bits 31..0 : Pointer to task register. Accepts only addresses to registers from the Task group. */ #define PPI_CH_TEP_TEP_Pos (0UL) /*!< Position of TEP field. */ @@ -4975,7 +5000,7 @@ POSSIBILITY OF SUCH DAMAGE. #define PPI_CHG_CH0_Included (1UL) /*!< Include */ /* Register: PPI_FORK_TEP */ -/* Description: Description cluster: Channel n task end-point */ +/* Description: Description cluster: Channel n task endpoint */ /* Bits 31..0 : Pointer to task register */ #define PPI_FORK_TEP_TEP_Pos (0UL) /*!< Position of TEP field. */ @@ -5237,23 +5262,23 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: QDEC_REPORTPER */ /* Description: Number of samples to be taken before REPORTRDY and DBLRDY events can be generated */ -/* Bits 3..0 : Specifies the number of samples to be accumulated in the ACC register before the REPORTRDY and DBLRDY events can be generated */ +/* Bits 3..0 : Specifies the number of samples to be accumulated in the ACC register before the REPORTRDY and DBLRDY events can be generated. */ #define QDEC_REPORTPER_REPORTPER_Pos (0UL) /*!< Position of REPORTPER field. */ #define QDEC_REPORTPER_REPORTPER_Msk (0xFUL << QDEC_REPORTPER_REPORTPER_Pos) /*!< Bit mask of REPORTPER field. */ -#define QDEC_REPORTPER_REPORTPER_10Smpl (0UL) /*!< 10 samples / report */ -#define QDEC_REPORTPER_REPORTPER_40Smpl (1UL) /*!< 40 samples / report */ -#define QDEC_REPORTPER_REPORTPER_80Smpl (2UL) /*!< 80 samples / report */ -#define QDEC_REPORTPER_REPORTPER_120Smpl (3UL) /*!< 120 samples / report */ -#define QDEC_REPORTPER_REPORTPER_160Smpl (4UL) /*!< 160 samples / report */ -#define QDEC_REPORTPER_REPORTPER_200Smpl (5UL) /*!< 200 samples / report */ -#define QDEC_REPORTPER_REPORTPER_240Smpl (6UL) /*!< 240 samples / report */ -#define QDEC_REPORTPER_REPORTPER_280Smpl (7UL) /*!< 280 samples / report */ -#define QDEC_REPORTPER_REPORTPER_1Smpl (8UL) /*!< 1 sample / report */ +#define QDEC_REPORTPER_REPORTPER_10Smpl (0UL) /*!< 10 samples/report */ +#define QDEC_REPORTPER_REPORTPER_40Smpl (1UL) /*!< 40 samples/report */ +#define QDEC_REPORTPER_REPORTPER_80Smpl (2UL) /*!< 80 samples/report */ +#define QDEC_REPORTPER_REPORTPER_120Smpl (3UL) /*!< 120 samples/report */ +#define QDEC_REPORTPER_REPORTPER_160Smpl (4UL) /*!< 160 samples/report */ +#define QDEC_REPORTPER_REPORTPER_200Smpl (5UL) /*!< 200 samples/report */ +#define QDEC_REPORTPER_REPORTPER_240Smpl (6UL) /*!< 240 samples/report */ +#define QDEC_REPORTPER_REPORTPER_280Smpl (7UL) /*!< 280 samples/report */ +#define QDEC_REPORTPER_REPORTPER_1Smpl (8UL) /*!< 1 sample/report */ /* Register: QDEC_ACC */ /* Description: Register accumulating the valid transitions */ -/* Bits 31..0 : Register accumulating all valid samples (not double transition) read from the SAMPLE register */ +/* Bits 31..0 : Register accumulating all valid samples (not double transition) read from the SAMPLE register. */ #define QDEC_ACC_ACC_Pos (0UL) /*!< Position of ACC field. */ #define QDEC_ACC_ACC_Msk (0xFFFFFFFFUL << QDEC_ACC_ACC_Pos) /*!< Bit mask of ACC field. */ @@ -5550,9 +5575,9 @@ POSSIBILITY OF SUCH DAMAGE. #define RADIO_EVENTS_FRAMESTART_EVENTS_FRAMESTART_Generated (1UL) /*!< Event generated */ /* Register: RADIO_EVENTS_EDEND */ -/* Description: Sampling of energy detection complete. A new ED sample is ready for readout from the RADIO.EDSAMPLE register */ +/* Description: Sampling of energy detection complete. A new ED sample is ready for readout from the RADIO.EDSAMPLE register. */ -/* Bit 0 : Sampling of energy detection complete. A new ED sample is ready for readout from the RADIO.EDSAMPLE register */ +/* Bit 0 : Sampling of energy detection complete. A new ED sample is ready for readout from the RADIO.EDSAMPLE register. */ #define RADIO_EVENTS_EDEND_EVENTS_EDEND_Pos (0UL) /*!< Position of EVENTS_EDEND field. */ #define RADIO_EVENTS_EDEND_EVENTS_EDEND_Msk (0x1UL << RADIO_EVENTS_EDEND_EVENTS_EDEND_Pos) /*!< Bit mask of EVENTS_EDEND field. */ #define RADIO_EVENTS_EDEND_EVENTS_EDEND_NotGenerated (0UL) /*!< Event not generated */ @@ -6205,7 +6230,7 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: RADIO_FREQUENCY */ /* Description: Frequency */ -/* Bit 8 : Channel map selection. */ +/* Bit 8 : Channel map selection */ #define RADIO_FREQUENCY_MAP_Pos (8UL) /*!< Position of MAP field. */ #define RADIO_FREQUENCY_MAP_Msk (0x1UL << RADIO_FREQUENCY_MAP_Pos) /*!< Bit mask of MAP field. */ #define RADIO_FREQUENCY_MAP_Default (0UL) /*!< Channel map between 2400 MHZ .. 2500 MHz */ @@ -6282,15 +6307,15 @@ POSSIBILITY OF SUCH DAMAGE. #define RADIO_PCNF0_S1INCL_Automatic (0UL) /*!< Include S1 field in RAM only if S1LEN > 0 */ #define RADIO_PCNF0_S1INCL_Include (1UL) /*!< Always include S1 field in RAM independent of S1LEN */ -/* Bits 19..16 : Length on air of S1 field in number of bits. */ +/* Bits 19..16 : Length on air of S1 field in number of bits */ #define RADIO_PCNF0_S1LEN_Pos (16UL) /*!< Position of S1LEN field. */ #define RADIO_PCNF0_S1LEN_Msk (0xFUL << RADIO_PCNF0_S1LEN_Pos) /*!< Bit mask of S1LEN field. */ -/* Bit 8 : Length on air of S0 field in number of bytes. */ +/* Bit 8 : Length on air of S0 field in number of bytes */ #define RADIO_PCNF0_S0LEN_Pos (8UL) /*!< Position of S0LEN field. */ #define RADIO_PCNF0_S0LEN_Msk (0x1UL << RADIO_PCNF0_S0LEN_Pos) /*!< Bit mask of S0LEN field. */ -/* Bits 3..0 : Length on air of LENGTH field in number of bits. */ +/* Bits 3..0 : Length on air of LENGTH field in number of bits */ #define RADIO_PCNF0_LFLEN_Pos (0UL) /*!< Position of LFLEN field. */ #define RADIO_PCNF0_LFLEN_Msk (0xFUL << RADIO_PCNF0_LFLEN_Pos) /*!< Bit mask of LFLEN field. */ @@ -6441,7 +6466,7 @@ POSSIBILITY OF SUCH DAMAGE. #define RADIO_CRCCNF_SKIPADDR_Skip (1UL) /*!< CRC calculation does not include address field. The CRC calculation will start at the first byte after the address. */ #define RADIO_CRCCNF_SKIPADDR_Ieee802154 (2UL) /*!< CRC calculation as per 802.15.4 standard. Starting at first byte after length field. */ -/* Bits 1..0 : CRC length in number of bytes. */ +/* Bits 1..0 : CRC length in number of bytes For MODE Ble_LR125Kbit and Ble_LR500Kbit, only LEN set to 3 is supported */ #define RADIO_CRCCNF_LEN_Pos (0UL) /*!< Position of LEN field. */ #define RADIO_CRCCNF_LEN_Msk (0x3UL << RADIO_CRCCNF_LEN_Pos) /*!< Bit mask of LEN field. */ #define RADIO_CRCCNF_LEN_Disabled (0UL) /*!< CRC length is zero and CRC calculation is disabled */ @@ -6466,14 +6491,14 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: RADIO_TIFS */ /* Description: Interframe spacing in us */ -/* Bits 9..0 : Interframe spacing in us */ +/* Bits 9..0 : Interframe spacing in us. */ #define RADIO_TIFS_TIFS_Pos (0UL) /*!< Position of TIFS field. */ #define RADIO_TIFS_TIFS_Msk (0x3FFUL << RADIO_TIFS_TIFS_Pos) /*!< Bit mask of TIFS field. */ /* Register: RADIO_RSSISAMPLE */ /* Description: RSSI sample */ -/* Bits 6..0 : RSSI sample */ +/* Bits 6..0 : RSSI sample. */ #define RADIO_RSSISAMPLE_RSSISAMPLE_Pos (0UL) /*!< Position of RSSISAMPLE field. */ #define RADIO_RSSISAMPLE_RSSISAMPLE_Msk (0x7FUL << RADIO_RSSISAMPLE_RSSISAMPLE_Pos) /*!< Bit mask of RSSISAMPLE field. */ @@ -6632,7 +6657,7 @@ POSSIBILITY OF SUCH DAMAGE. #define RADIO_MODECNF0_RU_Pos (0UL) /*!< Position of RU field. */ #define RADIO_MODECNF0_RU_Msk (0x1UL << RADIO_MODECNF0_RU_Pos) /*!< Bit mask of RU field. */ #define RADIO_MODECNF0_RU_Default (0UL) /*!< Default ramp-up time (tRXEN and tTXEN), compatible with firmware written for nRF51 */ -#define RADIO_MODECNF0_RU_Fast (1UL) /*!< Fast ramp-up (tRXEN,FAST and tTXEN,FAST), see electrical specification for more information */ +#define RADIO_MODECNF0_RU_Fast (1UL) /*!< Fast ramp-up (tRXEN,FAST and tTXEN,FAST), see electrical specifications for more information */ /* Register: RADIO_SFD */ /* Description: IEEE 802.15.4 start of frame delimiter */ @@ -6700,32 +6725,32 @@ POSSIBILITY OF SUCH DAMAGE. #define RADIO_CTEINLINECONF_S0CONF_Pos (16UL) /*!< Position of S0CONF field. */ #define RADIO_CTEINLINECONF_S0CONF_Msk (0xFFUL << RADIO_CTEINLINECONF_S0CONF_Pos) /*!< Bit mask of S0CONF field. */ -/* Bits 15..13 : Spacing between samples for the samples in the SWITCHING period when CTEINLINEMODE is set */ +/* Bits 15..13 : Spacing between samples for the samples in the SWITCHING period when CTEINLINEMODE is set. */ #define RADIO_CTEINLINECONF_CTEINLINERXMODE2US_Pos (13UL) /*!< Position of CTEINLINERXMODE2US field. */ #define RADIO_CTEINLINECONF_CTEINLINERXMODE2US_Msk (0x7UL << RADIO_CTEINLINECONF_CTEINLINERXMODE2US_Pos) /*!< Bit mask of CTEINLINERXMODE2US field. */ -#define RADIO_CTEINLINECONF_CTEINLINERXMODE2US_4us (1UL) /*!< 4us */ -#define RADIO_CTEINLINECONF_CTEINLINERXMODE2US_2us (2UL) /*!< 2us */ -#define RADIO_CTEINLINECONF_CTEINLINERXMODE2US_1us (3UL) /*!< 1us */ -#define RADIO_CTEINLINECONF_CTEINLINERXMODE2US_500ns (4UL) /*!< 0.5us */ -#define RADIO_CTEINLINECONF_CTEINLINERXMODE2US_250ns (5UL) /*!< 0.25us */ -#define RADIO_CTEINLINECONF_CTEINLINERXMODE2US_125ns (6UL) /*!< 0.125us */ - -/* Bits 12..10 : Spacing between samples for the samples in the SWITCHING period when CTEINLINEMODE is set */ +#define RADIO_CTEINLINECONF_CTEINLINERXMODE2US_4us (1UL) /*!< 4 us */ +#define RADIO_CTEINLINECONF_CTEINLINERXMODE2US_2us (2UL) /*!< 2 us */ +#define RADIO_CTEINLINECONF_CTEINLINERXMODE2US_1us (3UL) /*!< 1 us */ +#define RADIO_CTEINLINECONF_CTEINLINERXMODE2US_500ns (4UL) /*!< 0.5 us */ +#define RADIO_CTEINLINECONF_CTEINLINERXMODE2US_250ns (5UL) /*!< 0.25 us */ +#define RADIO_CTEINLINECONF_CTEINLINERXMODE2US_125ns (6UL) /*!< 0.125 us */ + +/* Bits 12..10 : Spacing between samples for the samples in the SWITCHING period when CTEINLINEMODE is set. */ #define RADIO_CTEINLINECONF_CTEINLINERXMODE1US_Pos (10UL) /*!< Position of CTEINLINERXMODE1US field. */ #define RADIO_CTEINLINECONF_CTEINLINERXMODE1US_Msk (0x7UL << RADIO_CTEINLINECONF_CTEINLINERXMODE1US_Pos) /*!< Bit mask of CTEINLINERXMODE1US field. */ -#define RADIO_CTEINLINECONF_CTEINLINERXMODE1US_4us (1UL) /*!< 4us */ -#define RADIO_CTEINLINECONF_CTEINLINERXMODE1US_2us (2UL) /*!< 2us */ -#define RADIO_CTEINLINECONF_CTEINLINERXMODE1US_1us (3UL) /*!< 1us */ -#define RADIO_CTEINLINECONF_CTEINLINERXMODE1US_500ns (4UL) /*!< 0.5us */ -#define RADIO_CTEINLINECONF_CTEINLINERXMODE1US_250ns (5UL) /*!< 0.25us */ -#define RADIO_CTEINLINECONF_CTEINLINERXMODE1US_125ns (6UL) /*!< 0.125us */ +#define RADIO_CTEINLINECONF_CTEINLINERXMODE1US_4us (1UL) /*!< 4 us */ +#define RADIO_CTEINLINECONF_CTEINLINERXMODE1US_2us (2UL) /*!< 2 us */ +#define RADIO_CTEINLINECONF_CTEINLINERXMODE1US_1us (3UL) /*!< 1 us */ +#define RADIO_CTEINLINECONF_CTEINLINERXMODE1US_500ns (4UL) /*!< 0.5 us */ +#define RADIO_CTEINLINECONF_CTEINLINERXMODE1US_250ns (5UL) /*!< 0.25 us */ +#define RADIO_CTEINLINECONF_CTEINLINERXMODE1US_125ns (6UL) /*!< 0.125 us */ /* Bits 7..6 : Max range of CTETime */ #define RADIO_CTEINLINECONF_CTETIMEVALIDRANGE_Pos (6UL) /*!< Position of CTETIMEVALIDRANGE field. */ #define RADIO_CTEINLINECONF_CTETIMEVALIDRANGE_Msk (0x3UL << RADIO_CTEINLINECONF_CTETIMEVALIDRANGE_Pos) /*!< Bit mask of CTETIMEVALIDRANGE field. */ -#define RADIO_CTEINLINECONF_CTETIMEVALIDRANGE_20 (0UL) /*!< 20 in 8us unit (default) Set to 20 if parsed CTETime is larger han 20 */ -#define RADIO_CTEINLINECONF_CTETIMEVALIDRANGE_31 (1UL) /*!< 31 in 8us unit */ -#define RADIO_CTEINLINECONF_CTETIMEVALIDRANGE_63 (2UL) /*!< 63 in 8us unit */ +#define RADIO_CTEINLINECONF_CTETIMEVALIDRANGE_20 (0UL) /*!< 20 in 8 us unit (default) Set to 20 if parsed CTETime is larger than 20 */ +#define RADIO_CTEINLINECONF_CTETIMEVALIDRANGE_31 (1UL) /*!< 31 in 8 us unit */ +#define RADIO_CTEINLINECONF_CTETIMEVALIDRANGE_63 (2UL) /*!< 63 in 8 us unit */ /* Bit 4 : Sampling/switching if CRC is not OK */ #define RADIO_CTEINLINECONF_CTEERRORHANDLING_Pos (4UL) /*!< Position of CTEERRORHANDLING field. */ @@ -6760,12 +6785,12 @@ POSSIBILITY OF SUCH DAMAGE. /* Bits 18..16 : Interval between samples in the SWITCHING period when CTEINLINECTRLEN is 0 */ #define RADIO_DFECTRL1_TSAMPLESPACING_Pos (16UL) /*!< Position of TSAMPLESPACING field. */ #define RADIO_DFECTRL1_TSAMPLESPACING_Msk (0x7UL << RADIO_DFECTRL1_TSAMPLESPACING_Pos) /*!< Bit mask of TSAMPLESPACING field. */ -#define RADIO_DFECTRL1_TSAMPLESPACING_4us (1UL) /*!< 4us */ -#define RADIO_DFECTRL1_TSAMPLESPACING_2us (2UL) /*!< 2us */ -#define RADIO_DFECTRL1_TSAMPLESPACING_1us (3UL) /*!< 1us */ -#define RADIO_DFECTRL1_TSAMPLESPACING_500ns (4UL) /*!< 0.5us */ -#define RADIO_DFECTRL1_TSAMPLESPACING_250ns (5UL) /*!< 0.25us */ -#define RADIO_DFECTRL1_TSAMPLESPACING_125ns (6UL) /*!< 0.125us */ +#define RADIO_DFECTRL1_TSAMPLESPACING_4us (1UL) /*!< 4 us */ +#define RADIO_DFECTRL1_TSAMPLESPACING_2us (2UL) /*!< 2 us */ +#define RADIO_DFECTRL1_TSAMPLESPACING_1us (3UL) /*!< 1 us */ +#define RADIO_DFECTRL1_TSAMPLESPACING_500ns (4UL) /*!< 0.5 us */ +#define RADIO_DFECTRL1_TSAMPLESPACING_250ns (5UL) /*!< 0.25 us */ +#define RADIO_DFECTRL1_TSAMPLESPACING_125ns (6UL) /*!< 0.125 us */ /* Bit 15 : Whether to sample I/Q or magnitude/phase */ #define RADIO_DFECTRL1_SAMPLETYPE_Pos (15UL) /*!< Position of SAMPLETYPE field. */ @@ -6776,19 +6801,19 @@ POSSIBILITY OF SUCH DAMAGE. /* Bits 14..12 : Interval between samples in the REFERENCE period */ #define RADIO_DFECTRL1_TSAMPLESPACINGREF_Pos (12UL) /*!< Position of TSAMPLESPACINGREF field. */ #define RADIO_DFECTRL1_TSAMPLESPACINGREF_Msk (0x7UL << RADIO_DFECTRL1_TSAMPLESPACINGREF_Pos) /*!< Bit mask of TSAMPLESPACINGREF field. */ -#define RADIO_DFECTRL1_TSAMPLESPACINGREF_4us (1UL) /*!< 4us */ -#define RADIO_DFECTRL1_TSAMPLESPACINGREF_2us (2UL) /*!< 2us */ -#define RADIO_DFECTRL1_TSAMPLESPACINGREF_1us (3UL) /*!< 1us */ -#define RADIO_DFECTRL1_TSAMPLESPACINGREF_500ns (4UL) /*!< 0.5us */ -#define RADIO_DFECTRL1_TSAMPLESPACINGREF_250ns (5UL) /*!< 0.25us */ -#define RADIO_DFECTRL1_TSAMPLESPACINGREF_125ns (6UL) /*!< 0.125us */ +#define RADIO_DFECTRL1_TSAMPLESPACINGREF_4us (1UL) /*!< 4 us */ +#define RADIO_DFECTRL1_TSAMPLESPACINGREF_2us (2UL) /*!< 2 us */ +#define RADIO_DFECTRL1_TSAMPLESPACINGREF_1us (3UL) /*!< 1 us */ +#define RADIO_DFECTRL1_TSAMPLESPACINGREF_500ns (4UL) /*!< 0.5 us */ +#define RADIO_DFECTRL1_TSAMPLESPACINGREF_250ns (5UL) /*!< 0.25 us */ +#define RADIO_DFECTRL1_TSAMPLESPACINGREF_125ns (6UL) /*!< 0.125 us */ /* Bits 10..8 : Interval between every time the antenna is changed in the SWITCHING state */ #define RADIO_DFECTRL1_TSWITCHSPACING_Pos (8UL) /*!< Position of TSWITCHSPACING field. */ #define RADIO_DFECTRL1_TSWITCHSPACING_Msk (0x7UL << RADIO_DFECTRL1_TSWITCHSPACING_Pos) /*!< Bit mask of TSWITCHSPACING field. */ -#define RADIO_DFECTRL1_TSWITCHSPACING_4us (1UL) /*!< 4us */ -#define RADIO_DFECTRL1_TSWITCHSPACING_2us (2UL) /*!< 2us */ -#define RADIO_DFECTRL1_TSWITCHSPACING_1us (3UL) /*!< 1us */ +#define RADIO_DFECTRL1_TSWITCHSPACING_4us (1UL) /*!< 4 us */ +#define RADIO_DFECTRL1_TSWITCHSPACING_2us (2UL) /*!< 2 us */ +#define RADIO_DFECTRL1_TSWITCHSPACING_1us (3UL) /*!< 1 us */ /* Bit 7 : Add CTE extension and do antenna switching/sampling in this extension */ #define RADIO_DFECTRL1_DFEINEXTENSION_Pos (7UL) /*!< Position of DFEINEXTENSION field. */ @@ -6814,7 +6839,7 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: RADIO_SWITCHPATTERN */ /* Description: GPIO patterns to be used for each antenna */ -/* Bits 7..0 : Fill array of GPIO patterns for antenna control */ +/* Bits 7..0 : Fill array of GPIO patterns for antenna control. */ #define RADIO_SWITCHPATTERN_SWITCHPATTERN_Pos (0UL) /*!< Position of SWITCHPATTERN field. */ #define RADIO_SWITCHPATTERN_SWITCHPATTERN_Msk (0xFFUL << RADIO_SWITCHPATTERN_SWITCHPATTERN_Pos) /*!< Bit mask of SWITCHPATTERN field. */ @@ -7233,7 +7258,7 @@ POSSIBILITY OF SUCH DAMAGE. #define RTC_COUNTER_COUNTER_Msk (0xFFFFFFUL << RTC_COUNTER_COUNTER_Pos) /*!< Bit mask of COUNTER field. */ /* Register: RTC_PRESCALER */ -/* Description: 12 bit prescaler for COUNTER frequency (32768/(PRESCALER+1)).Must be written when RTC is stopped */ +/* Description: 12 bit prescaler for COUNTER frequency (32768/(PRESCALER+1)). Must be written when RTC is stopped. */ /* Bits 11..0 : Prescaler value */ #define RTC_PRESCALER_PRESCALER_Pos (0UL) /*!< Position of PRESCALER field. */ @@ -7337,7 +7362,7 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: SPI_TXD */ /* Description: TXD register */ -/* Bits 7..0 : TX data to send. Double buffered */ +/* Bits 7..0 : TX data to send. Double buffered. */ #define SPI_TXD_TXD_Pos (0UL) /*!< Position of TXD field. */ #define SPI_TXD_TXD_Msk (0xFFUL << SPI_TXD_TXD_Pos) /*!< Bit mask of TXD field. */ @@ -8037,121 +8062,121 @@ POSSIBILITY OF SUCH DAMAGE. #define TEMP_TEMP_TEMP_Msk (0xFFFFFFFFUL << TEMP_TEMP_TEMP_Pos) /*!< Bit mask of TEMP field. */ /* Register: TEMP_A0 */ -/* Description: Slope of 1st piece wise linear function */ +/* Description: Slope of first piecewise linear function */ -/* Bits 11..0 : Slope of 1st piece wise linear function */ +/* Bits 11..0 : Slope of first piecewise linear function */ #define TEMP_A0_A0_Pos (0UL) /*!< Position of A0 field. */ #define TEMP_A0_A0_Msk (0xFFFUL << TEMP_A0_A0_Pos) /*!< Bit mask of A0 field. */ /* Register: TEMP_A1 */ -/* Description: Slope of 2nd piece wise linear function */ +/* Description: Slope of second piecewise linear function */ -/* Bits 11..0 : Slope of 2nd piece wise linear function */ +/* Bits 11..0 : Slope of second piecewise linear function */ #define TEMP_A1_A1_Pos (0UL) /*!< Position of A1 field. */ #define TEMP_A1_A1_Msk (0xFFFUL << TEMP_A1_A1_Pos) /*!< Bit mask of A1 field. */ /* Register: TEMP_A2 */ -/* Description: Slope of 3rd piece wise linear function */ +/* Description: Slope of third piecewise linear function */ -/* Bits 11..0 : Slope of 3rd piece wise linear function */ +/* Bits 11..0 : Slope of third piecewise linear function */ #define TEMP_A2_A2_Pos (0UL) /*!< Position of A2 field. */ #define TEMP_A2_A2_Msk (0xFFFUL << TEMP_A2_A2_Pos) /*!< Bit mask of A2 field. */ /* Register: TEMP_A3 */ -/* Description: Slope of 4th piece wise linear function */ +/* Description: Slope of fourth piecewise linear function */ -/* Bits 11..0 : Slope of 4th piece wise linear function */ +/* Bits 11..0 : Slope of fourth piecewise linear function */ #define TEMP_A3_A3_Pos (0UL) /*!< Position of A3 field. */ #define TEMP_A3_A3_Msk (0xFFFUL << TEMP_A3_A3_Pos) /*!< Bit mask of A3 field. */ /* Register: TEMP_A4 */ -/* Description: Slope of 5th piece wise linear function */ +/* Description: Slope of fifth piecewise linear function */ -/* Bits 11..0 : Slope of 5th piece wise linear function */ +/* Bits 11..0 : Slope of fifth piecewise linear function */ #define TEMP_A4_A4_Pos (0UL) /*!< Position of A4 field. */ #define TEMP_A4_A4_Msk (0xFFFUL << TEMP_A4_A4_Pos) /*!< Bit mask of A4 field. */ /* Register: TEMP_A5 */ -/* Description: Slope of 6th piece wise linear function */ +/* Description: Slope of sixth piecewise linear function */ -/* Bits 11..0 : Slope of 6th piece wise linear function */ +/* Bits 11..0 : Slope of sixth piecewise linear function */ #define TEMP_A5_A5_Pos (0UL) /*!< Position of A5 field. */ #define TEMP_A5_A5_Msk (0xFFFUL << TEMP_A5_A5_Pos) /*!< Bit mask of A5 field. */ /* Register: TEMP_B0 */ -/* Description: y-intercept of 1st piece wise linear function */ +/* Description: y-intercept of first piecewise linear function */ -/* Bits 13..0 : y-intercept of 1st piece wise linear function */ +/* Bits 13..0 : y-intercept of first piecewise linear function */ #define TEMP_B0_B0_Pos (0UL) /*!< Position of B0 field. */ #define TEMP_B0_B0_Msk (0x3FFFUL << TEMP_B0_B0_Pos) /*!< Bit mask of B0 field. */ /* Register: TEMP_B1 */ -/* Description: y-intercept of 2nd piece wise linear function */ +/* Description: y-intercept of second piecewise linear function */ -/* Bits 13..0 : y-intercept of 2nd piece wise linear function */ +/* Bits 13..0 : y-intercept of second piecewise linear function */ #define TEMP_B1_B1_Pos (0UL) /*!< Position of B1 field. */ #define TEMP_B1_B1_Msk (0x3FFFUL << TEMP_B1_B1_Pos) /*!< Bit mask of B1 field. */ /* Register: TEMP_B2 */ -/* Description: y-intercept of 3rd piece wise linear function */ +/* Description: y-intercept of third piecewise linear function */ -/* Bits 13..0 : y-intercept of 3rd piece wise linear function */ +/* Bits 13..0 : y-intercept of third piecewise linear function */ #define TEMP_B2_B2_Pos (0UL) /*!< Position of B2 field. */ #define TEMP_B2_B2_Msk (0x3FFFUL << TEMP_B2_B2_Pos) /*!< Bit mask of B2 field. */ /* Register: TEMP_B3 */ -/* Description: y-intercept of 4th piece wise linear function */ +/* Description: y-intercept of fourth piecewise linear function */ -/* Bits 13..0 : y-intercept of 4th piece wise linear function */ +/* Bits 13..0 : y-intercept of fourth piecewise linear function */ #define TEMP_B3_B3_Pos (0UL) /*!< Position of B3 field. */ #define TEMP_B3_B3_Msk (0x3FFFUL << TEMP_B3_B3_Pos) /*!< Bit mask of B3 field. */ /* Register: TEMP_B4 */ -/* Description: y-intercept of 5th piece wise linear function */ +/* Description: y-intercept of fifth piecewise linear function */ -/* Bits 13..0 : y-intercept of 5th piece wise linear function */ +/* Bits 13..0 : y-intercept of fifth piecewise linear function */ #define TEMP_B4_B4_Pos (0UL) /*!< Position of B4 field. */ #define TEMP_B4_B4_Msk (0x3FFFUL << TEMP_B4_B4_Pos) /*!< Bit mask of B4 field. */ /* Register: TEMP_B5 */ -/* Description: y-intercept of 6th piece wise linear function */ +/* Description: y-intercept of sixth piecewise linear function */ -/* Bits 13..0 : y-intercept of 6th piece wise linear function */ +/* Bits 13..0 : y-intercept of sixth piecewise linear function */ #define TEMP_B5_B5_Pos (0UL) /*!< Position of B5 field. */ #define TEMP_B5_B5_Msk (0x3FFFUL << TEMP_B5_B5_Pos) /*!< Bit mask of B5 field. */ /* Register: TEMP_T0 */ -/* Description: End point of 1st piece wise linear function */ +/* Description: End point of first piecewise linear function */ -/* Bits 7..0 : End point of 1st piece wise linear function */ +/* Bits 7..0 : End point of first piecewise linear function */ #define TEMP_T0_T0_Pos (0UL) /*!< Position of T0 field. */ #define TEMP_T0_T0_Msk (0xFFUL << TEMP_T0_T0_Pos) /*!< Bit mask of T0 field. */ /* Register: TEMP_T1 */ -/* Description: End point of 2nd piece wise linear function */ +/* Description: End point of second piecewise linear function */ -/* Bits 7..0 : End point of 2nd piece wise linear function */ +/* Bits 7..0 : End point of second piecewise linear function */ #define TEMP_T1_T1_Pos (0UL) /*!< Position of T1 field. */ #define TEMP_T1_T1_Msk (0xFFUL << TEMP_T1_T1_Pos) /*!< Bit mask of T1 field. */ /* Register: TEMP_T2 */ -/* Description: End point of 3rd piece wise linear function */ +/* Description: End point of third piecewise linear function */ -/* Bits 7..0 : End point of 3rd piece wise linear function */ +/* Bits 7..0 : End point of third piecewise linear function */ #define TEMP_T2_T2_Pos (0UL) /*!< Position of T2 field. */ #define TEMP_T2_T2_Msk (0xFFUL << TEMP_T2_T2_Pos) /*!< Bit mask of T2 field. */ /* Register: TEMP_T3 */ -/* Description: End point of 4th piece wise linear function */ +/* Description: End point of fourth piecewise linear function */ -/* Bits 7..0 : End point of 4th piece wise linear function */ +/* Bits 7..0 : End point of fourth piecewise linear function */ #define TEMP_T3_T3_Pos (0UL) /*!< Position of T3 field. */ #define TEMP_T3_T3_Msk (0xFFUL << TEMP_T3_T3_Pos) /*!< Bit mask of T3 field. */ /* Register: TEMP_T4 */ -/* Description: End point of 5th piece wise linear function */ +/* Description: End point of fifth piecewise linear function */ -/* Bits 7..0 : End point of 5th piece wise linear function */ +/* Bits 7..0 : End point of fifth piecewise linear function */ #define TEMP_T4_T4_Pos (0UL) /*!< Position of T4 field. */ #define TEMP_T4_T4_Msk (0xFFUL << TEMP_T4_T4_Pos) /*!< Bit mask of T4 field. */ @@ -8769,9 +8794,9 @@ POSSIBILITY OF SUCH DAMAGE. #define TWIM_EVENTS_ERROR_EVENTS_ERROR_Generated (1UL) /*!< Event generated */ /* Register: TWIM_EVENTS_SUSPENDED */ -/* Description: Last byte has been sent out after the SUSPEND task has been issued, TWI traffic is now suspended. */ +/* Description: SUSPEND task has been issued, TWI traffic is now suspended. */ -/* Bit 0 : Last byte has been sent out after the SUSPEND task has been issued, TWI traffic is now suspended. */ +/* Bit 0 : SUSPEND task has been issued, TWI traffic is now suspended. */ #define TWIM_EVENTS_SUSPENDED_EVENTS_SUSPENDED_Pos (0UL) /*!< Position of EVENTS_SUSPENDED field. */ #define TWIM_EVENTS_SUSPENDED_EVENTS_SUSPENDED_Msk (0x1UL << TWIM_EVENTS_SUSPENDED_EVENTS_SUSPENDED_Pos) /*!< Bit mask of EVENTS_SUSPENDED field. */ #define TWIM_EVENTS_SUSPENDED_EVENTS_SUSPENDED_NotGenerated (0UL) /*!< Event not generated */ @@ -9400,7 +9425,7 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: TWIS_MATCH */ /* Description: Status register indicating which address had a match */ -/* Bit 0 : Which of the addresses in {ADDRESS} matched the incoming address */ +/* Bit 0 : Indication of which address in {ADDRESS} that matched the incoming address */ #define TWIS_MATCH_MATCH_Pos (0UL) /*!< Position of MATCH field. */ #define TWIS_MATCH_MATCH_Msk (0x1UL << TWIS_MATCH_MATCH_Pos) /*!< Bit mask of MATCH field. */ @@ -10273,7 +10298,7 @@ POSSIBILITY OF SUCH DAMAGE. #define UARTE_INTENCLR_CTS_Clear (1UL) /*!< Disable */ /* Register: UARTE_ERRORSRC */ -/* Description: Error source Note : this register is read / write one to clear. */ +/* Description: Error source This register is read/write one to clear. */ /* Bit 3 : Break condition */ #define UARTE_ERRORSRC_BREAK_Pos (3UL) /*!< Position of BREAK field. */ @@ -10383,7 +10408,7 @@ POSSIBILITY OF SUCH DAMAGE. #define UARTE_BAUDRATE_BAUDRATE_Baud250000 (0x04000000UL) /*!< 250000 baud */ #define UARTE_BAUDRATE_BAUDRATE_Baud460800 (0x07400000UL) /*!< 460800 baud (actual rate: 457143) */ #define UARTE_BAUDRATE_BAUDRATE_Baud921600 (0x0F000000UL) /*!< 921600 baud (actual rate: 941176) */ -#define UARTE_BAUDRATE_BAUDRATE_Baud1M (0x10000000UL) /*!< 1Mega baud */ +#define UARTE_BAUDRATE_BAUDRATE_Baud1M (0x10000000UL) /*!< 1 megabaud */ /* Register: UARTE_RXD_PTR */ /* Description: Data pointer */ @@ -10499,7 +10524,8 @@ POSSIBILITY OF SUCH DAMAGE. #define UICR_APPROTECT_PALL_Pos (0UL) /*!< Position of PALL field. */ #define UICR_APPROTECT_PALL_Msk (0xFFUL << UICR_APPROTECT_PALL_Pos) /*!< Bit mask of PALL field. */ #define UICR_APPROTECT_PALL_Enabled (0x00UL) /*!< Enable */ -#define UICR_APPROTECT_PALL_Disabled (0xFFUL) /*!< Disable */ +#define UICR_APPROTECT_PALL_HwDisabled (0x5AUL) /*!< Hardware disable of access port protection for devices where access port protection is controlled by hardware and software */ +#define UICR_APPROTECT_PALL_Disabled (0xFFUL) /*!< Hardware disable of access port protection for devices where access port protection is controlled by hardware */ /* Register: UICR_DEBUGCTRL */ /* Description: Processor debug control */ @@ -10511,7 +10537,7 @@ POSSIBILITY OF SUCH DAMAGE. #define UICR_DEBUGCTRL_CPUFPBEN_Enabled (0xFFUL) /*!< Enable CPU FPB unit (default behavior) */ /* Register: UICR_REGOUT0 */ -/* Description: Output voltage from REG0 regulator stage. The maximum output voltage from this stage is given as VDDH - VREG0DROP. */ +/* Description: Output voltage from REG0 regulator stage. The maximum output voltage from this stage is given as VDDH - V_VDDH-VDD. */ /* Bits 2..0 : Output voltage from REG0 regulator stage. */ #define UICR_REGOUT0_VOUT_Pos (0UL) /*!< Position of VOUT field. */ @@ -11788,7 +11814,7 @@ POSSIBILITY OF SUCH DAMAGE. /* Bits 15..0 : Controls the split of ISO buffers */ #define USBD_ISOSPLIT_SPLIT_Pos (0UL) /*!< Position of SPLIT field. */ #define USBD_ISOSPLIT_SPLIT_Msk (0xFFFFUL << USBD_ISOSPLIT_SPLIT_Pos) /*!< Bit mask of SPLIT field. */ -#define USBD_ISOSPLIT_SPLIT_OneDir (0x0000UL) /*!< Full buffer dedicated to either iso IN or OUT */ +#define USBD_ISOSPLIT_SPLIT_OneDir (0x0000UL) /*!< Full buffer dedicated to either ISO IN or OUT */ #define USBD_ISOSPLIT_SPLIT_HalfIN (0x0080UL) /*!< Lower half for IN, upper half for OUT */ /* Register: USBD_FRAMECNTR */ diff --git a/mdk/nrf52820_peripherals.h b/mdk/nrf52820_peripherals.h index 84dc1bb042..72c28333cf 100644 --- a/mdk/nrf52820_peripherals.h +++ b/mdk/nrf52820_peripherals.h @@ -1,6 +1,8 @@ /* -Copyright (c) 2010 - 2020, Nordic Semiconductor ASA All rights reserved. +Copyright (c) 2010 - 2021, Nordic Semiconductor ASA All rights reserved. + +SPDX-License-Identifier: BSD-3-Clause Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: diff --git a/mdk/nrf52832_peripherals.h b/mdk/nrf52832_peripherals.h index af7ace555c..bada5f2c42 100644 --- a/mdk/nrf52832_peripherals.h +++ b/mdk/nrf52832_peripherals.h @@ -1,6 +1,8 @@ /* -Copyright (c) 2010 - 2020, Nordic Semiconductor ASA All rights reserved. +Copyright (c) 2010 - 2021, Nordic Semiconductor ASA All rights reserved. + +SPDX-License-Identifier: BSD-3-Clause Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: diff --git a/mdk/nrf52833.h b/mdk/nrf52833.h index afb4a24772..dad362e219 100644 --- a/mdk/nrf52833.h +++ b/mdk/nrf52833.h @@ -1,5 +1,7 @@ /* - * Copyright (c) 2010 - 2020, Nordic Semiconductor ASA All rights reserved. + * Copyright (c) 2010 - 2021, Nordic Semiconductor ASA All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: @@ -30,10 +32,10 @@ * @file nrf52833.h * @brief CMSIS HeaderFile * @version 1 - * @date 04. November 2020 - * @note Generated by SVDConv V3.3.35 on Wednesday, 04.11.2020 13:48:08 + * @date 29. April 2021 + * @note Generated by SVDConv V3.3.35 on Thursday, 29.04.2021 12:43:46 * from File 'nrf52833.svd', - * last modified on Wednesday, 04.11.2020 12:48:01 + * last modified on Thursday, 29.04.2021 10:43:41 */ @@ -600,8 +602,8 @@ typedef struct { * @brief ACL_ACL [ACL] (Unspecified) */ typedef struct { - __IOM uint32_t ADDR; /*!< (@ 0x00000000) Description cluster: Configure the word-aligned - start address of region n to protect */ + __IOM uint32_t ADDR; /*!< (@ 0x00000000) Description cluster: Start address of region + to protect. The start address must be word-aligned. */ __IOM uint32_t SIZE; /*!< (@ 0x00000004) Description cluster: Size of region to protect counting from address ACL[n].ADDR. Write '0' as no effect. */ @@ -625,8 +627,8 @@ typedef struct { * @brief PPI_CH [CH] (PPI Channel) */ typedef struct { - __IOM uint32_t EEP; /*!< (@ 0x00000000) Description cluster: Channel n event end-point */ - __IOM uint32_t TEP; /*!< (@ 0x00000004) Description cluster: Channel n task end-point */ + __IOM uint32_t EEP; /*!< (@ 0x00000000) Description cluster: Channel n event endpoint */ + __IOM uint32_t TEP; /*!< (@ 0x00000004) Description cluster: Channel n task endpoint */ } PPI_CH_Type; /*!< Size = 8 (0x8) */ @@ -634,7 +636,7 @@ typedef struct { * @brief PPI_FORK [FORK] (Fork) */ typedef struct { - __IOM uint32_t TEP; /*!< (@ 0x00000000) Description cluster: Channel n task end-point */ + __IOM uint32_t TEP; /*!< (@ 0x00000000) Description cluster: Channel n task endpoint */ } PPI_FORK_Type; /*!< Size = 4 (0x4) */ @@ -897,11 +899,30 @@ typedef struct { /*!< (@ 0x10001000) UICR Structu __IM uint32_t RESERVED3[60]; __IOM uint32_t REGOUT0; /*!< (@ 0x00000304) Output voltage from REG0 regulator stage. The maximum output voltage from this stage is - given as VDDH - VREG0DROP. */ + given as VDDH - V_VDDH-VDD. */ } NRF_UICR_Type; /*!< Size = 776 (0x308) */ +/* =========================================================================================================================== */ +/* ================ APPROTECT ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Access Port Protection (APPROTECT) + */ + +typedef struct { /*!< (@ 0x40000000) APPROTECT Structure */ + __IM uint32_t RESERVED[340]; + __IOM uint32_t FORCEPROTECT; /*!< (@ 0x00000550) Software force enable APPROTECT mechanism until + next reset. */ + __IM uint32_t RESERVED1; + __IOM uint32_t DISABLE; /*!< (@ 0x00000558) Software disable APPROTECT mechanism */ +} NRF_APPROTECT_Type; /*!< Size = 1372 (0x55c) */ + + + /* =========================================================================================================================== */ /* ================ CLOCK ================ */ /* =========================================================================================================================== */ @@ -1027,7 +1048,7 @@ typedef struct { /*!< (@ 0x50000000) P0 Structure __IOM uint32_t LATCH; /*!< (@ 0x00000520) Latch register indicating what GPIO pins that have met the criteria set in the PIN_CNF[n].SENSE registers */ - __IOM uint32_t DETECTMODE; /*!< (@ 0x00000524) Select between default DETECT signal behaviour + __IOM uint32_t DETECTMODE; /*!< (@ 0x00000524) Select between default DETECT signal behavior and LDETECT mode */ __IM uint32_t RESERVED1[118]; __IOM uint32_t PIN_CNF[32]; /*!< (@ 0x00000700) Description collection: Configuration of GPIO @@ -1081,7 +1102,7 @@ typedef struct { /*!< (@ 0x40001000) RADIO Struct __IOM uint32_t EVENTS_FRAMESTART; /*!< (@ 0x00000138) IEEE 802.15.4 length field received */ __IOM uint32_t EVENTS_EDEND; /*!< (@ 0x0000013C) Sampling of energy detection complete. A new ED sample is ready for readout from the - RADIO.EDSAMPLE register */ + RADIO.EDSAMPLE register. */ __IOM uint32_t EVENTS_EDSTOPPED; /*!< (@ 0x00000140) The sampling of energy detection has stopped */ __IOM uint32_t EVENTS_CCAIDLE; /*!< (@ 0x00000144) Wireless medium in idle - clear to send */ __IOM uint32_t EVENTS_CCABUSY; /*!< (@ 0x00000148) Wireless medium busy - do not send */ @@ -1261,8 +1282,8 @@ typedef struct { /*!< (@ 0x40002000) UARTE0 Struc __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ __IM uint32_t RESERVED9[93]; - __IOM uint32_t ERRORSRC; /*!< (@ 0x00000480) Error source Note : this register is read / write - one to clear. */ + __IOM uint32_t ERRORSRC; /*!< (@ 0x00000480) Error source This register is read/write one + to clear. */ __IM uint32_t RESERVED10[31]; __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable UART */ __IM uint32_t RESERVED11; @@ -1344,8 +1365,8 @@ typedef struct { /*!< (@ 0x40003000) SPIM0 Struct __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ __IM uint32_t RESERVED9[61]; __IOM uint32_t STALLSTAT; /*!< (@ 0x00000400) Stall status for EasyDMA RAM accesses. The fields - in this register is set to STALL by hardware - whenever a stall occurres and can be cleared + in this register are set to STALL by hardware + whenever a stall occurs and can be cleared (set to NOSTALL) by the CPU. */ __IM uint32_t RESERVED10[63]; __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable SPIM */ @@ -1494,9 +1515,8 @@ typedef struct { /*!< (@ 0x40003000) TWIM0 Struct __IM uint32_t RESERVED4[7]; __IOM uint32_t EVENTS_ERROR; /*!< (@ 0x00000124) TWI error */ __IM uint32_t RESERVED5[8]; - __IOM uint32_t EVENTS_SUSPENDED; /*!< (@ 0x00000148) Last byte has been sent out after the SUSPEND - task has been issued, TWI traffic is now - suspended. */ + __IOM uint32_t EVENTS_SUSPENDED; /*!< (@ 0x00000148) SUSPEND task has been issued, TWI traffic is + now suspended. */ __IOM uint32_t EVENTS_RXSTARTED; /*!< (@ 0x0000014C) Receive sequence started */ __IOM uint32_t EVENTS_TXSTARTED; /*!< (@ 0x00000150) Transmit sequence started */ __IM uint32_t RESERVED6[2]; @@ -1832,8 +1852,8 @@ typedef struct { /*!< (@ 0x4000B000) RTC0 Structu __IOM uint32_t EVTENCLR; /*!< (@ 0x00000348) Disable event routing */ __IM uint32_t RESERVED4[110]; __IM uint32_t COUNTER; /*!< (@ 0x00000504) Current COUNTER value */ - __IOM uint32_t PRESCALER; /*!< (@ 0x00000508) 12 bit prescaler for COUNTER frequency (32768/(PRESCALER+1)).Mu - t be written when RTC is stopped */ + __IOM uint32_t PRESCALER; /*!< (@ 0x00000508) 12 bit prescaler for COUNTER frequency (32768/(PRESCALER+1)). + Must be written when RTC is stopped. */ __IM uint32_t RESERVED5[13]; __IOM uint32_t CC[4]; /*!< (@ 0x00000540) Description collection: Compare register n */ } NRF_RTC_Type; /*!< Size = 1360 (0x550) */ @@ -1860,25 +1880,25 @@ typedef struct { /*!< (@ 0x4000C000) TEMP Structu __IM uint32_t RESERVED2[127]; __IM int32_t TEMP; /*!< (@ 0x00000508) Temperature in degC (0.25deg steps) */ __IM uint32_t RESERVED3[5]; - __IOM uint32_t A0; /*!< (@ 0x00000520) Slope of 1st piece wise linear function */ - __IOM uint32_t A1; /*!< (@ 0x00000524) Slope of 2nd piece wise linear function */ - __IOM uint32_t A2; /*!< (@ 0x00000528) Slope of 3rd piece wise linear function */ - __IOM uint32_t A3; /*!< (@ 0x0000052C) Slope of 4th piece wise linear function */ - __IOM uint32_t A4; /*!< (@ 0x00000530) Slope of 5th piece wise linear function */ - __IOM uint32_t A5; /*!< (@ 0x00000534) Slope of 6th piece wise linear function */ + __IOM uint32_t A0; /*!< (@ 0x00000520) Slope of first piecewise linear function */ + __IOM uint32_t A1; /*!< (@ 0x00000524) Slope of second piecewise linear function */ + __IOM uint32_t A2; /*!< (@ 0x00000528) Slope of third piecewise linear function */ + __IOM uint32_t A3; /*!< (@ 0x0000052C) Slope of fourth piecewise linear function */ + __IOM uint32_t A4; /*!< (@ 0x00000530) Slope of fifth piecewise linear function */ + __IOM uint32_t A5; /*!< (@ 0x00000534) Slope of sixth piecewise linear function */ __IM uint32_t RESERVED4[2]; - __IOM uint32_t B0; /*!< (@ 0x00000540) y-intercept of 1st piece wise linear function */ - __IOM uint32_t B1; /*!< (@ 0x00000544) y-intercept of 2nd piece wise linear function */ - __IOM uint32_t B2; /*!< (@ 0x00000548) y-intercept of 3rd piece wise linear function */ - __IOM uint32_t B3; /*!< (@ 0x0000054C) y-intercept of 4th piece wise linear function */ - __IOM uint32_t B4; /*!< (@ 0x00000550) y-intercept of 5th piece wise linear function */ - __IOM uint32_t B5; /*!< (@ 0x00000554) y-intercept of 6th piece wise linear function */ + __IOM uint32_t B0; /*!< (@ 0x00000540) y-intercept of first piecewise linear function */ + __IOM uint32_t B1; /*!< (@ 0x00000544) y-intercept of second piecewise linear function */ + __IOM uint32_t B2; /*!< (@ 0x00000548) y-intercept of third piecewise linear function */ + __IOM uint32_t B3; /*!< (@ 0x0000054C) y-intercept of fourth piecewise linear function */ + __IOM uint32_t B4; /*!< (@ 0x00000550) y-intercept of fifth piecewise linear function */ + __IOM uint32_t B5; /*!< (@ 0x00000554) y-intercept of sixth piecewise linear function */ __IM uint32_t RESERVED5[2]; - __IOM uint32_t T0; /*!< (@ 0x00000560) End point of 1st piece wise linear function */ - __IOM uint32_t T1; /*!< (@ 0x00000564) End point of 2nd piece wise linear function */ - __IOM uint32_t T2; /*!< (@ 0x00000568) End point of 3rd piece wise linear function */ - __IOM uint32_t T3; /*!< (@ 0x0000056C) End point of 4th piece wise linear function */ - __IOM uint32_t T4; /*!< (@ 0x00000570) End point of 5th piece wise linear function */ + __IOM uint32_t T0; /*!< (@ 0x00000560) End point of first piecewise linear function */ + __IOM uint32_t T1; /*!< (@ 0x00000564) End point of second piecewise linear function */ + __IOM uint32_t T2; /*!< (@ 0x00000568) End point of third piecewise linear function */ + __IOM uint32_t T3; /*!< (@ 0x0000056C) End point of fourth piecewise linear function */ + __IOM uint32_t T4; /*!< (@ 0x00000570) End point of fifth piecewise linear function */ } NRF_TEMP_Type; /*!< Size = 1396 (0x574) */ @@ -1979,7 +1999,7 @@ typedef struct { /*!< (@ 0x4000F000) AAR Structur */ typedef struct { /*!< (@ 0x4000F000) CCM Structure */ - __OM uint32_t TASKS_KSGEN; /*!< (@ 0x00000000) Start generation of key-stream. This operation + __OM uint32_t TASKS_KSGEN; /*!< (@ 0x00000000) Start generation of keystream. This operation will stop by itself when completed. */ __OM uint32_t TASKS_CRYPT; /*!< (@ 0x00000004) Start encryption/decryption. This operation will stop by itself when completed. */ @@ -1988,7 +2008,7 @@ typedef struct { /*!< (@ 0x4000F000) CCM Structur the contents of the RATEOVERRIDE register for any ongoing encryption/decryption */ __IM uint32_t RESERVED[60]; - __IOM uint32_t EVENTS_ENDKSGEN; /*!< (@ 0x00000100) Key-stream generation complete */ + __IOM uint32_t EVENTS_ENDKSGEN; /*!< (@ 0x00000100) Keystream generation complete */ __IOM uint32_t EVENTS_ENDCRYPT; /*!< (@ 0x00000104) Encrypt/decrypt complete */ __IOM uint32_t EVENTS_ERROR; /*!< (@ 0x00000108) Deprecated register - CCM error event */ __IM uint32_t RESERVED1[61]; @@ -2006,7 +2026,7 @@ typedef struct { /*!< (@ 0x4000F000) CCM Structur __IOM uint32_t INPTR; /*!< (@ 0x0000050C) Input pointer */ __IOM uint32_t OUTPTR; /*!< (@ 0x00000510) Output pointer */ __IOM uint32_t SCRATCHPTR; /*!< (@ 0x00000514) Pointer to data area used for temporary storage */ - __IOM uint32_t MAXPACKETSIZE; /*!< (@ 0x00000518) Length of key-stream generated when MODE.LENGTH + __IOM uint32_t MAXPACKETSIZE; /*!< (@ 0x00000518) Length of keystream generated when MODE.LENGTH = Extended. */ __IOM uint32_t RATEOVERRIDE; /*!< (@ 0x0000051C) Data rate override setting. */ } NRF_CCM_Type; /*!< Size = 1312 (0x520) */ @@ -2611,6 +2631,7 @@ typedef struct { /*!< (@ 0x40027000) USBD Structu #define NRF_FICR_BASE 0x10000000UL #define NRF_UICR_BASE 0x10001000UL +#define NRF_APPROTECT_BASE 0x40000000UL #define NRF_CLOCK_BASE 0x40000000UL #define NRF_POWER_BASE 0x40000000UL #define NRF_P0_BASE 0x50000000UL @@ -2694,6 +2715,7 @@ typedef struct { /*!< (@ 0x40027000) USBD Structu #define NRF_FICR ((NRF_FICR_Type*) NRF_FICR_BASE) #define NRF_UICR ((NRF_UICR_Type*) NRF_UICR_BASE) +#define NRF_APPROTECT ((NRF_APPROTECT_Type*) NRF_APPROTECT_BASE) #define NRF_CLOCK ((NRF_CLOCK_Type*) NRF_CLOCK_BASE) #define NRF_POWER ((NRF_POWER_Type*) NRF_POWER_BASE) #define NRF_P0 ((NRF_GPIO_Type*) NRF_P0_BASE) diff --git a/mdk/nrf52833.svd b/mdk/nrf52833.svd index 2688c6917e..c427c5cd65 100644 --- a/mdk/nrf52833.svd +++ b/mdk/nrf52833.svd @@ -8,7 +8,9 @@ 1 nRF52833 reference description for radio MCU with ARM 32-bit Cortex-M4 Microcontroller -Copyright (c) 2010 - 2020, Nordic Semiconductor ASA All rights reserved.\n +Copyright (c) 2010 - 2021, Nordic Semiconductor ASA All rights reserved.\n +\n +SPDX-License-Identifier: BSD-3-Clause\n \n Redistribution and use in source and binary forms, with or without\n modification, are permitted provided that the following conditions are met:\n @@ -214,6 +216,11 @@ POSSIBILITY OF SUCH DAMAGE.\n 0 31 + + N52820 + nRF52820 + 0x52820 + N52833 nRF52833 @@ -256,6 +263,16 @@ POSSIBILITY OF SUCH DAMAGE.\n AAAB 0x41414142 + + AAA0 + AAA0 + 0x41414130 + + + AAA1 + AAA1 + 0x41414131 + Unspecified Unspecified @@ -280,17 +297,17 @@ POSSIBILITY OF SUCH DAMAGE.\n QD - QDxx - 40-pin QFN + QDxx - 5x5 40-pin QFN 0x2007 QI - QIxx - 73-pin aQFN + QIxx - 7x7 73-pin aQFN 0x2004 CJ - CJxx - WLCSP + CJxx - 3.175 x 3.175 WLCSP 0x2008 @@ -948,9 +965,14 @@ POSSIBILITY OF SUCH DAMAGE.\n Disabled - Disable + Hardware disable of access port protection for devices where access port protection is controlled by hardware 0xFF + + HwDisabled + Hardware disable of access port protection for devices where access port protection is controlled by hardware and software + 0x5A + Enabled Enable @@ -975,12 +997,12 @@ POSSIBILITY OF SUCH DAMAGE.\n Disabled - Operation as GPIO pins. Same protection as normal GPIO pins + Operation as GPIO pins. Same protection as normal GPIO pins. 0 NFC - Operation as NFC antenna pins. Configures the protection for NFC operation + Operation as NFC antenna pins. Configures the protection for NFC operation. 1 @@ -1034,7 +1056,7 @@ POSSIBILITY OF SUCH DAMAGE.\n REGOUT0 - Output voltage from REG0 regulator stage. The maximum output voltage from this stage is given as VDDH - VREG0DROP. + Output voltage from REG0 regulator stage. The maximum output voltage from this stage is given as VDDH - V_VDDH-VDD. 0x304 read-write 0xFFFFFFFF @@ -1086,10 +1108,70 @@ POSSIBILITY OF SUCH DAMAGE.\n + + APPROTECT + Access Port Protection + 0x40000000 + + 0 + 0x1000 + registers + + APPROTECT + 0x20 + + + FORCEPROTECT + Software force enable APPROTECT mechanism until next reset. + 0x550 + read-writeonce + 0xFFFFFFFF + + + FORCEPROTECT + Write 0x0 to force enable APPROTECT mechanism + 0 + 7 + + write + + Force + Software force enable APPROTECT mechanism + 0x0 + + + + + + + DISABLE + Software disable APPROTECT mechanism + 0x558 + read-write + 0x00000000 + + + DISABLE + Software disable APPROTECT mechanism + 0 + 7 + + + SwDisable + Software disable APPROTECT mechanism + 0x5A + + + + + + + CLOCK Clock control 0x40000000 + APPROTECT 0 0x1000 @@ -2122,7 +2204,7 @@ POSSIBILITY OF SUCH DAMAGE.\n POWER Power control 0x40000000 - CLOCK + APPROTECT 0 0x1000 @@ -5325,7 +5407,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets the pin high; writing a '0' has no effect + Write: a '1' sets the pin high; a '0' has no effect 1 @@ -5352,7 +5434,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets the pin high; writing a '0' has no effect + Write: a '1' sets the pin high; a '0' has no effect 1 @@ -5379,7 +5461,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets the pin high; writing a '0' has no effect + Write: a '1' sets the pin high; a '0' has no effect 1 @@ -5406,7 +5488,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets the pin high; writing a '0' has no effect + Write: a '1' sets the pin high; a '0' has no effect 1 @@ -5433,7 +5515,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets the pin high; writing a '0' has no effect + Write: a '1' sets the pin high; a '0' has no effect 1 @@ -5460,7 +5542,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets the pin high; writing a '0' has no effect + Write: a '1' sets the pin high; a '0' has no effect 1 @@ -5487,7 +5569,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets the pin high; writing a '0' has no effect + Write: a '1' sets the pin high; a '0' has no effect 1 @@ -5514,7 +5596,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets the pin high; writing a '0' has no effect + Write: a '1' sets the pin high; a '0' has no effect 1 @@ -5541,7 +5623,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets the pin high; writing a '0' has no effect + Write: a '1' sets the pin high; a '0' has no effect 1 @@ -5568,7 +5650,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets the pin high; writing a '0' has no effect + Write: a '1' sets the pin high; a '0' has no effect 1 @@ -5595,7 +5677,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets the pin high; writing a '0' has no effect + Write: a '1' sets the pin high; a '0' has no effect 1 @@ -5622,7 +5704,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets the pin high; writing a '0' has no effect + Write: a '1' sets the pin high; a '0' has no effect 1 @@ -5649,7 +5731,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets the pin high; writing a '0' has no effect + Write: a '1' sets the pin high; a '0' has no effect 1 @@ -5676,7 +5758,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets the pin high; writing a '0' has no effect + Write: a '1' sets the pin high; a '0' has no effect 1 @@ -5703,7 +5785,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets the pin high; writing a '0' has no effect + Write: a '1' sets the pin high; a '0' has no effect 1 @@ -5730,7 +5812,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets the pin high; writing a '0' has no effect + Write: a '1' sets the pin high; a '0' has no effect 1 @@ -5757,7 +5839,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets the pin high; writing a '0' has no effect + Write: a '1' sets the pin high; a '0' has no effect 1 @@ -5784,7 +5866,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets the pin high; writing a '0' has no effect + Write: a '1' sets the pin high; a '0' has no effect 1 @@ -5811,7 +5893,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets the pin high; writing a '0' has no effect + Write: a '1' sets the pin high; a '0' has no effect 1 @@ -5838,7 +5920,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets the pin high; writing a '0' has no effect + Write: a '1' sets the pin high; a '0' has no effect 1 @@ -5865,7 +5947,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets the pin high; writing a '0' has no effect + Write: a '1' sets the pin high; a '0' has no effect 1 @@ -5892,7 +5974,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets the pin high; writing a '0' has no effect + Write: a '1' sets the pin high; a '0' has no effect 1 @@ -5919,7 +6001,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets the pin high; writing a '0' has no effect + Write: a '1' sets the pin high; a '0' has no effect 1 @@ -5946,7 +6028,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets the pin high; writing a '0' has no effect + Write: a '1' sets the pin high; a '0' has no effect 1 @@ -5973,7 +6055,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets the pin high; writing a '0' has no effect + Write: a '1' sets the pin high; a '0' has no effect 1 @@ -6000,7 +6082,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets the pin high; writing a '0' has no effect + Write: a '1' sets the pin high; a '0' has no effect 1 @@ -6027,7 +6109,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets the pin high; writing a '0' has no effect + Write: a '1' sets the pin high; a '0' has no effect 1 @@ -6054,7 +6136,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets the pin high; writing a '0' has no effect + Write: a '1' sets the pin high; a '0' has no effect 1 @@ -6081,7 +6163,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets the pin high; writing a '0' has no effect + Write: a '1' sets the pin high; a '0' has no effect 1 @@ -6108,7 +6190,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets the pin high; writing a '0' has no effect + Write: a '1' sets the pin high; a '0' has no effect 1 @@ -6135,7 +6217,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets the pin high; writing a '0' has no effect + Write: a '1' sets the pin high; a '0' has no effect 1 @@ -6162,7 +6244,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets the pin high; writing a '0' has no effect + Write: a '1' sets the pin high; a '0' has no effect 1 @@ -6198,7 +6280,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect + Write: a '1' sets the pin low; a '0' has no effect 1 @@ -6225,7 +6307,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect + Write: a '1' sets the pin low; a '0' has no effect 1 @@ -6252,7 +6334,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect + Write: a '1' sets the pin low; a '0' has no effect 1 @@ -6279,7 +6361,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect + Write: a '1' sets the pin low; a '0' has no effect 1 @@ -6306,7 +6388,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect + Write: a '1' sets the pin low; a '0' has no effect 1 @@ -6333,7 +6415,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect + Write: a '1' sets the pin low; a '0' has no effect 1 @@ -6360,7 +6442,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect + Write: a '1' sets the pin low; a '0' has no effect 1 @@ -6387,7 +6469,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect + Write: a '1' sets the pin low; a '0' has no effect 1 @@ -6414,7 +6496,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect + Write: a '1' sets the pin low; a '0' has no effect 1 @@ -6441,7 +6523,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect + Write: a '1' sets the pin low; a '0' has no effect 1 @@ -6468,7 +6550,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect + Write: a '1' sets the pin low; a '0' has no effect 1 @@ -6495,7 +6577,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect + Write: a '1' sets the pin low; a '0' has no effect 1 @@ -6522,7 +6604,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect + Write: a '1' sets the pin low; a '0' has no effect 1 @@ -6549,7 +6631,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect + Write: a '1' sets the pin low; a '0' has no effect 1 @@ -6576,7 +6658,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect + Write: a '1' sets the pin low; a '0' has no effect 1 @@ -6603,7 +6685,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect + Write: a '1' sets the pin low; a '0' has no effect 1 @@ -6630,7 +6712,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect + Write: a '1' sets the pin low; a '0' has no effect 1 @@ -6657,7 +6739,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect + Write: a '1' sets the pin low; a '0' has no effect 1 @@ -6684,7 +6766,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect + Write: a '1' sets the pin low; a '0' has no effect 1 @@ -6711,7 +6793,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect + Write: a '1' sets the pin low; a '0' has no effect 1 @@ -6738,7 +6820,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect + Write: a '1' sets the pin low; a '0' has no effect 1 @@ -6765,7 +6847,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect + Write: a '1' sets the pin low; a '0' has no effect 1 @@ -6792,7 +6874,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect + Write: a '1' sets the pin low; a '0' has no effect 1 @@ -6819,7 +6901,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect + Write: a '1' sets the pin low; a '0' has no effect 1 @@ -6846,7 +6928,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect + Write: a '1' sets the pin low; a '0' has no effect 1 @@ -6873,7 +6955,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect + Write: a '1' sets the pin low; a '0' has no effect 1 @@ -6900,7 +6982,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect + Write: a '1' sets the pin low; a '0' has no effect 1 @@ -6927,7 +7009,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect + Write: a '1' sets the pin low; a '0' has no effect 1 @@ -6954,7 +7036,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect + Write: a '1' sets the pin low; a '0' has no effect 1 @@ -6981,7 +7063,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect + Write: a '1' sets the pin low; a '0' has no effect 1 @@ -7008,7 +7090,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect + Write: a '1' sets the pin low; a '0' has no effect 1 @@ -7035,7 +7117,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect + Write: a '1' sets the pin low; a '0' has no effect 1 @@ -8239,7 +8321,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets pin to output; writing a '0' has no effect + Write: a '1' sets pin to output; a '0' has no effect 1 @@ -8266,7 +8348,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets pin to output; writing a '0' has no effect + Write: a '1' sets pin to output; a '0' has no effect 1 @@ -8293,7 +8375,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets pin to output; writing a '0' has no effect + Write: a '1' sets pin to output; a '0' has no effect 1 @@ -8320,7 +8402,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets pin to output; writing a '0' has no effect + Write: a '1' sets pin to output; a '0' has no effect 1 @@ -8347,7 +8429,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets pin to output; writing a '0' has no effect + Write: a '1' sets pin to output; a '0' has no effect 1 @@ -8374,7 +8456,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets pin to output; writing a '0' has no effect + Write: a '1' sets pin to output; a '0' has no effect 1 @@ -8401,7 +8483,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets pin to output; writing a '0' has no effect + Write: a '1' sets pin to output; a '0' has no effect 1 @@ -8428,7 +8510,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets pin to output; writing a '0' has no effect + Write: a '1' sets pin to output; a '0' has no effect 1 @@ -8455,7 +8537,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets pin to output; writing a '0' has no effect + Write: a '1' sets pin to output; a '0' has no effect 1 @@ -8482,7 +8564,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets pin to output; writing a '0' has no effect + Write: a '1' sets pin to output; a '0' has no effect 1 @@ -8509,7 +8591,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets pin to output; writing a '0' has no effect + Write: a '1' sets pin to output; a '0' has no effect 1 @@ -8536,7 +8618,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets pin to output; writing a '0' has no effect + Write: a '1' sets pin to output; a '0' has no effect 1 @@ -8563,7 +8645,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets pin to output; writing a '0' has no effect + Write: a '1' sets pin to output; a '0' has no effect 1 @@ -8590,7 +8672,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets pin to output; writing a '0' has no effect + Write: a '1' sets pin to output; a '0' has no effect 1 @@ -8617,7 +8699,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets pin to output; writing a '0' has no effect + Write: a '1' sets pin to output; a '0' has no effect 1 @@ -8644,7 +8726,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets pin to output; writing a '0' has no effect + Write: a '1' sets pin to output; a '0' has no effect 1 @@ -8671,7 +8753,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets pin to output; writing a '0' has no effect + Write: a '1' sets pin to output; a '0' has no effect 1 @@ -8698,7 +8780,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets pin to output; writing a '0' has no effect + Write: a '1' sets pin to output; a '0' has no effect 1 @@ -8725,7 +8807,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets pin to output; writing a '0' has no effect + Write: a '1' sets pin to output; a '0' has no effect 1 @@ -8752,7 +8834,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets pin to output; writing a '0' has no effect + Write: a '1' sets pin to output; a '0' has no effect 1 @@ -8779,7 +8861,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets pin to output; writing a '0' has no effect + Write: a '1' sets pin to output; a '0' has no effect 1 @@ -8806,7 +8888,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets pin to output; writing a '0' has no effect + Write: a '1' sets pin to output; a '0' has no effect 1 @@ -8833,7 +8915,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets pin to output; writing a '0' has no effect + Write: a '1' sets pin to output; a '0' has no effect 1 @@ -8860,7 +8942,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets pin to output; writing a '0' has no effect + Write: a '1' sets pin to output; a '0' has no effect 1 @@ -8887,7 +8969,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets pin to output; writing a '0' has no effect + Write: a '1' sets pin to output; a '0' has no effect 1 @@ -8914,7 +8996,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets pin to output; writing a '0' has no effect + Write: a '1' sets pin to output; a '0' has no effect 1 @@ -8941,7 +9023,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets pin to output; writing a '0' has no effect + Write: a '1' sets pin to output; a '0' has no effect 1 @@ -8968,7 +9050,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets pin to output; writing a '0' has no effect + Write: a '1' sets pin to output; a '0' has no effect 1 @@ -8995,7 +9077,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets pin to output; writing a '0' has no effect + Write: a '1' sets pin to output; a '0' has no effect 1 @@ -9022,7 +9104,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets pin to output; writing a '0' has no effect + Write: a '1' sets pin to output; a '0' has no effect 1 @@ -9049,7 +9131,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets pin to output; writing a '0' has no effect + Write: a '1' sets pin to output; a '0' has no effect 1 @@ -9076,7 +9158,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets pin to output; writing a '0' has no effect + Write: a '1' sets pin to output; a '0' has no effect 1 @@ -9112,7 +9194,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect + Write: a '1' sets pin to input; a '0' has no effect 1 @@ -9139,7 +9221,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect + Write: a '1' sets pin to input; a '0' has no effect 1 @@ -9166,7 +9248,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect + Write: a '1' sets pin to input; a '0' has no effect 1 @@ -9193,7 +9275,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect + Write: a '1' sets pin to input; a '0' has no effect 1 @@ -9220,7 +9302,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect + Write: a '1' sets pin to input; a '0' has no effect 1 @@ -9247,7 +9329,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect + Write: a '1' sets pin to input; a '0' has no effect 1 @@ -9274,7 +9356,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect + Write: a '1' sets pin to input; a '0' has no effect 1 @@ -9301,7 +9383,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect + Write: a '1' sets pin to input; a '0' has no effect 1 @@ -9328,7 +9410,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect + Write: a '1' sets pin to input; a '0' has no effect 1 @@ -9355,7 +9437,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect + Write: a '1' sets pin to input; a '0' has no effect 1 @@ -9382,7 +9464,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect + Write: a '1' sets pin to input; a '0' has no effect 1 @@ -9409,7 +9491,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect + Write: a '1' sets pin to input; a '0' has no effect 1 @@ -9436,7 +9518,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect + Write: a '1' sets pin to input; a '0' has no effect 1 @@ -9463,7 +9545,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect + Write: a '1' sets pin to input; a '0' has no effect 1 @@ -9490,7 +9572,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect + Write: a '1' sets pin to input; a '0' has no effect 1 @@ -9517,7 +9599,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect + Write: a '1' sets pin to input; a '0' has no effect 1 @@ -9544,7 +9626,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect + Write: a '1' sets pin to input; a '0' has no effect 1 @@ -9571,7 +9653,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect + Write: a '1' sets pin to input; a '0' has no effect 1 @@ -9598,7 +9680,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect + Write: a '1' sets pin to input; a '0' has no effect 1 @@ -9625,7 +9707,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect + Write: a '1' sets pin to input; a '0' has no effect 1 @@ -9652,7 +9734,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect + Write: a '1' sets pin to input; a '0' has no effect 1 @@ -9679,7 +9761,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect + Write: a '1' sets pin to input; a '0' has no effect 1 @@ -9706,7 +9788,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect + Write: a '1' sets pin to input; a '0' has no effect 1 @@ -9733,7 +9815,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect + Write: a '1' sets pin to input; a '0' has no effect 1 @@ -9760,7 +9842,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect + Write: a '1' sets pin to input; a '0' has no effect 1 @@ -9787,7 +9869,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect + Write: a '1' sets pin to input; a '0' has no effect 1 @@ -9814,7 +9896,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect + Write: a '1' sets pin to input; a '0' has no effect 1 @@ -9841,7 +9923,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect + Write: a '1' sets pin to input; a '0' has no effect 1 @@ -9868,7 +9950,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect + Write: a '1' sets pin to input; a '0' has no effect 1 @@ -9895,7 +9977,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect + Write: a '1' sets pin to input; a '0' has no effect 1 @@ -9922,7 +10004,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect + Write: a '1' sets pin to input; a '0' has no effect 1 @@ -9949,7 +10031,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect + Write: a '1' sets pin to input; a '0' has no effect 1 @@ -10542,13 +10624,13 @@ POSSIBILITY OF SUCH DAMAGE.\n DETECTMODE - Select between default DETECT signal behaviour and LDETECT mode + Select between default DETECT signal behavior and LDETECT mode 0x524 read-write DETECTMODE - Select between default DETECT signal behaviour and LDETECT mode + Select between default DETECT signal behavior and LDETECT mode 0 0 @@ -10559,7 +10641,7 @@ POSSIBILITY OF SUCH DAMAGE.\n LDETECT - Use the latched LDETECT behaviour + Use the latched LDETECT behavior 1 @@ -11318,13 +11400,13 @@ POSSIBILITY OF SUCH DAMAGE.\n EVENTS_EDEND - Sampling of energy detection complete. A new ED sample is ready for readout from the RADIO.EDSAMPLE register + Sampling of energy detection complete. A new ED sample is ready for readout from the RADIO.EDSAMPLE register. 0x13C read-write EVENTS_EDEND - Sampling of energy detection complete. A new ED sample is ready for readout from the RADIO.EDSAMPLE register + Sampling of energy detection complete. A new ED sample is ready for readout from the RADIO.EDSAMPLE register. 0 0 @@ -13522,7 +13604,7 @@ POSSIBILITY OF SUCH DAMAGE.\n MAP - Channel map selection. + Channel map selection 8 8 @@ -13690,19 +13772,19 @@ POSSIBILITY OF SUCH DAMAGE.\n LFLEN - Length on air of LENGTH field in number of bits. + Length on air of LENGTH field in number of bits 0 3 S0LEN - Length on air of S0 field in number of bytes. + Length on air of S0 field in number of bytes 8 8 S1LEN - Length on air of S1 field in number of bits. + Length on air of S1 field in number of bits 16 19 @@ -14112,7 +14194,7 @@ POSSIBILITY OF SUCH DAMAGE.\n LEN - CRC length in number of bytes. + CRC length in number of bytes For MODE Ble_LR125Kbit and Ble_LR500Kbit, only LEN set to 3 is supported 0 1 @@ -14200,7 +14282,7 @@ POSSIBILITY OF SUCH DAMAGE.\n TIFS - Interframe spacing in us + Interframe spacing in us. 0 9 @@ -14214,7 +14296,7 @@ POSSIBILITY OF SUCH DAMAGE.\n RSSISAMPLE - RSSI sample + RSSI sample. 0 6 @@ -14590,7 +14672,7 @@ POSSIBILITY OF SUCH DAMAGE.\n Fast - Fast ramp-up (tRXEN,FAST and tTXEN,FAST), see electrical specification for more information + Fast ramp-up (tRXEN,FAST and tTXEN,FAST), see electrical specifications for more information 1 @@ -14826,93 +14908,93 @@ POSSIBILITY OF SUCH DAMAGE.\n 20 - 20 in 8us unit (default) Set to 20 if parsed CTETime is larger han 20 + 20 in 8 us unit (default) Set to 20 if parsed CTETime is larger than 20 0 31 - 31 in 8us unit + 31 in 8 us unit 1 63 - 63 in 8us unit + 63 in 8 us unit 2 CTEINLINERXMODE1US - Spacing between samples for the samples in the SWITCHING period when CTEINLINEMODE is set + Spacing between samples for the samples in the SWITCHING period when CTEINLINEMODE is set. 10 12 4us - 4us + 4 us 1 2us - 2us + 2 us 2 1us - 1us + 1 us 3 500ns - 0.5us + 0.5 us 4 250ns - 0.25us + 0.25 us 5 125ns - 0.125us + 0.125 us 6 CTEINLINERXMODE2US - Spacing between samples for the samples in the SWITCHING period when CTEINLINEMODE is set + Spacing between samples for the samples in the SWITCHING period when CTEINLINEMODE is set. 13 15 4us - 4us + 4 us 1 2us - 2us + 2 us 2 1us - 1us + 1 us 3 500ns - 0.5us + 0.5 us 4 250ns - 0.25us + 0.25 us 5 125ns - 0.125us + 0.125 us 6 @@ -14970,17 +15052,17 @@ POSSIBILITY OF SUCH DAMAGE.\n 4us - 4us + 4 us 1 2us - 2us + 2 us 2 1us - 1us + 1 us 3 @@ -14993,32 +15075,32 @@ POSSIBILITY OF SUCH DAMAGE.\n 4us - 4us + 4 us 1 2us - 2us + 2 us 2 1us - 1us + 1 us 3 500ns - 0.5us + 0.5 us 4 250ns - 0.25us + 0.25 us 5 125ns - 0.125us + 0.125 us 6 @@ -15049,32 +15131,32 @@ POSSIBILITY OF SUCH DAMAGE.\n 4us - 4us + 4 us 1 2us - 2us + 2 us 2 1us - 1us + 1 us 3 500ns - 0.5us + 0.5 us 4 250ns - 0.25us + 0.25 us 5 125ns - 0.125us + 0.125 us 6 @@ -15130,7 +15212,7 @@ POSSIBILITY OF SUCH DAMAGE.\n SWITCHPATTERN - Fill array of GPIO patterns for antenna control + Fill array of GPIO patterns for antenna control. 0 7 @@ -17711,7 +17793,7 @@ POSSIBILITY OF SUCH DAMAGE.\n ERRORSRC - Error source Note : this register is read / write one to clear. + Error source This register is read/write one to clear. 0x480 read-write oneToClear @@ -18083,7 +18165,7 @@ POSSIBILITY OF SUCH DAMAGE.\n Baud1M - 1Mega baud + 1 megabaud 0x10000000 @@ -18556,7 +18638,7 @@ POSSIBILITY OF SUCH DAMAGE.\n TXD - TX data to send. Double buffered + TX data to send. Double buffered. 0 7 @@ -19224,7 +19306,7 @@ POSSIBILITY OF SUCH DAMAGE.\n STALLSTAT - Stall status for EasyDMA RAM accesses. The fields in this register is set to STALL by hardware whenever a stall occurres and can be cleared (set to NOSTALL) by the CPU. + Stall status for EasyDMA RAM accesses. The fields in this register are set to STALL by hardware whenever a stall occurs and can be cleared (set to NOSTALL) by the CPU. 0x400 read-write 0x00000000 @@ -21829,13 +21911,13 @@ POSSIBILITY OF SUCH DAMAGE.\n EVENTS_SUSPENDED - Last byte has been sent out after the SUSPEND task has been issued, TWI traffic is now suspended. + SUSPEND task has been issued, TWI traffic is now suspended. 0x148 read-write EVENTS_SUSPENDED - Last byte has been sent out after the SUSPEND task has been issued, TWI traffic is now suspended. + SUSPEND task has been issued, TWI traffic is now suspended. 0 0 @@ -23823,7 +23905,7 @@ POSSIBILITY OF SUCH DAMAGE.\n MATCH - Which of the addresses in {ADDRESS} matched the incoming address + Indication of which address in {ADDRESS} that matched the incoming address 0 0 @@ -31878,7 +31960,7 @@ POSSIBILITY OF SUCH DAMAGE.\n PRESCALER - 12 bit prescaler for COUNTER frequency (32768/(PRESCALER+1)).Must be written when RTC is stopped + 12 bit prescaler for COUNTER frequency (32768/(PRESCALER+1)). Must be written when RTC is stopped. 0x508 read-write @@ -32079,14 +32161,14 @@ POSSIBILITY OF SUCH DAMAGE.\n A0 - Slope of 1st piece wise linear function + Slope of first piecewise linear function 0x520 read-write 0x00000326 A0 - Slope of 1st piece wise linear function + Slope of first piecewise linear function 0 11 @@ -32094,14 +32176,14 @@ POSSIBILITY OF SUCH DAMAGE.\n A1 - Slope of 2nd piece wise linear function + Slope of second piecewise linear function 0x524 read-write 0x00000348 A1 - Slope of 2nd piece wise linear function + Slope of second piecewise linear function 0 11 @@ -32109,14 +32191,14 @@ POSSIBILITY OF SUCH DAMAGE.\n A2 - Slope of 3rd piece wise linear function + Slope of third piecewise linear function 0x528 read-write 0x000003AA A2 - Slope of 3rd piece wise linear function + Slope of third piecewise linear function 0 11 @@ -32124,14 +32206,14 @@ POSSIBILITY OF SUCH DAMAGE.\n A3 - Slope of 4th piece wise linear function + Slope of fourth piecewise linear function 0x52C read-write 0x0000040E A3 - Slope of 4th piece wise linear function + Slope of fourth piecewise linear function 0 11 @@ -32139,14 +32221,14 @@ POSSIBILITY OF SUCH DAMAGE.\n A4 - Slope of 5th piece wise linear function + Slope of fifth piecewise linear function 0x530 read-write 0x000004BD A4 - Slope of 5th piece wise linear function + Slope of fifth piecewise linear function 0 11 @@ -32154,14 +32236,14 @@ POSSIBILITY OF SUCH DAMAGE.\n A5 - Slope of 6th piece wise linear function + Slope of sixth piecewise linear function 0x534 read-write 0x000005A3 A5 - Slope of 6th piece wise linear function + Slope of sixth piecewise linear function 0 11 @@ -32169,14 +32251,14 @@ POSSIBILITY OF SUCH DAMAGE.\n B0 - y-intercept of 1st piece wise linear function + y-intercept of first piecewise linear function 0x540 read-write 0x00003FEF B0 - y-intercept of 1st piece wise linear function + y-intercept of first piecewise linear function 0 13 @@ -32184,14 +32266,14 @@ POSSIBILITY OF SUCH DAMAGE.\n B1 - y-intercept of 2nd piece wise linear function + y-intercept of second piecewise linear function 0x544 read-write 0x00003FBE B1 - y-intercept of 2nd piece wise linear function + y-intercept of second piecewise linear function 0 13 @@ -32199,14 +32281,14 @@ POSSIBILITY OF SUCH DAMAGE.\n B2 - y-intercept of 3rd piece wise linear function + y-intercept of third piecewise linear function 0x548 read-write 0x00003FBE B2 - y-intercept of 3rd piece wise linear function + y-intercept of third piecewise linear function 0 13 @@ -32214,14 +32296,14 @@ POSSIBILITY OF SUCH DAMAGE.\n B3 - y-intercept of 4th piece wise linear function + y-intercept of fourth piecewise linear function 0x54C read-write 0x00000012 B3 - y-intercept of 4th piece wise linear function + y-intercept of fourth piecewise linear function 0 13 @@ -32229,14 +32311,14 @@ POSSIBILITY OF SUCH DAMAGE.\n B4 - y-intercept of 5th piece wise linear function + y-intercept of fifth piecewise linear function 0x550 read-write 0x00000124 B4 - y-intercept of 5th piece wise linear function + y-intercept of fifth piecewise linear function 0 13 @@ -32244,14 +32326,14 @@ POSSIBILITY OF SUCH DAMAGE.\n B5 - y-intercept of 6th piece wise linear function + y-intercept of sixth piecewise linear function 0x554 read-write 0x0000027C B5 - y-intercept of 6th piece wise linear function + y-intercept of sixth piecewise linear function 0 13 @@ -32259,14 +32341,14 @@ POSSIBILITY OF SUCH DAMAGE.\n T0 - End point of 1st piece wise linear function + End point of first piecewise linear function 0x560 read-write 0x000000E2 T0 - End point of 1st piece wise linear function + End point of first piecewise linear function 0 7 @@ -32274,14 +32356,14 @@ POSSIBILITY OF SUCH DAMAGE.\n T1 - End point of 2nd piece wise linear function + End point of second piecewise linear function 0x564 read-write 0x00000000 T1 - End point of 2nd piece wise linear function + End point of second piecewise linear function 0 7 @@ -32289,14 +32371,14 @@ POSSIBILITY OF SUCH DAMAGE.\n T2 - End point of 3rd piece wise linear function + End point of third piecewise linear function 0x568 read-write 0x00000019 T2 - End point of 3rd piece wise linear function + End point of third piecewise linear function 0 7 @@ -32304,14 +32386,14 @@ POSSIBILITY OF SUCH DAMAGE.\n T3 - End point of 4th piece wise linear function + End point of fourth piecewise linear function 0x56C read-write 0x0000003C T3 - End point of 4th piece wise linear function + End point of fourth piecewise linear function 0 7 @@ -32319,14 +32401,14 @@ POSSIBILITY OF SUCH DAMAGE.\n T4 - End point of 5th piece wise linear function + End point of fifth piecewise linear function 0x570 read-write 0x00000050 T4 - End point of 5th piece wise linear function + End point of fifth piecewise linear function 0 7 @@ -33169,7 +33251,7 @@ POSSIBILITY OF SUCH DAMAGE.\n NIRK - Number of Identity root keys available in the IRK data structure + Number of Identity Root Keys available in the IRK data structure 0 4 @@ -33238,13 +33320,13 @@ POSSIBILITY OF SUCH DAMAGE.\n TASKS_KSGEN - Start generation of key-stream. This operation will stop by itself when completed. + Start generation of keystream. This operation will stop by itself when completed. 0x000 write-only TASKS_KSGEN - Start generation of key-stream. This operation will stop by itself when completed. + Start generation of keystream. This operation will stop by itself when completed. 0 0 @@ -33322,13 +33404,13 @@ POSSIBILITY OF SUCH DAMAGE.\n EVENTS_ENDKSGEN - Key-stream generation complete + Keystream generation complete 0x100 read-write EVENTS_ENDKSGEN - Key-stream generation complete + Keystream generation complete 0 0 @@ -33715,12 +33797,12 @@ POSSIBILITY OF SUCH DAMAGE.\n Default - Default length. Effective length of LENGTH field in encrypted/decrypted packet is 5 bits. A key-stream for packet payloads up to 27 bytes will be generated. + Default length. Effective length of LENGTH field in encrypted/decrypted packet is 5 bits. A keystream for packet payloads up to 27 bytes will be generated. 0 Extended - Extended length. Effective length of LENGTH field in encrypted/decrypted packet is 8 bits. A key-stream for packet payloads up to MAXPACKETSIZE bytes will be generated. + Extended length. Effective length of LENGTH field in encrypted/decrypted packet is 8 bits. A keystream for packet payloads up to MAXPACKETSIZE bytes will be generated. 1 @@ -33777,7 +33859,7 @@ POSSIBILITY OF SUCH DAMAGE.\n SCRATCHPTR - Pointer to a scratch data area used for temporary storage during key-stream generation, + Pointer to a scratch data area used for temporary storage during keystream generation, MIC generation and encryption/decryption. 0 31 @@ -33786,14 +33868,14 @@ POSSIBILITY OF SUCH DAMAGE.\n MAXPACKETSIZE - Length of key-stream generated when MODE.LENGTH = Extended. + Length of keystream generated when MODE.LENGTH = Extended. 0x518 read-write 0x000000FB MAXPACKETSIZE - Length of key-stream generated when MODE.LENGTH = Extended. This value must be greater or equal to the subsequent packet payload to be encrypted/decrypted. + Length of keystream generated when MODE.LENGTH = Extended. This value must be greater or equal to the subsequent packet payload to be encrypted/decrypted. 0 7 @@ -35214,53 +35296,53 @@ POSSIBILITY OF SUCH DAMAGE.\n REPORTPER - Specifies the number of samples to be accumulated in the ACC register before the REPORTRDY and DBLRDY events can be generated + Specifies the number of samples to be accumulated in the ACC register before the REPORTRDY and DBLRDY events can be generated. 0 3 10Smpl - 10 samples / report + 10 samples/report 0 40Smpl - 40 samples / report + 40 samples/report 1 80Smpl - 80 samples / report + 80 samples/report 2 120Smpl - 120 samples / report + 120 samples/report 3 160Smpl - 160 samples / report + 160 samples/report 4 200Smpl - 200 samples / report + 200 samples/report 5 240Smpl - 240 samples / report + 240 samples/report 6 280Smpl - 280 samples / report + 280 samples/report 7 1Smpl - 1 sample / report + 1 sample/report 8 @@ -35276,7 +35358,7 @@ POSSIBILITY OF SUCH DAMAGE.\n ACC - Register accumulating all valid samples (not double transition) read from the SAMPLE register + Register accumulating all valid samples (not double transition) read from the SAMPLE register. 0 31 @@ -40487,14 +40569,14 @@ POSSIBILITY OF SUCH DAMAGE.\n 0x800 ADDR - Description cluster: Configure the word-aligned start address of region n to protect + Description cluster: Start address of region to protect. The start address must be word-aligned. 0x000 read-writeonce 0x00000000 ADDR - Valid word-aligned start address of region n to protect. Address must point to a flash page boundary. + Start address of flash region n. The start address must point to a flash page boundary. 0 31 @@ -41516,7 +41598,7 @@ POSSIBILITY OF SUCH DAMAGE.\n CH0 - Channel 0 enable set register. Writing '0' has no effect + Channel 0 enable set register. Writing '0' has no effect. 0 0 @@ -41543,7 +41625,7 @@ POSSIBILITY OF SUCH DAMAGE.\n CH1 - Channel 1 enable set register. Writing '0' has no effect + Channel 1 enable set register. Writing '0' has no effect. 1 1 @@ -41570,7 +41652,7 @@ POSSIBILITY OF SUCH DAMAGE.\n CH2 - Channel 2 enable set register. Writing '0' has no effect + Channel 2 enable set register. Writing '0' has no effect. 2 2 @@ -41597,7 +41679,7 @@ POSSIBILITY OF SUCH DAMAGE.\n CH3 - Channel 3 enable set register. Writing '0' has no effect + Channel 3 enable set register. Writing '0' has no effect. 3 3 @@ -41624,7 +41706,7 @@ POSSIBILITY OF SUCH DAMAGE.\n CH4 - Channel 4 enable set register. Writing '0' has no effect + Channel 4 enable set register. Writing '0' has no effect. 4 4 @@ -41651,7 +41733,7 @@ POSSIBILITY OF SUCH DAMAGE.\n CH5 - Channel 5 enable set register. Writing '0' has no effect + Channel 5 enable set register. Writing '0' has no effect. 5 5 @@ -41678,7 +41760,7 @@ POSSIBILITY OF SUCH DAMAGE.\n CH6 - Channel 6 enable set register. Writing '0' has no effect + Channel 6 enable set register. Writing '0' has no effect. 6 6 @@ -41705,7 +41787,7 @@ POSSIBILITY OF SUCH DAMAGE.\n CH7 - Channel 7 enable set register. Writing '0' has no effect + Channel 7 enable set register. Writing '0' has no effect. 7 7 @@ -41732,7 +41814,7 @@ POSSIBILITY OF SUCH DAMAGE.\n CH8 - Channel 8 enable set register. Writing '0' has no effect + Channel 8 enable set register. Writing '0' has no effect. 8 8 @@ -41759,7 +41841,7 @@ POSSIBILITY OF SUCH DAMAGE.\n CH9 - Channel 9 enable set register. Writing '0' has no effect + Channel 9 enable set register. Writing '0' has no effect. 9 9 @@ -41786,7 +41868,7 @@ POSSIBILITY OF SUCH DAMAGE.\n CH10 - Channel 10 enable set register. Writing '0' has no effect + Channel 10 enable set register. Writing '0' has no effect. 10 10 @@ -41813,7 +41895,7 @@ POSSIBILITY OF SUCH DAMAGE.\n CH11 - Channel 11 enable set register. Writing '0' has no effect + Channel 11 enable set register. Writing '0' has no effect. 11 11 @@ -41840,7 +41922,7 @@ POSSIBILITY OF SUCH DAMAGE.\n CH12 - Channel 12 enable set register. Writing '0' has no effect + Channel 12 enable set register. Writing '0' has no effect. 12 12 @@ -41867,7 +41949,7 @@ POSSIBILITY OF SUCH DAMAGE.\n CH13 - Channel 13 enable set register. Writing '0' has no effect + Channel 13 enable set register. Writing '0' has no effect. 13 13 @@ -41894,7 +41976,7 @@ POSSIBILITY OF SUCH DAMAGE.\n CH14 - Channel 14 enable set register. Writing '0' has no effect + Channel 14 enable set register. Writing '0' has no effect. 14 14 @@ -41921,7 +42003,7 @@ POSSIBILITY OF SUCH DAMAGE.\n CH15 - Channel 15 enable set register. Writing '0' has no effect + Channel 15 enable set register. Writing '0' has no effect. 15 15 @@ -41948,7 +42030,7 @@ POSSIBILITY OF SUCH DAMAGE.\n CH16 - Channel 16 enable set register. Writing '0' has no effect + Channel 16 enable set register. Writing '0' has no effect. 16 16 @@ -41975,7 +42057,7 @@ POSSIBILITY OF SUCH DAMAGE.\n CH17 - Channel 17 enable set register. Writing '0' has no effect + Channel 17 enable set register. Writing '0' has no effect. 17 17 @@ -42002,7 +42084,7 @@ POSSIBILITY OF SUCH DAMAGE.\n CH18 - Channel 18 enable set register. Writing '0' has no effect + Channel 18 enable set register. Writing '0' has no effect. 18 18 @@ -42029,7 +42111,7 @@ POSSIBILITY OF SUCH DAMAGE.\n CH19 - Channel 19 enable set register. Writing '0' has no effect + Channel 19 enable set register. Writing '0' has no effect. 19 19 @@ -42056,7 +42138,7 @@ POSSIBILITY OF SUCH DAMAGE.\n CH20 - Channel 20 enable set register. Writing '0' has no effect + Channel 20 enable set register. Writing '0' has no effect. 20 20 @@ -42083,7 +42165,7 @@ POSSIBILITY OF SUCH DAMAGE.\n CH21 - Channel 21 enable set register. Writing '0' has no effect + Channel 21 enable set register. Writing '0' has no effect. 21 21 @@ -42110,7 +42192,7 @@ POSSIBILITY OF SUCH DAMAGE.\n CH22 - Channel 22 enable set register. Writing '0' has no effect + Channel 22 enable set register. Writing '0' has no effect. 22 22 @@ -42137,7 +42219,7 @@ POSSIBILITY OF SUCH DAMAGE.\n CH23 - Channel 23 enable set register. Writing '0' has no effect + Channel 23 enable set register. Writing '0' has no effect. 23 23 @@ -42164,7 +42246,7 @@ POSSIBILITY OF SUCH DAMAGE.\n CH24 - Channel 24 enable set register. Writing '0' has no effect + Channel 24 enable set register. Writing '0' has no effect. 24 24 @@ -42191,7 +42273,7 @@ POSSIBILITY OF SUCH DAMAGE.\n CH25 - Channel 25 enable set register. Writing '0' has no effect + Channel 25 enable set register. Writing '0' has no effect. 25 25 @@ -42218,7 +42300,7 @@ POSSIBILITY OF SUCH DAMAGE.\n CH26 - Channel 26 enable set register. Writing '0' has no effect + Channel 26 enable set register. Writing '0' has no effect. 26 26 @@ -42245,7 +42327,7 @@ POSSIBILITY OF SUCH DAMAGE.\n CH27 - Channel 27 enable set register. Writing '0' has no effect + Channel 27 enable set register. Writing '0' has no effect. 27 27 @@ -42272,7 +42354,7 @@ POSSIBILITY OF SUCH DAMAGE.\n CH28 - Channel 28 enable set register. Writing '0' has no effect + Channel 28 enable set register. Writing '0' has no effect. 28 28 @@ -42299,7 +42381,7 @@ POSSIBILITY OF SUCH DAMAGE.\n CH29 - Channel 29 enable set register. Writing '0' has no effect + Channel 29 enable set register. Writing '0' has no effect. 29 29 @@ -42326,7 +42408,7 @@ POSSIBILITY OF SUCH DAMAGE.\n CH30 - Channel 30 enable set register. Writing '0' has no effect + Channel 30 enable set register. Writing '0' has no effect. 30 30 @@ -42353,7 +42435,7 @@ POSSIBILITY OF SUCH DAMAGE.\n CH31 - Channel 31 enable set register. Writing '0' has no effect + Channel 31 enable set register. Writing '0' has no effect. 31 31 @@ -42389,7 +42471,7 @@ POSSIBILITY OF SUCH DAMAGE.\n CH0 - Channel 0 enable clear register. Writing '0' has no effect + Channel 0 enable clear register. Writing '0' has no effect. 0 0 @@ -42416,7 +42498,7 @@ POSSIBILITY OF SUCH DAMAGE.\n CH1 - Channel 1 enable clear register. Writing '0' has no effect + Channel 1 enable clear register. Writing '0' has no effect. 1 1 @@ -42443,7 +42525,7 @@ POSSIBILITY OF SUCH DAMAGE.\n CH2 - Channel 2 enable clear register. Writing '0' has no effect + Channel 2 enable clear register. Writing '0' has no effect. 2 2 @@ -42470,7 +42552,7 @@ POSSIBILITY OF SUCH DAMAGE.\n CH3 - Channel 3 enable clear register. Writing '0' has no effect + Channel 3 enable clear register. Writing '0' has no effect. 3 3 @@ -42497,7 +42579,7 @@ POSSIBILITY OF SUCH DAMAGE.\n CH4 - Channel 4 enable clear register. Writing '0' has no effect + Channel 4 enable clear register. Writing '0' has no effect. 4 4 @@ -42524,7 +42606,7 @@ POSSIBILITY OF SUCH DAMAGE.\n CH5 - Channel 5 enable clear register. Writing '0' has no effect + Channel 5 enable clear register. Writing '0' has no effect. 5 5 @@ -42551,7 +42633,7 @@ POSSIBILITY OF SUCH DAMAGE.\n CH6 - Channel 6 enable clear register. Writing '0' has no effect + Channel 6 enable clear register. Writing '0' has no effect. 6 6 @@ -42578,7 +42660,7 @@ POSSIBILITY OF SUCH DAMAGE.\n CH7 - Channel 7 enable clear register. Writing '0' has no effect + Channel 7 enable clear register. Writing '0' has no effect. 7 7 @@ -42605,7 +42687,7 @@ POSSIBILITY OF SUCH DAMAGE.\n CH8 - Channel 8 enable clear register. Writing '0' has no effect + Channel 8 enable clear register. Writing '0' has no effect. 8 8 @@ -42632,7 +42714,7 @@ POSSIBILITY OF SUCH DAMAGE.\n CH9 - Channel 9 enable clear register. Writing '0' has no effect + Channel 9 enable clear register. Writing '0' has no effect. 9 9 @@ -42659,7 +42741,7 @@ POSSIBILITY OF SUCH DAMAGE.\n CH10 - Channel 10 enable clear register. Writing '0' has no effect + Channel 10 enable clear register. Writing '0' has no effect. 10 10 @@ -42686,7 +42768,7 @@ POSSIBILITY OF SUCH DAMAGE.\n CH11 - Channel 11 enable clear register. Writing '0' has no effect + Channel 11 enable clear register. Writing '0' has no effect. 11 11 @@ -42713,7 +42795,7 @@ POSSIBILITY OF SUCH DAMAGE.\n CH12 - Channel 12 enable clear register. Writing '0' has no effect + Channel 12 enable clear register. Writing '0' has no effect. 12 12 @@ -42740,7 +42822,7 @@ POSSIBILITY OF SUCH DAMAGE.\n CH13 - Channel 13 enable clear register. Writing '0' has no effect + Channel 13 enable clear register. Writing '0' has no effect. 13 13 @@ -42767,7 +42849,7 @@ POSSIBILITY OF SUCH DAMAGE.\n CH14 - Channel 14 enable clear register. Writing '0' has no effect + Channel 14 enable clear register. Writing '0' has no effect. 14 14 @@ -42794,7 +42876,7 @@ POSSIBILITY OF SUCH DAMAGE.\n CH15 - Channel 15 enable clear register. Writing '0' has no effect + Channel 15 enable clear register. Writing '0' has no effect. 15 15 @@ -42821,7 +42903,7 @@ POSSIBILITY OF SUCH DAMAGE.\n CH16 - Channel 16 enable clear register. Writing '0' has no effect + Channel 16 enable clear register. Writing '0' has no effect. 16 16 @@ -42848,7 +42930,7 @@ POSSIBILITY OF SUCH DAMAGE.\n CH17 - Channel 17 enable clear register. Writing '0' has no effect + Channel 17 enable clear register. Writing '0' has no effect. 17 17 @@ -42875,7 +42957,7 @@ POSSIBILITY OF SUCH DAMAGE.\n CH18 - Channel 18 enable clear register. Writing '0' has no effect + Channel 18 enable clear register. Writing '0' has no effect. 18 18 @@ -42902,7 +42984,7 @@ POSSIBILITY OF SUCH DAMAGE.\n CH19 - Channel 19 enable clear register. Writing '0' has no effect + Channel 19 enable clear register. Writing '0' has no effect. 19 19 @@ -42929,7 +43011,7 @@ POSSIBILITY OF SUCH DAMAGE.\n CH20 - Channel 20 enable clear register. Writing '0' has no effect + Channel 20 enable clear register. Writing '0' has no effect. 20 20 @@ -42956,7 +43038,7 @@ POSSIBILITY OF SUCH DAMAGE.\n CH21 - Channel 21 enable clear register. Writing '0' has no effect + Channel 21 enable clear register. Writing '0' has no effect. 21 21 @@ -42983,7 +43065,7 @@ POSSIBILITY OF SUCH DAMAGE.\n CH22 - Channel 22 enable clear register. Writing '0' has no effect + Channel 22 enable clear register. Writing '0' has no effect. 22 22 @@ -43010,7 +43092,7 @@ POSSIBILITY OF SUCH DAMAGE.\n CH23 - Channel 23 enable clear register. Writing '0' has no effect + Channel 23 enable clear register. Writing '0' has no effect. 23 23 @@ -43037,7 +43119,7 @@ POSSIBILITY OF SUCH DAMAGE.\n CH24 - Channel 24 enable clear register. Writing '0' has no effect + Channel 24 enable clear register. Writing '0' has no effect. 24 24 @@ -43064,7 +43146,7 @@ POSSIBILITY OF SUCH DAMAGE.\n CH25 - Channel 25 enable clear register. Writing '0' has no effect + Channel 25 enable clear register. Writing '0' has no effect. 25 25 @@ -43091,7 +43173,7 @@ POSSIBILITY OF SUCH DAMAGE.\n CH26 - Channel 26 enable clear register. Writing '0' has no effect + Channel 26 enable clear register. Writing '0' has no effect. 26 26 @@ -43118,7 +43200,7 @@ POSSIBILITY OF SUCH DAMAGE.\n CH27 - Channel 27 enable clear register. Writing '0' has no effect + Channel 27 enable clear register. Writing '0' has no effect. 27 27 @@ -43145,7 +43227,7 @@ POSSIBILITY OF SUCH DAMAGE.\n CH28 - Channel 28 enable clear register. Writing '0' has no effect + Channel 28 enable clear register. Writing '0' has no effect. 28 28 @@ -43172,7 +43254,7 @@ POSSIBILITY OF SUCH DAMAGE.\n CH29 - Channel 29 enable clear register. Writing '0' has no effect + Channel 29 enable clear register. Writing '0' has no effect. 29 29 @@ -43199,7 +43281,7 @@ POSSIBILITY OF SUCH DAMAGE.\n CH30 - Channel 30 enable clear register. Writing '0' has no effect + Channel 30 enable clear register. Writing '0' has no effect. 30 30 @@ -43226,7 +43308,7 @@ POSSIBILITY OF SUCH DAMAGE.\n CH31 - Channel 31 enable clear register. Writing '0' has no effect + Channel 31 enable clear register. Writing '0' has no effect. 31 31 @@ -43263,7 +43345,7 @@ POSSIBILITY OF SUCH DAMAGE.\n 0x510 EEP - Description cluster: Channel n event end-point + Description cluster: Channel n event endpoint 0x000 read-write @@ -43277,7 +43359,7 @@ POSSIBILITY OF SUCH DAMAGE.\n TEP - Description cluster: Channel n task end-point + Description cluster: Channel n task endpoint 0x004 read-write @@ -43886,7 +43968,7 @@ POSSIBILITY OF SUCH DAMAGE.\n 0x910 TEP - Description cluster: Channel n task end-point + Description cluster: Channel n task endpoint 0x000 read-write @@ -53713,7 +53795,7 @@ POSSIBILITY OF SUCH DAMAGE.\n OneDir - Full buffer dedicated to either iso IN or OUT + Full buffer dedicated to either ISO IN or OUT 0x0000 diff --git a/mdk/nrf52833_bitfields.h b/mdk/nrf52833_bitfields.h index d256fbb1ae..372472b215 100644 --- a/mdk/nrf52833_bitfields.h +++ b/mdk/nrf52833_bitfields.h @@ -1,6 +1,8 @@ /* -Copyright (c) 2010 - 2020, Nordic Semiconductor ASA All rights reserved. +Copyright (c) 2010 - 2021, Nordic Semiconductor ASA All rights reserved. + +SPDX-License-Identifier: BSD-3-Clause Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: @@ -148,7 +150,7 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: AAR_NIRK */ /* Description: Number of IRKs */ -/* Bits 4..0 : Number of Identity root keys available in the IRK data structure */ +/* Bits 4..0 : Number of Identity Root Keys available in the IRK data structure */ #define AAR_NIRK_NIRK_Pos (0UL) /*!< Position of NIRK field. */ #define AAR_NIRK_NIRK_Msk (0x1FUL << AAR_NIRK_NIRK_Pos) /*!< Bit mask of NIRK field. */ @@ -178,9 +180,9 @@ POSSIBILITY OF SUCH DAMAGE. /* Description: Access control lists */ /* Register: ACL_ACL_ADDR */ -/* Description: Description cluster: Configure the word-aligned start address of region n to protect */ +/* Description: Description cluster: Start address of region to protect. The start address must be word-aligned. */ -/* Bits 31..0 : Valid word-aligned start address of region n to protect. Address must point to a flash page boundary. */ +/* Bits 31..0 : Start address of flash region n. The start address must point to a flash page boundary. */ #define ACL_ACL_ADDR_ADDR_Pos (0UL) /*!< Position of ADDR field. */ #define ACL_ACL_ADDR_ADDR_Msk (0xFFFFFFFFUL << ACL_ACL_ADDR_ADDR_Pos) /*!< Bit mask of ADDR field. */ @@ -207,13 +209,33 @@ POSSIBILITY OF SUCH DAMAGE. #define ACL_ACL_PERM_WRITE_Disable (1UL) /*!< Block write and erase instructions to region n */ +/* Peripheral: APPROTECT */ +/* Description: Access Port Protection */ + +/* Register: APPROTECT_FORCEPROTECT */ +/* Description: Software force enable APPROTECT mechanism until next reset. */ + +/* Bits 7..0 : Write 0x0 to force enable APPROTECT mechanism */ +#define APPROTECT_FORCEPROTECT_FORCEPROTECT_Pos (0UL) /*!< Position of FORCEPROTECT field. */ +#define APPROTECT_FORCEPROTECT_FORCEPROTECT_Msk (0xFFUL << APPROTECT_FORCEPROTECT_FORCEPROTECT_Pos) /*!< Bit mask of FORCEPROTECT field. */ +#define APPROTECT_FORCEPROTECT_FORCEPROTECT_Force (0x0UL) /*!< Software force enable APPROTECT mechanism */ + +/* Register: APPROTECT_DISABLE */ +/* Description: Software disable APPROTECT mechanism */ + +/* Bits 7..0 : Software disable APPROTECT mechanism */ +#define APPROTECT_DISABLE_DISABLE_Pos (0UL) /*!< Position of DISABLE field. */ +#define APPROTECT_DISABLE_DISABLE_Msk (0xFFUL << APPROTECT_DISABLE_DISABLE_Pos) /*!< Bit mask of DISABLE field. */ +#define APPROTECT_DISABLE_DISABLE_SwDisable (0x5AUL) /*!< Software disable APPROTECT mechanism */ + + /* Peripheral: CCM */ /* Description: AES CCM Mode Encryption */ /* Register: CCM_TASKS_KSGEN */ -/* Description: Start generation of key-stream. This operation will stop by itself when completed. */ +/* Description: Start generation of keystream. This operation will stop by itself when completed. */ -/* Bit 0 : Start generation of key-stream. This operation will stop by itself when completed. */ +/* Bit 0 : Start generation of keystream. This operation will stop by itself when completed. */ #define CCM_TASKS_KSGEN_TASKS_KSGEN_Pos (0UL) /*!< Position of TASKS_KSGEN field. */ #define CCM_TASKS_KSGEN_TASKS_KSGEN_Msk (0x1UL << CCM_TASKS_KSGEN_TASKS_KSGEN_Pos) /*!< Bit mask of TASKS_KSGEN field. */ #define CCM_TASKS_KSGEN_TASKS_KSGEN_Trigger (1UL) /*!< Trigger task */ @@ -243,9 +265,9 @@ POSSIBILITY OF SUCH DAMAGE. #define CCM_TASKS_RATEOVERRIDE_TASKS_RATEOVERRIDE_Trigger (1UL) /*!< Trigger task */ /* Register: CCM_EVENTS_ENDKSGEN */ -/* Description: Key-stream generation complete */ +/* Description: Keystream generation complete */ -/* Bit 0 : Key-stream generation complete */ +/* Bit 0 : Keystream generation complete */ #define CCM_EVENTS_ENDKSGEN_EVENTS_ENDKSGEN_Pos (0UL) /*!< Position of EVENTS_ENDKSGEN field. */ #define CCM_EVENTS_ENDKSGEN_EVENTS_ENDKSGEN_Msk (0x1UL << CCM_EVENTS_ENDKSGEN_EVENTS_ENDKSGEN_Pos) /*!< Bit mask of EVENTS_ENDKSGEN field. */ #define CCM_EVENTS_ENDKSGEN_EVENTS_ENDKSGEN_NotGenerated (0UL) /*!< Event not generated */ @@ -350,8 +372,8 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 24 : Packet length configuration */ #define CCM_MODE_LENGTH_Pos (24UL) /*!< Position of LENGTH field. */ #define CCM_MODE_LENGTH_Msk (0x1UL << CCM_MODE_LENGTH_Pos) /*!< Bit mask of LENGTH field. */ -#define CCM_MODE_LENGTH_Default (0UL) /*!< Default length. Effective length of LENGTH field in encrypted/decrypted packet is 5 bits. A key-stream for packet payloads up to 27 bytes will be generated. */ -#define CCM_MODE_LENGTH_Extended (1UL) /*!< Extended length. Effective length of LENGTH field in encrypted/decrypted packet is 8 bits. A key-stream for packet payloads up to MAXPACKETSIZE bytes will be generated. */ +#define CCM_MODE_LENGTH_Default (0UL) /*!< Default length. Effective length of LENGTH field in encrypted/decrypted packet is 5 bits. A keystream for packet payloads up to 27 bytes will be generated. */ +#define CCM_MODE_LENGTH_Extended (1UL) /*!< Extended length. Effective length of LENGTH field in encrypted/decrypted packet is 8 bits. A keystream for packet payloads up to MAXPACKETSIZE bytes will be generated. */ /* Bits 17..16 : Radio data rate that the CCM shall run synchronous with */ #define CCM_MODE_DATARATE_Pos (16UL) /*!< Position of DATARATE field. */ @@ -391,15 +413,15 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: CCM_SCRATCHPTR */ /* Description: Pointer to data area used for temporary storage */ -/* Bits 31..0 : Pointer to a scratch data area used for temporary storage during key-stream generation, +/* Bits 31..0 : Pointer to a scratch data area used for temporary storage during keystream generation, MIC generation and encryption/decryption. */ #define CCM_SCRATCHPTR_SCRATCHPTR_Pos (0UL) /*!< Position of SCRATCHPTR field. */ #define CCM_SCRATCHPTR_SCRATCHPTR_Msk (0xFFFFFFFFUL << CCM_SCRATCHPTR_SCRATCHPTR_Pos) /*!< Bit mask of SCRATCHPTR field. */ /* Register: CCM_MAXPACKETSIZE */ -/* Description: Length of key-stream generated when MODE.LENGTH = Extended. */ +/* Description: Length of keystream generated when MODE.LENGTH = Extended. */ -/* Bits 7..0 : Length of key-stream generated when MODE.LENGTH = Extended. This value must be greater or equal to the subsequent packet payload to be encrypted/decrypted. */ +/* Bits 7..0 : Length of keystream generated when MODE.LENGTH = Extended. This value must be greater or equal to the subsequent packet payload to be encrypted/decrypted. */ #define CCM_MAXPACKETSIZE_MAXPACKETSIZE_Pos (0UL) /*!< Position of MAXPACKETSIZE field. */ #define CCM_MAXPACKETSIZE_MAXPACKETSIZE_Msk (0xFFUL << CCM_MAXPACKETSIZE_MAXPACKETSIZE_Pos) /*!< Bit mask of MAXPACKETSIZE field. */ @@ -1514,6 +1536,7 @@ POSSIBILITY OF SUCH DAMAGE. /* Bits 31..0 : Part code */ #define FICR_INFO_PART_PART_Pos (0UL) /*!< Position of PART field. */ #define FICR_INFO_PART_PART_Msk (0xFFFFFFFFUL << FICR_INFO_PART_PART_Pos) /*!< Bit mask of PART field. */ +#define FICR_INFO_PART_PART_N52820 (0x52820UL) /*!< nRF52820 */ #define FICR_INFO_PART_PART_N52833 (0x52833UL) /*!< nRF52833 */ #define FICR_INFO_PART_PART_N52840 (0x52840UL) /*!< nRF52840 */ #define FICR_INFO_PART_PART_Unspecified (0xFFFFFFFFUL) /*!< Unspecified */ @@ -1524,6 +1547,8 @@ POSSIBILITY OF SUCH DAMAGE. /* Bits 31..0 : Build code (hardware version and production configuration). Encoded as ASCII. */ #define FICR_INFO_VARIANT_VARIANT_Pos (0UL) /*!< Position of VARIANT field. */ #define FICR_INFO_VARIANT_VARIANT_Msk (0xFFFFFFFFUL << FICR_INFO_VARIANT_VARIANT_Pos) /*!< Bit mask of VARIANT field. */ +#define FICR_INFO_VARIANT_VARIANT_AAA0 (0x41414130UL) /*!< AAA0 */ +#define FICR_INFO_VARIANT_VARIANT_AAA1 (0x41414131UL) /*!< AAA1 */ #define FICR_INFO_VARIANT_VARIANT_AAAA (0x41414141UL) /*!< AAAA */ #define FICR_INFO_VARIANT_VARIANT_AAAB (0x41414142UL) /*!< AAAB */ #define FICR_INFO_VARIANT_VARIANT_Unspecified (0xFFFFFFFFUL) /*!< Unspecified */ @@ -1534,9 +1559,9 @@ POSSIBILITY OF SUCH DAMAGE. /* Bits 31..0 : Package option */ #define FICR_INFO_PACKAGE_PACKAGE_Pos (0UL) /*!< Position of PACKAGE field. */ #define FICR_INFO_PACKAGE_PACKAGE_Msk (0xFFFFFFFFUL << FICR_INFO_PACKAGE_PACKAGE_Pos) /*!< Bit mask of PACKAGE field. */ -#define FICR_INFO_PACKAGE_PACKAGE_QI (0x2004UL) /*!< QIxx - 73-pin aQFN */ -#define FICR_INFO_PACKAGE_PACKAGE_QD (0x2007UL) /*!< QDxx - 40-pin QFN */ -#define FICR_INFO_PACKAGE_PACKAGE_CJ (0x2008UL) /*!< CJxx - WLCSP */ +#define FICR_INFO_PACKAGE_PACKAGE_QI (0x2004UL) /*!< QIxx - 7x7 73-pin aQFN */ +#define FICR_INFO_PACKAGE_PACKAGE_QD (0x2007UL) /*!< QDxx - 5x5 40-pin QFN */ +#define FICR_INFO_PACKAGE_PACKAGE_CJ (0x2008UL) /*!< CJxx - 3.175 x 3.175 WLCSP */ #define FICR_INFO_PACKAGE_PACKAGE_Unspecified (0xFFFFFFFFUL) /*!< Unspecified */ /* Register: FICR_INFO_RAM */ @@ -5130,224 +5155,224 @@ POSSIBILITY OF SUCH DAMAGE. #define GPIO_OUTSET_PIN31_Msk (0x1UL << GPIO_OUTSET_PIN31_Pos) /*!< Bit mask of PIN31 field. */ #define GPIO_OUTSET_PIN31_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTSET_PIN31_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTSET_PIN31_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ +#define GPIO_OUTSET_PIN31_Set (1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */ /* Bit 30 : Pin 30 */ #define GPIO_OUTSET_PIN30_Pos (30UL) /*!< Position of PIN30 field. */ #define GPIO_OUTSET_PIN30_Msk (0x1UL << GPIO_OUTSET_PIN30_Pos) /*!< Bit mask of PIN30 field. */ #define GPIO_OUTSET_PIN30_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTSET_PIN30_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTSET_PIN30_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ +#define GPIO_OUTSET_PIN30_Set (1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */ /* Bit 29 : Pin 29 */ #define GPIO_OUTSET_PIN29_Pos (29UL) /*!< Position of PIN29 field. */ #define GPIO_OUTSET_PIN29_Msk (0x1UL << GPIO_OUTSET_PIN29_Pos) /*!< Bit mask of PIN29 field. */ #define GPIO_OUTSET_PIN29_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTSET_PIN29_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTSET_PIN29_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ +#define GPIO_OUTSET_PIN29_Set (1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */ /* Bit 28 : Pin 28 */ #define GPIO_OUTSET_PIN28_Pos (28UL) /*!< Position of PIN28 field. */ #define GPIO_OUTSET_PIN28_Msk (0x1UL << GPIO_OUTSET_PIN28_Pos) /*!< Bit mask of PIN28 field. */ #define GPIO_OUTSET_PIN28_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTSET_PIN28_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTSET_PIN28_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ +#define GPIO_OUTSET_PIN28_Set (1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */ /* Bit 27 : Pin 27 */ #define GPIO_OUTSET_PIN27_Pos (27UL) /*!< Position of PIN27 field. */ #define GPIO_OUTSET_PIN27_Msk (0x1UL << GPIO_OUTSET_PIN27_Pos) /*!< Bit mask of PIN27 field. */ #define GPIO_OUTSET_PIN27_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTSET_PIN27_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTSET_PIN27_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ +#define GPIO_OUTSET_PIN27_Set (1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */ /* Bit 26 : Pin 26 */ #define GPIO_OUTSET_PIN26_Pos (26UL) /*!< Position of PIN26 field. */ #define GPIO_OUTSET_PIN26_Msk (0x1UL << GPIO_OUTSET_PIN26_Pos) /*!< Bit mask of PIN26 field. */ #define GPIO_OUTSET_PIN26_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTSET_PIN26_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTSET_PIN26_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ +#define GPIO_OUTSET_PIN26_Set (1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */ /* Bit 25 : Pin 25 */ #define GPIO_OUTSET_PIN25_Pos (25UL) /*!< Position of PIN25 field. */ #define GPIO_OUTSET_PIN25_Msk (0x1UL << GPIO_OUTSET_PIN25_Pos) /*!< Bit mask of PIN25 field. */ #define GPIO_OUTSET_PIN25_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTSET_PIN25_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTSET_PIN25_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ +#define GPIO_OUTSET_PIN25_Set (1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */ /* Bit 24 : Pin 24 */ #define GPIO_OUTSET_PIN24_Pos (24UL) /*!< Position of PIN24 field. */ #define GPIO_OUTSET_PIN24_Msk (0x1UL << GPIO_OUTSET_PIN24_Pos) /*!< Bit mask of PIN24 field. */ #define GPIO_OUTSET_PIN24_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTSET_PIN24_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTSET_PIN24_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ +#define GPIO_OUTSET_PIN24_Set (1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */ /* Bit 23 : Pin 23 */ #define GPIO_OUTSET_PIN23_Pos (23UL) /*!< Position of PIN23 field. */ #define GPIO_OUTSET_PIN23_Msk (0x1UL << GPIO_OUTSET_PIN23_Pos) /*!< Bit mask of PIN23 field. */ #define GPIO_OUTSET_PIN23_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTSET_PIN23_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTSET_PIN23_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ +#define GPIO_OUTSET_PIN23_Set (1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */ /* Bit 22 : Pin 22 */ #define GPIO_OUTSET_PIN22_Pos (22UL) /*!< Position of PIN22 field. */ #define GPIO_OUTSET_PIN22_Msk (0x1UL << GPIO_OUTSET_PIN22_Pos) /*!< Bit mask of PIN22 field. */ #define GPIO_OUTSET_PIN22_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTSET_PIN22_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTSET_PIN22_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ +#define GPIO_OUTSET_PIN22_Set (1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */ /* Bit 21 : Pin 21 */ #define GPIO_OUTSET_PIN21_Pos (21UL) /*!< Position of PIN21 field. */ #define GPIO_OUTSET_PIN21_Msk (0x1UL << GPIO_OUTSET_PIN21_Pos) /*!< Bit mask of PIN21 field. */ #define GPIO_OUTSET_PIN21_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTSET_PIN21_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTSET_PIN21_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ +#define GPIO_OUTSET_PIN21_Set (1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */ /* Bit 20 : Pin 20 */ #define GPIO_OUTSET_PIN20_Pos (20UL) /*!< Position of PIN20 field. */ #define GPIO_OUTSET_PIN20_Msk (0x1UL << GPIO_OUTSET_PIN20_Pos) /*!< Bit mask of PIN20 field. */ #define GPIO_OUTSET_PIN20_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTSET_PIN20_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTSET_PIN20_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ +#define GPIO_OUTSET_PIN20_Set (1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */ /* Bit 19 : Pin 19 */ #define GPIO_OUTSET_PIN19_Pos (19UL) /*!< Position of PIN19 field. */ #define GPIO_OUTSET_PIN19_Msk (0x1UL << GPIO_OUTSET_PIN19_Pos) /*!< Bit mask of PIN19 field. */ #define GPIO_OUTSET_PIN19_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTSET_PIN19_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTSET_PIN19_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ +#define GPIO_OUTSET_PIN19_Set (1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */ /* Bit 18 : Pin 18 */ #define GPIO_OUTSET_PIN18_Pos (18UL) /*!< Position of PIN18 field. */ #define GPIO_OUTSET_PIN18_Msk (0x1UL << GPIO_OUTSET_PIN18_Pos) /*!< Bit mask of PIN18 field. */ #define GPIO_OUTSET_PIN18_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTSET_PIN18_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTSET_PIN18_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ +#define GPIO_OUTSET_PIN18_Set (1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */ /* Bit 17 : Pin 17 */ #define GPIO_OUTSET_PIN17_Pos (17UL) /*!< Position of PIN17 field. */ #define GPIO_OUTSET_PIN17_Msk (0x1UL << GPIO_OUTSET_PIN17_Pos) /*!< Bit mask of PIN17 field. */ #define GPIO_OUTSET_PIN17_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTSET_PIN17_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTSET_PIN17_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ +#define GPIO_OUTSET_PIN17_Set (1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */ /* Bit 16 : Pin 16 */ #define GPIO_OUTSET_PIN16_Pos (16UL) /*!< Position of PIN16 field. */ #define GPIO_OUTSET_PIN16_Msk (0x1UL << GPIO_OUTSET_PIN16_Pos) /*!< Bit mask of PIN16 field. */ #define GPIO_OUTSET_PIN16_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTSET_PIN16_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTSET_PIN16_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ +#define GPIO_OUTSET_PIN16_Set (1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */ /* Bit 15 : Pin 15 */ #define GPIO_OUTSET_PIN15_Pos (15UL) /*!< Position of PIN15 field. */ #define GPIO_OUTSET_PIN15_Msk (0x1UL << GPIO_OUTSET_PIN15_Pos) /*!< Bit mask of PIN15 field. */ #define GPIO_OUTSET_PIN15_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTSET_PIN15_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTSET_PIN15_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ +#define GPIO_OUTSET_PIN15_Set (1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */ /* Bit 14 : Pin 14 */ #define GPIO_OUTSET_PIN14_Pos (14UL) /*!< Position of PIN14 field. */ #define GPIO_OUTSET_PIN14_Msk (0x1UL << GPIO_OUTSET_PIN14_Pos) /*!< Bit mask of PIN14 field. */ #define GPIO_OUTSET_PIN14_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTSET_PIN14_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTSET_PIN14_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ +#define GPIO_OUTSET_PIN14_Set (1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */ /* Bit 13 : Pin 13 */ #define GPIO_OUTSET_PIN13_Pos (13UL) /*!< Position of PIN13 field. */ #define GPIO_OUTSET_PIN13_Msk (0x1UL << GPIO_OUTSET_PIN13_Pos) /*!< Bit mask of PIN13 field. */ #define GPIO_OUTSET_PIN13_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTSET_PIN13_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTSET_PIN13_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ +#define GPIO_OUTSET_PIN13_Set (1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */ /* Bit 12 : Pin 12 */ #define GPIO_OUTSET_PIN12_Pos (12UL) /*!< Position of PIN12 field. */ #define GPIO_OUTSET_PIN12_Msk (0x1UL << GPIO_OUTSET_PIN12_Pos) /*!< Bit mask of PIN12 field. */ #define GPIO_OUTSET_PIN12_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTSET_PIN12_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTSET_PIN12_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ +#define GPIO_OUTSET_PIN12_Set (1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */ /* Bit 11 : Pin 11 */ #define GPIO_OUTSET_PIN11_Pos (11UL) /*!< Position of PIN11 field. */ #define GPIO_OUTSET_PIN11_Msk (0x1UL << GPIO_OUTSET_PIN11_Pos) /*!< Bit mask of PIN11 field. */ #define GPIO_OUTSET_PIN11_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTSET_PIN11_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTSET_PIN11_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ +#define GPIO_OUTSET_PIN11_Set (1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */ /* Bit 10 : Pin 10 */ #define GPIO_OUTSET_PIN10_Pos (10UL) /*!< Position of PIN10 field. */ #define GPIO_OUTSET_PIN10_Msk (0x1UL << GPIO_OUTSET_PIN10_Pos) /*!< Bit mask of PIN10 field. */ #define GPIO_OUTSET_PIN10_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTSET_PIN10_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTSET_PIN10_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ +#define GPIO_OUTSET_PIN10_Set (1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */ /* Bit 9 : Pin 9 */ #define GPIO_OUTSET_PIN9_Pos (9UL) /*!< Position of PIN9 field. */ #define GPIO_OUTSET_PIN9_Msk (0x1UL << GPIO_OUTSET_PIN9_Pos) /*!< Bit mask of PIN9 field. */ #define GPIO_OUTSET_PIN9_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTSET_PIN9_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTSET_PIN9_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ +#define GPIO_OUTSET_PIN9_Set (1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */ /* Bit 8 : Pin 8 */ #define GPIO_OUTSET_PIN8_Pos (8UL) /*!< Position of PIN8 field. */ #define GPIO_OUTSET_PIN8_Msk (0x1UL << GPIO_OUTSET_PIN8_Pos) /*!< Bit mask of PIN8 field. */ #define GPIO_OUTSET_PIN8_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTSET_PIN8_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTSET_PIN8_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ +#define GPIO_OUTSET_PIN8_Set (1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */ /* Bit 7 : Pin 7 */ #define GPIO_OUTSET_PIN7_Pos (7UL) /*!< Position of PIN7 field. */ #define GPIO_OUTSET_PIN7_Msk (0x1UL << GPIO_OUTSET_PIN7_Pos) /*!< Bit mask of PIN7 field. */ #define GPIO_OUTSET_PIN7_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTSET_PIN7_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTSET_PIN7_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ +#define GPIO_OUTSET_PIN7_Set (1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */ /* Bit 6 : Pin 6 */ #define GPIO_OUTSET_PIN6_Pos (6UL) /*!< Position of PIN6 field. */ #define GPIO_OUTSET_PIN6_Msk (0x1UL << GPIO_OUTSET_PIN6_Pos) /*!< Bit mask of PIN6 field. */ #define GPIO_OUTSET_PIN6_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTSET_PIN6_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTSET_PIN6_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ +#define GPIO_OUTSET_PIN6_Set (1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */ /* Bit 5 : Pin 5 */ #define GPIO_OUTSET_PIN5_Pos (5UL) /*!< Position of PIN5 field. */ #define GPIO_OUTSET_PIN5_Msk (0x1UL << GPIO_OUTSET_PIN5_Pos) /*!< Bit mask of PIN5 field. */ #define GPIO_OUTSET_PIN5_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTSET_PIN5_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTSET_PIN5_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ +#define GPIO_OUTSET_PIN5_Set (1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */ /* Bit 4 : Pin 4 */ #define GPIO_OUTSET_PIN4_Pos (4UL) /*!< Position of PIN4 field. */ #define GPIO_OUTSET_PIN4_Msk (0x1UL << GPIO_OUTSET_PIN4_Pos) /*!< Bit mask of PIN4 field. */ #define GPIO_OUTSET_PIN4_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTSET_PIN4_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTSET_PIN4_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ +#define GPIO_OUTSET_PIN4_Set (1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */ /* Bit 3 : Pin 3 */ #define GPIO_OUTSET_PIN3_Pos (3UL) /*!< Position of PIN3 field. */ #define GPIO_OUTSET_PIN3_Msk (0x1UL << GPIO_OUTSET_PIN3_Pos) /*!< Bit mask of PIN3 field. */ #define GPIO_OUTSET_PIN3_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTSET_PIN3_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTSET_PIN3_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ +#define GPIO_OUTSET_PIN3_Set (1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */ /* Bit 2 : Pin 2 */ #define GPIO_OUTSET_PIN2_Pos (2UL) /*!< Position of PIN2 field. */ #define GPIO_OUTSET_PIN2_Msk (0x1UL << GPIO_OUTSET_PIN2_Pos) /*!< Bit mask of PIN2 field. */ #define GPIO_OUTSET_PIN2_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTSET_PIN2_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTSET_PIN2_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ +#define GPIO_OUTSET_PIN2_Set (1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */ /* Bit 1 : Pin 1 */ #define GPIO_OUTSET_PIN1_Pos (1UL) /*!< Position of PIN1 field. */ #define GPIO_OUTSET_PIN1_Msk (0x1UL << GPIO_OUTSET_PIN1_Pos) /*!< Bit mask of PIN1 field. */ #define GPIO_OUTSET_PIN1_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTSET_PIN1_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTSET_PIN1_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ +#define GPIO_OUTSET_PIN1_Set (1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */ /* Bit 0 : Pin 0 */ #define GPIO_OUTSET_PIN0_Pos (0UL) /*!< Position of PIN0 field. */ #define GPIO_OUTSET_PIN0_Msk (0x1UL << GPIO_OUTSET_PIN0_Pos) /*!< Bit mask of PIN0 field. */ #define GPIO_OUTSET_PIN0_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTSET_PIN0_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTSET_PIN0_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ +#define GPIO_OUTSET_PIN0_Set (1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */ /* Register: GPIO_OUTCLR */ /* Description: Clear individual bits in GPIO port */ @@ -5357,224 +5382,224 @@ POSSIBILITY OF SUCH DAMAGE. #define GPIO_OUTCLR_PIN31_Msk (0x1UL << GPIO_OUTCLR_PIN31_Pos) /*!< Bit mask of PIN31 field. */ #define GPIO_OUTCLR_PIN31_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTCLR_PIN31_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTCLR_PIN31_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ +#define GPIO_OUTCLR_PIN31_Clear (1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */ /* Bit 30 : Pin 30 */ #define GPIO_OUTCLR_PIN30_Pos (30UL) /*!< Position of PIN30 field. */ #define GPIO_OUTCLR_PIN30_Msk (0x1UL << GPIO_OUTCLR_PIN30_Pos) /*!< Bit mask of PIN30 field. */ #define GPIO_OUTCLR_PIN30_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTCLR_PIN30_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTCLR_PIN30_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ +#define GPIO_OUTCLR_PIN30_Clear (1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */ /* Bit 29 : Pin 29 */ #define GPIO_OUTCLR_PIN29_Pos (29UL) /*!< Position of PIN29 field. */ #define GPIO_OUTCLR_PIN29_Msk (0x1UL << GPIO_OUTCLR_PIN29_Pos) /*!< Bit mask of PIN29 field. */ #define GPIO_OUTCLR_PIN29_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTCLR_PIN29_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTCLR_PIN29_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ +#define GPIO_OUTCLR_PIN29_Clear (1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */ /* Bit 28 : Pin 28 */ #define GPIO_OUTCLR_PIN28_Pos (28UL) /*!< Position of PIN28 field. */ #define GPIO_OUTCLR_PIN28_Msk (0x1UL << GPIO_OUTCLR_PIN28_Pos) /*!< Bit mask of PIN28 field. */ #define GPIO_OUTCLR_PIN28_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTCLR_PIN28_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTCLR_PIN28_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ +#define GPIO_OUTCLR_PIN28_Clear (1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */ /* Bit 27 : Pin 27 */ #define GPIO_OUTCLR_PIN27_Pos (27UL) /*!< Position of PIN27 field. */ #define GPIO_OUTCLR_PIN27_Msk (0x1UL << GPIO_OUTCLR_PIN27_Pos) /*!< Bit mask of PIN27 field. */ #define GPIO_OUTCLR_PIN27_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTCLR_PIN27_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTCLR_PIN27_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ +#define GPIO_OUTCLR_PIN27_Clear (1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */ /* Bit 26 : Pin 26 */ #define GPIO_OUTCLR_PIN26_Pos (26UL) /*!< Position of PIN26 field. */ #define GPIO_OUTCLR_PIN26_Msk (0x1UL << GPIO_OUTCLR_PIN26_Pos) /*!< Bit mask of PIN26 field. */ #define GPIO_OUTCLR_PIN26_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTCLR_PIN26_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTCLR_PIN26_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ +#define GPIO_OUTCLR_PIN26_Clear (1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */ /* Bit 25 : Pin 25 */ #define GPIO_OUTCLR_PIN25_Pos (25UL) /*!< Position of PIN25 field. */ #define GPIO_OUTCLR_PIN25_Msk (0x1UL << GPIO_OUTCLR_PIN25_Pos) /*!< Bit mask of PIN25 field. */ #define GPIO_OUTCLR_PIN25_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTCLR_PIN25_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTCLR_PIN25_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ +#define GPIO_OUTCLR_PIN25_Clear (1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */ /* Bit 24 : Pin 24 */ #define GPIO_OUTCLR_PIN24_Pos (24UL) /*!< Position of PIN24 field. */ #define GPIO_OUTCLR_PIN24_Msk (0x1UL << GPIO_OUTCLR_PIN24_Pos) /*!< Bit mask of PIN24 field. */ #define GPIO_OUTCLR_PIN24_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTCLR_PIN24_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTCLR_PIN24_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ +#define GPIO_OUTCLR_PIN24_Clear (1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */ /* Bit 23 : Pin 23 */ #define GPIO_OUTCLR_PIN23_Pos (23UL) /*!< Position of PIN23 field. */ #define GPIO_OUTCLR_PIN23_Msk (0x1UL << GPIO_OUTCLR_PIN23_Pos) /*!< Bit mask of PIN23 field. */ #define GPIO_OUTCLR_PIN23_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTCLR_PIN23_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTCLR_PIN23_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ +#define GPIO_OUTCLR_PIN23_Clear (1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */ /* Bit 22 : Pin 22 */ #define GPIO_OUTCLR_PIN22_Pos (22UL) /*!< Position of PIN22 field. */ #define GPIO_OUTCLR_PIN22_Msk (0x1UL << GPIO_OUTCLR_PIN22_Pos) /*!< Bit mask of PIN22 field. */ #define GPIO_OUTCLR_PIN22_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTCLR_PIN22_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTCLR_PIN22_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ +#define GPIO_OUTCLR_PIN22_Clear (1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */ /* Bit 21 : Pin 21 */ #define GPIO_OUTCLR_PIN21_Pos (21UL) /*!< Position of PIN21 field. */ #define GPIO_OUTCLR_PIN21_Msk (0x1UL << GPIO_OUTCLR_PIN21_Pos) /*!< Bit mask of PIN21 field. */ #define GPIO_OUTCLR_PIN21_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTCLR_PIN21_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTCLR_PIN21_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ +#define GPIO_OUTCLR_PIN21_Clear (1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */ /* Bit 20 : Pin 20 */ #define GPIO_OUTCLR_PIN20_Pos (20UL) /*!< Position of PIN20 field. */ #define GPIO_OUTCLR_PIN20_Msk (0x1UL << GPIO_OUTCLR_PIN20_Pos) /*!< Bit mask of PIN20 field. */ #define GPIO_OUTCLR_PIN20_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTCLR_PIN20_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTCLR_PIN20_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ +#define GPIO_OUTCLR_PIN20_Clear (1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */ /* Bit 19 : Pin 19 */ #define GPIO_OUTCLR_PIN19_Pos (19UL) /*!< Position of PIN19 field. */ #define GPIO_OUTCLR_PIN19_Msk (0x1UL << GPIO_OUTCLR_PIN19_Pos) /*!< Bit mask of PIN19 field. */ #define GPIO_OUTCLR_PIN19_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTCLR_PIN19_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTCLR_PIN19_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ +#define GPIO_OUTCLR_PIN19_Clear (1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */ /* Bit 18 : Pin 18 */ #define GPIO_OUTCLR_PIN18_Pos (18UL) /*!< Position of PIN18 field. */ #define GPIO_OUTCLR_PIN18_Msk (0x1UL << GPIO_OUTCLR_PIN18_Pos) /*!< Bit mask of PIN18 field. */ #define GPIO_OUTCLR_PIN18_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTCLR_PIN18_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTCLR_PIN18_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ +#define GPIO_OUTCLR_PIN18_Clear (1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */ /* Bit 17 : Pin 17 */ #define GPIO_OUTCLR_PIN17_Pos (17UL) /*!< Position of PIN17 field. */ #define GPIO_OUTCLR_PIN17_Msk (0x1UL << GPIO_OUTCLR_PIN17_Pos) /*!< Bit mask of PIN17 field. */ #define GPIO_OUTCLR_PIN17_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTCLR_PIN17_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTCLR_PIN17_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ +#define GPIO_OUTCLR_PIN17_Clear (1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */ /* Bit 16 : Pin 16 */ #define GPIO_OUTCLR_PIN16_Pos (16UL) /*!< Position of PIN16 field. */ #define GPIO_OUTCLR_PIN16_Msk (0x1UL << GPIO_OUTCLR_PIN16_Pos) /*!< Bit mask of PIN16 field. */ #define GPIO_OUTCLR_PIN16_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTCLR_PIN16_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTCLR_PIN16_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ +#define GPIO_OUTCLR_PIN16_Clear (1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */ /* Bit 15 : Pin 15 */ #define GPIO_OUTCLR_PIN15_Pos (15UL) /*!< Position of PIN15 field. */ #define GPIO_OUTCLR_PIN15_Msk (0x1UL << GPIO_OUTCLR_PIN15_Pos) /*!< Bit mask of PIN15 field. */ #define GPIO_OUTCLR_PIN15_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTCLR_PIN15_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTCLR_PIN15_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ +#define GPIO_OUTCLR_PIN15_Clear (1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */ /* Bit 14 : Pin 14 */ #define GPIO_OUTCLR_PIN14_Pos (14UL) /*!< Position of PIN14 field. */ #define GPIO_OUTCLR_PIN14_Msk (0x1UL << GPIO_OUTCLR_PIN14_Pos) /*!< Bit mask of PIN14 field. */ #define GPIO_OUTCLR_PIN14_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTCLR_PIN14_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTCLR_PIN14_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ +#define GPIO_OUTCLR_PIN14_Clear (1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */ /* Bit 13 : Pin 13 */ #define GPIO_OUTCLR_PIN13_Pos (13UL) /*!< Position of PIN13 field. */ #define GPIO_OUTCLR_PIN13_Msk (0x1UL << GPIO_OUTCLR_PIN13_Pos) /*!< Bit mask of PIN13 field. */ #define GPIO_OUTCLR_PIN13_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTCLR_PIN13_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTCLR_PIN13_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ +#define GPIO_OUTCLR_PIN13_Clear (1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */ /* Bit 12 : Pin 12 */ #define GPIO_OUTCLR_PIN12_Pos (12UL) /*!< Position of PIN12 field. */ #define GPIO_OUTCLR_PIN12_Msk (0x1UL << GPIO_OUTCLR_PIN12_Pos) /*!< Bit mask of PIN12 field. */ #define GPIO_OUTCLR_PIN12_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTCLR_PIN12_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTCLR_PIN12_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ +#define GPIO_OUTCLR_PIN12_Clear (1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */ /* Bit 11 : Pin 11 */ #define GPIO_OUTCLR_PIN11_Pos (11UL) /*!< Position of PIN11 field. */ #define GPIO_OUTCLR_PIN11_Msk (0x1UL << GPIO_OUTCLR_PIN11_Pos) /*!< Bit mask of PIN11 field. */ #define GPIO_OUTCLR_PIN11_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTCLR_PIN11_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTCLR_PIN11_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ +#define GPIO_OUTCLR_PIN11_Clear (1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */ /* Bit 10 : Pin 10 */ #define GPIO_OUTCLR_PIN10_Pos (10UL) /*!< Position of PIN10 field. */ #define GPIO_OUTCLR_PIN10_Msk (0x1UL << GPIO_OUTCLR_PIN10_Pos) /*!< Bit mask of PIN10 field. */ #define GPIO_OUTCLR_PIN10_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTCLR_PIN10_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTCLR_PIN10_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ +#define GPIO_OUTCLR_PIN10_Clear (1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */ /* Bit 9 : Pin 9 */ #define GPIO_OUTCLR_PIN9_Pos (9UL) /*!< Position of PIN9 field. */ #define GPIO_OUTCLR_PIN9_Msk (0x1UL << GPIO_OUTCLR_PIN9_Pos) /*!< Bit mask of PIN9 field. */ #define GPIO_OUTCLR_PIN9_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTCLR_PIN9_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTCLR_PIN9_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ +#define GPIO_OUTCLR_PIN9_Clear (1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */ /* Bit 8 : Pin 8 */ #define GPIO_OUTCLR_PIN8_Pos (8UL) /*!< Position of PIN8 field. */ #define GPIO_OUTCLR_PIN8_Msk (0x1UL << GPIO_OUTCLR_PIN8_Pos) /*!< Bit mask of PIN8 field. */ #define GPIO_OUTCLR_PIN8_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTCLR_PIN8_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTCLR_PIN8_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ +#define GPIO_OUTCLR_PIN8_Clear (1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */ /* Bit 7 : Pin 7 */ #define GPIO_OUTCLR_PIN7_Pos (7UL) /*!< Position of PIN7 field. */ #define GPIO_OUTCLR_PIN7_Msk (0x1UL << GPIO_OUTCLR_PIN7_Pos) /*!< Bit mask of PIN7 field. */ #define GPIO_OUTCLR_PIN7_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTCLR_PIN7_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTCLR_PIN7_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ +#define GPIO_OUTCLR_PIN7_Clear (1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */ /* Bit 6 : Pin 6 */ #define GPIO_OUTCLR_PIN6_Pos (6UL) /*!< Position of PIN6 field. */ #define GPIO_OUTCLR_PIN6_Msk (0x1UL << GPIO_OUTCLR_PIN6_Pos) /*!< Bit mask of PIN6 field. */ #define GPIO_OUTCLR_PIN6_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTCLR_PIN6_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTCLR_PIN6_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ +#define GPIO_OUTCLR_PIN6_Clear (1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */ /* Bit 5 : Pin 5 */ #define GPIO_OUTCLR_PIN5_Pos (5UL) /*!< Position of PIN5 field. */ #define GPIO_OUTCLR_PIN5_Msk (0x1UL << GPIO_OUTCLR_PIN5_Pos) /*!< Bit mask of PIN5 field. */ #define GPIO_OUTCLR_PIN5_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTCLR_PIN5_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTCLR_PIN5_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ +#define GPIO_OUTCLR_PIN5_Clear (1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */ /* Bit 4 : Pin 4 */ #define GPIO_OUTCLR_PIN4_Pos (4UL) /*!< Position of PIN4 field. */ #define GPIO_OUTCLR_PIN4_Msk (0x1UL << GPIO_OUTCLR_PIN4_Pos) /*!< Bit mask of PIN4 field. */ #define GPIO_OUTCLR_PIN4_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTCLR_PIN4_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTCLR_PIN4_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ +#define GPIO_OUTCLR_PIN4_Clear (1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */ /* Bit 3 : Pin 3 */ #define GPIO_OUTCLR_PIN3_Pos (3UL) /*!< Position of PIN3 field. */ #define GPIO_OUTCLR_PIN3_Msk (0x1UL << GPIO_OUTCLR_PIN3_Pos) /*!< Bit mask of PIN3 field. */ #define GPIO_OUTCLR_PIN3_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTCLR_PIN3_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTCLR_PIN3_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ +#define GPIO_OUTCLR_PIN3_Clear (1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */ /* Bit 2 : Pin 2 */ #define GPIO_OUTCLR_PIN2_Pos (2UL) /*!< Position of PIN2 field. */ #define GPIO_OUTCLR_PIN2_Msk (0x1UL << GPIO_OUTCLR_PIN2_Pos) /*!< Bit mask of PIN2 field. */ #define GPIO_OUTCLR_PIN2_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTCLR_PIN2_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTCLR_PIN2_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ +#define GPIO_OUTCLR_PIN2_Clear (1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */ /* Bit 1 : Pin 1 */ #define GPIO_OUTCLR_PIN1_Pos (1UL) /*!< Position of PIN1 field. */ #define GPIO_OUTCLR_PIN1_Msk (0x1UL << GPIO_OUTCLR_PIN1_Pos) /*!< Bit mask of PIN1 field. */ #define GPIO_OUTCLR_PIN1_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTCLR_PIN1_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTCLR_PIN1_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ +#define GPIO_OUTCLR_PIN1_Clear (1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */ /* Bit 0 : Pin 0 */ #define GPIO_OUTCLR_PIN0_Pos (0UL) /*!< Position of PIN0 field. */ #define GPIO_OUTCLR_PIN0_Msk (0x1UL << GPIO_OUTCLR_PIN0_Pos) /*!< Bit mask of PIN0 field. */ #define GPIO_OUTCLR_PIN0_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTCLR_PIN0_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTCLR_PIN0_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ +#define GPIO_OUTCLR_PIN0_Clear (1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */ /* Register: GPIO_IN */ /* Description: Read GPIO port */ @@ -5974,224 +5999,224 @@ POSSIBILITY OF SUCH DAMAGE. #define GPIO_DIRSET_PIN31_Msk (0x1UL << GPIO_DIRSET_PIN31_Pos) /*!< Bit mask of PIN31 field. */ #define GPIO_DIRSET_PIN31_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRSET_PIN31_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRSET_PIN31_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ +#define GPIO_DIRSET_PIN31_Set (1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */ /* Bit 30 : Set as output pin 30 */ #define GPIO_DIRSET_PIN30_Pos (30UL) /*!< Position of PIN30 field. */ #define GPIO_DIRSET_PIN30_Msk (0x1UL << GPIO_DIRSET_PIN30_Pos) /*!< Bit mask of PIN30 field. */ #define GPIO_DIRSET_PIN30_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRSET_PIN30_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRSET_PIN30_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ +#define GPIO_DIRSET_PIN30_Set (1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */ /* Bit 29 : Set as output pin 29 */ #define GPIO_DIRSET_PIN29_Pos (29UL) /*!< Position of PIN29 field. */ #define GPIO_DIRSET_PIN29_Msk (0x1UL << GPIO_DIRSET_PIN29_Pos) /*!< Bit mask of PIN29 field. */ #define GPIO_DIRSET_PIN29_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRSET_PIN29_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRSET_PIN29_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ +#define GPIO_DIRSET_PIN29_Set (1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */ /* Bit 28 : Set as output pin 28 */ #define GPIO_DIRSET_PIN28_Pos (28UL) /*!< Position of PIN28 field. */ #define GPIO_DIRSET_PIN28_Msk (0x1UL << GPIO_DIRSET_PIN28_Pos) /*!< Bit mask of PIN28 field. */ #define GPIO_DIRSET_PIN28_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRSET_PIN28_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRSET_PIN28_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ +#define GPIO_DIRSET_PIN28_Set (1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */ /* Bit 27 : Set as output pin 27 */ #define GPIO_DIRSET_PIN27_Pos (27UL) /*!< Position of PIN27 field. */ #define GPIO_DIRSET_PIN27_Msk (0x1UL << GPIO_DIRSET_PIN27_Pos) /*!< Bit mask of PIN27 field. */ #define GPIO_DIRSET_PIN27_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRSET_PIN27_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRSET_PIN27_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ +#define GPIO_DIRSET_PIN27_Set (1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */ /* Bit 26 : Set as output pin 26 */ #define GPIO_DIRSET_PIN26_Pos (26UL) /*!< Position of PIN26 field. */ #define GPIO_DIRSET_PIN26_Msk (0x1UL << GPIO_DIRSET_PIN26_Pos) /*!< Bit mask of PIN26 field. */ #define GPIO_DIRSET_PIN26_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRSET_PIN26_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRSET_PIN26_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ +#define GPIO_DIRSET_PIN26_Set (1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */ /* Bit 25 : Set as output pin 25 */ #define GPIO_DIRSET_PIN25_Pos (25UL) /*!< Position of PIN25 field. */ #define GPIO_DIRSET_PIN25_Msk (0x1UL << GPIO_DIRSET_PIN25_Pos) /*!< Bit mask of PIN25 field. */ #define GPIO_DIRSET_PIN25_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRSET_PIN25_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRSET_PIN25_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ +#define GPIO_DIRSET_PIN25_Set (1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */ /* Bit 24 : Set as output pin 24 */ #define GPIO_DIRSET_PIN24_Pos (24UL) /*!< Position of PIN24 field. */ #define GPIO_DIRSET_PIN24_Msk (0x1UL << GPIO_DIRSET_PIN24_Pos) /*!< Bit mask of PIN24 field. */ #define GPIO_DIRSET_PIN24_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRSET_PIN24_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRSET_PIN24_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ +#define GPIO_DIRSET_PIN24_Set (1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */ /* Bit 23 : Set as output pin 23 */ #define GPIO_DIRSET_PIN23_Pos (23UL) /*!< Position of PIN23 field. */ #define GPIO_DIRSET_PIN23_Msk (0x1UL << GPIO_DIRSET_PIN23_Pos) /*!< Bit mask of PIN23 field. */ #define GPIO_DIRSET_PIN23_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRSET_PIN23_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRSET_PIN23_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ +#define GPIO_DIRSET_PIN23_Set (1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */ /* Bit 22 : Set as output pin 22 */ #define GPIO_DIRSET_PIN22_Pos (22UL) /*!< Position of PIN22 field. */ #define GPIO_DIRSET_PIN22_Msk (0x1UL << GPIO_DIRSET_PIN22_Pos) /*!< Bit mask of PIN22 field. */ #define GPIO_DIRSET_PIN22_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRSET_PIN22_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRSET_PIN22_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ +#define GPIO_DIRSET_PIN22_Set (1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */ /* Bit 21 : Set as output pin 21 */ #define GPIO_DIRSET_PIN21_Pos (21UL) /*!< Position of PIN21 field. */ #define GPIO_DIRSET_PIN21_Msk (0x1UL << GPIO_DIRSET_PIN21_Pos) /*!< Bit mask of PIN21 field. */ #define GPIO_DIRSET_PIN21_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRSET_PIN21_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRSET_PIN21_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ +#define GPIO_DIRSET_PIN21_Set (1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */ /* Bit 20 : Set as output pin 20 */ #define GPIO_DIRSET_PIN20_Pos (20UL) /*!< Position of PIN20 field. */ #define GPIO_DIRSET_PIN20_Msk (0x1UL << GPIO_DIRSET_PIN20_Pos) /*!< Bit mask of PIN20 field. */ #define GPIO_DIRSET_PIN20_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRSET_PIN20_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRSET_PIN20_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ +#define GPIO_DIRSET_PIN20_Set (1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */ /* Bit 19 : Set as output pin 19 */ #define GPIO_DIRSET_PIN19_Pos (19UL) /*!< Position of PIN19 field. */ #define GPIO_DIRSET_PIN19_Msk (0x1UL << GPIO_DIRSET_PIN19_Pos) /*!< Bit mask of PIN19 field. */ #define GPIO_DIRSET_PIN19_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRSET_PIN19_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRSET_PIN19_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ +#define GPIO_DIRSET_PIN19_Set (1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */ /* Bit 18 : Set as output pin 18 */ #define GPIO_DIRSET_PIN18_Pos (18UL) /*!< Position of PIN18 field. */ #define GPIO_DIRSET_PIN18_Msk (0x1UL << GPIO_DIRSET_PIN18_Pos) /*!< Bit mask of PIN18 field. */ #define GPIO_DIRSET_PIN18_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRSET_PIN18_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRSET_PIN18_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ +#define GPIO_DIRSET_PIN18_Set (1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */ /* Bit 17 : Set as output pin 17 */ #define GPIO_DIRSET_PIN17_Pos (17UL) /*!< Position of PIN17 field. */ #define GPIO_DIRSET_PIN17_Msk (0x1UL << GPIO_DIRSET_PIN17_Pos) /*!< Bit mask of PIN17 field. */ #define GPIO_DIRSET_PIN17_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRSET_PIN17_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRSET_PIN17_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ +#define GPIO_DIRSET_PIN17_Set (1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */ /* Bit 16 : Set as output pin 16 */ #define GPIO_DIRSET_PIN16_Pos (16UL) /*!< Position of PIN16 field. */ #define GPIO_DIRSET_PIN16_Msk (0x1UL << GPIO_DIRSET_PIN16_Pos) /*!< Bit mask of PIN16 field. */ #define GPIO_DIRSET_PIN16_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRSET_PIN16_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRSET_PIN16_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ +#define GPIO_DIRSET_PIN16_Set (1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */ /* Bit 15 : Set as output pin 15 */ #define GPIO_DIRSET_PIN15_Pos (15UL) /*!< Position of PIN15 field. */ #define GPIO_DIRSET_PIN15_Msk (0x1UL << GPIO_DIRSET_PIN15_Pos) /*!< Bit mask of PIN15 field. */ #define GPIO_DIRSET_PIN15_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRSET_PIN15_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRSET_PIN15_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ +#define GPIO_DIRSET_PIN15_Set (1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */ /* Bit 14 : Set as output pin 14 */ #define GPIO_DIRSET_PIN14_Pos (14UL) /*!< Position of PIN14 field. */ #define GPIO_DIRSET_PIN14_Msk (0x1UL << GPIO_DIRSET_PIN14_Pos) /*!< Bit mask of PIN14 field. */ #define GPIO_DIRSET_PIN14_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRSET_PIN14_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRSET_PIN14_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ +#define GPIO_DIRSET_PIN14_Set (1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */ /* Bit 13 : Set as output pin 13 */ #define GPIO_DIRSET_PIN13_Pos (13UL) /*!< Position of PIN13 field. */ #define GPIO_DIRSET_PIN13_Msk (0x1UL << GPIO_DIRSET_PIN13_Pos) /*!< Bit mask of PIN13 field. */ #define GPIO_DIRSET_PIN13_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRSET_PIN13_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRSET_PIN13_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ +#define GPIO_DIRSET_PIN13_Set (1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */ /* Bit 12 : Set as output pin 12 */ #define GPIO_DIRSET_PIN12_Pos (12UL) /*!< Position of PIN12 field. */ #define GPIO_DIRSET_PIN12_Msk (0x1UL << GPIO_DIRSET_PIN12_Pos) /*!< Bit mask of PIN12 field. */ #define GPIO_DIRSET_PIN12_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRSET_PIN12_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRSET_PIN12_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ +#define GPIO_DIRSET_PIN12_Set (1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */ /* Bit 11 : Set as output pin 11 */ #define GPIO_DIRSET_PIN11_Pos (11UL) /*!< Position of PIN11 field. */ #define GPIO_DIRSET_PIN11_Msk (0x1UL << GPIO_DIRSET_PIN11_Pos) /*!< Bit mask of PIN11 field. */ #define GPIO_DIRSET_PIN11_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRSET_PIN11_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRSET_PIN11_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ +#define GPIO_DIRSET_PIN11_Set (1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */ /* Bit 10 : Set as output pin 10 */ #define GPIO_DIRSET_PIN10_Pos (10UL) /*!< Position of PIN10 field. */ #define GPIO_DIRSET_PIN10_Msk (0x1UL << GPIO_DIRSET_PIN10_Pos) /*!< Bit mask of PIN10 field. */ #define GPIO_DIRSET_PIN10_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRSET_PIN10_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRSET_PIN10_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ +#define GPIO_DIRSET_PIN10_Set (1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */ /* Bit 9 : Set as output pin 9 */ #define GPIO_DIRSET_PIN9_Pos (9UL) /*!< Position of PIN9 field. */ #define GPIO_DIRSET_PIN9_Msk (0x1UL << GPIO_DIRSET_PIN9_Pos) /*!< Bit mask of PIN9 field. */ #define GPIO_DIRSET_PIN9_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRSET_PIN9_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRSET_PIN9_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ +#define GPIO_DIRSET_PIN9_Set (1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */ /* Bit 8 : Set as output pin 8 */ #define GPIO_DIRSET_PIN8_Pos (8UL) /*!< Position of PIN8 field. */ #define GPIO_DIRSET_PIN8_Msk (0x1UL << GPIO_DIRSET_PIN8_Pos) /*!< Bit mask of PIN8 field. */ #define GPIO_DIRSET_PIN8_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRSET_PIN8_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRSET_PIN8_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ +#define GPIO_DIRSET_PIN8_Set (1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */ /* Bit 7 : Set as output pin 7 */ #define GPIO_DIRSET_PIN7_Pos (7UL) /*!< Position of PIN7 field. */ #define GPIO_DIRSET_PIN7_Msk (0x1UL << GPIO_DIRSET_PIN7_Pos) /*!< Bit mask of PIN7 field. */ #define GPIO_DIRSET_PIN7_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRSET_PIN7_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRSET_PIN7_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ +#define GPIO_DIRSET_PIN7_Set (1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */ /* Bit 6 : Set as output pin 6 */ #define GPIO_DIRSET_PIN6_Pos (6UL) /*!< Position of PIN6 field. */ #define GPIO_DIRSET_PIN6_Msk (0x1UL << GPIO_DIRSET_PIN6_Pos) /*!< Bit mask of PIN6 field. */ #define GPIO_DIRSET_PIN6_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRSET_PIN6_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRSET_PIN6_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ +#define GPIO_DIRSET_PIN6_Set (1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */ /* Bit 5 : Set as output pin 5 */ #define GPIO_DIRSET_PIN5_Pos (5UL) /*!< Position of PIN5 field. */ #define GPIO_DIRSET_PIN5_Msk (0x1UL << GPIO_DIRSET_PIN5_Pos) /*!< Bit mask of PIN5 field. */ #define GPIO_DIRSET_PIN5_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRSET_PIN5_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRSET_PIN5_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ +#define GPIO_DIRSET_PIN5_Set (1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */ /* Bit 4 : Set as output pin 4 */ #define GPIO_DIRSET_PIN4_Pos (4UL) /*!< Position of PIN4 field. */ #define GPIO_DIRSET_PIN4_Msk (0x1UL << GPIO_DIRSET_PIN4_Pos) /*!< Bit mask of PIN4 field. */ #define GPIO_DIRSET_PIN4_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRSET_PIN4_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRSET_PIN4_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ +#define GPIO_DIRSET_PIN4_Set (1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */ /* Bit 3 : Set as output pin 3 */ #define GPIO_DIRSET_PIN3_Pos (3UL) /*!< Position of PIN3 field. */ #define GPIO_DIRSET_PIN3_Msk (0x1UL << GPIO_DIRSET_PIN3_Pos) /*!< Bit mask of PIN3 field. */ #define GPIO_DIRSET_PIN3_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRSET_PIN3_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRSET_PIN3_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ +#define GPIO_DIRSET_PIN3_Set (1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */ /* Bit 2 : Set as output pin 2 */ #define GPIO_DIRSET_PIN2_Pos (2UL) /*!< Position of PIN2 field. */ #define GPIO_DIRSET_PIN2_Msk (0x1UL << GPIO_DIRSET_PIN2_Pos) /*!< Bit mask of PIN2 field. */ #define GPIO_DIRSET_PIN2_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRSET_PIN2_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRSET_PIN2_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ +#define GPIO_DIRSET_PIN2_Set (1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */ /* Bit 1 : Set as output pin 1 */ #define GPIO_DIRSET_PIN1_Pos (1UL) /*!< Position of PIN1 field. */ #define GPIO_DIRSET_PIN1_Msk (0x1UL << GPIO_DIRSET_PIN1_Pos) /*!< Bit mask of PIN1 field. */ #define GPIO_DIRSET_PIN1_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRSET_PIN1_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRSET_PIN1_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ +#define GPIO_DIRSET_PIN1_Set (1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */ /* Bit 0 : Set as output pin 0 */ #define GPIO_DIRSET_PIN0_Pos (0UL) /*!< Position of PIN0 field. */ #define GPIO_DIRSET_PIN0_Msk (0x1UL << GPIO_DIRSET_PIN0_Pos) /*!< Bit mask of PIN0 field. */ #define GPIO_DIRSET_PIN0_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRSET_PIN0_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRSET_PIN0_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ +#define GPIO_DIRSET_PIN0_Set (1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */ /* Register: GPIO_DIRCLR */ /* Description: DIR clear register */ @@ -6201,224 +6226,224 @@ POSSIBILITY OF SUCH DAMAGE. #define GPIO_DIRCLR_PIN31_Msk (0x1UL << GPIO_DIRCLR_PIN31_Pos) /*!< Bit mask of PIN31 field. */ #define GPIO_DIRCLR_PIN31_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRCLR_PIN31_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRCLR_PIN31_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ +#define GPIO_DIRCLR_PIN31_Clear (1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */ /* Bit 30 : Set as input pin 30 */ #define GPIO_DIRCLR_PIN30_Pos (30UL) /*!< Position of PIN30 field. */ #define GPIO_DIRCLR_PIN30_Msk (0x1UL << GPIO_DIRCLR_PIN30_Pos) /*!< Bit mask of PIN30 field. */ #define GPIO_DIRCLR_PIN30_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRCLR_PIN30_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRCLR_PIN30_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ +#define GPIO_DIRCLR_PIN30_Clear (1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */ /* Bit 29 : Set as input pin 29 */ #define GPIO_DIRCLR_PIN29_Pos (29UL) /*!< Position of PIN29 field. */ #define GPIO_DIRCLR_PIN29_Msk (0x1UL << GPIO_DIRCLR_PIN29_Pos) /*!< Bit mask of PIN29 field. */ #define GPIO_DIRCLR_PIN29_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRCLR_PIN29_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRCLR_PIN29_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ +#define GPIO_DIRCLR_PIN29_Clear (1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */ /* Bit 28 : Set as input pin 28 */ #define GPIO_DIRCLR_PIN28_Pos (28UL) /*!< Position of PIN28 field. */ #define GPIO_DIRCLR_PIN28_Msk (0x1UL << GPIO_DIRCLR_PIN28_Pos) /*!< Bit mask of PIN28 field. */ #define GPIO_DIRCLR_PIN28_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRCLR_PIN28_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRCLR_PIN28_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ +#define GPIO_DIRCLR_PIN28_Clear (1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */ /* Bit 27 : Set as input pin 27 */ #define GPIO_DIRCLR_PIN27_Pos (27UL) /*!< Position of PIN27 field. */ #define GPIO_DIRCLR_PIN27_Msk (0x1UL << GPIO_DIRCLR_PIN27_Pos) /*!< Bit mask of PIN27 field. */ #define GPIO_DIRCLR_PIN27_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRCLR_PIN27_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRCLR_PIN27_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ +#define GPIO_DIRCLR_PIN27_Clear (1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */ /* Bit 26 : Set as input pin 26 */ #define GPIO_DIRCLR_PIN26_Pos (26UL) /*!< Position of PIN26 field. */ #define GPIO_DIRCLR_PIN26_Msk (0x1UL << GPIO_DIRCLR_PIN26_Pos) /*!< Bit mask of PIN26 field. */ #define GPIO_DIRCLR_PIN26_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRCLR_PIN26_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRCLR_PIN26_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ +#define GPIO_DIRCLR_PIN26_Clear (1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */ /* Bit 25 : Set as input pin 25 */ #define GPIO_DIRCLR_PIN25_Pos (25UL) /*!< Position of PIN25 field. */ #define GPIO_DIRCLR_PIN25_Msk (0x1UL << GPIO_DIRCLR_PIN25_Pos) /*!< Bit mask of PIN25 field. */ #define GPIO_DIRCLR_PIN25_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRCLR_PIN25_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRCLR_PIN25_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ +#define GPIO_DIRCLR_PIN25_Clear (1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */ /* Bit 24 : Set as input pin 24 */ #define GPIO_DIRCLR_PIN24_Pos (24UL) /*!< Position of PIN24 field. */ #define GPIO_DIRCLR_PIN24_Msk (0x1UL << GPIO_DIRCLR_PIN24_Pos) /*!< Bit mask of PIN24 field. */ #define GPIO_DIRCLR_PIN24_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRCLR_PIN24_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRCLR_PIN24_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ +#define GPIO_DIRCLR_PIN24_Clear (1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */ /* Bit 23 : Set as input pin 23 */ #define GPIO_DIRCLR_PIN23_Pos (23UL) /*!< Position of PIN23 field. */ #define GPIO_DIRCLR_PIN23_Msk (0x1UL << GPIO_DIRCLR_PIN23_Pos) /*!< Bit mask of PIN23 field. */ #define GPIO_DIRCLR_PIN23_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRCLR_PIN23_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRCLR_PIN23_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ +#define GPIO_DIRCLR_PIN23_Clear (1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */ /* Bit 22 : Set as input pin 22 */ #define GPIO_DIRCLR_PIN22_Pos (22UL) /*!< Position of PIN22 field. */ #define GPIO_DIRCLR_PIN22_Msk (0x1UL << GPIO_DIRCLR_PIN22_Pos) /*!< Bit mask of PIN22 field. */ #define GPIO_DIRCLR_PIN22_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRCLR_PIN22_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRCLR_PIN22_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ +#define GPIO_DIRCLR_PIN22_Clear (1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */ /* Bit 21 : Set as input pin 21 */ #define GPIO_DIRCLR_PIN21_Pos (21UL) /*!< Position of PIN21 field. */ #define GPIO_DIRCLR_PIN21_Msk (0x1UL << GPIO_DIRCLR_PIN21_Pos) /*!< Bit mask of PIN21 field. */ #define GPIO_DIRCLR_PIN21_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRCLR_PIN21_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRCLR_PIN21_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ +#define GPIO_DIRCLR_PIN21_Clear (1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */ /* Bit 20 : Set as input pin 20 */ #define GPIO_DIRCLR_PIN20_Pos (20UL) /*!< Position of PIN20 field. */ #define GPIO_DIRCLR_PIN20_Msk (0x1UL << GPIO_DIRCLR_PIN20_Pos) /*!< Bit mask of PIN20 field. */ #define GPIO_DIRCLR_PIN20_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRCLR_PIN20_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRCLR_PIN20_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ +#define GPIO_DIRCLR_PIN20_Clear (1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */ /* Bit 19 : Set as input pin 19 */ #define GPIO_DIRCLR_PIN19_Pos (19UL) /*!< Position of PIN19 field. */ #define GPIO_DIRCLR_PIN19_Msk (0x1UL << GPIO_DIRCLR_PIN19_Pos) /*!< Bit mask of PIN19 field. */ #define GPIO_DIRCLR_PIN19_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRCLR_PIN19_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRCLR_PIN19_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ +#define GPIO_DIRCLR_PIN19_Clear (1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */ /* Bit 18 : Set as input pin 18 */ #define GPIO_DIRCLR_PIN18_Pos (18UL) /*!< Position of PIN18 field. */ #define GPIO_DIRCLR_PIN18_Msk (0x1UL << GPIO_DIRCLR_PIN18_Pos) /*!< Bit mask of PIN18 field. */ #define GPIO_DIRCLR_PIN18_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRCLR_PIN18_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRCLR_PIN18_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ +#define GPIO_DIRCLR_PIN18_Clear (1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */ /* Bit 17 : Set as input pin 17 */ #define GPIO_DIRCLR_PIN17_Pos (17UL) /*!< Position of PIN17 field. */ #define GPIO_DIRCLR_PIN17_Msk (0x1UL << GPIO_DIRCLR_PIN17_Pos) /*!< Bit mask of PIN17 field. */ #define GPIO_DIRCLR_PIN17_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRCLR_PIN17_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRCLR_PIN17_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ +#define GPIO_DIRCLR_PIN17_Clear (1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */ /* Bit 16 : Set as input pin 16 */ #define GPIO_DIRCLR_PIN16_Pos (16UL) /*!< Position of PIN16 field. */ #define GPIO_DIRCLR_PIN16_Msk (0x1UL << GPIO_DIRCLR_PIN16_Pos) /*!< Bit mask of PIN16 field. */ #define GPIO_DIRCLR_PIN16_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRCLR_PIN16_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRCLR_PIN16_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ +#define GPIO_DIRCLR_PIN16_Clear (1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */ /* Bit 15 : Set as input pin 15 */ #define GPIO_DIRCLR_PIN15_Pos (15UL) /*!< Position of PIN15 field. */ #define GPIO_DIRCLR_PIN15_Msk (0x1UL << GPIO_DIRCLR_PIN15_Pos) /*!< Bit mask of PIN15 field. */ #define GPIO_DIRCLR_PIN15_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRCLR_PIN15_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRCLR_PIN15_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ +#define GPIO_DIRCLR_PIN15_Clear (1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */ /* Bit 14 : Set as input pin 14 */ #define GPIO_DIRCLR_PIN14_Pos (14UL) /*!< Position of PIN14 field. */ #define GPIO_DIRCLR_PIN14_Msk (0x1UL << GPIO_DIRCLR_PIN14_Pos) /*!< Bit mask of PIN14 field. */ #define GPIO_DIRCLR_PIN14_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRCLR_PIN14_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRCLR_PIN14_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ +#define GPIO_DIRCLR_PIN14_Clear (1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */ /* Bit 13 : Set as input pin 13 */ #define GPIO_DIRCLR_PIN13_Pos (13UL) /*!< Position of PIN13 field. */ #define GPIO_DIRCLR_PIN13_Msk (0x1UL << GPIO_DIRCLR_PIN13_Pos) /*!< Bit mask of PIN13 field. */ #define GPIO_DIRCLR_PIN13_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRCLR_PIN13_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRCLR_PIN13_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ +#define GPIO_DIRCLR_PIN13_Clear (1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */ /* Bit 12 : Set as input pin 12 */ #define GPIO_DIRCLR_PIN12_Pos (12UL) /*!< Position of PIN12 field. */ #define GPIO_DIRCLR_PIN12_Msk (0x1UL << GPIO_DIRCLR_PIN12_Pos) /*!< Bit mask of PIN12 field. */ #define GPIO_DIRCLR_PIN12_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRCLR_PIN12_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRCLR_PIN12_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ +#define GPIO_DIRCLR_PIN12_Clear (1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */ /* Bit 11 : Set as input pin 11 */ #define GPIO_DIRCLR_PIN11_Pos (11UL) /*!< Position of PIN11 field. */ #define GPIO_DIRCLR_PIN11_Msk (0x1UL << GPIO_DIRCLR_PIN11_Pos) /*!< Bit mask of PIN11 field. */ #define GPIO_DIRCLR_PIN11_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRCLR_PIN11_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRCLR_PIN11_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ +#define GPIO_DIRCLR_PIN11_Clear (1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */ /* Bit 10 : Set as input pin 10 */ #define GPIO_DIRCLR_PIN10_Pos (10UL) /*!< Position of PIN10 field. */ #define GPIO_DIRCLR_PIN10_Msk (0x1UL << GPIO_DIRCLR_PIN10_Pos) /*!< Bit mask of PIN10 field. */ #define GPIO_DIRCLR_PIN10_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRCLR_PIN10_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRCLR_PIN10_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ +#define GPIO_DIRCLR_PIN10_Clear (1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */ /* Bit 9 : Set as input pin 9 */ #define GPIO_DIRCLR_PIN9_Pos (9UL) /*!< Position of PIN9 field. */ #define GPIO_DIRCLR_PIN9_Msk (0x1UL << GPIO_DIRCLR_PIN9_Pos) /*!< Bit mask of PIN9 field. */ #define GPIO_DIRCLR_PIN9_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRCLR_PIN9_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRCLR_PIN9_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ +#define GPIO_DIRCLR_PIN9_Clear (1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */ /* Bit 8 : Set as input pin 8 */ #define GPIO_DIRCLR_PIN8_Pos (8UL) /*!< Position of PIN8 field. */ #define GPIO_DIRCLR_PIN8_Msk (0x1UL << GPIO_DIRCLR_PIN8_Pos) /*!< Bit mask of PIN8 field. */ #define GPIO_DIRCLR_PIN8_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRCLR_PIN8_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRCLR_PIN8_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ +#define GPIO_DIRCLR_PIN8_Clear (1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */ /* Bit 7 : Set as input pin 7 */ #define GPIO_DIRCLR_PIN7_Pos (7UL) /*!< Position of PIN7 field. */ #define GPIO_DIRCLR_PIN7_Msk (0x1UL << GPIO_DIRCLR_PIN7_Pos) /*!< Bit mask of PIN7 field. */ #define GPIO_DIRCLR_PIN7_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRCLR_PIN7_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRCLR_PIN7_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ +#define GPIO_DIRCLR_PIN7_Clear (1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */ /* Bit 6 : Set as input pin 6 */ #define GPIO_DIRCLR_PIN6_Pos (6UL) /*!< Position of PIN6 field. */ #define GPIO_DIRCLR_PIN6_Msk (0x1UL << GPIO_DIRCLR_PIN6_Pos) /*!< Bit mask of PIN6 field. */ #define GPIO_DIRCLR_PIN6_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRCLR_PIN6_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRCLR_PIN6_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ +#define GPIO_DIRCLR_PIN6_Clear (1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */ /* Bit 5 : Set as input pin 5 */ #define GPIO_DIRCLR_PIN5_Pos (5UL) /*!< Position of PIN5 field. */ #define GPIO_DIRCLR_PIN5_Msk (0x1UL << GPIO_DIRCLR_PIN5_Pos) /*!< Bit mask of PIN5 field. */ #define GPIO_DIRCLR_PIN5_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRCLR_PIN5_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRCLR_PIN5_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ +#define GPIO_DIRCLR_PIN5_Clear (1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */ /* Bit 4 : Set as input pin 4 */ #define GPIO_DIRCLR_PIN4_Pos (4UL) /*!< Position of PIN4 field. */ #define GPIO_DIRCLR_PIN4_Msk (0x1UL << GPIO_DIRCLR_PIN4_Pos) /*!< Bit mask of PIN4 field. */ #define GPIO_DIRCLR_PIN4_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRCLR_PIN4_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRCLR_PIN4_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ +#define GPIO_DIRCLR_PIN4_Clear (1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */ /* Bit 3 : Set as input pin 3 */ #define GPIO_DIRCLR_PIN3_Pos (3UL) /*!< Position of PIN3 field. */ #define GPIO_DIRCLR_PIN3_Msk (0x1UL << GPIO_DIRCLR_PIN3_Pos) /*!< Bit mask of PIN3 field. */ #define GPIO_DIRCLR_PIN3_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRCLR_PIN3_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRCLR_PIN3_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ +#define GPIO_DIRCLR_PIN3_Clear (1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */ /* Bit 2 : Set as input pin 2 */ #define GPIO_DIRCLR_PIN2_Pos (2UL) /*!< Position of PIN2 field. */ #define GPIO_DIRCLR_PIN2_Msk (0x1UL << GPIO_DIRCLR_PIN2_Pos) /*!< Bit mask of PIN2 field. */ #define GPIO_DIRCLR_PIN2_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRCLR_PIN2_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRCLR_PIN2_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ +#define GPIO_DIRCLR_PIN2_Clear (1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */ /* Bit 1 : Set as input pin 1 */ #define GPIO_DIRCLR_PIN1_Pos (1UL) /*!< Position of PIN1 field. */ #define GPIO_DIRCLR_PIN1_Msk (0x1UL << GPIO_DIRCLR_PIN1_Pos) /*!< Bit mask of PIN1 field. */ #define GPIO_DIRCLR_PIN1_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRCLR_PIN1_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRCLR_PIN1_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ +#define GPIO_DIRCLR_PIN1_Clear (1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */ /* Bit 0 : Set as input pin 0 */ #define GPIO_DIRCLR_PIN0_Pos (0UL) /*!< Position of PIN0 field. */ #define GPIO_DIRCLR_PIN0_Msk (0x1UL << GPIO_DIRCLR_PIN0_Pos) /*!< Bit mask of PIN0 field. */ #define GPIO_DIRCLR_PIN0_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRCLR_PIN0_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRCLR_PIN0_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ +#define GPIO_DIRCLR_PIN0_Clear (1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */ /* Register: GPIO_LATCH */ /* Description: Latch register indicating what GPIO pins that have met the criteria set in the PIN_CNF[n].SENSE registers */ @@ -6616,13 +6641,13 @@ POSSIBILITY OF SUCH DAMAGE. #define GPIO_LATCH_PIN0_Latched (1UL) /*!< Criteria has been met */ /* Register: GPIO_DETECTMODE */ -/* Description: Select between default DETECT signal behaviour and LDETECT mode */ +/* Description: Select between default DETECT signal behavior and LDETECT mode */ -/* Bit 0 : Select between default DETECT signal behaviour and LDETECT mode */ +/* Bit 0 : Select between default DETECT signal behavior and LDETECT mode */ #define GPIO_DETECTMODE_DETECTMODE_Pos (0UL) /*!< Position of DETECTMODE field. */ #define GPIO_DETECTMODE_DETECTMODE_Msk (0x1UL << GPIO_DETECTMODE_DETECTMODE_Pos) /*!< Bit mask of DETECTMODE field. */ #define GPIO_DETECTMODE_DETECTMODE_Default (0UL) /*!< DETECT directly connected to PIN DETECT signals */ -#define GPIO_DETECTMODE_DETECTMODE_LDETECT (1UL) /*!< Use the latched LDETECT behaviour */ +#define GPIO_DETECTMODE_DETECTMODE_LDETECT (1UL) /*!< Use the latched LDETECT behavior */ /* Register: GPIO_PIN_CNF */ /* Description: Description collection: Configuration of GPIO pins */ @@ -7982,224 +8007,224 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: PPI_CHENSET */ /* Description: Channel enable set register */ -/* Bit 31 : Channel 31 enable set register. Writing '0' has no effect */ +/* Bit 31 : Channel 31 enable set register. Writing '0' has no effect. */ #define PPI_CHENSET_CH31_Pos (31UL) /*!< Position of CH31 field. */ #define PPI_CHENSET_CH31_Msk (0x1UL << PPI_CHENSET_CH31_Pos) /*!< Bit mask of CH31 field. */ #define PPI_CHENSET_CH31_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENSET_CH31_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENSET_CH31_Set (1UL) /*!< Write: Enable channel */ -/* Bit 30 : Channel 30 enable set register. Writing '0' has no effect */ +/* Bit 30 : Channel 30 enable set register. Writing '0' has no effect. */ #define PPI_CHENSET_CH30_Pos (30UL) /*!< Position of CH30 field. */ #define PPI_CHENSET_CH30_Msk (0x1UL << PPI_CHENSET_CH30_Pos) /*!< Bit mask of CH30 field. */ #define PPI_CHENSET_CH30_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENSET_CH30_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENSET_CH30_Set (1UL) /*!< Write: Enable channel */ -/* Bit 29 : Channel 29 enable set register. Writing '0' has no effect */ +/* Bit 29 : Channel 29 enable set register. Writing '0' has no effect. */ #define PPI_CHENSET_CH29_Pos (29UL) /*!< Position of CH29 field. */ #define PPI_CHENSET_CH29_Msk (0x1UL << PPI_CHENSET_CH29_Pos) /*!< Bit mask of CH29 field. */ #define PPI_CHENSET_CH29_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENSET_CH29_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENSET_CH29_Set (1UL) /*!< Write: Enable channel */ -/* Bit 28 : Channel 28 enable set register. Writing '0' has no effect */ +/* Bit 28 : Channel 28 enable set register. Writing '0' has no effect. */ #define PPI_CHENSET_CH28_Pos (28UL) /*!< Position of CH28 field. */ #define PPI_CHENSET_CH28_Msk (0x1UL << PPI_CHENSET_CH28_Pos) /*!< Bit mask of CH28 field. */ #define PPI_CHENSET_CH28_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENSET_CH28_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENSET_CH28_Set (1UL) /*!< Write: Enable channel */ -/* Bit 27 : Channel 27 enable set register. Writing '0' has no effect */ +/* Bit 27 : Channel 27 enable set register. Writing '0' has no effect. */ #define PPI_CHENSET_CH27_Pos (27UL) /*!< Position of CH27 field. */ #define PPI_CHENSET_CH27_Msk (0x1UL << PPI_CHENSET_CH27_Pos) /*!< Bit mask of CH27 field. */ #define PPI_CHENSET_CH27_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENSET_CH27_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENSET_CH27_Set (1UL) /*!< Write: Enable channel */ -/* Bit 26 : Channel 26 enable set register. Writing '0' has no effect */ +/* Bit 26 : Channel 26 enable set register. Writing '0' has no effect. */ #define PPI_CHENSET_CH26_Pos (26UL) /*!< Position of CH26 field. */ #define PPI_CHENSET_CH26_Msk (0x1UL << PPI_CHENSET_CH26_Pos) /*!< Bit mask of CH26 field. */ #define PPI_CHENSET_CH26_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENSET_CH26_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENSET_CH26_Set (1UL) /*!< Write: Enable channel */ -/* Bit 25 : Channel 25 enable set register. Writing '0' has no effect */ +/* Bit 25 : Channel 25 enable set register. Writing '0' has no effect. */ #define PPI_CHENSET_CH25_Pos (25UL) /*!< Position of CH25 field. */ #define PPI_CHENSET_CH25_Msk (0x1UL << PPI_CHENSET_CH25_Pos) /*!< Bit mask of CH25 field. */ #define PPI_CHENSET_CH25_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENSET_CH25_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENSET_CH25_Set (1UL) /*!< Write: Enable channel */ -/* Bit 24 : Channel 24 enable set register. Writing '0' has no effect */ +/* Bit 24 : Channel 24 enable set register. Writing '0' has no effect. */ #define PPI_CHENSET_CH24_Pos (24UL) /*!< Position of CH24 field. */ #define PPI_CHENSET_CH24_Msk (0x1UL << PPI_CHENSET_CH24_Pos) /*!< Bit mask of CH24 field. */ #define PPI_CHENSET_CH24_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENSET_CH24_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENSET_CH24_Set (1UL) /*!< Write: Enable channel */ -/* Bit 23 : Channel 23 enable set register. Writing '0' has no effect */ +/* Bit 23 : Channel 23 enable set register. Writing '0' has no effect. */ #define PPI_CHENSET_CH23_Pos (23UL) /*!< Position of CH23 field. */ #define PPI_CHENSET_CH23_Msk (0x1UL << PPI_CHENSET_CH23_Pos) /*!< Bit mask of CH23 field. */ #define PPI_CHENSET_CH23_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENSET_CH23_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENSET_CH23_Set (1UL) /*!< Write: Enable channel */ -/* Bit 22 : Channel 22 enable set register. Writing '0' has no effect */ +/* Bit 22 : Channel 22 enable set register. Writing '0' has no effect. */ #define PPI_CHENSET_CH22_Pos (22UL) /*!< Position of CH22 field. */ #define PPI_CHENSET_CH22_Msk (0x1UL << PPI_CHENSET_CH22_Pos) /*!< Bit mask of CH22 field. */ #define PPI_CHENSET_CH22_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENSET_CH22_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENSET_CH22_Set (1UL) /*!< Write: Enable channel */ -/* Bit 21 : Channel 21 enable set register. Writing '0' has no effect */ +/* Bit 21 : Channel 21 enable set register. Writing '0' has no effect. */ #define PPI_CHENSET_CH21_Pos (21UL) /*!< Position of CH21 field. */ #define PPI_CHENSET_CH21_Msk (0x1UL << PPI_CHENSET_CH21_Pos) /*!< Bit mask of CH21 field. */ #define PPI_CHENSET_CH21_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENSET_CH21_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENSET_CH21_Set (1UL) /*!< Write: Enable channel */ -/* Bit 20 : Channel 20 enable set register. Writing '0' has no effect */ +/* Bit 20 : Channel 20 enable set register. Writing '0' has no effect. */ #define PPI_CHENSET_CH20_Pos (20UL) /*!< Position of CH20 field. */ #define PPI_CHENSET_CH20_Msk (0x1UL << PPI_CHENSET_CH20_Pos) /*!< Bit mask of CH20 field. */ #define PPI_CHENSET_CH20_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENSET_CH20_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENSET_CH20_Set (1UL) /*!< Write: Enable channel */ -/* Bit 19 : Channel 19 enable set register. Writing '0' has no effect */ +/* Bit 19 : Channel 19 enable set register. Writing '0' has no effect. */ #define PPI_CHENSET_CH19_Pos (19UL) /*!< Position of CH19 field. */ #define PPI_CHENSET_CH19_Msk (0x1UL << PPI_CHENSET_CH19_Pos) /*!< Bit mask of CH19 field. */ #define PPI_CHENSET_CH19_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENSET_CH19_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENSET_CH19_Set (1UL) /*!< Write: Enable channel */ -/* Bit 18 : Channel 18 enable set register. Writing '0' has no effect */ +/* Bit 18 : Channel 18 enable set register. Writing '0' has no effect. */ #define PPI_CHENSET_CH18_Pos (18UL) /*!< Position of CH18 field. */ #define PPI_CHENSET_CH18_Msk (0x1UL << PPI_CHENSET_CH18_Pos) /*!< Bit mask of CH18 field. */ #define PPI_CHENSET_CH18_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENSET_CH18_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENSET_CH18_Set (1UL) /*!< Write: Enable channel */ -/* Bit 17 : Channel 17 enable set register. Writing '0' has no effect */ +/* Bit 17 : Channel 17 enable set register. Writing '0' has no effect. */ #define PPI_CHENSET_CH17_Pos (17UL) /*!< Position of CH17 field. */ #define PPI_CHENSET_CH17_Msk (0x1UL << PPI_CHENSET_CH17_Pos) /*!< Bit mask of CH17 field. */ #define PPI_CHENSET_CH17_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENSET_CH17_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENSET_CH17_Set (1UL) /*!< Write: Enable channel */ -/* Bit 16 : Channel 16 enable set register. Writing '0' has no effect */ +/* Bit 16 : Channel 16 enable set register. Writing '0' has no effect. */ #define PPI_CHENSET_CH16_Pos (16UL) /*!< Position of CH16 field. */ #define PPI_CHENSET_CH16_Msk (0x1UL << PPI_CHENSET_CH16_Pos) /*!< Bit mask of CH16 field. */ #define PPI_CHENSET_CH16_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENSET_CH16_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENSET_CH16_Set (1UL) /*!< Write: Enable channel */ -/* Bit 15 : Channel 15 enable set register. Writing '0' has no effect */ +/* Bit 15 : Channel 15 enable set register. Writing '0' has no effect. */ #define PPI_CHENSET_CH15_Pos (15UL) /*!< Position of CH15 field. */ #define PPI_CHENSET_CH15_Msk (0x1UL << PPI_CHENSET_CH15_Pos) /*!< Bit mask of CH15 field. */ #define PPI_CHENSET_CH15_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENSET_CH15_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENSET_CH15_Set (1UL) /*!< Write: Enable channel */ -/* Bit 14 : Channel 14 enable set register. Writing '0' has no effect */ +/* Bit 14 : Channel 14 enable set register. Writing '0' has no effect. */ #define PPI_CHENSET_CH14_Pos (14UL) /*!< Position of CH14 field. */ #define PPI_CHENSET_CH14_Msk (0x1UL << PPI_CHENSET_CH14_Pos) /*!< Bit mask of CH14 field. */ #define PPI_CHENSET_CH14_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENSET_CH14_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENSET_CH14_Set (1UL) /*!< Write: Enable channel */ -/* Bit 13 : Channel 13 enable set register. Writing '0' has no effect */ +/* Bit 13 : Channel 13 enable set register. Writing '0' has no effect. */ #define PPI_CHENSET_CH13_Pos (13UL) /*!< Position of CH13 field. */ #define PPI_CHENSET_CH13_Msk (0x1UL << PPI_CHENSET_CH13_Pos) /*!< Bit mask of CH13 field. */ #define PPI_CHENSET_CH13_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENSET_CH13_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENSET_CH13_Set (1UL) /*!< Write: Enable channel */ -/* Bit 12 : Channel 12 enable set register. Writing '0' has no effect */ +/* Bit 12 : Channel 12 enable set register. Writing '0' has no effect. */ #define PPI_CHENSET_CH12_Pos (12UL) /*!< Position of CH12 field. */ #define PPI_CHENSET_CH12_Msk (0x1UL << PPI_CHENSET_CH12_Pos) /*!< Bit mask of CH12 field. */ #define PPI_CHENSET_CH12_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENSET_CH12_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENSET_CH12_Set (1UL) /*!< Write: Enable channel */ -/* Bit 11 : Channel 11 enable set register. Writing '0' has no effect */ +/* Bit 11 : Channel 11 enable set register. Writing '0' has no effect. */ #define PPI_CHENSET_CH11_Pos (11UL) /*!< Position of CH11 field. */ #define PPI_CHENSET_CH11_Msk (0x1UL << PPI_CHENSET_CH11_Pos) /*!< Bit mask of CH11 field. */ #define PPI_CHENSET_CH11_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENSET_CH11_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENSET_CH11_Set (1UL) /*!< Write: Enable channel */ -/* Bit 10 : Channel 10 enable set register. Writing '0' has no effect */ +/* Bit 10 : Channel 10 enable set register. Writing '0' has no effect. */ #define PPI_CHENSET_CH10_Pos (10UL) /*!< Position of CH10 field. */ #define PPI_CHENSET_CH10_Msk (0x1UL << PPI_CHENSET_CH10_Pos) /*!< Bit mask of CH10 field. */ #define PPI_CHENSET_CH10_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENSET_CH10_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENSET_CH10_Set (1UL) /*!< Write: Enable channel */ -/* Bit 9 : Channel 9 enable set register. Writing '0' has no effect */ +/* Bit 9 : Channel 9 enable set register. Writing '0' has no effect. */ #define PPI_CHENSET_CH9_Pos (9UL) /*!< Position of CH9 field. */ #define PPI_CHENSET_CH9_Msk (0x1UL << PPI_CHENSET_CH9_Pos) /*!< Bit mask of CH9 field. */ #define PPI_CHENSET_CH9_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENSET_CH9_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENSET_CH9_Set (1UL) /*!< Write: Enable channel */ -/* Bit 8 : Channel 8 enable set register. Writing '0' has no effect */ +/* Bit 8 : Channel 8 enable set register. Writing '0' has no effect. */ #define PPI_CHENSET_CH8_Pos (8UL) /*!< Position of CH8 field. */ #define PPI_CHENSET_CH8_Msk (0x1UL << PPI_CHENSET_CH8_Pos) /*!< Bit mask of CH8 field. */ #define PPI_CHENSET_CH8_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENSET_CH8_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENSET_CH8_Set (1UL) /*!< Write: Enable channel */ -/* Bit 7 : Channel 7 enable set register. Writing '0' has no effect */ +/* Bit 7 : Channel 7 enable set register. Writing '0' has no effect. */ #define PPI_CHENSET_CH7_Pos (7UL) /*!< Position of CH7 field. */ #define PPI_CHENSET_CH7_Msk (0x1UL << PPI_CHENSET_CH7_Pos) /*!< Bit mask of CH7 field. */ #define PPI_CHENSET_CH7_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENSET_CH7_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENSET_CH7_Set (1UL) /*!< Write: Enable channel */ -/* Bit 6 : Channel 6 enable set register. Writing '0' has no effect */ +/* Bit 6 : Channel 6 enable set register. Writing '0' has no effect. */ #define PPI_CHENSET_CH6_Pos (6UL) /*!< Position of CH6 field. */ #define PPI_CHENSET_CH6_Msk (0x1UL << PPI_CHENSET_CH6_Pos) /*!< Bit mask of CH6 field. */ #define PPI_CHENSET_CH6_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENSET_CH6_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENSET_CH6_Set (1UL) /*!< Write: Enable channel */ -/* Bit 5 : Channel 5 enable set register. Writing '0' has no effect */ +/* Bit 5 : Channel 5 enable set register. Writing '0' has no effect. */ #define PPI_CHENSET_CH5_Pos (5UL) /*!< Position of CH5 field. */ #define PPI_CHENSET_CH5_Msk (0x1UL << PPI_CHENSET_CH5_Pos) /*!< Bit mask of CH5 field. */ #define PPI_CHENSET_CH5_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENSET_CH5_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENSET_CH5_Set (1UL) /*!< Write: Enable channel */ -/* Bit 4 : Channel 4 enable set register. Writing '0' has no effect */ +/* Bit 4 : Channel 4 enable set register. Writing '0' has no effect. */ #define PPI_CHENSET_CH4_Pos (4UL) /*!< Position of CH4 field. */ #define PPI_CHENSET_CH4_Msk (0x1UL << PPI_CHENSET_CH4_Pos) /*!< Bit mask of CH4 field. */ #define PPI_CHENSET_CH4_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENSET_CH4_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENSET_CH4_Set (1UL) /*!< Write: Enable channel */ -/* Bit 3 : Channel 3 enable set register. Writing '0' has no effect */ +/* Bit 3 : Channel 3 enable set register. Writing '0' has no effect. */ #define PPI_CHENSET_CH3_Pos (3UL) /*!< Position of CH3 field. */ #define PPI_CHENSET_CH3_Msk (0x1UL << PPI_CHENSET_CH3_Pos) /*!< Bit mask of CH3 field. */ #define PPI_CHENSET_CH3_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENSET_CH3_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENSET_CH3_Set (1UL) /*!< Write: Enable channel */ -/* Bit 2 : Channel 2 enable set register. Writing '0' has no effect */ +/* Bit 2 : Channel 2 enable set register. Writing '0' has no effect. */ #define PPI_CHENSET_CH2_Pos (2UL) /*!< Position of CH2 field. */ #define PPI_CHENSET_CH2_Msk (0x1UL << PPI_CHENSET_CH2_Pos) /*!< Bit mask of CH2 field. */ #define PPI_CHENSET_CH2_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENSET_CH2_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENSET_CH2_Set (1UL) /*!< Write: Enable channel */ -/* Bit 1 : Channel 1 enable set register. Writing '0' has no effect */ +/* Bit 1 : Channel 1 enable set register. Writing '0' has no effect. */ #define PPI_CHENSET_CH1_Pos (1UL) /*!< Position of CH1 field. */ #define PPI_CHENSET_CH1_Msk (0x1UL << PPI_CHENSET_CH1_Pos) /*!< Bit mask of CH1 field. */ #define PPI_CHENSET_CH1_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENSET_CH1_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENSET_CH1_Set (1UL) /*!< Write: Enable channel */ -/* Bit 0 : Channel 0 enable set register. Writing '0' has no effect */ +/* Bit 0 : Channel 0 enable set register. Writing '0' has no effect. */ #define PPI_CHENSET_CH0_Pos (0UL) /*!< Position of CH0 field. */ #define PPI_CHENSET_CH0_Msk (0x1UL << PPI_CHENSET_CH0_Pos) /*!< Bit mask of CH0 field. */ #define PPI_CHENSET_CH0_Disabled (0UL) /*!< Read: channel disabled */ @@ -8209,224 +8234,224 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: PPI_CHENCLR */ /* Description: Channel enable clear register */ -/* Bit 31 : Channel 31 enable clear register. Writing '0' has no effect */ +/* Bit 31 : Channel 31 enable clear register. Writing '0' has no effect. */ #define PPI_CHENCLR_CH31_Pos (31UL) /*!< Position of CH31 field. */ #define PPI_CHENCLR_CH31_Msk (0x1UL << PPI_CHENCLR_CH31_Pos) /*!< Bit mask of CH31 field. */ #define PPI_CHENCLR_CH31_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENCLR_CH31_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENCLR_CH31_Clear (1UL) /*!< Write: disable channel */ -/* Bit 30 : Channel 30 enable clear register. Writing '0' has no effect */ +/* Bit 30 : Channel 30 enable clear register. Writing '0' has no effect. */ #define PPI_CHENCLR_CH30_Pos (30UL) /*!< Position of CH30 field. */ #define PPI_CHENCLR_CH30_Msk (0x1UL << PPI_CHENCLR_CH30_Pos) /*!< Bit mask of CH30 field. */ #define PPI_CHENCLR_CH30_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENCLR_CH30_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENCLR_CH30_Clear (1UL) /*!< Write: disable channel */ -/* Bit 29 : Channel 29 enable clear register. Writing '0' has no effect */ +/* Bit 29 : Channel 29 enable clear register. Writing '0' has no effect. */ #define PPI_CHENCLR_CH29_Pos (29UL) /*!< Position of CH29 field. */ #define PPI_CHENCLR_CH29_Msk (0x1UL << PPI_CHENCLR_CH29_Pos) /*!< Bit mask of CH29 field. */ #define PPI_CHENCLR_CH29_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENCLR_CH29_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENCLR_CH29_Clear (1UL) /*!< Write: disable channel */ -/* Bit 28 : Channel 28 enable clear register. Writing '0' has no effect */ +/* Bit 28 : Channel 28 enable clear register. Writing '0' has no effect. */ #define PPI_CHENCLR_CH28_Pos (28UL) /*!< Position of CH28 field. */ #define PPI_CHENCLR_CH28_Msk (0x1UL << PPI_CHENCLR_CH28_Pos) /*!< Bit mask of CH28 field. */ #define PPI_CHENCLR_CH28_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENCLR_CH28_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENCLR_CH28_Clear (1UL) /*!< Write: disable channel */ -/* Bit 27 : Channel 27 enable clear register. Writing '0' has no effect */ +/* Bit 27 : Channel 27 enable clear register. Writing '0' has no effect. */ #define PPI_CHENCLR_CH27_Pos (27UL) /*!< Position of CH27 field. */ #define PPI_CHENCLR_CH27_Msk (0x1UL << PPI_CHENCLR_CH27_Pos) /*!< Bit mask of CH27 field. */ #define PPI_CHENCLR_CH27_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENCLR_CH27_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENCLR_CH27_Clear (1UL) /*!< Write: disable channel */ -/* Bit 26 : Channel 26 enable clear register. Writing '0' has no effect */ +/* Bit 26 : Channel 26 enable clear register. Writing '0' has no effect. */ #define PPI_CHENCLR_CH26_Pos (26UL) /*!< Position of CH26 field. */ #define PPI_CHENCLR_CH26_Msk (0x1UL << PPI_CHENCLR_CH26_Pos) /*!< Bit mask of CH26 field. */ #define PPI_CHENCLR_CH26_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENCLR_CH26_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENCLR_CH26_Clear (1UL) /*!< Write: disable channel */ -/* Bit 25 : Channel 25 enable clear register. Writing '0' has no effect */ +/* Bit 25 : Channel 25 enable clear register. Writing '0' has no effect. */ #define PPI_CHENCLR_CH25_Pos (25UL) /*!< Position of CH25 field. */ #define PPI_CHENCLR_CH25_Msk (0x1UL << PPI_CHENCLR_CH25_Pos) /*!< Bit mask of CH25 field. */ #define PPI_CHENCLR_CH25_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENCLR_CH25_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENCLR_CH25_Clear (1UL) /*!< Write: disable channel */ -/* Bit 24 : Channel 24 enable clear register. Writing '0' has no effect */ +/* Bit 24 : Channel 24 enable clear register. Writing '0' has no effect. */ #define PPI_CHENCLR_CH24_Pos (24UL) /*!< Position of CH24 field. */ #define PPI_CHENCLR_CH24_Msk (0x1UL << PPI_CHENCLR_CH24_Pos) /*!< Bit mask of CH24 field. */ #define PPI_CHENCLR_CH24_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENCLR_CH24_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENCLR_CH24_Clear (1UL) /*!< Write: disable channel */ -/* Bit 23 : Channel 23 enable clear register. Writing '0' has no effect */ +/* Bit 23 : Channel 23 enable clear register. Writing '0' has no effect. */ #define PPI_CHENCLR_CH23_Pos (23UL) /*!< Position of CH23 field. */ #define PPI_CHENCLR_CH23_Msk (0x1UL << PPI_CHENCLR_CH23_Pos) /*!< Bit mask of CH23 field. */ #define PPI_CHENCLR_CH23_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENCLR_CH23_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENCLR_CH23_Clear (1UL) /*!< Write: disable channel */ -/* Bit 22 : Channel 22 enable clear register. Writing '0' has no effect */ +/* Bit 22 : Channel 22 enable clear register. Writing '0' has no effect. */ #define PPI_CHENCLR_CH22_Pos (22UL) /*!< Position of CH22 field. */ #define PPI_CHENCLR_CH22_Msk (0x1UL << PPI_CHENCLR_CH22_Pos) /*!< Bit mask of CH22 field. */ #define PPI_CHENCLR_CH22_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENCLR_CH22_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENCLR_CH22_Clear (1UL) /*!< Write: disable channel */ -/* Bit 21 : Channel 21 enable clear register. Writing '0' has no effect */ +/* Bit 21 : Channel 21 enable clear register. Writing '0' has no effect. */ #define PPI_CHENCLR_CH21_Pos (21UL) /*!< Position of CH21 field. */ #define PPI_CHENCLR_CH21_Msk (0x1UL << PPI_CHENCLR_CH21_Pos) /*!< Bit mask of CH21 field. */ #define PPI_CHENCLR_CH21_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENCLR_CH21_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENCLR_CH21_Clear (1UL) /*!< Write: disable channel */ -/* Bit 20 : Channel 20 enable clear register. Writing '0' has no effect */ +/* Bit 20 : Channel 20 enable clear register. Writing '0' has no effect. */ #define PPI_CHENCLR_CH20_Pos (20UL) /*!< Position of CH20 field. */ #define PPI_CHENCLR_CH20_Msk (0x1UL << PPI_CHENCLR_CH20_Pos) /*!< Bit mask of CH20 field. */ #define PPI_CHENCLR_CH20_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENCLR_CH20_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENCLR_CH20_Clear (1UL) /*!< Write: disable channel */ -/* Bit 19 : Channel 19 enable clear register. Writing '0' has no effect */ +/* Bit 19 : Channel 19 enable clear register. Writing '0' has no effect. */ #define PPI_CHENCLR_CH19_Pos (19UL) /*!< Position of CH19 field. */ #define PPI_CHENCLR_CH19_Msk (0x1UL << PPI_CHENCLR_CH19_Pos) /*!< Bit mask of CH19 field. */ #define PPI_CHENCLR_CH19_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENCLR_CH19_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENCLR_CH19_Clear (1UL) /*!< Write: disable channel */ -/* Bit 18 : Channel 18 enable clear register. Writing '0' has no effect */ +/* Bit 18 : Channel 18 enable clear register. Writing '0' has no effect. */ #define PPI_CHENCLR_CH18_Pos (18UL) /*!< Position of CH18 field. */ #define PPI_CHENCLR_CH18_Msk (0x1UL << PPI_CHENCLR_CH18_Pos) /*!< Bit mask of CH18 field. */ #define PPI_CHENCLR_CH18_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENCLR_CH18_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENCLR_CH18_Clear (1UL) /*!< Write: disable channel */ -/* Bit 17 : Channel 17 enable clear register. Writing '0' has no effect */ +/* Bit 17 : Channel 17 enable clear register. Writing '0' has no effect. */ #define PPI_CHENCLR_CH17_Pos (17UL) /*!< Position of CH17 field. */ #define PPI_CHENCLR_CH17_Msk (0x1UL << PPI_CHENCLR_CH17_Pos) /*!< Bit mask of CH17 field. */ #define PPI_CHENCLR_CH17_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENCLR_CH17_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENCLR_CH17_Clear (1UL) /*!< Write: disable channel */ -/* Bit 16 : Channel 16 enable clear register. Writing '0' has no effect */ +/* Bit 16 : Channel 16 enable clear register. Writing '0' has no effect. */ #define PPI_CHENCLR_CH16_Pos (16UL) /*!< Position of CH16 field. */ #define PPI_CHENCLR_CH16_Msk (0x1UL << PPI_CHENCLR_CH16_Pos) /*!< Bit mask of CH16 field. */ #define PPI_CHENCLR_CH16_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENCLR_CH16_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENCLR_CH16_Clear (1UL) /*!< Write: disable channel */ -/* Bit 15 : Channel 15 enable clear register. Writing '0' has no effect */ +/* Bit 15 : Channel 15 enable clear register. Writing '0' has no effect. */ #define PPI_CHENCLR_CH15_Pos (15UL) /*!< Position of CH15 field. */ #define PPI_CHENCLR_CH15_Msk (0x1UL << PPI_CHENCLR_CH15_Pos) /*!< Bit mask of CH15 field. */ #define PPI_CHENCLR_CH15_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENCLR_CH15_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENCLR_CH15_Clear (1UL) /*!< Write: disable channel */ -/* Bit 14 : Channel 14 enable clear register. Writing '0' has no effect */ +/* Bit 14 : Channel 14 enable clear register. Writing '0' has no effect. */ #define PPI_CHENCLR_CH14_Pos (14UL) /*!< Position of CH14 field. */ #define PPI_CHENCLR_CH14_Msk (0x1UL << PPI_CHENCLR_CH14_Pos) /*!< Bit mask of CH14 field. */ #define PPI_CHENCLR_CH14_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENCLR_CH14_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENCLR_CH14_Clear (1UL) /*!< Write: disable channel */ -/* Bit 13 : Channel 13 enable clear register. Writing '0' has no effect */ +/* Bit 13 : Channel 13 enable clear register. Writing '0' has no effect. */ #define PPI_CHENCLR_CH13_Pos (13UL) /*!< Position of CH13 field. */ #define PPI_CHENCLR_CH13_Msk (0x1UL << PPI_CHENCLR_CH13_Pos) /*!< Bit mask of CH13 field. */ #define PPI_CHENCLR_CH13_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENCLR_CH13_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENCLR_CH13_Clear (1UL) /*!< Write: disable channel */ -/* Bit 12 : Channel 12 enable clear register. Writing '0' has no effect */ +/* Bit 12 : Channel 12 enable clear register. Writing '0' has no effect. */ #define PPI_CHENCLR_CH12_Pos (12UL) /*!< Position of CH12 field. */ #define PPI_CHENCLR_CH12_Msk (0x1UL << PPI_CHENCLR_CH12_Pos) /*!< Bit mask of CH12 field. */ #define PPI_CHENCLR_CH12_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENCLR_CH12_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENCLR_CH12_Clear (1UL) /*!< Write: disable channel */ -/* Bit 11 : Channel 11 enable clear register. Writing '0' has no effect */ +/* Bit 11 : Channel 11 enable clear register. Writing '0' has no effect. */ #define PPI_CHENCLR_CH11_Pos (11UL) /*!< Position of CH11 field. */ #define PPI_CHENCLR_CH11_Msk (0x1UL << PPI_CHENCLR_CH11_Pos) /*!< Bit mask of CH11 field. */ #define PPI_CHENCLR_CH11_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENCLR_CH11_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENCLR_CH11_Clear (1UL) /*!< Write: disable channel */ -/* Bit 10 : Channel 10 enable clear register. Writing '0' has no effect */ +/* Bit 10 : Channel 10 enable clear register. Writing '0' has no effect. */ #define PPI_CHENCLR_CH10_Pos (10UL) /*!< Position of CH10 field. */ #define PPI_CHENCLR_CH10_Msk (0x1UL << PPI_CHENCLR_CH10_Pos) /*!< Bit mask of CH10 field. */ #define PPI_CHENCLR_CH10_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENCLR_CH10_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENCLR_CH10_Clear (1UL) /*!< Write: disable channel */ -/* Bit 9 : Channel 9 enable clear register. Writing '0' has no effect */ +/* Bit 9 : Channel 9 enable clear register. Writing '0' has no effect. */ #define PPI_CHENCLR_CH9_Pos (9UL) /*!< Position of CH9 field. */ #define PPI_CHENCLR_CH9_Msk (0x1UL << PPI_CHENCLR_CH9_Pos) /*!< Bit mask of CH9 field. */ #define PPI_CHENCLR_CH9_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENCLR_CH9_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENCLR_CH9_Clear (1UL) /*!< Write: disable channel */ -/* Bit 8 : Channel 8 enable clear register. Writing '0' has no effect */ +/* Bit 8 : Channel 8 enable clear register. Writing '0' has no effect. */ #define PPI_CHENCLR_CH8_Pos (8UL) /*!< Position of CH8 field. */ #define PPI_CHENCLR_CH8_Msk (0x1UL << PPI_CHENCLR_CH8_Pos) /*!< Bit mask of CH8 field. */ #define PPI_CHENCLR_CH8_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENCLR_CH8_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENCLR_CH8_Clear (1UL) /*!< Write: disable channel */ -/* Bit 7 : Channel 7 enable clear register. Writing '0' has no effect */ +/* Bit 7 : Channel 7 enable clear register. Writing '0' has no effect. */ #define PPI_CHENCLR_CH7_Pos (7UL) /*!< Position of CH7 field. */ #define PPI_CHENCLR_CH7_Msk (0x1UL << PPI_CHENCLR_CH7_Pos) /*!< Bit mask of CH7 field. */ #define PPI_CHENCLR_CH7_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENCLR_CH7_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENCLR_CH7_Clear (1UL) /*!< Write: disable channel */ -/* Bit 6 : Channel 6 enable clear register. Writing '0' has no effect */ +/* Bit 6 : Channel 6 enable clear register. Writing '0' has no effect. */ #define PPI_CHENCLR_CH6_Pos (6UL) /*!< Position of CH6 field. */ #define PPI_CHENCLR_CH6_Msk (0x1UL << PPI_CHENCLR_CH6_Pos) /*!< Bit mask of CH6 field. */ #define PPI_CHENCLR_CH6_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENCLR_CH6_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENCLR_CH6_Clear (1UL) /*!< Write: disable channel */ -/* Bit 5 : Channel 5 enable clear register. Writing '0' has no effect */ +/* Bit 5 : Channel 5 enable clear register. Writing '0' has no effect. */ #define PPI_CHENCLR_CH5_Pos (5UL) /*!< Position of CH5 field. */ #define PPI_CHENCLR_CH5_Msk (0x1UL << PPI_CHENCLR_CH5_Pos) /*!< Bit mask of CH5 field. */ #define PPI_CHENCLR_CH5_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENCLR_CH5_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENCLR_CH5_Clear (1UL) /*!< Write: disable channel */ -/* Bit 4 : Channel 4 enable clear register. Writing '0' has no effect */ +/* Bit 4 : Channel 4 enable clear register. Writing '0' has no effect. */ #define PPI_CHENCLR_CH4_Pos (4UL) /*!< Position of CH4 field. */ #define PPI_CHENCLR_CH4_Msk (0x1UL << PPI_CHENCLR_CH4_Pos) /*!< Bit mask of CH4 field. */ #define PPI_CHENCLR_CH4_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENCLR_CH4_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENCLR_CH4_Clear (1UL) /*!< Write: disable channel */ -/* Bit 3 : Channel 3 enable clear register. Writing '0' has no effect */ +/* Bit 3 : Channel 3 enable clear register. Writing '0' has no effect. */ #define PPI_CHENCLR_CH3_Pos (3UL) /*!< Position of CH3 field. */ #define PPI_CHENCLR_CH3_Msk (0x1UL << PPI_CHENCLR_CH3_Pos) /*!< Bit mask of CH3 field. */ #define PPI_CHENCLR_CH3_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENCLR_CH3_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENCLR_CH3_Clear (1UL) /*!< Write: disable channel */ -/* Bit 2 : Channel 2 enable clear register. Writing '0' has no effect */ +/* Bit 2 : Channel 2 enable clear register. Writing '0' has no effect. */ #define PPI_CHENCLR_CH2_Pos (2UL) /*!< Position of CH2 field. */ #define PPI_CHENCLR_CH2_Msk (0x1UL << PPI_CHENCLR_CH2_Pos) /*!< Bit mask of CH2 field. */ #define PPI_CHENCLR_CH2_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENCLR_CH2_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENCLR_CH2_Clear (1UL) /*!< Write: disable channel */ -/* Bit 1 : Channel 1 enable clear register. Writing '0' has no effect */ +/* Bit 1 : Channel 1 enable clear register. Writing '0' has no effect. */ #define PPI_CHENCLR_CH1_Pos (1UL) /*!< Position of CH1 field. */ #define PPI_CHENCLR_CH1_Msk (0x1UL << PPI_CHENCLR_CH1_Pos) /*!< Bit mask of CH1 field. */ #define PPI_CHENCLR_CH1_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENCLR_CH1_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENCLR_CH1_Clear (1UL) /*!< Write: disable channel */ -/* Bit 0 : Channel 0 enable clear register. Writing '0' has no effect */ +/* Bit 0 : Channel 0 enable clear register. Writing '0' has no effect. */ #define PPI_CHENCLR_CH0_Pos (0UL) /*!< Position of CH0 field. */ #define PPI_CHENCLR_CH0_Msk (0x1UL << PPI_CHENCLR_CH0_Pos) /*!< Bit mask of CH0 field. */ #define PPI_CHENCLR_CH0_Disabled (0UL) /*!< Read: channel disabled */ @@ -8434,14 +8459,14 @@ POSSIBILITY OF SUCH DAMAGE. #define PPI_CHENCLR_CH0_Clear (1UL) /*!< Write: disable channel */ /* Register: PPI_CH_EEP */ -/* Description: Description cluster: Channel n event end-point */ +/* Description: Description cluster: Channel n event endpoint */ /* Bits 31..0 : Pointer to event register. Accepts only addresses to registers from the Event group. */ #define PPI_CH_EEP_EEP_Pos (0UL) /*!< Position of EEP field. */ #define PPI_CH_EEP_EEP_Msk (0xFFFFFFFFUL << PPI_CH_EEP_EEP_Pos) /*!< Bit mask of EEP field. */ /* Register: PPI_CH_TEP */ -/* Description: Description cluster: Channel n task end-point */ +/* Description: Description cluster: Channel n task endpoint */ /* Bits 31..0 : Pointer to task register. Accepts only addresses to registers from the Task group. */ #define PPI_CH_TEP_TEP_Pos (0UL) /*!< Position of TEP field. */ @@ -8643,7 +8668,7 @@ POSSIBILITY OF SUCH DAMAGE. #define PPI_CHG_CH0_Included (1UL) /*!< Include */ /* Register: PPI_FORK_TEP */ -/* Description: Description cluster: Channel n task end-point */ +/* Description: Description cluster: Channel n task endpoint */ /* Bits 31..0 : Pointer to task register */ #define PPI_FORK_TEP_TEP_Pos (0UL) /*!< Position of TEP field. */ @@ -9272,23 +9297,23 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: QDEC_REPORTPER */ /* Description: Number of samples to be taken before REPORTRDY and DBLRDY events can be generated */ -/* Bits 3..0 : Specifies the number of samples to be accumulated in the ACC register before the REPORTRDY and DBLRDY events can be generated */ +/* Bits 3..0 : Specifies the number of samples to be accumulated in the ACC register before the REPORTRDY and DBLRDY events can be generated. */ #define QDEC_REPORTPER_REPORTPER_Pos (0UL) /*!< Position of REPORTPER field. */ #define QDEC_REPORTPER_REPORTPER_Msk (0xFUL << QDEC_REPORTPER_REPORTPER_Pos) /*!< Bit mask of REPORTPER field. */ -#define QDEC_REPORTPER_REPORTPER_10Smpl (0UL) /*!< 10 samples / report */ -#define QDEC_REPORTPER_REPORTPER_40Smpl (1UL) /*!< 40 samples / report */ -#define QDEC_REPORTPER_REPORTPER_80Smpl (2UL) /*!< 80 samples / report */ -#define QDEC_REPORTPER_REPORTPER_120Smpl (3UL) /*!< 120 samples / report */ -#define QDEC_REPORTPER_REPORTPER_160Smpl (4UL) /*!< 160 samples / report */ -#define QDEC_REPORTPER_REPORTPER_200Smpl (5UL) /*!< 200 samples / report */ -#define QDEC_REPORTPER_REPORTPER_240Smpl (6UL) /*!< 240 samples / report */ -#define QDEC_REPORTPER_REPORTPER_280Smpl (7UL) /*!< 280 samples / report */ -#define QDEC_REPORTPER_REPORTPER_1Smpl (8UL) /*!< 1 sample / report */ +#define QDEC_REPORTPER_REPORTPER_10Smpl (0UL) /*!< 10 samples/report */ +#define QDEC_REPORTPER_REPORTPER_40Smpl (1UL) /*!< 40 samples/report */ +#define QDEC_REPORTPER_REPORTPER_80Smpl (2UL) /*!< 80 samples/report */ +#define QDEC_REPORTPER_REPORTPER_120Smpl (3UL) /*!< 120 samples/report */ +#define QDEC_REPORTPER_REPORTPER_160Smpl (4UL) /*!< 160 samples/report */ +#define QDEC_REPORTPER_REPORTPER_200Smpl (5UL) /*!< 200 samples/report */ +#define QDEC_REPORTPER_REPORTPER_240Smpl (6UL) /*!< 240 samples/report */ +#define QDEC_REPORTPER_REPORTPER_280Smpl (7UL) /*!< 280 samples/report */ +#define QDEC_REPORTPER_REPORTPER_1Smpl (8UL) /*!< 1 sample/report */ /* Register: QDEC_ACC */ /* Description: Register accumulating the valid transitions */ -/* Bits 31..0 : Register accumulating all valid samples (not double transition) read from the SAMPLE register */ +/* Bits 31..0 : Register accumulating all valid samples (not double transition) read from the SAMPLE register. */ #define QDEC_ACC_ACC_Pos (0UL) /*!< Position of ACC field. */ #define QDEC_ACC_ACC_Msk (0xFFFFFFFFUL << QDEC_ACC_ACC_Pos) /*!< Bit mask of ACC field. */ @@ -9597,9 +9622,9 @@ POSSIBILITY OF SUCH DAMAGE. #define RADIO_EVENTS_FRAMESTART_EVENTS_FRAMESTART_Generated (1UL) /*!< Event generated */ /* Register: RADIO_EVENTS_EDEND */ -/* Description: Sampling of energy detection complete. A new ED sample is ready for readout from the RADIO.EDSAMPLE register */ +/* Description: Sampling of energy detection complete. A new ED sample is ready for readout from the RADIO.EDSAMPLE register. */ -/* Bit 0 : Sampling of energy detection complete. A new ED sample is ready for readout from the RADIO.EDSAMPLE register */ +/* Bit 0 : Sampling of energy detection complete. A new ED sample is ready for readout from the RADIO.EDSAMPLE register. */ #define RADIO_EVENTS_EDEND_EVENTS_EDEND_Pos (0UL) /*!< Position of EVENTS_EDEND field. */ #define RADIO_EVENTS_EDEND_EVENTS_EDEND_Msk (0x1UL << RADIO_EVENTS_EDEND_EVENTS_EDEND_Pos) /*!< Bit mask of EVENTS_EDEND field. */ #define RADIO_EVENTS_EDEND_EVENTS_EDEND_NotGenerated (0UL) /*!< Event not generated */ @@ -10252,7 +10277,7 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: RADIO_FREQUENCY */ /* Description: Frequency */ -/* Bit 8 : Channel map selection. */ +/* Bit 8 : Channel map selection */ #define RADIO_FREQUENCY_MAP_Pos (8UL) /*!< Position of MAP field. */ #define RADIO_FREQUENCY_MAP_Msk (0x1UL << RADIO_FREQUENCY_MAP_Pos) /*!< Bit mask of MAP field. */ #define RADIO_FREQUENCY_MAP_Default (0UL) /*!< Channel map between 2400 MHZ .. 2500 MHz */ @@ -10329,15 +10354,15 @@ POSSIBILITY OF SUCH DAMAGE. #define RADIO_PCNF0_S1INCL_Automatic (0UL) /*!< Include S1 field in RAM only if S1LEN > 0 */ #define RADIO_PCNF0_S1INCL_Include (1UL) /*!< Always include S1 field in RAM independent of S1LEN */ -/* Bits 19..16 : Length on air of S1 field in number of bits. */ +/* Bits 19..16 : Length on air of S1 field in number of bits */ #define RADIO_PCNF0_S1LEN_Pos (16UL) /*!< Position of S1LEN field. */ #define RADIO_PCNF0_S1LEN_Msk (0xFUL << RADIO_PCNF0_S1LEN_Pos) /*!< Bit mask of S1LEN field. */ -/* Bit 8 : Length on air of S0 field in number of bytes. */ +/* Bit 8 : Length on air of S0 field in number of bytes */ #define RADIO_PCNF0_S0LEN_Pos (8UL) /*!< Position of S0LEN field. */ #define RADIO_PCNF0_S0LEN_Msk (0x1UL << RADIO_PCNF0_S0LEN_Pos) /*!< Bit mask of S0LEN field. */ -/* Bits 3..0 : Length on air of LENGTH field in number of bits. */ +/* Bits 3..0 : Length on air of LENGTH field in number of bits */ #define RADIO_PCNF0_LFLEN_Pos (0UL) /*!< Position of LFLEN field. */ #define RADIO_PCNF0_LFLEN_Msk (0xFUL << RADIO_PCNF0_LFLEN_Pos) /*!< Bit mask of LFLEN field. */ @@ -10488,7 +10513,7 @@ POSSIBILITY OF SUCH DAMAGE. #define RADIO_CRCCNF_SKIPADDR_Skip (1UL) /*!< CRC calculation does not include address field. The CRC calculation will start at the first byte after the address. */ #define RADIO_CRCCNF_SKIPADDR_Ieee802154 (2UL) /*!< CRC calculation as per 802.15.4 standard. Starting at first byte after length field. */ -/* Bits 1..0 : CRC length in number of bytes. */ +/* Bits 1..0 : CRC length in number of bytes For MODE Ble_LR125Kbit and Ble_LR500Kbit, only LEN set to 3 is supported */ #define RADIO_CRCCNF_LEN_Pos (0UL) /*!< Position of LEN field. */ #define RADIO_CRCCNF_LEN_Msk (0x3UL << RADIO_CRCCNF_LEN_Pos) /*!< Bit mask of LEN field. */ #define RADIO_CRCCNF_LEN_Disabled (0UL) /*!< CRC length is zero and CRC calculation is disabled */ @@ -10513,14 +10538,14 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: RADIO_TIFS */ /* Description: Interframe spacing in us */ -/* Bits 9..0 : Interframe spacing in us */ +/* Bits 9..0 : Interframe spacing in us. */ #define RADIO_TIFS_TIFS_Pos (0UL) /*!< Position of TIFS field. */ #define RADIO_TIFS_TIFS_Msk (0x3FFUL << RADIO_TIFS_TIFS_Pos) /*!< Bit mask of TIFS field. */ /* Register: RADIO_RSSISAMPLE */ /* Description: RSSI sample */ -/* Bits 6..0 : RSSI sample */ +/* Bits 6..0 : RSSI sample. */ #define RADIO_RSSISAMPLE_RSSISAMPLE_Pos (0UL) /*!< Position of RSSISAMPLE field. */ #define RADIO_RSSISAMPLE_RSSISAMPLE_Msk (0x7FUL << RADIO_RSSISAMPLE_RSSISAMPLE_Pos) /*!< Bit mask of RSSISAMPLE field. */ @@ -10679,7 +10704,7 @@ POSSIBILITY OF SUCH DAMAGE. #define RADIO_MODECNF0_RU_Pos (0UL) /*!< Position of RU field. */ #define RADIO_MODECNF0_RU_Msk (0x1UL << RADIO_MODECNF0_RU_Pos) /*!< Bit mask of RU field. */ #define RADIO_MODECNF0_RU_Default (0UL) /*!< Default ramp-up time (tRXEN and tTXEN), compatible with firmware written for nRF51 */ -#define RADIO_MODECNF0_RU_Fast (1UL) /*!< Fast ramp-up (tRXEN,FAST and tTXEN,FAST), see electrical specification for more information */ +#define RADIO_MODECNF0_RU_Fast (1UL) /*!< Fast ramp-up (tRXEN,FAST and tTXEN,FAST), see electrical specifications for more information */ /* Register: RADIO_SFD */ /* Description: IEEE 802.15.4 start of frame delimiter */ @@ -10747,32 +10772,32 @@ POSSIBILITY OF SUCH DAMAGE. #define RADIO_CTEINLINECONF_S0CONF_Pos (16UL) /*!< Position of S0CONF field. */ #define RADIO_CTEINLINECONF_S0CONF_Msk (0xFFUL << RADIO_CTEINLINECONF_S0CONF_Pos) /*!< Bit mask of S0CONF field. */ -/* Bits 15..13 : Spacing between samples for the samples in the SWITCHING period when CTEINLINEMODE is set */ +/* Bits 15..13 : Spacing between samples for the samples in the SWITCHING period when CTEINLINEMODE is set. */ #define RADIO_CTEINLINECONF_CTEINLINERXMODE2US_Pos (13UL) /*!< Position of CTEINLINERXMODE2US field. */ #define RADIO_CTEINLINECONF_CTEINLINERXMODE2US_Msk (0x7UL << RADIO_CTEINLINECONF_CTEINLINERXMODE2US_Pos) /*!< Bit mask of CTEINLINERXMODE2US field. */ -#define RADIO_CTEINLINECONF_CTEINLINERXMODE2US_4us (1UL) /*!< 4us */ -#define RADIO_CTEINLINECONF_CTEINLINERXMODE2US_2us (2UL) /*!< 2us */ -#define RADIO_CTEINLINECONF_CTEINLINERXMODE2US_1us (3UL) /*!< 1us */ -#define RADIO_CTEINLINECONF_CTEINLINERXMODE2US_500ns (4UL) /*!< 0.5us */ -#define RADIO_CTEINLINECONF_CTEINLINERXMODE2US_250ns (5UL) /*!< 0.25us */ -#define RADIO_CTEINLINECONF_CTEINLINERXMODE2US_125ns (6UL) /*!< 0.125us */ - -/* Bits 12..10 : Spacing between samples for the samples in the SWITCHING period when CTEINLINEMODE is set */ +#define RADIO_CTEINLINECONF_CTEINLINERXMODE2US_4us (1UL) /*!< 4 us */ +#define RADIO_CTEINLINECONF_CTEINLINERXMODE2US_2us (2UL) /*!< 2 us */ +#define RADIO_CTEINLINECONF_CTEINLINERXMODE2US_1us (3UL) /*!< 1 us */ +#define RADIO_CTEINLINECONF_CTEINLINERXMODE2US_500ns (4UL) /*!< 0.5 us */ +#define RADIO_CTEINLINECONF_CTEINLINERXMODE2US_250ns (5UL) /*!< 0.25 us */ +#define RADIO_CTEINLINECONF_CTEINLINERXMODE2US_125ns (6UL) /*!< 0.125 us */ + +/* Bits 12..10 : Spacing between samples for the samples in the SWITCHING period when CTEINLINEMODE is set. */ #define RADIO_CTEINLINECONF_CTEINLINERXMODE1US_Pos (10UL) /*!< Position of CTEINLINERXMODE1US field. */ #define RADIO_CTEINLINECONF_CTEINLINERXMODE1US_Msk (0x7UL << RADIO_CTEINLINECONF_CTEINLINERXMODE1US_Pos) /*!< Bit mask of CTEINLINERXMODE1US field. */ -#define RADIO_CTEINLINECONF_CTEINLINERXMODE1US_4us (1UL) /*!< 4us */ -#define RADIO_CTEINLINECONF_CTEINLINERXMODE1US_2us (2UL) /*!< 2us */ -#define RADIO_CTEINLINECONF_CTEINLINERXMODE1US_1us (3UL) /*!< 1us */ -#define RADIO_CTEINLINECONF_CTEINLINERXMODE1US_500ns (4UL) /*!< 0.5us */ -#define RADIO_CTEINLINECONF_CTEINLINERXMODE1US_250ns (5UL) /*!< 0.25us */ -#define RADIO_CTEINLINECONF_CTEINLINERXMODE1US_125ns (6UL) /*!< 0.125us */ +#define RADIO_CTEINLINECONF_CTEINLINERXMODE1US_4us (1UL) /*!< 4 us */ +#define RADIO_CTEINLINECONF_CTEINLINERXMODE1US_2us (2UL) /*!< 2 us */ +#define RADIO_CTEINLINECONF_CTEINLINERXMODE1US_1us (3UL) /*!< 1 us */ +#define RADIO_CTEINLINECONF_CTEINLINERXMODE1US_500ns (4UL) /*!< 0.5 us */ +#define RADIO_CTEINLINECONF_CTEINLINERXMODE1US_250ns (5UL) /*!< 0.25 us */ +#define RADIO_CTEINLINECONF_CTEINLINERXMODE1US_125ns (6UL) /*!< 0.125 us */ /* Bits 7..6 : Max range of CTETime */ #define RADIO_CTEINLINECONF_CTETIMEVALIDRANGE_Pos (6UL) /*!< Position of CTETIMEVALIDRANGE field. */ #define RADIO_CTEINLINECONF_CTETIMEVALIDRANGE_Msk (0x3UL << RADIO_CTEINLINECONF_CTETIMEVALIDRANGE_Pos) /*!< Bit mask of CTETIMEVALIDRANGE field. */ -#define RADIO_CTEINLINECONF_CTETIMEVALIDRANGE_20 (0UL) /*!< 20 in 8us unit (default) Set to 20 if parsed CTETime is larger han 20 */ -#define RADIO_CTEINLINECONF_CTETIMEVALIDRANGE_31 (1UL) /*!< 31 in 8us unit */ -#define RADIO_CTEINLINECONF_CTETIMEVALIDRANGE_63 (2UL) /*!< 63 in 8us unit */ +#define RADIO_CTEINLINECONF_CTETIMEVALIDRANGE_20 (0UL) /*!< 20 in 8 us unit (default) Set to 20 if parsed CTETime is larger than 20 */ +#define RADIO_CTEINLINECONF_CTETIMEVALIDRANGE_31 (1UL) /*!< 31 in 8 us unit */ +#define RADIO_CTEINLINECONF_CTETIMEVALIDRANGE_63 (2UL) /*!< 63 in 8 us unit */ /* Bit 4 : Sampling/switching if CRC is not OK */ #define RADIO_CTEINLINECONF_CTEERRORHANDLING_Pos (4UL) /*!< Position of CTEERRORHANDLING field. */ @@ -10807,12 +10832,12 @@ POSSIBILITY OF SUCH DAMAGE. /* Bits 18..16 : Interval between samples in the SWITCHING period when CTEINLINECTRLEN is 0 */ #define RADIO_DFECTRL1_TSAMPLESPACING_Pos (16UL) /*!< Position of TSAMPLESPACING field. */ #define RADIO_DFECTRL1_TSAMPLESPACING_Msk (0x7UL << RADIO_DFECTRL1_TSAMPLESPACING_Pos) /*!< Bit mask of TSAMPLESPACING field. */ -#define RADIO_DFECTRL1_TSAMPLESPACING_4us (1UL) /*!< 4us */ -#define RADIO_DFECTRL1_TSAMPLESPACING_2us (2UL) /*!< 2us */ -#define RADIO_DFECTRL1_TSAMPLESPACING_1us (3UL) /*!< 1us */ -#define RADIO_DFECTRL1_TSAMPLESPACING_500ns (4UL) /*!< 0.5us */ -#define RADIO_DFECTRL1_TSAMPLESPACING_250ns (5UL) /*!< 0.25us */ -#define RADIO_DFECTRL1_TSAMPLESPACING_125ns (6UL) /*!< 0.125us */ +#define RADIO_DFECTRL1_TSAMPLESPACING_4us (1UL) /*!< 4 us */ +#define RADIO_DFECTRL1_TSAMPLESPACING_2us (2UL) /*!< 2 us */ +#define RADIO_DFECTRL1_TSAMPLESPACING_1us (3UL) /*!< 1 us */ +#define RADIO_DFECTRL1_TSAMPLESPACING_500ns (4UL) /*!< 0.5 us */ +#define RADIO_DFECTRL1_TSAMPLESPACING_250ns (5UL) /*!< 0.25 us */ +#define RADIO_DFECTRL1_TSAMPLESPACING_125ns (6UL) /*!< 0.125 us */ /* Bit 15 : Whether to sample I/Q or magnitude/phase */ #define RADIO_DFECTRL1_SAMPLETYPE_Pos (15UL) /*!< Position of SAMPLETYPE field. */ @@ -10823,19 +10848,19 @@ POSSIBILITY OF SUCH DAMAGE. /* Bits 14..12 : Interval between samples in the REFERENCE period */ #define RADIO_DFECTRL1_TSAMPLESPACINGREF_Pos (12UL) /*!< Position of TSAMPLESPACINGREF field. */ #define RADIO_DFECTRL1_TSAMPLESPACINGREF_Msk (0x7UL << RADIO_DFECTRL1_TSAMPLESPACINGREF_Pos) /*!< Bit mask of TSAMPLESPACINGREF field. */ -#define RADIO_DFECTRL1_TSAMPLESPACINGREF_4us (1UL) /*!< 4us */ -#define RADIO_DFECTRL1_TSAMPLESPACINGREF_2us (2UL) /*!< 2us */ -#define RADIO_DFECTRL1_TSAMPLESPACINGREF_1us (3UL) /*!< 1us */ -#define RADIO_DFECTRL1_TSAMPLESPACINGREF_500ns (4UL) /*!< 0.5us */ -#define RADIO_DFECTRL1_TSAMPLESPACINGREF_250ns (5UL) /*!< 0.25us */ -#define RADIO_DFECTRL1_TSAMPLESPACINGREF_125ns (6UL) /*!< 0.125us */ +#define RADIO_DFECTRL1_TSAMPLESPACINGREF_4us (1UL) /*!< 4 us */ +#define RADIO_DFECTRL1_TSAMPLESPACINGREF_2us (2UL) /*!< 2 us */ +#define RADIO_DFECTRL1_TSAMPLESPACINGREF_1us (3UL) /*!< 1 us */ +#define RADIO_DFECTRL1_TSAMPLESPACINGREF_500ns (4UL) /*!< 0.5 us */ +#define RADIO_DFECTRL1_TSAMPLESPACINGREF_250ns (5UL) /*!< 0.25 us */ +#define RADIO_DFECTRL1_TSAMPLESPACINGREF_125ns (6UL) /*!< 0.125 us */ /* Bits 10..8 : Interval between every time the antenna is changed in the SWITCHING state */ #define RADIO_DFECTRL1_TSWITCHSPACING_Pos (8UL) /*!< Position of TSWITCHSPACING field. */ #define RADIO_DFECTRL1_TSWITCHSPACING_Msk (0x7UL << RADIO_DFECTRL1_TSWITCHSPACING_Pos) /*!< Bit mask of TSWITCHSPACING field. */ -#define RADIO_DFECTRL1_TSWITCHSPACING_4us (1UL) /*!< 4us */ -#define RADIO_DFECTRL1_TSWITCHSPACING_2us (2UL) /*!< 2us */ -#define RADIO_DFECTRL1_TSWITCHSPACING_1us (3UL) /*!< 1us */ +#define RADIO_DFECTRL1_TSWITCHSPACING_4us (1UL) /*!< 4 us */ +#define RADIO_DFECTRL1_TSWITCHSPACING_2us (2UL) /*!< 2 us */ +#define RADIO_DFECTRL1_TSWITCHSPACING_1us (3UL) /*!< 1 us */ /* Bit 7 : Add CTE extension and do antenna switching/sampling in this extension */ #define RADIO_DFECTRL1_DFEINEXTENSION_Pos (7UL) /*!< Position of DFEINEXTENSION field. */ @@ -10861,7 +10886,7 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: RADIO_SWITCHPATTERN */ /* Description: GPIO patterns to be used for each antenna */ -/* Bits 7..0 : Fill array of GPIO patterns for antenna control */ +/* Bits 7..0 : Fill array of GPIO patterns for antenna control. */ #define RADIO_SWITCHPATTERN_SWITCHPATTERN_Pos (0UL) /*!< Position of SWITCHPATTERN field. */ #define RADIO_SWITCHPATTERN_SWITCHPATTERN_Msk (0xFFUL << RADIO_SWITCHPATTERN_SWITCHPATTERN_Pos) /*!< Bit mask of SWITCHPATTERN field. */ @@ -11284,7 +11309,7 @@ POSSIBILITY OF SUCH DAMAGE. #define RTC_COUNTER_COUNTER_Msk (0xFFFFFFUL << RTC_COUNTER_COUNTER_Pos) /*!< Bit mask of COUNTER field. */ /* Register: RTC_PRESCALER */ -/* Description: 12 bit prescaler for COUNTER frequency (32768/(PRESCALER+1)).Must be written when RTC is stopped */ +/* Description: 12 bit prescaler for COUNTER frequency (32768/(PRESCALER+1)). Must be written when RTC is stopped. */ /* Bits 11..0 : Prescaler value */ #define RTC_PRESCALER_PRESCALER_Pos (0UL) /*!< Position of PRESCALER field. */ @@ -12142,7 +12167,7 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: SPI_TXD */ /* Description: TXD register */ -/* Bits 7..0 : TX data to send. Double buffered */ +/* Bits 7..0 : TX data to send. Double buffered. */ #define SPI_TXD_TXD_Pos (0UL) /*!< Position of TXD field. */ #define SPI_TXD_TXD_Msk (0xFFUL << SPI_TXD_TXD_Pos) /*!< Bit mask of TXD field. */ @@ -12348,7 +12373,7 @@ POSSIBILITY OF SUCH DAMAGE. #define SPIM_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */ /* Register: SPIM_STALLSTAT */ -/* Description: Stall status for EasyDMA RAM accesses. The fields in this register is set to STALL by hardware whenever a stall occurres and can be cleared (set to NOSTALL) by the CPU. */ +/* Description: Stall status for EasyDMA RAM accesses. The fields in this register are set to STALL by hardware whenever a stall occurs and can be cleared (set to NOSTALL) by the CPU. */ /* Bit 1 : Stall status for EasyDMA RAM writes */ #define SPIM_STALLSTAT_RX_Pos (1UL) /*!< Position of RX field. */ @@ -12951,121 +12976,121 @@ POSSIBILITY OF SUCH DAMAGE. #define TEMP_TEMP_TEMP_Msk (0xFFFFFFFFUL << TEMP_TEMP_TEMP_Pos) /*!< Bit mask of TEMP field. */ /* Register: TEMP_A0 */ -/* Description: Slope of 1st piece wise linear function */ +/* Description: Slope of first piecewise linear function */ -/* Bits 11..0 : Slope of 1st piece wise linear function */ +/* Bits 11..0 : Slope of first piecewise linear function */ #define TEMP_A0_A0_Pos (0UL) /*!< Position of A0 field. */ #define TEMP_A0_A0_Msk (0xFFFUL << TEMP_A0_A0_Pos) /*!< Bit mask of A0 field. */ /* Register: TEMP_A1 */ -/* Description: Slope of 2nd piece wise linear function */ +/* Description: Slope of second piecewise linear function */ -/* Bits 11..0 : Slope of 2nd piece wise linear function */ +/* Bits 11..0 : Slope of second piecewise linear function */ #define TEMP_A1_A1_Pos (0UL) /*!< Position of A1 field. */ #define TEMP_A1_A1_Msk (0xFFFUL << TEMP_A1_A1_Pos) /*!< Bit mask of A1 field. */ /* Register: TEMP_A2 */ -/* Description: Slope of 3rd piece wise linear function */ +/* Description: Slope of third piecewise linear function */ -/* Bits 11..0 : Slope of 3rd piece wise linear function */ +/* Bits 11..0 : Slope of third piecewise linear function */ #define TEMP_A2_A2_Pos (0UL) /*!< Position of A2 field. */ #define TEMP_A2_A2_Msk (0xFFFUL << TEMP_A2_A2_Pos) /*!< Bit mask of A2 field. */ /* Register: TEMP_A3 */ -/* Description: Slope of 4th piece wise linear function */ +/* Description: Slope of fourth piecewise linear function */ -/* Bits 11..0 : Slope of 4th piece wise linear function */ +/* Bits 11..0 : Slope of fourth piecewise linear function */ #define TEMP_A3_A3_Pos (0UL) /*!< Position of A3 field. */ #define TEMP_A3_A3_Msk (0xFFFUL << TEMP_A3_A3_Pos) /*!< Bit mask of A3 field. */ /* Register: TEMP_A4 */ -/* Description: Slope of 5th piece wise linear function */ +/* Description: Slope of fifth piecewise linear function */ -/* Bits 11..0 : Slope of 5th piece wise linear function */ +/* Bits 11..0 : Slope of fifth piecewise linear function */ #define TEMP_A4_A4_Pos (0UL) /*!< Position of A4 field. */ #define TEMP_A4_A4_Msk (0xFFFUL << TEMP_A4_A4_Pos) /*!< Bit mask of A4 field. */ /* Register: TEMP_A5 */ -/* Description: Slope of 6th piece wise linear function */ +/* Description: Slope of sixth piecewise linear function */ -/* Bits 11..0 : Slope of 6th piece wise linear function */ +/* Bits 11..0 : Slope of sixth piecewise linear function */ #define TEMP_A5_A5_Pos (0UL) /*!< Position of A5 field. */ #define TEMP_A5_A5_Msk (0xFFFUL << TEMP_A5_A5_Pos) /*!< Bit mask of A5 field. */ /* Register: TEMP_B0 */ -/* Description: y-intercept of 1st piece wise linear function */ +/* Description: y-intercept of first piecewise linear function */ -/* Bits 13..0 : y-intercept of 1st piece wise linear function */ +/* Bits 13..0 : y-intercept of first piecewise linear function */ #define TEMP_B0_B0_Pos (0UL) /*!< Position of B0 field. */ #define TEMP_B0_B0_Msk (0x3FFFUL << TEMP_B0_B0_Pos) /*!< Bit mask of B0 field. */ /* Register: TEMP_B1 */ -/* Description: y-intercept of 2nd piece wise linear function */ +/* Description: y-intercept of second piecewise linear function */ -/* Bits 13..0 : y-intercept of 2nd piece wise linear function */ +/* Bits 13..0 : y-intercept of second piecewise linear function */ #define TEMP_B1_B1_Pos (0UL) /*!< Position of B1 field. */ #define TEMP_B1_B1_Msk (0x3FFFUL << TEMP_B1_B1_Pos) /*!< Bit mask of B1 field. */ /* Register: TEMP_B2 */ -/* Description: y-intercept of 3rd piece wise linear function */ +/* Description: y-intercept of third piecewise linear function */ -/* Bits 13..0 : y-intercept of 3rd piece wise linear function */ +/* Bits 13..0 : y-intercept of third piecewise linear function */ #define TEMP_B2_B2_Pos (0UL) /*!< Position of B2 field. */ #define TEMP_B2_B2_Msk (0x3FFFUL << TEMP_B2_B2_Pos) /*!< Bit mask of B2 field. */ /* Register: TEMP_B3 */ -/* Description: y-intercept of 4th piece wise linear function */ +/* Description: y-intercept of fourth piecewise linear function */ -/* Bits 13..0 : y-intercept of 4th piece wise linear function */ +/* Bits 13..0 : y-intercept of fourth piecewise linear function */ #define TEMP_B3_B3_Pos (0UL) /*!< Position of B3 field. */ #define TEMP_B3_B3_Msk (0x3FFFUL << TEMP_B3_B3_Pos) /*!< Bit mask of B3 field. */ /* Register: TEMP_B4 */ -/* Description: y-intercept of 5th piece wise linear function */ +/* Description: y-intercept of fifth piecewise linear function */ -/* Bits 13..0 : y-intercept of 5th piece wise linear function */ +/* Bits 13..0 : y-intercept of fifth piecewise linear function */ #define TEMP_B4_B4_Pos (0UL) /*!< Position of B4 field. */ #define TEMP_B4_B4_Msk (0x3FFFUL << TEMP_B4_B4_Pos) /*!< Bit mask of B4 field. */ /* Register: TEMP_B5 */ -/* Description: y-intercept of 6th piece wise linear function */ +/* Description: y-intercept of sixth piecewise linear function */ -/* Bits 13..0 : y-intercept of 6th piece wise linear function */ +/* Bits 13..0 : y-intercept of sixth piecewise linear function */ #define TEMP_B5_B5_Pos (0UL) /*!< Position of B5 field. */ #define TEMP_B5_B5_Msk (0x3FFFUL << TEMP_B5_B5_Pos) /*!< Bit mask of B5 field. */ /* Register: TEMP_T0 */ -/* Description: End point of 1st piece wise linear function */ +/* Description: End point of first piecewise linear function */ -/* Bits 7..0 : End point of 1st piece wise linear function */ +/* Bits 7..0 : End point of first piecewise linear function */ #define TEMP_T0_T0_Pos (0UL) /*!< Position of T0 field. */ #define TEMP_T0_T0_Msk (0xFFUL << TEMP_T0_T0_Pos) /*!< Bit mask of T0 field. */ /* Register: TEMP_T1 */ -/* Description: End point of 2nd piece wise linear function */ +/* Description: End point of second piecewise linear function */ -/* Bits 7..0 : End point of 2nd piece wise linear function */ +/* Bits 7..0 : End point of second piecewise linear function */ #define TEMP_T1_T1_Pos (0UL) /*!< Position of T1 field. */ #define TEMP_T1_T1_Msk (0xFFUL << TEMP_T1_T1_Pos) /*!< Bit mask of T1 field. */ /* Register: TEMP_T2 */ -/* Description: End point of 3rd piece wise linear function */ +/* Description: End point of third piecewise linear function */ -/* Bits 7..0 : End point of 3rd piece wise linear function */ +/* Bits 7..0 : End point of third piecewise linear function */ #define TEMP_T2_T2_Pos (0UL) /*!< Position of T2 field. */ #define TEMP_T2_T2_Msk (0xFFUL << TEMP_T2_T2_Pos) /*!< Bit mask of T2 field. */ /* Register: TEMP_T3 */ -/* Description: End point of 4th piece wise linear function */ +/* Description: End point of fourth piecewise linear function */ -/* Bits 7..0 : End point of 4th piece wise linear function */ +/* Bits 7..0 : End point of fourth piecewise linear function */ #define TEMP_T3_T3_Pos (0UL) /*!< Position of T3 field. */ #define TEMP_T3_T3_Msk (0xFFUL << TEMP_T3_T3_Pos) /*!< Bit mask of T3 field. */ /* Register: TEMP_T4 */ -/* Description: End point of 5th piece wise linear function */ +/* Description: End point of fifth piecewise linear function */ -/* Bits 7..0 : End point of 5th piece wise linear function */ +/* Bits 7..0 : End point of fifth piecewise linear function */ #define TEMP_T4_T4_Pos (0UL) /*!< Position of T4 field. */ #define TEMP_T4_T4_Msk (0xFFUL << TEMP_T4_T4_Pos) /*!< Bit mask of T4 field. */ @@ -13691,9 +13716,9 @@ POSSIBILITY OF SUCH DAMAGE. #define TWIM_EVENTS_ERROR_EVENTS_ERROR_Generated (1UL) /*!< Event generated */ /* Register: TWIM_EVENTS_SUSPENDED */ -/* Description: Last byte has been sent out after the SUSPEND task has been issued, TWI traffic is now suspended. */ +/* Description: SUSPEND task has been issued, TWI traffic is now suspended. */ -/* Bit 0 : Last byte has been sent out after the SUSPEND task has been issued, TWI traffic is now suspended. */ +/* Bit 0 : SUSPEND task has been issued, TWI traffic is now suspended. */ #define TWIM_EVENTS_SUSPENDED_EVENTS_SUSPENDED_Pos (0UL) /*!< Position of EVENTS_SUSPENDED field. */ #define TWIM_EVENTS_SUSPENDED_EVENTS_SUSPENDED_Msk (0x1UL << TWIM_EVENTS_SUSPENDED_EVENTS_SUSPENDED_Pos) /*!< Bit mask of EVENTS_SUSPENDED field. */ #define TWIM_EVENTS_SUSPENDED_EVENTS_SUSPENDED_NotGenerated (0UL) /*!< Event not generated */ @@ -14330,7 +14355,7 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: TWIS_MATCH */ /* Description: Status register indicating which address had a match */ -/* Bit 0 : Which of the addresses in {ADDRESS} matched the incoming address */ +/* Bit 0 : Indication of which address in {ADDRESS} that matched the incoming address */ #define TWIS_MATCH_MATCH_Pos (0UL) /*!< Position of MATCH field. */ #define TWIS_MATCH_MATCH_Msk (0x1UL << TWIS_MATCH_MATCH_Pos) /*!< Bit mask of MATCH field. */ @@ -15227,7 +15252,7 @@ POSSIBILITY OF SUCH DAMAGE. #define UARTE_INTENCLR_CTS_Clear (1UL) /*!< Disable */ /* Register: UARTE_ERRORSRC */ -/* Description: Error source Note : this register is read / write one to clear. */ +/* Description: Error source This register is read/write one to clear. */ /* Bit 3 : Break condition */ #define UARTE_ERRORSRC_BREAK_Pos (3UL) /*!< Position of BREAK field. */ @@ -15353,7 +15378,7 @@ POSSIBILITY OF SUCH DAMAGE. #define UARTE_BAUDRATE_BAUDRATE_Baud250000 (0x04000000UL) /*!< 250000 baud */ #define UARTE_BAUDRATE_BAUDRATE_Baud460800 (0x07400000UL) /*!< 460800 baud (actual rate: 457143) */ #define UARTE_BAUDRATE_BAUDRATE_Baud921600 (0x0F000000UL) /*!< 921600 baud (actual rate: 941176) */ -#define UARTE_BAUDRATE_BAUDRATE_Baud1M (0x10000000UL) /*!< 1Mega baud */ +#define UARTE_BAUDRATE_BAUDRATE_Baud1M (0x10000000UL) /*!< 1 megabaud */ /* Register: UARTE_RXD_PTR */ /* Description: Data pointer */ @@ -15473,7 +15498,8 @@ POSSIBILITY OF SUCH DAMAGE. #define UICR_APPROTECT_PALL_Pos (0UL) /*!< Position of PALL field. */ #define UICR_APPROTECT_PALL_Msk (0xFFUL << UICR_APPROTECT_PALL_Pos) /*!< Bit mask of PALL field. */ #define UICR_APPROTECT_PALL_Enabled (0x00UL) /*!< Enable */ -#define UICR_APPROTECT_PALL_Disabled (0xFFUL) /*!< Disable */ +#define UICR_APPROTECT_PALL_HwDisabled (0x5AUL) /*!< Hardware disable of access port protection for devices where access port protection is controlled by hardware and software */ +#define UICR_APPROTECT_PALL_Disabled (0xFFUL) /*!< Hardware disable of access port protection for devices where access port protection is controlled by hardware */ /* Register: UICR_NFCPINS */ /* Description: Setting of pins dedicated to NFC functionality: NFC antenna or GPIO */ @@ -15481,8 +15507,8 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 0 : Setting of pins dedicated to NFC functionality */ #define UICR_NFCPINS_PROTECT_Pos (0UL) /*!< Position of PROTECT field. */ #define UICR_NFCPINS_PROTECT_Msk (0x1UL << UICR_NFCPINS_PROTECT_Pos) /*!< Bit mask of PROTECT field. */ -#define UICR_NFCPINS_PROTECT_Disabled (0UL) /*!< Operation as GPIO pins. Same protection as normal GPIO pins */ -#define UICR_NFCPINS_PROTECT_NFC (1UL) /*!< Operation as NFC antenna pins. Configures the protection for NFC operation */ +#define UICR_NFCPINS_PROTECT_Disabled (0UL) /*!< Operation as GPIO pins. Same protection as normal GPIO pins. */ +#define UICR_NFCPINS_PROTECT_NFC (1UL) /*!< Operation as NFC antenna pins. Configures the protection for NFC operation. */ /* Register: UICR_DEBUGCTRL */ /* Description: Processor debug control */ @@ -15500,7 +15526,7 @@ POSSIBILITY OF SUCH DAMAGE. #define UICR_DEBUGCTRL_CPUNIDEN_Enabled (0xFFUL) /*!< Enable CPU ITM and ETM functionality (default behavior) */ /* Register: UICR_REGOUT0 */ -/* Description: Output voltage from REG0 regulator stage. The maximum output voltage from this stage is given as VDDH - VREG0DROP. */ +/* Description: Output voltage from REG0 regulator stage. The maximum output voltage from this stage is given as VDDH - V_VDDH-VDD. */ /* Bits 2..0 : Output voltage from REG0 regulator stage. */ #define UICR_REGOUT0_VOUT_Pos (0UL) /*!< Position of VOUT field. */ @@ -16777,7 +16803,7 @@ POSSIBILITY OF SUCH DAMAGE. /* Bits 15..0 : Controls the split of ISO buffers */ #define USBD_ISOSPLIT_SPLIT_Pos (0UL) /*!< Position of SPLIT field. */ #define USBD_ISOSPLIT_SPLIT_Msk (0xFFFFUL << USBD_ISOSPLIT_SPLIT_Pos) /*!< Bit mask of SPLIT field. */ -#define USBD_ISOSPLIT_SPLIT_OneDir (0x0000UL) /*!< Full buffer dedicated to either iso IN or OUT */ +#define USBD_ISOSPLIT_SPLIT_OneDir (0x0000UL) /*!< Full buffer dedicated to either ISO IN or OUT */ #define USBD_ISOSPLIT_SPLIT_HalfIN (0x0080UL) /*!< Lower half for IN, upper half for OUT */ /* Register: USBD_FRAMECNTR */ diff --git a/mdk/nrf52833_peripherals.h b/mdk/nrf52833_peripherals.h index 70e62741f8..c0629c3a0e 100644 --- a/mdk/nrf52833_peripherals.h +++ b/mdk/nrf52833_peripherals.h @@ -1,6 +1,8 @@ /* -Copyright (c) 2010 - 2020, Nordic Semiconductor ASA All rights reserved. +Copyright (c) 2010 - 2021, Nordic Semiconductor ASA All rights reserved. + +SPDX-License-Identifier: BSD-3-Clause Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: diff --git a/mdk/nrf52833_to_nrf52820.h b/mdk/nrf52833_to_nrf52820.h index 0f270431df..a7835d1ecf 100644 --- a/mdk/nrf52833_to_nrf52820.h +++ b/mdk/nrf52833_to_nrf52820.h @@ -1,6 +1,8 @@ /* -Copyright (c) 2010 - 2020, Nordic Semiconductor ASA All rights reserved. +Copyright (c) 2010 - 2021, Nordic Semiconductor ASA All rights reserved. + +SPDX-License-Identifier: BSD-3-Clause Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: diff --git a/mdk/nrf52840.h b/mdk/nrf52840.h index a9b54ee080..141e436929 100644 --- a/mdk/nrf52840.h +++ b/mdk/nrf52840.h @@ -1,5 +1,7 @@ /* - * Copyright (c) 2010 - 2020, Nordic Semiconductor ASA All rights reserved. + * Copyright (c) 2010 - 2021, Nordic Semiconductor ASA All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: @@ -30,10 +32,10 @@ * @file nrf52840.h * @brief CMSIS HeaderFile * @version 1 - * @date 04. November 2020 - * @note Generated by SVDConv V3.3.35 on Wednesday, 04.11.2020 13:48:08 + * @date 29. April 2021 + * @note Generated by SVDConv V3.3.35 on Thursday, 29.04.2021 12:43:48 * from File 'nrf52840.svd', - * last modified on Wednesday, 04.11.2020 12:48:01 + * last modified on Thursday, 29.04.2021 10:43:41 */ @@ -598,8 +600,8 @@ typedef struct { * @brief ACL_ACL [ACL] (Unspecified) */ typedef struct { - __IOM uint32_t ADDR; /*!< (@ 0x00000000) Description cluster: Configure the word-aligned - start address of region n to protect */ + __IOM uint32_t ADDR; /*!< (@ 0x00000000) Description cluster: Start address of region + to protect. The start address must be word-aligned. */ __IOM uint32_t SIZE; /*!< (@ 0x00000004) Description cluster: Size of region to protect counting from address ACL[n].ADDR. Write '0' as no effect. */ @@ -623,8 +625,8 @@ typedef struct { * @brief PPI_CH [CH] (PPI Channel) */ typedef struct { - __IOM uint32_t EEP; /*!< (@ 0x00000000) Description cluster: Channel n event end-point */ - __IOM uint32_t TEP; /*!< (@ 0x00000004) Description cluster: Channel n task end-point */ + __IOM uint32_t EEP; /*!< (@ 0x00000000) Description cluster: Channel n event endpoint */ + __IOM uint32_t TEP; /*!< (@ 0x00000004) Description cluster: Channel n task endpoint */ } PPI_CH_Type; /*!< Size = 8 (0x8) */ @@ -632,7 +634,7 @@ typedef struct { * @brief PPI_FORK [FORK] (Fork) */ typedef struct { - __IOM uint32_t TEP; /*!< (@ 0x00000000) Description cluster: Channel n task end-point */ + __IOM uint32_t TEP; /*!< (@ 0x00000000) Description cluster: Channel n task endpoint */ } PPI_FORK_Type; /*!< Size = 4 (0x4) */ @@ -938,12 +940,32 @@ typedef struct { /*!< (@ 0x10001000) UICR Structu NFC antenna or GPIO */ __IOM uint32_t DEBUGCTRL; /*!< (@ 0x00000210) Processor debug control */ __IM uint32_t RESERVED3[60]; - __IOM uint32_t REGOUT0; /*!< (@ 0x00000304) GPIO reference voltage / external output supply - voltage in high voltage mode */ + __IOM uint32_t REGOUT0; /*!< (@ 0x00000304) Output voltage from REG0 regulator stage. The + maximum output voltage from this stage is + given as VDDH - V_VDDH-VDD. */ } NRF_UICR_Type; /*!< Size = 776 (0x308) */ +/* =========================================================================================================================== */ +/* ================ APPROTECT ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Access Port Protection (APPROTECT) + */ + +typedef struct { /*!< (@ 0x40000000) APPROTECT Structure */ + __IM uint32_t RESERVED[340]; + __IOM uint32_t FORCEPROTECT; /*!< (@ 0x00000550) Software force enable APPROTECT mechanism until + next reset. */ + __IM uint32_t RESERVED1; + __IOM uint32_t DISABLE; /*!< (@ 0x00000558) Software disable APPROTECT mechanism */ +} NRF_APPROTECT_Type; /*!< Size = 1372 (0x55c) */ + + + /* =========================================================================================================================== */ /* ================ CLOCK ================ */ /* =========================================================================================================================== */ @@ -1070,7 +1092,7 @@ typedef struct { /*!< (@ 0x50000000) P0 Structure __IOM uint32_t LATCH; /*!< (@ 0x00000520) Latch register indicating what GPIO pins that have met the criteria set in the PIN_CNF[n].SENSE registers */ - __IOM uint32_t DETECTMODE; /*!< (@ 0x00000524) Select between default DETECT signal behaviour + __IOM uint32_t DETECTMODE; /*!< (@ 0x00000524) Select between default DETECT signal behavior and LDETECT mode */ __IM uint32_t RESERVED1[118]; __IOM uint32_t PIN_CNF[32]; /*!< (@ 0x00000700) Description collection: Configuration of GPIO @@ -1287,8 +1309,8 @@ typedef struct { /*!< (@ 0x40002000) UARTE0 Struc __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ __IM uint32_t RESERVED9[93]; - __IOM uint32_t ERRORSRC; /*!< (@ 0x00000480) Error source Note : this register is read / write - one to clear. */ + __IOM uint32_t ERRORSRC; /*!< (@ 0x00000480) Error source This register is read/write one + to clear. */ __IM uint32_t RESERVED10[31]; __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable UART */ __IM uint32_t RESERVED11; @@ -1370,8 +1392,8 @@ typedef struct { /*!< (@ 0x40003000) SPIM0 Struct __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ __IM uint32_t RESERVED9[61]; __IOM uint32_t STALLSTAT; /*!< (@ 0x00000400) Stall status for EasyDMA RAM accesses. The fields - in this register is set to STALL by hardware - whenever a stall occurres and can be cleared + in this register are set to STALL by hardware + whenever a stall occurs and can be cleared (set to NOSTALL) by the CPU. */ __IM uint32_t RESERVED10[63]; __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable SPIM */ @@ -1520,9 +1542,8 @@ typedef struct { /*!< (@ 0x40003000) TWIM0 Struct __IM uint32_t RESERVED4[7]; __IOM uint32_t EVENTS_ERROR; /*!< (@ 0x00000124) TWI error */ __IM uint32_t RESERVED5[8]; - __IOM uint32_t EVENTS_SUSPENDED; /*!< (@ 0x00000148) Last byte has been sent out after the SUSPEND - task has been issued, TWI traffic is now - suspended. */ + __IOM uint32_t EVENTS_SUSPENDED; /*!< (@ 0x00000148) SUSPEND task has been issued, TWI traffic is + now suspended. */ __IOM uint32_t EVENTS_RXSTARTED; /*!< (@ 0x0000014C) Receive sequence started */ __IOM uint32_t EVENTS_TXSTARTED; /*!< (@ 0x00000150) Transmit sequence started */ __IM uint32_t RESERVED6[2]; @@ -1693,7 +1714,7 @@ typedef struct { /*!< (@ 0x40005000) NFCT Structu __IOM uint32_t NFCID1_3RD_LAST; /*!< (@ 0x00000598) Third last NFCID1 part (10 bytes ID) */ __IOM uint32_t AUTOCOLRESCONFIG; /*!< (@ 0x0000059C) Controls the auto collision resolution function. This setting must be done before the NFCT - peripheral is enabled. */ + peripheral is activated. */ __IOM uint32_t SENSRES; /*!< (@ 0x000005A0) NFC-A SENS_RES auto-response settings */ __IOM uint32_t SELRES; /*!< (@ 0x000005A4) NFC-A SEL_RES auto-response settings */ } NRF_NFCT_Type; /*!< Size = 1448 (0x5a8) */ @@ -1732,7 +1753,7 @@ typedef struct { /*!< (@ 0x40006000) GPIOTE Struc __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ __IM uint32_t RESERVED5[129]; __IOM uint32_t CONFIG[8]; /*!< (@ 0x00000510) Description collection: Configuration for OUT[n], - SET[n] and CLR[n] tasks and IN[n] event */ + SET[n], and CLR[n] tasks and IN[n] event */ } NRF_GPIOTE_Type; /*!< Size = 1328 (0x530) */ @@ -1853,8 +1874,8 @@ typedef struct { /*!< (@ 0x4000B000) RTC0 Structu __IOM uint32_t EVTENCLR; /*!< (@ 0x00000348) Disable event routing */ __IM uint32_t RESERVED4[110]; __IM uint32_t COUNTER; /*!< (@ 0x00000504) Current COUNTER value */ - __IOM uint32_t PRESCALER; /*!< (@ 0x00000508) 12 bit prescaler for COUNTER frequency (32768/(PRESCALER+1)).Mu - t be written when RTC is stopped */ + __IOM uint32_t PRESCALER; /*!< (@ 0x00000508) 12 bit prescaler for COUNTER frequency (32768/(PRESCALER+1)). + Must be written when RTC is stopped. */ __IM uint32_t RESERVED5[13]; __IOM uint32_t CC[4]; /*!< (@ 0x00000540) Description collection: Compare register n */ } NRF_RTC_Type; /*!< Size = 1360 (0x550) */ @@ -1881,25 +1902,25 @@ typedef struct { /*!< (@ 0x4000C000) TEMP Structu __IM uint32_t RESERVED2[127]; __IM int32_t TEMP; /*!< (@ 0x00000508) Temperature in degC (0.25deg steps) */ __IM uint32_t RESERVED3[5]; - __IOM uint32_t A0; /*!< (@ 0x00000520) Slope of 1st piece wise linear function */ - __IOM uint32_t A1; /*!< (@ 0x00000524) Slope of 2nd piece wise linear function */ - __IOM uint32_t A2; /*!< (@ 0x00000528) Slope of 3rd piece wise linear function */ - __IOM uint32_t A3; /*!< (@ 0x0000052C) Slope of 4th piece wise linear function */ - __IOM uint32_t A4; /*!< (@ 0x00000530) Slope of 5th piece wise linear function */ - __IOM uint32_t A5; /*!< (@ 0x00000534) Slope of 6th piece wise linear function */ + __IOM uint32_t A0; /*!< (@ 0x00000520) Slope of first piecewise linear function */ + __IOM uint32_t A1; /*!< (@ 0x00000524) Slope of second piecewise linear function */ + __IOM uint32_t A2; /*!< (@ 0x00000528) Slope of third piecewise linear function */ + __IOM uint32_t A3; /*!< (@ 0x0000052C) Slope of fourth piecewise linear function */ + __IOM uint32_t A4; /*!< (@ 0x00000530) Slope of fifth piecewise linear function */ + __IOM uint32_t A5; /*!< (@ 0x00000534) Slope of sixth piecewise linear function */ __IM uint32_t RESERVED4[2]; - __IOM uint32_t B0; /*!< (@ 0x00000540) y-intercept of 1st piece wise linear function */ - __IOM uint32_t B1; /*!< (@ 0x00000544) y-intercept of 2nd piece wise linear function */ - __IOM uint32_t B2; /*!< (@ 0x00000548) y-intercept of 3rd piece wise linear function */ - __IOM uint32_t B3; /*!< (@ 0x0000054C) y-intercept of 4th piece wise linear function */ - __IOM uint32_t B4; /*!< (@ 0x00000550) y-intercept of 5th piece wise linear function */ - __IOM uint32_t B5; /*!< (@ 0x00000554) y-intercept of 6th piece wise linear function */ + __IOM uint32_t B0; /*!< (@ 0x00000540) y-intercept of first piecewise linear function */ + __IOM uint32_t B1; /*!< (@ 0x00000544) y-intercept of second piecewise linear function */ + __IOM uint32_t B2; /*!< (@ 0x00000548) y-intercept of third piecewise linear function */ + __IOM uint32_t B3; /*!< (@ 0x0000054C) y-intercept of fourth piecewise linear function */ + __IOM uint32_t B4; /*!< (@ 0x00000550) y-intercept of fifth piecewise linear function */ + __IOM uint32_t B5; /*!< (@ 0x00000554) y-intercept of sixth piecewise linear function */ __IM uint32_t RESERVED5[2]; - __IOM uint32_t T0; /*!< (@ 0x00000560) End point of 1st piece wise linear function */ - __IOM uint32_t T1; /*!< (@ 0x00000564) End point of 2nd piece wise linear function */ - __IOM uint32_t T2; /*!< (@ 0x00000568) End point of 3rd piece wise linear function */ - __IOM uint32_t T3; /*!< (@ 0x0000056C) End point of 4th piece wise linear function */ - __IOM uint32_t T4; /*!< (@ 0x00000570) End point of 5th piece wise linear function */ + __IOM uint32_t T0; /*!< (@ 0x00000560) End point of first piecewise linear function */ + __IOM uint32_t T1; /*!< (@ 0x00000564) End point of second piecewise linear function */ + __IOM uint32_t T2; /*!< (@ 0x00000568) End point of third piecewise linear function */ + __IOM uint32_t T3; /*!< (@ 0x0000056C) End point of fourth piecewise linear function */ + __IOM uint32_t T4; /*!< (@ 0x00000570) End point of fifth piecewise linear function */ } NRF_TEMP_Type; /*!< Size = 1396 (0x574) */ @@ -2000,7 +2021,7 @@ typedef struct { /*!< (@ 0x4000F000) AAR Structur */ typedef struct { /*!< (@ 0x4000F000) CCM Structure */ - __OM uint32_t TASKS_KSGEN; /*!< (@ 0x00000000) Start generation of key-stream. This operation + __OM uint32_t TASKS_KSGEN; /*!< (@ 0x00000000) Start generation of keystream. This operation will stop by itself when completed. */ __OM uint32_t TASKS_CRYPT; /*!< (@ 0x00000004) Start encryption/decryption. This operation will stop by itself when completed. */ @@ -2009,7 +2030,7 @@ typedef struct { /*!< (@ 0x4000F000) CCM Structur the contents of the RATEOVERRIDE register for any ongoing encryption/decryption */ __IM uint32_t RESERVED[60]; - __IOM uint32_t EVENTS_ENDKSGEN; /*!< (@ 0x00000100) Key-stream generation complete */ + __IOM uint32_t EVENTS_ENDKSGEN; /*!< (@ 0x00000100) Keystream generation complete */ __IOM uint32_t EVENTS_ENDCRYPT; /*!< (@ 0x00000104) Encrypt/decrypt complete */ __IOM uint32_t EVENTS_ERROR; /*!< (@ 0x00000108) Deprecated register - CCM error event */ __IM uint32_t RESERVED1[61]; @@ -2027,7 +2048,7 @@ typedef struct { /*!< (@ 0x4000F000) CCM Structur __IOM uint32_t INPTR; /*!< (@ 0x0000050C) Input pointer */ __IOM uint32_t OUTPTR; /*!< (@ 0x00000510) Output pointer */ __IOM uint32_t SCRATCHPTR; /*!< (@ 0x00000514) Pointer to data area used for temporary storage */ - __IOM uint32_t MAXPACKETSIZE; /*!< (@ 0x00000518) Length of key-stream generated when MODE.LENGTH + __IOM uint32_t MAXPACKETSIZE; /*!< (@ 0x00000518) Length of keystream generated when MODE.LENGTH = Extended. */ __IOM uint32_t RATEOVERRIDE; /*!< (@ 0x0000051C) Data rate override setting. */ } NRF_CCM_Type; /*!< Size = 1312 (0x520) */ @@ -2157,7 +2178,7 @@ typedef struct { /*!< (@ 0x40013000) COMP Structu /** - * @brief Low Power Comparator (LPCOMP) + * @brief Low-power comparator (LPCOMP) */ typedef struct { /*!< (@ 0x40013000) LPCOMP Structure */ @@ -2195,7 +2216,7 @@ typedef struct { /*!< (@ 0x40013000) LPCOMP Struc /** - * @brief Event Generator Unit 0 (EGU0) + * @brief Event generator unit 0 (EGU0) */ typedef struct { /*!< (@ 0x40014000) EGU0 Structure */ @@ -2357,23 +2378,23 @@ typedef struct { /*!< (@ 0x4001E000) NVMC Structu __IOM uint32_t CONFIG; /*!< (@ 0x00000504) Configuration register */ union { - __IOM uint32_t ERASEPAGE; /*!< (@ 0x00000508) Register for erasing a page in code area */ - __IOM uint32_t ERASEPCR1; /*!< (@ 0x00000508) Deprecated register - Register for erasing a - page in code area. Equivalent to ERASEPAGE. */ + __OM uint32_t ERASEPAGE; /*!< (@ 0x00000508) Register for erasing a page in code area */ + __OM uint32_t ERASEPCR1; /*!< (@ 0x00000508) Deprecated register - Register for erasing a + page in code area, equivalent to ERASEPAGE */ }; - __IOM uint32_t ERASEALL; /*!< (@ 0x0000050C) Register for erasing all non-volatile user memory */ - __IOM uint32_t ERASEPCR0; /*!< (@ 0x00000510) Deprecated register - Register for erasing a - page in code area. Equivalent to ERASEPAGE. */ - __IOM uint32_t ERASEUICR; /*!< (@ 0x00000514) Register for erasing user information configuration + __OM uint32_t ERASEALL; /*!< (@ 0x0000050C) Register for erasing all non-volatile user memory */ + __OM uint32_t ERASEPCR0; /*!< (@ 0x00000510) Deprecated register - Register for erasing a + page in code area, equivalent to ERASEPAGE */ + __OM uint32_t ERASEUICR; /*!< (@ 0x00000514) Register for erasing user information configuration registers */ - __IOM uint32_t ERASEPAGEPARTIAL; /*!< (@ 0x00000518) Register for partial erase of a page in code + __OM uint32_t ERASEPAGEPARTIAL; /*!< (@ 0x00000518) Register for partial erase of a page in code area */ __IOM uint32_t ERASEPAGEPARTIALCFG; /*!< (@ 0x0000051C) Register for partial erase configuration */ __IM uint32_t RESERVED3[8]; - __IOM uint32_t ICACHECNF; /*!< (@ 0x00000540) I-code cache configuration register. */ + __IOM uint32_t ICACHECNF; /*!< (@ 0x00000540) I-code cache configuration register */ __IM uint32_t RESERVED4; - __IOM uint32_t IHIT; /*!< (@ 0x00000548) I-code cache hit counter. */ - __IOM uint32_t IMISS; /*!< (@ 0x0000054C) I-code cache miss counter. */ + __IOM uint32_t IHIT; /*!< (@ 0x00000548) I-code cache hit counter */ + __IOM uint32_t IMISS; /*!< (@ 0x0000054C) I-code cache miss counter */ } NRF_NVMC_Type; /*!< Size = 1360 (0x550) */ @@ -2542,17 +2563,17 @@ typedef struct { /*!< (@ 0x40027000) USBD Structu have been captured on all endpoints reported in the EPSTATUS register */ __IOM uint32_t EVENTS_ENDEPIN[8]; /*!< (@ 0x00000108) Description collection: The whole EPIN[n] buffer - has been consumed. The RAM buffer can be - accessed safely by software. */ + has been consumed. The buffer can be accessed + safely by software. */ __IOM uint32_t EVENTS_EP0DATADONE; /*!< (@ 0x00000128) An acknowledged data transfer has taken place on the control endpoint */ __IOM uint32_t EVENTS_ENDISOIN; /*!< (@ 0x0000012C) The whole ISOIN buffer has been consumed. The - RAM buffer can be accessed safely by software. */ + buffer can be accessed safely by software. */ __IOM uint32_t EVENTS_ENDEPOUT[8]; /*!< (@ 0x00000130) Description collection: The whole EPOUT[n] buffer - has been consumed. The RAM buffer can be - accessed safely by software. */ + has been consumed. The buffer can be accessed + safely by software. */ __IOM uint32_t EVENTS_ENDISOOUT; /*!< (@ 0x00000150) The whole ISOOUT buffer has been consumed. The - RAM buffer can be accessed safely by software. */ + buffer can be accessed safely by software. */ __IOM uint32_t EVENTS_SOF; /*!< (@ 0x00000154) Signals that a SOF (start of frame) condition has been detected on USB lines */ __IOM uint32_t EVENTS_USBEVENT; /*!< (@ 0x00000158) An event or an error not covered by specific @@ -2684,7 +2705,7 @@ typedef struct { /*!< (@ 0x5002A000) CC_HOST_RGF __IOM uint32_t HOST_CRYPTOKEY_SEL; /*!< (@ 0x00001A38) AES hardware key select */ __IM uint32_t RESERVED1[4]; __IOM uint32_t HOST_IOT_KPRTL_LOCK; /*!< (@ 0x00001A4C) This write-once register is the K_PRTL lock register. - When this register is set, K_PRTL can not + When this register is set, K_PRTL cannot be used and a zeroed key will be used instead. The value of this register is saved in the CRYPTOCELL AO power domain. */ @@ -2737,6 +2758,7 @@ typedef struct { /*!< (@ 0x5002A000) CRYPTOCELL S #define NRF_FICR_BASE 0x10000000UL #define NRF_UICR_BASE 0x10001000UL +#define NRF_APPROTECT_BASE 0x40000000UL #define NRF_CLOCK_BASE 0x40000000UL #define NRF_POWER_BASE 0x40000000UL #define NRF_P0_BASE 0x50000000UL @@ -2823,6 +2845,7 @@ typedef struct { /*!< (@ 0x5002A000) CRYPTOCELL S #define NRF_FICR ((NRF_FICR_Type*) NRF_FICR_BASE) #define NRF_UICR ((NRF_UICR_Type*) NRF_UICR_BASE) +#define NRF_APPROTECT ((NRF_APPROTECT_Type*) NRF_APPROTECT_BASE) #define NRF_CLOCK ((NRF_CLOCK_Type*) NRF_CLOCK_BASE) #define NRF_POWER ((NRF_POWER_Type*) NRF_POWER_BASE) #define NRF_P0 ((NRF_GPIO_Type*) NRF_P0_BASE) diff --git a/mdk/nrf52840.svd b/mdk/nrf52840.svd index 399571b681..a5e5325c60 100644 --- a/mdk/nrf52840.svd +++ b/mdk/nrf52840.svd @@ -8,7 +8,9 @@ 1 nRF52840 reference description for radio MCU with ARM 32-bit Cortex-M4 Microcontroller -Copyright (c) 2010 - 2020, Nordic Semiconductor ASA All rights reserved.\n +Copyright (c) 2010 - 2021, Nordic Semiconductor ASA All rights reserved.\n +\n +SPDX-License-Identifier: BSD-3-Clause\n \n Redistribution and use in source and binary forms, with or without\n modification, are permitted provided that the following conditions are met:\n @@ -214,6 +216,11 @@ POSSIBILITY OF SUCH DAMAGE.\n 0 31 + + N52820 + nRF52820 + 0x52820 + N52833 nRF52833 @@ -281,6 +288,31 @@ POSSIBILITY OF SUCH DAMAGE.\n AAAB 0x41414142 + + AAC0 + AAC0 + 0x41414330 + + + AADA + AADA + 0x41414441 + + + AAD0 + AAD0 + 0x41414430 + + + AAD1 + AAD1 + 0x41414431 + + + AAEA + AAEA + 0x41414541 + Unspecified Unspecified @@ -305,12 +337,12 @@ POSSIBILITY OF SUCH DAMAGE.\n QI - QIxx - 73-pin aQFN + QIxx - 7x7 73-pin aQFN 0x2004 CK - CKxx - WLCSP + CKxx - 3.544 x 3.607 WLCSP 0x2005 @@ -457,7 +489,7 @@ POSSIBILITY OF SUCH DAMAGE.\n Slope definition A0 0x000 read-only - 0xFFFFF320 + 0xFFFFFFFF A @@ -472,7 +504,7 @@ POSSIBILITY OF SUCH DAMAGE.\n Slope definition A1 0x004 read-only - 0xFFFFF343 + 0xFFFFFFFF A @@ -487,7 +519,7 @@ POSSIBILITY OF SUCH DAMAGE.\n Slope definition A2 0x008 read-only - 0xFFFFF35D + 0xFFFFFFFF A @@ -502,7 +534,7 @@ POSSIBILITY OF SUCH DAMAGE.\n Slope definition A3 0x00C read-only - 0xFFFFF400 + 0xFFFFFFFF A @@ -517,7 +549,7 @@ POSSIBILITY OF SUCH DAMAGE.\n Slope definition A4 0x010 read-only - 0xFFFFF452 + 0xFFFFFFFF A @@ -532,7 +564,7 @@ POSSIBILITY OF SUCH DAMAGE.\n Slope definition A5 0x014 read-only - 0xFFFFF37B + 0xFFFFFFFF A @@ -547,7 +579,7 @@ POSSIBILITY OF SUCH DAMAGE.\n Y-intercept B0 0x018 read-only - 0xFFFF3FCC + 0xFFFFFFFF B @@ -562,7 +594,7 @@ POSSIBILITY OF SUCH DAMAGE.\n Y-intercept B1 0x01C read-only - 0xFFFF3F98 + 0xFFFFFFFF B @@ -577,7 +609,7 @@ POSSIBILITY OF SUCH DAMAGE.\n Y-intercept B2 0x020 read-only - 0xFFFF3F98 + 0xFFFFFFFF B @@ -592,7 +624,7 @@ POSSIBILITY OF SUCH DAMAGE.\n Y-intercept B3 0x024 read-only - 0xFFFF0012 + 0xFFFFFFFF B @@ -607,7 +639,7 @@ POSSIBILITY OF SUCH DAMAGE.\n Y-intercept B4 0x028 read-only - 0xFFFF004D + 0xFFFFFFFF B @@ -622,7 +654,7 @@ POSSIBILITY OF SUCH DAMAGE.\n Y-intercept B5 0x02C read-only - 0xFFFF3E10 + 0xFFFFFFFF B @@ -637,7 +669,7 @@ POSSIBILITY OF SUCH DAMAGE.\n Segment end T0 0x030 read-only - 0xFFFFFFE2 + 0xFFFFFFFF T @@ -652,7 +684,7 @@ POSSIBILITY OF SUCH DAMAGE.\n Segment end T1 0x034 read-only - 0xFFFFFF00 + 0xFFFFFFFF T @@ -667,7 +699,7 @@ POSSIBILITY OF SUCH DAMAGE.\n Segment end T2 0x038 read-only - 0xFFFFFF14 + 0xFFFFFFFF T @@ -682,7 +714,7 @@ POSSIBILITY OF SUCH DAMAGE.\n Segment end T3 0x03C read-only - 0xFFFFFF19 + 0xFFFFFFFF T @@ -697,7 +729,7 @@ POSSIBILITY OF SUCH DAMAGE.\n Segment end T4 0x040 read-only - 0xFFFFFF50 + 0xFFFFFFFF T @@ -1095,9 +1127,14 @@ POSSIBILITY OF SUCH DAMAGE.\n Disabled - Disable + Hardware disable of access port protection for devices where access port protection is controlled by hardware 0xFF + + HwDisabled + Hardware disable of access port protection for devices where access port protection is controlled by hardware and software + 0x5A + Enabled Enable @@ -1122,12 +1159,12 @@ POSSIBILITY OF SUCH DAMAGE.\n Disabled - Operation as GPIO pins. Same protection as normal GPIO pins + Operation as GPIO pins. Same protection as normal GPIO pins. 0 NFC - Operation as NFC antenna pins. Configures the protection for NFC operation + Operation as NFC antenna pins. Configures the protection for NFC operation. 1 @@ -1181,14 +1218,14 @@ POSSIBILITY OF SUCH DAMAGE.\n REGOUT0 - GPIO reference voltage / external output supply voltage in high voltage mode + Output voltage from REG0 regulator stage. The maximum output voltage from this stage is given as VDDH - V_VDDH-VDD. 0x304 read-write 0xFFFFFFFF VOUT - Output voltage from of REG0 regulator stage. The maximum output voltage from this stage is given as VDDH - VEXDIF. + Output voltage from REG0 regulator stage. 0 2 @@ -1233,10 +1270,70 @@ POSSIBILITY OF SUCH DAMAGE.\n + + APPROTECT + Access Port Protection + 0x40000000 + + 0 + 0x1000 + registers + + APPROTECT + 0x20 + + + FORCEPROTECT + Software force enable APPROTECT mechanism until next reset. + 0x550 + read-writeonce + 0xFFFFFFFF + + + FORCEPROTECT + Write 0x0 to force enable APPROTECT mechanism + 0 + 7 + + write + + Force + Software force enable APPROTECT mechanism + 0x0 + + + + + + + DISABLE + Software disable APPROTECT mechanism + 0x558 + read-write + 0x00000000 + + + DISABLE + Software disable APPROTECT mechanism + 0 + 7 + + + SwDisable + Software disable APPROTECT mechanism + 0x5A + + + + + + + CLOCK Clock control 0x40000000 + APPROTECT 0 0x1000 @@ -2287,7 +2384,7 @@ POSSIBILITY OF SUCH DAMAGE.\n POWER Power control 0x40000000 - CLOCK + APPROTECT 0 0x1000 @@ -5516,8 +5613,8 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets the pin high; writing a '0' has no effect 1 + Write: a '1' sets the pin high; a '0' has no effect @@ -5543,7 +5640,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets the pin high; writing a '0' has no effect + Write: a '1' sets the pin high; a '0' has no effect 1 @@ -5570,7 +5667,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets the pin high; writing a '0' has no effect + Write: a '1' sets the pin high; a '0' has no effect 1 @@ -5597,7 +5694,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets the pin high; writing a '0' has no effect + Write: a '1' sets the pin high; a '0' has no effect 1 @@ -5624,7 +5721,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets the pin high; writing a '0' has no effect + Write: a '1' sets the pin high; a '0' has no effect 1 @@ -5651,7 +5748,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets the pin high; writing a '0' has no effect + Write: a '1' sets the pin high; a '0' has no effect 1 @@ -5678,7 +5775,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets the pin high; writing a '0' has no effect + Write: a '1' sets the pin high; a '0' has no effect 1 @@ -5705,7 +5802,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets the pin high; writing a '0' has no effect + Write: a '1' sets the pin high; a '0' has no effect 1 @@ -5732,7 +5829,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets the pin high; writing a '0' has no effect + Write: a '1' sets the pin high; a '0' has no effect 1 @@ -5759,7 +5856,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets the pin high; writing a '0' has no effect + Write: a '1' sets the pin high; a '0' has no effect 1 @@ -5786,7 +5883,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets the pin high; writing a '0' has no effect + Write: a '1' sets the pin high; a '0' has no effect 1 @@ -5813,7 +5910,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets the pin high; writing a '0' has no effect + Write: a '1' sets the pin high; a '0' has no effect 1 @@ -5840,7 +5937,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets the pin high; writing a '0' has no effect + Write: a '1' sets the pin high; a '0' has no effect 1 @@ -5867,7 +5964,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets the pin high; writing a '0' has no effect + Write: a '1' sets the pin high; a '0' has no effect 1 @@ -5894,7 +5991,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets the pin high; writing a '0' has no effect + Write: a '1' sets the pin high; a '0' has no effect 1 @@ -5921,7 +6018,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets the pin high; writing a '0' has no effect + Write: a '1' sets the pin high; a '0' has no effect 1 @@ -5948,7 +6045,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets the pin high; writing a '0' has no effect + Write: a '1' sets the pin high; a '0' has no effect 1 @@ -5975,7 +6072,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets the pin high; writing a '0' has no effect + Write: a '1' sets the pin high; a '0' has no effect 1 @@ -6002,7 +6099,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets the pin high; writing a '0' has no effect + Write: a '1' sets the pin high; a '0' has no effect 1 @@ -6029,7 +6126,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets the pin high; writing a '0' has no effect + Write: a '1' sets the pin high; a '0' has no effect 1 @@ -6056,7 +6153,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets the pin high; writing a '0' has no effect + Write: a '1' sets the pin high; a '0' has no effect 1 @@ -6083,7 +6180,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets the pin high; writing a '0' has no effect + Write: a '1' sets the pin high; a '0' has no effect 1 @@ -6110,7 +6207,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets the pin high; writing a '0' has no effect + Write: a '1' sets the pin high; a '0' has no effect 1 @@ -6137,7 +6234,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets the pin high; writing a '0' has no effect + Write: a '1' sets the pin high; a '0' has no effect 1 @@ -6164,7 +6261,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets the pin high; writing a '0' has no effect + Write: a '1' sets the pin high; a '0' has no effect 1 @@ -6191,7 +6288,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets the pin high; writing a '0' has no effect + Write: a '1' sets the pin high; a '0' has no effect 1 @@ -6218,7 +6315,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets the pin high; writing a '0' has no effect + Write: a '1' sets the pin high; a '0' has no effect 1 @@ -6245,7 +6342,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets the pin high; writing a '0' has no effect + Write: a '1' sets the pin high; a '0' has no effect 1 @@ -6272,7 +6369,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets the pin high; writing a '0' has no effect + Write: a '1' sets the pin high; a '0' has no effect 1 @@ -6299,7 +6396,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets the pin high; writing a '0' has no effect + Write: a '1' sets the pin high; a '0' has no effect 1 @@ -6326,7 +6423,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets the pin high; writing a '0' has no effect + Write: a '1' sets the pin high; a '0' has no effect 1 @@ -6353,7 +6450,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets the pin high; writing a '0' has no effect + Write: a '1' sets the pin high; a '0' has no effect 1 @@ -6389,7 +6486,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect + Write: a '1' sets the pin low; a '0' has no effect 1 @@ -6416,7 +6513,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect + Write: a '1' sets the pin low; a '0' has no effect 1 @@ -6443,7 +6540,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect + Write: a '1' sets the pin low; a '0' has no effect 1 @@ -6470,7 +6567,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect + Write: a '1' sets the pin low; a '0' has no effect 1 @@ -6497,7 +6594,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect + Write: a '1' sets the pin low; a '0' has no effect 1 @@ -6524,7 +6621,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect + Write: a '1' sets the pin low; a '0' has no effect 1 @@ -6551,7 +6648,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect + Write: a '1' sets the pin low; a '0' has no effect 1 @@ -6578,7 +6675,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect + Write: a '1' sets the pin low; a '0' has no effect 1 @@ -6605,7 +6702,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect + Write: a '1' sets the pin low; a '0' has no effect 1 @@ -6632,7 +6729,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect + Write: a '1' sets the pin low; a '0' has no effect 1 @@ -6659,7 +6756,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect + Write: a '1' sets the pin low; a '0' has no effect 1 @@ -6686,7 +6783,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect + Write: a '1' sets the pin low; a '0' has no effect 1 @@ -6713,7 +6810,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect + Write: a '1' sets the pin low; a '0' has no effect 1 @@ -6740,7 +6837,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect + Write: a '1' sets the pin low; a '0' has no effect 1 @@ -6767,7 +6864,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect + Write: a '1' sets the pin low; a '0' has no effect 1 @@ -6794,7 +6891,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect + Write: a '1' sets the pin low; a '0' has no effect 1 @@ -6821,7 +6918,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect + Write: a '1' sets the pin low; a '0' has no effect 1 @@ -6848,7 +6945,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect + Write: a '1' sets the pin low; a '0' has no effect 1 @@ -6875,7 +6972,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect + Write: a '1' sets the pin low; a '0' has no effect 1 @@ -6902,7 +6999,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect + Write: a '1' sets the pin low; a '0' has no effect 1 @@ -6929,7 +7026,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect + Write: a '1' sets the pin low; a '0' has no effect 1 @@ -6956,7 +7053,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect + Write: a '1' sets the pin low; a '0' has no effect 1 @@ -6983,7 +7080,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect + Write: a '1' sets the pin low; a '0' has no effect 1 @@ -7010,7 +7107,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect + Write: a '1' sets the pin low; a '0' has no effect 1 @@ -7037,7 +7134,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect + Write: a '1' sets the pin low; a '0' has no effect 1 @@ -7064,7 +7161,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect + Write: a '1' sets the pin low; a '0' has no effect 1 @@ -7091,7 +7188,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect + Write: a '1' sets the pin low; a '0' has no effect 1 @@ -7118,7 +7215,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect + Write: a '1' sets the pin low; a '0' has no effect 1 @@ -7145,7 +7242,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect + Write: a '1' sets the pin low; a '0' has no effect 1 @@ -7172,7 +7269,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect + Write: a '1' sets the pin low; a '0' has no effect 1 @@ -7199,7 +7296,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect + Write: a '1' sets the pin low; a '0' has no effect 1 @@ -7226,7 +7323,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect + Write: a '1' sets the pin low; a '0' has no effect 1 @@ -8430,7 +8527,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets pin to output; writing a '0' has no effect + Write: a '1' sets pin to output; a '0' has no effect 1 @@ -8457,7 +8554,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets pin to output; writing a '0' has no effect + Write: a '1' sets pin to output; a '0' has no effect 1 @@ -8484,7 +8581,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets pin to output; writing a '0' has no effect + Write: a '1' sets pin to output; a '0' has no effect 1 @@ -8511,7 +8608,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets pin to output; writing a '0' has no effect + Write: a '1' sets pin to output; a '0' has no effect 1 @@ -8538,7 +8635,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets pin to output; writing a '0' has no effect + Write: a '1' sets pin to output; a '0' has no effect 1 @@ -8565,7 +8662,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets pin to output; writing a '0' has no effect + Write: a '1' sets pin to output; a '0' has no effect 1 @@ -8592,7 +8689,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets pin to output; writing a '0' has no effect + Write: a '1' sets pin to output; a '0' has no effect 1 @@ -8619,7 +8716,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets pin to output; writing a '0' has no effect + Write: a '1' sets pin to output; a '0' has no effect 1 @@ -8646,7 +8743,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets pin to output; writing a '0' has no effect + Write: a '1' sets pin to output; a '0' has no effect 1 @@ -8673,7 +8770,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets pin to output; writing a '0' has no effect + Write: a '1' sets pin to output; a '0' has no effect 1 @@ -8700,7 +8797,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets pin to output; writing a '0' has no effect + Write: a '1' sets pin to output; a '0' has no effect 1 @@ -8727,7 +8824,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets pin to output; writing a '0' has no effect + Write: a '1' sets pin to output; a '0' has no effect 1 @@ -8754,7 +8851,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets pin to output; writing a '0' has no effect + Write: a '1' sets pin to output; a '0' has no effect 1 @@ -8781,7 +8878,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets pin to output; writing a '0' has no effect + Write: a '1' sets pin to output; a '0' has no effect 1 @@ -8808,7 +8905,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets pin to output; writing a '0' has no effect + Write: a '1' sets pin to output; a '0' has no effect 1 @@ -8835,7 +8932,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets pin to output; writing a '0' has no effect + Write: a '1' sets pin to output; a '0' has no effect 1 @@ -8862,7 +8959,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets pin to output; writing a '0' has no effect + Write: a '1' sets pin to output; a '0' has no effect 1 @@ -8889,7 +8986,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets pin to output; writing a '0' has no effect + Write: a '1' sets pin to output; a '0' has no effect 1 @@ -8916,7 +9013,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets pin to output; writing a '0' has no effect + Write: a '1' sets pin to output; a '0' has no effect 1 @@ -8943,7 +9040,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets pin to output; writing a '0' has no effect + Write: a '1' sets pin to output; a '0' has no effect 1 @@ -8970,7 +9067,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets pin to output; writing a '0' has no effect + Write: a '1' sets pin to output; a '0' has no effect 1 @@ -8997,7 +9094,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets pin to output; writing a '0' has no effect + Write: a '1' sets pin to output; a '0' has no effect 1 @@ -9024,7 +9121,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets pin to output; writing a '0' has no effect + Write: a '1' sets pin to output; a '0' has no effect 1 @@ -9051,7 +9148,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets pin to output; writing a '0' has no effect + Write: a '1' sets pin to output; a '0' has no effect 1 @@ -9078,7 +9175,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets pin to output; writing a '0' has no effect + Write: a '1' sets pin to output; a '0' has no effect 1 @@ -9105,7 +9202,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets pin to output; writing a '0' has no effect + Write: a '1' sets pin to output; a '0' has no effect 1 @@ -9132,7 +9229,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets pin to output; writing a '0' has no effect + Write: a '1' sets pin to output; a '0' has no effect 1 @@ -9159,7 +9256,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets pin to output; writing a '0' has no effect + Write: a '1' sets pin to output; a '0' has no effect 1 @@ -9186,7 +9283,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets pin to output; writing a '0' has no effect + Write: a '1' sets pin to output; a '0' has no effect 1 @@ -9213,7 +9310,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets pin to output; writing a '0' has no effect + Write: a '1' sets pin to output; a '0' has no effect 1 @@ -9240,7 +9337,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets pin to output; writing a '0' has no effect + Write: a '1' sets pin to output; a '0' has no effect 1 @@ -9267,7 +9364,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets pin to output; writing a '0' has no effect + Write: a '1' sets pin to output; a '0' has no effect 1 @@ -9303,7 +9400,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect + Write: a '1' sets pin to input; a '0' has no effect 1 @@ -9330,7 +9427,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect + Write: a '1' sets pin to input; a '0' has no effect 1 @@ -9357,7 +9454,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect + Write: a '1' sets pin to input; a '0' has no effect 1 @@ -9384,7 +9481,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect + Write: a '1' sets pin to input; a '0' has no effect 1 @@ -9411,7 +9508,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect + Write: a '1' sets pin to input; a '0' has no effect 1 @@ -9438,7 +9535,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect + Write: a '1' sets pin to input; a '0' has no effect 1 @@ -9465,7 +9562,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect + Write: a '1' sets pin to input; a '0' has no effect 1 @@ -9492,7 +9589,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect + Write: a '1' sets pin to input; a '0' has no effect 1 @@ -9519,7 +9616,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect + Write: a '1' sets pin to input; a '0' has no effect 1 @@ -9546,7 +9643,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect + Write: a '1' sets pin to input; a '0' has no effect 1 @@ -9573,7 +9670,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect + Write: a '1' sets pin to input; a '0' has no effect 1 @@ -9600,7 +9697,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect + Write: a '1' sets pin to input; a '0' has no effect 1 @@ -9627,7 +9724,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect + Write: a '1' sets pin to input; a '0' has no effect 1 @@ -9654,7 +9751,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect + Write: a '1' sets pin to input; a '0' has no effect 1 @@ -9681,7 +9778,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect + Write: a '1' sets pin to input; a '0' has no effect 1 @@ -9708,7 +9805,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect + Write: a '1' sets pin to input; a '0' has no effect 1 @@ -9735,7 +9832,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect + Write: a '1' sets pin to input; a '0' has no effect 1 @@ -9762,7 +9859,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect + Write: a '1' sets pin to input; a '0' has no effect 1 @@ -9789,7 +9886,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect + Write: a '1' sets pin to input; a '0' has no effect 1 @@ -9816,7 +9913,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect + Write: a '1' sets pin to input; a '0' has no effect 1 @@ -9843,7 +9940,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect + Write: a '1' sets pin to input; a '0' has no effect 1 @@ -9870,7 +9967,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect + Write: a '1' sets pin to input; a '0' has no effect 1 @@ -9897,7 +9994,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect + Write: a '1' sets pin to input; a '0' has no effect 1 @@ -9924,7 +10021,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect + Write: a '1' sets pin to input; a '0' has no effect 1 @@ -9951,7 +10048,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect + Write: a '1' sets pin to input; a '0' has no effect 1 @@ -9978,7 +10075,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect + Write: a '1' sets pin to input; a '0' has no effect 1 @@ -10005,7 +10102,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect + Write: a '1' sets pin to input; a '0' has no effect 1 @@ -10032,7 +10129,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect + Write: a '1' sets pin to input; a '0' has no effect 1 @@ -10059,7 +10156,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect + Write: a '1' sets pin to input; a '0' has no effect 1 @@ -10086,7 +10183,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect + Write: a '1' sets pin to input; a '0' has no effect 1 @@ -10113,7 +10210,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect + Write: a '1' sets pin to input; a '0' has no effect 1 @@ -10140,7 +10237,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect + Write: a '1' sets pin to input; a '0' has no effect 1 @@ -10733,13 +10830,13 @@ POSSIBILITY OF SUCH DAMAGE.\n DETECTMODE - Select between default DETECT signal behaviour and LDETECT mode + Select between default DETECT signal behavior and LDETECT mode 0x524 read-write DETECTMODE - Select between default DETECT signal behaviour and LDETECT mode + Select between default DETECT signal behavior and LDETECT mode 0 0 @@ -10750,7 +10847,7 @@ POSSIBILITY OF SUCH DAMAGE.\n LDETECT - Use the latched LDETECT behaviour + Use the latched LDETECT behavior 1 @@ -17181,7 +17278,7 @@ POSSIBILITY OF SUCH DAMAGE.\n ERRORSRC - Error source Note : this register is read / write one to clear. + Error source This register is read/write one to clear. 0x480 read-write oneToClear @@ -17553,7 +17650,7 @@ POSSIBILITY OF SUCH DAMAGE.\n Baud1M - 1Mega baud + 1 megabaud 0x10000000 @@ -18008,7 +18105,7 @@ POSSIBILITY OF SUCH DAMAGE.\n TXD - TX data to send. Double buffered + TX data to send. Double buffered. 0 7 @@ -18676,7 +18773,7 @@ POSSIBILITY OF SUCH DAMAGE.\n STALLSTAT - Stall status for EasyDMA RAM accesses. The fields in this register is set to STALL by hardware whenever a stall occurres and can be cleared (set to NOSTALL) by the CPU. + Stall status for EasyDMA RAM accesses. The fields in this register are set to STALL by hardware whenever a stall occurs and can be cleared (set to NOSTALL) by the CPU. 0x400 read-write 0x00000000 @@ -21281,13 +21378,13 @@ POSSIBILITY OF SUCH DAMAGE.\n EVENTS_SUSPENDED - Last byte has been sent out after the SUSPEND task has been issued, TWI traffic is now suspended. + SUSPEND task has been issued, TWI traffic is now suspended. 0x148 read-write EVENTS_SUSPENDED - Last byte has been sent out after the SUSPEND task has been issued, TWI traffic is now suspended. + SUSPEND task has been issued, TWI traffic is now suspended. 0 0 @@ -23275,7 +23372,7 @@ POSSIBILITY OF SUCH DAMAGE.\n MATCH - Which of the addresses in {ADDRESS} matched the incoming address + Indication of which address in {ADDRESS} that matched the incoming address 0 0 @@ -25982,7 +26079,7 @@ POSSIBILITY OF SUCH DAMAGE.\n AUTOCOLRESCONFIG - Controls the auto collision resolution function. This setting must be done before the NFCT peripheral is enabled. + Controls the auto collision resolution function. This setting must be done before the NFCT peripheral is activated. 0x59C read-write 0x00000002 @@ -26780,7 +26877,7 @@ POSSIBILITY OF SUCH DAMAGE.\n 0x8 0x4 CONFIG[%s] - Description collection: Configuration for OUT[n], SET[n] and CLR[n] tasks and IN[n] event + Description collection: Configuration for OUT[n], SET[n], and CLR[n] tasks and IN[n] event 0x510 read-write @@ -26809,7 +26906,7 @@ POSSIBILITY OF SUCH DAMAGE.\n PSEL - GPIO number associated with SET[n], CLR[n] and OUT[n] tasks and IN[n] event + GPIO number associated with SET[n], CLR[n], and OUT[n] tasks and IN[n] event 8 12 @@ -31254,7 +31351,7 @@ POSSIBILITY OF SUCH DAMAGE.\n PRESCALER - 12 bit prescaler for COUNTER frequency (32768/(PRESCALER+1)).Must be written when RTC is stopped + 12 bit prescaler for COUNTER frequency (32768/(PRESCALER+1)). Must be written when RTC is stopped. 0x508 read-write @@ -31455,14 +31552,14 @@ POSSIBILITY OF SUCH DAMAGE.\n A0 - Slope of 1st piece wise linear function + Slope of first piecewise linear function 0x520 read-write 0x00000326 A0 - Slope of 1st piece wise linear function + Slope of first piecewise linear function 0 11 @@ -31470,14 +31567,14 @@ POSSIBILITY OF SUCH DAMAGE.\n A1 - Slope of 2nd piece wise linear function + Slope of second piecewise linear function 0x524 read-write 0x00000348 A1 - Slope of 2nd piece wise linear function + Slope of second piecewise linear function 0 11 @@ -31485,14 +31582,14 @@ POSSIBILITY OF SUCH DAMAGE.\n A2 - Slope of 3rd piece wise linear function + Slope of third piecewise linear function 0x528 read-write 0x000003AA A2 - Slope of 3rd piece wise linear function + Slope of third piecewise linear function 0 11 @@ -31500,14 +31597,14 @@ POSSIBILITY OF SUCH DAMAGE.\n A3 - Slope of 4th piece wise linear function + Slope of fourth piecewise linear function 0x52C read-write 0x0000040E A3 - Slope of 4th piece wise linear function + Slope of fourth piecewise linear function 0 11 @@ -31515,14 +31612,14 @@ POSSIBILITY OF SUCH DAMAGE.\n A4 - Slope of 5th piece wise linear function + Slope of fifth piecewise linear function 0x530 read-write 0x000004BD A4 - Slope of 5th piece wise linear function + Slope of fifth piecewise linear function 0 11 @@ -31530,14 +31627,14 @@ POSSIBILITY OF SUCH DAMAGE.\n A5 - Slope of 6th piece wise linear function + Slope of sixth piecewise linear function 0x534 read-write 0x000005A3 A5 - Slope of 6th piece wise linear function + Slope of sixth piecewise linear function 0 11 @@ -31545,14 +31642,14 @@ POSSIBILITY OF SUCH DAMAGE.\n B0 - y-intercept of 1st piece wise linear function + y-intercept of first piecewise linear function 0x540 read-write 0x00003FEF B0 - y-intercept of 1st piece wise linear function + y-intercept of first piecewise linear function 0 13 @@ -31560,14 +31657,14 @@ POSSIBILITY OF SUCH DAMAGE.\n B1 - y-intercept of 2nd piece wise linear function + y-intercept of second piecewise linear function 0x544 read-write 0x00003FBE B1 - y-intercept of 2nd piece wise linear function + y-intercept of second piecewise linear function 0 13 @@ -31575,14 +31672,14 @@ POSSIBILITY OF SUCH DAMAGE.\n B2 - y-intercept of 3rd piece wise linear function + y-intercept of third piecewise linear function 0x548 read-write 0x00003FBE B2 - y-intercept of 3rd piece wise linear function + y-intercept of third piecewise linear function 0 13 @@ -31590,14 +31687,14 @@ POSSIBILITY OF SUCH DAMAGE.\n B3 - y-intercept of 4th piece wise linear function + y-intercept of fourth piecewise linear function 0x54C read-write 0x00000012 B3 - y-intercept of 4th piece wise linear function + y-intercept of fourth piecewise linear function 0 13 @@ -31605,14 +31702,14 @@ POSSIBILITY OF SUCH DAMAGE.\n B4 - y-intercept of 5th piece wise linear function + y-intercept of fifth piecewise linear function 0x550 read-write 0x00000124 B4 - y-intercept of 5th piece wise linear function + y-intercept of fifth piecewise linear function 0 13 @@ -31620,14 +31717,14 @@ POSSIBILITY OF SUCH DAMAGE.\n B5 - y-intercept of 6th piece wise linear function + y-intercept of sixth piecewise linear function 0x554 read-write 0x0000027C B5 - y-intercept of 6th piece wise linear function + y-intercept of sixth piecewise linear function 0 13 @@ -31635,14 +31732,14 @@ POSSIBILITY OF SUCH DAMAGE.\n T0 - End point of 1st piece wise linear function + End point of first piecewise linear function 0x560 read-write 0x000000E2 T0 - End point of 1st piece wise linear function + End point of first piecewise linear function 0 7 @@ -31650,14 +31747,14 @@ POSSIBILITY OF SUCH DAMAGE.\n T1 - End point of 2nd piece wise linear function + End point of second piecewise linear function 0x564 read-write 0x00000000 T1 - End point of 2nd piece wise linear function + End point of second piecewise linear function 0 7 @@ -31665,14 +31762,14 @@ POSSIBILITY OF SUCH DAMAGE.\n T2 - End point of 3rd piece wise linear function + End point of third piecewise linear function 0x568 read-write 0x00000019 T2 - End point of 3rd piece wise linear function + End point of third piecewise linear function 0 7 @@ -31680,14 +31777,14 @@ POSSIBILITY OF SUCH DAMAGE.\n T3 - End point of 4th piece wise linear function + End point of fourth piecewise linear function 0x56C read-write 0x0000003C T3 - End point of 4th piece wise linear function + End point of fourth piecewise linear function 0 7 @@ -31695,14 +31792,14 @@ POSSIBILITY OF SUCH DAMAGE.\n T4 - End point of 5th piece wise linear function + End point of fifth piecewise linear function 0x570 read-write 0x00000050 T4 - End point of 5th piece wise linear function + End point of fifth piecewise linear function 0 7 @@ -32545,7 +32642,7 @@ POSSIBILITY OF SUCH DAMAGE.\n NIRK - Number of Identity root keys available in the IRK data structure + Number of Identity Root Keys available in the IRK data structure 0 4 @@ -32614,13 +32711,13 @@ POSSIBILITY OF SUCH DAMAGE.\n TASKS_KSGEN - Start generation of key-stream. This operation will stop by itself when completed. + Start generation of keystream. This operation will stop by itself when completed. 0x000 write-only TASKS_KSGEN - Start generation of key-stream. This operation will stop by itself when completed. + Start generation of keystream. This operation will stop by itself when completed. 0 0 @@ -32698,13 +32795,13 @@ POSSIBILITY OF SUCH DAMAGE.\n EVENTS_ENDKSGEN - Key-stream generation complete + Keystream generation complete 0x100 read-write EVENTS_ENDKSGEN - Key-stream generation complete + Keystream generation complete 0 0 @@ -33091,12 +33188,12 @@ POSSIBILITY OF SUCH DAMAGE.\n Default - Default length. Effective length of LENGTH field in encrypted/decrypted packet is 5 bits. A key-stream for packet payloads up to 27 bytes will be generated. + Default length. Effective length of LENGTH field in encrypted/decrypted packet is 5 bits. A keystream for packet payloads up to 27 bytes will be generated. 0 Extended - Extended length. Effective length of LENGTH field in encrypted/decrypted packet is 8 bits. A key-stream for packet payloads up to MAXPACKETSIZE bytes will be generated. + Extended length. Effective length of LENGTH field in encrypted/decrypted packet is 8 bits. A keystream for packet payloads up to MAXPACKETSIZE bytes will be generated. 1 @@ -33153,7 +33250,7 @@ POSSIBILITY OF SUCH DAMAGE.\n SCRATCHPTR - Pointer to a scratch data area used for temporary storage during key-stream generation, + Pointer to a scratch data area used for temporary storage during keystream generation, MIC generation and encryption/decryption. 0 31 @@ -33162,14 +33259,14 @@ POSSIBILITY OF SUCH DAMAGE.\n MAXPACKETSIZE - Length of key-stream generated when MODE.LENGTH = Extended. + Length of keystream generated when MODE.LENGTH = Extended. 0x518 read-write 0x000000FB MAXPACKETSIZE - Length of key-stream generated when MODE.LENGTH = Extended. This value must be greater or equal to the subsequent packet payload to be encrypted/decrypted. + Length of keystream generated when MODE.LENGTH = Extended. This value must be greater or equal to the subsequent packet payload to be encrypted/decrypted. 0 7 @@ -34590,53 +34687,53 @@ POSSIBILITY OF SUCH DAMAGE.\n REPORTPER - Specifies the number of samples to be accumulated in the ACC register before the REPORTRDY and DBLRDY events can be generated + Specifies the number of samples to be accumulated in the ACC register before the REPORTRDY and DBLRDY events can be generated. 0 3 10Smpl - 10 samples / report + 10 samples/report 0 40Smpl - 40 samples / report + 40 samples/report 1 80Smpl - 80 samples / report + 80 samples/report 2 120Smpl - 120 samples / report + 120 samples/report 3 160Smpl - 160 samples / report + 160 samples/report 4 200Smpl - 200 samples / report + 200 samples/report 5 240Smpl - 240 samples / report + 240 samples/report 6 280Smpl - 280 samples / report + 280 samples/report 7 1Smpl - 1 sample / report + 1 sample/report 8 @@ -34652,7 +34749,7 @@ POSSIBILITY OF SUCH DAMAGE.\n ACC - Register accumulating all valid samples (not double transition) read from the SAMPLE register + Register accumulating all valid samples (not double transition) read from the SAMPLE register. 0 31 @@ -35604,7 +35701,7 @@ POSSIBILITY OF SUCH DAMAGE.\n ARef - VREF = AREF (VDD &gt;= VREF &gt;= AREFMIN) + VREF = AREF 5 @@ -35767,7 +35864,7 @@ POSSIBILITY OF SUCH DAMAGE.\n LPCOMP - Low Power Comparator + Low-power comparator 0x40013000 COMP @@ -36293,12 +36390,12 @@ POSSIBILITY OF SUCH DAMAGE.\n Below - Input voltage is below the reference threshold (VIN+ &lt; VIN-). + Input voltage is below the reference threshold (VIN+ &lt; VIN-) 0 Above - Input voltage is above the reference threshold (VIN+ &gt; VIN-). + Input voltage is above the reference threshold (VIN+ &gt; VIN-) 1 @@ -36571,7 +36668,7 @@ POSSIBILITY OF SUCH DAMAGE.\n EGU0 - Event Generator Unit 0 + Event generator unit 0 0x40014000 EGU @@ -37844,7 +37941,7 @@ POSSIBILITY OF SUCH DAMAGE.\n EGU1 - Event Generator Unit 1 + Event generator unit 1 0x40015000 SWI1_EGU1 @@ -37863,7 +37960,7 @@ POSSIBILITY OF SUCH DAMAGE.\n EGU2 - Event Generator Unit 2 + Event generator unit 2 0x40016000 SWI2_EGU2 @@ -37882,7 +37979,7 @@ POSSIBILITY OF SUCH DAMAGE.\n EGU3 - Event Generator Unit 3 + Event generator unit 3 0x40017000 SWI3_EGU3 @@ -37901,7 +37998,7 @@ POSSIBILITY OF SUCH DAMAGE.\n EGU4 - Event Generator Unit 4 + Event generator unit 4 0x40018000 SWI4_EGU4 @@ -37920,7 +38017,7 @@ POSSIBILITY OF SUCH DAMAGE.\n EGU5 - Event Generator Unit 5 + Event generator unit 5 0x40019000 SWI5_EGU5 @@ -39545,7 +39642,7 @@ POSSIBILITY OF SUCH DAMAGE.\n FREQ - PDM_CLK frequency + PDM_CLK frequency configuration 0 31 @@ -39598,19 +39695,19 @@ POSSIBILITY OF SUCH DAMAGE.\n Stereo - Sample and store one pair (Left + Right) of 16bit samples per RAM word R=[31:16]; L=[15:0] + Sample and store one pair (left + right) of 16-bit samples per RAM word R=[31:16]; L=[15:0] 0 Mono - Sample and store two successive Left samples (16 bit each) per RAM word L1=[31:16]; L0=[15:0] + Sample and store two successive left samples (16 bits each) per RAM word L1=[31:16]; L0=[15:0] 1 EDGE - Defines on which PDM_CLK edge Left (or mono) is sampled + Defines on which PDM_CLK edge left (or mono) is sampled 1 1 @@ -39643,17 +39740,17 @@ POSSIBILITY OF SUCH DAMAGE.\n MinGain - -20dB gain adjustment (minimum) + -20 dB gain adjustment (minimum) 0x00 DefaultGain - 0dB gain adjustment + 0 dB gain adjustment 0x28 MaxGain - +20dB gain adjustment (maximum) + +20 dB gain adjustment (maximum) 0x50 @@ -39675,17 +39772,17 @@ POSSIBILITY OF SUCH DAMAGE.\n MinGain - -20dB gain adjustment (minimum) + -20 dB gain adjustment (minimum) 0x00 DefaultGain - 0dB gain adjustment + 0 dB gain adjustment 0x28 MaxGain - +20dB gain adjustment (maximum) + +20 dB gain adjustment (maximum) 0x50 @@ -39863,14 +39960,14 @@ POSSIBILITY OF SUCH DAMAGE.\n 0x800 ADDR - Description cluster: Configure the word-aligned start address of region n to protect + Description cluster: Start address of region to protect. The start address must be word-aligned. 0x000 read-writeonce 0x00000000 ADDR - Valid word-aligned start address of region n to protect. Address must point to a flash page boundary. + Start address of flash region n. The start address must point to a flash page boundary. 0 31 @@ -39885,7 +39982,7 @@ POSSIBILITY OF SUCH DAMAGE.\n SIZE - Size of flash region n in bytes. Must be a multiple of the flash page size, and the maximum region size is limited to 512 kB. + Size of flash region n in bytes. Must be a multiple of the flash page size. 0 31 @@ -39984,6 +40081,7 @@ POSSIBILITY OF SUCH DAMAGE.\n Ready flag 0x408 read-only + 0x00000001 READYNEXT @@ -40040,7 +40138,7 @@ POSSIBILITY OF SUCH DAMAGE.\n ERASEPAGE Register for erasing a page in code area 0x508 - read-write + write-only ERASEPAGE @@ -40052,14 +40150,14 @@ POSSIBILITY OF SUCH DAMAGE.\n ERASEPCR1 - Deprecated register - Register for erasing a page in code area. Equivalent to ERASEPAGE. + Deprecated register - Register for erasing a page in code area, equivalent to ERASEPAGE 0x508 - read-write + write-only ERASEPAGE ERASEPCR1 - Register for erasing a page in code area. Equivalent to ERASEPAGE. + Register for erasing a page in code area, equivalent to ERASEPAGE 0 31 @@ -40069,11 +40167,11 @@ POSSIBILITY OF SUCH DAMAGE.\n ERASEALL Register for erasing all non-volatile user memory 0x50C - read-write + write-only ERASEALL - Erase all non-volatile memory including UICR registers. Note that the erase must be enabled using CONFIG.WEN before the non-volatile memory can be erased. + Erase all non-volatile memory including UICR registers. The erase must be enabled using CONFIG.WEN before the non-volatile memory can be erased. 0 0 @@ -40093,13 +40191,13 @@ POSSIBILITY OF SUCH DAMAGE.\n ERASEPCR0 - Deprecated register - Register for erasing a page in code area. Equivalent to ERASEPAGE. + Deprecated register - Register for erasing a page in code area, equivalent to ERASEPAGE 0x510 - read-write + write-only ERASEPCR0 - Register for starting erase of a page in code area. Equivalent to ERASEPAGE. + Register for starting erase of a page in code area, equivalent to ERASEPAGE 0 31 @@ -40109,11 +40207,11 @@ POSSIBILITY OF SUCH DAMAGE.\n ERASEUICR Register for erasing user information configuration registers 0x514 - read-write + write-only ERASEUICR - Register starting erase of all user information configuration registers. Note that the erase must be enabled using CONFIG.WEN before the UICR can be erased. + Register starting erase of all user information configuration registers. The erase must be enabled using CONFIG.WEN before the UICR can be erased. 0 0 @@ -40135,7 +40233,7 @@ POSSIBILITY OF SUCH DAMAGE.\n ERASEPAGEPARTIAL Register for partial erase of a page in code area 0x518 - read-write + write-only ERASEPAGEPARTIAL @@ -40162,7 +40260,7 @@ POSSIBILITY OF SUCH DAMAGE.\n ICACHECNF - I-code cache configuration register. + I-code cache configuration register 0x540 read-write 0x00000000 @@ -40207,13 +40305,13 @@ POSSIBILITY OF SUCH DAMAGE.\n IHIT - I-code cache hit counter. + I-code cache hit counter 0x548 read-write HITS - Number of cache hits + Number of cache hits. Register is writable, but only to '0'. 0 31 @@ -40221,13 +40319,13 @@ POSSIBILITY OF SUCH DAMAGE.\n IMISS - I-code cache miss counter. + I-code cache miss counter 0x54C read-write MISSES - Number of cache misses + Number of cache misses. Register is writable, but only to '0'. 0 31 @@ -40891,7 +40989,7 @@ POSSIBILITY OF SUCH DAMAGE.\n CH0 - Channel 0 enable set register. Writing '0' has no effect + Channel 0 enable set register. Writing '0' has no effect. 0 0 @@ -40918,7 +41016,7 @@ POSSIBILITY OF SUCH DAMAGE.\n CH1 - Channel 1 enable set register. Writing '0' has no effect + Channel 1 enable set register. Writing '0' has no effect. 1 1 @@ -40945,7 +41043,7 @@ POSSIBILITY OF SUCH DAMAGE.\n CH2 - Channel 2 enable set register. Writing '0' has no effect + Channel 2 enable set register. Writing '0' has no effect. 2 2 @@ -40972,7 +41070,7 @@ POSSIBILITY OF SUCH DAMAGE.\n CH3 - Channel 3 enable set register. Writing '0' has no effect + Channel 3 enable set register. Writing '0' has no effect. 3 3 @@ -40999,7 +41097,7 @@ POSSIBILITY OF SUCH DAMAGE.\n CH4 - Channel 4 enable set register. Writing '0' has no effect + Channel 4 enable set register. Writing '0' has no effect. 4 4 @@ -41026,7 +41124,7 @@ POSSIBILITY OF SUCH DAMAGE.\n CH5 - Channel 5 enable set register. Writing '0' has no effect + Channel 5 enable set register. Writing '0' has no effect. 5 5 @@ -41053,7 +41151,7 @@ POSSIBILITY OF SUCH DAMAGE.\n CH6 - Channel 6 enable set register. Writing '0' has no effect + Channel 6 enable set register. Writing '0' has no effect. 6 6 @@ -41080,7 +41178,7 @@ POSSIBILITY OF SUCH DAMAGE.\n CH7 - Channel 7 enable set register. Writing '0' has no effect + Channel 7 enable set register. Writing '0' has no effect. 7 7 @@ -41107,7 +41205,7 @@ POSSIBILITY OF SUCH DAMAGE.\n CH8 - Channel 8 enable set register. Writing '0' has no effect + Channel 8 enable set register. Writing '0' has no effect. 8 8 @@ -41134,7 +41232,7 @@ POSSIBILITY OF SUCH DAMAGE.\n CH9 - Channel 9 enable set register. Writing '0' has no effect + Channel 9 enable set register. Writing '0' has no effect. 9 9 @@ -41161,7 +41259,7 @@ POSSIBILITY OF SUCH DAMAGE.\n CH10 - Channel 10 enable set register. Writing '0' has no effect + Channel 10 enable set register. Writing '0' has no effect. 10 10 @@ -41188,7 +41286,7 @@ POSSIBILITY OF SUCH DAMAGE.\n CH11 - Channel 11 enable set register. Writing '0' has no effect + Channel 11 enable set register. Writing '0' has no effect. 11 11 @@ -41215,7 +41313,7 @@ POSSIBILITY OF SUCH DAMAGE.\n CH12 - Channel 12 enable set register. Writing '0' has no effect + Channel 12 enable set register. Writing '0' has no effect. 12 12 @@ -41242,7 +41340,7 @@ POSSIBILITY OF SUCH DAMAGE.\n CH13 - Channel 13 enable set register. Writing '0' has no effect + Channel 13 enable set register. Writing '0' has no effect. 13 13 @@ -41269,7 +41367,7 @@ POSSIBILITY OF SUCH DAMAGE.\n CH14 - Channel 14 enable set register. Writing '0' has no effect + Channel 14 enable set register. Writing '0' has no effect. 14 14 @@ -41296,7 +41394,7 @@ POSSIBILITY OF SUCH DAMAGE.\n CH15 - Channel 15 enable set register. Writing '0' has no effect + Channel 15 enable set register. Writing '0' has no effect. 15 15 @@ -41323,7 +41421,7 @@ POSSIBILITY OF SUCH DAMAGE.\n CH16 - Channel 16 enable set register. Writing '0' has no effect + Channel 16 enable set register. Writing '0' has no effect. 16 16 @@ -41350,7 +41448,7 @@ POSSIBILITY OF SUCH DAMAGE.\n CH17 - Channel 17 enable set register. Writing '0' has no effect + Channel 17 enable set register. Writing '0' has no effect. 17 17 @@ -41377,7 +41475,7 @@ POSSIBILITY OF SUCH DAMAGE.\n CH18 - Channel 18 enable set register. Writing '0' has no effect + Channel 18 enable set register. Writing '0' has no effect. 18 18 @@ -41404,7 +41502,7 @@ POSSIBILITY OF SUCH DAMAGE.\n CH19 - Channel 19 enable set register. Writing '0' has no effect + Channel 19 enable set register. Writing '0' has no effect. 19 19 @@ -41431,7 +41529,7 @@ POSSIBILITY OF SUCH DAMAGE.\n CH20 - Channel 20 enable set register. Writing '0' has no effect + Channel 20 enable set register. Writing '0' has no effect. 20 20 @@ -41458,7 +41556,7 @@ POSSIBILITY OF SUCH DAMAGE.\n CH21 - Channel 21 enable set register. Writing '0' has no effect + Channel 21 enable set register. Writing '0' has no effect. 21 21 @@ -41485,7 +41583,7 @@ POSSIBILITY OF SUCH DAMAGE.\n CH22 - Channel 22 enable set register. Writing '0' has no effect + Channel 22 enable set register. Writing '0' has no effect. 22 22 @@ -41512,7 +41610,7 @@ POSSIBILITY OF SUCH DAMAGE.\n CH23 - Channel 23 enable set register. Writing '0' has no effect + Channel 23 enable set register. Writing '0' has no effect. 23 23 @@ -41539,7 +41637,7 @@ POSSIBILITY OF SUCH DAMAGE.\n CH24 - Channel 24 enable set register. Writing '0' has no effect + Channel 24 enable set register. Writing '0' has no effect. 24 24 @@ -41566,7 +41664,7 @@ POSSIBILITY OF SUCH DAMAGE.\n CH25 - Channel 25 enable set register. Writing '0' has no effect + Channel 25 enable set register. Writing '0' has no effect. 25 25 @@ -41593,7 +41691,7 @@ POSSIBILITY OF SUCH DAMAGE.\n CH26 - Channel 26 enable set register. Writing '0' has no effect + Channel 26 enable set register. Writing '0' has no effect. 26 26 @@ -41620,7 +41718,7 @@ POSSIBILITY OF SUCH DAMAGE.\n CH27 - Channel 27 enable set register. Writing '0' has no effect + Channel 27 enable set register. Writing '0' has no effect. 27 27 @@ -41647,7 +41745,7 @@ POSSIBILITY OF SUCH DAMAGE.\n CH28 - Channel 28 enable set register. Writing '0' has no effect + Channel 28 enable set register. Writing '0' has no effect. 28 28 @@ -41674,7 +41772,7 @@ POSSIBILITY OF SUCH DAMAGE.\n CH29 - Channel 29 enable set register. Writing '0' has no effect + Channel 29 enable set register. Writing '0' has no effect. 29 29 @@ -41701,7 +41799,7 @@ POSSIBILITY OF SUCH DAMAGE.\n CH30 - Channel 30 enable set register. Writing '0' has no effect + Channel 30 enable set register. Writing '0' has no effect. 30 30 @@ -41728,7 +41826,7 @@ POSSIBILITY OF SUCH DAMAGE.\n CH31 - Channel 31 enable set register. Writing '0' has no effect + Channel 31 enable set register. Writing '0' has no effect. 31 31 @@ -41764,7 +41862,7 @@ POSSIBILITY OF SUCH DAMAGE.\n CH0 - Channel 0 enable clear register. Writing '0' has no effect + Channel 0 enable clear register. Writing '0' has no effect. 0 0 @@ -41791,7 +41889,7 @@ POSSIBILITY OF SUCH DAMAGE.\n CH1 - Channel 1 enable clear register. Writing '0' has no effect + Channel 1 enable clear register. Writing '0' has no effect. 1 1 @@ -41818,7 +41916,7 @@ POSSIBILITY OF SUCH DAMAGE.\n CH2 - Channel 2 enable clear register. Writing '0' has no effect + Channel 2 enable clear register. Writing '0' has no effect. 2 2 @@ -41845,7 +41943,7 @@ POSSIBILITY OF SUCH DAMAGE.\n CH3 - Channel 3 enable clear register. Writing '0' has no effect + Channel 3 enable clear register. Writing '0' has no effect. 3 3 @@ -41872,7 +41970,7 @@ POSSIBILITY OF SUCH DAMAGE.\n CH4 - Channel 4 enable clear register. Writing '0' has no effect + Channel 4 enable clear register. Writing '0' has no effect. 4 4 @@ -41899,7 +41997,7 @@ POSSIBILITY OF SUCH DAMAGE.\n CH5 - Channel 5 enable clear register. Writing '0' has no effect + Channel 5 enable clear register. Writing '0' has no effect. 5 5 @@ -41926,7 +42024,7 @@ POSSIBILITY OF SUCH DAMAGE.\n CH6 - Channel 6 enable clear register. Writing '0' has no effect + Channel 6 enable clear register. Writing '0' has no effect. 6 6 @@ -41953,7 +42051,7 @@ POSSIBILITY OF SUCH DAMAGE.\n CH7 - Channel 7 enable clear register. Writing '0' has no effect + Channel 7 enable clear register. Writing '0' has no effect. 7 7 @@ -41980,7 +42078,7 @@ POSSIBILITY OF SUCH DAMAGE.\n CH8 - Channel 8 enable clear register. Writing '0' has no effect + Channel 8 enable clear register. Writing '0' has no effect. 8 8 @@ -42007,7 +42105,7 @@ POSSIBILITY OF SUCH DAMAGE.\n CH9 - Channel 9 enable clear register. Writing '0' has no effect + Channel 9 enable clear register. Writing '0' has no effect. 9 9 @@ -42034,7 +42132,7 @@ POSSIBILITY OF SUCH DAMAGE.\n CH10 - Channel 10 enable clear register. Writing '0' has no effect + Channel 10 enable clear register. Writing '0' has no effect. 10 10 @@ -42061,7 +42159,7 @@ POSSIBILITY OF SUCH DAMAGE.\n CH11 - Channel 11 enable clear register. Writing '0' has no effect + Channel 11 enable clear register. Writing '0' has no effect. 11 11 @@ -42088,7 +42186,7 @@ POSSIBILITY OF SUCH DAMAGE.\n CH12 - Channel 12 enable clear register. Writing '0' has no effect + Channel 12 enable clear register. Writing '0' has no effect. 12 12 @@ -42115,7 +42213,7 @@ POSSIBILITY OF SUCH DAMAGE.\n CH13 - Channel 13 enable clear register. Writing '0' has no effect + Channel 13 enable clear register. Writing '0' has no effect. 13 13 @@ -42142,7 +42240,7 @@ POSSIBILITY OF SUCH DAMAGE.\n CH14 - Channel 14 enable clear register. Writing '0' has no effect + Channel 14 enable clear register. Writing '0' has no effect. 14 14 @@ -42169,7 +42267,7 @@ POSSIBILITY OF SUCH DAMAGE.\n CH15 - Channel 15 enable clear register. Writing '0' has no effect + Channel 15 enable clear register. Writing '0' has no effect. 15 15 @@ -42196,7 +42294,7 @@ POSSIBILITY OF SUCH DAMAGE.\n CH16 - Channel 16 enable clear register. Writing '0' has no effect + Channel 16 enable clear register. Writing '0' has no effect. 16 16 @@ -42223,7 +42321,7 @@ POSSIBILITY OF SUCH DAMAGE.\n CH17 - Channel 17 enable clear register. Writing '0' has no effect + Channel 17 enable clear register. Writing '0' has no effect. 17 17 @@ -42250,7 +42348,7 @@ POSSIBILITY OF SUCH DAMAGE.\n CH18 - Channel 18 enable clear register. Writing '0' has no effect + Channel 18 enable clear register. Writing '0' has no effect. 18 18 @@ -42277,7 +42375,7 @@ POSSIBILITY OF SUCH DAMAGE.\n CH19 - Channel 19 enable clear register. Writing '0' has no effect + Channel 19 enable clear register. Writing '0' has no effect. 19 19 @@ -42304,7 +42402,7 @@ POSSIBILITY OF SUCH DAMAGE.\n CH20 - Channel 20 enable clear register. Writing '0' has no effect + Channel 20 enable clear register. Writing '0' has no effect. 20 20 @@ -42331,7 +42429,7 @@ POSSIBILITY OF SUCH DAMAGE.\n CH21 - Channel 21 enable clear register. Writing '0' has no effect + Channel 21 enable clear register. Writing '0' has no effect. 21 21 @@ -42358,7 +42456,7 @@ POSSIBILITY OF SUCH DAMAGE.\n CH22 - Channel 22 enable clear register. Writing '0' has no effect + Channel 22 enable clear register. Writing '0' has no effect. 22 22 @@ -42385,7 +42483,7 @@ POSSIBILITY OF SUCH DAMAGE.\n CH23 - Channel 23 enable clear register. Writing '0' has no effect + Channel 23 enable clear register. Writing '0' has no effect. 23 23 @@ -42412,7 +42510,7 @@ POSSIBILITY OF SUCH DAMAGE.\n CH24 - Channel 24 enable clear register. Writing '0' has no effect + Channel 24 enable clear register. Writing '0' has no effect. 24 24 @@ -42439,7 +42537,7 @@ POSSIBILITY OF SUCH DAMAGE.\n CH25 - Channel 25 enable clear register. Writing '0' has no effect + Channel 25 enable clear register. Writing '0' has no effect. 25 25 @@ -42466,7 +42564,7 @@ POSSIBILITY OF SUCH DAMAGE.\n CH26 - Channel 26 enable clear register. Writing '0' has no effect + Channel 26 enable clear register. Writing '0' has no effect. 26 26 @@ -42493,7 +42591,7 @@ POSSIBILITY OF SUCH DAMAGE.\n CH27 - Channel 27 enable clear register. Writing '0' has no effect + Channel 27 enable clear register. Writing '0' has no effect. 27 27 @@ -42520,7 +42618,7 @@ POSSIBILITY OF SUCH DAMAGE.\n CH28 - Channel 28 enable clear register. Writing '0' has no effect + Channel 28 enable clear register. Writing '0' has no effect. 28 28 @@ -42547,7 +42645,7 @@ POSSIBILITY OF SUCH DAMAGE.\n CH29 - Channel 29 enable clear register. Writing '0' has no effect + Channel 29 enable clear register. Writing '0' has no effect. 29 29 @@ -42574,7 +42672,7 @@ POSSIBILITY OF SUCH DAMAGE.\n CH30 - Channel 30 enable clear register. Writing '0' has no effect + Channel 30 enable clear register. Writing '0' has no effect. 30 30 @@ -42601,7 +42699,7 @@ POSSIBILITY OF SUCH DAMAGE.\n CH31 - Channel 31 enable clear register. Writing '0' has no effect + Channel 31 enable clear register. Writing '0' has no effect. 31 31 @@ -42638,7 +42736,7 @@ POSSIBILITY OF SUCH DAMAGE.\n 0x510 EEP - Description cluster: Channel n event end-point + Description cluster: Channel n event endpoint 0x000 read-write @@ -42652,7 +42750,7 @@ POSSIBILITY OF SUCH DAMAGE.\n TEP - Description cluster: Channel n task end-point + Description cluster: Channel n task endpoint 0x004 read-write @@ -43261,7 +43359,7 @@ POSSIBILITY OF SUCH DAMAGE.\n 0x910 TEP - Description cluster: Channel n task end-point + Description cluster: Channel n task endpoint 0x000 read-write @@ -49319,13 +49417,13 @@ POSSIBILITY OF SUCH DAMAGE.\n 0x8 0x4 EVENTS_ENDEPIN[%s] - Description collection: The whole EPIN[n] buffer has been consumed. The RAM buffer can be accessed safely by software. + Description collection: The whole EPIN[n] buffer has been consumed. The buffer can be accessed safely by software. 0x108 read-write EVENTS_ENDEPIN - The whole EPIN[n] buffer has been consumed. The RAM buffer can be accessed safely by software. + The whole EPIN[n] buffer has been consumed. The buffer can be accessed safely by software. 0 0 @@ -49371,13 +49469,13 @@ POSSIBILITY OF SUCH DAMAGE.\n EVENTS_ENDISOIN - The whole ISOIN buffer has been consumed. The RAM buffer can be accessed safely by software. + The whole ISOIN buffer has been consumed. The buffer can be accessed safely by software. 0x12C read-write EVENTS_ENDISOIN - The whole ISOIN buffer has been consumed. The RAM buffer can be accessed safely by software. + The whole ISOIN buffer has been consumed. The buffer can be accessed safely by software. 0 0 @@ -49399,13 +49497,13 @@ POSSIBILITY OF SUCH DAMAGE.\n 0x8 0x4 EVENTS_ENDEPOUT[%s] - Description collection: The whole EPOUT[n] buffer has been consumed. The RAM buffer can be accessed safely by software. + Description collection: The whole EPOUT[n] buffer has been consumed. The buffer can be accessed safely by software. 0x130 read-write EVENTS_ENDEPOUT - The whole EPOUT[n] buffer has been consumed. The RAM buffer can be accessed safely by software. + The whole EPOUT[n] buffer has been consumed. The buffer can be accessed safely by software. 0 0 @@ -49425,13 +49523,13 @@ POSSIBILITY OF SUCH DAMAGE.\n EVENTS_ENDISOOUT - The whole ISOOUT buffer has been consumed. The RAM buffer can be accessed safely by software. + The whole ISOOUT buffer has been consumed. The buffer can be accessed safely by software. 0x150 read-write EVENTS_ENDISOOUT - The whole ISOOUT buffer has been consumed. The RAM buffer can be accessed safely by software. + The whole ISOOUT buffer has been consumed. The buffer can be accessed safely by software. 0 0 @@ -53088,7 +53186,7 @@ POSSIBILITY OF SUCH DAMAGE.\n OneDir - Full buffer dedicated to either iso IN or OUT + Full buffer dedicated to either ISO IN or OUT 0x0000 @@ -53183,7 +53281,7 @@ POSSIBILITY OF SUCH DAMAGE.\n PTR - Data pointer. Accepts any address in Data RAM. + Data pointer 0 31 @@ -53232,7 +53330,7 @@ POSSIBILITY OF SUCH DAMAGE.\n PTR - Data pointer. Accepts any address in Data RAM. + Data pointer 0 31 @@ -53283,7 +53381,7 @@ POSSIBILITY OF SUCH DAMAGE.\n PTR - Data pointer. Accepts any address in Data RAM. + Data pointer 0 31 @@ -53332,7 +53430,7 @@ POSSIBILITY OF SUCH DAMAGE.\n PTR - Data pointer. Accepts any address in Data RAM. + Data pointer 0 31 @@ -54668,14 +54766,14 @@ POSSIBILITY OF SUCH DAMAGE.\n HOST_IOT_KPRTL_LOCK - This write-once register is the K_PRTL lock register. When this register is set, K_PRTL can not be used and a zeroed key will be used instead. The value of this register is saved in the CRYPTOCELL AO power domain. + This write-once register is the K_PRTL lock register. When this register is set, K_PRTL cannot be used and a zeroed key will be used instead. The value of this register is saved in the CRYPTOCELL AO power domain. 0x1A4C read-write 0x00000000 HOST_IOT_KPRTL_LOCK - This register is the K_PRTL lock register. When this register is set, K_PRTL can not be used and a zeroed key will be used instead. The value of this register is saved in the CRYPTOCELL AO power domain. + This register is the K_PRTL lock register. When this register is set, K_PRTL cannot be used and a zeroed key will be used instead. The value of this register is saved in the CRYPTOCELL AO power domain. 0 0 @@ -54702,7 +54800,7 @@ POSSIBILITY OF SUCH DAMAGE.\n HOST_IOT_KDR0 - Write: K_DR bits 31:0 Read: 0x00000000 when 128-bit K_DR key value is not yet retained in the CRYPTOCELL AO power domain Read: 0x00000001 when 128-bit K_DR key value is successfully retained in the CRYPTOCELL AO power domain + Write: K_DR bits 31:0. Read: 0x00000000 when 128-bit K_DR key value is not yet retained in the CRYPTOCELL AO power domain. Read: 0x00000001 when 128-bit K_DR key value is successfully retained in the CRYPTOCELL AO power domain. 0 31 @@ -54780,18 +54878,18 @@ POSSIBILITY OF SUCH DAMAGE.\n LCS_IS_VALID - This field is read-only and indicates if CRYPTOCELL LCS has been successfully configured since last reset + Read-only field. Indicates if CRYPTOCELL LCS has been successfully configured since last reset. 8 8 Invalid - A valid LCS is not yet retained in the CRYPTOCELL AO power domain + Valid LCS not yet retained in the CRYPTOCELL AO power domain 0 Valid - A valid LCS is successfully retained in the CRYPTOCELL AO power domain + Valid LCS successfully retained in the CRYPTOCELL AO power domain 1 @@ -54837,7 +54935,7 @@ POSSIBILITY OF SUCH DAMAGE.\n Enabled - CRYPTOCELL subsystem enabled + CRYPTOCELL subsystem enabled. 1 diff --git a/mdk/nrf52840_bitfields.h b/mdk/nrf52840_bitfields.h index e91dd4dd1f..2e8b24ac8c 100644 --- a/mdk/nrf52840_bitfields.h +++ b/mdk/nrf52840_bitfields.h @@ -1,6 +1,8 @@ /* -Copyright (c) 2010 - 2020, Nordic Semiconductor ASA All rights reserved. +Copyright (c) 2010 - 2021, Nordic Semiconductor ASA All rights reserved. + +SPDX-License-Identifier: BSD-3-Clause Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: @@ -148,7 +150,7 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: AAR_NIRK */ /* Description: Number of IRKs */ -/* Bits 4..0 : Number of Identity root keys available in the IRK data structure */ +/* Bits 4..0 : Number of Identity Root Keys available in the IRK data structure */ #define AAR_NIRK_NIRK_Pos (0UL) /*!< Position of NIRK field. */ #define AAR_NIRK_NIRK_Msk (0x1FUL << AAR_NIRK_NIRK_Pos) /*!< Bit mask of NIRK field. */ @@ -178,16 +180,16 @@ POSSIBILITY OF SUCH DAMAGE. /* Description: Access control lists */ /* Register: ACL_ACL_ADDR */ -/* Description: Description cluster: Configure the word-aligned start address of region n to protect */ +/* Description: Description cluster: Start address of region to protect. The start address must be word-aligned. */ -/* Bits 31..0 : Valid word-aligned start address of region n to protect. Address must point to a flash page boundary. */ +/* Bits 31..0 : Start address of flash region n. The start address must point to a flash page boundary. */ #define ACL_ACL_ADDR_ADDR_Pos (0UL) /*!< Position of ADDR field. */ #define ACL_ACL_ADDR_ADDR_Msk (0xFFFFFFFFUL << ACL_ACL_ADDR_ADDR_Pos) /*!< Bit mask of ADDR field. */ /* Register: ACL_ACL_SIZE */ /* Description: Description cluster: Size of region to protect counting from address ACL[n].ADDR. Write '0' as no effect. */ -/* Bits 31..0 : Size of flash region n in bytes. Must be a multiple of the flash page size, and the maximum region size is limited to 512 kB. */ +/* Bits 31..0 : Size of flash region n in bytes. Must be a multiple of the flash page size. */ #define ACL_ACL_SIZE_SIZE_Pos (0UL) /*!< Position of SIZE field. */ #define ACL_ACL_SIZE_SIZE_Msk (0xFFFFFFFFUL << ACL_ACL_SIZE_SIZE_Pos) /*!< Bit mask of SIZE field. */ @@ -207,13 +209,33 @@ POSSIBILITY OF SUCH DAMAGE. #define ACL_ACL_PERM_WRITE_Disable (1UL) /*!< Block write and erase instructions to region n */ +/* Peripheral: APPROTECT */ +/* Description: Access Port Protection */ + +/* Register: APPROTECT_FORCEPROTECT */ +/* Description: Software force enable APPROTECT mechanism until next reset. */ + +/* Bits 7..0 : Write 0x0 to force enable APPROTECT mechanism */ +#define APPROTECT_FORCEPROTECT_FORCEPROTECT_Pos (0UL) /*!< Position of FORCEPROTECT field. */ +#define APPROTECT_FORCEPROTECT_FORCEPROTECT_Msk (0xFFUL << APPROTECT_FORCEPROTECT_FORCEPROTECT_Pos) /*!< Bit mask of FORCEPROTECT field. */ +#define APPROTECT_FORCEPROTECT_FORCEPROTECT_Force (0x0UL) /*!< Software force enable APPROTECT mechanism */ + +/* Register: APPROTECT_DISABLE */ +/* Description: Software disable APPROTECT mechanism */ + +/* Bits 7..0 : Software disable APPROTECT mechanism */ +#define APPROTECT_DISABLE_DISABLE_Pos (0UL) /*!< Position of DISABLE field. */ +#define APPROTECT_DISABLE_DISABLE_Msk (0xFFUL << APPROTECT_DISABLE_DISABLE_Pos) /*!< Bit mask of DISABLE field. */ +#define APPROTECT_DISABLE_DISABLE_SwDisable (0x5AUL) /*!< Software disable APPROTECT mechanism */ + + /* Peripheral: CCM */ /* Description: AES CCM Mode Encryption */ /* Register: CCM_TASKS_KSGEN */ -/* Description: Start generation of key-stream. This operation will stop by itself when completed. */ +/* Description: Start generation of keystream. This operation will stop by itself when completed. */ -/* Bit 0 : Start generation of key-stream. This operation will stop by itself when completed. */ +/* Bit 0 : Start generation of keystream. This operation will stop by itself when completed. */ #define CCM_TASKS_KSGEN_TASKS_KSGEN_Pos (0UL) /*!< Position of TASKS_KSGEN field. */ #define CCM_TASKS_KSGEN_TASKS_KSGEN_Msk (0x1UL << CCM_TASKS_KSGEN_TASKS_KSGEN_Pos) /*!< Bit mask of TASKS_KSGEN field. */ #define CCM_TASKS_KSGEN_TASKS_KSGEN_Trigger (1UL) /*!< Trigger task */ @@ -243,9 +265,9 @@ POSSIBILITY OF SUCH DAMAGE. #define CCM_TASKS_RATEOVERRIDE_TASKS_RATEOVERRIDE_Trigger (1UL) /*!< Trigger task */ /* Register: CCM_EVENTS_ENDKSGEN */ -/* Description: Key-stream generation complete */ +/* Description: Keystream generation complete */ -/* Bit 0 : Key-stream generation complete */ +/* Bit 0 : Keystream generation complete */ #define CCM_EVENTS_ENDKSGEN_EVENTS_ENDKSGEN_Pos (0UL) /*!< Position of EVENTS_ENDKSGEN field. */ #define CCM_EVENTS_ENDKSGEN_EVENTS_ENDKSGEN_Msk (0x1UL << CCM_EVENTS_ENDKSGEN_EVENTS_ENDKSGEN_Pos) /*!< Bit mask of EVENTS_ENDKSGEN field. */ #define CCM_EVENTS_ENDKSGEN_EVENTS_ENDKSGEN_NotGenerated (0UL) /*!< Event not generated */ @@ -350,8 +372,8 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 24 : Packet length configuration */ #define CCM_MODE_LENGTH_Pos (24UL) /*!< Position of LENGTH field. */ #define CCM_MODE_LENGTH_Msk (0x1UL << CCM_MODE_LENGTH_Pos) /*!< Bit mask of LENGTH field. */ -#define CCM_MODE_LENGTH_Default (0UL) /*!< Default length. Effective length of LENGTH field in encrypted/decrypted packet is 5 bits. A key-stream for packet payloads up to 27 bytes will be generated. */ -#define CCM_MODE_LENGTH_Extended (1UL) /*!< Extended length. Effective length of LENGTH field in encrypted/decrypted packet is 8 bits. A key-stream for packet payloads up to MAXPACKETSIZE bytes will be generated. */ +#define CCM_MODE_LENGTH_Default (0UL) /*!< Default length. Effective length of LENGTH field in encrypted/decrypted packet is 5 bits. A keystream for packet payloads up to 27 bytes will be generated. */ +#define CCM_MODE_LENGTH_Extended (1UL) /*!< Extended length. Effective length of LENGTH field in encrypted/decrypted packet is 8 bits. A keystream for packet payloads up to MAXPACKETSIZE bytes will be generated. */ /* Bits 17..16 : Radio data rate that the CCM shall run synchronous with */ #define CCM_MODE_DATARATE_Pos (16UL) /*!< Position of DATARATE field. */ @@ -391,15 +413,15 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: CCM_SCRATCHPTR */ /* Description: Pointer to data area used for temporary storage */ -/* Bits 31..0 : Pointer to a scratch data area used for temporary storage during key-stream generation, +/* Bits 31..0 : Pointer to a scratch data area used for temporary storage during keystream generation, MIC generation and encryption/decryption. */ #define CCM_SCRATCHPTR_SCRATCHPTR_Pos (0UL) /*!< Position of SCRATCHPTR field. */ #define CCM_SCRATCHPTR_SCRATCHPTR_Msk (0xFFFFFFFFUL << CCM_SCRATCHPTR_SCRATCHPTR_Pos) /*!< Bit mask of SCRATCHPTR field. */ /* Register: CCM_MAXPACKETSIZE */ -/* Description: Length of key-stream generated when MODE.LENGTH = Extended. */ +/* Description: Length of keystream generated when MODE.LENGTH = Extended. */ -/* Bits 7..0 : Length of key-stream generated when MODE.LENGTH = Extended. This value must be greater or equal to the subsequent packet payload to be encrypted/decrypted. */ +/* Bits 7..0 : Length of keystream generated when MODE.LENGTH = Extended. This value must be greater or equal to the subsequent packet payload to be encrypted/decrypted. */ #define CCM_MAXPACKETSIZE_MAXPACKETSIZE_Pos (0UL) /*!< Position of MAXPACKETSIZE field. */ #define CCM_MAXPACKETSIZE_MAXPACKETSIZE_Msk (0xFFUL << CCM_MAXPACKETSIZE_MAXPACKETSIZE_Pos) /*!< Bit mask of MAXPACKETSIZE field. */ @@ -429,9 +451,9 @@ POSSIBILITY OF SUCH DAMAGE. #define CC_HOST_RGF_HOST_CRYPTOKEY_SEL_HOST_CRYPTOKEY_SEL_Session (2UL) /*!< Use provided session key */ /* Register: CC_HOST_RGF_HOST_IOT_KPRTL_LOCK */ -/* Description: This write-once register is the K_PRTL lock register. When this register is set, K_PRTL can not be used and a zeroed key will be used instead. The value of this register is saved in the CRYPTOCELL AO power domain. */ +/* Description: This write-once register is the K_PRTL lock register. When this register is set, K_PRTL cannot be used and a zeroed key will be used instead. The value of this register is saved in the CRYPTOCELL AO power domain. */ -/* Bit 0 : This register is the K_PRTL lock register. When this register is set, K_PRTL can not be used and a zeroed key will be used instead. The value of this register is saved in the CRYPTOCELL AO power domain. */ +/* Bit 0 : This register is the K_PRTL lock register. When this register is set, K_PRTL cannot be used and a zeroed key will be used instead. The value of this register is saved in the CRYPTOCELL AO power domain. */ #define CC_HOST_RGF_HOST_IOT_KPRTL_LOCK_HOST_IOT_KPRTL_LOCK_Pos (0UL) /*!< Position of HOST_IOT_KPRTL_LOCK field. */ #define CC_HOST_RGF_HOST_IOT_KPRTL_LOCK_HOST_IOT_KPRTL_LOCK_Msk (0x1UL << CC_HOST_RGF_HOST_IOT_KPRTL_LOCK_HOST_IOT_KPRTL_LOCK_Pos) /*!< Bit mask of HOST_IOT_KPRTL_LOCK field. */ #define CC_HOST_RGF_HOST_IOT_KPRTL_LOCK_HOST_IOT_KPRTL_LOCK_Disabled (0UL) /*!< K_PRTL can be selected for use from register HOST_CRYPTOKEY_SEL */ @@ -440,7 +462,7 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: CC_HOST_RGF_HOST_IOT_KDR0 */ /* Description: This register holds bits 31:0 of K_DR. The value of this register is saved in the CRYPTOCELL AO power domain. Reading from this address returns the K_DR valid status indicating if K_DR is successfully retained. */ -/* Bits 31..0 : Write: K_DR bits 31:0 Read: 0x00000000 when 128-bit K_DR key value is not yet retained in the CRYPTOCELL AO power domain Read: 0x00000001 when 128-bit K_DR key value is successfully retained in the CRYPTOCELL AO power domain */ +/* Bits 31..0 : Write: K_DR bits 31:0. Read: 0x00000000 when 128-bit K_DR key value is not yet retained in the CRYPTOCELL AO power domain. Read: 0x00000001 when 128-bit K_DR key value is successfully retained in the CRYPTOCELL AO power domain. */ #define CC_HOST_RGF_HOST_IOT_KDR0_HOST_IOT_KDR0_Pos (0UL) /*!< Position of HOST_IOT_KDR0 field. */ #define CC_HOST_RGF_HOST_IOT_KDR0_HOST_IOT_KDR0_Msk (0xFFFFFFFFUL << CC_HOST_RGF_HOST_IOT_KDR0_HOST_IOT_KDR0_Pos) /*!< Bit mask of HOST_IOT_KDR0 field. */ @@ -468,11 +490,11 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: CC_HOST_RGF_HOST_IOT_LCS */ /* Description: Controls lifecycle state (LCS) for CRYPTOCELL subsystem */ -/* Bit 8 : This field is read-only and indicates if CRYPTOCELL LCS has been successfully configured since last reset */ +/* Bit 8 : Read-only field. Indicates if CRYPTOCELL LCS has been successfully configured since last reset. */ #define CC_HOST_RGF_HOST_IOT_LCS_LCS_IS_VALID_Pos (8UL) /*!< Position of LCS_IS_VALID field. */ #define CC_HOST_RGF_HOST_IOT_LCS_LCS_IS_VALID_Msk (0x1UL << CC_HOST_RGF_HOST_IOT_LCS_LCS_IS_VALID_Pos) /*!< Bit mask of LCS_IS_VALID field. */ -#define CC_HOST_RGF_HOST_IOT_LCS_LCS_IS_VALID_Invalid (0UL) /*!< A valid LCS is not yet retained in the CRYPTOCELL AO power domain */ -#define CC_HOST_RGF_HOST_IOT_LCS_LCS_IS_VALID_Valid (1UL) /*!< A valid LCS is successfully retained in the CRYPTOCELL AO power domain */ +#define CC_HOST_RGF_HOST_IOT_LCS_LCS_IS_VALID_Invalid (0UL) /*!< Valid LCS not yet retained in the CRYPTOCELL AO power domain */ +#define CC_HOST_RGF_HOST_IOT_LCS_LCS_IS_VALID_Valid (1UL) /*!< Valid LCS successfully retained in the CRYPTOCELL AO power domain */ /* Bits 2..0 : Lifecycle state value. This field is write-once per reset. */ #define CC_HOST_RGF_HOST_IOT_LCS_LCS_Pos (0UL) /*!< Position of LCS field. */ @@ -1043,7 +1065,7 @@ POSSIBILITY OF SUCH DAMAGE. #define COMP_REFSEL_REFSEL_Int1V8 (1UL) /*!< VREF = internal 1.8 V reference (VDD >= VREF + 0.2 V) */ #define COMP_REFSEL_REFSEL_Int2V4 (2UL) /*!< VREF = internal 2.4 V reference (VDD >= VREF + 0.2 V) */ #define COMP_REFSEL_REFSEL_VDD (4UL) /*!< VREF = VDD */ -#define COMP_REFSEL_REFSEL_ARef (5UL) /*!< VREF = AREF (VDD >= VREF >= AREFMIN) */ +#define COMP_REFSEL_REFSEL_ARef (5UL) /*!< VREF = AREF */ /* Register: COMP_EXTREFSEL */ /* Description: External reference select */ @@ -1107,7 +1129,7 @@ POSSIBILITY OF SUCH DAMAGE. #define CRYPTOCELL_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ #define CRYPTOCELL_ENABLE_ENABLE_Msk (0x1UL << CRYPTOCELL_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ #define CRYPTOCELL_ENABLE_ENABLE_Disabled (0UL) /*!< CRYPTOCELL subsystem disabled */ -#define CRYPTOCELL_ENABLE_ENABLE_Enabled (1UL) /*!< CRYPTOCELL subsystem enabled */ +#define CRYPTOCELL_ENABLE_ENABLE_Enabled (1UL) /*!< CRYPTOCELL subsystem enabled. */ /* Peripheral: ECB */ @@ -1190,7 +1212,7 @@ POSSIBILITY OF SUCH DAMAGE. /* Peripheral: EGU */ -/* Description: Event Generator Unit 0 */ +/* Description: Event generator unit 0 */ /* Register: EGU_TASKS_TRIGGER */ /* Description: Description collection: Trigger n for triggering the corresponding TRIGGERED[n] event */ @@ -1599,6 +1621,7 @@ POSSIBILITY OF SUCH DAMAGE. /* Bits 31..0 : Part code */ #define FICR_INFO_PART_PART_Pos (0UL) /*!< Position of PART field. */ #define FICR_INFO_PART_PART_Msk (0xFFFFFFFFUL << FICR_INFO_PART_PART_Pos) /*!< Bit mask of PART field. */ +#define FICR_INFO_PART_PART_N52820 (0x52820UL) /*!< nRF52820 */ #define FICR_INFO_PART_PART_N52833 (0x52833UL) /*!< nRF52833 */ #define FICR_INFO_PART_PART_N52840 (0x52840UL) /*!< nRF52840 */ #define FICR_INFO_PART_PART_Unspecified (0xFFFFFFFFUL) /*!< Unspecified */ @@ -1613,7 +1636,12 @@ POSSIBILITY OF SUCH DAMAGE. #define FICR_INFO_VARIANT_VARIANT_AAAB (0x41414142UL) /*!< AAAB */ #define FICR_INFO_VARIANT_VARIANT_AABA (0x41414241UL) /*!< AABA */ #define FICR_INFO_VARIANT_VARIANT_AABB (0x41414242UL) /*!< AABB */ +#define FICR_INFO_VARIANT_VARIANT_AAC0 (0x41414330UL) /*!< AAC0 */ #define FICR_INFO_VARIANT_VARIANT_AACA (0x41414341UL) /*!< AACA */ +#define FICR_INFO_VARIANT_VARIANT_AAD0 (0x41414430UL) /*!< AAD0 */ +#define FICR_INFO_VARIANT_VARIANT_AAD1 (0x41414431UL) /*!< AAD1 */ +#define FICR_INFO_VARIANT_VARIANT_AADA (0x41414441UL) /*!< AADA */ +#define FICR_INFO_VARIANT_VARIANT_AAEA (0x41414541UL) /*!< AAEA */ #define FICR_INFO_VARIANT_VARIANT_BAAA (0x42414141UL) /*!< BAAA */ #define FICR_INFO_VARIANT_VARIANT_CAAA (0x43414141UL) /*!< CAAA */ #define FICR_INFO_VARIANT_VARIANT_Unspecified (0xFFFFFFFFUL) /*!< Unspecified */ @@ -1624,8 +1652,8 @@ POSSIBILITY OF SUCH DAMAGE. /* Bits 31..0 : Package option */ #define FICR_INFO_PACKAGE_PACKAGE_Pos (0UL) /*!< Position of PACKAGE field. */ #define FICR_INFO_PACKAGE_PACKAGE_Msk (0xFFFFFFFFUL << FICR_INFO_PACKAGE_PACKAGE_Pos) /*!< Bit mask of PACKAGE field. */ -#define FICR_INFO_PACKAGE_PACKAGE_QI (0x2004UL) /*!< QIxx - 73-pin aQFN */ -#define FICR_INFO_PACKAGE_PACKAGE_CK (0x2005UL) /*!< CKxx - WLCSP */ +#define FICR_INFO_PACKAGE_PACKAGE_QI (0x2004UL) /*!< QIxx - 7x7 73-pin aQFN */ +#define FICR_INFO_PACKAGE_PACKAGE_CK (0x2005UL) /*!< CKxx - 3.544 x 3.607 WLCSP */ #define FICR_INFO_PACKAGE_PACKAGE_Unspecified (0xFFFFFFFFUL) /*!< Unspecified */ /* Register: FICR_INFO_RAM */ @@ -2093,7 +2121,7 @@ POSSIBILITY OF SUCH DAMAGE. #define GPIOTE_INTENCLR_IN0_Clear (1UL) /*!< Disable */ /* Register: GPIOTE_CONFIG */ -/* Description: Description collection: Configuration for OUT[n], SET[n] and CLR[n] tasks and IN[n] event */ +/* Description: Description collection: Configuration for OUT[n], SET[n], and CLR[n] tasks and IN[n] event */ /* Bit 20 : When in task mode: Initial value of the output when the GPIOTE channel is configured. When in event mode: No effect. */ #define GPIOTE_CONFIG_OUTINIT_Pos (20UL) /*!< Position of OUTINIT field. */ @@ -2113,7 +2141,7 @@ POSSIBILITY OF SUCH DAMAGE. #define GPIOTE_CONFIG_PORT_Pos (13UL) /*!< Position of PORT field. */ #define GPIOTE_CONFIG_PORT_Msk (0x1UL << GPIOTE_CONFIG_PORT_Pos) /*!< Bit mask of PORT field. */ -/* Bits 12..8 : GPIO number associated with SET[n], CLR[n] and OUT[n] tasks and IN[n] event */ +/* Bits 12..8 : GPIO number associated with SET[n], CLR[n], and OUT[n] tasks and IN[n] event */ #define GPIOTE_CONFIG_PSEL_Pos (8UL) /*!< Position of PSEL field. */ #define GPIOTE_CONFIG_PSEL_Msk (0x1FUL << GPIOTE_CONFIG_PSEL_Pos) /*!< Bit mask of PSEL field. */ @@ -2471,7 +2499,7 @@ POSSIBILITY OF SUCH DAMAGE. /* Peripheral: LPCOMP */ -/* Description: Low Power Comparator */ +/* Description: Low-power comparator */ /* Register: LPCOMP_TASKS_START */ /* Description: Start comparator */ @@ -2634,8 +2662,8 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 0 : Result of last compare. Decision point SAMPLE task. */ #define LPCOMP_RESULT_RESULT_Pos (0UL) /*!< Position of RESULT field. */ #define LPCOMP_RESULT_RESULT_Msk (0x1UL << LPCOMP_RESULT_RESULT_Pos) /*!< Bit mask of RESULT field. */ -#define LPCOMP_RESULT_RESULT_Below (0UL) /*!< Input voltage is below the reference threshold (VIN+ < VIN-). */ -#define LPCOMP_RESULT_RESULT_Above (1UL) /*!< Input voltage is above the reference threshold (VIN+ > VIN-). */ +#define LPCOMP_RESULT_RESULT_Below (0UL) /*!< Input voltage is below the reference threshold (VIN+ < VIN-) */ +#define LPCOMP_RESULT_RESULT_Above (1UL) /*!< Input voltage is above the reference threshold (VIN+ > VIN-) */ /* Register: LPCOMP_ENABLE */ /* Description: Enable LPCOMP */ @@ -4863,7 +4891,7 @@ POSSIBILITY OF SUCH DAMAGE. #define NFCT_NFCID1_3RD_LAST_NFCID1_S_Msk (0xFFUL << NFCT_NFCID1_3RD_LAST_NFCID1_S_Pos) /*!< Bit mask of NFCID1_S field. */ /* Register: NFCT_AUTOCOLRESCONFIG */ -/* Description: Controls the auto collision resolution function. This setting must be done before the NFCT peripheral is enabled. */ +/* Description: Controls the auto collision resolution function. This setting must be done before the NFCT peripheral is activated. */ /* Bit 0 : Enables/disables auto collision resolution */ #define NFCT_AUTOCOLRESCONFIG_MODE_Pos (0UL) /*!< Position of MODE field. */ @@ -4966,32 +4994,32 @@ POSSIBILITY OF SUCH DAMAGE. #define NVMC_ERASEPAGE_ERASEPAGE_Msk (0xFFFFFFFFUL << NVMC_ERASEPAGE_ERASEPAGE_Pos) /*!< Bit mask of ERASEPAGE field. */ /* Register: NVMC_ERASEPCR1 */ -/* Description: Deprecated register - Register for erasing a page in code area. Equivalent to ERASEPAGE. */ +/* Description: Deprecated register - Register for erasing a page in code area, equivalent to ERASEPAGE */ -/* Bits 31..0 : Register for erasing a page in code area. Equivalent to ERASEPAGE. */ +/* Bits 31..0 : Register for erasing a page in code area, equivalent to ERASEPAGE */ #define NVMC_ERASEPCR1_ERASEPCR1_Pos (0UL) /*!< Position of ERASEPCR1 field. */ #define NVMC_ERASEPCR1_ERASEPCR1_Msk (0xFFFFFFFFUL << NVMC_ERASEPCR1_ERASEPCR1_Pos) /*!< Bit mask of ERASEPCR1 field. */ /* Register: NVMC_ERASEALL */ /* Description: Register for erasing all non-volatile user memory */ -/* Bit 0 : Erase all non-volatile memory including UICR registers. Note that the erase must be enabled using CONFIG.WEN before the non-volatile memory can be erased. */ +/* Bit 0 : Erase all non-volatile memory including UICR registers. The erase must be enabled using CONFIG.WEN before the non-volatile memory can be erased. */ #define NVMC_ERASEALL_ERASEALL_Pos (0UL) /*!< Position of ERASEALL field. */ #define NVMC_ERASEALL_ERASEALL_Msk (0x1UL << NVMC_ERASEALL_ERASEALL_Pos) /*!< Bit mask of ERASEALL field. */ #define NVMC_ERASEALL_ERASEALL_NoOperation (0UL) /*!< No operation */ #define NVMC_ERASEALL_ERASEALL_Erase (1UL) /*!< Start chip erase */ /* Register: NVMC_ERASEPCR0 */ -/* Description: Deprecated register - Register for erasing a page in code area. Equivalent to ERASEPAGE. */ +/* Description: Deprecated register - Register for erasing a page in code area, equivalent to ERASEPAGE */ -/* Bits 31..0 : Register for starting erase of a page in code area. Equivalent to ERASEPAGE. */ +/* Bits 31..0 : Register for starting erase of a page in code area, equivalent to ERASEPAGE */ #define NVMC_ERASEPCR0_ERASEPCR0_Pos (0UL) /*!< Position of ERASEPCR0 field. */ #define NVMC_ERASEPCR0_ERASEPCR0_Msk (0xFFFFFFFFUL << NVMC_ERASEPCR0_ERASEPCR0_Pos) /*!< Bit mask of ERASEPCR0 field. */ /* Register: NVMC_ERASEUICR */ /* Description: Register for erasing user information configuration registers */ -/* Bit 0 : Register starting erase of all user information configuration registers. Note that the erase must be enabled using CONFIG.WEN before the UICR can be erased. */ +/* Bit 0 : Register starting erase of all user information configuration registers. The erase must be enabled using CONFIG.WEN before the UICR can be erased. */ #define NVMC_ERASEUICR_ERASEUICR_Pos (0UL) /*!< Position of ERASEUICR field. */ #define NVMC_ERASEUICR_ERASEUICR_Msk (0x1UL << NVMC_ERASEUICR_ERASEUICR_Pos) /*!< Bit mask of ERASEUICR field. */ #define NVMC_ERASEUICR_ERASEUICR_NoOperation (0UL) /*!< No operation */ @@ -5012,7 +5040,7 @@ POSSIBILITY OF SUCH DAMAGE. #define NVMC_ERASEPAGEPARTIALCFG_DURATION_Msk (0x7FUL << NVMC_ERASEPAGEPARTIALCFG_DURATION_Pos) /*!< Bit mask of DURATION field. */ /* Register: NVMC_ICACHECNF */ -/* Description: I-code cache configuration register. */ +/* Description: I-code cache configuration register */ /* Bit 8 : Cache profiling enable */ #define NVMC_ICACHECNF_CACHEPROFEN_Pos (8UL) /*!< Position of CACHEPROFEN field. */ @@ -5027,16 +5055,16 @@ POSSIBILITY OF SUCH DAMAGE. #define NVMC_ICACHECNF_CACHEEN_Enabled (1UL) /*!< Enable cache */ /* Register: NVMC_IHIT */ -/* Description: I-code cache hit counter. */ +/* Description: I-code cache hit counter */ -/* Bits 31..0 : Number of cache hits */ +/* Bits 31..0 : Number of cache hits. Register is writable, but only to '0'. */ #define NVMC_IHIT_HITS_Pos (0UL) /*!< Position of HITS field. */ #define NVMC_IHIT_HITS_Msk (0xFFFFFFFFUL << NVMC_IHIT_HITS_Pos) /*!< Bit mask of HITS field. */ /* Register: NVMC_IMISS */ -/* Description: I-code cache miss counter. */ +/* Description: I-code cache miss counter */ -/* Bits 31..0 : Number of cache misses */ +/* Bits 31..0 : Number of cache misses. Register is writable, but only to '0'. */ #define NVMC_IMISS_MISSES_Pos (0UL) /*!< Position of MISSES field. */ #define NVMC_IMISS_MISSES_Msk (0xFFFFFFFFUL << NVMC_IMISS_MISSES_Pos) /*!< Bit mask of MISSES field. */ @@ -5247,224 +5275,224 @@ POSSIBILITY OF SUCH DAMAGE. #define GPIO_OUTSET_PIN31_Msk (0x1UL << GPIO_OUTSET_PIN31_Pos) /*!< Bit mask of PIN31 field. */ #define GPIO_OUTSET_PIN31_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTSET_PIN31_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTSET_PIN31_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ +#define GPIO_OUTSET_PIN31_Set (1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */ /* Bit 30 : Pin 30 */ #define GPIO_OUTSET_PIN30_Pos (30UL) /*!< Position of PIN30 field. */ #define GPIO_OUTSET_PIN30_Msk (0x1UL << GPIO_OUTSET_PIN30_Pos) /*!< Bit mask of PIN30 field. */ #define GPIO_OUTSET_PIN30_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTSET_PIN30_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTSET_PIN30_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ +#define GPIO_OUTSET_PIN30_Set (1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */ /* Bit 29 : Pin 29 */ #define GPIO_OUTSET_PIN29_Pos (29UL) /*!< Position of PIN29 field. */ #define GPIO_OUTSET_PIN29_Msk (0x1UL << GPIO_OUTSET_PIN29_Pos) /*!< Bit mask of PIN29 field. */ #define GPIO_OUTSET_PIN29_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTSET_PIN29_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTSET_PIN29_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ +#define GPIO_OUTSET_PIN29_Set (1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */ /* Bit 28 : Pin 28 */ #define GPIO_OUTSET_PIN28_Pos (28UL) /*!< Position of PIN28 field. */ #define GPIO_OUTSET_PIN28_Msk (0x1UL << GPIO_OUTSET_PIN28_Pos) /*!< Bit mask of PIN28 field. */ #define GPIO_OUTSET_PIN28_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTSET_PIN28_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTSET_PIN28_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ +#define GPIO_OUTSET_PIN28_Set (1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */ /* Bit 27 : Pin 27 */ #define GPIO_OUTSET_PIN27_Pos (27UL) /*!< Position of PIN27 field. */ #define GPIO_OUTSET_PIN27_Msk (0x1UL << GPIO_OUTSET_PIN27_Pos) /*!< Bit mask of PIN27 field. */ #define GPIO_OUTSET_PIN27_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTSET_PIN27_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTSET_PIN27_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ +#define GPIO_OUTSET_PIN27_Set (1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */ /* Bit 26 : Pin 26 */ #define GPIO_OUTSET_PIN26_Pos (26UL) /*!< Position of PIN26 field. */ #define GPIO_OUTSET_PIN26_Msk (0x1UL << GPIO_OUTSET_PIN26_Pos) /*!< Bit mask of PIN26 field. */ #define GPIO_OUTSET_PIN26_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTSET_PIN26_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTSET_PIN26_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ +#define GPIO_OUTSET_PIN26_Set (1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */ /* Bit 25 : Pin 25 */ #define GPIO_OUTSET_PIN25_Pos (25UL) /*!< Position of PIN25 field. */ #define GPIO_OUTSET_PIN25_Msk (0x1UL << GPIO_OUTSET_PIN25_Pos) /*!< Bit mask of PIN25 field. */ #define GPIO_OUTSET_PIN25_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTSET_PIN25_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTSET_PIN25_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ +#define GPIO_OUTSET_PIN25_Set (1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */ /* Bit 24 : Pin 24 */ #define GPIO_OUTSET_PIN24_Pos (24UL) /*!< Position of PIN24 field. */ #define GPIO_OUTSET_PIN24_Msk (0x1UL << GPIO_OUTSET_PIN24_Pos) /*!< Bit mask of PIN24 field. */ #define GPIO_OUTSET_PIN24_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTSET_PIN24_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTSET_PIN24_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ +#define GPIO_OUTSET_PIN24_Set (1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */ /* Bit 23 : Pin 23 */ #define GPIO_OUTSET_PIN23_Pos (23UL) /*!< Position of PIN23 field. */ #define GPIO_OUTSET_PIN23_Msk (0x1UL << GPIO_OUTSET_PIN23_Pos) /*!< Bit mask of PIN23 field. */ #define GPIO_OUTSET_PIN23_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTSET_PIN23_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTSET_PIN23_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ +#define GPIO_OUTSET_PIN23_Set (1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */ /* Bit 22 : Pin 22 */ #define GPIO_OUTSET_PIN22_Pos (22UL) /*!< Position of PIN22 field. */ #define GPIO_OUTSET_PIN22_Msk (0x1UL << GPIO_OUTSET_PIN22_Pos) /*!< Bit mask of PIN22 field. */ #define GPIO_OUTSET_PIN22_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTSET_PIN22_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTSET_PIN22_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ +#define GPIO_OUTSET_PIN22_Set (1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */ /* Bit 21 : Pin 21 */ #define GPIO_OUTSET_PIN21_Pos (21UL) /*!< Position of PIN21 field. */ #define GPIO_OUTSET_PIN21_Msk (0x1UL << GPIO_OUTSET_PIN21_Pos) /*!< Bit mask of PIN21 field. */ #define GPIO_OUTSET_PIN21_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTSET_PIN21_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTSET_PIN21_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ +#define GPIO_OUTSET_PIN21_Set (1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */ /* Bit 20 : Pin 20 */ #define GPIO_OUTSET_PIN20_Pos (20UL) /*!< Position of PIN20 field. */ #define GPIO_OUTSET_PIN20_Msk (0x1UL << GPIO_OUTSET_PIN20_Pos) /*!< Bit mask of PIN20 field. */ #define GPIO_OUTSET_PIN20_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTSET_PIN20_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTSET_PIN20_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ +#define GPIO_OUTSET_PIN20_Set (1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */ /* Bit 19 : Pin 19 */ #define GPIO_OUTSET_PIN19_Pos (19UL) /*!< Position of PIN19 field. */ #define GPIO_OUTSET_PIN19_Msk (0x1UL << GPIO_OUTSET_PIN19_Pos) /*!< Bit mask of PIN19 field. */ #define GPIO_OUTSET_PIN19_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTSET_PIN19_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTSET_PIN19_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ +#define GPIO_OUTSET_PIN19_Set (1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */ /* Bit 18 : Pin 18 */ #define GPIO_OUTSET_PIN18_Pos (18UL) /*!< Position of PIN18 field. */ #define GPIO_OUTSET_PIN18_Msk (0x1UL << GPIO_OUTSET_PIN18_Pos) /*!< Bit mask of PIN18 field. */ #define GPIO_OUTSET_PIN18_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTSET_PIN18_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTSET_PIN18_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ +#define GPIO_OUTSET_PIN18_Set (1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */ /* Bit 17 : Pin 17 */ #define GPIO_OUTSET_PIN17_Pos (17UL) /*!< Position of PIN17 field. */ #define GPIO_OUTSET_PIN17_Msk (0x1UL << GPIO_OUTSET_PIN17_Pos) /*!< Bit mask of PIN17 field. */ #define GPIO_OUTSET_PIN17_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTSET_PIN17_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTSET_PIN17_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ +#define GPIO_OUTSET_PIN17_Set (1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */ /* Bit 16 : Pin 16 */ #define GPIO_OUTSET_PIN16_Pos (16UL) /*!< Position of PIN16 field. */ #define GPIO_OUTSET_PIN16_Msk (0x1UL << GPIO_OUTSET_PIN16_Pos) /*!< Bit mask of PIN16 field. */ #define GPIO_OUTSET_PIN16_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTSET_PIN16_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTSET_PIN16_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ +#define GPIO_OUTSET_PIN16_Set (1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */ /* Bit 15 : Pin 15 */ #define GPIO_OUTSET_PIN15_Pos (15UL) /*!< Position of PIN15 field. */ #define GPIO_OUTSET_PIN15_Msk (0x1UL << GPIO_OUTSET_PIN15_Pos) /*!< Bit mask of PIN15 field. */ #define GPIO_OUTSET_PIN15_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTSET_PIN15_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTSET_PIN15_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ +#define GPIO_OUTSET_PIN15_Set (1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */ /* Bit 14 : Pin 14 */ #define GPIO_OUTSET_PIN14_Pos (14UL) /*!< Position of PIN14 field. */ #define GPIO_OUTSET_PIN14_Msk (0x1UL << GPIO_OUTSET_PIN14_Pos) /*!< Bit mask of PIN14 field. */ #define GPIO_OUTSET_PIN14_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTSET_PIN14_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTSET_PIN14_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ +#define GPIO_OUTSET_PIN14_Set (1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */ /* Bit 13 : Pin 13 */ #define GPIO_OUTSET_PIN13_Pos (13UL) /*!< Position of PIN13 field. */ #define GPIO_OUTSET_PIN13_Msk (0x1UL << GPIO_OUTSET_PIN13_Pos) /*!< Bit mask of PIN13 field. */ #define GPIO_OUTSET_PIN13_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTSET_PIN13_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTSET_PIN13_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ +#define GPIO_OUTSET_PIN13_Set (1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */ /* Bit 12 : Pin 12 */ #define GPIO_OUTSET_PIN12_Pos (12UL) /*!< Position of PIN12 field. */ #define GPIO_OUTSET_PIN12_Msk (0x1UL << GPIO_OUTSET_PIN12_Pos) /*!< Bit mask of PIN12 field. */ #define GPIO_OUTSET_PIN12_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTSET_PIN12_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTSET_PIN12_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ +#define GPIO_OUTSET_PIN12_Set (1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */ /* Bit 11 : Pin 11 */ #define GPIO_OUTSET_PIN11_Pos (11UL) /*!< Position of PIN11 field. */ #define GPIO_OUTSET_PIN11_Msk (0x1UL << GPIO_OUTSET_PIN11_Pos) /*!< Bit mask of PIN11 field. */ #define GPIO_OUTSET_PIN11_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTSET_PIN11_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTSET_PIN11_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ +#define GPIO_OUTSET_PIN11_Set (1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */ /* Bit 10 : Pin 10 */ #define GPIO_OUTSET_PIN10_Pos (10UL) /*!< Position of PIN10 field. */ #define GPIO_OUTSET_PIN10_Msk (0x1UL << GPIO_OUTSET_PIN10_Pos) /*!< Bit mask of PIN10 field. */ #define GPIO_OUTSET_PIN10_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTSET_PIN10_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTSET_PIN10_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ +#define GPIO_OUTSET_PIN10_Set (1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */ /* Bit 9 : Pin 9 */ #define GPIO_OUTSET_PIN9_Pos (9UL) /*!< Position of PIN9 field. */ #define GPIO_OUTSET_PIN9_Msk (0x1UL << GPIO_OUTSET_PIN9_Pos) /*!< Bit mask of PIN9 field. */ #define GPIO_OUTSET_PIN9_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTSET_PIN9_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTSET_PIN9_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ +#define GPIO_OUTSET_PIN9_Set (1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */ /* Bit 8 : Pin 8 */ #define GPIO_OUTSET_PIN8_Pos (8UL) /*!< Position of PIN8 field. */ #define GPIO_OUTSET_PIN8_Msk (0x1UL << GPIO_OUTSET_PIN8_Pos) /*!< Bit mask of PIN8 field. */ #define GPIO_OUTSET_PIN8_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTSET_PIN8_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTSET_PIN8_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ +#define GPIO_OUTSET_PIN8_Set (1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */ /* Bit 7 : Pin 7 */ #define GPIO_OUTSET_PIN7_Pos (7UL) /*!< Position of PIN7 field. */ #define GPIO_OUTSET_PIN7_Msk (0x1UL << GPIO_OUTSET_PIN7_Pos) /*!< Bit mask of PIN7 field. */ #define GPIO_OUTSET_PIN7_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTSET_PIN7_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTSET_PIN7_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ +#define GPIO_OUTSET_PIN7_Set (1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */ /* Bit 6 : Pin 6 */ #define GPIO_OUTSET_PIN6_Pos (6UL) /*!< Position of PIN6 field. */ #define GPIO_OUTSET_PIN6_Msk (0x1UL << GPIO_OUTSET_PIN6_Pos) /*!< Bit mask of PIN6 field. */ #define GPIO_OUTSET_PIN6_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTSET_PIN6_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTSET_PIN6_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ +#define GPIO_OUTSET_PIN6_Set (1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */ /* Bit 5 : Pin 5 */ #define GPIO_OUTSET_PIN5_Pos (5UL) /*!< Position of PIN5 field. */ #define GPIO_OUTSET_PIN5_Msk (0x1UL << GPIO_OUTSET_PIN5_Pos) /*!< Bit mask of PIN5 field. */ #define GPIO_OUTSET_PIN5_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTSET_PIN5_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTSET_PIN5_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ +#define GPIO_OUTSET_PIN5_Set (1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */ /* Bit 4 : Pin 4 */ #define GPIO_OUTSET_PIN4_Pos (4UL) /*!< Position of PIN4 field. */ #define GPIO_OUTSET_PIN4_Msk (0x1UL << GPIO_OUTSET_PIN4_Pos) /*!< Bit mask of PIN4 field. */ #define GPIO_OUTSET_PIN4_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTSET_PIN4_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTSET_PIN4_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ +#define GPIO_OUTSET_PIN4_Set (1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */ /* Bit 3 : Pin 3 */ #define GPIO_OUTSET_PIN3_Pos (3UL) /*!< Position of PIN3 field. */ #define GPIO_OUTSET_PIN3_Msk (0x1UL << GPIO_OUTSET_PIN3_Pos) /*!< Bit mask of PIN3 field. */ #define GPIO_OUTSET_PIN3_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTSET_PIN3_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTSET_PIN3_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ +#define GPIO_OUTSET_PIN3_Set (1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */ /* Bit 2 : Pin 2 */ #define GPIO_OUTSET_PIN2_Pos (2UL) /*!< Position of PIN2 field. */ #define GPIO_OUTSET_PIN2_Msk (0x1UL << GPIO_OUTSET_PIN2_Pos) /*!< Bit mask of PIN2 field. */ #define GPIO_OUTSET_PIN2_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTSET_PIN2_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTSET_PIN2_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ +#define GPIO_OUTSET_PIN2_Set (1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */ /* Bit 1 : Pin 1 */ #define GPIO_OUTSET_PIN1_Pos (1UL) /*!< Position of PIN1 field. */ #define GPIO_OUTSET_PIN1_Msk (0x1UL << GPIO_OUTSET_PIN1_Pos) /*!< Bit mask of PIN1 field. */ #define GPIO_OUTSET_PIN1_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTSET_PIN1_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTSET_PIN1_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ +#define GPIO_OUTSET_PIN1_Set (1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */ /* Bit 0 : Pin 0 */ #define GPIO_OUTSET_PIN0_Pos (0UL) /*!< Position of PIN0 field. */ #define GPIO_OUTSET_PIN0_Msk (0x1UL << GPIO_OUTSET_PIN0_Pos) /*!< Bit mask of PIN0 field. */ #define GPIO_OUTSET_PIN0_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTSET_PIN0_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTSET_PIN0_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ +#define GPIO_OUTSET_PIN0_Set (1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */ /* Register: GPIO_OUTCLR */ /* Description: Clear individual bits in GPIO port */ @@ -5474,224 +5502,224 @@ POSSIBILITY OF SUCH DAMAGE. #define GPIO_OUTCLR_PIN31_Msk (0x1UL << GPIO_OUTCLR_PIN31_Pos) /*!< Bit mask of PIN31 field. */ #define GPIO_OUTCLR_PIN31_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTCLR_PIN31_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTCLR_PIN31_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ +#define GPIO_OUTCLR_PIN31_Clear (1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */ /* Bit 30 : Pin 30 */ #define GPIO_OUTCLR_PIN30_Pos (30UL) /*!< Position of PIN30 field. */ #define GPIO_OUTCLR_PIN30_Msk (0x1UL << GPIO_OUTCLR_PIN30_Pos) /*!< Bit mask of PIN30 field. */ #define GPIO_OUTCLR_PIN30_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTCLR_PIN30_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTCLR_PIN30_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ +#define GPIO_OUTCLR_PIN30_Clear (1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */ /* Bit 29 : Pin 29 */ #define GPIO_OUTCLR_PIN29_Pos (29UL) /*!< Position of PIN29 field. */ #define GPIO_OUTCLR_PIN29_Msk (0x1UL << GPIO_OUTCLR_PIN29_Pos) /*!< Bit mask of PIN29 field. */ #define GPIO_OUTCLR_PIN29_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTCLR_PIN29_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTCLR_PIN29_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ +#define GPIO_OUTCLR_PIN29_Clear (1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */ /* Bit 28 : Pin 28 */ #define GPIO_OUTCLR_PIN28_Pos (28UL) /*!< Position of PIN28 field. */ #define GPIO_OUTCLR_PIN28_Msk (0x1UL << GPIO_OUTCLR_PIN28_Pos) /*!< Bit mask of PIN28 field. */ #define GPIO_OUTCLR_PIN28_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTCLR_PIN28_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTCLR_PIN28_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ +#define GPIO_OUTCLR_PIN28_Clear (1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */ /* Bit 27 : Pin 27 */ #define GPIO_OUTCLR_PIN27_Pos (27UL) /*!< Position of PIN27 field. */ #define GPIO_OUTCLR_PIN27_Msk (0x1UL << GPIO_OUTCLR_PIN27_Pos) /*!< Bit mask of PIN27 field. */ #define GPIO_OUTCLR_PIN27_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTCLR_PIN27_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTCLR_PIN27_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ +#define GPIO_OUTCLR_PIN27_Clear (1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */ /* Bit 26 : Pin 26 */ #define GPIO_OUTCLR_PIN26_Pos (26UL) /*!< Position of PIN26 field. */ #define GPIO_OUTCLR_PIN26_Msk (0x1UL << GPIO_OUTCLR_PIN26_Pos) /*!< Bit mask of PIN26 field. */ #define GPIO_OUTCLR_PIN26_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTCLR_PIN26_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTCLR_PIN26_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ +#define GPIO_OUTCLR_PIN26_Clear (1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */ /* Bit 25 : Pin 25 */ #define GPIO_OUTCLR_PIN25_Pos (25UL) /*!< Position of PIN25 field. */ #define GPIO_OUTCLR_PIN25_Msk (0x1UL << GPIO_OUTCLR_PIN25_Pos) /*!< Bit mask of PIN25 field. */ #define GPIO_OUTCLR_PIN25_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTCLR_PIN25_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTCLR_PIN25_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ +#define GPIO_OUTCLR_PIN25_Clear (1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */ /* Bit 24 : Pin 24 */ #define GPIO_OUTCLR_PIN24_Pos (24UL) /*!< Position of PIN24 field. */ #define GPIO_OUTCLR_PIN24_Msk (0x1UL << GPIO_OUTCLR_PIN24_Pos) /*!< Bit mask of PIN24 field. */ #define GPIO_OUTCLR_PIN24_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTCLR_PIN24_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTCLR_PIN24_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ +#define GPIO_OUTCLR_PIN24_Clear (1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */ /* Bit 23 : Pin 23 */ #define GPIO_OUTCLR_PIN23_Pos (23UL) /*!< Position of PIN23 field. */ #define GPIO_OUTCLR_PIN23_Msk (0x1UL << GPIO_OUTCLR_PIN23_Pos) /*!< Bit mask of PIN23 field. */ #define GPIO_OUTCLR_PIN23_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTCLR_PIN23_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTCLR_PIN23_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ +#define GPIO_OUTCLR_PIN23_Clear (1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */ /* Bit 22 : Pin 22 */ #define GPIO_OUTCLR_PIN22_Pos (22UL) /*!< Position of PIN22 field. */ #define GPIO_OUTCLR_PIN22_Msk (0x1UL << GPIO_OUTCLR_PIN22_Pos) /*!< Bit mask of PIN22 field. */ #define GPIO_OUTCLR_PIN22_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTCLR_PIN22_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTCLR_PIN22_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ +#define GPIO_OUTCLR_PIN22_Clear (1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */ /* Bit 21 : Pin 21 */ #define GPIO_OUTCLR_PIN21_Pos (21UL) /*!< Position of PIN21 field. */ #define GPIO_OUTCLR_PIN21_Msk (0x1UL << GPIO_OUTCLR_PIN21_Pos) /*!< Bit mask of PIN21 field. */ #define GPIO_OUTCLR_PIN21_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTCLR_PIN21_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTCLR_PIN21_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ +#define GPIO_OUTCLR_PIN21_Clear (1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */ /* Bit 20 : Pin 20 */ #define GPIO_OUTCLR_PIN20_Pos (20UL) /*!< Position of PIN20 field. */ #define GPIO_OUTCLR_PIN20_Msk (0x1UL << GPIO_OUTCLR_PIN20_Pos) /*!< Bit mask of PIN20 field. */ #define GPIO_OUTCLR_PIN20_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTCLR_PIN20_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTCLR_PIN20_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ +#define GPIO_OUTCLR_PIN20_Clear (1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */ /* Bit 19 : Pin 19 */ #define GPIO_OUTCLR_PIN19_Pos (19UL) /*!< Position of PIN19 field. */ #define GPIO_OUTCLR_PIN19_Msk (0x1UL << GPIO_OUTCLR_PIN19_Pos) /*!< Bit mask of PIN19 field. */ #define GPIO_OUTCLR_PIN19_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTCLR_PIN19_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTCLR_PIN19_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ +#define GPIO_OUTCLR_PIN19_Clear (1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */ /* Bit 18 : Pin 18 */ #define GPIO_OUTCLR_PIN18_Pos (18UL) /*!< Position of PIN18 field. */ #define GPIO_OUTCLR_PIN18_Msk (0x1UL << GPIO_OUTCLR_PIN18_Pos) /*!< Bit mask of PIN18 field. */ #define GPIO_OUTCLR_PIN18_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTCLR_PIN18_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTCLR_PIN18_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ +#define GPIO_OUTCLR_PIN18_Clear (1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */ /* Bit 17 : Pin 17 */ #define GPIO_OUTCLR_PIN17_Pos (17UL) /*!< Position of PIN17 field. */ #define GPIO_OUTCLR_PIN17_Msk (0x1UL << GPIO_OUTCLR_PIN17_Pos) /*!< Bit mask of PIN17 field. */ #define GPIO_OUTCLR_PIN17_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTCLR_PIN17_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTCLR_PIN17_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ +#define GPIO_OUTCLR_PIN17_Clear (1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */ /* Bit 16 : Pin 16 */ #define GPIO_OUTCLR_PIN16_Pos (16UL) /*!< Position of PIN16 field. */ #define GPIO_OUTCLR_PIN16_Msk (0x1UL << GPIO_OUTCLR_PIN16_Pos) /*!< Bit mask of PIN16 field. */ #define GPIO_OUTCLR_PIN16_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTCLR_PIN16_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTCLR_PIN16_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ +#define GPIO_OUTCLR_PIN16_Clear (1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */ /* Bit 15 : Pin 15 */ #define GPIO_OUTCLR_PIN15_Pos (15UL) /*!< Position of PIN15 field. */ #define GPIO_OUTCLR_PIN15_Msk (0x1UL << GPIO_OUTCLR_PIN15_Pos) /*!< Bit mask of PIN15 field. */ #define GPIO_OUTCLR_PIN15_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTCLR_PIN15_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTCLR_PIN15_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ +#define GPIO_OUTCLR_PIN15_Clear (1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */ /* Bit 14 : Pin 14 */ #define GPIO_OUTCLR_PIN14_Pos (14UL) /*!< Position of PIN14 field. */ #define GPIO_OUTCLR_PIN14_Msk (0x1UL << GPIO_OUTCLR_PIN14_Pos) /*!< Bit mask of PIN14 field. */ #define GPIO_OUTCLR_PIN14_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTCLR_PIN14_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTCLR_PIN14_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ +#define GPIO_OUTCLR_PIN14_Clear (1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */ /* Bit 13 : Pin 13 */ #define GPIO_OUTCLR_PIN13_Pos (13UL) /*!< Position of PIN13 field. */ #define GPIO_OUTCLR_PIN13_Msk (0x1UL << GPIO_OUTCLR_PIN13_Pos) /*!< Bit mask of PIN13 field. */ #define GPIO_OUTCLR_PIN13_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTCLR_PIN13_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTCLR_PIN13_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ +#define GPIO_OUTCLR_PIN13_Clear (1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */ /* Bit 12 : Pin 12 */ #define GPIO_OUTCLR_PIN12_Pos (12UL) /*!< Position of PIN12 field. */ #define GPIO_OUTCLR_PIN12_Msk (0x1UL << GPIO_OUTCLR_PIN12_Pos) /*!< Bit mask of PIN12 field. */ #define GPIO_OUTCLR_PIN12_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTCLR_PIN12_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTCLR_PIN12_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ +#define GPIO_OUTCLR_PIN12_Clear (1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */ /* Bit 11 : Pin 11 */ #define GPIO_OUTCLR_PIN11_Pos (11UL) /*!< Position of PIN11 field. */ #define GPIO_OUTCLR_PIN11_Msk (0x1UL << GPIO_OUTCLR_PIN11_Pos) /*!< Bit mask of PIN11 field. */ #define GPIO_OUTCLR_PIN11_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTCLR_PIN11_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTCLR_PIN11_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ +#define GPIO_OUTCLR_PIN11_Clear (1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */ /* Bit 10 : Pin 10 */ #define GPIO_OUTCLR_PIN10_Pos (10UL) /*!< Position of PIN10 field. */ #define GPIO_OUTCLR_PIN10_Msk (0x1UL << GPIO_OUTCLR_PIN10_Pos) /*!< Bit mask of PIN10 field. */ #define GPIO_OUTCLR_PIN10_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTCLR_PIN10_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTCLR_PIN10_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ +#define GPIO_OUTCLR_PIN10_Clear (1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */ /* Bit 9 : Pin 9 */ #define GPIO_OUTCLR_PIN9_Pos (9UL) /*!< Position of PIN9 field. */ #define GPIO_OUTCLR_PIN9_Msk (0x1UL << GPIO_OUTCLR_PIN9_Pos) /*!< Bit mask of PIN9 field. */ #define GPIO_OUTCLR_PIN9_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTCLR_PIN9_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTCLR_PIN9_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ +#define GPIO_OUTCLR_PIN9_Clear (1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */ /* Bit 8 : Pin 8 */ #define GPIO_OUTCLR_PIN8_Pos (8UL) /*!< Position of PIN8 field. */ #define GPIO_OUTCLR_PIN8_Msk (0x1UL << GPIO_OUTCLR_PIN8_Pos) /*!< Bit mask of PIN8 field. */ #define GPIO_OUTCLR_PIN8_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTCLR_PIN8_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTCLR_PIN8_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ +#define GPIO_OUTCLR_PIN8_Clear (1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */ /* Bit 7 : Pin 7 */ #define GPIO_OUTCLR_PIN7_Pos (7UL) /*!< Position of PIN7 field. */ #define GPIO_OUTCLR_PIN7_Msk (0x1UL << GPIO_OUTCLR_PIN7_Pos) /*!< Bit mask of PIN7 field. */ #define GPIO_OUTCLR_PIN7_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTCLR_PIN7_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTCLR_PIN7_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ +#define GPIO_OUTCLR_PIN7_Clear (1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */ /* Bit 6 : Pin 6 */ #define GPIO_OUTCLR_PIN6_Pos (6UL) /*!< Position of PIN6 field. */ #define GPIO_OUTCLR_PIN6_Msk (0x1UL << GPIO_OUTCLR_PIN6_Pos) /*!< Bit mask of PIN6 field. */ #define GPIO_OUTCLR_PIN6_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTCLR_PIN6_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTCLR_PIN6_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ +#define GPIO_OUTCLR_PIN6_Clear (1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */ /* Bit 5 : Pin 5 */ #define GPIO_OUTCLR_PIN5_Pos (5UL) /*!< Position of PIN5 field. */ #define GPIO_OUTCLR_PIN5_Msk (0x1UL << GPIO_OUTCLR_PIN5_Pos) /*!< Bit mask of PIN5 field. */ #define GPIO_OUTCLR_PIN5_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTCLR_PIN5_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTCLR_PIN5_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ +#define GPIO_OUTCLR_PIN5_Clear (1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */ /* Bit 4 : Pin 4 */ #define GPIO_OUTCLR_PIN4_Pos (4UL) /*!< Position of PIN4 field. */ #define GPIO_OUTCLR_PIN4_Msk (0x1UL << GPIO_OUTCLR_PIN4_Pos) /*!< Bit mask of PIN4 field. */ #define GPIO_OUTCLR_PIN4_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTCLR_PIN4_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTCLR_PIN4_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ +#define GPIO_OUTCLR_PIN4_Clear (1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */ /* Bit 3 : Pin 3 */ #define GPIO_OUTCLR_PIN3_Pos (3UL) /*!< Position of PIN3 field. */ #define GPIO_OUTCLR_PIN3_Msk (0x1UL << GPIO_OUTCLR_PIN3_Pos) /*!< Bit mask of PIN3 field. */ #define GPIO_OUTCLR_PIN3_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTCLR_PIN3_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTCLR_PIN3_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ +#define GPIO_OUTCLR_PIN3_Clear (1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */ /* Bit 2 : Pin 2 */ #define GPIO_OUTCLR_PIN2_Pos (2UL) /*!< Position of PIN2 field. */ #define GPIO_OUTCLR_PIN2_Msk (0x1UL << GPIO_OUTCLR_PIN2_Pos) /*!< Bit mask of PIN2 field. */ #define GPIO_OUTCLR_PIN2_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTCLR_PIN2_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTCLR_PIN2_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ +#define GPIO_OUTCLR_PIN2_Clear (1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */ /* Bit 1 : Pin 1 */ #define GPIO_OUTCLR_PIN1_Pos (1UL) /*!< Position of PIN1 field. */ #define GPIO_OUTCLR_PIN1_Msk (0x1UL << GPIO_OUTCLR_PIN1_Pos) /*!< Bit mask of PIN1 field. */ #define GPIO_OUTCLR_PIN1_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTCLR_PIN1_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTCLR_PIN1_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ +#define GPIO_OUTCLR_PIN1_Clear (1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */ /* Bit 0 : Pin 0 */ #define GPIO_OUTCLR_PIN0_Pos (0UL) /*!< Position of PIN0 field. */ #define GPIO_OUTCLR_PIN0_Msk (0x1UL << GPIO_OUTCLR_PIN0_Pos) /*!< Bit mask of PIN0 field. */ #define GPIO_OUTCLR_PIN0_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTCLR_PIN0_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTCLR_PIN0_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ +#define GPIO_OUTCLR_PIN0_Clear (1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */ /* Register: GPIO_IN */ /* Description: Read GPIO port */ @@ -6091,224 +6119,224 @@ POSSIBILITY OF SUCH DAMAGE. #define GPIO_DIRSET_PIN31_Msk (0x1UL << GPIO_DIRSET_PIN31_Pos) /*!< Bit mask of PIN31 field. */ #define GPIO_DIRSET_PIN31_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRSET_PIN31_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRSET_PIN31_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ +#define GPIO_DIRSET_PIN31_Set (1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */ /* Bit 30 : Set as output pin 30 */ #define GPIO_DIRSET_PIN30_Pos (30UL) /*!< Position of PIN30 field. */ #define GPIO_DIRSET_PIN30_Msk (0x1UL << GPIO_DIRSET_PIN30_Pos) /*!< Bit mask of PIN30 field. */ #define GPIO_DIRSET_PIN30_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRSET_PIN30_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRSET_PIN30_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ +#define GPIO_DIRSET_PIN30_Set (1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */ /* Bit 29 : Set as output pin 29 */ #define GPIO_DIRSET_PIN29_Pos (29UL) /*!< Position of PIN29 field. */ #define GPIO_DIRSET_PIN29_Msk (0x1UL << GPIO_DIRSET_PIN29_Pos) /*!< Bit mask of PIN29 field. */ #define GPIO_DIRSET_PIN29_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRSET_PIN29_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRSET_PIN29_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ +#define GPIO_DIRSET_PIN29_Set (1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */ /* Bit 28 : Set as output pin 28 */ #define GPIO_DIRSET_PIN28_Pos (28UL) /*!< Position of PIN28 field. */ #define GPIO_DIRSET_PIN28_Msk (0x1UL << GPIO_DIRSET_PIN28_Pos) /*!< Bit mask of PIN28 field. */ #define GPIO_DIRSET_PIN28_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRSET_PIN28_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRSET_PIN28_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ +#define GPIO_DIRSET_PIN28_Set (1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */ /* Bit 27 : Set as output pin 27 */ #define GPIO_DIRSET_PIN27_Pos (27UL) /*!< Position of PIN27 field. */ #define GPIO_DIRSET_PIN27_Msk (0x1UL << GPIO_DIRSET_PIN27_Pos) /*!< Bit mask of PIN27 field. */ #define GPIO_DIRSET_PIN27_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRSET_PIN27_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRSET_PIN27_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ +#define GPIO_DIRSET_PIN27_Set (1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */ /* Bit 26 : Set as output pin 26 */ #define GPIO_DIRSET_PIN26_Pos (26UL) /*!< Position of PIN26 field. */ #define GPIO_DIRSET_PIN26_Msk (0x1UL << GPIO_DIRSET_PIN26_Pos) /*!< Bit mask of PIN26 field. */ #define GPIO_DIRSET_PIN26_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRSET_PIN26_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRSET_PIN26_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ +#define GPIO_DIRSET_PIN26_Set (1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */ /* Bit 25 : Set as output pin 25 */ #define GPIO_DIRSET_PIN25_Pos (25UL) /*!< Position of PIN25 field. */ #define GPIO_DIRSET_PIN25_Msk (0x1UL << GPIO_DIRSET_PIN25_Pos) /*!< Bit mask of PIN25 field. */ #define GPIO_DIRSET_PIN25_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRSET_PIN25_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRSET_PIN25_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ +#define GPIO_DIRSET_PIN25_Set (1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */ /* Bit 24 : Set as output pin 24 */ #define GPIO_DIRSET_PIN24_Pos (24UL) /*!< Position of PIN24 field. */ #define GPIO_DIRSET_PIN24_Msk (0x1UL << GPIO_DIRSET_PIN24_Pos) /*!< Bit mask of PIN24 field. */ #define GPIO_DIRSET_PIN24_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRSET_PIN24_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRSET_PIN24_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ +#define GPIO_DIRSET_PIN24_Set (1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */ /* Bit 23 : Set as output pin 23 */ #define GPIO_DIRSET_PIN23_Pos (23UL) /*!< Position of PIN23 field. */ #define GPIO_DIRSET_PIN23_Msk (0x1UL << GPIO_DIRSET_PIN23_Pos) /*!< Bit mask of PIN23 field. */ #define GPIO_DIRSET_PIN23_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRSET_PIN23_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRSET_PIN23_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ +#define GPIO_DIRSET_PIN23_Set (1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */ /* Bit 22 : Set as output pin 22 */ #define GPIO_DIRSET_PIN22_Pos (22UL) /*!< Position of PIN22 field. */ #define GPIO_DIRSET_PIN22_Msk (0x1UL << GPIO_DIRSET_PIN22_Pos) /*!< Bit mask of PIN22 field. */ #define GPIO_DIRSET_PIN22_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRSET_PIN22_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRSET_PIN22_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ +#define GPIO_DIRSET_PIN22_Set (1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */ /* Bit 21 : Set as output pin 21 */ #define GPIO_DIRSET_PIN21_Pos (21UL) /*!< Position of PIN21 field. */ #define GPIO_DIRSET_PIN21_Msk (0x1UL << GPIO_DIRSET_PIN21_Pos) /*!< Bit mask of PIN21 field. */ #define GPIO_DIRSET_PIN21_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRSET_PIN21_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRSET_PIN21_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ +#define GPIO_DIRSET_PIN21_Set (1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */ /* Bit 20 : Set as output pin 20 */ #define GPIO_DIRSET_PIN20_Pos (20UL) /*!< Position of PIN20 field. */ #define GPIO_DIRSET_PIN20_Msk (0x1UL << GPIO_DIRSET_PIN20_Pos) /*!< Bit mask of PIN20 field. */ #define GPIO_DIRSET_PIN20_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRSET_PIN20_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRSET_PIN20_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ +#define GPIO_DIRSET_PIN20_Set (1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */ /* Bit 19 : Set as output pin 19 */ #define GPIO_DIRSET_PIN19_Pos (19UL) /*!< Position of PIN19 field. */ #define GPIO_DIRSET_PIN19_Msk (0x1UL << GPIO_DIRSET_PIN19_Pos) /*!< Bit mask of PIN19 field. */ #define GPIO_DIRSET_PIN19_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRSET_PIN19_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRSET_PIN19_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ +#define GPIO_DIRSET_PIN19_Set (1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */ /* Bit 18 : Set as output pin 18 */ #define GPIO_DIRSET_PIN18_Pos (18UL) /*!< Position of PIN18 field. */ #define GPIO_DIRSET_PIN18_Msk (0x1UL << GPIO_DIRSET_PIN18_Pos) /*!< Bit mask of PIN18 field. */ #define GPIO_DIRSET_PIN18_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRSET_PIN18_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRSET_PIN18_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ +#define GPIO_DIRSET_PIN18_Set (1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */ /* Bit 17 : Set as output pin 17 */ #define GPIO_DIRSET_PIN17_Pos (17UL) /*!< Position of PIN17 field. */ #define GPIO_DIRSET_PIN17_Msk (0x1UL << GPIO_DIRSET_PIN17_Pos) /*!< Bit mask of PIN17 field. */ #define GPIO_DIRSET_PIN17_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRSET_PIN17_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRSET_PIN17_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ +#define GPIO_DIRSET_PIN17_Set (1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */ /* Bit 16 : Set as output pin 16 */ #define GPIO_DIRSET_PIN16_Pos (16UL) /*!< Position of PIN16 field. */ #define GPIO_DIRSET_PIN16_Msk (0x1UL << GPIO_DIRSET_PIN16_Pos) /*!< Bit mask of PIN16 field. */ #define GPIO_DIRSET_PIN16_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRSET_PIN16_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRSET_PIN16_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ +#define GPIO_DIRSET_PIN16_Set (1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */ /* Bit 15 : Set as output pin 15 */ #define GPIO_DIRSET_PIN15_Pos (15UL) /*!< Position of PIN15 field. */ #define GPIO_DIRSET_PIN15_Msk (0x1UL << GPIO_DIRSET_PIN15_Pos) /*!< Bit mask of PIN15 field. */ #define GPIO_DIRSET_PIN15_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRSET_PIN15_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRSET_PIN15_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ +#define GPIO_DIRSET_PIN15_Set (1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */ /* Bit 14 : Set as output pin 14 */ #define GPIO_DIRSET_PIN14_Pos (14UL) /*!< Position of PIN14 field. */ #define GPIO_DIRSET_PIN14_Msk (0x1UL << GPIO_DIRSET_PIN14_Pos) /*!< Bit mask of PIN14 field. */ #define GPIO_DIRSET_PIN14_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRSET_PIN14_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRSET_PIN14_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ +#define GPIO_DIRSET_PIN14_Set (1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */ /* Bit 13 : Set as output pin 13 */ #define GPIO_DIRSET_PIN13_Pos (13UL) /*!< Position of PIN13 field. */ #define GPIO_DIRSET_PIN13_Msk (0x1UL << GPIO_DIRSET_PIN13_Pos) /*!< Bit mask of PIN13 field. */ #define GPIO_DIRSET_PIN13_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRSET_PIN13_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRSET_PIN13_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ +#define GPIO_DIRSET_PIN13_Set (1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */ /* Bit 12 : Set as output pin 12 */ #define GPIO_DIRSET_PIN12_Pos (12UL) /*!< Position of PIN12 field. */ #define GPIO_DIRSET_PIN12_Msk (0x1UL << GPIO_DIRSET_PIN12_Pos) /*!< Bit mask of PIN12 field. */ #define GPIO_DIRSET_PIN12_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRSET_PIN12_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRSET_PIN12_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ +#define GPIO_DIRSET_PIN12_Set (1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */ /* Bit 11 : Set as output pin 11 */ #define GPIO_DIRSET_PIN11_Pos (11UL) /*!< Position of PIN11 field. */ #define GPIO_DIRSET_PIN11_Msk (0x1UL << GPIO_DIRSET_PIN11_Pos) /*!< Bit mask of PIN11 field. */ #define GPIO_DIRSET_PIN11_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRSET_PIN11_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRSET_PIN11_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ +#define GPIO_DIRSET_PIN11_Set (1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */ /* Bit 10 : Set as output pin 10 */ #define GPIO_DIRSET_PIN10_Pos (10UL) /*!< Position of PIN10 field. */ #define GPIO_DIRSET_PIN10_Msk (0x1UL << GPIO_DIRSET_PIN10_Pos) /*!< Bit mask of PIN10 field. */ #define GPIO_DIRSET_PIN10_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRSET_PIN10_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRSET_PIN10_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ +#define GPIO_DIRSET_PIN10_Set (1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */ /* Bit 9 : Set as output pin 9 */ #define GPIO_DIRSET_PIN9_Pos (9UL) /*!< Position of PIN9 field. */ #define GPIO_DIRSET_PIN9_Msk (0x1UL << GPIO_DIRSET_PIN9_Pos) /*!< Bit mask of PIN9 field. */ #define GPIO_DIRSET_PIN9_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRSET_PIN9_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRSET_PIN9_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ +#define GPIO_DIRSET_PIN9_Set (1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */ /* Bit 8 : Set as output pin 8 */ #define GPIO_DIRSET_PIN8_Pos (8UL) /*!< Position of PIN8 field. */ #define GPIO_DIRSET_PIN8_Msk (0x1UL << GPIO_DIRSET_PIN8_Pos) /*!< Bit mask of PIN8 field. */ #define GPIO_DIRSET_PIN8_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRSET_PIN8_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRSET_PIN8_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ +#define GPIO_DIRSET_PIN8_Set (1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */ /* Bit 7 : Set as output pin 7 */ #define GPIO_DIRSET_PIN7_Pos (7UL) /*!< Position of PIN7 field. */ #define GPIO_DIRSET_PIN7_Msk (0x1UL << GPIO_DIRSET_PIN7_Pos) /*!< Bit mask of PIN7 field. */ #define GPIO_DIRSET_PIN7_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRSET_PIN7_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRSET_PIN7_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ +#define GPIO_DIRSET_PIN7_Set (1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */ /* Bit 6 : Set as output pin 6 */ #define GPIO_DIRSET_PIN6_Pos (6UL) /*!< Position of PIN6 field. */ #define GPIO_DIRSET_PIN6_Msk (0x1UL << GPIO_DIRSET_PIN6_Pos) /*!< Bit mask of PIN6 field. */ #define GPIO_DIRSET_PIN6_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRSET_PIN6_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRSET_PIN6_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ +#define GPIO_DIRSET_PIN6_Set (1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */ /* Bit 5 : Set as output pin 5 */ #define GPIO_DIRSET_PIN5_Pos (5UL) /*!< Position of PIN5 field. */ #define GPIO_DIRSET_PIN5_Msk (0x1UL << GPIO_DIRSET_PIN5_Pos) /*!< Bit mask of PIN5 field. */ #define GPIO_DIRSET_PIN5_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRSET_PIN5_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRSET_PIN5_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ +#define GPIO_DIRSET_PIN5_Set (1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */ /* Bit 4 : Set as output pin 4 */ #define GPIO_DIRSET_PIN4_Pos (4UL) /*!< Position of PIN4 field. */ #define GPIO_DIRSET_PIN4_Msk (0x1UL << GPIO_DIRSET_PIN4_Pos) /*!< Bit mask of PIN4 field. */ #define GPIO_DIRSET_PIN4_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRSET_PIN4_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRSET_PIN4_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ +#define GPIO_DIRSET_PIN4_Set (1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */ /* Bit 3 : Set as output pin 3 */ #define GPIO_DIRSET_PIN3_Pos (3UL) /*!< Position of PIN3 field. */ #define GPIO_DIRSET_PIN3_Msk (0x1UL << GPIO_DIRSET_PIN3_Pos) /*!< Bit mask of PIN3 field. */ #define GPIO_DIRSET_PIN3_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRSET_PIN3_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRSET_PIN3_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ +#define GPIO_DIRSET_PIN3_Set (1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */ /* Bit 2 : Set as output pin 2 */ #define GPIO_DIRSET_PIN2_Pos (2UL) /*!< Position of PIN2 field. */ #define GPIO_DIRSET_PIN2_Msk (0x1UL << GPIO_DIRSET_PIN2_Pos) /*!< Bit mask of PIN2 field. */ #define GPIO_DIRSET_PIN2_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRSET_PIN2_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRSET_PIN2_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ +#define GPIO_DIRSET_PIN2_Set (1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */ /* Bit 1 : Set as output pin 1 */ #define GPIO_DIRSET_PIN1_Pos (1UL) /*!< Position of PIN1 field. */ #define GPIO_DIRSET_PIN1_Msk (0x1UL << GPIO_DIRSET_PIN1_Pos) /*!< Bit mask of PIN1 field. */ #define GPIO_DIRSET_PIN1_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRSET_PIN1_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRSET_PIN1_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ +#define GPIO_DIRSET_PIN1_Set (1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */ /* Bit 0 : Set as output pin 0 */ #define GPIO_DIRSET_PIN0_Pos (0UL) /*!< Position of PIN0 field. */ #define GPIO_DIRSET_PIN0_Msk (0x1UL << GPIO_DIRSET_PIN0_Pos) /*!< Bit mask of PIN0 field. */ #define GPIO_DIRSET_PIN0_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRSET_PIN0_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRSET_PIN0_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ +#define GPIO_DIRSET_PIN0_Set (1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */ /* Register: GPIO_DIRCLR */ /* Description: DIR clear register */ @@ -6318,224 +6346,224 @@ POSSIBILITY OF SUCH DAMAGE. #define GPIO_DIRCLR_PIN31_Msk (0x1UL << GPIO_DIRCLR_PIN31_Pos) /*!< Bit mask of PIN31 field. */ #define GPIO_DIRCLR_PIN31_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRCLR_PIN31_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRCLR_PIN31_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ +#define GPIO_DIRCLR_PIN31_Clear (1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */ /* Bit 30 : Set as input pin 30 */ #define GPIO_DIRCLR_PIN30_Pos (30UL) /*!< Position of PIN30 field. */ #define GPIO_DIRCLR_PIN30_Msk (0x1UL << GPIO_DIRCLR_PIN30_Pos) /*!< Bit mask of PIN30 field. */ #define GPIO_DIRCLR_PIN30_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRCLR_PIN30_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRCLR_PIN30_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ +#define GPIO_DIRCLR_PIN30_Clear (1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */ /* Bit 29 : Set as input pin 29 */ #define GPIO_DIRCLR_PIN29_Pos (29UL) /*!< Position of PIN29 field. */ #define GPIO_DIRCLR_PIN29_Msk (0x1UL << GPIO_DIRCLR_PIN29_Pos) /*!< Bit mask of PIN29 field. */ #define GPIO_DIRCLR_PIN29_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRCLR_PIN29_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRCLR_PIN29_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ +#define GPIO_DIRCLR_PIN29_Clear (1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */ /* Bit 28 : Set as input pin 28 */ #define GPIO_DIRCLR_PIN28_Pos (28UL) /*!< Position of PIN28 field. */ #define GPIO_DIRCLR_PIN28_Msk (0x1UL << GPIO_DIRCLR_PIN28_Pos) /*!< Bit mask of PIN28 field. */ #define GPIO_DIRCLR_PIN28_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRCLR_PIN28_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRCLR_PIN28_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ +#define GPIO_DIRCLR_PIN28_Clear (1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */ /* Bit 27 : Set as input pin 27 */ #define GPIO_DIRCLR_PIN27_Pos (27UL) /*!< Position of PIN27 field. */ #define GPIO_DIRCLR_PIN27_Msk (0x1UL << GPIO_DIRCLR_PIN27_Pos) /*!< Bit mask of PIN27 field. */ #define GPIO_DIRCLR_PIN27_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRCLR_PIN27_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRCLR_PIN27_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ +#define GPIO_DIRCLR_PIN27_Clear (1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */ /* Bit 26 : Set as input pin 26 */ #define GPIO_DIRCLR_PIN26_Pos (26UL) /*!< Position of PIN26 field. */ #define GPIO_DIRCLR_PIN26_Msk (0x1UL << GPIO_DIRCLR_PIN26_Pos) /*!< Bit mask of PIN26 field. */ #define GPIO_DIRCLR_PIN26_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRCLR_PIN26_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRCLR_PIN26_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ +#define GPIO_DIRCLR_PIN26_Clear (1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */ /* Bit 25 : Set as input pin 25 */ #define GPIO_DIRCLR_PIN25_Pos (25UL) /*!< Position of PIN25 field. */ #define GPIO_DIRCLR_PIN25_Msk (0x1UL << GPIO_DIRCLR_PIN25_Pos) /*!< Bit mask of PIN25 field. */ #define GPIO_DIRCLR_PIN25_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRCLR_PIN25_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRCLR_PIN25_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ +#define GPIO_DIRCLR_PIN25_Clear (1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */ /* Bit 24 : Set as input pin 24 */ #define GPIO_DIRCLR_PIN24_Pos (24UL) /*!< Position of PIN24 field. */ #define GPIO_DIRCLR_PIN24_Msk (0x1UL << GPIO_DIRCLR_PIN24_Pos) /*!< Bit mask of PIN24 field. */ #define GPIO_DIRCLR_PIN24_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRCLR_PIN24_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRCLR_PIN24_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ +#define GPIO_DIRCLR_PIN24_Clear (1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */ /* Bit 23 : Set as input pin 23 */ #define GPIO_DIRCLR_PIN23_Pos (23UL) /*!< Position of PIN23 field. */ #define GPIO_DIRCLR_PIN23_Msk (0x1UL << GPIO_DIRCLR_PIN23_Pos) /*!< Bit mask of PIN23 field. */ #define GPIO_DIRCLR_PIN23_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRCLR_PIN23_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRCLR_PIN23_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ +#define GPIO_DIRCLR_PIN23_Clear (1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */ /* Bit 22 : Set as input pin 22 */ #define GPIO_DIRCLR_PIN22_Pos (22UL) /*!< Position of PIN22 field. */ #define GPIO_DIRCLR_PIN22_Msk (0x1UL << GPIO_DIRCLR_PIN22_Pos) /*!< Bit mask of PIN22 field. */ #define GPIO_DIRCLR_PIN22_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRCLR_PIN22_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRCLR_PIN22_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ +#define GPIO_DIRCLR_PIN22_Clear (1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */ /* Bit 21 : Set as input pin 21 */ #define GPIO_DIRCLR_PIN21_Pos (21UL) /*!< Position of PIN21 field. */ #define GPIO_DIRCLR_PIN21_Msk (0x1UL << GPIO_DIRCLR_PIN21_Pos) /*!< Bit mask of PIN21 field. */ #define GPIO_DIRCLR_PIN21_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRCLR_PIN21_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRCLR_PIN21_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ +#define GPIO_DIRCLR_PIN21_Clear (1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */ /* Bit 20 : Set as input pin 20 */ #define GPIO_DIRCLR_PIN20_Pos (20UL) /*!< Position of PIN20 field. */ #define GPIO_DIRCLR_PIN20_Msk (0x1UL << GPIO_DIRCLR_PIN20_Pos) /*!< Bit mask of PIN20 field. */ #define GPIO_DIRCLR_PIN20_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRCLR_PIN20_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRCLR_PIN20_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ +#define GPIO_DIRCLR_PIN20_Clear (1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */ /* Bit 19 : Set as input pin 19 */ #define GPIO_DIRCLR_PIN19_Pos (19UL) /*!< Position of PIN19 field. */ #define GPIO_DIRCLR_PIN19_Msk (0x1UL << GPIO_DIRCLR_PIN19_Pos) /*!< Bit mask of PIN19 field. */ #define GPIO_DIRCLR_PIN19_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRCLR_PIN19_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRCLR_PIN19_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ +#define GPIO_DIRCLR_PIN19_Clear (1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */ /* Bit 18 : Set as input pin 18 */ #define GPIO_DIRCLR_PIN18_Pos (18UL) /*!< Position of PIN18 field. */ #define GPIO_DIRCLR_PIN18_Msk (0x1UL << GPIO_DIRCLR_PIN18_Pos) /*!< Bit mask of PIN18 field. */ #define GPIO_DIRCLR_PIN18_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRCLR_PIN18_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRCLR_PIN18_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ +#define GPIO_DIRCLR_PIN18_Clear (1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */ /* Bit 17 : Set as input pin 17 */ #define GPIO_DIRCLR_PIN17_Pos (17UL) /*!< Position of PIN17 field. */ #define GPIO_DIRCLR_PIN17_Msk (0x1UL << GPIO_DIRCLR_PIN17_Pos) /*!< Bit mask of PIN17 field. */ #define GPIO_DIRCLR_PIN17_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRCLR_PIN17_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRCLR_PIN17_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ +#define GPIO_DIRCLR_PIN17_Clear (1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */ /* Bit 16 : Set as input pin 16 */ #define GPIO_DIRCLR_PIN16_Pos (16UL) /*!< Position of PIN16 field. */ #define GPIO_DIRCLR_PIN16_Msk (0x1UL << GPIO_DIRCLR_PIN16_Pos) /*!< Bit mask of PIN16 field. */ #define GPIO_DIRCLR_PIN16_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRCLR_PIN16_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRCLR_PIN16_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ +#define GPIO_DIRCLR_PIN16_Clear (1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */ /* Bit 15 : Set as input pin 15 */ #define GPIO_DIRCLR_PIN15_Pos (15UL) /*!< Position of PIN15 field. */ #define GPIO_DIRCLR_PIN15_Msk (0x1UL << GPIO_DIRCLR_PIN15_Pos) /*!< Bit mask of PIN15 field. */ #define GPIO_DIRCLR_PIN15_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRCLR_PIN15_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRCLR_PIN15_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ +#define GPIO_DIRCLR_PIN15_Clear (1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */ /* Bit 14 : Set as input pin 14 */ #define GPIO_DIRCLR_PIN14_Pos (14UL) /*!< Position of PIN14 field. */ #define GPIO_DIRCLR_PIN14_Msk (0x1UL << GPIO_DIRCLR_PIN14_Pos) /*!< Bit mask of PIN14 field. */ #define GPIO_DIRCLR_PIN14_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRCLR_PIN14_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRCLR_PIN14_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ +#define GPIO_DIRCLR_PIN14_Clear (1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */ /* Bit 13 : Set as input pin 13 */ #define GPIO_DIRCLR_PIN13_Pos (13UL) /*!< Position of PIN13 field. */ #define GPIO_DIRCLR_PIN13_Msk (0x1UL << GPIO_DIRCLR_PIN13_Pos) /*!< Bit mask of PIN13 field. */ #define GPIO_DIRCLR_PIN13_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRCLR_PIN13_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRCLR_PIN13_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ +#define GPIO_DIRCLR_PIN13_Clear (1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */ /* Bit 12 : Set as input pin 12 */ #define GPIO_DIRCLR_PIN12_Pos (12UL) /*!< Position of PIN12 field. */ #define GPIO_DIRCLR_PIN12_Msk (0x1UL << GPIO_DIRCLR_PIN12_Pos) /*!< Bit mask of PIN12 field. */ #define GPIO_DIRCLR_PIN12_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRCLR_PIN12_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRCLR_PIN12_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ +#define GPIO_DIRCLR_PIN12_Clear (1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */ /* Bit 11 : Set as input pin 11 */ #define GPIO_DIRCLR_PIN11_Pos (11UL) /*!< Position of PIN11 field. */ #define GPIO_DIRCLR_PIN11_Msk (0x1UL << GPIO_DIRCLR_PIN11_Pos) /*!< Bit mask of PIN11 field. */ #define GPIO_DIRCLR_PIN11_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRCLR_PIN11_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRCLR_PIN11_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ +#define GPIO_DIRCLR_PIN11_Clear (1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */ /* Bit 10 : Set as input pin 10 */ #define GPIO_DIRCLR_PIN10_Pos (10UL) /*!< Position of PIN10 field. */ #define GPIO_DIRCLR_PIN10_Msk (0x1UL << GPIO_DIRCLR_PIN10_Pos) /*!< Bit mask of PIN10 field. */ #define GPIO_DIRCLR_PIN10_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRCLR_PIN10_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRCLR_PIN10_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ +#define GPIO_DIRCLR_PIN10_Clear (1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */ /* Bit 9 : Set as input pin 9 */ #define GPIO_DIRCLR_PIN9_Pos (9UL) /*!< Position of PIN9 field. */ #define GPIO_DIRCLR_PIN9_Msk (0x1UL << GPIO_DIRCLR_PIN9_Pos) /*!< Bit mask of PIN9 field. */ #define GPIO_DIRCLR_PIN9_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRCLR_PIN9_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRCLR_PIN9_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ +#define GPIO_DIRCLR_PIN9_Clear (1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */ /* Bit 8 : Set as input pin 8 */ #define GPIO_DIRCLR_PIN8_Pos (8UL) /*!< Position of PIN8 field. */ #define GPIO_DIRCLR_PIN8_Msk (0x1UL << GPIO_DIRCLR_PIN8_Pos) /*!< Bit mask of PIN8 field. */ #define GPIO_DIRCLR_PIN8_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRCLR_PIN8_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRCLR_PIN8_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ +#define GPIO_DIRCLR_PIN8_Clear (1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */ /* Bit 7 : Set as input pin 7 */ #define GPIO_DIRCLR_PIN7_Pos (7UL) /*!< Position of PIN7 field. */ #define GPIO_DIRCLR_PIN7_Msk (0x1UL << GPIO_DIRCLR_PIN7_Pos) /*!< Bit mask of PIN7 field. */ #define GPIO_DIRCLR_PIN7_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRCLR_PIN7_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRCLR_PIN7_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ +#define GPIO_DIRCLR_PIN7_Clear (1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */ /* Bit 6 : Set as input pin 6 */ #define GPIO_DIRCLR_PIN6_Pos (6UL) /*!< Position of PIN6 field. */ #define GPIO_DIRCLR_PIN6_Msk (0x1UL << GPIO_DIRCLR_PIN6_Pos) /*!< Bit mask of PIN6 field. */ #define GPIO_DIRCLR_PIN6_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRCLR_PIN6_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRCLR_PIN6_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ +#define GPIO_DIRCLR_PIN6_Clear (1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */ /* Bit 5 : Set as input pin 5 */ #define GPIO_DIRCLR_PIN5_Pos (5UL) /*!< Position of PIN5 field. */ #define GPIO_DIRCLR_PIN5_Msk (0x1UL << GPIO_DIRCLR_PIN5_Pos) /*!< Bit mask of PIN5 field. */ #define GPIO_DIRCLR_PIN5_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRCLR_PIN5_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRCLR_PIN5_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ +#define GPIO_DIRCLR_PIN5_Clear (1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */ /* Bit 4 : Set as input pin 4 */ #define GPIO_DIRCLR_PIN4_Pos (4UL) /*!< Position of PIN4 field. */ #define GPIO_DIRCLR_PIN4_Msk (0x1UL << GPIO_DIRCLR_PIN4_Pos) /*!< Bit mask of PIN4 field. */ #define GPIO_DIRCLR_PIN4_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRCLR_PIN4_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRCLR_PIN4_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ +#define GPIO_DIRCLR_PIN4_Clear (1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */ /* Bit 3 : Set as input pin 3 */ #define GPIO_DIRCLR_PIN3_Pos (3UL) /*!< Position of PIN3 field. */ #define GPIO_DIRCLR_PIN3_Msk (0x1UL << GPIO_DIRCLR_PIN3_Pos) /*!< Bit mask of PIN3 field. */ #define GPIO_DIRCLR_PIN3_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRCLR_PIN3_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRCLR_PIN3_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ +#define GPIO_DIRCLR_PIN3_Clear (1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */ /* Bit 2 : Set as input pin 2 */ #define GPIO_DIRCLR_PIN2_Pos (2UL) /*!< Position of PIN2 field. */ #define GPIO_DIRCLR_PIN2_Msk (0x1UL << GPIO_DIRCLR_PIN2_Pos) /*!< Bit mask of PIN2 field. */ #define GPIO_DIRCLR_PIN2_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRCLR_PIN2_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRCLR_PIN2_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ +#define GPIO_DIRCLR_PIN2_Clear (1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */ /* Bit 1 : Set as input pin 1 */ #define GPIO_DIRCLR_PIN1_Pos (1UL) /*!< Position of PIN1 field. */ #define GPIO_DIRCLR_PIN1_Msk (0x1UL << GPIO_DIRCLR_PIN1_Pos) /*!< Bit mask of PIN1 field. */ #define GPIO_DIRCLR_PIN1_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRCLR_PIN1_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRCLR_PIN1_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ +#define GPIO_DIRCLR_PIN1_Clear (1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */ /* Bit 0 : Set as input pin 0 */ #define GPIO_DIRCLR_PIN0_Pos (0UL) /*!< Position of PIN0 field. */ #define GPIO_DIRCLR_PIN0_Msk (0x1UL << GPIO_DIRCLR_PIN0_Pos) /*!< Bit mask of PIN0 field. */ #define GPIO_DIRCLR_PIN0_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRCLR_PIN0_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRCLR_PIN0_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ +#define GPIO_DIRCLR_PIN0_Clear (1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */ /* Register: GPIO_LATCH */ /* Description: Latch register indicating what GPIO pins that have met the criteria set in the PIN_CNF[n].SENSE registers */ @@ -6733,13 +6761,13 @@ POSSIBILITY OF SUCH DAMAGE. #define GPIO_LATCH_PIN0_Latched (1UL) /*!< Criteria has been met */ /* Register: GPIO_DETECTMODE */ -/* Description: Select between default DETECT signal behaviour and LDETECT mode */ +/* Description: Select between default DETECT signal behavior and LDETECT mode */ -/* Bit 0 : Select between default DETECT signal behaviour and LDETECT mode */ +/* Bit 0 : Select between default DETECT signal behavior and LDETECT mode */ #define GPIO_DETECTMODE_DETECTMODE_Pos (0UL) /*!< Position of DETECTMODE field. */ #define GPIO_DETECTMODE_DETECTMODE_Msk (0x1UL << GPIO_DETECTMODE_DETECTMODE_Pos) /*!< Bit mask of DETECTMODE field. */ #define GPIO_DETECTMODE_DETECTMODE_Default (0UL) /*!< DETECT directly connected to PIN DETECT signals */ -#define GPIO_DETECTMODE_DETECTMODE_LDETECT (1UL) /*!< Use the latched LDETECT behaviour */ +#define GPIO_DETECTMODE_DETECTMODE_LDETECT (1UL) /*!< Use the latched LDETECT behavior */ /* Register: GPIO_PIN_CNF */ /* Description: Description collection: Configuration of GPIO pins */ @@ -6910,7 +6938,7 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: PDM_PDMCLKCTRL */ /* Description: PDM clock generator control */ -/* Bits 31..0 : PDM_CLK frequency */ +/* Bits 31..0 : PDM_CLK frequency configuration */ #define PDM_PDMCLKCTRL_FREQ_Pos (0UL) /*!< Position of FREQ field. */ #define PDM_PDMCLKCTRL_FREQ_Msk (0xFFFFFFFFUL << PDM_PDMCLKCTRL_FREQ_Pos) /*!< Bit mask of FREQ field. */ #define PDM_PDMCLKCTRL_FREQ_1000K (0x08000000UL) /*!< PDM_CLK = 32 MHz / 32 = 1.000 MHz */ @@ -6923,7 +6951,7 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: PDM_MODE */ /* Description: Defines the routing of the connected PDM microphones' signals */ -/* Bit 1 : Defines on which PDM_CLK edge Left (or mono) is sampled */ +/* Bit 1 : Defines on which PDM_CLK edge left (or mono) is sampled */ #define PDM_MODE_EDGE_Pos (1UL) /*!< Position of EDGE field. */ #define PDM_MODE_EDGE_Msk (0x1UL << PDM_MODE_EDGE_Pos) /*!< Bit mask of EDGE field. */ #define PDM_MODE_EDGE_LeftFalling (0UL) /*!< Left (or mono) is sampled on falling edge of PDM_CLK */ @@ -6932,8 +6960,8 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 0 : Mono or stereo operation */ #define PDM_MODE_OPERATION_Pos (0UL) /*!< Position of OPERATION field. */ #define PDM_MODE_OPERATION_Msk (0x1UL << PDM_MODE_OPERATION_Pos) /*!< Bit mask of OPERATION field. */ -#define PDM_MODE_OPERATION_Stereo (0UL) /*!< Sample and store one pair (Left + Right) of 16bit samples per RAM word R=[31:16]; L=[15:0] */ -#define PDM_MODE_OPERATION_Mono (1UL) /*!< Sample and store two successive Left samples (16 bit each) per RAM word L1=[31:16]; L0=[15:0] */ +#define PDM_MODE_OPERATION_Stereo (0UL) /*!< Sample and store one pair (left + right) of 16-bit samples per RAM word R=[31:16]; L=[15:0] */ +#define PDM_MODE_OPERATION_Mono (1UL) /*!< Sample and store two successive left samples (16 bits each) per RAM word L1=[31:16]; L0=[15:0] */ /* Register: PDM_GAINL */ /* Description: Left output gain adjustment */ @@ -6941,9 +6969,9 @@ POSSIBILITY OF SUCH DAMAGE. /* Bits 6..0 : Left output gain adjustment, in 0.5 dB steps, around the default module gain (see electrical parameters) 0x00 -20 dB gain adjust 0x01 -19.5 dB gain adjust (...) 0x27 -0.5 dB gain adjust 0x28 0 dB gain adjust 0x29 +0.5 dB gain adjust (...) 0x4F +19.5 dB gain adjust 0x50 +20 dB gain adjust */ #define PDM_GAINL_GAINL_Pos (0UL) /*!< Position of GAINL field. */ #define PDM_GAINL_GAINL_Msk (0x7FUL << PDM_GAINL_GAINL_Pos) /*!< Bit mask of GAINL field. */ -#define PDM_GAINL_GAINL_MinGain (0x00UL) /*!< -20dB gain adjustment (minimum) */ -#define PDM_GAINL_GAINL_DefaultGain (0x28UL) /*!< 0dB gain adjustment */ -#define PDM_GAINL_GAINL_MaxGain (0x50UL) /*!< +20dB gain adjustment (maximum) */ +#define PDM_GAINL_GAINL_MinGain (0x00UL) /*!< -20 dB gain adjustment (minimum) */ +#define PDM_GAINL_GAINL_DefaultGain (0x28UL) /*!< 0 dB gain adjustment */ +#define PDM_GAINL_GAINL_MaxGain (0x50UL) /*!< +20 dB gain adjustment (maximum) */ /* Register: PDM_GAINR */ /* Description: Right output gain adjustment */ @@ -6951,9 +6979,9 @@ POSSIBILITY OF SUCH DAMAGE. /* Bits 6..0 : Right output gain adjustment, in 0.5 dB steps, around the default module gain (see electrical parameters) */ #define PDM_GAINR_GAINR_Pos (0UL) /*!< Position of GAINR field. */ #define PDM_GAINR_GAINR_Msk (0x7FUL << PDM_GAINR_GAINR_Pos) /*!< Bit mask of GAINR field. */ -#define PDM_GAINR_GAINR_MinGain (0x00UL) /*!< -20dB gain adjustment (minimum) */ -#define PDM_GAINR_GAINR_DefaultGain (0x28UL) /*!< 0dB gain adjustment */ -#define PDM_GAINR_GAINR_MaxGain (0x50UL) /*!< +20dB gain adjustment (maximum) */ +#define PDM_GAINR_GAINR_MinGain (0x00UL) /*!< -20 dB gain adjustment (minimum) */ +#define PDM_GAINR_GAINR_DefaultGain (0x28UL) /*!< 0 dB gain adjustment */ +#define PDM_GAINR_GAINR_MaxGain (0x50UL) /*!< +20 dB gain adjustment (maximum) */ /* Register: PDM_RATIO */ /* Description: Selects the ratio between PDM_CLK and output sample rate. Change PDMCLKCTRL accordingly. */ @@ -8108,224 +8136,224 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: PPI_CHENSET */ /* Description: Channel enable set register */ -/* Bit 31 : Channel 31 enable set register. Writing '0' has no effect */ +/* Bit 31 : Channel 31 enable set register. Writing '0' has no effect. */ #define PPI_CHENSET_CH31_Pos (31UL) /*!< Position of CH31 field. */ #define PPI_CHENSET_CH31_Msk (0x1UL << PPI_CHENSET_CH31_Pos) /*!< Bit mask of CH31 field. */ #define PPI_CHENSET_CH31_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENSET_CH31_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENSET_CH31_Set (1UL) /*!< Write: Enable channel */ -/* Bit 30 : Channel 30 enable set register. Writing '0' has no effect */ +/* Bit 30 : Channel 30 enable set register. Writing '0' has no effect. */ #define PPI_CHENSET_CH30_Pos (30UL) /*!< Position of CH30 field. */ #define PPI_CHENSET_CH30_Msk (0x1UL << PPI_CHENSET_CH30_Pos) /*!< Bit mask of CH30 field. */ #define PPI_CHENSET_CH30_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENSET_CH30_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENSET_CH30_Set (1UL) /*!< Write: Enable channel */ -/* Bit 29 : Channel 29 enable set register. Writing '0' has no effect */ +/* Bit 29 : Channel 29 enable set register. Writing '0' has no effect. */ #define PPI_CHENSET_CH29_Pos (29UL) /*!< Position of CH29 field. */ #define PPI_CHENSET_CH29_Msk (0x1UL << PPI_CHENSET_CH29_Pos) /*!< Bit mask of CH29 field. */ #define PPI_CHENSET_CH29_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENSET_CH29_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENSET_CH29_Set (1UL) /*!< Write: Enable channel */ -/* Bit 28 : Channel 28 enable set register. Writing '0' has no effect */ +/* Bit 28 : Channel 28 enable set register. Writing '0' has no effect. */ #define PPI_CHENSET_CH28_Pos (28UL) /*!< Position of CH28 field. */ #define PPI_CHENSET_CH28_Msk (0x1UL << PPI_CHENSET_CH28_Pos) /*!< Bit mask of CH28 field. */ #define PPI_CHENSET_CH28_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENSET_CH28_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENSET_CH28_Set (1UL) /*!< Write: Enable channel */ -/* Bit 27 : Channel 27 enable set register. Writing '0' has no effect */ +/* Bit 27 : Channel 27 enable set register. Writing '0' has no effect. */ #define PPI_CHENSET_CH27_Pos (27UL) /*!< Position of CH27 field. */ #define PPI_CHENSET_CH27_Msk (0x1UL << PPI_CHENSET_CH27_Pos) /*!< Bit mask of CH27 field. */ #define PPI_CHENSET_CH27_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENSET_CH27_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENSET_CH27_Set (1UL) /*!< Write: Enable channel */ -/* Bit 26 : Channel 26 enable set register. Writing '0' has no effect */ +/* Bit 26 : Channel 26 enable set register. Writing '0' has no effect. */ #define PPI_CHENSET_CH26_Pos (26UL) /*!< Position of CH26 field. */ #define PPI_CHENSET_CH26_Msk (0x1UL << PPI_CHENSET_CH26_Pos) /*!< Bit mask of CH26 field. */ #define PPI_CHENSET_CH26_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENSET_CH26_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENSET_CH26_Set (1UL) /*!< Write: Enable channel */ -/* Bit 25 : Channel 25 enable set register. Writing '0' has no effect */ +/* Bit 25 : Channel 25 enable set register. Writing '0' has no effect. */ #define PPI_CHENSET_CH25_Pos (25UL) /*!< Position of CH25 field. */ #define PPI_CHENSET_CH25_Msk (0x1UL << PPI_CHENSET_CH25_Pos) /*!< Bit mask of CH25 field. */ #define PPI_CHENSET_CH25_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENSET_CH25_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENSET_CH25_Set (1UL) /*!< Write: Enable channel */ -/* Bit 24 : Channel 24 enable set register. Writing '0' has no effect */ +/* Bit 24 : Channel 24 enable set register. Writing '0' has no effect. */ #define PPI_CHENSET_CH24_Pos (24UL) /*!< Position of CH24 field. */ #define PPI_CHENSET_CH24_Msk (0x1UL << PPI_CHENSET_CH24_Pos) /*!< Bit mask of CH24 field. */ #define PPI_CHENSET_CH24_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENSET_CH24_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENSET_CH24_Set (1UL) /*!< Write: Enable channel */ -/* Bit 23 : Channel 23 enable set register. Writing '0' has no effect */ +/* Bit 23 : Channel 23 enable set register. Writing '0' has no effect. */ #define PPI_CHENSET_CH23_Pos (23UL) /*!< Position of CH23 field. */ #define PPI_CHENSET_CH23_Msk (0x1UL << PPI_CHENSET_CH23_Pos) /*!< Bit mask of CH23 field. */ #define PPI_CHENSET_CH23_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENSET_CH23_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENSET_CH23_Set (1UL) /*!< Write: Enable channel */ -/* Bit 22 : Channel 22 enable set register. Writing '0' has no effect */ +/* Bit 22 : Channel 22 enable set register. Writing '0' has no effect. */ #define PPI_CHENSET_CH22_Pos (22UL) /*!< Position of CH22 field. */ #define PPI_CHENSET_CH22_Msk (0x1UL << PPI_CHENSET_CH22_Pos) /*!< Bit mask of CH22 field. */ #define PPI_CHENSET_CH22_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENSET_CH22_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENSET_CH22_Set (1UL) /*!< Write: Enable channel */ -/* Bit 21 : Channel 21 enable set register. Writing '0' has no effect */ +/* Bit 21 : Channel 21 enable set register. Writing '0' has no effect. */ #define PPI_CHENSET_CH21_Pos (21UL) /*!< Position of CH21 field. */ #define PPI_CHENSET_CH21_Msk (0x1UL << PPI_CHENSET_CH21_Pos) /*!< Bit mask of CH21 field. */ #define PPI_CHENSET_CH21_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENSET_CH21_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENSET_CH21_Set (1UL) /*!< Write: Enable channel */ -/* Bit 20 : Channel 20 enable set register. Writing '0' has no effect */ +/* Bit 20 : Channel 20 enable set register. Writing '0' has no effect. */ #define PPI_CHENSET_CH20_Pos (20UL) /*!< Position of CH20 field. */ #define PPI_CHENSET_CH20_Msk (0x1UL << PPI_CHENSET_CH20_Pos) /*!< Bit mask of CH20 field. */ #define PPI_CHENSET_CH20_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENSET_CH20_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENSET_CH20_Set (1UL) /*!< Write: Enable channel */ -/* Bit 19 : Channel 19 enable set register. Writing '0' has no effect */ +/* Bit 19 : Channel 19 enable set register. Writing '0' has no effect. */ #define PPI_CHENSET_CH19_Pos (19UL) /*!< Position of CH19 field. */ #define PPI_CHENSET_CH19_Msk (0x1UL << PPI_CHENSET_CH19_Pos) /*!< Bit mask of CH19 field. */ #define PPI_CHENSET_CH19_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENSET_CH19_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENSET_CH19_Set (1UL) /*!< Write: Enable channel */ -/* Bit 18 : Channel 18 enable set register. Writing '0' has no effect */ +/* Bit 18 : Channel 18 enable set register. Writing '0' has no effect. */ #define PPI_CHENSET_CH18_Pos (18UL) /*!< Position of CH18 field. */ #define PPI_CHENSET_CH18_Msk (0x1UL << PPI_CHENSET_CH18_Pos) /*!< Bit mask of CH18 field. */ #define PPI_CHENSET_CH18_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENSET_CH18_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENSET_CH18_Set (1UL) /*!< Write: Enable channel */ -/* Bit 17 : Channel 17 enable set register. Writing '0' has no effect */ +/* Bit 17 : Channel 17 enable set register. Writing '0' has no effect. */ #define PPI_CHENSET_CH17_Pos (17UL) /*!< Position of CH17 field. */ #define PPI_CHENSET_CH17_Msk (0x1UL << PPI_CHENSET_CH17_Pos) /*!< Bit mask of CH17 field. */ #define PPI_CHENSET_CH17_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENSET_CH17_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENSET_CH17_Set (1UL) /*!< Write: Enable channel */ -/* Bit 16 : Channel 16 enable set register. Writing '0' has no effect */ +/* Bit 16 : Channel 16 enable set register. Writing '0' has no effect. */ #define PPI_CHENSET_CH16_Pos (16UL) /*!< Position of CH16 field. */ #define PPI_CHENSET_CH16_Msk (0x1UL << PPI_CHENSET_CH16_Pos) /*!< Bit mask of CH16 field. */ #define PPI_CHENSET_CH16_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENSET_CH16_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENSET_CH16_Set (1UL) /*!< Write: Enable channel */ -/* Bit 15 : Channel 15 enable set register. Writing '0' has no effect */ +/* Bit 15 : Channel 15 enable set register. Writing '0' has no effect. */ #define PPI_CHENSET_CH15_Pos (15UL) /*!< Position of CH15 field. */ #define PPI_CHENSET_CH15_Msk (0x1UL << PPI_CHENSET_CH15_Pos) /*!< Bit mask of CH15 field. */ #define PPI_CHENSET_CH15_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENSET_CH15_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENSET_CH15_Set (1UL) /*!< Write: Enable channel */ -/* Bit 14 : Channel 14 enable set register. Writing '0' has no effect */ +/* Bit 14 : Channel 14 enable set register. Writing '0' has no effect. */ #define PPI_CHENSET_CH14_Pos (14UL) /*!< Position of CH14 field. */ #define PPI_CHENSET_CH14_Msk (0x1UL << PPI_CHENSET_CH14_Pos) /*!< Bit mask of CH14 field. */ #define PPI_CHENSET_CH14_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENSET_CH14_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENSET_CH14_Set (1UL) /*!< Write: Enable channel */ -/* Bit 13 : Channel 13 enable set register. Writing '0' has no effect */ +/* Bit 13 : Channel 13 enable set register. Writing '0' has no effect. */ #define PPI_CHENSET_CH13_Pos (13UL) /*!< Position of CH13 field. */ #define PPI_CHENSET_CH13_Msk (0x1UL << PPI_CHENSET_CH13_Pos) /*!< Bit mask of CH13 field. */ #define PPI_CHENSET_CH13_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENSET_CH13_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENSET_CH13_Set (1UL) /*!< Write: Enable channel */ -/* Bit 12 : Channel 12 enable set register. Writing '0' has no effect */ +/* Bit 12 : Channel 12 enable set register. Writing '0' has no effect. */ #define PPI_CHENSET_CH12_Pos (12UL) /*!< Position of CH12 field. */ #define PPI_CHENSET_CH12_Msk (0x1UL << PPI_CHENSET_CH12_Pos) /*!< Bit mask of CH12 field. */ #define PPI_CHENSET_CH12_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENSET_CH12_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENSET_CH12_Set (1UL) /*!< Write: Enable channel */ -/* Bit 11 : Channel 11 enable set register. Writing '0' has no effect */ +/* Bit 11 : Channel 11 enable set register. Writing '0' has no effect. */ #define PPI_CHENSET_CH11_Pos (11UL) /*!< Position of CH11 field. */ #define PPI_CHENSET_CH11_Msk (0x1UL << PPI_CHENSET_CH11_Pos) /*!< Bit mask of CH11 field. */ #define PPI_CHENSET_CH11_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENSET_CH11_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENSET_CH11_Set (1UL) /*!< Write: Enable channel */ -/* Bit 10 : Channel 10 enable set register. Writing '0' has no effect */ +/* Bit 10 : Channel 10 enable set register. Writing '0' has no effect. */ #define PPI_CHENSET_CH10_Pos (10UL) /*!< Position of CH10 field. */ #define PPI_CHENSET_CH10_Msk (0x1UL << PPI_CHENSET_CH10_Pos) /*!< Bit mask of CH10 field. */ #define PPI_CHENSET_CH10_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENSET_CH10_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENSET_CH10_Set (1UL) /*!< Write: Enable channel */ -/* Bit 9 : Channel 9 enable set register. Writing '0' has no effect */ +/* Bit 9 : Channel 9 enable set register. Writing '0' has no effect. */ #define PPI_CHENSET_CH9_Pos (9UL) /*!< Position of CH9 field. */ #define PPI_CHENSET_CH9_Msk (0x1UL << PPI_CHENSET_CH9_Pos) /*!< Bit mask of CH9 field. */ #define PPI_CHENSET_CH9_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENSET_CH9_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENSET_CH9_Set (1UL) /*!< Write: Enable channel */ -/* Bit 8 : Channel 8 enable set register. Writing '0' has no effect */ +/* Bit 8 : Channel 8 enable set register. Writing '0' has no effect. */ #define PPI_CHENSET_CH8_Pos (8UL) /*!< Position of CH8 field. */ #define PPI_CHENSET_CH8_Msk (0x1UL << PPI_CHENSET_CH8_Pos) /*!< Bit mask of CH8 field. */ #define PPI_CHENSET_CH8_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENSET_CH8_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENSET_CH8_Set (1UL) /*!< Write: Enable channel */ -/* Bit 7 : Channel 7 enable set register. Writing '0' has no effect */ +/* Bit 7 : Channel 7 enable set register. Writing '0' has no effect. */ #define PPI_CHENSET_CH7_Pos (7UL) /*!< Position of CH7 field. */ #define PPI_CHENSET_CH7_Msk (0x1UL << PPI_CHENSET_CH7_Pos) /*!< Bit mask of CH7 field. */ #define PPI_CHENSET_CH7_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENSET_CH7_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENSET_CH7_Set (1UL) /*!< Write: Enable channel */ -/* Bit 6 : Channel 6 enable set register. Writing '0' has no effect */ +/* Bit 6 : Channel 6 enable set register. Writing '0' has no effect. */ #define PPI_CHENSET_CH6_Pos (6UL) /*!< Position of CH6 field. */ #define PPI_CHENSET_CH6_Msk (0x1UL << PPI_CHENSET_CH6_Pos) /*!< Bit mask of CH6 field. */ #define PPI_CHENSET_CH6_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENSET_CH6_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENSET_CH6_Set (1UL) /*!< Write: Enable channel */ -/* Bit 5 : Channel 5 enable set register. Writing '0' has no effect */ +/* Bit 5 : Channel 5 enable set register. Writing '0' has no effect. */ #define PPI_CHENSET_CH5_Pos (5UL) /*!< Position of CH5 field. */ #define PPI_CHENSET_CH5_Msk (0x1UL << PPI_CHENSET_CH5_Pos) /*!< Bit mask of CH5 field. */ #define PPI_CHENSET_CH5_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENSET_CH5_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENSET_CH5_Set (1UL) /*!< Write: Enable channel */ -/* Bit 4 : Channel 4 enable set register. Writing '0' has no effect */ +/* Bit 4 : Channel 4 enable set register. Writing '0' has no effect. */ #define PPI_CHENSET_CH4_Pos (4UL) /*!< Position of CH4 field. */ #define PPI_CHENSET_CH4_Msk (0x1UL << PPI_CHENSET_CH4_Pos) /*!< Bit mask of CH4 field. */ #define PPI_CHENSET_CH4_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENSET_CH4_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENSET_CH4_Set (1UL) /*!< Write: Enable channel */ -/* Bit 3 : Channel 3 enable set register. Writing '0' has no effect */ +/* Bit 3 : Channel 3 enable set register. Writing '0' has no effect. */ #define PPI_CHENSET_CH3_Pos (3UL) /*!< Position of CH3 field. */ #define PPI_CHENSET_CH3_Msk (0x1UL << PPI_CHENSET_CH3_Pos) /*!< Bit mask of CH3 field. */ #define PPI_CHENSET_CH3_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENSET_CH3_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENSET_CH3_Set (1UL) /*!< Write: Enable channel */ -/* Bit 2 : Channel 2 enable set register. Writing '0' has no effect */ +/* Bit 2 : Channel 2 enable set register. Writing '0' has no effect. */ #define PPI_CHENSET_CH2_Pos (2UL) /*!< Position of CH2 field. */ #define PPI_CHENSET_CH2_Msk (0x1UL << PPI_CHENSET_CH2_Pos) /*!< Bit mask of CH2 field. */ #define PPI_CHENSET_CH2_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENSET_CH2_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENSET_CH2_Set (1UL) /*!< Write: Enable channel */ -/* Bit 1 : Channel 1 enable set register. Writing '0' has no effect */ +/* Bit 1 : Channel 1 enable set register. Writing '0' has no effect. */ #define PPI_CHENSET_CH1_Pos (1UL) /*!< Position of CH1 field. */ #define PPI_CHENSET_CH1_Msk (0x1UL << PPI_CHENSET_CH1_Pos) /*!< Bit mask of CH1 field. */ #define PPI_CHENSET_CH1_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENSET_CH1_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENSET_CH1_Set (1UL) /*!< Write: Enable channel */ -/* Bit 0 : Channel 0 enable set register. Writing '0' has no effect */ +/* Bit 0 : Channel 0 enable set register. Writing '0' has no effect. */ #define PPI_CHENSET_CH0_Pos (0UL) /*!< Position of CH0 field. */ #define PPI_CHENSET_CH0_Msk (0x1UL << PPI_CHENSET_CH0_Pos) /*!< Bit mask of CH0 field. */ #define PPI_CHENSET_CH0_Disabled (0UL) /*!< Read: channel disabled */ @@ -8335,224 +8363,224 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: PPI_CHENCLR */ /* Description: Channel enable clear register */ -/* Bit 31 : Channel 31 enable clear register. Writing '0' has no effect */ +/* Bit 31 : Channel 31 enable clear register. Writing '0' has no effect. */ #define PPI_CHENCLR_CH31_Pos (31UL) /*!< Position of CH31 field. */ #define PPI_CHENCLR_CH31_Msk (0x1UL << PPI_CHENCLR_CH31_Pos) /*!< Bit mask of CH31 field. */ #define PPI_CHENCLR_CH31_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENCLR_CH31_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENCLR_CH31_Clear (1UL) /*!< Write: disable channel */ -/* Bit 30 : Channel 30 enable clear register. Writing '0' has no effect */ +/* Bit 30 : Channel 30 enable clear register. Writing '0' has no effect. */ #define PPI_CHENCLR_CH30_Pos (30UL) /*!< Position of CH30 field. */ #define PPI_CHENCLR_CH30_Msk (0x1UL << PPI_CHENCLR_CH30_Pos) /*!< Bit mask of CH30 field. */ #define PPI_CHENCLR_CH30_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENCLR_CH30_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENCLR_CH30_Clear (1UL) /*!< Write: disable channel */ -/* Bit 29 : Channel 29 enable clear register. Writing '0' has no effect */ +/* Bit 29 : Channel 29 enable clear register. Writing '0' has no effect. */ #define PPI_CHENCLR_CH29_Pos (29UL) /*!< Position of CH29 field. */ #define PPI_CHENCLR_CH29_Msk (0x1UL << PPI_CHENCLR_CH29_Pos) /*!< Bit mask of CH29 field. */ #define PPI_CHENCLR_CH29_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENCLR_CH29_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENCLR_CH29_Clear (1UL) /*!< Write: disable channel */ -/* Bit 28 : Channel 28 enable clear register. Writing '0' has no effect */ +/* Bit 28 : Channel 28 enable clear register. Writing '0' has no effect. */ #define PPI_CHENCLR_CH28_Pos (28UL) /*!< Position of CH28 field. */ #define PPI_CHENCLR_CH28_Msk (0x1UL << PPI_CHENCLR_CH28_Pos) /*!< Bit mask of CH28 field. */ #define PPI_CHENCLR_CH28_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENCLR_CH28_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENCLR_CH28_Clear (1UL) /*!< Write: disable channel */ -/* Bit 27 : Channel 27 enable clear register. Writing '0' has no effect */ +/* Bit 27 : Channel 27 enable clear register. Writing '0' has no effect. */ #define PPI_CHENCLR_CH27_Pos (27UL) /*!< Position of CH27 field. */ #define PPI_CHENCLR_CH27_Msk (0x1UL << PPI_CHENCLR_CH27_Pos) /*!< Bit mask of CH27 field. */ #define PPI_CHENCLR_CH27_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENCLR_CH27_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENCLR_CH27_Clear (1UL) /*!< Write: disable channel */ -/* Bit 26 : Channel 26 enable clear register. Writing '0' has no effect */ +/* Bit 26 : Channel 26 enable clear register. Writing '0' has no effect. */ #define PPI_CHENCLR_CH26_Pos (26UL) /*!< Position of CH26 field. */ #define PPI_CHENCLR_CH26_Msk (0x1UL << PPI_CHENCLR_CH26_Pos) /*!< Bit mask of CH26 field. */ #define PPI_CHENCLR_CH26_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENCLR_CH26_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENCLR_CH26_Clear (1UL) /*!< Write: disable channel */ -/* Bit 25 : Channel 25 enable clear register. Writing '0' has no effect */ +/* Bit 25 : Channel 25 enable clear register. Writing '0' has no effect. */ #define PPI_CHENCLR_CH25_Pos (25UL) /*!< Position of CH25 field. */ #define PPI_CHENCLR_CH25_Msk (0x1UL << PPI_CHENCLR_CH25_Pos) /*!< Bit mask of CH25 field. */ #define PPI_CHENCLR_CH25_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENCLR_CH25_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENCLR_CH25_Clear (1UL) /*!< Write: disable channel */ -/* Bit 24 : Channel 24 enable clear register. Writing '0' has no effect */ +/* Bit 24 : Channel 24 enable clear register. Writing '0' has no effect. */ #define PPI_CHENCLR_CH24_Pos (24UL) /*!< Position of CH24 field. */ #define PPI_CHENCLR_CH24_Msk (0x1UL << PPI_CHENCLR_CH24_Pos) /*!< Bit mask of CH24 field. */ #define PPI_CHENCLR_CH24_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENCLR_CH24_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENCLR_CH24_Clear (1UL) /*!< Write: disable channel */ -/* Bit 23 : Channel 23 enable clear register. Writing '0' has no effect */ +/* Bit 23 : Channel 23 enable clear register. Writing '0' has no effect. */ #define PPI_CHENCLR_CH23_Pos (23UL) /*!< Position of CH23 field. */ #define PPI_CHENCLR_CH23_Msk (0x1UL << PPI_CHENCLR_CH23_Pos) /*!< Bit mask of CH23 field. */ #define PPI_CHENCLR_CH23_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENCLR_CH23_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENCLR_CH23_Clear (1UL) /*!< Write: disable channel */ -/* Bit 22 : Channel 22 enable clear register. Writing '0' has no effect */ +/* Bit 22 : Channel 22 enable clear register. Writing '0' has no effect. */ #define PPI_CHENCLR_CH22_Pos (22UL) /*!< Position of CH22 field. */ #define PPI_CHENCLR_CH22_Msk (0x1UL << PPI_CHENCLR_CH22_Pos) /*!< Bit mask of CH22 field. */ #define PPI_CHENCLR_CH22_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENCLR_CH22_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENCLR_CH22_Clear (1UL) /*!< Write: disable channel */ -/* Bit 21 : Channel 21 enable clear register. Writing '0' has no effect */ +/* Bit 21 : Channel 21 enable clear register. Writing '0' has no effect. */ #define PPI_CHENCLR_CH21_Pos (21UL) /*!< Position of CH21 field. */ #define PPI_CHENCLR_CH21_Msk (0x1UL << PPI_CHENCLR_CH21_Pos) /*!< Bit mask of CH21 field. */ #define PPI_CHENCLR_CH21_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENCLR_CH21_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENCLR_CH21_Clear (1UL) /*!< Write: disable channel */ -/* Bit 20 : Channel 20 enable clear register. Writing '0' has no effect */ +/* Bit 20 : Channel 20 enable clear register. Writing '0' has no effect. */ #define PPI_CHENCLR_CH20_Pos (20UL) /*!< Position of CH20 field. */ #define PPI_CHENCLR_CH20_Msk (0x1UL << PPI_CHENCLR_CH20_Pos) /*!< Bit mask of CH20 field. */ #define PPI_CHENCLR_CH20_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENCLR_CH20_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENCLR_CH20_Clear (1UL) /*!< Write: disable channel */ -/* Bit 19 : Channel 19 enable clear register. Writing '0' has no effect */ +/* Bit 19 : Channel 19 enable clear register. Writing '0' has no effect. */ #define PPI_CHENCLR_CH19_Pos (19UL) /*!< Position of CH19 field. */ #define PPI_CHENCLR_CH19_Msk (0x1UL << PPI_CHENCLR_CH19_Pos) /*!< Bit mask of CH19 field. */ #define PPI_CHENCLR_CH19_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENCLR_CH19_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENCLR_CH19_Clear (1UL) /*!< Write: disable channel */ -/* Bit 18 : Channel 18 enable clear register. Writing '0' has no effect */ +/* Bit 18 : Channel 18 enable clear register. Writing '0' has no effect. */ #define PPI_CHENCLR_CH18_Pos (18UL) /*!< Position of CH18 field. */ #define PPI_CHENCLR_CH18_Msk (0x1UL << PPI_CHENCLR_CH18_Pos) /*!< Bit mask of CH18 field. */ #define PPI_CHENCLR_CH18_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENCLR_CH18_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENCLR_CH18_Clear (1UL) /*!< Write: disable channel */ -/* Bit 17 : Channel 17 enable clear register. Writing '0' has no effect */ +/* Bit 17 : Channel 17 enable clear register. Writing '0' has no effect. */ #define PPI_CHENCLR_CH17_Pos (17UL) /*!< Position of CH17 field. */ #define PPI_CHENCLR_CH17_Msk (0x1UL << PPI_CHENCLR_CH17_Pos) /*!< Bit mask of CH17 field. */ #define PPI_CHENCLR_CH17_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENCLR_CH17_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENCLR_CH17_Clear (1UL) /*!< Write: disable channel */ -/* Bit 16 : Channel 16 enable clear register. Writing '0' has no effect */ +/* Bit 16 : Channel 16 enable clear register. Writing '0' has no effect. */ #define PPI_CHENCLR_CH16_Pos (16UL) /*!< Position of CH16 field. */ #define PPI_CHENCLR_CH16_Msk (0x1UL << PPI_CHENCLR_CH16_Pos) /*!< Bit mask of CH16 field. */ #define PPI_CHENCLR_CH16_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENCLR_CH16_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENCLR_CH16_Clear (1UL) /*!< Write: disable channel */ -/* Bit 15 : Channel 15 enable clear register. Writing '0' has no effect */ +/* Bit 15 : Channel 15 enable clear register. Writing '0' has no effect. */ #define PPI_CHENCLR_CH15_Pos (15UL) /*!< Position of CH15 field. */ #define PPI_CHENCLR_CH15_Msk (0x1UL << PPI_CHENCLR_CH15_Pos) /*!< Bit mask of CH15 field. */ #define PPI_CHENCLR_CH15_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENCLR_CH15_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENCLR_CH15_Clear (1UL) /*!< Write: disable channel */ -/* Bit 14 : Channel 14 enable clear register. Writing '0' has no effect */ +/* Bit 14 : Channel 14 enable clear register. Writing '0' has no effect. */ #define PPI_CHENCLR_CH14_Pos (14UL) /*!< Position of CH14 field. */ #define PPI_CHENCLR_CH14_Msk (0x1UL << PPI_CHENCLR_CH14_Pos) /*!< Bit mask of CH14 field. */ #define PPI_CHENCLR_CH14_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENCLR_CH14_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENCLR_CH14_Clear (1UL) /*!< Write: disable channel */ -/* Bit 13 : Channel 13 enable clear register. Writing '0' has no effect */ +/* Bit 13 : Channel 13 enable clear register. Writing '0' has no effect. */ #define PPI_CHENCLR_CH13_Pos (13UL) /*!< Position of CH13 field. */ #define PPI_CHENCLR_CH13_Msk (0x1UL << PPI_CHENCLR_CH13_Pos) /*!< Bit mask of CH13 field. */ #define PPI_CHENCLR_CH13_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENCLR_CH13_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENCLR_CH13_Clear (1UL) /*!< Write: disable channel */ -/* Bit 12 : Channel 12 enable clear register. Writing '0' has no effect */ +/* Bit 12 : Channel 12 enable clear register. Writing '0' has no effect. */ #define PPI_CHENCLR_CH12_Pos (12UL) /*!< Position of CH12 field. */ #define PPI_CHENCLR_CH12_Msk (0x1UL << PPI_CHENCLR_CH12_Pos) /*!< Bit mask of CH12 field. */ #define PPI_CHENCLR_CH12_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENCLR_CH12_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENCLR_CH12_Clear (1UL) /*!< Write: disable channel */ -/* Bit 11 : Channel 11 enable clear register. Writing '0' has no effect */ +/* Bit 11 : Channel 11 enable clear register. Writing '0' has no effect. */ #define PPI_CHENCLR_CH11_Pos (11UL) /*!< Position of CH11 field. */ #define PPI_CHENCLR_CH11_Msk (0x1UL << PPI_CHENCLR_CH11_Pos) /*!< Bit mask of CH11 field. */ #define PPI_CHENCLR_CH11_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENCLR_CH11_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENCLR_CH11_Clear (1UL) /*!< Write: disable channel */ -/* Bit 10 : Channel 10 enable clear register. Writing '0' has no effect */ +/* Bit 10 : Channel 10 enable clear register. Writing '0' has no effect. */ #define PPI_CHENCLR_CH10_Pos (10UL) /*!< Position of CH10 field. */ #define PPI_CHENCLR_CH10_Msk (0x1UL << PPI_CHENCLR_CH10_Pos) /*!< Bit mask of CH10 field. */ #define PPI_CHENCLR_CH10_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENCLR_CH10_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENCLR_CH10_Clear (1UL) /*!< Write: disable channel */ -/* Bit 9 : Channel 9 enable clear register. Writing '0' has no effect */ +/* Bit 9 : Channel 9 enable clear register. Writing '0' has no effect. */ #define PPI_CHENCLR_CH9_Pos (9UL) /*!< Position of CH9 field. */ #define PPI_CHENCLR_CH9_Msk (0x1UL << PPI_CHENCLR_CH9_Pos) /*!< Bit mask of CH9 field. */ #define PPI_CHENCLR_CH9_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENCLR_CH9_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENCLR_CH9_Clear (1UL) /*!< Write: disable channel */ -/* Bit 8 : Channel 8 enable clear register. Writing '0' has no effect */ +/* Bit 8 : Channel 8 enable clear register. Writing '0' has no effect. */ #define PPI_CHENCLR_CH8_Pos (8UL) /*!< Position of CH8 field. */ #define PPI_CHENCLR_CH8_Msk (0x1UL << PPI_CHENCLR_CH8_Pos) /*!< Bit mask of CH8 field. */ #define PPI_CHENCLR_CH8_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENCLR_CH8_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENCLR_CH8_Clear (1UL) /*!< Write: disable channel */ -/* Bit 7 : Channel 7 enable clear register. Writing '0' has no effect */ +/* Bit 7 : Channel 7 enable clear register. Writing '0' has no effect. */ #define PPI_CHENCLR_CH7_Pos (7UL) /*!< Position of CH7 field. */ #define PPI_CHENCLR_CH7_Msk (0x1UL << PPI_CHENCLR_CH7_Pos) /*!< Bit mask of CH7 field. */ #define PPI_CHENCLR_CH7_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENCLR_CH7_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENCLR_CH7_Clear (1UL) /*!< Write: disable channel */ -/* Bit 6 : Channel 6 enable clear register. Writing '0' has no effect */ +/* Bit 6 : Channel 6 enable clear register. Writing '0' has no effect. */ #define PPI_CHENCLR_CH6_Pos (6UL) /*!< Position of CH6 field. */ #define PPI_CHENCLR_CH6_Msk (0x1UL << PPI_CHENCLR_CH6_Pos) /*!< Bit mask of CH6 field. */ #define PPI_CHENCLR_CH6_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENCLR_CH6_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENCLR_CH6_Clear (1UL) /*!< Write: disable channel */ -/* Bit 5 : Channel 5 enable clear register. Writing '0' has no effect */ +/* Bit 5 : Channel 5 enable clear register. Writing '0' has no effect. */ #define PPI_CHENCLR_CH5_Pos (5UL) /*!< Position of CH5 field. */ #define PPI_CHENCLR_CH5_Msk (0x1UL << PPI_CHENCLR_CH5_Pos) /*!< Bit mask of CH5 field. */ #define PPI_CHENCLR_CH5_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENCLR_CH5_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENCLR_CH5_Clear (1UL) /*!< Write: disable channel */ -/* Bit 4 : Channel 4 enable clear register. Writing '0' has no effect */ +/* Bit 4 : Channel 4 enable clear register. Writing '0' has no effect. */ #define PPI_CHENCLR_CH4_Pos (4UL) /*!< Position of CH4 field. */ #define PPI_CHENCLR_CH4_Msk (0x1UL << PPI_CHENCLR_CH4_Pos) /*!< Bit mask of CH4 field. */ #define PPI_CHENCLR_CH4_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENCLR_CH4_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENCLR_CH4_Clear (1UL) /*!< Write: disable channel */ -/* Bit 3 : Channel 3 enable clear register. Writing '0' has no effect */ +/* Bit 3 : Channel 3 enable clear register. Writing '0' has no effect. */ #define PPI_CHENCLR_CH3_Pos (3UL) /*!< Position of CH3 field. */ #define PPI_CHENCLR_CH3_Msk (0x1UL << PPI_CHENCLR_CH3_Pos) /*!< Bit mask of CH3 field. */ #define PPI_CHENCLR_CH3_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENCLR_CH3_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENCLR_CH3_Clear (1UL) /*!< Write: disable channel */ -/* Bit 2 : Channel 2 enable clear register. Writing '0' has no effect */ +/* Bit 2 : Channel 2 enable clear register. Writing '0' has no effect. */ #define PPI_CHENCLR_CH2_Pos (2UL) /*!< Position of CH2 field. */ #define PPI_CHENCLR_CH2_Msk (0x1UL << PPI_CHENCLR_CH2_Pos) /*!< Bit mask of CH2 field. */ #define PPI_CHENCLR_CH2_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENCLR_CH2_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENCLR_CH2_Clear (1UL) /*!< Write: disable channel */ -/* Bit 1 : Channel 1 enable clear register. Writing '0' has no effect */ +/* Bit 1 : Channel 1 enable clear register. Writing '0' has no effect. */ #define PPI_CHENCLR_CH1_Pos (1UL) /*!< Position of CH1 field. */ #define PPI_CHENCLR_CH1_Msk (0x1UL << PPI_CHENCLR_CH1_Pos) /*!< Bit mask of CH1 field. */ #define PPI_CHENCLR_CH1_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENCLR_CH1_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENCLR_CH1_Clear (1UL) /*!< Write: disable channel */ -/* Bit 0 : Channel 0 enable clear register. Writing '0' has no effect */ +/* Bit 0 : Channel 0 enable clear register. Writing '0' has no effect. */ #define PPI_CHENCLR_CH0_Pos (0UL) /*!< Position of CH0 field. */ #define PPI_CHENCLR_CH0_Msk (0x1UL << PPI_CHENCLR_CH0_Pos) /*!< Bit mask of CH0 field. */ #define PPI_CHENCLR_CH0_Disabled (0UL) /*!< Read: channel disabled */ @@ -8560,14 +8588,14 @@ POSSIBILITY OF SUCH DAMAGE. #define PPI_CHENCLR_CH0_Clear (1UL) /*!< Write: disable channel */ /* Register: PPI_CH_EEP */ -/* Description: Description cluster: Channel n event end-point */ +/* Description: Description cluster: Channel n event endpoint */ /* Bits 31..0 : Pointer to event register. Accepts only addresses to registers from the Event group. */ #define PPI_CH_EEP_EEP_Pos (0UL) /*!< Position of EEP field. */ #define PPI_CH_EEP_EEP_Msk (0xFFFFFFFFUL << PPI_CH_EEP_EEP_Pos) /*!< Bit mask of EEP field. */ /* Register: PPI_CH_TEP */ -/* Description: Description cluster: Channel n task end-point */ +/* Description: Description cluster: Channel n task endpoint */ /* Bits 31..0 : Pointer to task register. Accepts only addresses to registers from the Task group. */ #define PPI_CH_TEP_TEP_Pos (0UL) /*!< Position of TEP field. */ @@ -8769,7 +8797,7 @@ POSSIBILITY OF SUCH DAMAGE. #define PPI_CHG_CH0_Included (1UL) /*!< Include */ /* Register: PPI_FORK_TEP */ -/* Description: Description cluster: Channel n task end-point */ +/* Description: Description cluster: Channel n task endpoint */ /* Bits 31..0 : Pointer to task register */ #define PPI_FORK_TEP_TEP_Pos (0UL) /*!< Position of TEP field. */ @@ -9398,23 +9426,23 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: QDEC_REPORTPER */ /* Description: Number of samples to be taken before REPORTRDY and DBLRDY events can be generated */ -/* Bits 3..0 : Specifies the number of samples to be accumulated in the ACC register before the REPORTRDY and DBLRDY events can be generated */ +/* Bits 3..0 : Specifies the number of samples to be accumulated in the ACC register before the REPORTRDY and DBLRDY events can be generated. */ #define QDEC_REPORTPER_REPORTPER_Pos (0UL) /*!< Position of REPORTPER field. */ #define QDEC_REPORTPER_REPORTPER_Msk (0xFUL << QDEC_REPORTPER_REPORTPER_Pos) /*!< Bit mask of REPORTPER field. */ -#define QDEC_REPORTPER_REPORTPER_10Smpl (0UL) /*!< 10 samples / report */ -#define QDEC_REPORTPER_REPORTPER_40Smpl (1UL) /*!< 40 samples / report */ -#define QDEC_REPORTPER_REPORTPER_80Smpl (2UL) /*!< 80 samples / report */ -#define QDEC_REPORTPER_REPORTPER_120Smpl (3UL) /*!< 120 samples / report */ -#define QDEC_REPORTPER_REPORTPER_160Smpl (4UL) /*!< 160 samples / report */ -#define QDEC_REPORTPER_REPORTPER_200Smpl (5UL) /*!< 200 samples / report */ -#define QDEC_REPORTPER_REPORTPER_240Smpl (6UL) /*!< 240 samples / report */ -#define QDEC_REPORTPER_REPORTPER_280Smpl (7UL) /*!< 280 samples / report */ -#define QDEC_REPORTPER_REPORTPER_1Smpl (8UL) /*!< 1 sample / report */ +#define QDEC_REPORTPER_REPORTPER_10Smpl (0UL) /*!< 10 samples/report */ +#define QDEC_REPORTPER_REPORTPER_40Smpl (1UL) /*!< 40 samples/report */ +#define QDEC_REPORTPER_REPORTPER_80Smpl (2UL) /*!< 80 samples/report */ +#define QDEC_REPORTPER_REPORTPER_120Smpl (3UL) /*!< 120 samples/report */ +#define QDEC_REPORTPER_REPORTPER_160Smpl (4UL) /*!< 160 samples/report */ +#define QDEC_REPORTPER_REPORTPER_200Smpl (5UL) /*!< 200 samples/report */ +#define QDEC_REPORTPER_REPORTPER_240Smpl (6UL) /*!< 240 samples/report */ +#define QDEC_REPORTPER_REPORTPER_280Smpl (7UL) /*!< 280 samples/report */ +#define QDEC_REPORTPER_REPORTPER_1Smpl (8UL) /*!< 1 sample/report */ /* Register: QDEC_ACC */ /* Description: Register accumulating the valid transitions */ -/* Bits 31..0 : Register accumulating all valid samples (not double transition) read from the SAMPLE register */ +/* Bits 31..0 : Register accumulating all valid samples (not double transition) read from the SAMPLE register. */ #define QDEC_ACC_ACC_Pos (0UL) /*!< Position of ACC field. */ #define QDEC_ACC_ACC_Msk (0xFFFFFFFFUL << QDEC_ACC_ACC_Pos) /*!< Bit mask of ACC field. */ @@ -11649,7 +11677,7 @@ POSSIBILITY OF SUCH DAMAGE. #define RTC_COUNTER_COUNTER_Msk (0xFFFFFFUL << RTC_COUNTER_COUNTER_Pos) /*!< Bit mask of COUNTER field. */ /* Register: RTC_PRESCALER */ -/* Description: 12 bit prescaler for COUNTER frequency (32768/(PRESCALER+1)).Must be written when RTC is stopped */ +/* Description: 12 bit prescaler for COUNTER frequency (32768/(PRESCALER+1)). Must be written when RTC is stopped. */ /* Bits 11..0 : Prescaler value */ #define RTC_PRESCALER_PRESCALER_Pos (0UL) /*!< Position of PRESCALER field. */ @@ -12507,7 +12535,7 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: SPI_TXD */ /* Description: TXD register */ -/* Bits 7..0 : TX data to send. Double buffered */ +/* Bits 7..0 : TX data to send. Double buffered. */ #define SPI_TXD_TXD_Pos (0UL) /*!< Position of TXD field. */ #define SPI_TXD_TXD_Msk (0xFFUL << SPI_TXD_TXD_Pos) /*!< Bit mask of TXD field. */ @@ -12713,7 +12741,7 @@ POSSIBILITY OF SUCH DAMAGE. #define SPIM_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */ /* Register: SPIM_STALLSTAT */ -/* Description: Stall status for EasyDMA RAM accesses. The fields in this register is set to STALL by hardware whenever a stall occurres and can be cleared (set to NOSTALL) by the CPU. */ +/* Description: Stall status for EasyDMA RAM accesses. The fields in this register are set to STALL by hardware whenever a stall occurs and can be cleared (set to NOSTALL) by the CPU. */ /* Bit 1 : Stall status for EasyDMA RAM writes */ #define SPIM_STALLSTAT_RX_Pos (1UL) /*!< Position of RX field. */ @@ -13316,121 +13344,121 @@ POSSIBILITY OF SUCH DAMAGE. #define TEMP_TEMP_TEMP_Msk (0xFFFFFFFFUL << TEMP_TEMP_TEMP_Pos) /*!< Bit mask of TEMP field. */ /* Register: TEMP_A0 */ -/* Description: Slope of 1st piece wise linear function */ +/* Description: Slope of first piecewise linear function */ -/* Bits 11..0 : Slope of 1st piece wise linear function */ +/* Bits 11..0 : Slope of first piecewise linear function */ #define TEMP_A0_A0_Pos (0UL) /*!< Position of A0 field. */ #define TEMP_A0_A0_Msk (0xFFFUL << TEMP_A0_A0_Pos) /*!< Bit mask of A0 field. */ /* Register: TEMP_A1 */ -/* Description: Slope of 2nd piece wise linear function */ +/* Description: Slope of second piecewise linear function */ -/* Bits 11..0 : Slope of 2nd piece wise linear function */ +/* Bits 11..0 : Slope of second piecewise linear function */ #define TEMP_A1_A1_Pos (0UL) /*!< Position of A1 field. */ #define TEMP_A1_A1_Msk (0xFFFUL << TEMP_A1_A1_Pos) /*!< Bit mask of A1 field. */ /* Register: TEMP_A2 */ -/* Description: Slope of 3rd piece wise linear function */ +/* Description: Slope of third piecewise linear function */ -/* Bits 11..0 : Slope of 3rd piece wise linear function */ +/* Bits 11..0 : Slope of third piecewise linear function */ #define TEMP_A2_A2_Pos (0UL) /*!< Position of A2 field. */ #define TEMP_A2_A2_Msk (0xFFFUL << TEMP_A2_A2_Pos) /*!< Bit mask of A2 field. */ /* Register: TEMP_A3 */ -/* Description: Slope of 4th piece wise linear function */ +/* Description: Slope of fourth piecewise linear function */ -/* Bits 11..0 : Slope of 4th piece wise linear function */ +/* Bits 11..0 : Slope of fourth piecewise linear function */ #define TEMP_A3_A3_Pos (0UL) /*!< Position of A3 field. */ #define TEMP_A3_A3_Msk (0xFFFUL << TEMP_A3_A3_Pos) /*!< Bit mask of A3 field. */ /* Register: TEMP_A4 */ -/* Description: Slope of 5th piece wise linear function */ +/* Description: Slope of fifth piecewise linear function */ -/* Bits 11..0 : Slope of 5th piece wise linear function */ +/* Bits 11..0 : Slope of fifth piecewise linear function */ #define TEMP_A4_A4_Pos (0UL) /*!< Position of A4 field. */ #define TEMP_A4_A4_Msk (0xFFFUL << TEMP_A4_A4_Pos) /*!< Bit mask of A4 field. */ /* Register: TEMP_A5 */ -/* Description: Slope of 6th piece wise linear function */ +/* Description: Slope of sixth piecewise linear function */ -/* Bits 11..0 : Slope of 6th piece wise linear function */ +/* Bits 11..0 : Slope of sixth piecewise linear function */ #define TEMP_A5_A5_Pos (0UL) /*!< Position of A5 field. */ #define TEMP_A5_A5_Msk (0xFFFUL << TEMP_A5_A5_Pos) /*!< Bit mask of A5 field. */ /* Register: TEMP_B0 */ -/* Description: y-intercept of 1st piece wise linear function */ +/* Description: y-intercept of first piecewise linear function */ -/* Bits 13..0 : y-intercept of 1st piece wise linear function */ +/* Bits 13..0 : y-intercept of first piecewise linear function */ #define TEMP_B0_B0_Pos (0UL) /*!< Position of B0 field. */ #define TEMP_B0_B0_Msk (0x3FFFUL << TEMP_B0_B0_Pos) /*!< Bit mask of B0 field. */ /* Register: TEMP_B1 */ -/* Description: y-intercept of 2nd piece wise linear function */ +/* Description: y-intercept of second piecewise linear function */ -/* Bits 13..0 : y-intercept of 2nd piece wise linear function */ +/* Bits 13..0 : y-intercept of second piecewise linear function */ #define TEMP_B1_B1_Pos (0UL) /*!< Position of B1 field. */ #define TEMP_B1_B1_Msk (0x3FFFUL << TEMP_B1_B1_Pos) /*!< Bit mask of B1 field. */ /* Register: TEMP_B2 */ -/* Description: y-intercept of 3rd piece wise linear function */ +/* Description: y-intercept of third piecewise linear function */ -/* Bits 13..0 : y-intercept of 3rd piece wise linear function */ +/* Bits 13..0 : y-intercept of third piecewise linear function */ #define TEMP_B2_B2_Pos (0UL) /*!< Position of B2 field. */ #define TEMP_B2_B2_Msk (0x3FFFUL << TEMP_B2_B2_Pos) /*!< Bit mask of B2 field. */ /* Register: TEMP_B3 */ -/* Description: y-intercept of 4th piece wise linear function */ +/* Description: y-intercept of fourth piecewise linear function */ -/* Bits 13..0 : y-intercept of 4th piece wise linear function */ +/* Bits 13..0 : y-intercept of fourth piecewise linear function */ #define TEMP_B3_B3_Pos (0UL) /*!< Position of B3 field. */ #define TEMP_B3_B3_Msk (0x3FFFUL << TEMP_B3_B3_Pos) /*!< Bit mask of B3 field. */ /* Register: TEMP_B4 */ -/* Description: y-intercept of 5th piece wise linear function */ +/* Description: y-intercept of fifth piecewise linear function */ -/* Bits 13..0 : y-intercept of 5th piece wise linear function */ +/* Bits 13..0 : y-intercept of fifth piecewise linear function */ #define TEMP_B4_B4_Pos (0UL) /*!< Position of B4 field. */ #define TEMP_B4_B4_Msk (0x3FFFUL << TEMP_B4_B4_Pos) /*!< Bit mask of B4 field. */ /* Register: TEMP_B5 */ -/* Description: y-intercept of 6th piece wise linear function */ +/* Description: y-intercept of sixth piecewise linear function */ -/* Bits 13..0 : y-intercept of 6th piece wise linear function */ +/* Bits 13..0 : y-intercept of sixth piecewise linear function */ #define TEMP_B5_B5_Pos (0UL) /*!< Position of B5 field. */ #define TEMP_B5_B5_Msk (0x3FFFUL << TEMP_B5_B5_Pos) /*!< Bit mask of B5 field. */ /* Register: TEMP_T0 */ -/* Description: End point of 1st piece wise linear function */ +/* Description: End point of first piecewise linear function */ -/* Bits 7..0 : End point of 1st piece wise linear function */ +/* Bits 7..0 : End point of first piecewise linear function */ #define TEMP_T0_T0_Pos (0UL) /*!< Position of T0 field. */ #define TEMP_T0_T0_Msk (0xFFUL << TEMP_T0_T0_Pos) /*!< Bit mask of T0 field. */ /* Register: TEMP_T1 */ -/* Description: End point of 2nd piece wise linear function */ +/* Description: End point of second piecewise linear function */ -/* Bits 7..0 : End point of 2nd piece wise linear function */ +/* Bits 7..0 : End point of second piecewise linear function */ #define TEMP_T1_T1_Pos (0UL) /*!< Position of T1 field. */ #define TEMP_T1_T1_Msk (0xFFUL << TEMP_T1_T1_Pos) /*!< Bit mask of T1 field. */ /* Register: TEMP_T2 */ -/* Description: End point of 3rd piece wise linear function */ +/* Description: End point of third piecewise linear function */ -/* Bits 7..0 : End point of 3rd piece wise linear function */ +/* Bits 7..0 : End point of third piecewise linear function */ #define TEMP_T2_T2_Pos (0UL) /*!< Position of T2 field. */ #define TEMP_T2_T2_Msk (0xFFUL << TEMP_T2_T2_Pos) /*!< Bit mask of T2 field. */ /* Register: TEMP_T3 */ -/* Description: End point of 4th piece wise linear function */ +/* Description: End point of fourth piecewise linear function */ -/* Bits 7..0 : End point of 4th piece wise linear function */ +/* Bits 7..0 : End point of fourth piecewise linear function */ #define TEMP_T3_T3_Pos (0UL) /*!< Position of T3 field. */ #define TEMP_T3_T3_Msk (0xFFUL << TEMP_T3_T3_Pos) /*!< Bit mask of T3 field. */ /* Register: TEMP_T4 */ -/* Description: End point of 5th piece wise linear function */ +/* Description: End point of fifth piecewise linear function */ -/* Bits 7..0 : End point of 5th piece wise linear function */ +/* Bits 7..0 : End point of fifth piecewise linear function */ #define TEMP_T4_T4_Pos (0UL) /*!< Position of T4 field. */ #define TEMP_T4_T4_Msk (0xFFUL << TEMP_T4_T4_Pos) /*!< Bit mask of T4 field. */ @@ -14056,9 +14084,9 @@ POSSIBILITY OF SUCH DAMAGE. #define TWIM_EVENTS_ERROR_EVENTS_ERROR_Generated (1UL) /*!< Event generated */ /* Register: TWIM_EVENTS_SUSPENDED */ -/* Description: Last byte has been sent out after the SUSPEND task has been issued, TWI traffic is now suspended. */ +/* Description: SUSPEND task has been issued, TWI traffic is now suspended. */ -/* Bit 0 : Last byte has been sent out after the SUSPEND task has been issued, TWI traffic is now suspended. */ +/* Bit 0 : SUSPEND task has been issued, TWI traffic is now suspended. */ #define TWIM_EVENTS_SUSPENDED_EVENTS_SUSPENDED_Pos (0UL) /*!< Position of EVENTS_SUSPENDED field. */ #define TWIM_EVENTS_SUSPENDED_EVENTS_SUSPENDED_Msk (0x1UL << TWIM_EVENTS_SUSPENDED_EVENTS_SUSPENDED_Pos) /*!< Bit mask of EVENTS_SUSPENDED field. */ #define TWIM_EVENTS_SUSPENDED_EVENTS_SUSPENDED_NotGenerated (0UL) /*!< Event not generated */ @@ -14695,7 +14723,7 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: TWIS_MATCH */ /* Description: Status register indicating which address had a match */ -/* Bit 0 : Which of the addresses in {ADDRESS} matched the incoming address */ +/* Bit 0 : Indication of which address in {ADDRESS} that matched the incoming address */ #define TWIS_MATCH_MATCH_Pos (0UL) /*!< Position of MATCH field. */ #define TWIS_MATCH_MATCH_Msk (0x1UL << TWIS_MATCH_MATCH_Pos) /*!< Bit mask of MATCH field. */ @@ -15586,7 +15614,7 @@ POSSIBILITY OF SUCH DAMAGE. #define UARTE_INTENCLR_CTS_Clear (1UL) /*!< Disable */ /* Register: UARTE_ERRORSRC */ -/* Description: Error source Note : this register is read / write one to clear. */ +/* Description: Error source This register is read/write one to clear. */ /* Bit 3 : Break condition */ #define UARTE_ERRORSRC_BREAK_Pos (3UL) /*!< Position of BREAK field. */ @@ -15712,7 +15740,7 @@ POSSIBILITY OF SUCH DAMAGE. #define UARTE_BAUDRATE_BAUDRATE_Baud250000 (0x04000000UL) /*!< 250000 baud */ #define UARTE_BAUDRATE_BAUDRATE_Baud460800 (0x07400000UL) /*!< 460800 baud (actual rate: 457143) */ #define UARTE_BAUDRATE_BAUDRATE_Baud921600 (0x0F000000UL) /*!< 921600 baud (actual rate: 941176) */ -#define UARTE_BAUDRATE_BAUDRATE_Baud1M (0x10000000UL) /*!< 1Mega baud */ +#define UARTE_BAUDRATE_BAUDRATE_Baud1M (0x10000000UL) /*!< 1 megabaud */ /* Register: UARTE_RXD_PTR */ /* Description: Data pointer */ @@ -15826,7 +15854,8 @@ POSSIBILITY OF SUCH DAMAGE. #define UICR_APPROTECT_PALL_Pos (0UL) /*!< Position of PALL field. */ #define UICR_APPROTECT_PALL_Msk (0xFFUL << UICR_APPROTECT_PALL_Pos) /*!< Bit mask of PALL field. */ #define UICR_APPROTECT_PALL_Enabled (0x00UL) /*!< Enable */ -#define UICR_APPROTECT_PALL_Disabled (0xFFUL) /*!< Disable */ +#define UICR_APPROTECT_PALL_HwDisabled (0x5AUL) /*!< Hardware disable of access port protection for devices where access port protection is controlled by hardware and software */ +#define UICR_APPROTECT_PALL_Disabled (0xFFUL) /*!< Hardware disable of access port protection for devices where access port protection is controlled by hardware */ /* Register: UICR_NFCPINS */ /* Description: Setting of pins dedicated to NFC functionality: NFC antenna or GPIO */ @@ -15834,8 +15863,8 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 0 : Setting of pins dedicated to NFC functionality */ #define UICR_NFCPINS_PROTECT_Pos (0UL) /*!< Position of PROTECT field. */ #define UICR_NFCPINS_PROTECT_Msk (0x1UL << UICR_NFCPINS_PROTECT_Pos) /*!< Bit mask of PROTECT field. */ -#define UICR_NFCPINS_PROTECT_Disabled (0UL) /*!< Operation as GPIO pins. Same protection as normal GPIO pins */ -#define UICR_NFCPINS_PROTECT_NFC (1UL) /*!< Operation as NFC antenna pins. Configures the protection for NFC operation */ +#define UICR_NFCPINS_PROTECT_Disabled (0UL) /*!< Operation as GPIO pins. Same protection as normal GPIO pins. */ +#define UICR_NFCPINS_PROTECT_NFC (1UL) /*!< Operation as NFC antenna pins. Configures the protection for NFC operation. */ /* Register: UICR_DEBUGCTRL */ /* Description: Processor debug control */ @@ -15853,9 +15882,9 @@ POSSIBILITY OF SUCH DAMAGE. #define UICR_DEBUGCTRL_CPUNIDEN_Enabled (0xFFUL) /*!< Enable CPU ITM and ETM functionality (default behavior) */ /* Register: UICR_REGOUT0 */ -/* Description: GPIO reference voltage / external output supply voltage in high voltage mode */ +/* Description: Output voltage from REG0 regulator stage. The maximum output voltage from this stage is given as VDDH - V_VDDH-VDD. */ -/* Bits 2..0 : Output voltage from of REG0 regulator stage. The maximum output voltage from this stage is given as VDDH - VEXDIF. */ +/* Bits 2..0 : Output voltage from REG0 regulator stage. */ #define UICR_REGOUT0_VOUT_Pos (0UL) /*!< Position of VOUT field. */ #define UICR_REGOUT0_VOUT_Msk (0x7UL << UICR_REGOUT0_VOUT_Pos) /*!< Bit mask of VOUT field. */ #define UICR_REGOUT0_VOUT_1V8 (0UL) /*!< 1.8 V */ @@ -15961,9 +15990,9 @@ POSSIBILITY OF SUCH DAMAGE. #define USBD_EVENTS_STARTED_EVENTS_STARTED_Generated (1UL) /*!< Event generated */ /* Register: USBD_EVENTS_ENDEPIN */ -/* Description: Description collection: The whole EPIN[n] buffer has been consumed. The RAM buffer can be accessed safely by software. */ +/* Description: Description collection: The whole EPIN[n] buffer has been consumed. The buffer can be accessed safely by software. */ -/* Bit 0 : The whole EPIN[n] buffer has been consumed. The RAM buffer can be accessed safely by software. */ +/* Bit 0 : The whole EPIN[n] buffer has been consumed. The buffer can be accessed safely by software. */ #define USBD_EVENTS_ENDEPIN_EVENTS_ENDEPIN_Pos (0UL) /*!< Position of EVENTS_ENDEPIN field. */ #define USBD_EVENTS_ENDEPIN_EVENTS_ENDEPIN_Msk (0x1UL << USBD_EVENTS_ENDEPIN_EVENTS_ENDEPIN_Pos) /*!< Bit mask of EVENTS_ENDEPIN field. */ #define USBD_EVENTS_ENDEPIN_EVENTS_ENDEPIN_NotGenerated (0UL) /*!< Event not generated */ @@ -15979,27 +16008,27 @@ POSSIBILITY OF SUCH DAMAGE. #define USBD_EVENTS_EP0DATADONE_EVENTS_EP0DATADONE_Generated (1UL) /*!< Event generated */ /* Register: USBD_EVENTS_ENDISOIN */ -/* Description: The whole ISOIN buffer has been consumed. The RAM buffer can be accessed safely by software. */ +/* Description: The whole ISOIN buffer has been consumed. The buffer can be accessed safely by software. */ -/* Bit 0 : The whole ISOIN buffer has been consumed. The RAM buffer can be accessed safely by software. */ +/* Bit 0 : The whole ISOIN buffer has been consumed. The buffer can be accessed safely by software. */ #define USBD_EVENTS_ENDISOIN_EVENTS_ENDISOIN_Pos (0UL) /*!< Position of EVENTS_ENDISOIN field. */ #define USBD_EVENTS_ENDISOIN_EVENTS_ENDISOIN_Msk (0x1UL << USBD_EVENTS_ENDISOIN_EVENTS_ENDISOIN_Pos) /*!< Bit mask of EVENTS_ENDISOIN field. */ #define USBD_EVENTS_ENDISOIN_EVENTS_ENDISOIN_NotGenerated (0UL) /*!< Event not generated */ #define USBD_EVENTS_ENDISOIN_EVENTS_ENDISOIN_Generated (1UL) /*!< Event generated */ /* Register: USBD_EVENTS_ENDEPOUT */ -/* Description: Description collection: The whole EPOUT[n] buffer has been consumed. The RAM buffer can be accessed safely by software. */ +/* Description: Description collection: The whole EPOUT[n] buffer has been consumed. The buffer can be accessed safely by software. */ -/* Bit 0 : The whole EPOUT[n] buffer has been consumed. The RAM buffer can be accessed safely by software. */ +/* Bit 0 : The whole EPOUT[n] buffer has been consumed. The buffer can be accessed safely by software. */ #define USBD_EVENTS_ENDEPOUT_EVENTS_ENDEPOUT_Pos (0UL) /*!< Position of EVENTS_ENDEPOUT field. */ #define USBD_EVENTS_ENDEPOUT_EVENTS_ENDEPOUT_Msk (0x1UL << USBD_EVENTS_ENDEPOUT_EVENTS_ENDEPOUT_Pos) /*!< Bit mask of EVENTS_ENDEPOUT field. */ #define USBD_EVENTS_ENDEPOUT_EVENTS_ENDEPOUT_NotGenerated (0UL) /*!< Event not generated */ #define USBD_EVENTS_ENDEPOUT_EVENTS_ENDEPOUT_Generated (1UL) /*!< Event generated */ /* Register: USBD_EVENTS_ENDISOOUT */ -/* Description: The whole ISOOUT buffer has been consumed. The RAM buffer can be accessed safely by software. */ +/* Description: The whole ISOOUT buffer has been consumed. The buffer can be accessed safely by software. */ -/* Bit 0 : The whole ISOOUT buffer has been consumed. The RAM buffer can be accessed safely by software. */ +/* Bit 0 : The whole ISOOUT buffer has been consumed. The buffer can be accessed safely by software. */ #define USBD_EVENTS_ENDISOOUT_EVENTS_ENDISOOUT_Pos (0UL) /*!< Position of EVENTS_ENDISOOUT field. */ #define USBD_EVENTS_ENDISOOUT_EVENTS_ENDISOOUT_Msk (0x1UL << USBD_EVENTS_ENDISOOUT_EVENTS_ENDISOOUT_Pos) /*!< Bit mask of EVENTS_ENDISOOUT field. */ #define USBD_EVENTS_ENDISOOUT_EVENTS_ENDISOOUT_NotGenerated (0UL) /*!< Event not generated */ @@ -17130,7 +17159,7 @@ POSSIBILITY OF SUCH DAMAGE. /* Bits 15..0 : Controls the split of ISO buffers */ #define USBD_ISOSPLIT_SPLIT_Pos (0UL) /*!< Position of SPLIT field. */ #define USBD_ISOSPLIT_SPLIT_Msk (0xFFFFUL << USBD_ISOSPLIT_SPLIT_Pos) /*!< Bit mask of SPLIT field. */ -#define USBD_ISOSPLIT_SPLIT_OneDir (0x0000UL) /*!< Full buffer dedicated to either iso IN or OUT */ +#define USBD_ISOSPLIT_SPLIT_OneDir (0x0000UL) /*!< Full buffer dedicated to either ISO IN or OUT */ #define USBD_ISOSPLIT_SPLIT_HalfIN (0x0080UL) /*!< Lower half for IN, upper half for OUT */ /* Register: USBD_FRAMECNTR */ @@ -17161,7 +17190,7 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: USBD_EPIN_PTR */ /* Description: Description cluster: Data pointer */ -/* Bits 31..0 : Data pointer. Accepts any address in Data RAM. */ +/* Bits 31..0 : Data pointer */ #define USBD_EPIN_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ #define USBD_EPIN_PTR_PTR_Msk (0xFFFFFFFFUL << USBD_EPIN_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ @@ -17182,7 +17211,7 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: USBD_ISOIN_PTR */ /* Description: Data pointer */ -/* Bits 31..0 : Data pointer. Accepts any address in Data RAM. */ +/* Bits 31..0 : Data pointer */ #define USBD_ISOIN_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ #define USBD_ISOIN_PTR_PTR_Msk (0xFFFFFFFFUL << USBD_ISOIN_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ @@ -17203,7 +17232,7 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: USBD_EPOUT_PTR */ /* Description: Description cluster: Data pointer */ -/* Bits 31..0 : Data pointer. Accepts any address in Data RAM. */ +/* Bits 31..0 : Data pointer */ #define USBD_EPOUT_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ #define USBD_EPOUT_PTR_PTR_Msk (0xFFFFFFFFUL << USBD_EPOUT_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ @@ -17224,7 +17253,7 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: USBD_ISOOUT_PTR */ /* Description: Data pointer */ -/* Bits 31..0 : Data pointer. Accepts any address in Data RAM. */ +/* Bits 31..0 : Data pointer */ #define USBD_ISOOUT_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ #define USBD_ISOOUT_PTR_PTR_Msk (0xFFFFFFFFUL << USBD_ISOOUT_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ diff --git a/mdk/nrf52840_peripherals.h b/mdk/nrf52840_peripherals.h index 822d6cd43b..1c9140e7e2 100644 --- a/mdk/nrf52840_peripherals.h +++ b/mdk/nrf52840_peripherals.h @@ -1,6 +1,8 @@ /* -Copyright (c) 2010 - 2020, Nordic Semiconductor ASA All rights reserved. +Copyright (c) 2010 - 2021, Nordic Semiconductor ASA All rights reserved. + +SPDX-License-Identifier: BSD-3-Clause Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: diff --git a/mdk/nrf52_bitfields.h b/mdk/nrf52_bitfields.h index 93939c14ec..220ada67e4 100644 --- a/mdk/nrf52_bitfields.h +++ b/mdk/nrf52_bitfields.h @@ -1,6 +1,8 @@ /* -Copyright (c) 2010 - 2020, Nordic Semiconductor ASA All rights reserved. +Copyright (c) 2010 - 2021, Nordic Semiconductor ASA All rights reserved. + +SPDX-License-Identifier: BSD-3-Clause Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: @@ -131,6 +133,26 @@ POSSIBILITY OF SUCH DAMAGE. #define AAR_SCRATCHPTR_SCRATCHPTR_Msk (0xFFFFFFFFUL << AAR_SCRATCHPTR_SCRATCHPTR_Pos) /*!< Bit mask of SCRATCHPTR field. */ +/* Peripheral: APPROTECT */ +/* Description: Access Port Protection */ + +/* Register: APPROTECT_FORCEPROTECT */ +/* Description: Software force enable APPROTECT mechanism until next reset. This register can only be written once. */ + +/* Bits 7..0 : Write 0x0 to force enable APPROTECT mechanism */ +#define APPROTECT_FORCEPROTECT_FORCEPROTECT_Pos (0UL) /*!< Position of FORCEPROTECT field. */ +#define APPROTECT_FORCEPROTECT_FORCEPROTECT_Msk (0xFFUL << APPROTECT_FORCEPROTECT_FORCEPROTECT_Pos) /*!< Bit mask of FORCEPROTECT field. */ +#define APPROTECT_FORCEPROTECT_FORCEPROTECT_Force (0x0UL) /*!< Software force enable APPROTECT mechanism */ + +/* Register: APPROTECT_DISABLE */ +/* Description: Software disable APPROTECT mechanism */ + +/* Bits 7..0 : Software disable APPROTECT mechanism */ +#define APPROTECT_DISABLE_DISABLE_Pos (0UL) /*!< Position of DISABLE field. */ +#define APPROTECT_DISABLE_DISABLE_Msk (0xFFUL << APPROTECT_DISABLE_DISABLE_Pos) /*!< Bit mask of DISABLE field. */ +#define APPROTECT_DISABLE_DISABLE_SwDisable (0x5AUL) /*!< Software disable APPROTECT mechanism */ + + /* Peripheral: BPROT */ /* Description: Block Protect */ @@ -12467,13 +12489,14 @@ POSSIBILITY OF SUCH DAMAGE. #define UICR_PSELRESET_PIN_Msk (0x3FUL << UICR_PSELRESET_PIN_Pos) /*!< Bit mask of PIN field. */ /* Register: UICR_APPROTECT */ -/* Description: Access Port protection */ +/* Description: Access port protection */ -/* Bits 7..0 : Enable or disable Access Port protection. Any other value than 0xFF being written to this field will enable protection. */ +/* Bits 7..0 : Enable or disable access port protection. */ #define UICR_APPROTECT_PALL_Pos (0UL) /*!< Position of PALL field. */ #define UICR_APPROTECT_PALL_Msk (0xFFUL << UICR_APPROTECT_PALL_Pos) /*!< Bit mask of PALL field. */ #define UICR_APPROTECT_PALL_Enabled (0x00UL) /*!< Enable */ -#define UICR_APPROTECT_PALL_Disabled (0xFFUL) /*!< Disable */ +#define UICR_APPROTECT_PALL_HwDisabled (0x5AUL) /*!< Hardware disable of access port protection for devices where access port protection is controlled by hardware and software */ +#define UICR_APPROTECT_PALL_Disabled (0xFFUL) /*!< Hardware disable of access port protection for devices where access port protection is controlled by hardware */ /* Register: UICR_NFCPINS */ /* Description: Setting of pins dedicated to NFC functionality: NFC antenna or GPIO */ @@ -12481,8 +12504,8 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 0 : Setting of pins dedicated to NFC functionality */ #define UICR_NFCPINS_PROTECT_Pos (0UL) /*!< Position of PROTECT field. */ #define UICR_NFCPINS_PROTECT_Msk (0x1UL << UICR_NFCPINS_PROTECT_Pos) /*!< Bit mask of PROTECT field. */ -#define UICR_NFCPINS_PROTECT_Disabled (0UL) /*!< Operation as GPIO pins. Same protection as normal GPIO pins */ -#define UICR_NFCPINS_PROTECT_NFC (1UL) /*!< Operation as NFC antenna pins. Configures the protection for NFC operation */ +#define UICR_NFCPINS_PROTECT_Disabled (0UL) /*!< Operation as GPIO pins. Same protection as normal GPIO pins. */ +#define UICR_NFCPINS_PROTECT_NFC (1UL) /*!< Operation as NFC antenna pins. Configures the protection for NFC operation. */ /* Peripheral: WDT */ diff --git a/mdk/nrf52_erratas.h b/mdk/nrf52_erratas.h index 5ca1fc2d37..e05d5678b4 100644 --- a/mdk/nrf52_erratas.h +++ b/mdk/nrf52_erratas.h @@ -3,7 +3,9 @@ /* -Copyright (c) 2010 - 2020, Nordic Semiconductor ASA All rights reserved. +Copyright (c) 2010 - 2021, Nordic Semiconductor ASA All rights reserved. + +SPDX-License-Identifier: BSD-3-Clause Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: @@ -258,6 +260,8 @@ static bool nrf52_errata_1(void) return false; case 0x06ul: return false; + case 0x07ul: + return false; default: return false; } @@ -303,6 +307,8 @@ static bool nrf52_errata_2(void) return false; case 0x06ul: return false; + case 0x07ul: + return false; default: return false; } @@ -348,6 +354,8 @@ static bool nrf52_errata_3(void) return false; case 0x06ul: return false; + case 0x07ul: + return false; default: return false; } @@ -393,6 +401,8 @@ static bool nrf52_errata_4(void) return false; case 0x06ul: return false; + case 0x07ul: + return false; default: return false; } @@ -438,6 +448,8 @@ static bool nrf52_errata_7(void) return false; case 0x06ul: return false; + case 0x07ul: + return false; default: return false; } @@ -483,6 +495,8 @@ static bool nrf52_errata_8(void) return false; case 0x06ul: return false; + case 0x07ul: + return false; default: return false; } @@ -528,6 +542,8 @@ static bool nrf52_errata_9(void) return false; case 0x06ul: return false; + case 0x07ul: + return false; default: return false; } @@ -573,6 +589,8 @@ static bool nrf52_errata_10(void) return false; case 0x06ul: return false; + case 0x07ul: + return false; default: return false; } @@ -618,6 +636,8 @@ static bool nrf52_errata_11(void) return false; case 0x06ul: return false; + case 0x07ul: + return false; default: return false; } @@ -674,6 +694,8 @@ static bool nrf52_errata_12(void) return true; case 0x06ul: return true; + case 0x07ul: + return true; default: return true; } @@ -740,6 +762,8 @@ static bool nrf52_errata_15(void) return true; case 0x06ul: return true; + case 0x07ul: + return true; default: return true; } @@ -845,6 +869,8 @@ static bool nrf52_errata_16(void) return false; case 0x06ul: return false; + case 0x07ul: + return false; default: return false; } @@ -890,6 +916,8 @@ static bool nrf52_errata_17(void) return false; case 0x06ul: return false; + case 0x07ul: + return false; default: return false; } @@ -960,6 +988,8 @@ static bool nrf52_errata_20(void) return true; case 0x06ul: return true; + case 0x07ul: + return true; default: return true; } @@ -979,11 +1009,11 @@ static bool nrf52_errata_20(void) case 0x03ul: return true; case 0x04ul: - return false; + return true; case 0x05ul: - return false; + return true; default: - return false; + return true; } } #endif @@ -1010,6 +1040,8 @@ static bool nrf52_errata_20(void) return true; case 0x01ul: return true; + case 0x02ul: + return true; default: return true; } @@ -1050,6 +1082,8 @@ static bool nrf52_errata_20(void) return true; case 0x02ul: return true; + case 0x03ul: + return true; default: return true; } @@ -1095,6 +1129,8 @@ static bool nrf52_errata_23(void) return false; case 0x06ul: return false; + case 0x07ul: + return false; default: return false; } @@ -1140,6 +1176,8 @@ static bool nrf52_errata_24(void) return false; case 0x06ul: return false; + case 0x07ul: + return false; default: return false; } @@ -1185,6 +1223,8 @@ static bool nrf52_errata_25(void) return false; case 0x06ul: return false; + case 0x07ul: + return false; default: return false; } @@ -1230,6 +1270,8 @@ static bool nrf52_errata_26(void) return false; case 0x06ul: return false; + case 0x07ul: + return false; default: return false; } @@ -1275,6 +1317,8 @@ static bool nrf52_errata_27(void) return false; case 0x06ul: return false; + case 0x07ul: + return false; default: return false; } @@ -1320,6 +1364,8 @@ static bool nrf52_errata_28(void) return false; case 0x06ul: return false; + case 0x07ul: + return false; default: return false; } @@ -1365,6 +1411,8 @@ static bool nrf52_errata_29(void) return false; case 0x06ul: return false; + case 0x07ul: + return false; default: return false; } @@ -1410,6 +1458,8 @@ static bool nrf52_errata_30(void) return false; case 0x06ul: return false; + case 0x07ul: + return false; default: return false; } @@ -1474,6 +1524,8 @@ static bool nrf52_errata_31(void) return true; case 0x06ul: return true; + case 0x07ul: + return true; default: return true; } @@ -1557,6 +1609,8 @@ static bool nrf52_errata_32(void) return false; case 0x06ul: return false; + case 0x07ul: + return false; default: return false; } @@ -1602,6 +1656,8 @@ static bool nrf52_errata_33(void) return false; case 0x06ul: return false; + case 0x07ul: + return false; default: return false; } @@ -1647,6 +1703,8 @@ static bool nrf52_errata_34(void) return false; case 0x06ul: return false; + case 0x07ul: + return false; default: return false; } @@ -1692,6 +1750,8 @@ static bool nrf52_errata_35(void) return false; case 0x06ul: return false; + case 0x07ul: + return false; default: return false; } @@ -1762,6 +1822,8 @@ static bool nrf52_errata_36(void) return true; case 0x06ul: return true; + case 0x07ul: + return true; default: return true; } @@ -1781,11 +1843,11 @@ static bool nrf52_errata_36(void) case 0x03ul: return true; case 0x04ul: - return false; + return true; case 0x05ul: - return false; + return true; default: - return false; + return true; } } #endif @@ -1812,6 +1874,8 @@ static bool nrf52_errata_36(void) return true; case 0x01ul: return true; + case 0x02ul: + return true; default: return true; } @@ -1852,6 +1916,8 @@ static bool nrf52_errata_36(void) return true; case 0x02ul: return true; + case 0x03ul: + return true; default: return true; } @@ -1897,6 +1963,8 @@ static bool nrf52_errata_37(void) return false; case 0x06ul: return false; + case 0x07ul: + return false; default: return false; } @@ -1942,6 +2010,8 @@ static bool nrf52_errata_38(void) return false; case 0x06ul: return false; + case 0x07ul: + return false; default: return false; } @@ -1987,6 +2057,8 @@ static bool nrf52_errata_39(void) return false; case 0x06ul: return false; + case 0x07ul: + return false; default: return false; } @@ -2032,6 +2104,8 @@ static bool nrf52_errata_40(void) return false; case 0x06ul: return false; + case 0x07ul: + return false; default: return false; } @@ -2077,6 +2151,8 @@ static bool nrf52_errata_41(void) return false; case 0x06ul: return false; + case 0x07ul: + return false; default: return false; } @@ -2122,6 +2198,8 @@ static bool nrf52_errata_42(void) return false; case 0x06ul: return false; + case 0x07ul: + return false; default: return false; } @@ -2167,6 +2245,8 @@ static bool nrf52_errata_43(void) return false; case 0x06ul: return false; + case 0x07ul: + return false; default: return false; } @@ -2212,6 +2292,8 @@ static bool nrf52_errata_44(void) return false; case 0x06ul: return false; + case 0x07ul: + return false; default: return false; } @@ -2257,6 +2339,8 @@ static bool nrf52_errata_46(void) return false; case 0x06ul: return false; + case 0x07ul: + return false; default: return false; } @@ -2302,6 +2386,8 @@ static bool nrf52_errata_47(void) return false; case 0x06ul: return false; + case 0x07ul: + return false; default: return false; } @@ -2347,6 +2433,8 @@ static bool nrf52_errata_48(void) return false; case 0x06ul: return false; + case 0x07ul: + return false; default: return false; } @@ -2392,6 +2480,8 @@ static bool nrf52_errata_49(void) return false; case 0x06ul: return false; + case 0x07ul: + return false; default: return false; } @@ -2448,6 +2538,8 @@ static bool nrf52_errata_51(void) return true; case 0x06ul: return true; + case 0x07ul: + return true; default: return true; } @@ -2508,6 +2600,8 @@ static bool nrf52_errata_54(void) return true; case 0x06ul: return true; + case 0x07ul: + return true; default: return true; } @@ -2594,6 +2688,8 @@ static bool nrf52_errata_55(void) return true; case 0x06ul: return true; + case 0x07ul: + return true; default: return true; } @@ -2613,11 +2709,11 @@ static bool nrf52_errata_55(void) case 0x03ul: return true; case 0x04ul: - return false; + return true; case 0x05ul: - return false; + return true; default: - return false; + return true; } } #endif @@ -2630,6 +2726,8 @@ static bool nrf52_errata_55(void) return true; case 0x01ul: return true; + case 0x02ul: + return true; default: return true; } @@ -2646,6 +2744,8 @@ static bool nrf52_errata_55(void) return true; case 0x02ul: return false; + case 0x03ul: + return false; default: return false; } @@ -2691,6 +2791,8 @@ static bool nrf52_errata_57(void) return false; case 0x06ul: return false; + case 0x07ul: + return false; default: return false; } @@ -2751,6 +2853,8 @@ static bool nrf52_errata_58(void) return true; case 0x06ul: return true; + case 0x07ul: + return true; default: return true; } @@ -2818,6 +2922,8 @@ static bool nrf52_errata_62(void) return false; case 0x06ul: return false; + case 0x07ul: + return false; default: return false; } @@ -2863,6 +2969,8 @@ static bool nrf52_errata_63(void) return false; case 0x06ul: return false; + case 0x07ul: + return false; default: return false; } @@ -2919,6 +3027,8 @@ static bool nrf52_errata_64(void) return true; case 0x06ul: return true; + case 0x07ul: + return true; default: return true; } @@ -2964,6 +3074,8 @@ static bool nrf52_errata_65(void) return false; case 0x06ul: return false; + case 0x07ul: + return false; default: return false; } @@ -3034,6 +3146,8 @@ static bool nrf52_errata_66(void) return true; case 0x06ul: return true; + case 0x07ul: + return true; default: return true; } @@ -3053,11 +3167,11 @@ static bool nrf52_errata_66(void) case 0x03ul: return true; case 0x04ul: - return false; + return true; case 0x05ul: - return false; + return true; default: - return false; + return true; } } #endif @@ -3084,6 +3198,8 @@ static bool nrf52_errata_66(void) return true; case 0x01ul: return true; + case 0x02ul: + return true; default: return true; } @@ -3124,6 +3240,8 @@ static bool nrf52_errata_66(void) return true; case 0x02ul: return true; + case 0x03ul: + return true; default: return true; } @@ -3180,6 +3298,8 @@ static bool nrf52_errata_67(void) return true; case 0x06ul: return true; + case 0x07ul: + return true; default: return true; } @@ -3246,6 +3366,8 @@ static bool nrf52_errata_68(void) return true; case 0x06ul: return true; + case 0x07ul: + return true; default: return true; } @@ -3351,6 +3473,8 @@ static bool nrf52_errata_70(void) return false; case 0x06ul: return false; + case 0x07ul: + return false; default: return false; } @@ -3396,6 +3520,8 @@ static bool nrf52_errata_71(void) return false; case 0x06ul: return false; + case 0x07ul: + return false; default: return false; } @@ -3452,6 +3578,8 @@ static bool nrf52_errata_72(void) return true; case 0x06ul: return true; + case 0x07ul: + return true; default: return true; } @@ -3497,6 +3625,8 @@ static bool nrf52_errata_73(void) return false; case 0x06ul: return false; + case 0x07ul: + return false; default: return false; } @@ -3553,6 +3683,8 @@ static bool nrf52_errata_74(void) return true; case 0x06ul: return true; + case 0x07ul: + return true; default: return true; } @@ -3609,6 +3741,8 @@ static bool nrf52_errata_75(void) return true; case 0x06ul: return true; + case 0x07ul: + return true; default: return true; } @@ -3665,6 +3799,8 @@ static bool nrf52_errata_76(void) return true; case 0x06ul: return true; + case 0x07ul: + return true; default: return true; } @@ -3729,6 +3865,8 @@ static bool nrf52_errata_77(void) return true; case 0x06ul: return true; + case 0x07ul: + return true; default: return true; } @@ -3837,6 +3975,8 @@ static bool nrf52_errata_78(void) return true; case 0x06ul: return true; + case 0x07ul: + return true; default: return true; } @@ -3856,11 +3996,11 @@ static bool nrf52_errata_78(void) case 0x03ul: return true; case 0x04ul: - return false; + return true; case 0x05ul: - return false; + return true; default: - return false; + return true; } } #endif @@ -3887,6 +4027,8 @@ static bool nrf52_errata_78(void) return true; case 0x01ul: return true; + case 0x02ul: + return true; default: return true; } @@ -3927,6 +4069,8 @@ static bool nrf52_errata_78(void) return true; case 0x02ul: return true; + case 0x03ul: + return true; default: return true; } @@ -3983,6 +4127,8 @@ static bool nrf52_errata_79(void) return true; case 0x06ul: return true; + case 0x07ul: + return true; default: return true; } @@ -4049,6 +4195,8 @@ static bool nrf52_errata_81(void) return true; case 0x06ul: return true; + case 0x07ul: + return true; default: return true; } @@ -4068,11 +4216,11 @@ static bool nrf52_errata_81(void) case 0x03ul: return true; case 0x04ul: - return false; + return true; case 0x05ul: - return false; + return true; default: - return false; + return true; } } #endif @@ -4175,6 +4323,8 @@ static bool nrf52_errata_83(void) return true; case 0x06ul: return true; + case 0x07ul: + return true; default: return true; } @@ -4291,6 +4441,8 @@ static bool nrf52_errata_84(void) return true; case 0x06ul: return true; + case 0x07ul: + return true; default: return true; } @@ -4347,6 +4499,8 @@ static bool nrf52_errata_86(void) return true; case 0x06ul: return true; + case 0x07ul: + return true; default: return true; } @@ -4411,6 +4565,8 @@ static bool nrf52_errata_87(void) return true; case 0x06ul: return true; + case 0x07ul: + return true; default: return true; } @@ -4430,11 +4586,11 @@ static bool nrf52_errata_87(void) case 0x03ul: return true; case 0x04ul: - return false; + return true; case 0x05ul: - return false; + return true; default: - return false; + return true; } } #endif @@ -4447,6 +4603,8 @@ static bool nrf52_errata_87(void) return true; case 0x01ul: return true; + case 0x02ul: + return true; default: return true; } @@ -4462,9 +4620,11 @@ static bool nrf52_errata_87(void) case 0x01ul: return true; case 0x02ul: - return true; + return false; + case 0x03ul: + return false; default: - return true; + return false; } } #endif @@ -4527,6 +4687,8 @@ static bool nrf52_errata_88(void) return true; case 0x06ul: return true; + case 0x07ul: + return true; default: return true; } @@ -4625,6 +4787,8 @@ static bool nrf52_errata_89(void) return true; case 0x06ul: return true; + case 0x07ul: + return true; default: return true; } @@ -4703,8 +4867,10 @@ static bool nrf52_errata_91(void) return true; case 0x06ul: return true; + case 0x07ul: + return false; default: - return true; + return false; } } #endif @@ -4855,6 +5021,8 @@ static bool nrf52_errata_97(void) return true; case 0x06ul: return true; + case 0x07ul: + return true; default: return true; } @@ -4979,6 +5147,8 @@ static bool nrf52_errata_101(void) return true; case 0x06ul: return true; + case 0x07ul: + return true; default: return true; } @@ -5035,6 +5205,8 @@ static bool nrf52_errata_102(void) return true; case 0x06ul: return false; + case 0x07ul: + return false; default: return false; } @@ -5183,6 +5355,8 @@ static bool nrf52_errata_106(void) return true; case 0x06ul: return false; + case 0x07ul: + return false; default: return false; } @@ -5239,6 +5413,8 @@ static bool nrf52_errata_107(void) return true; case 0x06ul: return false; + case 0x07ul: + return false; default: return false; } @@ -5295,6 +5471,8 @@ static bool nrf52_errata_108(void) return true; case 0x06ul: return true; + case 0x07ul: + return true; default: return true; } @@ -5351,6 +5529,8 @@ static bool nrf52_errata_109(void) return true; case 0x06ul: return true; + case 0x07ul: + return true; default: return true; } @@ -5549,6 +5729,8 @@ static bool nrf52_errata_113(void) return true; case 0x06ul: return true; + case 0x07ul: + return true; default: return true; } @@ -5936,11 +6118,11 @@ static bool nrf52_errata_122(void) case 0x03ul: return true; case 0x04ul: - return false; + return true; case 0x05ul: - return false; + return true; default: - return false; + return true; } } #endif @@ -6133,6 +6315,8 @@ static bool nrf52_errata_132(void) return true; case 0x06ul: return true; + case 0x07ul: + return true; default: return true; } @@ -6341,6 +6525,8 @@ static bool nrf52_errata_136(void) return true; case 0x06ul: return true; + case 0x07ul: + return true; default: return true; } @@ -6360,11 +6546,11 @@ static bool nrf52_errata_136(void) case 0x03ul: return true; case 0x04ul: - return false; + return true; case 0x05ul: - return false; + return true; default: - return false; + return true; } } #endif @@ -6391,6 +6577,8 @@ static bool nrf52_errata_136(void) return true; case 0x01ul: return true; + case 0x02ul: + return true; default: return true; } @@ -6431,6 +6619,8 @@ static bool nrf52_errata_136(void) return true; case 0x02ul: return true; + case 0x03ul: + return true; default: return true; } @@ -6487,6 +6677,8 @@ static bool nrf52_errata_138(void) return true; case 0x06ul: return true; + case 0x07ul: + return true; default: return true; } @@ -6589,6 +6781,8 @@ static bool nrf52_errata_141(void) return true; case 0x06ul: return true; + case 0x07ul: + return true; default: return true; } @@ -6695,6 +6889,8 @@ static bool nrf52_errata_143(void) return true; case 0x06ul: return true; + case 0x07ul: + return true; default: return true; } @@ -6865,6 +7061,8 @@ static bool nrf52_errata_146(void) return true; case 0x06ul: return true; + case 0x07ul: + return true; default: return true; } @@ -6967,6 +7165,8 @@ static bool nrf52_errata_149(void) return true; case 0x06ul: return true; + case 0x07ul: + return true; default: return true; } @@ -7029,6 +7229,8 @@ static bool nrf52_errata_150(void) return true; case 0x06ul: return true; + case 0x07ul: + return true; default: return true; } @@ -7121,7 +7323,9 @@ static bool nrf52_errata_151(void) } /* ========= Errata 153 ========= */ -#if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) +#if defined (NRF52810_XXAA) || defined (DEVELOP_IN_NRF52810) \ + || defined (NRF52811_XXAA) || defined (DEVELOP_IN_NRF52811) \ + || defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) #define NRF52_ERRATA_153_PRESENT 1 #else #define NRF52_ERRATA_153_PRESENT 0 @@ -7136,7 +7340,9 @@ static bool nrf52_errata_153(void) #ifndef NRF52_SERIES return false; #else - #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + #if defined (NRF52810_XXAA) || defined (DEVELOP_IN_NRF52810)\ + || defined (NRF52811_XXAA) || defined (DEVELOP_IN_NRF52811)\ + || defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) uint32_t var1 = *(uint32_t *)0x10000130ul; uint32_t var2 = *(uint32_t *)0x10000134ul; #endif @@ -7154,11 +7360,37 @@ static bool nrf52_errata_153(void) case 0x03ul: return true; case 0x04ul: - return false; + return true; case 0x05ul: - return false; + return true; default: + return true; + } + } + #endif + #if defined (NRF52810_XXAA) || defined (DEVELOP_IN_NRF52810) + if (var1 == 0x0A) + { + switch(var2) + { + case 0x00ul: return false; + case 0x01ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52811_XXAA) || defined (DEVELOP_IN_NRF52811) + if (var1 == 0x0E) + { + switch(var2) + { + case 0x00ul: + return true; + default: + return true; } } #endif @@ -7269,6 +7501,8 @@ static bool nrf52_errata_155(void) return true; case 0x06ul: return true; + case 0x07ul: + return true; default: return true; } @@ -7288,11 +7522,11 @@ static bool nrf52_errata_155(void) case 0x03ul: return true; case 0x04ul: - return false; + return true; case 0x05ul: - return false; + return true; default: - return false; + return true; } } #endif @@ -7395,6 +7629,8 @@ static bool nrf52_errata_156(void) return true; case 0x06ul: return true; + case 0x07ul: + return true; default: return true; } @@ -7649,6 +7885,8 @@ static bool nrf52_errata_163(void) return true; case 0x06ul: return false; + case 0x07ul: + return false; default: return false; } @@ -7738,11 +7976,11 @@ static bool nrf52_errata_166(void) case 0x03ul: return true; case 0x04ul: - return false; + return true; case 0x05ul: - return false; + return true; default: - return false; + return true; } } #endif @@ -7788,11 +8026,11 @@ static bool nrf52_errata_170(void) case 0x03ul: return true; case 0x04ul: - return false; + return true; case 0x05ul: - return false; + return true; default: - return false; + return true; } } #endif @@ -7805,6 +8043,8 @@ static bool nrf52_errata_170(void) return true; case 0x01ul: return true; + case 0x02ul: + return true; default: return true; } @@ -7821,6 +8061,8 @@ static bool nrf52_errata_170(void) return true; case 0x02ul: return false; + case 0x03ul: + return false; default: return false; } @@ -7864,11 +8106,11 @@ static bool nrf52_errata_171(void) case 0x03ul: return true; case 0x04ul: - return false; + return true; case 0x05ul: - return false; + return true; default: - return false; + return true; } } #endif @@ -7910,11 +8152,11 @@ static bool nrf52_errata_172(void) case 0x03ul: return true; case 0x04ul: - return false; + return true; case 0x05ul: - return false; + return true; default: - return false; + return true; } } #endif @@ -7983,6 +8225,8 @@ static bool nrf52_errata_173(void) return true; case 0x06ul: return true; + case 0x07ul: + return true; default: return true; } @@ -8002,11 +8246,11 @@ static bool nrf52_errata_173(void) case 0x03ul: return true; case 0x04ul: - return false; + return true; case 0x05ul: - return false; + return true; default: - return false; + return true; } } #endif @@ -8033,6 +8277,8 @@ static bool nrf52_errata_173(void) return true; case 0x01ul: return true; + case 0x02ul: + return true; default: return true; } @@ -8073,6 +8319,8 @@ static bool nrf52_errata_173(void) return true; case 0x02ul: return true; + case 0x03ul: + return true; default: return true; } @@ -8116,11 +8364,11 @@ static bool nrf52_errata_174(void) case 0x03ul: return true; case 0x04ul: - return false; + return true; case 0x05ul: - return false; + return true; default: - return false; + return true; } } #endif @@ -8189,6 +8437,8 @@ static bool nrf52_errata_176(void) return true; case 0x06ul: return true; + case 0x07ul: + return true; default: return true; } @@ -8208,11 +8458,11 @@ static bool nrf52_errata_176(void) case 0x03ul: return true; case 0x04ul: - return false; + return true; case 0x05ul: - return false; + return true; default: - return false; + return true; } } #endif @@ -8239,6 +8489,8 @@ static bool nrf52_errata_176(void) return true; case 0x01ul: return true; + case 0x02ul: + return true; default: return true; } @@ -8279,6 +8531,8 @@ static bool nrf52_errata_176(void) return true; case 0x02ul: return true; + case 0x03ul: + return true; default: return true; } @@ -8335,6 +8589,8 @@ static bool nrf52_errata_178(void) return true; case 0x06ul: return true; + case 0x07ul: + return true; default: return true; } @@ -8401,6 +8657,8 @@ static bool nrf52_errata_179(void) return true; case 0x06ul: return true; + case 0x07ul: + return true; default: return true; } @@ -8420,11 +8678,11 @@ static bool nrf52_errata_179(void) case 0x03ul: return true; case 0x04ul: - return false; + return true; case 0x05ul: - return false; + return true; default: - return false; + return true; } } #endif @@ -8567,6 +8825,8 @@ static bool nrf52_errata_181(void) return true; case 0x06ul: return false; + case 0x07ul: + return false; default: return false; } @@ -8634,6 +8894,8 @@ static bool nrf52_errata_182(void) return false; case 0x06ul: return true; + case 0x07ul: + return true; default: return true; } @@ -8702,6 +8964,8 @@ static bool nrf52_errata_183(void) return true; case 0x06ul: return true; + case 0x07ul: + return true; default: return true; } @@ -8721,11 +8985,11 @@ static bool nrf52_errata_183(void) case 0x03ul: return true; case 0x04ul: - return false; + return true; case 0x05ul: - return false; + return true; default: - return false; + return true; } } #endif @@ -8752,6 +9016,8 @@ static bool nrf52_errata_183(void) return true; case 0x01ul: return true; + case 0x02ul: + return true; default: return true; } @@ -8780,6 +9046,8 @@ static bool nrf52_errata_183(void) return true; case 0x02ul: return false; + case 0x03ul: + return false; default: return false; } @@ -8833,11 +9101,11 @@ static bool nrf52_errata_184(void) case 0x03ul: return true; case 0x04ul: - return false; + return true; case 0x05ul: - return false; + return true; default: - return false; + return true; } } #endif @@ -8864,6 +9132,8 @@ static bool nrf52_errata_184(void) return true; case 0x01ul: return true; + case 0x02ul: + return true; default: return true; } @@ -8904,6 +9174,8 @@ static bool nrf52_errata_184(void) return true; case 0x02ul: return true; + case 0x03ul: + return true; default: return true; } @@ -8997,11 +9269,11 @@ static bool nrf52_errata_187(void) case 0x03ul: return true; case 0x04ul: - return false; + return true; case 0x05ul: - return false; + return true; default: - return false; + return true; } } #endif @@ -9014,6 +9286,8 @@ static bool nrf52_errata_187(void) return true; case 0x01ul: return true; + case 0x02ul: + return true; default: return true; } @@ -9030,6 +9304,8 @@ static bool nrf52_errata_187(void) return true; case 0x02ul: return true; + case 0x03ul: + return true; default: return true; } @@ -9123,11 +9399,11 @@ static bool nrf52_errata_190(void) case 0x03ul: return true; case 0x04ul: - return false; + return true; case 0x05ul: - return false; + return true; default: - return false; + return true; } } #endif @@ -9140,6 +9416,8 @@ static bool nrf52_errata_190(void) return true; case 0x01ul: return true; + case 0x02ul: + return true; default: return true; } @@ -9156,6 +9434,8 @@ static bool nrf52_errata_190(void) return true; case 0x02ul: return false; + case 0x03ul: + return false; default: return false; } @@ -9199,11 +9479,11 @@ static bool nrf52_errata_191(void) case 0x03ul: return true; case 0x04ul: - return false; + return true; case 0x05ul: - return false; + return true; default: - return false; + return true; } } #endif @@ -9264,6 +9544,8 @@ static bool nrf52_errata_192(void) return true; case 0x06ul: return true; + case 0x07ul: + return true; default: return true; } @@ -9343,11 +9625,11 @@ static bool nrf52_errata_193(void) case 0x03ul: return true; case 0x04ul: - return false; + return true; case 0x05ul: - return false; + return true; default: - return false; + return true; } } #endif @@ -9410,6 +9692,8 @@ static bool nrf52_errata_194(void) return true; case 0x06ul: return true; + case 0x07ul: + return true; default: return true; } @@ -9429,11 +9713,11 @@ static bool nrf52_errata_194(void) case 0x03ul: return true; case 0x04ul: - return false; + return true; case 0x05ul: - return false; + return true; default: - return false; + return true; } } #endif @@ -9446,6 +9730,8 @@ static bool nrf52_errata_194(void) return true; case 0x01ul: return true; + case 0x02ul: + return true; default: return true; } @@ -9462,6 +9748,8 @@ static bool nrf52_errata_194(void) return true; case 0x02ul: return false; + case 0x03ul: + return false; default: return false; } @@ -9505,11 +9793,11 @@ static bool nrf52_errata_195(void) case 0x03ul: return true; case 0x04ul: - return false; + return true; case 0x05ul: - return false; + return true; default: - return false; + return true; } } #endif @@ -9572,6 +9860,8 @@ static bool nrf52_errata_196(void) return true; case 0x06ul: return true; + case 0x07ul: + return true; default: return true; } @@ -9591,11 +9881,11 @@ static bool nrf52_errata_196(void) case 0x03ul: return true; case 0x04ul: - return false; + return true; case 0x05ul: - return false; + return true; default: - return false; + return true; } } #endif @@ -9608,6 +9898,8 @@ static bool nrf52_errata_196(void) return true; case 0x01ul: return true; + case 0x02ul: + return true; default: return true; } @@ -9624,6 +9916,8 @@ static bool nrf52_errata_196(void) return true; case 0x02ul: return false; + case 0x03ul: + return false; default: return false; } @@ -9713,11 +10007,11 @@ static bool nrf52_errata_198(void) case 0x03ul: return true; case 0x04ul: - return false; + return true; case 0x05ul: - return false; + return true; default: - return false; + return true; } } #endif @@ -9759,11 +10053,11 @@ static bool nrf52_errata_199(void) case 0x03ul: return true; case 0x04ul: - return false; + return true; case 0x05ul: - return false; + return true; default: - return false; + return true; } } #endif @@ -9870,6 +10164,8 @@ static bool nrf52_errata_201(void) return true; case 0x06ul: return true; + case 0x07ul: + return true; default: return true; } @@ -10014,6 +10310,8 @@ static bool nrf52_errata_204(void) return true; case 0x06ul: return true; + case 0x07ul: + return true; default: return true; } @@ -10033,11 +10331,11 @@ static bool nrf52_errata_204(void) case 0x03ul: return true; case 0x04ul: - return false; + return true; case 0x05ul: - return false; + return true; default: - return false; + return true; } } #endif @@ -10093,11 +10391,11 @@ static bool nrf52_errata_208(void) case 0x03ul: return true; case 0x04ul: - return false; + return true; case 0x05ul: - return false; + return true; default: - return false; + return true; } } #endif @@ -10139,11 +10437,11 @@ static bool nrf52_errata_209(void) case 0x03ul: return true; case 0x04ul: - return false; + return true; case 0x05ul: - return false; + return true; default: - return false; + return true; } } #endif @@ -10212,6 +10510,8 @@ static bool nrf52_errata_210(void) return true; case 0x06ul: return true; + case 0x07ul: + return true; default: return true; } @@ -10231,11 +10531,11 @@ static bool nrf52_errata_210(void) case 0x03ul: return true; case 0x04ul: - return false; + return true; case 0x05ul: - return false; + return true; default: - return false; + return true; } } #endif @@ -10262,6 +10562,8 @@ static bool nrf52_errata_210(void) return true; case 0x01ul: return true; + case 0x02ul: + return true; default: return true; } @@ -10302,6 +10604,8 @@ static bool nrf52_errata_210(void) return true; case 0x02ul: return true; + case 0x03ul: + return true; default: return true; } @@ -10349,11 +10653,11 @@ static bool nrf52_errata_211(void) case 0x03ul: return true; case 0x04ul: - return false; + return true; case 0x05ul: - return false; + return true; default: - return false; + return true; } } #endif @@ -10366,6 +10670,8 @@ static bool nrf52_errata_211(void) return true; case 0x01ul: return true; + case 0x02ul: + return true; default: return true; } @@ -10382,6 +10688,8 @@ static bool nrf52_errata_211(void) return true; case 0x02ul: return true; + case 0x03ul: + return true; default: return true; } @@ -10452,6 +10760,8 @@ static bool nrf52_errata_212(void) return true; case 0x06ul: return true; + case 0x07ul: + return true; default: return true; } @@ -10471,11 +10781,11 @@ static bool nrf52_errata_212(void) case 0x03ul: return true; case 0x04ul: - return false; + return true; case 0x05ul: - return false; + return true; default: - return false; + return true; } } #endif @@ -10502,6 +10812,8 @@ static bool nrf52_errata_212(void) return true; case 0x01ul: return true; + case 0x02ul: + return true; default: return true; } @@ -10542,6 +10854,8 @@ static bool nrf52_errata_212(void) return true; case 0x02ul: return false; + case 0x03ul: + return false; default: return false; } @@ -10606,6 +10920,8 @@ static bool nrf52_errata_213(void) return true; case 0x06ul: return true; + case 0x07ul: + return true; default: return true; } @@ -10625,11 +10941,11 @@ static bool nrf52_errata_213(void) case 0x03ul: return true; case 0x04ul: - return false; + return true; case 0x05ul: - return false; + return true; default: - return false; + return true; } } #endif @@ -10697,11 +11013,11 @@ static bool nrf52_errata_214(void) case 0x03ul: return true; case 0x04ul: - return false; + return true; case 0x05ul: - return false; + return true; default: - return false; + return true; } } #endif @@ -10743,11 +11059,11 @@ static bool nrf52_errata_215(void) case 0x03ul: return true; case 0x04ul: - return false; + return true; case 0x05ul: - return false; + return true; default: - return false; + return true; } } #endif @@ -10789,11 +11105,11 @@ static bool nrf52_errata_216(void) case 0x03ul: return true; case 0x04ul: - return false; + return true; case 0x05ul: - return false; + return true; default: - return false; + return true; } } #endif @@ -10922,6 +11238,8 @@ static bool nrf52_errata_218(void) return true; case 0x06ul: return true; + case 0x07ul: + return true; default: return true; } @@ -10941,11 +11259,11 @@ static bool nrf52_errata_218(void) case 0x03ul: return true; case 0x04ul: - return false; + return true; case 0x05ul: - return false; + return true; default: - return false; + return true; } } #endif @@ -10958,6 +11276,8 @@ static bool nrf52_errata_218(void) return true; case 0x01ul: return true; + case 0x02ul: + return true; default: return true; } @@ -10974,6 +11294,8 @@ static bool nrf52_errata_218(void) return true; case 0x02ul: return false; + case 0x03ul: + return false; default: return false; } @@ -11044,6 +11366,8 @@ static bool nrf52_errata_219(void) return true; case 0x06ul: return true; + case 0x07ul: + return true; default: return true; } @@ -11063,11 +11387,11 @@ static bool nrf52_errata_219(void) case 0x03ul: return true; case 0x04ul: - return false; + return true; case 0x05ul: - return false; + return true; default: - return false; + return true; } } #endif @@ -11094,6 +11418,8 @@ static bool nrf52_errata_219(void) return true; case 0x01ul: return true; + case 0x02ul: + return true; default: return true; } @@ -11134,6 +11460,8 @@ static bool nrf52_errata_219(void) return true; case 0x02ul: return true; + case 0x03ul: + return true; default: return true; } @@ -11190,6 +11518,8 @@ static bool nrf52_errata_220(void) return true; case 0x06ul: return true; + case 0x07ul: + return true; default: return true; } @@ -11230,6 +11560,8 @@ static bool nrf52_errata_223(void) return true; case 0x01ul: return true; + case 0x02ul: + return true; default: return true; } @@ -11246,6 +11578,8 @@ static bool nrf52_errata_223(void) return true; case 0x02ul: return true; + case 0x03ul: + return true; default: return true; } @@ -11286,6 +11620,8 @@ static bool nrf52_errata_225(void) return true; case 0x01ul: return true; + case 0x02ul: + return true; default: return true; } @@ -11302,6 +11638,8 @@ static bool nrf52_errata_225(void) return true; case 0x02ul: return true; + case 0x03ul: + return true; default: return true; } @@ -11353,11 +11691,11 @@ static bool nrf52_errata_228(void) case 0x03ul: return true; case 0x04ul: - return false; + return true; case 0x05ul: - return false; + return true; default: - return false; + return true; } } #endif @@ -11384,6 +11722,8 @@ static bool nrf52_errata_228(void) return true; case 0x01ul: return true; + case 0x02ul: + return true; default: return true; } @@ -11412,6 +11752,8 @@ static bool nrf52_errata_228(void) return true; case 0x02ul: return true; + case 0x03ul: + return true; default: return true; } @@ -11452,6 +11794,8 @@ static bool nrf52_errata_230(void) return false; case 0x02ul: return false; + case 0x03ul: + return false; default: return false; } @@ -11492,6 +11836,8 @@ static bool nrf52_errata_231(void) return false; case 0x02ul: return false; + case 0x03ul: + return false; default: return false; } @@ -11591,11 +11937,11 @@ static bool nrf52_errata_233(void) case 0x03ul: return true; case 0x04ul: - return false; + return true; case 0x05ul: - return false; + return true; default: - return false; + return true; } } #endif @@ -11608,6 +11954,8 @@ static bool nrf52_errata_233(void) return true; case 0x01ul: return true; + case 0x02ul: + return true; default: return true; } @@ -11624,6 +11972,8 @@ static bool nrf52_errata_233(void) return true; case 0x02ul: return true; + case 0x03ul: + return true; default: return true; } @@ -11675,11 +12025,11 @@ static bool nrf52_errata_236(void) case 0x03ul: return true; case 0x04ul: - return false; + return true; case 0x05ul: - return false; + return true; default: - return false; + return true; } } #endif @@ -11706,6 +12056,8 @@ static bool nrf52_errata_236(void) return true; case 0x01ul: return true; + case 0x02ul: + return true; default: return true; } @@ -11734,6 +12086,8 @@ static bool nrf52_errata_236(void) return true; case 0x02ul: return false; + case 0x03ul: + return false; default: return false; } @@ -11785,11 +12139,11 @@ static bool nrf52_errata_237(void) case 0x03ul: return true; case 0x04ul: - return false; + return true; case 0x05ul: - return false; + return true; default: - return false; + return true; } } #endif @@ -11816,6 +12170,8 @@ static bool nrf52_errata_237(void) return true; case 0x01ul: return true; + case 0x02ul: + return true; default: return true; } @@ -11844,6 +12200,8 @@ static bool nrf52_errata_237(void) return true; case 0x02ul: return false; + case 0x03ul: + return false; default: return false; } @@ -11998,6 +12356,8 @@ static bool nrf52_errata_243(void) return true; case 0x01ul: return true; + case 0x02ul: + return true; default: return true; } @@ -12014,6 +12374,8 @@ static bool nrf52_errata_243(void) return true; case 0x02ul: return true; + case 0x03ul: + return true; default: return true; } @@ -12130,6 +12492,8 @@ static bool nrf52_errata_245(void) return true; case 0x06ul: return true; + case 0x07ul: + return true; default: return true; } @@ -12180,6 +12544,8 @@ static bool nrf52_errata_245(void) return true; case 0x01ul: return true; + case 0x02ul: + return true; default: return true; } @@ -12220,6 +12586,8 @@ static bool nrf52_errata_245(void) return true; case 0x02ul: return true; + case 0x03ul: + return true; default: return true; } @@ -12304,6 +12672,8 @@ static bool nrf52_errata_246(void) return true; case 0x01ul: return true; + case 0x02ul: + return true; default: return true; } @@ -12344,6 +12714,8 @@ static bool nrf52_errata_246(void) return true; case 0x02ul: return true; + case 0x03ul: + return true; default: return true; } @@ -12426,6 +12798,8 @@ static bool nrf52_errata_248(void) return true; case 0x01ul: return true; + case 0x02ul: + return true; default: return true; } @@ -12454,6 +12828,8 @@ static bool nrf52_errata_248(void) return true; case 0x02ul: return true; + case 0x03ul: + return true; default: return true; } @@ -12464,7 +12840,11 @@ static bool nrf52_errata_248(void) } /* ========= Errata 249 ========= */ -#if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) +#if defined (NRF52820_XXAA) || defined (DEVELOP_IN_NRF52820) \ + || defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832) \ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) \ + || defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833) \ + || defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) #define NRF52_ERRATA_249_PRESENT 1 #else #define NRF52_ERRATA_249_PRESENT 0 @@ -12479,10 +12859,35 @@ static bool nrf52_errata_249(void) #ifndef NRF52_SERIES return false; #else - #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + #if defined (NRF52820_XXAA) || defined (DEVELOP_IN_NRF52820)\ + || defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833)\ + || defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) uint32_t var1 = *(uint32_t *)0x10000130ul; uint32_t var2 = *(uint32_t *)0x10000134ul; #endif + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + if (var1 == 0x06) + { + switch(var2) + { + case 0x03ul: + return false; + case 0x04ul: + return false; + case 0x05ul: + return false; + case 0x06ul: + return false; + case 0x07ul: + return true; + default: + return true; + } + } + #endif #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) if (var1 == 0x08) { @@ -12505,6 +12910,40 @@ static bool nrf52_errata_249(void) } } #endif + #if defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833) + if (var1 == 0x0D) + { + switch(var2) + { + case 0x00ul: + return false; + case 0x01ul: + return false; + case 0x02ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52820_XXAA) || defined (DEVELOP_IN_NRF52820) + if (var1 == 0x10) + { + switch(var2) + { + case 0x00ul: + return false; + case 0x01ul: + return false; + case 0x02ul: + return false; + case 0x03ul: + return true; + default: + return true; + } + } + #endif return false; #endif } @@ -12540,6 +12979,8 @@ static bool nrf52_errata_250(void) return true; case 0x01ul: return true; + case 0x02ul: + return true; default: return true; } @@ -12556,6 +12997,8 @@ static bool nrf52_errata_250(void) return true; case 0x02ul: return true; + case 0x03ul: + return true; default: return true; } diff --git a/mdk/nrf52_name_change.h b/mdk/nrf52_name_change.h index 7bc08c377b..6b1d66648f 100644 --- a/mdk/nrf52_name_change.h +++ b/mdk/nrf52_name_change.h @@ -1,6 +1,8 @@ /* -Copyright (c) 2010 - 2020, Nordic Semiconductor ASA All rights reserved. +Copyright (c) 2010 - 2021, Nordic Semiconductor ASA All rights reserved. + +SPDX-License-Identifier: BSD-3-Clause Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: diff --git a/mdk/nrf52_to_nrf52810.h b/mdk/nrf52_to_nrf52810.h index 13b7e98b94..1b3e431151 100644 --- a/mdk/nrf52_to_nrf52810.h +++ b/mdk/nrf52_to_nrf52810.h @@ -1,6 +1,8 @@ /* -Copyright (c) 2010 - 2020, Nordic Semiconductor ASA All rights reserved. +Copyright (c) 2010 - 2021, Nordic Semiconductor ASA All rights reserved. + +SPDX-License-Identifier: BSD-3-Clause Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: diff --git a/mdk/nrf52_to_nrf52833.h b/mdk/nrf52_to_nrf52833.h index ed2b4c0835..15944c34a0 100644 --- a/mdk/nrf52_to_nrf52833.h +++ b/mdk/nrf52_to_nrf52833.h @@ -1,6 +1,8 @@ /* -Copyright (c) 2010 - 2020, Nordic Semiconductor ASA All rights reserved. +Copyright (c) 2010 - 2021, Nordic Semiconductor ASA All rights reserved. + +SPDX-License-Identifier: BSD-3-Clause Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: diff --git a/mdk/nrf52_to_nrf52840.h b/mdk/nrf52_to_nrf52840.h index ab171791b8..01bf9e5354 100644 --- a/mdk/nrf52_to_nrf52840.h +++ b/mdk/nrf52_to_nrf52840.h @@ -1,6 +1,8 @@ /* -Copyright (c) 2010 - 2020, Nordic Semiconductor ASA All rights reserved. +Copyright (c) 2010 - 2021, Nordic Semiconductor ASA All rights reserved. + +SPDX-License-Identifier: BSD-3-Clause Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: diff --git a/mdk/nrf5340_application.h b/mdk/nrf5340_application.h index 55cb9bd71a..c130c5b33e 100644 --- a/mdk/nrf5340_application.h +++ b/mdk/nrf5340_application.h @@ -1,27 +1,28 @@ /* - * Copyright (c) 2010 - 2020, Nordic Semiconductor ASA All rights reserved.Redistribution and use in so - * urce and binary forms, with or withoutmodification, are permitted provided that the following condit - * ions are met:1. Redistributions of source code must retain the above copyright notice, this list of - * conditions and the following disclaimer.2. Redistributions in binary form must reproduce the above c - * opyright notice, this list of conditions and the following disclaimer in the documentation and/or ot - * her materials provided with the distribution.3. Neither the name of Nordic Semiconductor ASA nor the - * names of its contributors may be used to endorse or promote products derived from this software wit - * hout specific prior written permission.THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRI - * BUTORS "AS IS"AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THEIMPLIED WARRA - * NTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSEARE DISCLAIMED. IN NO EVENT SHALL NORD - * IC SEMICONDUCTOR ASA OR CONTRIBUTORS BELIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLA - * RY, ORCONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OFSUBSTITUTE GOODS OR SERVIC - * ES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESSINTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIAB - * ILITY, WHETHER INCONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)ARISING IN A - * NY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THEPOSSIBILITY OF SUCH DAMAGE. + * Copyright (c) 2010 - 2021, Nordic Semiconductor ASA All rights reserved.SPDX-License-Identifier: BSD + * -3-ClauseRedistribution and use in source and binary forms, with or withoutmodification, are permitt + * ed provided that the following conditions are met:1. Redistributions of source code must retain the + * above copyright notice, this list of conditions and the following disclaimer.2. Redistributions in b + * inary form must reproduce the above copyright notice, this list of conditions and the following disc + * laimer in the documentation and/or other materials provided with the distribution.3. Neither the nam + * e of Nordic Semiconductor ASA nor the names of its contributors may be used to endorse or promote pr + * oducts derived from this software without specific prior written permission.THIS SOFTWARE IS PROVIDE + * D BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, + * BUT NOT LIMITED TO, THEIMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSEA + * RE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BELIABLE FOR ANY DIRECT, I + * NDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, ORCONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PRO + * CUREMENT OFSUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESSINTERRUPTION) HOW + * EVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER INCONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE)ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THEP + * OSSIBILITY OF SUCH DAMAGE. * * @file nrf5340_application.h * @brief CMSIS HeaderFile * @version 1 - * @date 04. November 2020 - * @note Generated by SVDConv V3.3.35 on Wednesday, 04.11.2020 13:48:08 + * @date 29. April 2021 + * @note Generated by SVDConv V3.3.35 on Thursday, 29.04.2021 12:43:49 * from File 'nrf5340_application.svd', - * last modified on Wednesday, 04.11.2020 12:48:02 + * last modified on Thursday, 29.04.2021 10:43:41 */ @@ -74,11 +75,11 @@ typedef enum { CACHE_IRQn = 1, /*!< 1 CACHE */ SPU_IRQn = 3, /*!< 3 SPU */ CLOCK_POWER_IRQn = 5, /*!< 5 CLOCK_POWER */ - SPIM0_SPIS0_TWIM0_TWIS0_UARTE0_IRQn= 8, /*!< 8 SPIM0_SPIS0_TWIM0_TWIS0_UARTE0 */ - SPIM1_SPIS1_TWIM1_TWIS1_UARTE1_IRQn= 9, /*!< 9 SPIM1_SPIS1_TWIM1_TWIS1_UARTE1 */ + SERIAL0_IRQn = 8, /*!< 8 SERIAL0 */ + SERIAL1_IRQn = 9, /*!< 9 SERIAL1 */ SPIM4_IRQn = 10, /*!< 10 SPIM4 */ - SPIM2_SPIS2_TWIM2_TWIS2_UARTE2_IRQn= 11, /*!< 11 SPIM2_SPIS2_TWIM2_TWIS2_UARTE2 */ - SPIM3_SPIS3_TWIM3_TWIS3_UARTE3_IRQn= 12, /*!< 12 SPIM3_SPIS3_TWIM3_TWIS3_UARTE3 */ + SERIAL2_IRQn = 11, /*!< 11 SERIAL2 */ + SERIAL3_IRQn = 12, /*!< 12 SERIAL3 */ GPIOTE0_IRQn = 13, /*!< 13 GPIOTE0 */ SAADC_IRQn = 14, /*!< 14 SAADC */ TIMER0_IRQn = 15, /*!< 15 TIMER0 */ @@ -211,7 +212,7 @@ typedef struct { * @brief FICR_TRIMCNF [TRIMCNF] (Unspecified) */ typedef struct { - __IOM uint32_t* ADDR; /*!< (@ 0x00000000) Description cluster: Address of the PAR register + __IM uint32_t* ADDR; /*!< (@ 0x00000000) Description cluster: Address of the PAR register which will be written */ __IM uint32_t DATA; /*!< (@ 0x00000004) Description cluster: Data */ } FICR_TRIMCNF_Type; /*!< Size = 8 (0x8) */ @@ -292,7 +293,7 @@ typedef struct { */ typedef struct { __IOM uint32_t TRACECLK; /*!< (@ 0x00000000) Pin configuration for TRACECLK */ - __IOM uint32_t TRACEDATA0; /*!< (@ 0x00000004) Pin configuration for TRACEDATA[0] and SWO */ + __IOM uint32_t TRACEDATA0; /*!< (@ 0x00000004) Pin configuration for TRACEDATA[0] */ __IOM uint32_t TRACEDATA1; /*!< (@ 0x00000008) Pin configuration for TRACEDATA[1] */ __IOM uint32_t TRACEDATA2; /*!< (@ 0x0000000C) Pin configuration for TRACEDATA[2] */ __IOM uint32_t TRACEDATA3; /*!< (@ 0x00000010) Pin configuration for TRACEDATA[3] */ @@ -361,7 +362,7 @@ typedef struct { */ typedef struct { __IOM uint32_t PERM; /*!< (@ 0x00000000) Description cluster: Select between secure and - non-secure attribute for the DPPI channels. */ + non-secure attribute for the DPPI channels */ __IOM uint32_t LOCK; /*!< (@ 0x00000004) Description cluster: Prevent further modification of the corresponding PERM register */ } SPU_DPPI_Type; /*!< Size = 8 (0x8) */ @@ -373,7 +374,7 @@ typedef struct { typedef struct { __IOM uint32_t PERM; /*!< (@ 0x00000000) Description cluster: Select between secure and non-secure attribute for pins 0 to 31 of - port n. */ + port n */ __IOM uint32_t LOCK; /*!< (@ 0x00000004) Description cluster: Prevent further modification of the corresponding PERM register */ } SPU_GPIOPORT_Type; /*!< Size = 8 (0x8) */ @@ -908,8 +909,8 @@ typedef struct { __IM uint32_t RESERVED; __IOM uint32_t IO0; /*!< (@ 0x0000000C) Pin select for serial data MOSI/IO0. */ __IOM uint32_t IO1; /*!< (@ 0x00000010) Pin select for serial data MISO/IO1. */ - __IOM uint32_t IO2; /*!< (@ 0x00000014) Pin select for serial data IO2. */ - __IOM uint32_t IO3; /*!< (@ 0x00000018) Pin select for serial data IO3. */ + __IOM uint32_t IO2; /*!< (@ 0x00000014) Pin select for serial data WP/IO2. */ + __IOM uint32_t IO3; /*!< (@ 0x00000018) Pin select for serial data HOLD/IO3. */ } QSPI_PSEL_Type; /*!< Size = 28 (0x1c) */ @@ -1141,12 +1142,10 @@ typedef struct { /*!< (@ 0x00FF0000) FICR_S Struc typedef struct { /*!< (@ 0x00FF8000) UICR_S Structure */ __IOM uint32_t APPROTECT; /*!< (@ 0x00000000) Access port protection */ - __IM uint32_t RESERVED[2]; - __IOM uint32_t EXTSUPPLY; /*!< (@ 0x0000000C) Enable external circuitry to be supplied from - VDD pin. Applicable in 'High voltage mode' - only. */ - __IOM uint32_t VREGHVOUT; /*!< (@ 0x00000010) GPIO reference voltage / external output supply - voltage in 'High voltage mode'. */ + __IM uint32_t RESERVED[3]; + __IOM uint32_t VREGHVOUT; /*!< (@ 0x00000010) Output voltage from the high voltage (VREGH) + regulator stage. The maximum output voltage + from this stage is given as VDDH - VREGHDROP. */ __IOM uint32_t HFXOCNT; /*!< (@ 0x00000014) HFXO startup counter */ __IM uint32_t RESERVED1; __IOM uint32_t SECUREAPPROTECT; /*!< (@ 0x0000001C) Secure access port protection */ @@ -1224,7 +1223,8 @@ typedef struct { /*!< (@ 0xE0080000) TAD_S Struct __IM uint32_t RESERVED1[317]; __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable debug domain and aquire selected GPIOs */ __IOM TAD_PSEL_Type PSEL; /*!< (@ 0x00000504) Unspecified */ - __IOM uint32_t TRACEPORTSPEED; /*!< (@ 0x00000518) Clocking options for the Trace Port debug interface. */ + __IOM uint32_t TRACEPORTSPEED; /*!< (@ 0x00000518) Clocking options for the Trace Port debug interface + Reset behavior is the same as debug components */ } NRF_TAD_Type; /*!< Size = 1308 (0x51c) */ @@ -1296,17 +1296,17 @@ typedef struct { /*!< (@ 0x50001000) CACHE_S Stru __IM uint32_t RESERVED[256]; __IOM CACHE_PROFILING_Type PROFILING[2]; /*!< (@ 0x00000400) Unspecified */ __IM uint32_t RESERVED1[48]; - __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable cache */ - __OM uint32_t INVALIDATE; /*!< (@ 0x00000504) Invalidate the cache */ - __OM uint32_t ERASE; /*!< (@ 0x00000508) Erase the cache */ - __IOM uint32_t PROFILINGENABLE; /*!< (@ 0x0000050C) Enable the profiling counters */ - __OM uint32_t PROFILINGCLEAR; /*!< (@ 0x00000510) Clear the profiling counters */ - __IOM uint32_t MODE; /*!< (@ 0x00000514) Cache mode. Switching from Cache to RAM mode + __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable cache. */ + __OM uint32_t INVALIDATE; /*!< (@ 0x00000504) Invalidate the cache. */ + __OM uint32_t ERASE; /*!< (@ 0x00000508) Erase the cache. */ + __IOM uint32_t PROFILINGENABLE; /*!< (@ 0x0000050C) Enable the profiling counters. */ + __OM uint32_t PROFILINGCLEAR; /*!< (@ 0x00000510) Clear the profiling counters. */ + __IOM uint32_t MODE; /*!< (@ 0x00000514) Cache mode. Switching from Cache to Ram mode causes the RAM to be cleared. Switching from RAM to Cache mode causes the cache to be invalidated. */ - __IOM uint32_t DEBUGLOCK; /*!< (@ 0x00000518) Lock debug mode Ignored in RAM mode. */ - __IOM uint32_t ERASESTATUS; /*!< (@ 0x0000051C) Cache erase status */ + __IOM uint32_t DEBUGLOCK; /*!< (@ 0x00000518) Lock debug mode. */ + __IOM uint32_t ERASESTATUS; /*!< (@ 0x0000051C) Cache erase status. */ __IOM uint32_t WRITELOCK; /*!< (@ 0x00000520) Lock cache updates. Prevents updating of cache content on cache misses, but will continue to lookup instruction/data fetches in content @@ -1573,7 +1573,7 @@ typedef struct { /*!< (@ 0x40006000) CTRLAP_NS St __IOM CTRLAPPERI_APPROTECT_Type APPROTECT; /*!< (@ 0x00000540) Unspecified */ __IOM CTRLAPPERI_SECUREAPPROTECT_Type SECUREAPPROTECT;/*!< (@ 0x00000548) Unspecified */ __IM uint32_t RESERVED3[44]; - __IM uint32_t STATUS; /*!< (@ 0x00000600) Status bits for CTRL-AP peripheral */ + __IM uint32_t STATUS; /*!< (@ 0x00000600) Status bits for CTRL-AP peripheral. */ } NRF_CTRLAPPERI_Type; /*!< Size = 1540 (0x604) */ @@ -1627,7 +1627,7 @@ typedef struct { /*!< (@ 0x40008000) SPIM0_NS Str __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ __IM uint32_t RESERVED16[61]; __IOM uint32_t STALLSTAT; /*!< (@ 0x00000400) Stall status for EasyDMA RAM accesses. The fields - in this register is set to STALL by hardware + in this register are set to STALL by hardware whenever a stall occurres and can be cleared (set to NOSTALL) by the CPU. */ __IM uint32_t RESERVED17[63]; @@ -1925,8 +1925,7 @@ typedef struct { /*!< (@ 0x40008000) UARTE0_NS St __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ __IM uint32_t RESERVED17[93]; - __IOM uint32_t ERRORSRC; /*!< (@ 0x00000480) Error source Note : this register is read / write - one to clear. */ + __IOM uint32_t ERRORSRC; /*!< (@ 0x00000480) Error source */ __IM uint32_t RESERVED18[31]; __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable UART */ __IM uint32_t RESERVED19; @@ -2010,7 +2009,7 @@ typedef struct { /*!< (@ 0x4000E000) SAADC_NS Str RAM */ __OM uint32_t TASKS_SAMPLE; /*!< (@ 0x00000004) Take one ADC sample, if scan is enabled all channels are sampled */ - __OM uint32_t TASKS_STOP; /*!< (@ 0x00000008) Stop the ADC and terminate any on-going conversion */ + __OM uint32_t TASKS_STOP; /*!< (@ 0x00000008) Stop the ADC and terminate any ongoing conversion */ __OM uint32_t TASKS_CALIBRATEOFFSET; /*!< (@ 0x0000000C) Starts offset auto-calibration */ __IM uint32_t RESERVED[28]; __IOM uint32_t SUBSCRIBE_START; /*!< (@ 0x00000080) Subscribe configuration for task START */ @@ -2024,7 +2023,7 @@ typedef struct { /*!< (@ 0x4000E000) SAADC_NS Str on the mode, multiple conversions might be needed for a result to be transferred to RAM. */ - __IOM uint32_t EVENTS_RESULTDONE; /*!< (@ 0x0000010C) A result is ready to get transferred to RAM. */ + __IOM uint32_t EVENTS_RESULTDONE; /*!< (@ 0x0000010C) A result is ready to get transferred to RAM */ __IOM uint32_t EVENTS_CALIBRATEDONE; /*!< (@ 0x00000110) Calibration is complete */ __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000114) The ADC has stopped */ __IOM SAADC_EVENTS_CH_Type EVENTS_CH[8]; /*!< (@ 0x00000118) Peripheral events. */ @@ -2163,8 +2162,9 @@ typedef struct { /*!< (@ 0x40014000) RTC0_NS Stru __IOM uint32_t EVTENCLR; /*!< (@ 0x00000348) Disable event routing */ __IM uint32_t RESERVED10[110]; __IM uint32_t COUNTER; /*!< (@ 0x00000504) Current counter value */ - __IOM uint32_t PRESCALER; /*!< (@ 0x00000508) 12-bit prescaler for counter frequency (32768/(PRESCALER+1)). - Must be written when RTC is stopped. */ + __IOM uint32_t PRESCALER; /*!< (@ 0x00000508) 12-bit prescaler for counter frequency (32768 + / (PRESCALER + 1)). Must be written when + RTC is stopped. */ __IM uint32_t RESERVED11[13]; __IOM uint32_t CC[4]; /*!< (@ 0x00000540) Description collection: Compare register n */ } NRF_RTC_Type; /*!< Size = 1360 (0x550) */ @@ -2207,8 +2207,8 @@ typedef struct { /*!< (@ 0x40017000) DPPIC_NS Str */ typedef struct { /*!< (@ 0x40018000) WDT0_NS Structure */ - __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start the watchdog */ - __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stop the watchdog timer. */ + __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start WDT */ + __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stop WDT */ __IM uint32_t RESERVED[30]; __IOM uint32_t SUBSCRIBE_START; /*!< (@ 0x00000080) Subscribe configuration for task START */ __IOM uint32_t SUBSCRIBE_STOP; /*!< (@ 0x00000084) Subscribe configuration for task STOP */ @@ -2232,7 +2232,7 @@ typedef struct { /*!< (@ 0x40018000) WDT0_NS Stru __IOM uint32_t RREN; /*!< (@ 0x00000508) Enable register for reload request registers */ __IOM uint32_t CONFIG; /*!< (@ 0x0000050C) Configuration register */ __IM uint32_t RESERVED7[4]; - __OM uint32_t TSEN; /*!< (@ 0x00000520) Task Stop Enable */ + __OM uint32_t TSEN; /*!< (@ 0x00000520) Task stop enable */ __IM uint32_t RESERVED8[55]; __OM uint32_t RR[8]; /*!< (@ 0x00000600) Description collection: Reload request n */ } NRF_WDT_Type; /*!< Size = 1568 (0x620) */ @@ -2736,7 +2736,7 @@ typedef struct { /*!< (@ 0x4002D000) NFCT_NS Stru __IOM uint32_t ERRORSTATUS; /*!< (@ 0x00000404) NFC Error Status register */ __IM uint32_t RESERVED16; __IOM NFCT_FRAMESTATUS_Type FRAMESTATUS; /*!< (@ 0x0000040C) Unspecified */ - __IM uint32_t NFCTAGSTATE; /*!< (@ 0x00000410) NfcTag state register */ + __IM uint32_t NFCTAGSTATE; /*!< (@ 0x00000410) Current operating state of NFC tag */ __IM uint32_t RESERVED17[3]; __IM uint32_t SLEEPSTATE; /*!< (@ 0x00000420) Sleep state during automatic collision resolution */ __IM uint32_t RESERVED18[6]; @@ -2755,7 +2755,7 @@ typedef struct { /*!< (@ 0x4002D000) NFCT_NS Stru __IOM uint32_t MODULATIONCTRL; /*!< (@ 0x0000052C) Enables the modulation output to a GPIO pin which can be connected to a second external antenna. */ __IM uint32_t RESERVED21[2]; - __IOM uint32_t MODULATIONPSEL; /*!< (@ 0x00000538) Pin select for Modulation control. */ + __IOM uint32_t MODULATIONPSEL; /*!< (@ 0x00000538) Pin select for Modulation control */ __IM uint32_t RESERVED22[21]; __IOM uint32_t NFCID1_LAST; /*!< (@ 0x00000590) Last NFCID1 part (4, 7 or 10 bytes ID) */ __IOM uint32_t NFCID1_2ND_LAST; /*!< (@ 0x00000594) Second last NFCID1 part (7 or 10 bytes ID) */ @@ -3071,7 +3071,7 @@ typedef struct { /*!< (@ 0x40039000) NVMC_NS Stru __IM uint32_t RESERVED4[3]; __IOM uint32_t ERASEPAGEPARTIALCFG; /*!< (@ 0x0000051C) Register for partial erase configuration */ __IM uint32_t RESERVED5[25]; - __IOM uint32_t CONFIGNS; /*!< (@ 0x00000584) Unspecified */ + __IOM uint32_t CONFIGNS; /*!< (@ 0x00000584) Non-secure configuration register */ __OM uint32_t WRITEUICRNS; /*!< (@ 0x00000588) Non-secure APPROTECT enable register */ } NRF_NVMC_Type; /*!< Size = 1420 (0x58c) */ diff --git a/mdk/nrf5340_application.svd b/mdk/nrf5340_application.svd index 92b9c595d3..b6faf3369e 100644 --- a/mdk/nrf5340_application.svd +++ b/mdk/nrf5340_application.svd @@ -8,7 +8,9 @@ 1 nRF53 reference description for system-on-chip with dual ARM 32-bit Cortex-M33 microcontrollers -Copyright (c) 2010 - 2020, Nordic Semiconductor ASA All rights reserved. +Copyright (c) 2010 - 2021, Nordic Semiconductor ASA All rights reserved. + +SPDX-License-Identifier: BSD-3-Clause Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: @@ -188,7 +190,7 @@ POSSIBILITY OF SUCH DAMAGE. V - Valid bit. + Valid bit 30 30 read-only @@ -350,8 +352,8 @@ POSSIBILITY OF SUCH DAMAGE. 31 - QF - QFxx - 94 pin QFN + QK + QKxx - 94-pin aQFN 0x2000 @@ -546,7 +548,7 @@ POSSIBILITY OF SUCH DAMAGE. ADDR Description cluster: Address of the PAR register which will be written 0x000 - read-write + read-only 0xFFFFFFFF uint32_t * @@ -888,14 +890,14 @@ POSSIBILITY OF SUCH DAMAGE. PALL Blocks debugger read/write access to all CPU registers and - memory mapped addresses Using any value except Unprotected will lead to the protection being enabled. + memory mapped addresses. 0 31 Unprotected Unprotected - 0xFFFFFFFF + 0x50FA50FA Protected @@ -906,43 +908,16 @@ POSSIBILITY OF SUCH DAMAGE. - - EXTSUPPLY - Enable external circuitry to be supplied from VDD pin. Applicable in 'High voltage mode' only. - 0x00C - read-write - 0xFFFFFFFF - - - EXTSUPPLY - Enable external circuitry to be supplied from VDD pin (output of VREGH stage). - 0 - 0 - - - Disabled - No current can be drawn from the VDD pin. - 1 - - - Enabled - It is allowed to supply external circuitry from the VDD pin. - 0 - - - - - VREGHVOUT - GPIO reference voltage / external output supply voltage in 'High voltage mode'. + Output voltage from the high voltage (VREGH) regulator stage. The maximum output voltage from this stage is given as VDDH - VREGHDROP. 0x010 read-write 0xFFFFFFFF VREGHVOUT - VREGH regulator output voltage. The maximum output voltage from this stage is given as VDDH - VEXDIF. + VREGH regulator output voltage. 0 2 @@ -1027,14 +1002,14 @@ POSSIBILITY OF SUCH DAMAGE. PALL Blocks debugger read/write access to all secure CPU registers and secure memory - mapped addresses. Using any value except Unprotected will lead to the protection being enabled. + mapped addresses. 0 31 Unprotected Unprotected - 0xFFFFFFFF + 0x50FA50FA Protected @@ -2378,21 +2353,21 @@ POSSIBILITY OF SUCH DAMAGE. MAJOR - Major classification of the type of the debug component as specified in the ARM Architecture Specification for this + Major classification of the type of the debug component as specified in the Arm Architecture Specification for this debug and trace component. 0 3 Controller - Indicates that this component allows a debugger to control other components in a CoreSight SoC-400 system. - 0b0100 + Indicates that this component allows a debugger to control other components in an Arm CoreSight SoC-400 system. + 4 SUB - Sub-classification of the type of the debug component as specified in the ARM Architecture Specification within + Sub-classification of the type of the debug component as specified in the Arm Architecture Specification within the major classification as specified in the MAJOR field. 4 7 @@ -2400,7 +2375,7 @@ POSSIBILITY OF SUCH DAMAGE. Crosstrigger Indicates that this component is a sub-triggering component. - 0b0001 + 1 @@ -2421,8 +2396,8 @@ POSSIBILITY OF SUCH DAMAGE. Code - JEDEC continuation code - 0b0100 + JEDEC continuation code. + 4 @@ -2490,7 +2465,7 @@ POSSIBILITY OF SUCH DAMAGE. PartnumberH Indicates bits[11:8] of the part number of the component. - 0b1101 + 13 @@ -2502,8 +2477,8 @@ POSSIBILITY OF SUCH DAMAGE. Arm - ARM. Bits[3:0] of the JEDEC JEP106 Identity Code - 0b1011 + Arm. Bits[3:0] of the JEDEC JEP106 Identity Code + 11 @@ -2524,8 +2499,8 @@ POSSIBILITY OF SUCH DAMAGE. Arm - ARM. Bits[6:4] of the JEDEC JEP106 Identity Code - 0b011 + Arm. Bits[6:4] of the JEDEC JEP106 Identity Code + 3 @@ -2544,7 +2519,7 @@ POSSIBILITY OF SUCH DAMAGE. Rev0p0 This device is at r0p0 - 0b0000 + 0 @@ -2567,14 +2542,14 @@ POSSIBILITY OF SUCH DAMAGE. Unmodified Indicates that the customer has not modified this component. - 0b000 + 0 REVAND Indicates minor errata fixes specific to the revision of the component being used, for example metal fixes after - implementation. In most cases, this field is 0b0000. ARM recommends that the component designers ensure that a + implementation. In most cases, this field is 0b0000. Arm recommends that the component designers ensure that a metal fix can change this field if required, for example, by driving it from registers that reset to 0b0000. 4 7 @@ -2582,7 +2557,7 @@ POSSIBILITY OF SUCH DAMAGE. NoErrata Indicates that there are no errata fixes to this component. - 0b000 + 0 @@ -2626,7 +2601,7 @@ POSSIBILITY OF SUCH DAMAGE. Value Bits[11:8] of the identification code. - 0b0000 + 0 @@ -2640,7 +2615,7 @@ POSSIBILITY OF SUCH DAMAGE. Coresight Indicates that the component is a CoreSight component. - 0b1001 + 9 @@ -2820,7 +2795,7 @@ POSSIBILITY OF SUCH DAMAGE. TRACEDATA0 - Pin configuration for TRACEDATA[0] and SWO + Pin configuration for TRACEDATA[0] 0x004 read-write 0xFFFFFFFF @@ -2833,7 +2808,7 @@ POSSIBILITY OF SUCH DAMAGE. Tracedata0 - TRACEDATA0/SWO pin + TRACEDATA0 pin 11 @@ -2981,7 +2956,7 @@ POSSIBILITY OF SUCH DAMAGE. TRACEPORTSPEED - Clocking options for the Trace Port debug interface. + Clocking options for the Trace Port debug interface Reset behavior is the same as debug components 0x518 read-write 0x00000000 @@ -3003,13 +2978,13 @@ POSSIBILITY OF SUCH DAMAGE. 1 - 8MHz - Trace Port clock is: 8MHz + 16MHz + Trace Port clock is: 16MHz 2 - 4MHz - Trace Port clock is: 4MHz + 8MHz + Trace Port clock is: 8MHz 3 @@ -4020,7 +3995,7 @@ POSSIBILITY OF SUCH DAMAGE. ENABLE - Enable cache + Enable cache. 0x500 read-write @@ -4046,7 +4021,7 @@ POSSIBILITY OF SUCH DAMAGE. INVALIDATE - Invalidate the cache + Invalidate the cache. 0x504 write-only @@ -4067,7 +4042,7 @@ POSSIBILITY OF SUCH DAMAGE. ERASE - Erase the cache + Erase the cache. 0x508 write-only @@ -4088,7 +4063,7 @@ POSSIBILITY OF SUCH DAMAGE. PROFILINGENABLE - Enable the profiling counters + Enable the profiling counters. 0x50C read-write @@ -4114,7 +4089,7 @@ POSSIBILITY OF SUCH DAMAGE. PROFILINGCLEAR - Clear the profiling counters + Clear the profiling counters. 0x510 write-only @@ -4135,7 +4110,7 @@ POSSIBILITY OF SUCH DAMAGE. MODE - Cache mode. Switching from Cache to RAM mode causes the RAM to be cleared. Switching from RAM to Cache mode causes the cache to be invalidated. + Cache mode. Switching from Cache to Ram mode causes the RAM to be cleared. Switching from RAM to Cache mode causes the cache to be invalidated. 0x514 read-write @@ -4161,7 +4136,7 @@ POSSIBILITY OF SUCH DAMAGE. DEBUGLOCK - Lock debug mode Ignored in RAM mode. + Lock debug mode. 0x518 read-writeonce @@ -4187,7 +4162,7 @@ POSSIBILITY OF SUCH DAMAGE. ERASESTATUS - Cache erase status + Cache erase status. 0x51C read-write @@ -4678,18 +4653,18 @@ POSSIBILITY OF SUCH DAMAGE. TZM - Show ARM TrustZone status + Show Arm TrustZone status 0 0 NotAvailable - ARM TrustZone support not available + Arm TrustZone support not available 0 Enabled - ARM TrustZone support is available + Arm TrustZone support is available 1 @@ -4883,583 +4858,583 @@ POSSIBILITY OF SUCH DAMAGE. 0x480 PERM - Description cluster: Select between secure and non-secure attribute for the DPPI channels. + Description cluster: Select between secure and non-secure attribute for the DPPI channels 0x000 read-write 0xFFFFFFFF CHANNEL0 - Select secure attribute. + Select secure attribute 0 0 Secure - Channel0 has its secure attribute set + Channel 0 has its secure attribute set 1 NonSecure - Channel0 has its non-secure attribute set + Channel 0 has its non-secure attribute set 0 CHANNEL1 - Select secure attribute. + Select secure attribute 1 1 Secure - Channel1 has its secure attribute set + Channel 1 has its secure attribute set 1 NonSecure - Channel1 has its non-secure attribute set + Channel 1 has its non-secure attribute set 0 CHANNEL2 - Select secure attribute. + Select secure attribute 2 2 Secure - Channel2 has its secure attribute set + Channel 2 has its secure attribute set 1 NonSecure - Channel2 has its non-secure attribute set + Channel 2 has its non-secure attribute set 0 CHANNEL3 - Select secure attribute. + Select secure attribute 3 3 Secure - Channel3 has its secure attribute set + Channel 3 has its secure attribute set 1 NonSecure - Channel3 has its non-secure attribute set + Channel 3 has its non-secure attribute set 0 CHANNEL4 - Select secure attribute. + Select secure attribute 4 4 Secure - Channel4 has its secure attribute set + Channel 4 has its secure attribute set 1 NonSecure - Channel4 has its non-secure attribute set + Channel 4 has its non-secure attribute set 0 CHANNEL5 - Select secure attribute. + Select secure attribute 5 5 Secure - Channel5 has its secure attribute set + Channel 5 has its secure attribute set 1 NonSecure - Channel5 has its non-secure attribute set + Channel 5 has its non-secure attribute set 0 CHANNEL6 - Select secure attribute. + Select secure attribute 6 6 Secure - Channel6 has its secure attribute set + Channel 6 has its secure attribute set 1 NonSecure - Channel6 has its non-secure attribute set + Channel 6 has its non-secure attribute set 0 CHANNEL7 - Select secure attribute. + Select secure attribute 7 7 Secure - Channel7 has its secure attribute set + Channel 7 has its secure attribute set 1 NonSecure - Channel7 has its non-secure attribute set + Channel 7 has its non-secure attribute set 0 CHANNEL8 - Select secure attribute. + Select secure attribute 8 8 Secure - Channel8 has its secure attribute set + Channel 8 has its secure attribute set 1 NonSecure - Channel8 has its non-secure attribute set + Channel 8 has its non-secure attribute set 0 CHANNEL9 - Select secure attribute. + Select secure attribute 9 9 Secure - Channel9 has its secure attribute set + Channel 9 has its secure attribute set 1 NonSecure - Channel9 has its non-secure attribute set + Channel 9 has its non-secure attribute set 0 CHANNEL10 - Select secure attribute. + Select secure attribute 10 10 Secure - Channel10 has its secure attribute set + Channel 10 has its secure attribute set 1 NonSecure - Channel10 has its non-secure attribute set + Channel 10 has its non-secure attribute set 0 CHANNEL11 - Select secure attribute. + Select secure attribute 11 11 Secure - Channel11 has its secure attribute set + Channel 11 has its secure attribute set 1 NonSecure - Channel11 has its non-secure attribute set + Channel 11 has its non-secure attribute set 0 CHANNEL12 - Select secure attribute. + Select secure attribute 12 12 Secure - Channel12 has its secure attribute set + Channel 12 has its secure attribute set 1 NonSecure - Channel12 has its non-secure attribute set + Channel 12 has its non-secure attribute set 0 CHANNEL13 - Select secure attribute. + Select secure attribute 13 13 Secure - Channel13 has its secure attribute set + Channel 13 has its secure attribute set 1 NonSecure - Channel13 has its non-secure attribute set + Channel 13 has its non-secure attribute set 0 CHANNEL14 - Select secure attribute. + Select secure attribute 14 14 Secure - Channel14 has its secure attribute set + Channel 14 has its secure attribute set 1 NonSecure - Channel14 has its non-secure attribute set + Channel 14 has its non-secure attribute set 0 CHANNEL15 - Select secure attribute. + Select secure attribute 15 15 Secure - Channel15 has its secure attribute set + Channel 15 has its secure attribute set 1 NonSecure - Channel15 has its non-secure attribute set + Channel 15 has its non-secure attribute set 0 CHANNEL16 - Select secure attribute. + Select secure attribute 16 16 Secure - Channel16 has its secure attribute set + Channel 16 has its secure attribute set 1 NonSecure - Channel16 has its non-secure attribute set + Channel 16 has its non-secure attribute set 0 CHANNEL17 - Select secure attribute. + Select secure attribute 17 17 Secure - Channel17 has its secure attribute set + Channel 17 has its secure attribute set 1 NonSecure - Channel17 has its non-secure attribute set + Channel 17 has its non-secure attribute set 0 CHANNEL18 - Select secure attribute. + Select secure attribute 18 18 Secure - Channel18 has its secure attribute set + Channel 18 has its secure attribute set 1 NonSecure - Channel18 has its non-secure attribute set + Channel 18 has its non-secure attribute set 0 CHANNEL19 - Select secure attribute. + Select secure attribute 19 19 Secure - Channel19 has its secure attribute set + Channel 19 has its secure attribute set 1 NonSecure - Channel19 has its non-secure attribute set + Channel 19 has its non-secure attribute set 0 CHANNEL20 - Select secure attribute. + Select secure attribute 20 20 Secure - Channel20 has its secure attribute set + Channel 20 has its secure attribute set 1 NonSecure - Channel20 has its non-secure attribute set + Channel 20 has its non-secure attribute set 0 CHANNEL21 - Select secure attribute. + Select secure attribute 21 21 Secure - Channel21 has its secure attribute set + Channel 21 has its secure attribute set 1 NonSecure - Channel21 has its non-secure attribute set + Channel 21 has its non-secure attribute set 0 CHANNEL22 - Select secure attribute. + Select secure attribute 22 22 Secure - Channel22 has its secure attribute set + Channel 22 has its secure attribute set 1 NonSecure - Channel22 has its non-secure attribute set + Channel 22 has its non-secure attribute set 0 CHANNEL23 - Select secure attribute. + Select secure attribute 23 23 Secure - Channel23 has its secure attribute set + Channel 23 has its secure attribute set 1 NonSecure - Channel23 has its non-secure attribute set + Channel 23 has its non-secure attribute set 0 CHANNEL24 - Select secure attribute. + Select secure attribute 24 24 Secure - Channel24 has its secure attribute set + Channel 24 has its secure attribute set 1 NonSecure - Channel24 has its non-secure attribute set + Channel 24 has its non-secure attribute set 0 CHANNEL25 - Select secure attribute. + Select secure attribute 25 25 Secure - Channel25 has its secure attribute set + Channel 25 has its secure attribute set 1 NonSecure - Channel25 has its non-secure attribute set + Channel 25 has its non-secure attribute set 0 CHANNEL26 - Select secure attribute. + Select secure attribute 26 26 Secure - Channel26 has its secure attribute set + Channel 26 has its secure attribute set 1 NonSecure - Channel26 has its non-secure attribute set + Channel 26 has its non-secure attribute set 0 CHANNEL27 - Select secure attribute. + Select secure attribute 27 27 Secure - Channel27 has its secure attribute set + Channel 27 has its secure attribute set 1 NonSecure - Channel27 has its non-secure attribute set + Channel 27 has its non-secure attribute set 0 CHANNEL28 - Select secure attribute. + Select secure attribute 28 28 Secure - Channel28 has its secure attribute set + Channel 28 has its secure attribute set 1 NonSecure - Channel28 has its non-secure attribute set + Channel 28 has its non-secure attribute set 0 CHANNEL29 - Select secure attribute. + Select secure attribute 29 29 Secure - Channel29 has its secure attribute set + Channel 29 has its secure attribute set 1 NonSecure - Channel29 has its non-secure attribute set + Channel 29 has its non-secure attribute set 0 CHANNEL30 - Select secure attribute. + Select secure attribute 30 30 Secure - Channel30 has its secure attribute set + Channel 30 has its secure attribute set 1 NonSecure - Channel30 has its non-secure attribute set + Channel 30 has its non-secure attribute set 0 CHANNEL31 - Select secure attribute. + Select secure attribute 31 31 Secure - Channel31 has its secure attribute set + Channel 31 has its secure attribute set 1 NonSecure - Channel31 has its non-secure attribute set + Channel 31 has its non-secure attribute set 0 @@ -5503,7 +5478,7 @@ POSSIBILITY OF SUCH DAMAGE. 0x4C0 PERM - Description cluster: Select between secure and non-secure attribute for pins 0 to 31 of port n. + Description cluster: Select between secure and non-secure attribute for pins 0 to 31 of port n 0x000 read-write 0xFFFFFFFF @@ -6173,42 +6148,42 @@ POSSIBILITY OF SUCH DAMAGE. 32 - The region n is defined as non-secure callable with a 32-byte size + The region n is defined as non-secure callable with size 32 bytes 1 64 - The region n is defined as non-secure callable with a 64-byte size + The region n is defined as non-secure callable with size 64 bytes 2 128 - The region n is defined as non-secure callable with a 128-byte size + The region n is defined as non-secure callable with size 128 bytes 3 256 - The region n is defined as non-secure callable with a 256-byte size + The region n is defined as non-secure callable with size 256 bytes 4 512 - The region n is defined as non-secure callable with a 512-byte size + The region n is defined as non-secure callable with size 512 bytes 5 1024 - The region n is defined as non-secure callable with a 1024-byte size + The region n is defined as non-secure callable with size 1024 bytes 6 2048 - The region n is defined as non-secure callable with a 2048-byte size + The region n is defined as non-secure callable with size 2048 bytes 7 4096 - The region n is defined as non-secure callable with a 4096-byte size + The region n is defined as non-secure callable with size 4096 bytes 8 @@ -6293,42 +6268,42 @@ POSSIBILITY OF SUCH DAMAGE. 32 - The region n is defined as non-secure callable with a 32-byte size + The region n is defined as non-secure callable with size 32 bytes 1 64 - The region n is defined as non-secure callable with a 64-byte size + The region n is defined as non-secure callable with size 64 bytes 2 128 - The region n is defined as non-secure callable with a 128-byte size + The region n is defined as non-secure callable with size 128 bytes 3 256 - The region n is defined as non-secure callable with a 256-byte size + The region n is defined as non-secure callable with size 256 bytes 4 512 - The region n is defined as non-secure callable with a 512-byte size + The region n is defined as non-secure callable with size 512 bytes 5 1024 - The region n is defined as non-secure callable with a 1024-byte size + The region n is defined as non-secure callable with size 1024 bytes 6 2048 - The region n is defined as non-secure callable with a 2048-byte size + The region n is defined as non-secure callable with size 2048 bytes 7 4096 - The region n is defined as non-secure callable with a 4096-byte size + The region n is defined as non-secure callable with size 4096 bytes 8 @@ -6584,7 +6559,7 @@ POSSIBILITY OF SUCH DAMAGE. SECUREMAPPING - Define configuration capabilities for TrustZone Cortex-M secure attribute + Define configuration capabilities for Arm TrustZone Cortex-M secure attribute 0 1 read-only @@ -6613,7 +6588,7 @@ POSSIBILITY OF SUCH DAMAGE. DMA - Indicate if the peripheral has DMA capabilities and if DMA transfer can be assigned to a different security attribute than the peripheral itself + Indicates if the peripheral has DMA capabilities and if DMA transfer can be assigned to a different security attribute than the peripheral itself 2 3 read-only @@ -6819,8 +6794,8 @@ POSSIBILITY OF SUCH DAMAGE. 2 - C11PF - 11 pF internal load capacitance + C9PF + 9 pF internal load capacitance 3 @@ -8568,11 +8543,6 @@ POSSIBILITY OF SUCH DAMAGE. 0 1 - - LFULP - 32.768 kHz ultra-low power RC oscillator - 0 - LFRC 32.768 kHz RC oscillator @@ -8641,11 +8611,6 @@ POSSIBILITY OF SUCH DAMAGE. 0 1 - - LFULP - 32.768 kHz ultra-low power RC oscillator - 0 - LFRC 32.768 kHz RC oscillator @@ -8863,11 +8828,6 @@ POSSIBILITY OF SUCH DAMAGE. 0 1 - - LFULP - 32.768 kHz ultra-low power RC oscillator - 0 - LFRC 32.768 kHz RC oscillator @@ -10086,7 +10046,7 @@ POSSIBILITY OF SUCH DAMAGE. DISABLE This register disables the ERASEPROTECT register and performs an ERASEALL operation. 0x004 - read-write + read-writeonce 0x00000000 @@ -10140,7 +10100,9 @@ POSSIBILITY OF SUCH DAMAGE. KEY - Disable APPROTECT and enable debug access to non-secure mode until the next pin reset if the KEY fields match. The current APPROTECT value as configured from UICR is bypassed if the value of the KEY fields are non-zero and the KEY fields match on both the CPU and debugger sides. + If the value of the KEY field is non-zero, and the KEY fields match on both the + CPU and debugger sides, disable APPROTECT and enable debug access to non-secure mode until + the next pin reset, brown-out reset, power-on reset, or watchog timer reset. After reset the debugger side register has a fixed KEY value. To enable debug access, both CTRL-AP and UICR.APPROTECT protection needs to be disabled. 0 31 @@ -10189,7 +10151,9 @@ POSSIBILITY OF SUCH DAMAGE. KEY - Disable SECUREAPPROTECT and enable debug of secure mode until the next pin reset if the KEY fields match. The current SECUREAPPROTECT value as configured from UICR is bypassed if the value of the KEY fields are non-zero and the KEY fields match on both the CPU and debugger sides. + If the value of the KEY field is non-zero, and the KEY fields match on both the + CPU and debugger sides, disable SECUREAPPROTECT and enable debug access to secure mode until + the next pin reset, brown-out reset, power-on reset, or watchog timer reset. After reset the debugger side register has a fixed KEY value. To enable debug access, both CTRL-AP and UICR.SECUREAPPROTECT protection needs to be disabled. 0 31 @@ -10198,43 +10162,43 @@ POSSIBILITY OF SUCH DAMAGE. STATUS - Status bits for CTRL-AP peripheral + Status bits for CTRL-AP peripheral. 0x600 read-only 0x00000000 - APPROTECT - Status bit for access port protection in non-secure mode + UICRAPPROTECT + Status bit for UICR part of access port protection at last reset. 0 0 - Disabled - Non-secure mode access port protection is currently disabled + Enabled + APPROTECT was enabled in UICR 0 - Enabled - Non-secure mode access port protection is currently enabled + Disabled + APPROTECT wasdisabled in UICR 1 - SECUREAPPROTECT - Status bit for access port protection in secure mode + UICRSECUREAPPROTECT + Status bit for UICR part of secure access port protection at last reset. 1 1 - Disabled - Secure mode access port protection is currently disabled + Enabled + SECUREAPPROTECT was enabled in UICR 0 - Enabled - Secure mode access port protection is currently enabled + Disabled + SECUREAPPROTECT was disabled in UICR 1 @@ -10281,7 +10245,7 @@ POSSIBILITY OF SUCH DAMAGE. registers - SPIM0_SPIS0_TWIM0_TWIS0_UARTE0 + SERIAL0 8 SPIM @@ -11094,7 +11058,7 @@ POSSIBILITY OF SUCH DAMAGE. STALLSTAT - Stall status for EasyDMA RAM accesses. The fields in this register is set to STALL by hardware whenever a stall occurres and can be cleared (set to NOSTALL) by the CPU. + Stall status for EasyDMA RAM accesses. The fields in this register are set to STALL by hardware whenever a stall occurres and can be cleared (set to NOSTALL) by the CPU. 0x400 read-write 0x00000000 @@ -11747,7 +11711,7 @@ POSSIBILITY OF SUCH DAMAGE. registers - SPIM0_SPIS0_TWIM0_TWIS0_UARTE0 + SERIAL0 8 SPIS @@ -12776,7 +12740,7 @@ POSSIBILITY OF SUCH DAMAGE. registers - SPIM0_SPIS0_TWIM0_TWIS0_UARTE0 + SERIAL0 8 TWIM @@ -13519,24 +13483,6 @@ POSSIBILITY OF SUCH DAMAGE. - - LASTRX_SUSPEND - Shortcut between event LASTRX and task SUSPEND - 11 - 11 - - - Disabled - Disable shortcut - 0 - - - Enabled - Enable shortcut - 1 - - - LASTRX_STOP Shortcut between event LASTRX and task STOP @@ -14476,7 +14422,7 @@ POSSIBILITY OF SUCH DAMAGE. registers - SPIM0_SPIS0_TWIM0_TWIS0_UARTE0 + SERIAL0 8 TWIS @@ -15655,7 +15601,7 @@ POSSIBILITY OF SUCH DAMAGE. MATCH - Which of the addresses in {ADDRESS} matched the incoming address + Indication of which address in {ADDRESS} that matched the incoming address 0 0 @@ -16013,7 +15959,7 @@ POSSIBILITY OF SUCH DAMAGE. registers - SPIM0_SPIS0_TWIM0_TWIS0_UARTE0 + SERIAL0 8 UARTE @@ -17768,7 +17714,7 @@ POSSIBILITY OF SUCH DAMAGE. ERRORSRC - Error source Note : this register is read / write one to clear. + Error source 0x480 read-write oneToClear @@ -18140,7 +18086,7 @@ POSSIBILITY OF SUCH DAMAGE. Baud1M - 1Mega baud + 1 megabaud 0x10000000 @@ -18334,7 +18280,7 @@ POSSIBILITY OF SUCH DAMAGE. - SPIM0_SPIS0_TWIM0_TWIS0_UARTE0 + SERIAL0 8 @@ -18346,7 +18292,7 @@ POSSIBILITY OF SUCH DAMAGE. - SPIM0_SPIS0_TWIM0_TWIS0_UARTE0 + SERIAL0 8 @@ -18358,7 +18304,7 @@ POSSIBILITY OF SUCH DAMAGE. - SPIM0_SPIS0_TWIM0_TWIS0_UARTE0 + SERIAL0 8 @@ -18370,7 +18316,7 @@ POSSIBILITY OF SUCH DAMAGE. - SPIM0_SPIS0_TWIM0_TWIS0_UARTE0 + SERIAL0 8 @@ -18382,7 +18328,7 @@ POSSIBILITY OF SUCH DAMAGE. - SPIM0_SPIS0_TWIM0_TWIS0_UARTE0 + SERIAL0 8 @@ -18393,7 +18339,7 @@ POSSIBILITY OF SUCH DAMAGE. - SPIM1_SPIS1_TWIM1_TWIS1_UARTE1 + SERIAL1 9 @@ -18405,7 +18351,7 @@ POSSIBILITY OF SUCH DAMAGE. - SPIM1_SPIS1_TWIM1_TWIS1_UARTE1 + SERIAL1 9 @@ -18417,7 +18363,7 @@ POSSIBILITY OF SUCH DAMAGE. - SPIM1_SPIS1_TWIM1_TWIS1_UARTE1 + SERIAL1 9 @@ -18429,7 +18375,7 @@ POSSIBILITY OF SUCH DAMAGE. - SPIM1_SPIS1_TWIM1_TWIS1_UARTE1 + SERIAL1 9 @@ -18441,7 +18387,7 @@ POSSIBILITY OF SUCH DAMAGE. - SPIM1_SPIS1_TWIM1_TWIS1_UARTE1 + SERIAL1 9 @@ -18452,7 +18398,7 @@ POSSIBILITY OF SUCH DAMAGE. - SPIM1_SPIS1_TWIM1_TWIS1_UARTE1 + SERIAL1 9 @@ -18464,7 +18410,7 @@ POSSIBILITY OF SUCH DAMAGE. - SPIM1_SPIS1_TWIM1_TWIS1_UARTE1 + SERIAL1 9 @@ -18476,7 +18422,7 @@ POSSIBILITY OF SUCH DAMAGE. - SPIM1_SPIS1_TWIM1_TWIS1_UARTE1 + SERIAL1 9 @@ -18488,7 +18434,7 @@ POSSIBILITY OF SUCH DAMAGE. - SPIM1_SPIS1_TWIM1_TWIS1_UARTE1 + SERIAL1 9 @@ -18500,7 +18446,7 @@ POSSIBILITY OF SUCH DAMAGE. - SPIM1_SPIS1_TWIM1_TWIS1_UARTE1 + SERIAL1 9 @@ -18533,7 +18479,7 @@ POSSIBILITY OF SUCH DAMAGE. - SPIM2_SPIS2_TWIM2_TWIS2_UARTE2 + SERIAL2 11 @@ -18545,7 +18491,7 @@ POSSIBILITY OF SUCH DAMAGE. - SPIM2_SPIS2_TWIM2_TWIS2_UARTE2 + SERIAL2 11 @@ -18557,7 +18503,7 @@ POSSIBILITY OF SUCH DAMAGE. - SPIM2_SPIS2_TWIM2_TWIS2_UARTE2 + SERIAL2 11 @@ -18569,7 +18515,7 @@ POSSIBILITY OF SUCH DAMAGE. - SPIM2_SPIS2_TWIM2_TWIS2_UARTE2 + SERIAL2 11 @@ -18581,7 +18527,7 @@ POSSIBILITY OF SUCH DAMAGE. - SPIM2_SPIS2_TWIM2_TWIS2_UARTE2 + SERIAL2 11 @@ -18592,7 +18538,7 @@ POSSIBILITY OF SUCH DAMAGE. - SPIM2_SPIS2_TWIM2_TWIS2_UARTE2 + SERIAL2 11 @@ -18604,7 +18550,7 @@ POSSIBILITY OF SUCH DAMAGE. - SPIM2_SPIS2_TWIM2_TWIS2_UARTE2 + SERIAL2 11 @@ -18616,7 +18562,7 @@ POSSIBILITY OF SUCH DAMAGE. - SPIM2_SPIS2_TWIM2_TWIS2_UARTE2 + SERIAL2 11 @@ -18628,7 +18574,7 @@ POSSIBILITY OF SUCH DAMAGE. - SPIM2_SPIS2_TWIM2_TWIS2_UARTE2 + SERIAL2 11 @@ -18640,7 +18586,7 @@ POSSIBILITY OF SUCH DAMAGE. - SPIM2_SPIS2_TWIM2_TWIS2_UARTE2 + SERIAL2 11 @@ -18651,7 +18597,7 @@ POSSIBILITY OF SUCH DAMAGE. - SPIM3_SPIS3_TWIM3_TWIS3_UARTE3 + SERIAL3 12 @@ -18663,7 +18609,7 @@ POSSIBILITY OF SUCH DAMAGE. - SPIM3_SPIS3_TWIM3_TWIS3_UARTE3 + SERIAL3 12 @@ -18675,7 +18621,7 @@ POSSIBILITY OF SUCH DAMAGE. - SPIM3_SPIS3_TWIM3_TWIS3_UARTE3 + SERIAL3 12 @@ -18687,7 +18633,7 @@ POSSIBILITY OF SUCH DAMAGE. - SPIM3_SPIS3_TWIM3_TWIS3_UARTE3 + SERIAL3 12 @@ -18699,7 +18645,7 @@ POSSIBILITY OF SUCH DAMAGE. - SPIM3_SPIS3_TWIM3_TWIS3_UARTE3 + SERIAL3 12 @@ -18710,7 +18656,7 @@ POSSIBILITY OF SUCH DAMAGE. - SPIM3_SPIS3_TWIM3_TWIS3_UARTE3 + SERIAL3 12 @@ -18722,7 +18668,7 @@ POSSIBILITY OF SUCH DAMAGE. - SPIM3_SPIS3_TWIM3_TWIS3_UARTE3 + SERIAL3 12 @@ -18734,7 +18680,7 @@ POSSIBILITY OF SUCH DAMAGE. - SPIM3_SPIS3_TWIM3_TWIS3_UARTE3 + SERIAL3 12 @@ -18746,7 +18692,7 @@ POSSIBILITY OF SUCH DAMAGE. - SPIM3_SPIS3_TWIM3_TWIS3_UARTE3 + SERIAL3 12 @@ -18758,7 +18704,7 @@ POSSIBILITY OF SUCH DAMAGE. - SPIM3_SPIS3_TWIM3_TWIS3_UARTE3 + SERIAL3 12 @@ -19752,13 +19698,13 @@ POSSIBILITY OF SUCH DAMAGE. TASKS_STOP - Stop the ADC and terminate any on-going conversion + Stop the ADC and terminate any ongoing conversion 0x008 write-only TASKS_STOP - Stop the ADC and terminate any on-going conversion + Stop the ADC and terminate any ongoing conversion 0 0 @@ -19996,13 +19942,13 @@ POSSIBILITY OF SUCH DAMAGE. EVENTS_RESULTDONE - A result is ready to get transferred to RAM. + A result is ready to get transferred to RAM 0x10C read-write EVENTS_RESULTDONE - A result is ready to get transferred to RAM. + A result is ready to get transferred to RAM 0 0 @@ -22012,7 +21958,7 @@ POSSIBILITY OF SUCH DAMAGE. Ready - ADC is ready. No on-going conversion. + ADC is ready. No ongoing conversion. 0 @@ -22377,7 +22323,7 @@ POSSIBILITY OF SUCH DAMAGE. SE - Single ended, PSELN will be ignored, negative input to ADC shorted to GND + Single-ended, PSELN will be ignored, negative input to ADC shorted to GND 0 @@ -22535,7 +22481,7 @@ POSSIBILITY OF SUCH DAMAGE. CC - Capture and compare value. Sample rate is 16 MHz/CC + Capture and compare value; sample rate is 16 MHz/CC 0 10 @@ -25230,7 +25176,7 @@ POSSIBILITY OF SUCH DAMAGE. PRESCALER - 12-bit prescaler for counter frequency (32768/(PRESCALER+1)). Must be written when RTC is stopped. + 12-bit prescaler for counter frequency (32768 / (PRESCALER + 1)). Must be written when RTC is stopped. 0x508 read-write @@ -28376,13 +28322,13 @@ POSSIBILITY OF SUCH DAMAGE. TASKS_START - Start the watchdog + Start WDT 0x000 write-only TASKS_START - Start the watchdog + Start WDT 0 0 @@ -28397,13 +28343,13 @@ POSSIBILITY OF SUCH DAMAGE. TASKS_STOP - Stop the watchdog timer. + Stop WDT 0x004 write-only TASKS_STOP - Stop the watchdog timer. + Stop WDT 0 0 @@ -28848,13 +28794,13 @@ POSSIBILITY OF SUCH DAMAGE. RUNSTATUSWDT - Indicates whether or not the watchdog is running + Indicates whether or not WDT is running 0 0 NotRunning - Watchdog not running + Watchdog is not running 0 @@ -29196,54 +29142,54 @@ POSSIBILITY OF SUCH DAMAGE. SLEEP - Configure the watchdog to either be paused, or kept running, while the CPU is sleeping + Configure WDT to either be paused, or kept running, while the CPU is sleeping 0 0 Pause - Pause watchdog while the CPU is sleeping + Pause WDT while the CPU is sleeping 0 Run - Keep the watchdog running while the CPU is sleeping + Keep WDT running while the CPU is sleeping 1 HALT - Configure the watchdog to either be paused, or kept running, while the CPU is halted by the debugger + Configure WDT to either be paused, or kept running, while the CPU is halted by the debugger 3 3 Pause - Pause watchdog while the CPU is halted by the debugger + Pause WDT while the CPU is halted by the debugger 0 Run - Keep the watchdog running while the CPU is halted by the debugger + Keep WDT running while the CPU is halted by the debugger 1 STOPEN - Allow stopping the watchdog + Allow stopping WDT 6 6 Disable - Do not allow stopping the watchdog + Do not allow stopping WDT 0 Enable - Allow stopping the watchdog + Allow stopping WDT 1 @@ -29252,20 +29198,20 @@ POSSIBILITY OF SUCH DAMAGE. TSEN - Task Stop Enable + Task stop enable 0x520 write-only 0x00000000 TSEN - Task stop enable register + Allow stopping WDT 0 31 Enable - Value to allow stopping the watchdog + Value to allow stopping WDT 0x6E524635 @@ -36255,7 +36201,7 @@ POSSIBILITY OF SUCH DAMAGE. 32MDIV21 - 32 MHz / 21 = 1.5238095 Deprecated, use MCKFREQ equation. + 32 MHz / 21 = 1.5238095 MHz Deprecated, use MCKFREQ equation. 0x0C000000 @@ -36389,12 +36335,12 @@ POSSIBILITY OF SUCH DAMAGE. 32Bit - 32-bit sample. + 32 bit sample. 3 8BitIn16 - 8 bit sample in a 16 bit half-frame. + 8 bit sample in a 16-bit half-frame. 4 @@ -39853,7 +39799,7 @@ POSSIBILITY OF SUCH DAMAGE. IO2 - Pin select for serial data IO2. + Pin select for serial data WP/IO2. 0x014 read-write 0xFFFFFFFF @@ -39892,7 +39838,7 @@ POSSIBILITY OF SUCH DAMAGE. IO3 - Pin select for serial data IO3. + Pin select for serial data HOLD/IO3. 0x018 read-write 0xFFFFFFFF @@ -40412,6 +40358,11 @@ POSSIBILITY OF SUCH DAMAGE. Mode 0: Data are captured on the clock rising edge and data is output on a falling edge. Base level of clock is 0 (CPOL=0, CPHA=0). 0 + + MODE3 + Mode 3: Data are captured on the clock rising edge and data is output on a falling edge. Base level of clock is 1 (CPOL=1, CPHA=1). + 1 + @@ -40536,12 +40487,12 @@ POSSIBILITY OF SUCH DAMAGE. OpByte0 - Send opcode, byte0. + Send opcode, BYTE0. 2 All - Send opcode, byte0, byte1. + Send opcode, BYTE0, BYTE1. 3 @@ -40700,7 +40651,7 @@ POSSIBILITY OF SUCH DAMAGE. LFEN - Enable long frame mode. When enabled, a custom instruction transaction has to be ended by writing the LFSTOP field. + Enable Long frame mode. When enabled, a custom instruction transaction has to be ended by writing the LFSTOP field. 16 16 @@ -40800,7 +40751,15 @@ POSSIBILITY OF SUCH DAMAGE. SPI interface timing. 0x640 read-write - 0x00000600 + 0x00000200 + + + RXDELAY + Timing related to sampling of the input serial data. The value of RXDELAY specifies the number of prescaled 192 MHz cycles delay from the the rising edge of the SPI Clock (SCK) until the input serial data is sampled. For example, if RXDELAY is set to 0, the input serial data is sampled on the rising edge of SCK. + 8 + 10 + + @@ -43306,7 +43265,7 @@ POSSIBILITY OF SUCH DAMAGE. NFCTAGSTATE - NfcTag state register + Current operating state of NFC tag 0x410 read-only @@ -43432,7 +43391,7 @@ POSSIBILITY OF SUCH DAMAGE. FRAMEDELAYMIN - Minimum frame delay in number of 13.56 MHz clocks + Minimum frame delay in number of 13.56 MHz clock cycles 0 15 @@ -43447,7 +43406,7 @@ POSSIBILITY OF SUCH DAMAGE. FRAMEDELAYMAX - Maximum frame delay in number of 13.56 MHz clocks + Maximum frame delay in number of 13.56 MHz clock cycles 0 19 @@ -43620,7 +43579,7 @@ POSSIBILITY OF SUCH DAMAGE. TXDATABYTES - Number of complete bytes that shall be included in the frame, excluding CRC, parity and framing + Number of complete bytes that shall be included in the frame, excluding CRC, parity, and framing. 3 11 @@ -43756,7 +43715,7 @@ POSSIBILITY OF SUCH DAMAGE. MODULATIONPSEL - Pin select for Modulation control. + Pin select for Modulation control 0x538 read-write 0xFFFFFFFF @@ -43771,7 +43730,7 @@ POSSIBILITY OF SUCH DAMAGE. PORT Port number 5 - 6 + 5 CONNECT @@ -50214,7 +50173,7 @@ POSSIBILITY OF SUCH DAMAGE. OneDir - Full buffer dedicated to either iso IN or OUT + Full buffer dedicated to either ISO IN or OUT 0x0000 @@ -51510,7 +51469,7 @@ POSSIBILITY OF SUCH DAMAGE. Busy - NVMC is busy (on-going write or erase operation) + NVMC is busy (ongoing write or erase operation) 0 @@ -51595,7 +51554,7 @@ POSSIBILITY OF SUCH DAMAGE. ERASEALL - Erase all non-volatile memory including UICR registers. Note that erasing must be enabled by setting CONFIG.WEN = Een before the non-volatile memory can be erased. + Erase all non-volatile memory including UICR registers. Before the non-volatile memory can be erased, erasing must be enabled by setting CONFIG.WEN=Een. 0 0 @@ -51631,7 +51590,7 @@ POSSIBILITY OF SUCH DAMAGE. CONFIGNS - Unspecified + Non-secure configuration register 0x584 read-write @@ -56982,7 +56941,7 @@ POSSIBILITY OF SUCH DAMAGE. PIN0 - Status on whether PIN0 has met criteria set in PIN_CNF0.SENSE register. Write '1' to clear. + Status on whether PIN[0] has met criteria set in PIN_CNF[0].SENSE register. Write '1' to clear. 0 0 @@ -57000,7 +56959,7 @@ POSSIBILITY OF SUCH DAMAGE. PIN1 - Status on whether PIN1 has met criteria set in PIN_CNF1.SENSE register. Write '1' to clear. + Status on whether PIN[1] has met criteria set in PIN_CNF[1].SENSE register. Write '1' to clear. 1 1 @@ -57018,7 +56977,7 @@ POSSIBILITY OF SUCH DAMAGE. PIN2 - Status on whether PIN2 has met criteria set in PIN_CNF2.SENSE register. Write '1' to clear. + Status on whether PIN[2] has met criteria set in PIN_CNF[2].SENSE register. Write '1' to clear. 2 2 @@ -57036,7 +56995,7 @@ POSSIBILITY OF SUCH DAMAGE. PIN3 - Status on whether PIN3 has met criteria set in PIN_CNF3.SENSE register. Write '1' to clear. + Status on whether PIN[3] has met criteria set in PIN_CNF[3].SENSE register. Write '1' to clear. 3 3 @@ -57054,7 +57013,7 @@ POSSIBILITY OF SUCH DAMAGE. PIN4 - Status on whether PIN4 has met criteria set in PIN_CNF4.SENSE register. Write '1' to clear. + Status on whether PIN[4] has met criteria set in PIN_CNF[4].SENSE register. Write '1' to clear. 4 4 @@ -57072,7 +57031,7 @@ POSSIBILITY OF SUCH DAMAGE. PIN5 - Status on whether PIN5 has met criteria set in PIN_CNF5.SENSE register. Write '1' to clear. + Status on whether PIN[5] has met criteria set in PIN_CNF[5].SENSE register. Write '1' to clear. 5 5 @@ -57090,7 +57049,7 @@ POSSIBILITY OF SUCH DAMAGE. PIN6 - Status on whether PIN6 has met criteria set in PIN_CNF6.SENSE register. Write '1' to clear. + Status on whether PIN[6] has met criteria set in PIN_CNF[6].SENSE register. Write '1' to clear. 6 6 @@ -57108,7 +57067,7 @@ POSSIBILITY OF SUCH DAMAGE. PIN7 - Status on whether PIN7 has met criteria set in PIN_CNF7.SENSE register. Write '1' to clear. + Status on whether PIN[7] has met criteria set in PIN_CNF[7].SENSE register. Write '1' to clear. 7 7 @@ -57126,7 +57085,7 @@ POSSIBILITY OF SUCH DAMAGE. PIN8 - Status on whether PIN8 has met criteria set in PIN_CNF8.SENSE register. Write '1' to clear. + Status on whether PIN[8] has met criteria set in PIN_CNF[8].SENSE register. Write '1' to clear. 8 8 @@ -57144,7 +57103,7 @@ POSSIBILITY OF SUCH DAMAGE. PIN9 - Status on whether PIN9 has met criteria set in PIN_CNF9.SENSE register. Write '1' to clear. + Status on whether PIN[9] has met criteria set in PIN_CNF[9].SENSE register. Write '1' to clear. 9 9 @@ -57162,7 +57121,7 @@ POSSIBILITY OF SUCH DAMAGE. PIN10 - Status on whether PIN10 has met criteria set in PIN_CNF10.SENSE register. Write '1' to clear. + Status on whether PIN[10] has met criteria set in PIN_CNF[10].SENSE register. Write '1' to clear. 10 10 @@ -57180,7 +57139,7 @@ POSSIBILITY OF SUCH DAMAGE. PIN11 - Status on whether PIN11 has met criteria set in PIN_CNF11.SENSE register. Write '1' to clear. + Status on whether PIN[11] has met criteria set in PIN_CNF[11].SENSE register. Write '1' to clear. 11 11 @@ -57198,7 +57157,7 @@ POSSIBILITY OF SUCH DAMAGE. PIN12 - Status on whether PIN12 has met criteria set in PIN_CNF12.SENSE register. Write '1' to clear. + Status on whether PIN[12] has met criteria set in PIN_CNF[12].SENSE register. Write '1' to clear. 12 12 @@ -57216,7 +57175,7 @@ POSSIBILITY OF SUCH DAMAGE. PIN13 - Status on whether PIN13 has met criteria set in PIN_CNF13.SENSE register. Write '1' to clear. + Status on whether PIN[13] has met criteria set in PIN_CNF[13].SENSE register. Write '1' to clear. 13 13 @@ -57234,7 +57193,7 @@ POSSIBILITY OF SUCH DAMAGE. PIN14 - Status on whether PIN14 has met criteria set in PIN_CNF14.SENSE register. Write '1' to clear. + Status on whether PIN[14] has met criteria set in PIN_CNF[14].SENSE register. Write '1' to clear. 14 14 @@ -57252,7 +57211,7 @@ POSSIBILITY OF SUCH DAMAGE. PIN15 - Status on whether PIN15 has met criteria set in PIN_CNF15.SENSE register. Write '1' to clear. + Status on whether PIN[15] has met criteria set in PIN_CNF[15].SENSE register. Write '1' to clear. 15 15 @@ -57270,7 +57229,7 @@ POSSIBILITY OF SUCH DAMAGE. PIN16 - Status on whether PIN16 has met criteria set in PIN_CNF16.SENSE register. Write '1' to clear. + Status on whether PIN[16] has met criteria set in PIN_CNF[16].SENSE register. Write '1' to clear. 16 16 @@ -57288,7 +57247,7 @@ POSSIBILITY OF SUCH DAMAGE. PIN17 - Status on whether PIN17 has met criteria set in PIN_CNF17.SENSE register. Write '1' to clear. + Status on whether PIN[17] has met criteria set in PIN_CNF[17].SENSE register. Write '1' to clear. 17 17 @@ -57306,7 +57265,7 @@ POSSIBILITY OF SUCH DAMAGE. PIN18 - Status on whether PIN18 has met criteria set in PIN_CNF18.SENSE register. Write '1' to clear. + Status on whether PIN[18] has met criteria set in PIN_CNF[18].SENSE register. Write '1' to clear. 18 18 @@ -57324,7 +57283,7 @@ POSSIBILITY OF SUCH DAMAGE. PIN19 - Status on whether PIN19 has met criteria set in PIN_CNF19.SENSE register. Write '1' to clear. + Status on whether PIN[19] has met criteria set in PIN_CNF[19].SENSE register. Write '1' to clear. 19 19 @@ -57342,7 +57301,7 @@ POSSIBILITY OF SUCH DAMAGE. PIN20 - Status on whether PIN20 has met criteria set in PIN_CNF20.SENSE register. Write '1' to clear. + Status on whether PIN[20] has met criteria set in PIN_CNF[20].SENSE register. Write '1' to clear. 20 20 @@ -57360,7 +57319,7 @@ POSSIBILITY OF SUCH DAMAGE. PIN21 - Status on whether PIN21 has met criteria set in PIN_CNF21.SENSE register. Write '1' to clear. + Status on whether PIN[21] has met criteria set in PIN_CNF[21].SENSE register. Write '1' to clear. 21 21 @@ -57378,7 +57337,7 @@ POSSIBILITY OF SUCH DAMAGE. PIN22 - Status on whether PIN22 has met criteria set in PIN_CNF22.SENSE register. Write '1' to clear. + Status on whether PIN[22] has met criteria set in PIN_CNF[22].SENSE register. Write '1' to clear. 22 22 @@ -57396,7 +57355,7 @@ POSSIBILITY OF SUCH DAMAGE. PIN23 - Status on whether PIN23 has met criteria set in PIN_CNF23.SENSE register. Write '1' to clear. + Status on whether PIN[23] has met criteria set in PIN_CNF[23].SENSE register. Write '1' to clear. 23 23 @@ -57414,7 +57373,7 @@ POSSIBILITY OF SUCH DAMAGE. PIN24 - Status on whether PIN24 has met criteria set in PIN_CNF24.SENSE register. Write '1' to clear. + Status on whether PIN[24] has met criteria set in PIN_CNF[24].SENSE register. Write '1' to clear. 24 24 @@ -57432,7 +57391,7 @@ POSSIBILITY OF SUCH DAMAGE. PIN25 - Status on whether PIN25 has met criteria set in PIN_CNF25.SENSE register. Write '1' to clear. + Status on whether PIN[25] has met criteria set in PIN_CNF[25].SENSE register. Write '1' to clear. 25 25 @@ -57450,7 +57409,7 @@ POSSIBILITY OF SUCH DAMAGE. PIN26 - Status on whether PIN26 has met criteria set in PIN_CNF26.SENSE register. Write '1' to clear. + Status on whether PIN[26] has met criteria set in PIN_CNF[26].SENSE register. Write '1' to clear. 26 26 @@ -57468,7 +57427,7 @@ POSSIBILITY OF SUCH DAMAGE. PIN27 - Status on whether PIN27 has met criteria set in PIN_CNF27.SENSE register. Write '1' to clear. + Status on whether PIN[27] has met criteria set in PIN_CNF[27].SENSE register. Write '1' to clear. 27 27 @@ -57486,7 +57445,7 @@ POSSIBILITY OF SUCH DAMAGE. PIN28 - Status on whether PIN28 has met criteria set in PIN_CNF28.SENSE register. Write '1' to clear. + Status on whether PIN[28] has met criteria set in PIN_CNF[28].SENSE register. Write '1' to clear. 28 28 @@ -57504,7 +57463,7 @@ POSSIBILITY OF SUCH DAMAGE. PIN29 - Status on whether PIN29 has met criteria set in PIN_CNF29.SENSE register. Write '1' to clear. + Status on whether PIN[29] has met criteria set in PIN_CNF[29].SENSE register. Write '1' to clear. 29 29 @@ -57522,7 +57481,7 @@ POSSIBILITY OF SUCH DAMAGE. PIN30 - Status on whether PIN30 has met criteria set in PIN_CNF30.SENSE register. Write '1' to clear. + Status on whether PIN[30] has met criteria set in PIN_CNF[30].SENSE register. Write '1' to clear. 30 30 @@ -57540,7 +57499,7 @@ POSSIBILITY OF SUCH DAMAGE. PIN31 - Status on whether PIN31 has met criteria set in PIN_CNF31.SENSE register. Write '1' to clear. + Status on whether PIN[31] has met criteria set in PIN_CNF[31].SENSE register. Write '1' to clear. 31 31 diff --git a/mdk/nrf5340_application_bitfields.h b/mdk/nrf5340_application_bitfields.h index 094507730f..ab1d1a112b 100644 --- a/mdk/nrf5340_application_bitfields.h +++ b/mdk/nrf5340_application_bitfields.h @@ -1,6 +1,8 @@ /* -Copyright (c) 2010 - 2020, Nordic Semiconductor ASA All rights reserved. +Copyright (c) 2010 - 2021, Nordic Semiconductor ASA All rights reserved. + +SPDX-License-Identifier: BSD-3-Clause Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: @@ -79,7 +81,7 @@ POSSIBILITY OF SUCH DAMAGE. #define CACHEINFO_SET_WAY_MRU_Way0 (0UL) /*!< Way0 was most recently used */ #define CACHEINFO_SET_WAY_MRU_Way1 (1UL) /*!< Way1 was most recently used */ -/* Bit 30 : Valid bit. */ +/* Bit 30 : Valid bit */ #define CACHEINFO_SET_WAY_V_Pos (30UL) /*!< Position of V field. */ #define CACHEINFO_SET_WAY_V_Msk (0x1UL << CACHEINFO_SET_WAY_V_Pos) /*!< Bit mask of V field. */ #define CACHEINFO_SET_WAY_V_Invalid (0UL) /*!< Invalid cache line */ @@ -122,7 +124,7 @@ POSSIBILITY OF SUCH DAMAGE. #define CACHE_PROFILING_DMISS_MISSES_Msk (0xFFFFFFFFUL << CACHE_PROFILING_DMISS_MISSES_Pos) /*!< Bit mask of MISSES field. */ /* Register: CACHE_ENABLE */ -/* Description: Enable cache */ +/* Description: Enable cache. */ /* Bit 0 : Enable cache */ #define CACHE_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ @@ -131,7 +133,7 @@ POSSIBILITY OF SUCH DAMAGE. #define CACHE_ENABLE_ENABLE_Enabled (1UL) /*!< Enable cache */ /* Register: CACHE_INVALIDATE */ -/* Description: Invalidate the cache */ +/* Description: Invalidate the cache. */ /* Bit 0 : Invalidate the cache */ #define CACHE_INVALIDATE_INVALIDATE_Pos (0UL) /*!< Position of INVALIDATE field. */ @@ -139,7 +141,7 @@ POSSIBILITY OF SUCH DAMAGE. #define CACHE_INVALIDATE_INVALIDATE_Invalidate (1UL) /*!< Invalidate the cache */ /* Register: CACHE_ERASE */ -/* Description: Erase the cache */ +/* Description: Erase the cache. */ /* Bit 0 : Erase the cache */ #define CACHE_ERASE_ERASE_Pos (0UL) /*!< Position of ERASE field. */ @@ -147,7 +149,7 @@ POSSIBILITY OF SUCH DAMAGE. #define CACHE_ERASE_ERASE_Erase (1UL) /*!< Erase cache */ /* Register: CACHE_PROFILINGENABLE */ -/* Description: Enable the profiling counters */ +/* Description: Enable the profiling counters. */ /* Bit 0 : Enable the profiling counters */ #define CACHE_PROFILINGENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ @@ -156,7 +158,7 @@ POSSIBILITY OF SUCH DAMAGE. #define CACHE_PROFILINGENABLE_ENABLE_Enable (1UL) /*!< Enable profiling */ /* Register: CACHE_PROFILINGCLEAR */ -/* Description: Clear the profiling counters */ +/* Description: Clear the profiling counters. */ /* Bit 0 : Clearing the profiling counters */ #define CACHE_PROFILINGCLEAR_CLEAR_Pos (0UL) /*!< Position of CLEAR field. */ @@ -164,7 +166,7 @@ POSSIBILITY OF SUCH DAMAGE. #define CACHE_PROFILINGCLEAR_CLEAR_Clear (1UL) /*!< Clear the profiling counters */ /* Register: CACHE_MODE */ -/* Description: Cache mode. Switching from Cache to RAM mode causes the RAM to be cleared. Switching from RAM to Cache mode causes the cache to be invalidated. */ +/* Description: Cache mode. Switching from Cache to Ram mode causes the RAM to be cleared. Switching from RAM to Cache mode causes the cache to be invalidated. */ /* Bit 0 : Cache mode */ #define CACHE_MODE_MODE_Pos (0UL) /*!< Position of MODE field. */ @@ -173,7 +175,7 @@ POSSIBILITY OF SUCH DAMAGE. #define CACHE_MODE_MODE_Ram (1UL) /*!< RAM mode */ /* Register: CACHE_DEBUGLOCK */ -/* Description: Lock debug mode Ignored in RAM mode. */ +/* Description: Lock debug mode. */ /* Bit 0 : Lock debug mode */ #define CACHE_DEBUGLOCK_DEBUGLOCK_Pos (0UL) /*!< Position of DEBUGLOCK field. */ @@ -182,7 +184,7 @@ POSSIBILITY OF SUCH DAMAGE. #define CACHE_DEBUGLOCK_DEBUGLOCK_Locked (1UL) /*!< Debug mode locked */ /* Register: CACHE_ERASESTATUS */ -/* Description: Cache erase status */ +/* Description: Cache erase status. */ /* Bit 0 : Cache erase status */ #define CACHE_ERASESTATUS_ERASESTATUS_Pos (0UL) /*!< Position of ERASESTATUS field. */ @@ -701,7 +703,6 @@ POSSIBILITY OF SUCH DAMAGE. /* Bits 1..0 : Active clock source */ #define CLOCK_LFCLKSTAT_SRC_Pos (0UL) /*!< Position of SRC field. */ #define CLOCK_LFCLKSTAT_SRC_Msk (0x3UL << CLOCK_LFCLKSTAT_SRC_Pos) /*!< Bit mask of SRC field. */ -#define CLOCK_LFCLKSTAT_SRC_LFULP (0UL) /*!< 32.768 kHz ultra-low power RC oscillator */ #define CLOCK_LFCLKSTAT_SRC_LFRC (1UL) /*!< 32.768 kHz RC oscillator */ #define CLOCK_LFCLKSTAT_SRC_LFXO (2UL) /*!< 32.768 kHz crystal oscillator */ #define CLOCK_LFCLKSTAT_SRC_LFSYNT (3UL) /*!< 32.768 kHz synthesized from HFCLK */ @@ -712,7 +713,6 @@ POSSIBILITY OF SUCH DAMAGE. /* Bits 1..0 : Clock source */ #define CLOCK_LFCLKSRCCOPY_SRC_Pos (0UL) /*!< Position of SRC field. */ #define CLOCK_LFCLKSRCCOPY_SRC_Msk (0x3UL << CLOCK_LFCLKSRCCOPY_SRC_Pos) /*!< Bit mask of SRC field. */ -#define CLOCK_LFCLKSRCCOPY_SRC_LFULP (0UL) /*!< 32.768 kHz ultra-low power RC oscillator */ #define CLOCK_LFCLKSRCCOPY_SRC_LFRC (1UL) /*!< 32.768 kHz RC oscillator */ #define CLOCK_LFCLKSRCCOPY_SRC_LFXO (2UL) /*!< 32.768 kHz crystal oscillator */ #define CLOCK_LFCLKSRCCOPY_SRC_LFSYNT (3UL) /*!< 32.768 kHz synthesized from HFCLK */ @@ -786,7 +786,6 @@ POSSIBILITY OF SUCH DAMAGE. /* Bits 1..0 : Select which LFCLK source is started by the LFCLKSTART task */ #define CLOCK_LFCLKSRC_SRC_Pos (0UL) /*!< Position of SRC field. */ #define CLOCK_LFCLKSRC_SRC_Msk (0x3UL << CLOCK_LFCLKSRC_SRC_Pos) /*!< Bit mask of SRC field. */ -#define CLOCK_LFCLKSRC_SRC_LFULP (0UL) /*!< 32.768 kHz ultra-low power RC oscillator */ #define CLOCK_LFCLKSRC_SRC_LFRC (1UL) /*!< 32.768 kHz RC oscillator */ #define CLOCK_LFCLKSRC_SRC_LFXO (2UL) /*!< 32.768 kHz crystal oscillator */ #define CLOCK_LFCLKSRC_SRC_LFSYNT (3UL) /*!< 32.768 kHz synthesized from HFCLK */ @@ -1628,17 +1627,17 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: CTI_DEVTYPE */ /* Description: Device Type Identifier register */ -/* Bits 7..4 : Sub-classification of the type of the debug component as specified in the ARM Architecture Specification within +/* Bits 7..4 : Sub-classification of the type of the debug component as specified in the Arm Architecture Specification within the major classification as specified in the MAJOR field. */ #define CTI_DEVTYPE_SUB_Pos (4UL) /*!< Position of SUB field. */ #define CTI_DEVTYPE_SUB_Msk (0xFUL << CTI_DEVTYPE_SUB_Pos) /*!< Bit mask of SUB field. */ -#define CTI_DEVTYPE_SUB_Crosstrigger (0b0001UL) /*!< Indicates that this component is a sub-triggering component. */ +#define CTI_DEVTYPE_SUB_Crosstrigger (1UL) /*!< Indicates that this component is a sub-triggering component. */ -/* Bits 3..0 : Major classification of the type of the debug component as specified in the ARM Architecture Specification for this +/* Bits 3..0 : Major classification of the type of the debug component as specified in the Arm Architecture Specification for this debug and trace component. */ #define CTI_DEVTYPE_MAJOR_Pos (0UL) /*!< Position of MAJOR field. */ #define CTI_DEVTYPE_MAJOR_Msk (0xFUL << CTI_DEVTYPE_MAJOR_Pos) /*!< Bit mask of MAJOR field. */ -#define CTI_DEVTYPE_MAJOR_Controller (0b0100UL) /*!< Indicates that this component allows a debugger to control other components in a CoreSight SoC-400 system. */ +#define CTI_DEVTYPE_MAJOR_Controller (4UL) /*!< Indicates that this component allows a debugger to control other components in an Arm CoreSight SoC-400 system. */ /* Register: CTI_PIDR4 */ /* Description: Peripheral ID4 Register */ @@ -1650,7 +1649,7 @@ POSSIBILITY OF SUCH DAMAGE. /* Bits 3..0 : Together, PIDR1.DES_0, PIDR2.DES_1, and PIDR4.DES_2 identify the designer of the component. */ #define CTI_PIDR4_DES_2_Pos (0UL) /*!< Position of DES_2 field. */ #define CTI_PIDR4_DES_2_Msk (0xFUL << CTI_PIDR4_DES_2_Pos) /*!< Bit mask of DES_2 field. */ -#define CTI_PIDR4_DES_2_Code (0b0100UL) /*!< JEDEC continuation code */ +#define CTI_PIDR4_DES_2_Code (4UL) /*!< JEDEC continuation code. */ /* Register: CTI_PIDR0 */ /* Description: Peripheral ID0 Register */ @@ -1666,12 +1665,12 @@ POSSIBILITY OF SUCH DAMAGE. /* Bits 7..4 : Together, PIDR1.DES_0, PIDR2.DES_1, and PIDR4.DES_2 identify the designer of the component. */ #define CTI_PIDR1_DES_0_Pos (4UL) /*!< Position of DES_0 field. */ #define CTI_PIDR1_DES_0_Msk (0xFUL << CTI_PIDR1_DES_0_Pos) /*!< Bit mask of DES_0 field. */ -#define CTI_PIDR1_DES_0_Arm (0b1011UL) /*!< ARM. Bits[3:0] of the JEDEC JEP106 Identity Code */ +#define CTI_PIDR1_DES_0_Arm (11UL) /*!< Arm. Bits[3:0] of the JEDEC JEP106 Identity Code */ /* Bits 3..0 : Bits[11:8] of the 12-bit part number of the component. The designer of the component assigns this part number. */ #define CTI_PIDR1_PART_1_Pos (0UL) /*!< Position of PART_1 field. */ #define CTI_PIDR1_PART_1_Msk (0xFUL << CTI_PIDR1_PART_1_Pos) /*!< Bit mask of PART_1 field. */ -#define CTI_PIDR1_PART_1_PartnumberH (0b1101UL) /*!< Indicates bits[11:8] of the part number of the component. */ +#define CTI_PIDR1_PART_1_PartnumberH (13UL) /*!< Indicates bits[11:8] of the part number of the component. */ /* Register: CTI_PIDR2 */ /* Description: Peripheral ID2 Register */ @@ -1679,7 +1678,7 @@ POSSIBILITY OF SUCH DAMAGE. /* Bits 7..4 : Peripheral revision */ #define CTI_PIDR2_REVISION_Pos (4UL) /*!< Position of REVISION field. */ #define CTI_PIDR2_REVISION_Msk (0xFUL << CTI_PIDR2_REVISION_Pos) /*!< Bit mask of REVISION field. */ -#define CTI_PIDR2_REVISION_Rev0p0 (0b0000UL) /*!< This device is at r0p0 */ +#define CTI_PIDR2_REVISION_Rev0p0 (0UL) /*!< This device is at r0p0 */ /* Bit 3 : Always 1. Indicates that the JEDEC-assigned designer ID is used. */ #define CTI_PIDR2_JEDEC_Pos (3UL) /*!< Position of JEDEC field. */ @@ -1688,23 +1687,23 @@ POSSIBILITY OF SUCH DAMAGE. /* Bits 2..0 : Together, PIDR1.DES_0, PIDR2.DES_1, and PIDR4.DES_2 identify the designer of the component. */ #define CTI_PIDR2_DES_1_Pos (0UL) /*!< Position of DES_1 field. */ #define CTI_PIDR2_DES_1_Msk (0x7UL << CTI_PIDR2_DES_1_Pos) /*!< Bit mask of DES_1 field. */ -#define CTI_PIDR2_DES_1_Arm (0b011UL) /*!< ARM. Bits[6:4] of the JEDEC JEP106 Identity Code */ +#define CTI_PIDR2_DES_1_Arm (3UL) /*!< Arm. Bits[6:4] of the JEDEC JEP106 Identity Code */ /* Register: CTI_PIDR3 */ /* Description: Peripheral ID3 Register */ /* Bits 7..4 : Indicates minor errata fixes specific to the revision of the component being used, for example metal fixes after - implementation. In most cases, this field is 0b0000. ARM recommends that the component designers ensure that a + implementation. In most cases, this field is 0b0000. Arm recommends that the component designers ensure that a metal fix can change this field if required, for example, by driving it from registers that reset to 0b0000. */ #define CTI_PIDR3_REVAND_Pos (4UL) /*!< Position of REVAND field. */ #define CTI_PIDR3_REVAND_Msk (0xFUL << CTI_PIDR3_REVAND_Pos) /*!< Bit mask of REVAND field. */ -#define CTI_PIDR3_REVAND_NoErrata (0b000UL) /*!< Indicates that there are no errata fixes to this component. */ +#define CTI_PIDR3_REVAND_NoErrata (0UL) /*!< Indicates that there are no errata fixes to this component. */ /* Bits 3..0 : Customer Modified. Indicates whether the customer has modified the behavior of the component. In most cases, this field is 0b0000. Customers change this value when they make authorized modifications to this component. */ #define CTI_PIDR3_CMOD_Pos (0UL) /*!< Position of CMOD field. */ #define CTI_PIDR3_CMOD_Msk (0xFUL << CTI_PIDR3_CMOD_Pos) /*!< Bit mask of CMOD field. */ -#define CTI_PIDR3_CMOD_Unmodified (0b000UL) /*!< Indicates that the customer has not modified this component. */ +#define CTI_PIDR3_CMOD_Unmodified (0UL) /*!< Indicates that the customer has not modified this component. */ /* Register: CTI_CIDR0 */ /* Description: Component ID0 Register */ @@ -1721,12 +1720,12 @@ POSSIBILITY OF SUCH DAMAGE. Contains bits[15:12] of the component identification code */ #define CTI_CIDR1_CLASS_Pos (4UL) /*!< Position of CLASS field. */ #define CTI_CIDR1_CLASS_Msk (0xFUL << CTI_CIDR1_CLASS_Pos) /*!< Bit mask of CLASS field. */ -#define CTI_CIDR1_CLASS_Coresight (0b1001UL) /*!< Indicates that the component is a CoreSight component. */ +#define CTI_CIDR1_CLASS_Coresight (9UL) /*!< Indicates that the component is a CoreSight component. */ /* Bits 3..0 : Preamble[1]. Contains bits[11:8] of the component identification code. */ #define CTI_CIDR1_PRMBL_1_Pos (0UL) /*!< Position of PRMBL_1 field. */ #define CTI_CIDR1_PRMBL_1_Msk (0xFUL << CTI_CIDR1_PRMBL_1_Pos) /*!< Bit mask of PRMBL_1 field. */ -#define CTI_CIDR1_PRMBL_1_Value (0b0000UL) /*!< Bits[11:8] of the identification code. */ +#define CTI_CIDR1_PRMBL_1_Value (0UL) /*!< Bits[11:8] of the identification code. */ /* Register: CTI_CIDR2 */ /* Description: Component ID2 Register */ @@ -1808,7 +1807,9 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: CTRLAPPERI_APPROTECT_DISABLE */ /* Description: This register disables the APPROTECT register and enables debug access to non-secure mode. */ -/* Bits 31..0 : Disable APPROTECT and enable debug access to non-secure mode until the next pin reset if the KEY fields match. The current APPROTECT value as configured from UICR is bypassed if the value of the KEY fields are non-zero and the KEY fields match on both the CPU and debugger sides. */ +/* Bits 31..0 : If the value of the KEY field is non-zero, and the KEY fields match on both the + CPU and debugger sides, disable APPROTECT and enable debug access to non-secure mode until + the next pin reset, brown-out reset, power-on reset, or watchog timer reset. After reset the debugger side register has a fixed KEY value. To enable debug access, both CTRL-AP and UICR.APPROTECT protection needs to be disabled. */ #define CTRLAPPERI_APPROTECT_DISABLE_KEY_Pos (0UL) /*!< Position of KEY field. */ #define CTRLAPPERI_APPROTECT_DISABLE_KEY_Msk (0xFFFFFFFFUL << CTRLAPPERI_APPROTECT_DISABLE_KEY_Pos) /*!< Bit mask of KEY field. */ @@ -1824,12 +1825,14 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: CTRLAPPERI_SECUREAPPROTECT_DISABLE */ /* Description: This register disables the SECUREAPPROTECT register and enables debug access to secure mode. */ -/* Bits 31..0 : Disable SECUREAPPROTECT and enable debug of secure mode until the next pin reset if the KEY fields match. The current SECUREAPPROTECT value as configured from UICR is bypassed if the value of the KEY fields are non-zero and the KEY fields match on both the CPU and debugger sides. */ +/* Bits 31..0 : If the value of the KEY field is non-zero, and the KEY fields match on both the + CPU and debugger sides, disable SECUREAPPROTECT and enable debug access to secure mode until + the next pin reset, brown-out reset, power-on reset, or watchog timer reset. After reset the debugger side register has a fixed KEY value. To enable debug access, both CTRL-AP and UICR.SECUREAPPROTECT protection needs to be disabled. */ #define CTRLAPPERI_SECUREAPPROTECT_DISABLE_KEY_Pos (0UL) /*!< Position of KEY field. */ #define CTRLAPPERI_SECUREAPPROTECT_DISABLE_KEY_Msk (0xFFFFFFFFUL << CTRLAPPERI_SECUREAPPROTECT_DISABLE_KEY_Pos) /*!< Bit mask of KEY field. */ /* Register: CTRLAPPERI_STATUS */ -/* Description: Status bits for CTRL-AP peripheral */ +/* Description: Status bits for CTRL-AP peripheral. */ /* Bit 2 : Status bit for device debug interface mode */ #define CTRLAPPERI_STATUS_DBGIFACEMODE_Pos (2UL) /*!< Position of DBGIFACEMODE field. */ @@ -1837,17 +1840,17 @@ POSSIBILITY OF SUCH DAMAGE. #define CTRLAPPERI_STATUS_DBGIFACEMODE_Disabled (0UL) /*!< No debugger attached */ #define CTRLAPPERI_STATUS_DBGIFACEMODE_Enabled (1UL) /*!< Debugger is attached and device is in debug interface mode */ -/* Bit 1 : Status bit for access port protection in secure mode */ -#define CTRLAPPERI_STATUS_SECUREAPPROTECT_Pos (1UL) /*!< Position of SECUREAPPROTECT field. */ -#define CTRLAPPERI_STATUS_SECUREAPPROTECT_Msk (0x1UL << CTRLAPPERI_STATUS_SECUREAPPROTECT_Pos) /*!< Bit mask of SECUREAPPROTECT field. */ -#define CTRLAPPERI_STATUS_SECUREAPPROTECT_Disabled (0UL) /*!< Secure mode access port protection is currently disabled */ -#define CTRLAPPERI_STATUS_SECUREAPPROTECT_Enabled (1UL) /*!< Secure mode access port protection is currently enabled */ +/* Bit 1 : Status bit for UICR part of secure access port protection at last reset. */ +#define CTRLAPPERI_STATUS_UICRSECUREAPPROTECT_Pos (1UL) /*!< Position of UICRSECUREAPPROTECT field. */ +#define CTRLAPPERI_STATUS_UICRSECUREAPPROTECT_Msk (0x1UL << CTRLAPPERI_STATUS_UICRSECUREAPPROTECT_Pos) /*!< Bit mask of UICRSECUREAPPROTECT field. */ +#define CTRLAPPERI_STATUS_UICRSECUREAPPROTECT_Enabled (0UL) /*!< SECUREAPPROTECT was enabled in UICR */ +#define CTRLAPPERI_STATUS_UICRSECUREAPPROTECT_Disabled (1UL) /*!< SECUREAPPROTECT was disabled in UICR */ -/* Bit 0 : Status bit for access port protection in non-secure mode */ -#define CTRLAPPERI_STATUS_APPROTECT_Pos (0UL) /*!< Position of APPROTECT field. */ -#define CTRLAPPERI_STATUS_APPROTECT_Msk (0x1UL << CTRLAPPERI_STATUS_APPROTECT_Pos) /*!< Bit mask of APPROTECT field. */ -#define CTRLAPPERI_STATUS_APPROTECT_Disabled (0UL) /*!< Non-secure mode access port protection is currently disabled */ -#define CTRLAPPERI_STATUS_APPROTECT_Enabled (1UL) /*!< Non-secure mode access port protection is currently enabled */ +/* Bit 0 : Status bit for UICR part of access port protection at last reset. */ +#define CTRLAPPERI_STATUS_UICRAPPROTECT_Pos (0UL) /*!< Position of UICRAPPROTECT field. */ +#define CTRLAPPERI_STATUS_UICRAPPROTECT_Msk (0x1UL << CTRLAPPERI_STATUS_UICRAPPROTECT_Pos) /*!< Bit mask of UICRAPPROTECT field. */ +#define CTRLAPPERI_STATUS_UICRAPPROTECT_Enabled (0UL) /*!< APPROTECT was enabled in UICR */ +#define CTRLAPPERI_STATUS_UICRAPPROTECT_Disabled (1UL) /*!< APPROTECT wasdisabled in UICR */ /* Peripheral: DCNF */ @@ -3237,7 +3240,7 @@ POSSIBILITY OF SUCH DAMAGE. /* Bits 31..0 : Package option */ #define FICR_INFO_PACKAGE_PACKAGE_Pos (0UL) /*!< Position of PACKAGE field. */ #define FICR_INFO_PACKAGE_PACKAGE_Msk (0xFFFFFFFFUL << FICR_INFO_PACKAGE_PACKAGE_Pos) /*!< Bit mask of PACKAGE field. */ -#define FICR_INFO_PACKAGE_PACKAGE_QF (0x2000UL) /*!< QFxx - 94 pin QFN */ +#define FICR_INFO_PACKAGE_PACKAGE_QK (0x2000UL) /*!< QKxx - 94-pin aQFN */ #define FICR_INFO_PACKAGE_PACKAGE_Unspecified (0xFFFFFFFFUL) /*!< Unspecified */ /* Register: FICR_INFO_RAM */ @@ -4205,7 +4208,7 @@ POSSIBILITY OF SUCH DAMAGE. #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV31 (0x08400000UL) /*!< 32 MHz / 31 = 1.0322581 MHz Deprecated, use MCKFREQ equation. */ #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV30 (0x08800000UL) /*!< 32 MHz / 30 = 1.0666667 MHz Deprecated, use MCKFREQ equation. */ #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV23 (0x0B000000UL) /*!< 32 MHz / 23 = 1.3913043 MHz Deprecated, use MCKFREQ equation. */ -#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV21 (0x0C000000UL) /*!< 32 MHz / 21 = 1.5238095 Deprecated, use MCKFREQ equation. */ +#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV21 (0x0C000000UL) /*!< 32 MHz / 21 = 1.5238095 MHz Deprecated, use MCKFREQ equation. */ #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV16 (0x10000000UL) /*!< 32 MHz / 16 = 2.0 MHz Deprecated, use MCKFREQ equation. */ #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV15 (0x11000000UL) /*!< 32 MHz / 15 = 2.1333333 MHz Deprecated, use MCKFREQ equation. */ #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV11 (0x16000000UL) /*!< 32 MHz / 11 = 2.9090909 MHz Deprecated, use MCKFREQ equation. */ @@ -4242,8 +4245,8 @@ POSSIBILITY OF SUCH DAMAGE. #define I2S_CONFIG_SWIDTH_SWIDTH_8Bit (0UL) /*!< 8 bit sample. */ #define I2S_CONFIG_SWIDTH_SWIDTH_16Bit (1UL) /*!< 16 bit sample. */ #define I2S_CONFIG_SWIDTH_SWIDTH_24Bit (2UL) /*!< 24 bit sample. */ -#define I2S_CONFIG_SWIDTH_SWIDTH_32Bit (3UL) /*!< 32-bit sample. */ -#define I2S_CONFIG_SWIDTH_SWIDTH_8BitIn16 (4UL) /*!< 8 bit sample in a 16 bit half-frame. */ +#define I2S_CONFIG_SWIDTH_SWIDTH_32Bit (3UL) /*!< 32 bit sample. */ +#define I2S_CONFIG_SWIDTH_SWIDTH_8BitIn16 (4UL) /*!< 8 bit sample in a 16-bit half-frame. */ #define I2S_CONFIG_SWIDTH_SWIDTH_8BitIn32 (5UL) /*!< 8 bit sample in a 32-bit half-frame. */ #define I2S_CONFIG_SWIDTH_SWIDTH_16BitIn32 (6UL) /*!< 16 bit sample in a 32-bit half-frame. */ #define I2S_CONFIG_SWIDTH_SWIDTH_24BitIn32 (7UL) /*!< 24 bit sample in a 32-bit half-frame. */ @@ -6415,7 +6418,7 @@ POSSIBILITY OF SUCH DAMAGE. #define NFCT_FRAMESTATUS_RX_CRCERROR_CRCError (1UL) /*!< CRC received does not match local check */ /* Register: NFCT_NFCTAGSTATE */ -/* Description: NfcTag state register */ +/* Description: Current operating state of NFC tag */ /* Bits 2..0 : NfcTag state */ #define NFCT_NFCTAGSTATE_NFCTAGSTATE_Pos (0UL) /*!< Position of NFCTAGSTATE field. */ @@ -6456,14 +6459,14 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: NFCT_FRAMEDELAYMIN */ /* Description: Minimum frame delay */ -/* Bits 15..0 : Minimum frame delay in number of 13.56 MHz clocks */ +/* Bits 15..0 : Minimum frame delay in number of 13.56 MHz clock cycles */ #define NFCT_FRAMEDELAYMIN_FRAMEDELAYMIN_Pos (0UL) /*!< Position of FRAMEDELAYMIN field. */ #define NFCT_FRAMEDELAYMIN_FRAMEDELAYMIN_Msk (0xFFFFUL << NFCT_FRAMEDELAYMIN_FRAMEDELAYMIN_Pos) /*!< Bit mask of FRAMEDELAYMIN field. */ /* Register: NFCT_FRAMEDELAYMAX */ /* Description: Maximum frame delay */ -/* Bits 19..0 : Maximum frame delay in number of 13.56 MHz clocks */ +/* Bits 19..0 : Maximum frame delay in number of 13.56 MHz clock cycles */ #define NFCT_FRAMEDELAYMAX_FRAMEDELAYMAX_Pos (0UL) /*!< Position of FRAMEDELAYMAX field. */ #define NFCT_FRAMEDELAYMAX_FRAMEDELAYMAX_Msk (0xFFFFFUL << NFCT_FRAMEDELAYMAX_FRAMEDELAYMAX_Pos) /*!< Bit mask of FRAMEDELAYMAX field. */ @@ -6522,7 +6525,7 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: NFCT_TXD_AMOUNT */ /* Description: Size of outgoing frame */ -/* Bits 11..3 : Number of complete bytes that shall be included in the frame, excluding CRC, parity and framing */ +/* Bits 11..3 : Number of complete bytes that shall be included in the frame, excluding CRC, parity, and framing. */ #define NFCT_TXD_AMOUNT_TXDATABYTES_Pos (3UL) /*!< Position of TXDATABYTES field. */ #define NFCT_TXD_AMOUNT_TXDATABYTES_Msk (0x1FFUL << NFCT_TXD_AMOUNT_TXDATABYTES_Pos) /*!< Bit mask of TXDATABYTES field. */ @@ -6574,7 +6577,7 @@ POSSIBILITY OF SUCH DAMAGE. #define NFCT_MODULATIONCTRL_MODULATIONCTRL_InternalAndModToGpio (0x3UL) /*!< Use internal modulator and output digital modulation signal to a GPIO pin. */ /* Register: NFCT_MODULATIONPSEL */ -/* Description: Pin select for Modulation control. */ +/* Description: Pin select for Modulation control */ /* Bit 31 : Connection */ #define NFCT_MODULATIONPSEL_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ @@ -6582,9 +6585,9 @@ POSSIBILITY OF SUCH DAMAGE. #define NFCT_MODULATIONPSEL_CONNECT_Connected (0UL) /*!< Connect */ #define NFCT_MODULATIONPSEL_CONNECT_Disconnected (1UL) /*!< Disconnect */ -/* Bits 6..5 : Port number */ +/* Bit 5 : Port number */ #define NFCT_MODULATIONPSEL_PORT_Pos (5UL) /*!< Position of PORT field. */ -#define NFCT_MODULATIONPSEL_PORT_Msk (0x3UL << NFCT_MODULATIONPSEL_PORT_Pos) /*!< Bit mask of PORT field. */ +#define NFCT_MODULATIONPSEL_PORT_Msk (0x1UL << NFCT_MODULATIONPSEL_PORT_Pos) /*!< Bit mask of PORT field. */ /* Bits 4..0 : Pin number */ #define NFCT_MODULATIONPSEL_PIN_Pos (0UL) /*!< Position of PIN field. */ @@ -6713,7 +6716,7 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 0 : NVMC is ready or busy */ #define NVMC_READY_READY_Pos (0UL) /*!< Position of READY field. */ #define NVMC_READY_READY_Msk (0x1UL << NVMC_READY_READY_Pos) /*!< Bit mask of READY field. */ -#define NVMC_READY_READY_Busy (0UL) /*!< NVMC is busy (on-going write or erase operation) */ +#define NVMC_READY_READY_Busy (0UL) /*!< NVMC is busy (ongoing write or erase operation) */ #define NVMC_READY_READY_Ready (1UL) /*!< NVMC is ready */ /* Register: NVMC_READYNEXT */ @@ -6739,7 +6742,7 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: NVMC_ERASEALL */ /* Description: Register for erasing all non-volatile user memory */ -/* Bit 0 : Erase all non-volatile memory including UICR registers. Note that erasing must be enabled by setting CONFIG.WEN = Een before the non-volatile memory can be erased. */ +/* Bit 0 : Erase all non-volatile memory including UICR registers. Before the non-volatile memory can be erased, erasing must be enabled by setting CONFIG.WEN=Een. */ #define NVMC_ERASEALL_ERASEALL_Pos (0UL) /*!< Position of ERASEALL field. */ #define NVMC_ERASEALL_ERASEALL_Msk (0x1UL << NVMC_ERASEALL_ERASEALL_Pos) /*!< Bit mask of ERASEALL field. */ #define NVMC_ERASEALL_ERASEALL_NoOperation (0UL) /*!< No operation */ @@ -6753,7 +6756,7 @@ POSSIBILITY OF SUCH DAMAGE. #define NVMC_ERASEPAGEPARTIALCFG_DURATION_Msk (0x7FUL << NVMC_ERASEPAGEPARTIALCFG_DURATION_Pos) /*!< Bit mask of DURATION field. */ /* Register: NVMC_CONFIGNS */ -/* Description: Unspecified */ +/* Description: Non-secure configuration register */ /* Bits 1..0 : Program memory access mode. It is strongly recommended to only activate erase and write modes when they are actively used. */ #define NVMC_CONFIGNS_WEN_Pos (0UL) /*!< Position of WEN field. */ @@ -6810,7 +6813,7 @@ POSSIBILITY OF SUCH DAMAGE. #define OSCILLATORS_XOSC32KI_INTCAP_INTCAP_External (0UL) /*!< Use external load capacitors */ #define OSCILLATORS_XOSC32KI_INTCAP_INTCAP_C6PF (1UL) /*!< 6 pF internal load capacitance */ #define OSCILLATORS_XOSC32KI_INTCAP_INTCAP_C7PF (2UL) /*!< 7 pF internal load capacitance */ -#define OSCILLATORS_XOSC32KI_INTCAP_INTCAP_C11PF (3UL) /*!< 11 pF internal load capacitance */ +#define OSCILLATORS_XOSC32KI_INTCAP_INTCAP_C9PF (3UL) /*!< 9 pF internal load capacitance */ /* Peripheral: GPIO */ @@ -8312,193 +8315,193 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: GPIO_LATCH */ /* Description: Latch register indicating what GPIO pins that have met the criteria set in the PIN_CNF[n].SENSE registers */ -/* Bit 31 : Status on whether PIN31 has met criteria set in PIN_CNF31.SENSE register. Write '1' to clear. */ +/* Bit 31 : Status on whether PIN[31] has met criteria set in PIN_CNF[31].SENSE register. Write '1' to clear. */ #define GPIO_LATCH_PIN31_Pos (31UL) /*!< Position of PIN31 field. */ #define GPIO_LATCH_PIN31_Msk (0x1UL << GPIO_LATCH_PIN31_Pos) /*!< Bit mask of PIN31 field. */ #define GPIO_LATCH_PIN31_NotLatched (0UL) /*!< Criteria has not been met */ #define GPIO_LATCH_PIN31_Latched (1UL) /*!< Criteria has been met */ -/* Bit 30 : Status on whether PIN30 has met criteria set in PIN_CNF30.SENSE register. Write '1' to clear. */ +/* Bit 30 : Status on whether PIN[30] has met criteria set in PIN_CNF[30].SENSE register. Write '1' to clear. */ #define GPIO_LATCH_PIN30_Pos (30UL) /*!< Position of PIN30 field. */ #define GPIO_LATCH_PIN30_Msk (0x1UL << GPIO_LATCH_PIN30_Pos) /*!< Bit mask of PIN30 field. */ #define GPIO_LATCH_PIN30_NotLatched (0UL) /*!< Criteria has not been met */ #define GPIO_LATCH_PIN30_Latched (1UL) /*!< Criteria has been met */ -/* Bit 29 : Status on whether PIN29 has met criteria set in PIN_CNF29.SENSE register. Write '1' to clear. */ +/* Bit 29 : Status on whether PIN[29] has met criteria set in PIN_CNF[29].SENSE register. Write '1' to clear. */ #define GPIO_LATCH_PIN29_Pos (29UL) /*!< Position of PIN29 field. */ #define GPIO_LATCH_PIN29_Msk (0x1UL << GPIO_LATCH_PIN29_Pos) /*!< Bit mask of PIN29 field. */ #define GPIO_LATCH_PIN29_NotLatched (0UL) /*!< Criteria has not been met */ #define GPIO_LATCH_PIN29_Latched (1UL) /*!< Criteria has been met */ -/* Bit 28 : Status on whether PIN28 has met criteria set in PIN_CNF28.SENSE register. Write '1' to clear. */ +/* Bit 28 : Status on whether PIN[28] has met criteria set in PIN_CNF[28].SENSE register. Write '1' to clear. */ #define GPIO_LATCH_PIN28_Pos (28UL) /*!< Position of PIN28 field. */ #define GPIO_LATCH_PIN28_Msk (0x1UL << GPIO_LATCH_PIN28_Pos) /*!< Bit mask of PIN28 field. */ #define GPIO_LATCH_PIN28_NotLatched (0UL) /*!< Criteria has not been met */ #define GPIO_LATCH_PIN28_Latched (1UL) /*!< Criteria has been met */ -/* Bit 27 : Status on whether PIN27 has met criteria set in PIN_CNF27.SENSE register. Write '1' to clear. */ +/* Bit 27 : Status on whether PIN[27] has met criteria set in PIN_CNF[27].SENSE register. Write '1' to clear. */ #define GPIO_LATCH_PIN27_Pos (27UL) /*!< Position of PIN27 field. */ #define GPIO_LATCH_PIN27_Msk (0x1UL << GPIO_LATCH_PIN27_Pos) /*!< Bit mask of PIN27 field. */ #define GPIO_LATCH_PIN27_NotLatched (0UL) /*!< Criteria has not been met */ #define GPIO_LATCH_PIN27_Latched (1UL) /*!< Criteria has been met */ -/* Bit 26 : Status on whether PIN26 has met criteria set in PIN_CNF26.SENSE register. Write '1' to clear. */ +/* Bit 26 : Status on whether PIN[26] has met criteria set in PIN_CNF[26].SENSE register. Write '1' to clear. */ #define GPIO_LATCH_PIN26_Pos (26UL) /*!< Position of PIN26 field. */ #define GPIO_LATCH_PIN26_Msk (0x1UL << GPIO_LATCH_PIN26_Pos) /*!< Bit mask of PIN26 field. */ #define GPIO_LATCH_PIN26_NotLatched (0UL) /*!< Criteria has not been met */ #define GPIO_LATCH_PIN26_Latched (1UL) /*!< Criteria has been met */ -/* Bit 25 : Status on whether PIN25 has met criteria set in PIN_CNF25.SENSE register. Write '1' to clear. */ +/* Bit 25 : Status on whether PIN[25] has met criteria set in PIN_CNF[25].SENSE register. Write '1' to clear. */ #define GPIO_LATCH_PIN25_Pos (25UL) /*!< Position of PIN25 field. */ #define GPIO_LATCH_PIN25_Msk (0x1UL << GPIO_LATCH_PIN25_Pos) /*!< Bit mask of PIN25 field. */ #define GPIO_LATCH_PIN25_NotLatched (0UL) /*!< Criteria has not been met */ #define GPIO_LATCH_PIN25_Latched (1UL) /*!< Criteria has been met */ -/* Bit 24 : Status on whether PIN24 has met criteria set in PIN_CNF24.SENSE register. Write '1' to clear. */ +/* Bit 24 : Status on whether PIN[24] has met criteria set in PIN_CNF[24].SENSE register. Write '1' to clear. */ #define GPIO_LATCH_PIN24_Pos (24UL) /*!< Position of PIN24 field. */ #define GPIO_LATCH_PIN24_Msk (0x1UL << GPIO_LATCH_PIN24_Pos) /*!< Bit mask of PIN24 field. */ #define GPIO_LATCH_PIN24_NotLatched (0UL) /*!< Criteria has not been met */ #define GPIO_LATCH_PIN24_Latched (1UL) /*!< Criteria has been met */ -/* Bit 23 : Status on whether PIN23 has met criteria set in PIN_CNF23.SENSE register. Write '1' to clear. */ +/* Bit 23 : Status on whether PIN[23] has met criteria set in PIN_CNF[23].SENSE register. Write '1' to clear. */ #define GPIO_LATCH_PIN23_Pos (23UL) /*!< Position of PIN23 field. */ #define GPIO_LATCH_PIN23_Msk (0x1UL << GPIO_LATCH_PIN23_Pos) /*!< Bit mask of PIN23 field. */ #define GPIO_LATCH_PIN23_NotLatched (0UL) /*!< Criteria has not been met */ #define GPIO_LATCH_PIN23_Latched (1UL) /*!< Criteria has been met */ -/* Bit 22 : Status on whether PIN22 has met criteria set in PIN_CNF22.SENSE register. Write '1' to clear. */ +/* Bit 22 : Status on whether PIN[22] has met criteria set in PIN_CNF[22].SENSE register. Write '1' to clear. */ #define GPIO_LATCH_PIN22_Pos (22UL) /*!< Position of PIN22 field. */ #define GPIO_LATCH_PIN22_Msk (0x1UL << GPIO_LATCH_PIN22_Pos) /*!< Bit mask of PIN22 field. */ #define GPIO_LATCH_PIN22_NotLatched (0UL) /*!< Criteria has not been met */ #define GPIO_LATCH_PIN22_Latched (1UL) /*!< Criteria has been met */ -/* Bit 21 : Status on whether PIN21 has met criteria set in PIN_CNF21.SENSE register. Write '1' to clear. */ +/* Bit 21 : Status on whether PIN[21] has met criteria set in PIN_CNF[21].SENSE register. Write '1' to clear. */ #define GPIO_LATCH_PIN21_Pos (21UL) /*!< Position of PIN21 field. */ #define GPIO_LATCH_PIN21_Msk (0x1UL << GPIO_LATCH_PIN21_Pos) /*!< Bit mask of PIN21 field. */ #define GPIO_LATCH_PIN21_NotLatched (0UL) /*!< Criteria has not been met */ #define GPIO_LATCH_PIN21_Latched (1UL) /*!< Criteria has been met */ -/* Bit 20 : Status on whether PIN20 has met criteria set in PIN_CNF20.SENSE register. Write '1' to clear. */ +/* Bit 20 : Status on whether PIN[20] has met criteria set in PIN_CNF[20].SENSE register. Write '1' to clear. */ #define GPIO_LATCH_PIN20_Pos (20UL) /*!< Position of PIN20 field. */ #define GPIO_LATCH_PIN20_Msk (0x1UL << GPIO_LATCH_PIN20_Pos) /*!< Bit mask of PIN20 field. */ #define GPIO_LATCH_PIN20_NotLatched (0UL) /*!< Criteria has not been met */ #define GPIO_LATCH_PIN20_Latched (1UL) /*!< Criteria has been met */ -/* Bit 19 : Status on whether PIN19 has met criteria set in PIN_CNF19.SENSE register. Write '1' to clear. */ +/* Bit 19 : Status on whether PIN[19] has met criteria set in PIN_CNF[19].SENSE register. Write '1' to clear. */ #define GPIO_LATCH_PIN19_Pos (19UL) /*!< Position of PIN19 field. */ #define GPIO_LATCH_PIN19_Msk (0x1UL << GPIO_LATCH_PIN19_Pos) /*!< Bit mask of PIN19 field. */ #define GPIO_LATCH_PIN19_NotLatched (0UL) /*!< Criteria has not been met */ #define GPIO_LATCH_PIN19_Latched (1UL) /*!< Criteria has been met */ -/* Bit 18 : Status on whether PIN18 has met criteria set in PIN_CNF18.SENSE register. Write '1' to clear. */ +/* Bit 18 : Status on whether PIN[18] has met criteria set in PIN_CNF[18].SENSE register. Write '1' to clear. */ #define GPIO_LATCH_PIN18_Pos (18UL) /*!< Position of PIN18 field. */ #define GPIO_LATCH_PIN18_Msk (0x1UL << GPIO_LATCH_PIN18_Pos) /*!< Bit mask of PIN18 field. */ #define GPIO_LATCH_PIN18_NotLatched (0UL) /*!< Criteria has not been met */ #define GPIO_LATCH_PIN18_Latched (1UL) /*!< Criteria has been met */ -/* Bit 17 : Status on whether PIN17 has met criteria set in PIN_CNF17.SENSE register. Write '1' to clear. */ +/* Bit 17 : Status on whether PIN[17] has met criteria set in PIN_CNF[17].SENSE register. Write '1' to clear. */ #define GPIO_LATCH_PIN17_Pos (17UL) /*!< Position of PIN17 field. */ #define GPIO_LATCH_PIN17_Msk (0x1UL << GPIO_LATCH_PIN17_Pos) /*!< Bit mask of PIN17 field. */ #define GPIO_LATCH_PIN17_NotLatched (0UL) /*!< Criteria has not been met */ #define GPIO_LATCH_PIN17_Latched (1UL) /*!< Criteria has been met */ -/* Bit 16 : Status on whether PIN16 has met criteria set in PIN_CNF16.SENSE register. Write '1' to clear. */ +/* Bit 16 : Status on whether PIN[16] has met criteria set in PIN_CNF[16].SENSE register. Write '1' to clear. */ #define GPIO_LATCH_PIN16_Pos (16UL) /*!< Position of PIN16 field. */ #define GPIO_LATCH_PIN16_Msk (0x1UL << GPIO_LATCH_PIN16_Pos) /*!< Bit mask of PIN16 field. */ #define GPIO_LATCH_PIN16_NotLatched (0UL) /*!< Criteria has not been met */ #define GPIO_LATCH_PIN16_Latched (1UL) /*!< Criteria has been met */ -/* Bit 15 : Status on whether PIN15 has met criteria set in PIN_CNF15.SENSE register. Write '1' to clear. */ +/* Bit 15 : Status on whether PIN[15] has met criteria set in PIN_CNF[15].SENSE register. Write '1' to clear. */ #define GPIO_LATCH_PIN15_Pos (15UL) /*!< Position of PIN15 field. */ #define GPIO_LATCH_PIN15_Msk (0x1UL << GPIO_LATCH_PIN15_Pos) /*!< Bit mask of PIN15 field. */ #define GPIO_LATCH_PIN15_NotLatched (0UL) /*!< Criteria has not been met */ #define GPIO_LATCH_PIN15_Latched (1UL) /*!< Criteria has been met */ -/* Bit 14 : Status on whether PIN14 has met criteria set in PIN_CNF14.SENSE register. Write '1' to clear. */ +/* Bit 14 : Status on whether PIN[14] has met criteria set in PIN_CNF[14].SENSE register. Write '1' to clear. */ #define GPIO_LATCH_PIN14_Pos (14UL) /*!< Position of PIN14 field. */ #define GPIO_LATCH_PIN14_Msk (0x1UL << GPIO_LATCH_PIN14_Pos) /*!< Bit mask of PIN14 field. */ #define GPIO_LATCH_PIN14_NotLatched (0UL) /*!< Criteria has not been met */ #define GPIO_LATCH_PIN14_Latched (1UL) /*!< Criteria has been met */ -/* Bit 13 : Status on whether PIN13 has met criteria set in PIN_CNF13.SENSE register. Write '1' to clear. */ +/* Bit 13 : Status on whether PIN[13] has met criteria set in PIN_CNF[13].SENSE register. Write '1' to clear. */ #define GPIO_LATCH_PIN13_Pos (13UL) /*!< Position of PIN13 field. */ #define GPIO_LATCH_PIN13_Msk (0x1UL << GPIO_LATCH_PIN13_Pos) /*!< Bit mask of PIN13 field. */ #define GPIO_LATCH_PIN13_NotLatched (0UL) /*!< Criteria has not been met */ #define GPIO_LATCH_PIN13_Latched (1UL) /*!< Criteria has been met */ -/* Bit 12 : Status on whether PIN12 has met criteria set in PIN_CNF12.SENSE register. Write '1' to clear. */ +/* Bit 12 : Status on whether PIN[12] has met criteria set in PIN_CNF[12].SENSE register. Write '1' to clear. */ #define GPIO_LATCH_PIN12_Pos (12UL) /*!< Position of PIN12 field. */ #define GPIO_LATCH_PIN12_Msk (0x1UL << GPIO_LATCH_PIN12_Pos) /*!< Bit mask of PIN12 field. */ #define GPIO_LATCH_PIN12_NotLatched (0UL) /*!< Criteria has not been met */ #define GPIO_LATCH_PIN12_Latched (1UL) /*!< Criteria has been met */ -/* Bit 11 : Status on whether PIN11 has met criteria set in PIN_CNF11.SENSE register. Write '1' to clear. */ +/* Bit 11 : Status on whether PIN[11] has met criteria set in PIN_CNF[11].SENSE register. Write '1' to clear. */ #define GPIO_LATCH_PIN11_Pos (11UL) /*!< Position of PIN11 field. */ #define GPIO_LATCH_PIN11_Msk (0x1UL << GPIO_LATCH_PIN11_Pos) /*!< Bit mask of PIN11 field. */ #define GPIO_LATCH_PIN11_NotLatched (0UL) /*!< Criteria has not been met */ #define GPIO_LATCH_PIN11_Latched (1UL) /*!< Criteria has been met */ -/* Bit 10 : Status on whether PIN10 has met criteria set in PIN_CNF10.SENSE register. Write '1' to clear. */ +/* Bit 10 : Status on whether PIN[10] has met criteria set in PIN_CNF[10].SENSE register. Write '1' to clear. */ #define GPIO_LATCH_PIN10_Pos (10UL) /*!< Position of PIN10 field. */ #define GPIO_LATCH_PIN10_Msk (0x1UL << GPIO_LATCH_PIN10_Pos) /*!< Bit mask of PIN10 field. */ #define GPIO_LATCH_PIN10_NotLatched (0UL) /*!< Criteria has not been met */ #define GPIO_LATCH_PIN10_Latched (1UL) /*!< Criteria has been met */ -/* Bit 9 : Status on whether PIN9 has met criteria set in PIN_CNF9.SENSE register. Write '1' to clear. */ +/* Bit 9 : Status on whether PIN[9] has met criteria set in PIN_CNF[9].SENSE register. Write '1' to clear. */ #define GPIO_LATCH_PIN9_Pos (9UL) /*!< Position of PIN9 field. */ #define GPIO_LATCH_PIN9_Msk (0x1UL << GPIO_LATCH_PIN9_Pos) /*!< Bit mask of PIN9 field. */ #define GPIO_LATCH_PIN9_NotLatched (0UL) /*!< Criteria has not been met */ #define GPIO_LATCH_PIN9_Latched (1UL) /*!< Criteria has been met */ -/* Bit 8 : Status on whether PIN8 has met criteria set in PIN_CNF8.SENSE register. Write '1' to clear. */ +/* Bit 8 : Status on whether PIN[8] has met criteria set in PIN_CNF[8].SENSE register. Write '1' to clear. */ #define GPIO_LATCH_PIN8_Pos (8UL) /*!< Position of PIN8 field. */ #define GPIO_LATCH_PIN8_Msk (0x1UL << GPIO_LATCH_PIN8_Pos) /*!< Bit mask of PIN8 field. */ #define GPIO_LATCH_PIN8_NotLatched (0UL) /*!< Criteria has not been met */ #define GPIO_LATCH_PIN8_Latched (1UL) /*!< Criteria has been met */ -/* Bit 7 : Status on whether PIN7 has met criteria set in PIN_CNF7.SENSE register. Write '1' to clear. */ +/* Bit 7 : Status on whether PIN[7] has met criteria set in PIN_CNF[7].SENSE register. Write '1' to clear. */ #define GPIO_LATCH_PIN7_Pos (7UL) /*!< Position of PIN7 field. */ #define GPIO_LATCH_PIN7_Msk (0x1UL << GPIO_LATCH_PIN7_Pos) /*!< Bit mask of PIN7 field. */ #define GPIO_LATCH_PIN7_NotLatched (0UL) /*!< Criteria has not been met */ #define GPIO_LATCH_PIN7_Latched (1UL) /*!< Criteria has been met */ -/* Bit 6 : Status on whether PIN6 has met criteria set in PIN_CNF6.SENSE register. Write '1' to clear. */ +/* Bit 6 : Status on whether PIN[6] has met criteria set in PIN_CNF[6].SENSE register. Write '1' to clear. */ #define GPIO_LATCH_PIN6_Pos (6UL) /*!< Position of PIN6 field. */ #define GPIO_LATCH_PIN6_Msk (0x1UL << GPIO_LATCH_PIN6_Pos) /*!< Bit mask of PIN6 field. */ #define GPIO_LATCH_PIN6_NotLatched (0UL) /*!< Criteria has not been met */ #define GPIO_LATCH_PIN6_Latched (1UL) /*!< Criteria has been met */ -/* Bit 5 : Status on whether PIN5 has met criteria set in PIN_CNF5.SENSE register. Write '1' to clear. */ +/* Bit 5 : Status on whether PIN[5] has met criteria set in PIN_CNF[5].SENSE register. Write '1' to clear. */ #define GPIO_LATCH_PIN5_Pos (5UL) /*!< Position of PIN5 field. */ #define GPIO_LATCH_PIN5_Msk (0x1UL << GPIO_LATCH_PIN5_Pos) /*!< Bit mask of PIN5 field. */ #define GPIO_LATCH_PIN5_NotLatched (0UL) /*!< Criteria has not been met */ #define GPIO_LATCH_PIN5_Latched (1UL) /*!< Criteria has been met */ -/* Bit 4 : Status on whether PIN4 has met criteria set in PIN_CNF4.SENSE register. Write '1' to clear. */ +/* Bit 4 : Status on whether PIN[4] has met criteria set in PIN_CNF[4].SENSE register. Write '1' to clear. */ #define GPIO_LATCH_PIN4_Pos (4UL) /*!< Position of PIN4 field. */ #define GPIO_LATCH_PIN4_Msk (0x1UL << GPIO_LATCH_PIN4_Pos) /*!< Bit mask of PIN4 field. */ #define GPIO_LATCH_PIN4_NotLatched (0UL) /*!< Criteria has not been met */ #define GPIO_LATCH_PIN4_Latched (1UL) /*!< Criteria has been met */ -/* Bit 3 : Status on whether PIN3 has met criteria set in PIN_CNF3.SENSE register. Write '1' to clear. */ +/* Bit 3 : Status on whether PIN[3] has met criteria set in PIN_CNF[3].SENSE register. Write '1' to clear. */ #define GPIO_LATCH_PIN3_Pos (3UL) /*!< Position of PIN3 field. */ #define GPIO_LATCH_PIN3_Msk (0x1UL << GPIO_LATCH_PIN3_Pos) /*!< Bit mask of PIN3 field. */ #define GPIO_LATCH_PIN3_NotLatched (0UL) /*!< Criteria has not been met */ #define GPIO_LATCH_PIN3_Latched (1UL) /*!< Criteria has been met */ -/* Bit 2 : Status on whether PIN2 has met criteria set in PIN_CNF2.SENSE register. Write '1' to clear. */ +/* Bit 2 : Status on whether PIN[2] has met criteria set in PIN_CNF[2].SENSE register. Write '1' to clear. */ #define GPIO_LATCH_PIN2_Pos (2UL) /*!< Position of PIN2 field. */ #define GPIO_LATCH_PIN2_Msk (0x1UL << GPIO_LATCH_PIN2_Pos) /*!< Bit mask of PIN2 field. */ #define GPIO_LATCH_PIN2_NotLatched (0UL) /*!< Criteria has not been met */ #define GPIO_LATCH_PIN2_Latched (1UL) /*!< Criteria has been met */ -/* Bit 1 : Status on whether PIN1 has met criteria set in PIN_CNF1.SENSE register. Write '1' to clear. */ +/* Bit 1 : Status on whether PIN[1] has met criteria set in PIN_CNF[1].SENSE register. Write '1' to clear. */ #define GPIO_LATCH_PIN1_Pos (1UL) /*!< Position of PIN1 field. */ #define GPIO_LATCH_PIN1_Msk (0x1UL << GPIO_LATCH_PIN1_Pos) /*!< Bit mask of PIN1 field. */ #define GPIO_LATCH_PIN1_NotLatched (0UL) /*!< Criteria has not been met */ #define GPIO_LATCH_PIN1_Latched (1UL) /*!< Criteria has been met */ -/* Bit 0 : Status on whether PIN0 has met criteria set in PIN_CNF0.SENSE register. Write '1' to clear. */ +/* Bit 0 : Status on whether PIN[0] has met criteria set in PIN_CNF[0].SENSE register. Write '1' to clear. */ #define GPIO_LATCH_PIN0_Pos (0UL) /*!< Position of PIN0 field. */ #define GPIO_LATCH_PIN0_Msk (0x1UL << GPIO_LATCH_PIN0_Pos) /*!< Bit mask of PIN0 field. */ #define GPIO_LATCH_PIN0_NotLatched (0UL) /*!< Criteria has not been met */ @@ -10328,7 +10331,7 @@ POSSIBILITY OF SUCH DAMAGE. #define QSPI_PSEL_IO1_PIN_Msk (0x1FUL << QSPI_PSEL_IO1_PIN_Pos) /*!< Bit mask of PIN field. */ /* Register: QSPI_PSEL_IO2 */ -/* Description: Pin select for serial data IO2. */ +/* Description: Pin select for serial data WP/IO2. */ /* Bit 31 : Connection */ #define QSPI_PSEL_IO2_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ @@ -10345,7 +10348,7 @@ POSSIBILITY OF SUCH DAMAGE. #define QSPI_PSEL_IO2_PIN_Msk (0x1FUL << QSPI_PSEL_IO2_PIN_Pos) /*!< Bit mask of PIN field. */ /* Register: QSPI_PSEL_IO3 */ -/* Description: Pin select for serial data IO3. */ +/* Description: Pin select for serial data HOLD/IO3. */ /* Bit 31 : Connection */ #define QSPI_PSEL_IO3_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ @@ -10542,6 +10545,7 @@ POSSIBILITY OF SUCH DAMAGE. #define QSPI_IFCONFIG1_SPIMODE_Pos (25UL) /*!< Position of SPIMODE field. */ #define QSPI_IFCONFIG1_SPIMODE_Msk (0x1UL << QSPI_IFCONFIG1_SPIMODE_Pos) /*!< Bit mask of SPIMODE field. */ #define QSPI_IFCONFIG1_SPIMODE_MODE0 (0UL) /*!< Mode 0: Data are captured on the clock rising edge and data is output on a falling edge. Base level of clock is 0 (CPOL=0, CPHA=0). */ +#define QSPI_IFCONFIG1_SPIMODE_MODE3 (1UL) /*!< Mode 3: Data are captured on the clock rising edge and data is output on a falling edge. Base level of clock is 1 (CPOL=1, CPHA=1). */ /* Bit 24 : Enter/exit deep power-down mode (DPM) for external flash memory. */ #define QSPI_IFCONFIG1_DPMEN_Pos (24UL) /*!< Position of DPMEN field. */ @@ -10603,8 +10607,8 @@ POSSIBILITY OF SUCH DAMAGE. #define QSPI_ADDRCONF_MODE_Msk (0x3UL << QSPI_ADDRCONF_MODE_Pos) /*!< Bit mask of MODE field. */ #define QSPI_ADDRCONF_MODE_NoInstr (0UL) /*!< Do not send any instruction. */ #define QSPI_ADDRCONF_MODE_Opcode (1UL) /*!< Send opcode. */ -#define QSPI_ADDRCONF_MODE_OpByte0 (2UL) /*!< Send opcode, byte0. */ -#define QSPI_ADDRCONF_MODE_All (3UL) /*!< Send opcode, byte0, byte1. */ +#define QSPI_ADDRCONF_MODE_OpByte0 (2UL) /*!< Send opcode, BYTE0. */ +#define QSPI_ADDRCONF_MODE_All (3UL) /*!< Send opcode, BYTE0, BYTE1. */ /* Bits 23..16 : Byte 1 following byte 0. */ #define QSPI_ADDRCONF_BYTE1_Pos (16UL) /*!< Position of BYTE1 field. */ @@ -10626,7 +10630,7 @@ POSSIBILITY OF SUCH DAMAGE. #define QSPI_CINSTRCONF_LFSTOP_Msk (0x1UL << QSPI_CINSTRCONF_LFSTOP_Pos) /*!< Bit mask of LFSTOP field. */ #define QSPI_CINSTRCONF_LFSTOP_Stop (1UL) /*!< Stop */ -/* Bit 16 : Enable long frame mode. When enabled, a custom instruction transaction has to be ended by writing the LFSTOP field. */ +/* Bit 16 : Enable Long frame mode. When enabled, a custom instruction transaction has to be ended by writing the LFSTOP field. */ #define QSPI_CINSTRCONF_LFEN_Pos (16UL) /*!< Position of LFEN field. */ #define QSPI_CINSTRCONF_LFEN_Msk (0x1UL << QSPI_CINSTRCONF_LFEN_Pos) /*!< Bit mask of LFEN field. */ #define QSPI_CINSTRCONF_LFEN_Disable (0UL) /*!< Long frame mode disabled */ @@ -10707,6 +10711,13 @@ POSSIBILITY OF SUCH DAMAGE. #define QSPI_CINSTRDAT1_BYTE4_Pos (0UL) /*!< Position of BYTE4 field. */ #define QSPI_CINSTRDAT1_BYTE4_Msk (0xFFUL << QSPI_CINSTRDAT1_BYTE4_Pos) /*!< Bit mask of BYTE4 field. */ +/* Register: QSPI_IFTIMING */ +/* Description: SPI interface timing. */ + +/* Bits 10..8 : Timing related to sampling of the input serial data. The value of RXDELAY specifies the number of prescaled 192 MHz cycles delay from the the rising edge of the SPI Clock (SCK) until the input serial data is sampled. For example, if RXDELAY is set to 0, the input serial data is sampled on the rising edge of SCK. */ +#define QSPI_IFTIMING_RXDELAY_Pos (8UL) /*!< Position of RXDELAY field. */ +#define QSPI_IFTIMING_RXDELAY_Msk (0x7UL << QSPI_IFTIMING_RXDELAY_Pos) /*!< Bit mask of RXDELAY field. */ + /* Peripheral: REGULATORS */ /* Description: Voltage regulators 0 */ @@ -11309,7 +11320,7 @@ POSSIBILITY OF SUCH DAMAGE. #define RTC_COUNTER_COUNTER_Msk (0xFFFFFFUL << RTC_COUNTER_COUNTER_Pos) /*!< Bit mask of COUNTER field. */ /* Register: RTC_PRESCALER */ -/* Description: 12-bit prescaler for counter frequency (32768/(PRESCALER+1)). Must be written when RTC is stopped. */ +/* Description: 12-bit prescaler for counter frequency (32768 / (PRESCALER + 1)). Must be written when RTC is stopped. */ /* Bits 11..0 : Prescaler value */ #define RTC_PRESCALER_PRESCALER_Pos (0UL) /*!< Position of PRESCALER field. */ @@ -11343,9 +11354,9 @@ POSSIBILITY OF SUCH DAMAGE. #define SAADC_TASKS_SAMPLE_TASKS_SAMPLE_Trigger (1UL) /*!< Trigger task */ /* Register: SAADC_TASKS_STOP */ -/* Description: Stop the ADC and terminate any on-going conversion */ +/* Description: Stop the ADC and terminate any ongoing conversion */ -/* Bit 0 : Stop the ADC and terminate any on-going conversion */ +/* Bit 0 : Stop the ADC and terminate any ongoing conversion */ #define SAADC_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */ #define SAADC_TASKS_STOP_TASKS_STOP_Msk (0x1UL << SAADC_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */ #define SAADC_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */ @@ -11438,9 +11449,9 @@ POSSIBILITY OF SUCH DAMAGE. #define SAADC_EVENTS_DONE_EVENTS_DONE_Generated (1UL) /*!< Event generated */ /* Register: SAADC_EVENTS_RESULTDONE */ -/* Description: A result is ready to get transferred to RAM. */ +/* Description: A result is ready to get transferred to RAM */ -/* Bit 0 : A result is ready to get transferred to RAM. */ +/* Bit 0 : A result is ready to get transferred to RAM */ #define SAADC_EVENTS_RESULTDONE_EVENTS_RESULTDONE_Pos (0UL) /*!< Position of EVENTS_RESULTDONE field. */ #define SAADC_EVENTS_RESULTDONE_EVENTS_RESULTDONE_Msk (0x1UL << SAADC_EVENTS_RESULTDONE_EVENTS_RESULTDONE_Pos) /*!< Bit mask of EVENTS_RESULTDONE field. */ #define SAADC_EVENTS_RESULTDONE_EVENTS_RESULTDONE_NotGenerated (0UL) /*!< Event not generated */ @@ -12041,7 +12052,7 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 0 : Status */ #define SAADC_STATUS_STATUS_Pos (0UL) /*!< Position of STATUS field. */ #define SAADC_STATUS_STATUS_Msk (0x1UL << SAADC_STATUS_STATUS_Pos) /*!< Bit mask of STATUS field. */ -#define SAADC_STATUS_STATUS_Ready (0UL) /*!< ADC is ready. No on-going conversion. */ +#define SAADC_STATUS_STATUS_Ready (0UL) /*!< ADC is ready. No ongoing conversion. */ #define SAADC_STATUS_STATUS_Busy (1UL) /*!< ADC is busy. Single conversion in progress. */ /* Register: SAADC_ENABLE */ @@ -12101,7 +12112,7 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 20 : Enable differential mode */ #define SAADC_CH_CONFIG_MODE_Pos (20UL) /*!< Position of MODE field. */ #define SAADC_CH_CONFIG_MODE_Msk (0x1UL << SAADC_CH_CONFIG_MODE_Pos) /*!< Bit mask of MODE field. */ -#define SAADC_CH_CONFIG_MODE_SE (0UL) /*!< Single ended, PSELN will be ignored, negative input to ADC shorted to GND */ +#define SAADC_CH_CONFIG_MODE_SE (0UL) /*!< Single-ended, PSELN will be ignored, negative input to ADC shorted to GND */ #define SAADC_CH_CONFIG_MODE_Diff (1UL) /*!< Differential */ /* Bits 18..16 : Acquisition time, the time the ADC uses to sample the input voltage */ @@ -12195,7 +12206,7 @@ POSSIBILITY OF SUCH DAMAGE. #define SAADC_SAMPLERATE_MODE_Task (0UL) /*!< Rate is controlled from SAMPLE task */ #define SAADC_SAMPLERATE_MODE_Timers (1UL) /*!< Rate is controlled from local timer (use CC to control the rate) */ -/* Bits 10..0 : Capture and compare value. Sample rate is 16 MHz/CC */ +/* Bits 10..0 : Capture and compare value; sample rate is 16 MHz/CC */ #define SAADC_SAMPLERATE_CC_Pos (0UL) /*!< Position of CC field. */ #define SAADC_SAMPLERATE_CC_Msk (0x7FFUL << SAADC_SAMPLERATE_CC_Pos) /*!< Bit mask of CC field. */ @@ -12504,7 +12515,7 @@ POSSIBILITY OF SUCH DAMAGE. #define SPIM_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */ /* Register: SPIM_STALLSTAT */ -/* Description: Stall status for EasyDMA RAM accesses. The fields in this register is set to STALL by hardware whenever a stall occurres and can be cleared (set to NOSTALL) by the CPU. */ +/* Description: Stall status for EasyDMA RAM accesses. The fields in this register are set to STALL by hardware whenever a stall occurres and can be cleared (set to NOSTALL) by the CPU. */ /* Bit 1 : Stall status for EasyDMA RAM writes */ #define SPIM_STALLSTAT_RX_Pos (1UL) /*!< Position of RX field. */ @@ -13257,11 +13268,11 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: SPU_CAP */ /* Description: Show implemented features for the current device */ -/* Bit 0 : Show ARM TrustZone status */ +/* Bit 0 : Show Arm TrustZone status */ #define SPU_CAP_TZM_Pos (0UL) /*!< Position of TZM field. */ #define SPU_CAP_TZM_Msk (0x1UL << SPU_CAP_TZM_Pos) /*!< Bit mask of TZM field. */ -#define SPU_CAP_TZM_NotAvailable (0UL) /*!< ARM TrustZone support not available */ -#define SPU_CAP_TZM_Enabled (1UL) /*!< ARM TrustZone support is available */ +#define SPU_CAP_TZM_NotAvailable (0UL) /*!< Arm TrustZone support not available */ +#define SPU_CAP_TZM_Enabled (1UL) /*!< Arm TrustZone support is available */ /* Register: SPU_CPULOCK */ /* Description: Configure bits to lock down CPU features at runtime */ @@ -13319,199 +13330,199 @@ POSSIBILITY OF SUCH DAMAGE. #define SPU_EXTDOMAIN_PERM_SECUREMAPPING_UserSelectable (2UL) /*!< Non-secure or secure attribute for bus access from this domain is defined by the EXTDOMAIN[n].PERM register */ /* Register: SPU_DPPI_PERM */ -/* Description: Description cluster: Select between secure and non-secure attribute for the DPPI channels. */ +/* Description: Description cluster: Select between secure and non-secure attribute for the DPPI channels */ -/* Bit 31 : Select secure attribute. */ +/* Bit 31 : Select secure attribute */ #define SPU_DPPI_PERM_CHANNEL31_Pos (31UL) /*!< Position of CHANNEL31 field. */ #define SPU_DPPI_PERM_CHANNEL31_Msk (0x1UL << SPU_DPPI_PERM_CHANNEL31_Pos) /*!< Bit mask of CHANNEL31 field. */ -#define SPU_DPPI_PERM_CHANNEL31_NonSecure (0UL) /*!< Channel31 has its non-secure attribute set */ -#define SPU_DPPI_PERM_CHANNEL31_Secure (1UL) /*!< Channel31 has its secure attribute set */ +#define SPU_DPPI_PERM_CHANNEL31_NonSecure (0UL) /*!< Channel 31 has its non-secure attribute set */ +#define SPU_DPPI_PERM_CHANNEL31_Secure (1UL) /*!< Channel 31 has its secure attribute set */ -/* Bit 30 : Select secure attribute. */ +/* Bit 30 : Select secure attribute */ #define SPU_DPPI_PERM_CHANNEL30_Pos (30UL) /*!< Position of CHANNEL30 field. */ #define SPU_DPPI_PERM_CHANNEL30_Msk (0x1UL << SPU_DPPI_PERM_CHANNEL30_Pos) /*!< Bit mask of CHANNEL30 field. */ -#define SPU_DPPI_PERM_CHANNEL30_NonSecure (0UL) /*!< Channel30 has its non-secure attribute set */ -#define SPU_DPPI_PERM_CHANNEL30_Secure (1UL) /*!< Channel30 has its secure attribute set */ +#define SPU_DPPI_PERM_CHANNEL30_NonSecure (0UL) /*!< Channel 30 has its non-secure attribute set */ +#define SPU_DPPI_PERM_CHANNEL30_Secure (1UL) /*!< Channel 30 has its secure attribute set */ -/* Bit 29 : Select secure attribute. */ +/* Bit 29 : Select secure attribute */ #define SPU_DPPI_PERM_CHANNEL29_Pos (29UL) /*!< Position of CHANNEL29 field. */ #define SPU_DPPI_PERM_CHANNEL29_Msk (0x1UL << SPU_DPPI_PERM_CHANNEL29_Pos) /*!< Bit mask of CHANNEL29 field. */ -#define SPU_DPPI_PERM_CHANNEL29_NonSecure (0UL) /*!< Channel29 has its non-secure attribute set */ -#define SPU_DPPI_PERM_CHANNEL29_Secure (1UL) /*!< Channel29 has its secure attribute set */ +#define SPU_DPPI_PERM_CHANNEL29_NonSecure (0UL) /*!< Channel 29 has its non-secure attribute set */ +#define SPU_DPPI_PERM_CHANNEL29_Secure (1UL) /*!< Channel 29 has its secure attribute set */ -/* Bit 28 : Select secure attribute. */ +/* Bit 28 : Select secure attribute */ #define SPU_DPPI_PERM_CHANNEL28_Pos (28UL) /*!< Position of CHANNEL28 field. */ #define SPU_DPPI_PERM_CHANNEL28_Msk (0x1UL << SPU_DPPI_PERM_CHANNEL28_Pos) /*!< Bit mask of CHANNEL28 field. */ -#define SPU_DPPI_PERM_CHANNEL28_NonSecure (0UL) /*!< Channel28 has its non-secure attribute set */ -#define SPU_DPPI_PERM_CHANNEL28_Secure (1UL) /*!< Channel28 has its secure attribute set */ +#define SPU_DPPI_PERM_CHANNEL28_NonSecure (0UL) /*!< Channel 28 has its non-secure attribute set */ +#define SPU_DPPI_PERM_CHANNEL28_Secure (1UL) /*!< Channel 28 has its secure attribute set */ -/* Bit 27 : Select secure attribute. */ +/* Bit 27 : Select secure attribute */ #define SPU_DPPI_PERM_CHANNEL27_Pos (27UL) /*!< Position of CHANNEL27 field. */ #define SPU_DPPI_PERM_CHANNEL27_Msk (0x1UL << SPU_DPPI_PERM_CHANNEL27_Pos) /*!< Bit mask of CHANNEL27 field. */ -#define SPU_DPPI_PERM_CHANNEL27_NonSecure (0UL) /*!< Channel27 has its non-secure attribute set */ -#define SPU_DPPI_PERM_CHANNEL27_Secure (1UL) /*!< Channel27 has its secure attribute set */ +#define SPU_DPPI_PERM_CHANNEL27_NonSecure (0UL) /*!< Channel 27 has its non-secure attribute set */ +#define SPU_DPPI_PERM_CHANNEL27_Secure (1UL) /*!< Channel 27 has its secure attribute set */ -/* Bit 26 : Select secure attribute. */ +/* Bit 26 : Select secure attribute */ #define SPU_DPPI_PERM_CHANNEL26_Pos (26UL) /*!< Position of CHANNEL26 field. */ #define SPU_DPPI_PERM_CHANNEL26_Msk (0x1UL << SPU_DPPI_PERM_CHANNEL26_Pos) /*!< Bit mask of CHANNEL26 field. */ -#define SPU_DPPI_PERM_CHANNEL26_NonSecure (0UL) /*!< Channel26 has its non-secure attribute set */ -#define SPU_DPPI_PERM_CHANNEL26_Secure (1UL) /*!< Channel26 has its secure attribute set */ +#define SPU_DPPI_PERM_CHANNEL26_NonSecure (0UL) /*!< Channel 26 has its non-secure attribute set */ +#define SPU_DPPI_PERM_CHANNEL26_Secure (1UL) /*!< Channel 26 has its secure attribute set */ -/* Bit 25 : Select secure attribute. */ +/* Bit 25 : Select secure attribute */ #define SPU_DPPI_PERM_CHANNEL25_Pos (25UL) /*!< Position of CHANNEL25 field. */ #define SPU_DPPI_PERM_CHANNEL25_Msk (0x1UL << SPU_DPPI_PERM_CHANNEL25_Pos) /*!< Bit mask of CHANNEL25 field. */ -#define SPU_DPPI_PERM_CHANNEL25_NonSecure (0UL) /*!< Channel25 has its non-secure attribute set */ -#define SPU_DPPI_PERM_CHANNEL25_Secure (1UL) /*!< Channel25 has its secure attribute set */ +#define SPU_DPPI_PERM_CHANNEL25_NonSecure (0UL) /*!< Channel 25 has its non-secure attribute set */ +#define SPU_DPPI_PERM_CHANNEL25_Secure (1UL) /*!< Channel 25 has its secure attribute set */ -/* Bit 24 : Select secure attribute. */ +/* Bit 24 : Select secure attribute */ #define SPU_DPPI_PERM_CHANNEL24_Pos (24UL) /*!< Position of CHANNEL24 field. */ #define SPU_DPPI_PERM_CHANNEL24_Msk (0x1UL << SPU_DPPI_PERM_CHANNEL24_Pos) /*!< Bit mask of CHANNEL24 field. */ -#define SPU_DPPI_PERM_CHANNEL24_NonSecure (0UL) /*!< Channel24 has its non-secure attribute set */ -#define SPU_DPPI_PERM_CHANNEL24_Secure (1UL) /*!< Channel24 has its secure attribute set */ +#define SPU_DPPI_PERM_CHANNEL24_NonSecure (0UL) /*!< Channel 24 has its non-secure attribute set */ +#define SPU_DPPI_PERM_CHANNEL24_Secure (1UL) /*!< Channel 24 has its secure attribute set */ -/* Bit 23 : Select secure attribute. */ +/* Bit 23 : Select secure attribute */ #define SPU_DPPI_PERM_CHANNEL23_Pos (23UL) /*!< Position of CHANNEL23 field. */ #define SPU_DPPI_PERM_CHANNEL23_Msk (0x1UL << SPU_DPPI_PERM_CHANNEL23_Pos) /*!< Bit mask of CHANNEL23 field. */ -#define SPU_DPPI_PERM_CHANNEL23_NonSecure (0UL) /*!< Channel23 has its non-secure attribute set */ -#define SPU_DPPI_PERM_CHANNEL23_Secure (1UL) /*!< Channel23 has its secure attribute set */ +#define SPU_DPPI_PERM_CHANNEL23_NonSecure (0UL) /*!< Channel 23 has its non-secure attribute set */ +#define SPU_DPPI_PERM_CHANNEL23_Secure (1UL) /*!< Channel 23 has its secure attribute set */ -/* Bit 22 : Select secure attribute. */ +/* Bit 22 : Select secure attribute */ #define SPU_DPPI_PERM_CHANNEL22_Pos (22UL) /*!< Position of CHANNEL22 field. */ #define SPU_DPPI_PERM_CHANNEL22_Msk (0x1UL << SPU_DPPI_PERM_CHANNEL22_Pos) /*!< Bit mask of CHANNEL22 field. */ -#define SPU_DPPI_PERM_CHANNEL22_NonSecure (0UL) /*!< Channel22 has its non-secure attribute set */ -#define SPU_DPPI_PERM_CHANNEL22_Secure (1UL) /*!< Channel22 has its secure attribute set */ +#define SPU_DPPI_PERM_CHANNEL22_NonSecure (0UL) /*!< Channel 22 has its non-secure attribute set */ +#define SPU_DPPI_PERM_CHANNEL22_Secure (1UL) /*!< Channel 22 has its secure attribute set */ -/* Bit 21 : Select secure attribute. */ +/* Bit 21 : Select secure attribute */ #define SPU_DPPI_PERM_CHANNEL21_Pos (21UL) /*!< Position of CHANNEL21 field. */ #define SPU_DPPI_PERM_CHANNEL21_Msk (0x1UL << SPU_DPPI_PERM_CHANNEL21_Pos) /*!< Bit mask of CHANNEL21 field. */ -#define SPU_DPPI_PERM_CHANNEL21_NonSecure (0UL) /*!< Channel21 has its non-secure attribute set */ -#define SPU_DPPI_PERM_CHANNEL21_Secure (1UL) /*!< Channel21 has its secure attribute set */ +#define SPU_DPPI_PERM_CHANNEL21_NonSecure (0UL) /*!< Channel 21 has its non-secure attribute set */ +#define SPU_DPPI_PERM_CHANNEL21_Secure (1UL) /*!< Channel 21 has its secure attribute set */ -/* Bit 20 : Select secure attribute. */ +/* Bit 20 : Select secure attribute */ #define SPU_DPPI_PERM_CHANNEL20_Pos (20UL) /*!< Position of CHANNEL20 field. */ #define SPU_DPPI_PERM_CHANNEL20_Msk (0x1UL << SPU_DPPI_PERM_CHANNEL20_Pos) /*!< Bit mask of CHANNEL20 field. */ -#define SPU_DPPI_PERM_CHANNEL20_NonSecure (0UL) /*!< Channel20 has its non-secure attribute set */ -#define SPU_DPPI_PERM_CHANNEL20_Secure (1UL) /*!< Channel20 has its secure attribute set */ +#define SPU_DPPI_PERM_CHANNEL20_NonSecure (0UL) /*!< Channel 20 has its non-secure attribute set */ +#define SPU_DPPI_PERM_CHANNEL20_Secure (1UL) /*!< Channel 20 has its secure attribute set */ -/* Bit 19 : Select secure attribute. */ +/* Bit 19 : Select secure attribute */ #define SPU_DPPI_PERM_CHANNEL19_Pos (19UL) /*!< Position of CHANNEL19 field. */ #define SPU_DPPI_PERM_CHANNEL19_Msk (0x1UL << SPU_DPPI_PERM_CHANNEL19_Pos) /*!< Bit mask of CHANNEL19 field. */ -#define SPU_DPPI_PERM_CHANNEL19_NonSecure (0UL) /*!< Channel19 has its non-secure attribute set */ -#define SPU_DPPI_PERM_CHANNEL19_Secure (1UL) /*!< Channel19 has its secure attribute set */ +#define SPU_DPPI_PERM_CHANNEL19_NonSecure (0UL) /*!< Channel 19 has its non-secure attribute set */ +#define SPU_DPPI_PERM_CHANNEL19_Secure (1UL) /*!< Channel 19 has its secure attribute set */ -/* Bit 18 : Select secure attribute. */ +/* Bit 18 : Select secure attribute */ #define SPU_DPPI_PERM_CHANNEL18_Pos (18UL) /*!< Position of CHANNEL18 field. */ #define SPU_DPPI_PERM_CHANNEL18_Msk (0x1UL << SPU_DPPI_PERM_CHANNEL18_Pos) /*!< Bit mask of CHANNEL18 field. */ -#define SPU_DPPI_PERM_CHANNEL18_NonSecure (0UL) /*!< Channel18 has its non-secure attribute set */ -#define SPU_DPPI_PERM_CHANNEL18_Secure (1UL) /*!< Channel18 has its secure attribute set */ +#define SPU_DPPI_PERM_CHANNEL18_NonSecure (0UL) /*!< Channel 18 has its non-secure attribute set */ +#define SPU_DPPI_PERM_CHANNEL18_Secure (1UL) /*!< Channel 18 has its secure attribute set */ -/* Bit 17 : Select secure attribute. */ +/* Bit 17 : Select secure attribute */ #define SPU_DPPI_PERM_CHANNEL17_Pos (17UL) /*!< Position of CHANNEL17 field. */ #define SPU_DPPI_PERM_CHANNEL17_Msk (0x1UL << SPU_DPPI_PERM_CHANNEL17_Pos) /*!< Bit mask of CHANNEL17 field. */ -#define SPU_DPPI_PERM_CHANNEL17_NonSecure (0UL) /*!< Channel17 has its non-secure attribute set */ -#define SPU_DPPI_PERM_CHANNEL17_Secure (1UL) /*!< Channel17 has its secure attribute set */ +#define SPU_DPPI_PERM_CHANNEL17_NonSecure (0UL) /*!< Channel 17 has its non-secure attribute set */ +#define SPU_DPPI_PERM_CHANNEL17_Secure (1UL) /*!< Channel 17 has its secure attribute set */ -/* Bit 16 : Select secure attribute. */ +/* Bit 16 : Select secure attribute */ #define SPU_DPPI_PERM_CHANNEL16_Pos (16UL) /*!< Position of CHANNEL16 field. */ #define SPU_DPPI_PERM_CHANNEL16_Msk (0x1UL << SPU_DPPI_PERM_CHANNEL16_Pos) /*!< Bit mask of CHANNEL16 field. */ -#define SPU_DPPI_PERM_CHANNEL16_NonSecure (0UL) /*!< Channel16 has its non-secure attribute set */ -#define SPU_DPPI_PERM_CHANNEL16_Secure (1UL) /*!< Channel16 has its secure attribute set */ +#define SPU_DPPI_PERM_CHANNEL16_NonSecure (0UL) /*!< Channel 16 has its non-secure attribute set */ +#define SPU_DPPI_PERM_CHANNEL16_Secure (1UL) /*!< Channel 16 has its secure attribute set */ -/* Bit 15 : Select secure attribute. */ +/* Bit 15 : Select secure attribute */ #define SPU_DPPI_PERM_CHANNEL15_Pos (15UL) /*!< Position of CHANNEL15 field. */ #define SPU_DPPI_PERM_CHANNEL15_Msk (0x1UL << SPU_DPPI_PERM_CHANNEL15_Pos) /*!< Bit mask of CHANNEL15 field. */ -#define SPU_DPPI_PERM_CHANNEL15_NonSecure (0UL) /*!< Channel15 has its non-secure attribute set */ -#define SPU_DPPI_PERM_CHANNEL15_Secure (1UL) /*!< Channel15 has its secure attribute set */ +#define SPU_DPPI_PERM_CHANNEL15_NonSecure (0UL) /*!< Channel 15 has its non-secure attribute set */ +#define SPU_DPPI_PERM_CHANNEL15_Secure (1UL) /*!< Channel 15 has its secure attribute set */ -/* Bit 14 : Select secure attribute. */ +/* Bit 14 : Select secure attribute */ #define SPU_DPPI_PERM_CHANNEL14_Pos (14UL) /*!< Position of CHANNEL14 field. */ #define SPU_DPPI_PERM_CHANNEL14_Msk (0x1UL << SPU_DPPI_PERM_CHANNEL14_Pos) /*!< Bit mask of CHANNEL14 field. */ -#define SPU_DPPI_PERM_CHANNEL14_NonSecure (0UL) /*!< Channel14 has its non-secure attribute set */ -#define SPU_DPPI_PERM_CHANNEL14_Secure (1UL) /*!< Channel14 has its secure attribute set */ +#define SPU_DPPI_PERM_CHANNEL14_NonSecure (0UL) /*!< Channel 14 has its non-secure attribute set */ +#define SPU_DPPI_PERM_CHANNEL14_Secure (1UL) /*!< Channel 14 has its secure attribute set */ -/* Bit 13 : Select secure attribute. */ +/* Bit 13 : Select secure attribute */ #define SPU_DPPI_PERM_CHANNEL13_Pos (13UL) /*!< Position of CHANNEL13 field. */ #define SPU_DPPI_PERM_CHANNEL13_Msk (0x1UL << SPU_DPPI_PERM_CHANNEL13_Pos) /*!< Bit mask of CHANNEL13 field. */ -#define SPU_DPPI_PERM_CHANNEL13_NonSecure (0UL) /*!< Channel13 has its non-secure attribute set */ -#define SPU_DPPI_PERM_CHANNEL13_Secure (1UL) /*!< Channel13 has its secure attribute set */ +#define SPU_DPPI_PERM_CHANNEL13_NonSecure (0UL) /*!< Channel 13 has its non-secure attribute set */ +#define SPU_DPPI_PERM_CHANNEL13_Secure (1UL) /*!< Channel 13 has its secure attribute set */ -/* Bit 12 : Select secure attribute. */ +/* Bit 12 : Select secure attribute */ #define SPU_DPPI_PERM_CHANNEL12_Pos (12UL) /*!< Position of CHANNEL12 field. */ #define SPU_DPPI_PERM_CHANNEL12_Msk (0x1UL << SPU_DPPI_PERM_CHANNEL12_Pos) /*!< Bit mask of CHANNEL12 field. */ -#define SPU_DPPI_PERM_CHANNEL12_NonSecure (0UL) /*!< Channel12 has its non-secure attribute set */ -#define SPU_DPPI_PERM_CHANNEL12_Secure (1UL) /*!< Channel12 has its secure attribute set */ +#define SPU_DPPI_PERM_CHANNEL12_NonSecure (0UL) /*!< Channel 12 has its non-secure attribute set */ +#define SPU_DPPI_PERM_CHANNEL12_Secure (1UL) /*!< Channel 12 has its secure attribute set */ -/* Bit 11 : Select secure attribute. */ +/* Bit 11 : Select secure attribute */ #define SPU_DPPI_PERM_CHANNEL11_Pos (11UL) /*!< Position of CHANNEL11 field. */ #define SPU_DPPI_PERM_CHANNEL11_Msk (0x1UL << SPU_DPPI_PERM_CHANNEL11_Pos) /*!< Bit mask of CHANNEL11 field. */ -#define SPU_DPPI_PERM_CHANNEL11_NonSecure (0UL) /*!< Channel11 has its non-secure attribute set */ -#define SPU_DPPI_PERM_CHANNEL11_Secure (1UL) /*!< Channel11 has its secure attribute set */ +#define SPU_DPPI_PERM_CHANNEL11_NonSecure (0UL) /*!< Channel 11 has its non-secure attribute set */ +#define SPU_DPPI_PERM_CHANNEL11_Secure (1UL) /*!< Channel 11 has its secure attribute set */ -/* Bit 10 : Select secure attribute. */ +/* Bit 10 : Select secure attribute */ #define SPU_DPPI_PERM_CHANNEL10_Pos (10UL) /*!< Position of CHANNEL10 field. */ #define SPU_DPPI_PERM_CHANNEL10_Msk (0x1UL << SPU_DPPI_PERM_CHANNEL10_Pos) /*!< Bit mask of CHANNEL10 field. */ -#define SPU_DPPI_PERM_CHANNEL10_NonSecure (0UL) /*!< Channel10 has its non-secure attribute set */ -#define SPU_DPPI_PERM_CHANNEL10_Secure (1UL) /*!< Channel10 has its secure attribute set */ +#define SPU_DPPI_PERM_CHANNEL10_NonSecure (0UL) /*!< Channel 10 has its non-secure attribute set */ +#define SPU_DPPI_PERM_CHANNEL10_Secure (1UL) /*!< Channel 10 has its secure attribute set */ -/* Bit 9 : Select secure attribute. */ +/* Bit 9 : Select secure attribute */ #define SPU_DPPI_PERM_CHANNEL9_Pos (9UL) /*!< Position of CHANNEL9 field. */ #define SPU_DPPI_PERM_CHANNEL9_Msk (0x1UL << SPU_DPPI_PERM_CHANNEL9_Pos) /*!< Bit mask of CHANNEL9 field. */ -#define SPU_DPPI_PERM_CHANNEL9_NonSecure (0UL) /*!< Channel9 has its non-secure attribute set */ -#define SPU_DPPI_PERM_CHANNEL9_Secure (1UL) /*!< Channel9 has its secure attribute set */ +#define SPU_DPPI_PERM_CHANNEL9_NonSecure (0UL) /*!< Channel 9 has its non-secure attribute set */ +#define SPU_DPPI_PERM_CHANNEL9_Secure (1UL) /*!< Channel 9 has its secure attribute set */ -/* Bit 8 : Select secure attribute. */ +/* Bit 8 : Select secure attribute */ #define SPU_DPPI_PERM_CHANNEL8_Pos (8UL) /*!< Position of CHANNEL8 field. */ #define SPU_DPPI_PERM_CHANNEL8_Msk (0x1UL << SPU_DPPI_PERM_CHANNEL8_Pos) /*!< Bit mask of CHANNEL8 field. */ -#define SPU_DPPI_PERM_CHANNEL8_NonSecure (0UL) /*!< Channel8 has its non-secure attribute set */ -#define SPU_DPPI_PERM_CHANNEL8_Secure (1UL) /*!< Channel8 has its secure attribute set */ +#define SPU_DPPI_PERM_CHANNEL8_NonSecure (0UL) /*!< Channel 8 has its non-secure attribute set */ +#define SPU_DPPI_PERM_CHANNEL8_Secure (1UL) /*!< Channel 8 has its secure attribute set */ -/* Bit 7 : Select secure attribute. */ +/* Bit 7 : Select secure attribute */ #define SPU_DPPI_PERM_CHANNEL7_Pos (7UL) /*!< Position of CHANNEL7 field. */ #define SPU_DPPI_PERM_CHANNEL7_Msk (0x1UL << SPU_DPPI_PERM_CHANNEL7_Pos) /*!< Bit mask of CHANNEL7 field. */ -#define SPU_DPPI_PERM_CHANNEL7_NonSecure (0UL) /*!< Channel7 has its non-secure attribute set */ -#define SPU_DPPI_PERM_CHANNEL7_Secure (1UL) /*!< Channel7 has its secure attribute set */ +#define SPU_DPPI_PERM_CHANNEL7_NonSecure (0UL) /*!< Channel 7 has its non-secure attribute set */ +#define SPU_DPPI_PERM_CHANNEL7_Secure (1UL) /*!< Channel 7 has its secure attribute set */ -/* Bit 6 : Select secure attribute. */ +/* Bit 6 : Select secure attribute */ #define SPU_DPPI_PERM_CHANNEL6_Pos (6UL) /*!< Position of CHANNEL6 field. */ #define SPU_DPPI_PERM_CHANNEL6_Msk (0x1UL << SPU_DPPI_PERM_CHANNEL6_Pos) /*!< Bit mask of CHANNEL6 field. */ -#define SPU_DPPI_PERM_CHANNEL6_NonSecure (0UL) /*!< Channel6 has its non-secure attribute set */ -#define SPU_DPPI_PERM_CHANNEL6_Secure (1UL) /*!< Channel6 has its secure attribute set */ +#define SPU_DPPI_PERM_CHANNEL6_NonSecure (0UL) /*!< Channel 6 has its non-secure attribute set */ +#define SPU_DPPI_PERM_CHANNEL6_Secure (1UL) /*!< Channel 6 has its secure attribute set */ -/* Bit 5 : Select secure attribute. */ +/* Bit 5 : Select secure attribute */ #define SPU_DPPI_PERM_CHANNEL5_Pos (5UL) /*!< Position of CHANNEL5 field. */ #define SPU_DPPI_PERM_CHANNEL5_Msk (0x1UL << SPU_DPPI_PERM_CHANNEL5_Pos) /*!< Bit mask of CHANNEL5 field. */ -#define SPU_DPPI_PERM_CHANNEL5_NonSecure (0UL) /*!< Channel5 has its non-secure attribute set */ -#define SPU_DPPI_PERM_CHANNEL5_Secure (1UL) /*!< Channel5 has its secure attribute set */ +#define SPU_DPPI_PERM_CHANNEL5_NonSecure (0UL) /*!< Channel 5 has its non-secure attribute set */ +#define SPU_DPPI_PERM_CHANNEL5_Secure (1UL) /*!< Channel 5 has its secure attribute set */ -/* Bit 4 : Select secure attribute. */ +/* Bit 4 : Select secure attribute */ #define SPU_DPPI_PERM_CHANNEL4_Pos (4UL) /*!< Position of CHANNEL4 field. */ #define SPU_DPPI_PERM_CHANNEL4_Msk (0x1UL << SPU_DPPI_PERM_CHANNEL4_Pos) /*!< Bit mask of CHANNEL4 field. */ -#define SPU_DPPI_PERM_CHANNEL4_NonSecure (0UL) /*!< Channel4 has its non-secure attribute set */ -#define SPU_DPPI_PERM_CHANNEL4_Secure (1UL) /*!< Channel4 has its secure attribute set */ +#define SPU_DPPI_PERM_CHANNEL4_NonSecure (0UL) /*!< Channel 4 has its non-secure attribute set */ +#define SPU_DPPI_PERM_CHANNEL4_Secure (1UL) /*!< Channel 4 has its secure attribute set */ -/* Bit 3 : Select secure attribute. */ +/* Bit 3 : Select secure attribute */ #define SPU_DPPI_PERM_CHANNEL3_Pos (3UL) /*!< Position of CHANNEL3 field. */ #define SPU_DPPI_PERM_CHANNEL3_Msk (0x1UL << SPU_DPPI_PERM_CHANNEL3_Pos) /*!< Bit mask of CHANNEL3 field. */ -#define SPU_DPPI_PERM_CHANNEL3_NonSecure (0UL) /*!< Channel3 has its non-secure attribute set */ -#define SPU_DPPI_PERM_CHANNEL3_Secure (1UL) /*!< Channel3 has its secure attribute set */ +#define SPU_DPPI_PERM_CHANNEL3_NonSecure (0UL) /*!< Channel 3 has its non-secure attribute set */ +#define SPU_DPPI_PERM_CHANNEL3_Secure (1UL) /*!< Channel 3 has its secure attribute set */ -/* Bit 2 : Select secure attribute. */ +/* Bit 2 : Select secure attribute */ #define SPU_DPPI_PERM_CHANNEL2_Pos (2UL) /*!< Position of CHANNEL2 field. */ #define SPU_DPPI_PERM_CHANNEL2_Msk (0x1UL << SPU_DPPI_PERM_CHANNEL2_Pos) /*!< Bit mask of CHANNEL2 field. */ -#define SPU_DPPI_PERM_CHANNEL2_NonSecure (0UL) /*!< Channel2 has its non-secure attribute set */ -#define SPU_DPPI_PERM_CHANNEL2_Secure (1UL) /*!< Channel2 has its secure attribute set */ +#define SPU_DPPI_PERM_CHANNEL2_NonSecure (0UL) /*!< Channel 2 has its non-secure attribute set */ +#define SPU_DPPI_PERM_CHANNEL2_Secure (1UL) /*!< Channel 2 has its secure attribute set */ -/* Bit 1 : Select secure attribute. */ +/* Bit 1 : Select secure attribute */ #define SPU_DPPI_PERM_CHANNEL1_Pos (1UL) /*!< Position of CHANNEL1 field. */ #define SPU_DPPI_PERM_CHANNEL1_Msk (0x1UL << SPU_DPPI_PERM_CHANNEL1_Pos) /*!< Bit mask of CHANNEL1 field. */ -#define SPU_DPPI_PERM_CHANNEL1_NonSecure (0UL) /*!< Channel1 has its non-secure attribute set */ -#define SPU_DPPI_PERM_CHANNEL1_Secure (1UL) /*!< Channel1 has its secure attribute set */ +#define SPU_DPPI_PERM_CHANNEL1_NonSecure (0UL) /*!< Channel 1 has its non-secure attribute set */ +#define SPU_DPPI_PERM_CHANNEL1_Secure (1UL) /*!< Channel 1 has its secure attribute set */ -/* Bit 0 : Select secure attribute. */ +/* Bit 0 : Select secure attribute */ #define SPU_DPPI_PERM_CHANNEL0_Pos (0UL) /*!< Position of CHANNEL0 field. */ #define SPU_DPPI_PERM_CHANNEL0_Msk (0x1UL << SPU_DPPI_PERM_CHANNEL0_Pos) /*!< Bit mask of CHANNEL0 field. */ -#define SPU_DPPI_PERM_CHANNEL0_NonSecure (0UL) /*!< Channel0 has its non-secure attribute set */ -#define SPU_DPPI_PERM_CHANNEL0_Secure (1UL) /*!< Channel0 has its secure attribute set */ +#define SPU_DPPI_PERM_CHANNEL0_NonSecure (0UL) /*!< Channel 0 has its non-secure attribute set */ +#define SPU_DPPI_PERM_CHANNEL0_Secure (1UL) /*!< Channel 0 has its secure attribute set */ /* Register: SPU_DPPI_LOCK */ /* Description: Description cluster: Prevent further modification of the corresponding PERM register */ @@ -13523,7 +13534,7 @@ POSSIBILITY OF SUCH DAMAGE. #define SPU_DPPI_LOCK_LOCK_Locked (1UL) /*!< DPPI[n].PERM register can't be changed until next reset */ /* Register: SPU_GPIOPORT_PERM */ -/* Description: Description cluster: Select between secure and non-secure attribute for pins 0 to 31 of port n. */ +/* Description: Description cluster: Select between secure and non-secure attribute for pins 0 to 31 of port n */ /* Bit 31 : Select secure attribute attribute for PIN 31. */ #define SPU_GPIOPORT_PERM_PIN31_Pos (31UL) /*!< Position of PIN31 field. */ @@ -13752,14 +13763,14 @@ POSSIBILITY OF SUCH DAMAGE. #define SPU_FLASHNSC_SIZE_SIZE_Pos (0UL) /*!< Position of SIZE field. */ #define SPU_FLASHNSC_SIZE_SIZE_Msk (0xFUL << SPU_FLASHNSC_SIZE_SIZE_Pos) /*!< Bit mask of SIZE field. */ #define SPU_FLASHNSC_SIZE_SIZE_Disabled (0UL) /*!< The region n is not defined as a non-secure callable region. Normal security attributes (secure or non-secure) are enforced. */ -#define SPU_FLASHNSC_SIZE_SIZE_32 (1UL) /*!< The region n is defined as non-secure callable with a 32-byte size */ -#define SPU_FLASHNSC_SIZE_SIZE_64 (2UL) /*!< The region n is defined as non-secure callable with a 64-byte size */ -#define SPU_FLASHNSC_SIZE_SIZE_128 (3UL) /*!< The region n is defined as non-secure callable with a 128-byte size */ -#define SPU_FLASHNSC_SIZE_SIZE_256 (4UL) /*!< The region n is defined as non-secure callable with a 256-byte size */ -#define SPU_FLASHNSC_SIZE_SIZE_512 (5UL) /*!< The region n is defined as non-secure callable with a 512-byte size */ -#define SPU_FLASHNSC_SIZE_SIZE_1024 (6UL) /*!< The region n is defined as non-secure callable with a 1024-byte size */ -#define SPU_FLASHNSC_SIZE_SIZE_2048 (7UL) /*!< The region n is defined as non-secure callable with a 2048-byte size */ -#define SPU_FLASHNSC_SIZE_SIZE_4096 (8UL) /*!< The region n is defined as non-secure callable with a 4096-byte size */ +#define SPU_FLASHNSC_SIZE_SIZE_32 (1UL) /*!< The region n is defined as non-secure callable with size 32 bytes */ +#define SPU_FLASHNSC_SIZE_SIZE_64 (2UL) /*!< The region n is defined as non-secure callable with size 64 bytes */ +#define SPU_FLASHNSC_SIZE_SIZE_128 (3UL) /*!< The region n is defined as non-secure callable with size 128 bytes */ +#define SPU_FLASHNSC_SIZE_SIZE_256 (4UL) /*!< The region n is defined as non-secure callable with size 256 bytes */ +#define SPU_FLASHNSC_SIZE_SIZE_512 (5UL) /*!< The region n is defined as non-secure callable with size 512 bytes */ +#define SPU_FLASHNSC_SIZE_SIZE_1024 (6UL) /*!< The region n is defined as non-secure callable with size 1024 bytes */ +#define SPU_FLASHNSC_SIZE_SIZE_2048 (7UL) /*!< The region n is defined as non-secure callable with size 2048 bytes */ +#define SPU_FLASHNSC_SIZE_SIZE_4096 (8UL) /*!< The region n is defined as non-secure callable with size 4096 bytes */ /* Register: SPU_RAMNSC_REGION */ /* Description: Description cluster: Define which RAM region can contain the non-secure callable (NSC) region n */ @@ -13787,14 +13798,14 @@ POSSIBILITY OF SUCH DAMAGE. #define SPU_RAMNSC_SIZE_SIZE_Pos (0UL) /*!< Position of SIZE field. */ #define SPU_RAMNSC_SIZE_SIZE_Msk (0xFUL << SPU_RAMNSC_SIZE_SIZE_Pos) /*!< Bit mask of SIZE field. */ #define SPU_RAMNSC_SIZE_SIZE_Disabled (0UL) /*!< The region n is not defined as a non-secure callable region. Normal security attributes (secure or non-secure) are enforced. */ -#define SPU_RAMNSC_SIZE_SIZE_32 (1UL) /*!< The region n is defined as non-secure callable with a 32-byte size */ -#define SPU_RAMNSC_SIZE_SIZE_64 (2UL) /*!< The region n is defined as non-secure callable with a 64-byte size */ -#define SPU_RAMNSC_SIZE_SIZE_128 (3UL) /*!< The region n is defined as non-secure callable with a 128-byte size */ -#define SPU_RAMNSC_SIZE_SIZE_256 (4UL) /*!< The region n is defined as non-secure callable with a 256-byte size */ -#define SPU_RAMNSC_SIZE_SIZE_512 (5UL) /*!< The region n is defined as non-secure callable with a 512-byte size */ -#define SPU_RAMNSC_SIZE_SIZE_1024 (6UL) /*!< The region n is defined as non-secure callable with a 1024-byte size */ -#define SPU_RAMNSC_SIZE_SIZE_2048 (7UL) /*!< The region n is defined as non-secure callable with a 2048-byte size */ -#define SPU_RAMNSC_SIZE_SIZE_4096 (8UL) /*!< The region n is defined as non-secure callable with a 4096-byte size */ +#define SPU_RAMNSC_SIZE_SIZE_32 (1UL) /*!< The region n is defined as non-secure callable with size 32 bytes */ +#define SPU_RAMNSC_SIZE_SIZE_64 (2UL) /*!< The region n is defined as non-secure callable with size 64 bytes */ +#define SPU_RAMNSC_SIZE_SIZE_128 (3UL) /*!< The region n is defined as non-secure callable with size 128 bytes */ +#define SPU_RAMNSC_SIZE_SIZE_256 (4UL) /*!< The region n is defined as non-secure callable with size 256 bytes */ +#define SPU_RAMNSC_SIZE_SIZE_512 (5UL) /*!< The region n is defined as non-secure callable with size 512 bytes */ +#define SPU_RAMNSC_SIZE_SIZE_1024 (6UL) /*!< The region n is defined as non-secure callable with size 1024 bytes */ +#define SPU_RAMNSC_SIZE_SIZE_2048 (7UL) /*!< The region n is defined as non-secure callable with size 2048 bytes */ +#define SPU_RAMNSC_SIZE_SIZE_4096 (8UL) /*!< The region n is defined as non-secure callable with size 4096 bytes */ /* Register: SPU_FLASHREGION_PERM */ /* Description: Description cluster: Access permissions for flash region n */ @@ -13889,14 +13900,14 @@ POSSIBILITY OF SUCH DAMAGE. #define SPU_PERIPHID_PERM_SECATTR_NonSecure (0UL) /*!< If SECUREMAPPING == UserSelectable: Peripheral is mapped in non-secure peripheral address space. If SECUREMAPPING == Split: Peripheral is mapped in non-secure and secure peripheral address space. */ #define SPU_PERIPHID_PERM_SECATTR_Secure (1UL) /*!< Peripheral is mapped in secure peripheral address space */ -/* Bits 3..2 : Indicate if the peripheral has DMA capabilities and if DMA transfer can be assigned to a different security attribute than the peripheral itself */ +/* Bits 3..2 : Indicates if the peripheral has DMA capabilities and if DMA transfer can be assigned to a different security attribute than the peripheral itself */ #define SPU_PERIPHID_PERM_DMA_Pos (2UL) /*!< Position of DMA field. */ #define SPU_PERIPHID_PERM_DMA_Msk (0x3UL << SPU_PERIPHID_PERM_DMA_Pos) /*!< Bit mask of DMA field. */ #define SPU_PERIPHID_PERM_DMA_NoDMA (0UL) /*!< Peripheral has no DMA capability */ #define SPU_PERIPHID_PERM_DMA_NoSeparateAttribute (1UL) /*!< Peripheral has DMA and DMA transfers always have the same security attribute as assigned to the peripheral */ #define SPU_PERIPHID_PERM_DMA_SeparateAttribute (2UL) /*!< Peripheral has DMA and DMA transfers can have a different security attribute than the one assigned to the peripheral */ -/* Bits 1..0 : Define configuration capabilities for TrustZone Cortex-M secure attribute */ +/* Bits 1..0 : Define configuration capabilities for Arm TrustZone Cortex-M secure attribute */ #define SPU_PERIPHID_PERM_SECUREMAPPING_Pos (0UL) /*!< Position of SECUREMAPPING field. */ #define SPU_PERIPHID_PERM_SECUREMAPPING_Msk (0x3UL << SPU_PERIPHID_PERM_SECUREMAPPING_Pos) /*!< Bit mask of SECUREMAPPING field. */ #define SPU_PERIPHID_PERM_SECUREMAPPING_NonSecure (0UL) /*!< This peripheral is always accessible as a non-secure peripheral */ @@ -13948,7 +13959,7 @@ POSSIBILITY OF SUCH DAMAGE. #define TAD_PSEL_TRACECLK_PIN_Traceclk (12UL) /*!< TRACECLK pin */ /* Register: TAD_PSEL_TRACEDATA0 */ -/* Description: Pin configuration for TRACEDATA[0] and SWO */ +/* Description: Pin configuration for TRACEDATA[0] */ /* Bit 31 : Connection */ #define TAD_PSEL_TRACEDATA0_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ @@ -13959,7 +13970,7 @@ POSSIBILITY OF SUCH DAMAGE. /* Bits 4..0 : Pin number */ #define TAD_PSEL_TRACEDATA0_PIN_Pos (0UL) /*!< Position of PIN field. */ #define TAD_PSEL_TRACEDATA0_PIN_Msk (0x1FUL << TAD_PSEL_TRACEDATA0_PIN_Pos) /*!< Bit mask of PIN field. */ -#define TAD_PSEL_TRACEDATA0_PIN_Tracedata0 (11UL) /*!< TRACEDATA0/SWO pin */ +#define TAD_PSEL_TRACEDATA0_PIN_Tracedata0 (11UL) /*!< TRACEDATA0 pin */ /* Register: TAD_PSEL_TRACEDATA1 */ /* Description: Pin configuration for TRACEDATA[1] */ @@ -14004,15 +14015,15 @@ POSSIBILITY OF SUCH DAMAGE. #define TAD_PSEL_TRACEDATA3_PIN_Tracedata3 (8UL) /*!< TRACEDATA3 pin */ /* Register: TAD_TRACEPORTSPEED */ -/* Description: Clocking options for the Trace Port debug interface. */ +/* Description: Clocking options for the Trace Port debug interface Reset behavior is the same as debug components */ /* Bits 1..0 : Speed of Trace Port clock. Note that the TRACECLK pin output will be divided again by two from the Trace Port clock. */ #define TAD_TRACEPORTSPEED_TRACEPORTSPEED_Pos (0UL) /*!< Position of TRACEPORTSPEED field. */ #define TAD_TRACEPORTSPEED_TRACEPORTSPEED_Msk (0x3UL << TAD_TRACEPORTSPEED_TRACEPORTSPEED_Pos) /*!< Bit mask of TRACEPORTSPEED field. */ #define TAD_TRACEPORTSPEED_TRACEPORTSPEED_64MHz (0UL) /*!< Trace Port clock is: 64MHz */ #define TAD_TRACEPORTSPEED_TRACEPORTSPEED_32MHz (1UL) /*!< Trace Port clock is: 32MHz */ -#define TAD_TRACEPORTSPEED_TRACEPORTSPEED_8MHz (2UL) /*!< Trace Port clock is: 8MHz */ -#define TAD_TRACEPORTSPEED_TRACEPORTSPEED_4MHz (3UL) /*!< Trace Port clock is: 4MHz */ +#define TAD_TRACEPORTSPEED_TRACEPORTSPEED_16MHz (2UL) /*!< Trace Port clock is: 16MHz */ +#define TAD_TRACEPORTSPEED_TRACEPORTSPEED_8MHz (3UL) /*!< Trace Port clock is: 8MHz */ /* Peripheral: TIMER */ @@ -14686,12 +14697,6 @@ POSSIBILITY OF SUCH DAMAGE. #define TWIM_SHORTS_LASTRX_STOP_Disabled (0UL) /*!< Disable shortcut */ #define TWIM_SHORTS_LASTRX_STOP_Enabled (1UL) /*!< Enable shortcut */ -/* Bit 11 : Shortcut between event LASTRX and task SUSPEND */ -#define TWIM_SHORTS_LASTRX_SUSPEND_Pos (11UL) /*!< Position of LASTRX_SUSPEND field. */ -#define TWIM_SHORTS_LASTRX_SUSPEND_Msk (0x1UL << TWIM_SHORTS_LASTRX_SUSPEND_Pos) /*!< Bit mask of LASTRX_SUSPEND field. */ -#define TWIM_SHORTS_LASTRX_SUSPEND_Disabled (0UL) /*!< Disable shortcut */ -#define TWIM_SHORTS_LASTRX_SUSPEND_Enabled (1UL) /*!< Enable shortcut */ - /* Bit 10 : Shortcut between event LASTRX and task STARTTX */ #define TWIM_SHORTS_LASTRX_STARTTX_Pos (10UL) /*!< Position of LASTRX_STARTTX field. */ #define TWIM_SHORTS_LASTRX_STARTTX_Msk (0x1UL << TWIM_SHORTS_LASTRX_STARTTX_Pos) /*!< Bit mask of LASTRX_STARTTX field. */ @@ -15416,7 +15421,7 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: TWIS_MATCH */ /* Description: Status register indicating which address had a match */ -/* Bit 0 : Which of the addresses in {ADDRESS} matched the incoming address */ +/* Bit 0 : Indication of which address in {ADDRESS} that matched the incoming address */ #define TWIS_MATCH_MATCH_Pos (0UL) /*!< Position of MATCH field. */ #define TWIS_MATCH_MATCH_Msk (0x1UL << TWIS_MATCH_MATCH_Pos) /*!< Bit mask of MATCH field. */ @@ -16148,7 +16153,7 @@ POSSIBILITY OF SUCH DAMAGE. #define UARTE_INTENCLR_CTS_Clear (1UL) /*!< Disable */ /* Register: UARTE_ERRORSRC */ -/* Description: Error source Note : this register is read / write one to clear. */ +/* Description: Error source */ /* Bit 3 : Break condition */ #define UARTE_ERRORSRC_BREAK_Pos (3UL) /*!< Position of BREAK field. */ @@ -16274,7 +16279,7 @@ POSSIBILITY OF SUCH DAMAGE. #define UARTE_BAUDRATE_BAUDRATE_Baud250000 (0x04000000UL) /*!< 250000 baud */ #define UARTE_BAUDRATE_BAUDRATE_Baud460800 (0x07400000UL) /*!< 460800 baud (actual rate: 457143) */ #define UARTE_BAUDRATE_BAUDRATE_Baud921600 (0x0F000000UL) /*!< 921600 baud (actual rate: 941176) */ -#define UARTE_BAUDRATE_BAUDRATE_Baud1M (0x10000000UL) /*!< 1Mega baud */ +#define UARTE_BAUDRATE_BAUDRATE_Baud1M (0x10000000UL) /*!< 1 megabaud */ /* Register: UARTE_RXD_PTR */ /* Description: Data pointer */ @@ -16353,25 +16358,16 @@ POSSIBILITY OF SUCH DAMAGE. /* Description: Access port protection */ /* Bits 31..0 : Blocks debugger read/write access to all CPU registers and - memory mapped addresses Using any value except Unprotected will lead to the protection being enabled. */ + memory mapped addresses. */ #define UICR_APPROTECT_PALL_Pos (0UL) /*!< Position of PALL field. */ #define UICR_APPROTECT_PALL_Msk (0xFFFFFFFFUL << UICR_APPROTECT_PALL_Pos) /*!< Bit mask of PALL field. */ #define UICR_APPROTECT_PALL_Protected (0x00000000UL) /*!< Protected */ -#define UICR_APPROTECT_PALL_Unprotected (0xFFFFFFFFUL) /*!< Unprotected */ - -/* Register: UICR_EXTSUPPLY */ -/* Description: Enable external circuitry to be supplied from VDD pin. Applicable in 'High voltage mode' only. */ - -/* Bit 0 : Enable external circuitry to be supplied from VDD pin (output of VREGH stage). */ -#define UICR_EXTSUPPLY_EXTSUPPLY_Pos (0UL) /*!< Position of EXTSUPPLY field. */ -#define UICR_EXTSUPPLY_EXTSUPPLY_Msk (0x1UL << UICR_EXTSUPPLY_EXTSUPPLY_Pos) /*!< Bit mask of EXTSUPPLY field. */ -#define UICR_EXTSUPPLY_EXTSUPPLY_Enabled (0UL) /*!< It is allowed to supply external circuitry from the VDD pin. */ -#define UICR_EXTSUPPLY_EXTSUPPLY_Disabled (1UL) /*!< No current can be drawn from the VDD pin. */ +#define UICR_APPROTECT_PALL_Unprotected (0x50FA50FAUL) /*!< Unprotected */ /* Register: UICR_VREGHVOUT */ -/* Description: GPIO reference voltage / external output supply voltage in 'High voltage mode'. */ +/* Description: Output voltage from the high voltage (VREGH) regulator stage. The maximum output voltage from this stage is given as VDDH - VREGHDROP. */ -/* Bits 2..0 : VREGH regulator output voltage. The maximum output voltage from this stage is given as VDDH - VEXDIF. */ +/* Bits 2..0 : VREGH regulator output voltage. */ #define UICR_VREGHVOUT_VREGHVOUT_Pos (0UL) /*!< Position of VREGHVOUT field. */ #define UICR_VREGHVOUT_VREGHVOUT_Msk (0x7UL << UICR_VREGHVOUT_VREGHVOUT_Pos) /*!< Bit mask of VREGHVOUT field. */ #define UICR_VREGHVOUT_VREGHVOUT_1V8 (0UL) /*!< 1.8 V */ @@ -16396,11 +16392,11 @@ POSSIBILITY OF SUCH DAMAGE. /* Description: Secure access port protection */ /* Bits 31..0 : Blocks debugger read/write access to all secure CPU registers and secure memory - mapped addresses. Using any value except Unprotected will lead to the protection being enabled. */ + mapped addresses. */ #define UICR_SECUREAPPROTECT_PALL_Pos (0UL) /*!< Position of PALL field. */ #define UICR_SECUREAPPROTECT_PALL_Msk (0xFFFFFFFFUL << UICR_SECUREAPPROTECT_PALL_Pos) /*!< Bit mask of PALL field. */ #define UICR_SECUREAPPROTECT_PALL_Protected (0x00000000UL) /*!< Protected */ -#define UICR_SECUREAPPROTECT_PALL_Unprotected (0xFFFFFFFFUL) /*!< Unprotected */ +#define UICR_SECUREAPPROTECT_PALL_Unprotected (0x50FA50FAUL) /*!< Unprotected */ /* Register: UICR_ERASEPROTECT */ /* Description: Erase protection */ @@ -18006,7 +18002,7 @@ POSSIBILITY OF SUCH DAMAGE. /* Bits 15..0 : Controls the split of ISO buffers */ #define USBD_ISOSPLIT_SPLIT_Pos (0UL) /*!< Position of SPLIT field. */ #define USBD_ISOSPLIT_SPLIT_Msk (0xFFFFUL << USBD_ISOSPLIT_SPLIT_Pos) /*!< Bit mask of SPLIT field. */ -#define USBD_ISOSPLIT_SPLIT_OneDir (0x0000UL) /*!< Full buffer dedicated to either iso IN or OUT */ +#define USBD_ISOSPLIT_SPLIT_OneDir (0x0000UL) /*!< Full buffer dedicated to either ISO IN or OUT */ #define USBD_ISOSPLIT_SPLIT_HalfIN (0x0080UL) /*!< Lower half for IN, upper half for OUT */ /* Register: USBD_FRAMECNTR */ @@ -18802,17 +18798,17 @@ POSSIBILITY OF SUCH DAMAGE. /* Description: Watchdog Timer 0 */ /* Register: WDT_TASKS_START */ -/* Description: Start the watchdog */ +/* Description: Start WDT */ -/* Bit 0 : Start the watchdog */ +/* Bit 0 : Start WDT */ #define WDT_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */ #define WDT_TASKS_START_TASKS_START_Msk (0x1UL << WDT_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */ #define WDT_TASKS_START_TASKS_START_Trigger (1UL) /*!< Trigger task */ /* Register: WDT_TASKS_STOP */ -/* Description: Stop the watchdog timer. */ +/* Description: Stop WDT */ -/* Bit 0 : Stop the watchdog timer. */ +/* Bit 0 : Stop WDT */ #define WDT_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */ #define WDT_TASKS_STOP_TASKS_STOP_Msk (0x1UL << WDT_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */ #define WDT_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */ @@ -18958,10 +18954,10 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: WDT_RUNSTATUS */ /* Description: Run status */ -/* Bit 0 : Indicates whether or not the watchdog is running */ +/* Bit 0 : Indicates whether or not WDT is running */ #define WDT_RUNSTATUS_RUNSTATUSWDT_Pos (0UL) /*!< Position of RUNSTATUSWDT field. */ #define WDT_RUNSTATUS_RUNSTATUSWDT_Msk (0x1UL << WDT_RUNSTATUS_RUNSTATUSWDT_Pos) /*!< Bit mask of RUNSTATUSWDT field. */ -#define WDT_RUNSTATUS_RUNSTATUSWDT_NotRunning (0UL) /*!< Watchdog not running */ +#define WDT_RUNSTATUS_RUNSTATUSWDT_NotRunning (0UL) /*!< Watchdog is not running */ #define WDT_RUNSTATUS_RUNSTATUSWDT_Running (1UL) /*!< Watchdog is running */ /* Register: WDT_REQSTATUS */ @@ -19076,31 +19072,31 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: WDT_CONFIG */ /* Description: Configuration register */ -/* Bit 6 : Allow stopping the watchdog */ +/* Bit 6 : Allow stopping WDT */ #define WDT_CONFIG_STOPEN_Pos (6UL) /*!< Position of STOPEN field. */ #define WDT_CONFIG_STOPEN_Msk (0x1UL << WDT_CONFIG_STOPEN_Pos) /*!< Bit mask of STOPEN field. */ -#define WDT_CONFIG_STOPEN_Disable (0UL) /*!< Do not allow stopping the watchdog */ -#define WDT_CONFIG_STOPEN_Enable (1UL) /*!< Allow stopping the watchdog */ +#define WDT_CONFIG_STOPEN_Disable (0UL) /*!< Do not allow stopping WDT */ +#define WDT_CONFIG_STOPEN_Enable (1UL) /*!< Allow stopping WDT */ -/* Bit 3 : Configure the watchdog to either be paused, or kept running, while the CPU is halted by the debugger */ +/* Bit 3 : Configure WDT to either be paused, or kept running, while the CPU is halted by the debugger */ #define WDT_CONFIG_HALT_Pos (3UL) /*!< Position of HALT field. */ #define WDT_CONFIG_HALT_Msk (0x1UL << WDT_CONFIG_HALT_Pos) /*!< Bit mask of HALT field. */ -#define WDT_CONFIG_HALT_Pause (0UL) /*!< Pause watchdog while the CPU is halted by the debugger */ -#define WDT_CONFIG_HALT_Run (1UL) /*!< Keep the watchdog running while the CPU is halted by the debugger */ +#define WDT_CONFIG_HALT_Pause (0UL) /*!< Pause WDT while the CPU is halted by the debugger */ +#define WDT_CONFIG_HALT_Run (1UL) /*!< Keep WDT running while the CPU is halted by the debugger */ -/* Bit 0 : Configure the watchdog to either be paused, or kept running, while the CPU is sleeping */ +/* Bit 0 : Configure WDT to either be paused, or kept running, while the CPU is sleeping */ #define WDT_CONFIG_SLEEP_Pos (0UL) /*!< Position of SLEEP field. */ #define WDT_CONFIG_SLEEP_Msk (0x1UL << WDT_CONFIG_SLEEP_Pos) /*!< Bit mask of SLEEP field. */ -#define WDT_CONFIG_SLEEP_Pause (0UL) /*!< Pause watchdog while the CPU is sleeping */ -#define WDT_CONFIG_SLEEP_Run (1UL) /*!< Keep the watchdog running while the CPU is sleeping */ +#define WDT_CONFIG_SLEEP_Pause (0UL) /*!< Pause WDT while the CPU is sleeping */ +#define WDT_CONFIG_SLEEP_Run (1UL) /*!< Keep WDT running while the CPU is sleeping */ /* Register: WDT_TSEN */ -/* Description: Task Stop Enable */ +/* Description: Task stop enable */ -/* Bits 31..0 : Task stop enable register */ +/* Bits 31..0 : Allow stopping WDT */ #define WDT_TSEN_TSEN_Pos (0UL) /*!< Position of TSEN field. */ #define WDT_TSEN_TSEN_Msk (0xFFFFFFFFUL << WDT_TSEN_TSEN_Pos) /*!< Bit mask of TSEN field. */ -#define WDT_TSEN_TSEN_Enable (0x6E524635UL) /*!< Value to allow stopping the watchdog */ +#define WDT_TSEN_TSEN_Enable (0x6E524635UL) /*!< Value to allow stopping WDT */ /* Register: WDT_RR */ /* Description: Description collection: Reload request n */ diff --git a/mdk/nrf5340_application_name_change.h b/mdk/nrf5340_application_name_change.h new file mode 100644 index 0000000000..2b427e257f --- /dev/null +++ b/mdk/nrf5340_application_name_change.h @@ -0,0 +1,57 @@ +/* + +Copyright (c) 2010 - 2021, Nordic Semiconductor ASA All rights reserved. + +SPDX-License-Identifier: BSD-3-Clause + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + +1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + +2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + +3. Neither the name of Nordic Semiconductor ASA nor the names of its + contributors may be used to endorse or promote products derived from this + software without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE +ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE +LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +POSSIBILITY OF SUCH DAMAGE. + +*/ + +#ifndef NRF5340_APPLICATION_NAME_CHANGE_H +#define NRF5340_APPLICATION_NAME_CHANGE_H + +/*lint ++flb "Enter library region */ + +/* This file is given to prevent your SW from not compiling with the updates made to nrf5340_application.h and + * nrf5340_application_bitfields.h. The macros defined in this file were available previously. Do not use these + * macros on purpose. Use the ones defined in nrf5340_application.h and nrf5340_application_bitfields.h instead. + */ + +/* The serial box interrupt ISRs were renamed. Adding old names as macros. */ +#define SPIM0_SPIS0_TWIM0_TWIS0_UARTE0_IRQHandler SERIAL0_IRQHandler +#define SPIM0_SPIS0_TWIM0_TWIS0_UARTE0_IRQn SERIAL0_IRQn +#define SPIM1_SPIS1_TWIM1_TWIS1_UARTE1_IRQHandler SERIAL1_IRQHandler +#define SPIM1_SPIS1_TWIM1_TWIS1_UARTE1_IRQn SERIAL1_IRQn +#define SPIM2_SPIS2_TWIM2_TWIS2_UARTE2_IRQHandler SERIAL2_IRQHandler +#define SPIM2_SPIS2_TWIM2_TWIS2_UARTE2_IRQn SERIAL2_IRQn +#define SPIM3_SPIS3_TWIM3_TWIS3_UARTE3_IRQHandler SERIAL3_IRQHandler +#define SPIM3_SPIS3_TWIM3_TWIS3_UARTE3_IRQn SERIAL3_IRQn + + /*lint --flb "Leave library region" */ + +#endif /* NRF5340_APPLICATION_NAME_CHANGE_H */ diff --git a/mdk/nrf5340_application_peripherals.h b/mdk/nrf5340_application_peripherals.h index 5eb922d48a..58883cc935 100644 --- a/mdk/nrf5340_application_peripherals.h +++ b/mdk/nrf5340_application_peripherals.h @@ -1,6 +1,8 @@ /* -Copyright (c) 2010 - 2020, Nordic Semiconductor ASA All rights reserved. +Copyright (c) 2010 - 2021, Nordic Semiconductor ASA All rights reserved. + +SPDX-License-Identifier: BSD-3-Clause Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: @@ -38,6 +40,8 @@ POSSIBILITY OF SUCH DAMAGE. #define CLOCK_PRESENT #define CLOCK_COUNT 1 +#define CLOCK_FEATURE_HFCLK_DIVIDE_PRESENT + /* Power Peripheral */ #define POWER_PRESENT #define POWER_COUNT 1 diff --git a/mdk/nrf5340_network.h b/mdk/nrf5340_network.h index e1aae5b304..67ff4c07b5 100644 --- a/mdk/nrf5340_network.h +++ b/mdk/nrf5340_network.h @@ -1,27 +1,28 @@ /* - * Copyright (c) 2010 - 2020, Nordic Semiconductor ASA All rights reserved.Redistribution and use in so - * urce and binary forms, with or withoutmodification, are permitted provided that the following condit - * ions are met:1. Redistributions of source code must retain the above copyright notice, this list of - * conditions and the following disclaimer.2. Redistributions in binary form must reproduce the above c - * opyright notice, this list of conditions and the following disclaimer in the documentation and/or ot - * her materials provided with the distribution.3. Neither the name of Nordic Semiconductor ASA nor the - * names of its contributors may be used to endorse or promote products derived from this software wit - * hout specific prior written permission.THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRI - * BUTORS "AS IS"AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THEIMPLIED WARRA - * NTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSEARE DISCLAIMED. IN NO EVENT SHALL NORD - * IC SEMICONDUCTOR ASA OR CONTRIBUTORS BELIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLA - * RY, ORCONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OFSUBSTITUTE GOODS OR SERVIC - * ES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESSINTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIAB - * ILITY, WHETHER INCONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)ARISING IN A - * NY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THEPOSSIBILITY OF SUCH DAMAGE. + * Copyright (c) 2010 - 2021, Nordic Semiconductor ASA All rights reserved.SPDX-License-Identifier: BSD + * -3-ClauseRedistribution and use in source and binary forms, with or withoutmodification, are permitt + * ed provided that the following conditions are met:1. Redistributions of source code must retain the + * above copyright notice, this list of conditions and the following disclaimer.2. Redistributions in b + * inary form must reproduce the above copyright notice, this list of conditions and the following disc + * laimer in the documentation and/or other materials provided with the distribution.3. Neither the nam + * e of Nordic Semiconductor ASA nor the names of its contributors may be used to endorse or promote pr + * oducts derived from this software without specific prior written permission.THIS SOFTWARE IS PROVIDE + * D BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, + * BUT NOT LIMITED TO, THEIMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSEA + * RE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BELIABLE FOR ANY DIRECT, I + * NDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, ORCONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PRO + * CUREMENT OFSUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESSINTERRUPTION) HOW + * EVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER INCONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE)ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THEP + * OSSIBILITY OF SUCH DAMAGE. * * @file nrf5340_network.h * @brief CMSIS HeaderFile * @version 1 - * @date 04. November 2020 - * @note Generated by SVDConv V3.3.35 on Wednesday, 04.11.2020 13:48:09 + * @date 29. April 2021 + * @note Generated by SVDConv V3.3.35 on Thursday, 29.04.2021 12:43:57 * from File 'nrf5340_network.svd', - * last modified on Wednesday, 04.11.2020 12:48:02 + * last modified on Thursday, 29.04.2021 10:43:41 */ @@ -81,7 +82,7 @@ typedef enum { TEMP_IRQn = 16, /*!< 16 TEMP */ RTC0_IRQn = 17, /*!< 17 RTC0 */ IPC_IRQn = 18, /*!< 18 IPC */ - SPIM0_SPIS0_TWIM0_TWIS0_UARTE0_IRQn= 19, /*!< 19 SPIM0_SPIS0_TWIM0_TWIS0_UARTE0 */ + SERIAL0_IRQn = 19, /*!< 19 SERIAL0 */ EGU0_IRQn = 20, /*!< 20 EGU0 */ RTC1_IRQn = 22, /*!< 22 RTC1 */ TIMER1_IRQn = 24, /*!< 24 TIMER1 */ @@ -158,7 +159,7 @@ typedef struct { * @brief FICR_TRIMCNF [TRIMCNF] (Unspecified) */ typedef struct { - __IOM uint32_t* ADDR; /*!< (@ 0x00000000) Description cluster: Address */ + __IM uint32_t* ADDR; /*!< (@ 0x00000000) Description cluster: Address */ __IM uint32_t DATA; /*!< (@ 0x00000004) Description cluster: Data */ } FICR_TRIMCNF_Type; /*!< Size = 8 (0x8) */ @@ -426,11 +427,11 @@ typedef struct { * @brief ACL_ACL [ACL] (Unspecified) */ typedef struct { - __IOM uint32_t ADDR; /*!< (@ 0x00000000) Description cluster: Configure the word-aligned - start address of region n to protect */ + __IOM uint32_t ADDR; /*!< (@ 0x00000000) Description cluster: Start address of region + to protect. The start address must be word-aligned. */ __IOM uint32_t SIZE; /*!< (@ 0x00000004) Description cluster: Size of region to protect - counting from address ACL[n].ADDR. Write - '0' as no effect. */ + counting from address ACL[n].ADDR. Writing + a '0' has no effect. */ __IOM uint32_t PERM; /*!< (@ 0x00000008) Description cluster: Access permissions for region n as defined by start address ACL[n].ADDR and size ACL[n].SIZE */ @@ -723,7 +724,7 @@ typedef struct { /*!< (@ 0x41006000) CTRLAP_NS St __IM uint32_t RESERVED2[14]; __IOM CTRLAPPERI_APPROTECT_Type APPROTECT; /*!< (@ 0x00000540) Unspecified */ __IM uint32_t RESERVED3[46]; - __IM uint32_t STATUS; /*!< (@ 0x00000600) Status bits for CTRL-AP peripheral */ + __IM uint32_t STATUS; /*!< (@ 0x00000600) Status bits for CTRL-AP peripheral. */ } NRF_CTRLAPPERI_Type; /*!< Size = 1540 (0x604) */ @@ -787,7 +788,7 @@ typedef struct { /*!< (@ 0x41008000) RADIO_NS Str __IOM uint32_t EVENTS_FRAMESTART; /*!< (@ 0x00000138) IEEE 802.15.4 length field received */ __IOM uint32_t EVENTS_EDEND; /*!< (@ 0x0000013C) Sampling of energy detection complete. A new ED sample is ready for readout from the - RADIO.EDSAMPLE register */ + RADIO.EDSAMPLE register. */ __IOM uint32_t EVENTS_EDSTOPPED; /*!< (@ 0x00000140) The sampling of energy detection has stopped */ __IOM uint32_t EVENTS_CCAIDLE; /*!< (@ 0x00000144) Wireless medium in idle - clear to send */ __IOM uint32_t EVENTS_CCABUSY; /*!< (@ 0x00000148) Wireless medium busy - do not send */ @@ -1000,8 +1001,8 @@ typedef struct { /*!< (@ 0x4100A000) GPIOTE_NS St */ typedef struct { /*!< (@ 0x4100B000) WDT_NS Structure */ - __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start the watchdog */ - __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stop the watchdog timer. */ + __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start WDT */ + __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stop WDT */ __IM uint32_t RESERVED[30]; __IOM uint32_t SUBSCRIBE_START; /*!< (@ 0x00000080) Subscribe configuration for task START */ __IOM uint32_t SUBSCRIBE_STOP; /*!< (@ 0x00000084) Subscribe configuration for task STOP */ @@ -1025,7 +1026,7 @@ typedef struct { /*!< (@ 0x4100B000) WDT_NS Struc __IOM uint32_t RREN; /*!< (@ 0x00000508) Enable register for reload request registers */ __IOM uint32_t CONFIG; /*!< (@ 0x0000050C) Configuration register */ __IM uint32_t RESERVED7[4]; - __OM uint32_t TSEN; /*!< (@ 0x00000520) Task Stop Enable */ + __OM uint32_t TSEN; /*!< (@ 0x00000520) Task stop enable */ __IM uint32_t RESERVED8[55]; __OM uint32_t RR[8]; /*!< (@ 0x00000600) Description collection: Reload request n */ } NRF_WDT_Type; /*!< Size = 1568 (0x620) */ @@ -1266,25 +1267,25 @@ typedef struct { /*!< (@ 0x41010000) TEMP_NS Stru __IM uint32_t RESERVED4[127]; __IM int32_t TEMP; /*!< (@ 0x00000508) Temperature in degC (0.25deg steps) */ __IM uint32_t RESERVED5[5]; - __IOM uint32_t A0; /*!< (@ 0x00000520) Slope of 1st piece wise linear function */ - __IOM uint32_t A1; /*!< (@ 0x00000524) Slope of 2nd piece wise linear function */ - __IOM uint32_t A2; /*!< (@ 0x00000528) Slope of 3rd piece wise linear function */ - __IOM uint32_t A3; /*!< (@ 0x0000052C) Slope of 4th piece wise linear function */ - __IOM uint32_t A4; /*!< (@ 0x00000530) Slope of 5th piece wise linear function */ - __IOM uint32_t A5; /*!< (@ 0x00000534) Slope of 6th piece wise linear function */ + __IOM uint32_t A0; /*!< (@ 0x00000520) Slope of first piecewise linear function */ + __IOM uint32_t A1; /*!< (@ 0x00000524) Slope of second piecewise linear function */ + __IOM uint32_t A2; /*!< (@ 0x00000528) Slope of third piecewise linear function */ + __IOM uint32_t A3; /*!< (@ 0x0000052C) Slope of fourth piecewise linear function */ + __IOM uint32_t A4; /*!< (@ 0x00000530) Slope of fifth piecewise linear function */ + __IOM uint32_t A5; /*!< (@ 0x00000534) Slope of sixth piecewise linear function */ __IM uint32_t RESERVED6[2]; - __IOM uint32_t B0; /*!< (@ 0x00000540) y-intercept of 1st piece wise linear function */ - __IOM uint32_t B1; /*!< (@ 0x00000544) y-intercept of 2nd piece wise linear function */ - __IOM uint32_t B2; /*!< (@ 0x00000548) y-intercept of 3rd piece wise linear function */ - __IOM uint32_t B3; /*!< (@ 0x0000054C) y-intercept of 4th piece wise linear function */ - __IOM uint32_t B4; /*!< (@ 0x00000550) y-intercept of 5th piece wise linear function */ - __IOM uint32_t B5; /*!< (@ 0x00000554) y-intercept of 6th piece wise linear function */ + __IOM uint32_t B0; /*!< (@ 0x00000540) y-intercept of first piecewise linear function */ + __IOM uint32_t B1; /*!< (@ 0x00000544) y-intercept of second piecewise linear function */ + __IOM uint32_t B2; /*!< (@ 0x00000548) y-intercept of third piecewise linear function */ + __IOM uint32_t B3; /*!< (@ 0x0000054C) y-intercept of fourth piecewise linear function */ + __IOM uint32_t B4; /*!< (@ 0x00000550) y-intercept of fifth piecewise linear function */ + __IOM uint32_t B5; /*!< (@ 0x00000554) y-intercept of sixth piecewise linear function */ __IM uint32_t RESERVED7[2]; - __IOM uint32_t T0; /*!< (@ 0x00000560) End point of 1st piece wise linear function */ - __IOM uint32_t T1; /*!< (@ 0x00000564) End point of 2nd piece wise linear function */ - __IOM uint32_t T2; /*!< (@ 0x00000568) End point of 3rd piece wise linear function */ - __IOM uint32_t T3; /*!< (@ 0x0000056C) End point of 4th piece wise linear function */ - __IOM uint32_t T4; /*!< (@ 0x00000570) End point of 5th piece wise linear function */ + __IOM uint32_t T0; /*!< (@ 0x00000560) Endpoint of first piecewise linear function */ + __IOM uint32_t T1; /*!< (@ 0x00000564) Endpoint of second piecewise linear function */ + __IOM uint32_t T2; /*!< (@ 0x00000568) Endpoint of third piecewise linear function */ + __IOM uint32_t T3; /*!< (@ 0x0000056C) Endpoint of fourth piecewise linear function */ + __IOM uint32_t T4; /*!< (@ 0x00000570) Endpoint of fifth piecewise linear function */ } NRF_TEMP_Type; /*!< Size = 1396 (0x574) */ @@ -1337,8 +1338,9 @@ typedef struct { /*!< (@ 0x41011000) RTC0_NS Stru __IOM uint32_t EVTENCLR; /*!< (@ 0x00000348) Disable event routing */ __IM uint32_t RESERVED10[110]; __IM uint32_t COUNTER; /*!< (@ 0x00000504) Current counter value */ - __IOM uint32_t PRESCALER; /*!< (@ 0x00000508) 12-bit prescaler for counter frequency (32768/(PRESCALER+1)). - Must be written when RTC is stopped. */ + __IOM uint32_t PRESCALER; /*!< (@ 0x00000508) 12-bit prescaler for counter frequency (32768 + / (PRESCALER + 1)). Must be written when + RTC is stopped. */ __IM uint32_t RESERVED11[13]; __IOM uint32_t CC[4]; /*!< (@ 0x00000540) Description collection: Compare register n */ } NRF_RTC_Type; /*!< Size = 1360 (0x550) */ @@ -1432,7 +1434,7 @@ typedef struct { /*!< (@ 0x41013000) SPIM0_NS Str __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ __IM uint32_t RESERVED16[61]; __IOM uint32_t STALLSTAT; /*!< (@ 0x00000400) Stall status for EasyDMA RAM accesses. The fields - in this register is set to STALL by hardware + in this register are set to STALL by hardware whenever a stall occurres and can be cleared (set to NOSTALL) by the CPU. */ __IM uint32_t RESERVED17[63]; @@ -1730,8 +1732,7 @@ typedef struct { /*!< (@ 0x41013000) UARTE0_NS St __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ __IM uint32_t RESERVED17[93]; - __IOM uint32_t ERRORSRC; /*!< (@ 0x00000480) Error source Note : this register is read / write - one to clear. */ + __IOM uint32_t ERRORSRC; /*!< (@ 0x00000480) Error source */ __IM uint32_t RESERVED18[31]; __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable UART */ __IM uint32_t RESERVED19; diff --git a/mdk/nrf5340_network.svd b/mdk/nrf5340_network.svd index e03445183d..dbc86a68a9 100644 --- a/mdk/nrf5340_network.svd +++ b/mdk/nrf5340_network.svd @@ -8,7 +8,9 @@ 1 nRF53 reference description for system-on-chip with dual ARM 32-bit Cortex-M33 microcontrollers -Copyright (c) 2010 - 2020, Nordic Semiconductor ASA All rights reserved. +Copyright (c) 2010 - 2021, Nordic Semiconductor ASA All rights reserved. + +SPDX-License-Identifier: BSD-3-Clause Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: @@ -179,8 +181,8 @@ POSSIBILITY OF SUCH DAMAGE. 31 - QF - QFxx - 94 pin QFN + QK + QKxx - 94-pin aQFN 0x2000 @@ -453,7 +455,7 @@ POSSIBILITY OF SUCH DAMAGE. ADDR Description cluster: Address 0x000 - read-write + read-only 0xFFFFFFFF uint32_t * @@ -508,14 +510,14 @@ POSSIBILITY OF SUCH DAMAGE. PALL Blocks debugger read/write access to all CPU registers and memory mapped - addresses Using any value except Unprotected will lead to the protection being enabled. + addresses. 0 31 Unprotected Unprotected - 0xFFFFFFFF + 0x50FA50FA Protected @@ -1685,21 +1687,21 @@ POSSIBILITY OF SUCH DAMAGE. MAJOR - Major classification of the type of the debug component as specified in the ARM Architecture Specification for this + Major classification of the type of the debug component as specified in the Arm Architecture Specification for this debug and trace component. 0 3 Controller - Indicates that this component allows a debugger to control other components in a CoreSight SoC-400 system. - 0b0100 + Indicates that this component allows a debugger to control other components in an Arm CoreSight SoC-400 system. + 4 SUB - Sub-classification of the type of the debug component as specified in the ARM Architecture Specification within + Sub-classification of the type of the debug component as specified in the Arm Architecture Specification within the major classification as specified in the MAJOR field. 4 7 @@ -1707,7 +1709,7 @@ POSSIBILITY OF SUCH DAMAGE. Crosstrigger Indicates that this component is a sub-triggering component. - 0b0001 + 1 @@ -1728,8 +1730,8 @@ POSSIBILITY OF SUCH DAMAGE. Code - JEDEC continuation code - 0b0100 + JEDEC continuation code. + 4 @@ -1797,7 +1799,7 @@ POSSIBILITY OF SUCH DAMAGE. PartnumberH Indicates bits[11:8] of the part number of the component. - 0b1101 + 13 @@ -1809,8 +1811,8 @@ POSSIBILITY OF SUCH DAMAGE. Arm - ARM. Bits[3:0] of the JEDEC JEP106 Identity Code - 0b1011 + Arm. Bits[3:0] of the JEDEC JEP106 Identity Code + 11 @@ -1831,8 +1833,8 @@ POSSIBILITY OF SUCH DAMAGE. Arm - ARM. Bits[6:4] of the JEDEC JEP106 Identity Code - 0b011 + Arm. Bits[6:4] of the JEDEC JEP106 Identity Code + 3 @@ -1851,7 +1853,7 @@ POSSIBILITY OF SUCH DAMAGE. Rev0p0 This device is at r0p0 - 0b0000 + 0 @@ -1874,14 +1876,14 @@ POSSIBILITY OF SUCH DAMAGE. Unmodified Indicates that the customer has not modified this component. - 0b000 + 0 REVAND Indicates minor errata fixes specific to the revision of the component being used, for example metal fixes after - implementation. In most cases, this field is 0b0000. ARM recommends that the component designers ensure that a + implementation. In most cases, this field is 0b0000. Arm recommends that the component designers ensure that a metal fix can change this field if required, for example, by driving it from registers that reset to 0b0000. 4 7 @@ -1889,7 +1891,7 @@ POSSIBILITY OF SUCH DAMAGE. NoErrata Indicates that there are no errata fixes to this component. - 0b000 + 0 @@ -1933,7 +1935,7 @@ POSSIBILITY OF SUCH DAMAGE. Value Bits[11:8] of the identification code. - 0b0000 + 0 @@ -1947,7 +1949,7 @@ POSSIBILITY OF SUCH DAMAGE. Coresight Indicates that the component is a CoreSight component. - 0b1001 + 9 @@ -2988,11 +2990,6 @@ POSSIBILITY OF SUCH DAMAGE. 0 1 - - LFULP - 32.768 kHz ultra-low power RC oscillator - 0 - LFRC 32.768 kHz RC oscillator @@ -3061,11 +3058,6 @@ POSSIBILITY OF SUCH DAMAGE. 0 1 - - LFULP - 32.768 kHz ultra-low power RC oscillator - 0 - LFRC 32.768 kHz RC oscillator @@ -3125,11 +3117,6 @@ POSSIBILITY OF SUCH DAMAGE. 0 1 - - LFULP - 32.768 kHz ultra-low power RC oscillator - 0 - LFRC 32.768 kHz RC oscillator @@ -4240,7 +4227,7 @@ POSSIBILITY OF SUCH DAMAGE. DISABLE This register disables the ERASEPROTECT register and performs an ERASEALL operation. 0x004 - read-write + read-writeonce 0x00000000 @@ -4294,7 +4281,9 @@ POSSIBILITY OF SUCH DAMAGE. KEY - Disable APPROTECT and enable debug access to non-secure mode until the next pin reset if the KEY fields match. The current APPROTECT value as configured from UICR is bypassed if the value of the KEY fields are non-zero and the KEY fields match on both the CPU and debugger sides. + If the value of the KEY field is non-zero, and the KEY fields match on both the + CPU and debugger sides, disable APPROTECT and enable debug access to non-secure mode until + the next pin reset, brown-out reset, power-on reset, or watchog timer reset. After reset the debugger side register has a fixed KEY value. To enable debug access, both CTRL-AP and UICR.APPROTECT protection needs to be disabled. 0 31 @@ -4303,25 +4292,25 @@ POSSIBILITY OF SUCH DAMAGE. STATUS - Status bits for CTRL-AP peripheral + Status bits for CTRL-AP peripheral. 0x600 read-only 0x00000000 - APPROTECT - Status bit for access port protection in non-secure mode + UICRAPPROTECT + Status bit for UICR part of access port protection at last reset. 0 0 - Disabled - Non-secure mode access port protection is currently disabled + Enabled + APPROTECT was enabled in UICR 0 - Enabled - Non-secure mode access port protection is currently enabled + Disabled + APPROTECT wasdisabled in UICR 1 @@ -5357,13 +5346,13 @@ POSSIBILITY OF SUCH DAMAGE. EVENTS_EDEND - Sampling of energy detection complete. A new ED sample is ready for readout from the RADIO.EDSAMPLE register + Sampling of energy detection complete. A new ED sample is ready for readout from the RADIO.EDSAMPLE register. 0x13C read-write EVENTS_EDEND - Sampling of energy detection complete. A new ED sample is ready for readout from the RADIO.EDSAMPLE register + Sampling of energy detection complete. A new ED sample is ready for readout from the RADIO.EDSAMPLE register. 0 0 @@ -8305,18 +8294,18 @@ POSSIBILITY OF SUCH DAMAGE. MAP - Channel map selection. + Channel map selection 8 8 Default - Channel map between 2400 MHZ .. 2500 MHz + Channel map between 2400 MHz and 2500 MHz 0 Low - Channel map between 2360 MHZ .. 2460 MHz + Channel map between 2360 MHz and 2460 MHz 1 @@ -8443,12 +8432,12 @@ POSSIBILITY OF SUCH DAMAGE. Ble_LR125Kbit - Long range 125 kbps TX, 125 kbps and 500 kbps RX + Long Range 125 kbps TX, 125 kbps and 500 kbps RX 5 Ble_LR500Kbit - Long range 500 kbps TX, 125 kbps and 500 kbps RX + Long Range 500 kbps TX, 125 kbps and 500 kbps RX 6 @@ -8468,19 +8457,19 @@ POSSIBILITY OF SUCH DAMAGE. LFLEN - Length on air of LENGTH field in number of bits. + Length on air of LENGTH field in number of bits 0 3 S0LEN - Length on air of S0 field in number of bytes. + Length on air of S0 field in number of bytes 8 8 S1LEN - Length on air of S1 field in number of bits. + Length on air of S1 field in number of bits 16 19 @@ -8504,7 +8493,7 @@ POSSIBILITY OF SUCH DAMAGE. CILEN - Length of code indicator - long range + Length of code indicator - Long Range 22 23 @@ -8531,7 +8520,7 @@ POSSIBILITY OF SUCH DAMAGE. LongRange - Preamble - used for BLE long range + Preamble - used for Bluetooth LE Long Range 3 @@ -8890,7 +8879,7 @@ POSSIBILITY OF SUCH DAMAGE. LEN - CRC length in number of bytes. + CRC length in number of bytes For MODE Ble_LR125Kbit and Ble_LR500Kbit, only LEN set to 3 is supported 0 1 @@ -8978,7 +8967,7 @@ POSSIBILITY OF SUCH DAMAGE. TIFS - Interframe spacing in us + Interframe spacing in us. 0 9 @@ -8992,7 +8981,7 @@ POSSIBILITY OF SUCH DAMAGE. RSSISAMPLE - RSSI sample + RSSI sample. 0 6 @@ -9368,7 +9357,7 @@ POSSIBILITY OF SUCH DAMAGE. Fast - Fast ramp-up (tRXEN,FAST and tTXEN,FAST), see electrical specification for more information + Fast ramp-up (tRXEN,FAST and tTXEN,FAST), see electrical specifications for more information 1 @@ -9604,93 +9593,93 @@ POSSIBILITY OF SUCH DAMAGE. 20 - 20 in 8us unit (default) Set to 20 if parsed CTETime is larger han 20 + 20 in 8 us unit (default) Set to 20 if parsed CTETime is larger than 20 0 31 - 31 in 8us unit + 31 in 8 us unit 1 63 - 63 in 8us unit + 63 in 8 us unit 2 CTEINLINERXMODE1US - Spacing between samples for the samples in the SWITCHING period when CTEINLINEMODE is set + Spacing between samples for the samples in the SWITCHING period when CTEINLINEMODE is set. 10 12 4us - 4us + 4 us 1 2us - 2us + 2 us 2 1us - 1us + 1 us 3 500ns - 0.5us + 0.5 us 4 250ns - 0.25us + 0.25 us 5 125ns - 0.125us + 0.125 us 6 CTEINLINERXMODE2US - Spacing between samples for the samples in the SWITCHING period when CTEINLINEMODE is set + Spacing between samples for the samples in the SWITCHING period when CTEINLINEMODE is set. 13 15 4us - 4us + 4 us 1 2us - 2us + 2 us 2 1us - 1us + 1 us 3 500ns - 0.5us + 0.5 us 4 250ns - 0.25us + 0.25 us 5 125ns - 0.125us + 0.125 us 6 @@ -9748,17 +9737,17 @@ POSSIBILITY OF SUCH DAMAGE. 4us - 4us + 4 us 1 2us - 2us + 2 us 2 1us - 1us + 1 us 3 @@ -9771,32 +9760,32 @@ POSSIBILITY OF SUCH DAMAGE. 4us - 4us + 4 us 1 2us - 2us + 2 us 2 1us - 1us + 1 us 3 500ns - 0.5us + 0.5 us 4 250ns - 0.25us + 0.25 us 5 125ns - 0.125us + 0.125 us 6 @@ -9827,32 +9816,32 @@ POSSIBILITY OF SUCH DAMAGE. 4us - 4us + 4 us 1 2us - 2us + 2 us 2 1us - 1us + 1 us 3 500ns - 0.5us + 0.5 us 4 250ns - 0.25us + 0.25 us 5 125ns - 0.125us + 0.125 us 6 @@ -9887,13 +9876,13 @@ POSSIBILITY OF SUCH DAMAGE. TSWITCHOFFSET - Signed value offset after the end of the CRC before starting switching in number of 16M cycles + Signed value offset after the end of the CRC before starting switching in number of 16 MHz clock cycles 0 12 TSAMPLEOFFSET - Signed value offset before starting sampling in number of 16M cycles relative to the beginning of the REFERENCE state - 12 us after switching start + Signed value offset in number of 16 MHz clock cycles for fine tuning of the sampling instant for all IQ samples. With TSAMPLEOFFSET=0 the first sample is taken immediately at the start of the reference period 16 27 @@ -9908,7 +9897,7 @@ POSSIBILITY OF SUCH DAMAGE. SWITCHPATTERN - Fill array of GPIO patterns for antenna control + Fill array of GPIO patterns for antenna control. 0 7 @@ -11330,13 +11319,13 @@ POSSIBILITY OF SUCH DAMAGE. TASKS_START - Start the watchdog + Start WDT 0x000 write-only TASKS_START - Start the watchdog + Start WDT 0 0 @@ -11351,13 +11340,13 @@ POSSIBILITY OF SUCH DAMAGE. TASKS_STOP - Stop the watchdog timer. + Stop WDT 0x004 write-only TASKS_STOP - Stop the watchdog timer. + Stop WDT 0 0 @@ -11802,13 +11791,13 @@ POSSIBILITY OF SUCH DAMAGE. RUNSTATUSWDT - Indicates whether or not the watchdog is running + Indicates whether or not WDT is running 0 0 NotRunning - Watchdog not running + Watchdog is not running 0 @@ -12150,54 +12139,54 @@ POSSIBILITY OF SUCH DAMAGE. SLEEP - Configure the watchdog to either be paused, or kept running, while the CPU is sleeping + Configure WDT to either be paused, or kept running, while the CPU is sleeping 0 0 Pause - Pause watchdog while the CPU is sleeping + Pause WDT while the CPU is sleeping 0 Run - Keep the watchdog running while the CPU is sleeping + Keep WDT running while the CPU is sleeping 1 HALT - Configure the watchdog to either be paused, or kept running, while the CPU is halted by the debugger + Configure WDT to either be paused, or kept running, while the CPU is halted by the debugger 3 3 Pause - Pause watchdog while the CPU is halted by the debugger + Pause WDT while the CPU is halted by the debugger 0 Run - Keep the watchdog running while the CPU is halted by the debugger + Keep WDT running while the CPU is halted by the debugger 1 STOPEN - Allow stopping the watchdog + Allow stopping WDT 6 6 Disable - Do not allow stopping the watchdog + Do not allow stopping WDT 0 Enable - Allow stopping the watchdog + Allow stopping WDT 1 @@ -12206,20 +12195,20 @@ POSSIBILITY OF SUCH DAMAGE. TSEN - Task Stop Enable + Task stop enable 0x520 write-only 0x00000000 TSEN - Task stop enable register + Allow stopping WDT 0 31 Enable - Value to allow stopping the watchdog + Value to allow stopping WDT 0x6E524635 @@ -14569,7 +14558,7 @@ POSSIBILITY OF SUCH DAMAGE. NIRK - Number of Identity root keys available in the IRK data structure + Number of Identity Root Keys available in the IRK data structure 0 4 @@ -15317,12 +15306,12 @@ POSSIBILITY OF SUCH DAMAGE. 125Kbps - 125 Kbps + 125 kbps 2 500Kbps - 500 Kbps + 500 kbps 3 @@ -15444,12 +15433,12 @@ POSSIBILITY OF SUCH DAMAGE. 125Kbps - 125 Kbps + 125 kbps 2 500Kbps - 500 Kbps + 500 kbps 3 @@ -17355,14 +17344,14 @@ POSSIBILITY OF SUCH DAMAGE. A0 - Slope of 1st piece wise linear function + Slope of first piecewise linear function 0x520 read-write 0x000002D9 A0 - Slope of 1st piece wise linear function + Slope of first piecewise linear function 0 11 @@ -17370,14 +17359,14 @@ POSSIBILITY OF SUCH DAMAGE. A1 - Slope of 2nd piece wise linear function + Slope of second piecewise linear function 0x524 read-write 0x00000322 A1 - Slope of 2nd piece wise linear function + Slope of second piecewise linear function 0 11 @@ -17385,14 +17374,14 @@ POSSIBILITY OF SUCH DAMAGE. A2 - Slope of 3rd piece wise linear function + Slope of third piecewise linear function 0x528 read-write 0x00000355 A2 - Slope of 3rd piece wise linear function + Slope of third piecewise linear function 0 11 @@ -17400,14 +17389,14 @@ POSSIBILITY OF SUCH DAMAGE. A3 - Slope of 4th piece wise linear function + Slope of fourth piecewise linear function 0x52C read-write 0x000003DF A3 - Slope of 4th piece wise linear function + Slope of fourth piecewise linear function 0 11 @@ -17415,14 +17404,14 @@ POSSIBILITY OF SUCH DAMAGE. A4 - Slope of 5th piece wise linear function + Slope of fifth piecewise linear function 0x530 read-write 0x0000044E A4 - Slope of 5th piece wise linear function + Slope of fifth piecewise linear function 0 11 @@ -17430,14 +17419,14 @@ POSSIBILITY OF SUCH DAMAGE. A5 - Slope of 6th piece wise linear function + Slope of sixth piecewise linear function 0x534 read-write 0x000004B7 A5 - Slope of 6th piece wise linear function + Slope of sixth piecewise linear function 0 11 @@ -17445,14 +17434,14 @@ POSSIBILITY OF SUCH DAMAGE. B0 - y-intercept of 1st piece wise linear function + y-intercept of first piecewise linear function 0x540 read-write 0x00000FC7 B0 - y-intercept of 1st piece wise linear function + y-intercept of first piecewise linear function 0 11 @@ -17460,14 +17449,14 @@ POSSIBILITY OF SUCH DAMAGE. B1 - y-intercept of 2nd piece wise linear function + y-intercept of second piecewise linear function 0x544 read-write 0x00000F71 B1 - y-intercept of 2nd piece wise linear function + y-intercept of second piecewise linear function 0 11 @@ -17475,14 +17464,14 @@ POSSIBILITY OF SUCH DAMAGE. B2 - y-intercept of 3rd piece wise linear function + y-intercept of third piecewise linear function 0x548 read-write 0x00000F6C B2 - y-intercept of 3rd piece wise linear function + y-intercept of third piecewise linear function 0 11 @@ -17490,14 +17479,14 @@ POSSIBILITY OF SUCH DAMAGE. B3 - y-intercept of 4th piece wise linear function + y-intercept of fourth piecewise linear function 0x54C read-write 0x00000FCB B3 - y-intercept of 4th piece wise linear function + y-intercept of fourth piecewise linear function 0 11 @@ -17505,14 +17494,14 @@ POSSIBILITY OF SUCH DAMAGE. B4 - y-intercept of 5th piece wise linear function + y-intercept of fifth piecewise linear function 0x550 read-write 0x0000004B B4 - y-intercept of 5th piece wise linear function + y-intercept of fifth piecewise linear function 0 11 @@ -17520,14 +17509,14 @@ POSSIBILITY OF SUCH DAMAGE. B5 - y-intercept of 6th piece wise linear function + y-intercept of sixth piecewise linear function 0x554 read-write 0x000000F6 B5 - y-intercept of 6th piece wise linear function + y-intercept of sixth piecewise linear function 0 11 @@ -17535,14 +17524,14 @@ POSSIBILITY OF SUCH DAMAGE. T0 - End point of 1st piece wise linear function + Endpoint of first piecewise linear function 0x560 read-write 0x000000E1 T0 - End point of 1st piece wise linear function + Endpoint of first piecewise linear function 0 7 @@ -17550,14 +17539,14 @@ POSSIBILITY OF SUCH DAMAGE. T1 - End point of 2nd piece wise linear function + Endpoint of second piecewise linear function 0x564 read-write 0x000000F9 T1 - End point of 2nd piece wise linear function + Endpoint of second piecewise linear function 0 7 @@ -17565,14 +17554,14 @@ POSSIBILITY OF SUCH DAMAGE. T2 - End point of 3rd piece wise linear function + Endpoint of third piecewise linear function 0x568 read-write 0x00000010 T2 - End point of 3rd piece wise linear function + Endpoint of third piecewise linear function 0 7 @@ -17580,14 +17569,14 @@ POSSIBILITY OF SUCH DAMAGE. T3 - End point of 4th piece wise linear function + Endpoint of fourth piecewise linear function 0x56C read-write 0x00000026 T3 - End point of 4th piece wise linear function + Endpoint of fourth piecewise linear function 0 7 @@ -17595,14 +17584,14 @@ POSSIBILITY OF SUCH DAMAGE. T4 - End point of 5th piece wise linear function + Endpoint of fifth piecewise linear function 0x570 read-write 0x0000003F T4 - End point of 5th piece wise linear function + Endpoint of fifth piecewise linear function 0 7 @@ -18960,7 +18949,7 @@ POSSIBILITY OF SUCH DAMAGE. PRESCALER - 12-bit prescaler for counter frequency (32768/(PRESCALER+1)). Must be written when RTC is stopped. + 12-bit prescaler for counter frequency (32768 / (PRESCALER + 1)). Must be written when RTC is stopped. 0x508 read-write @@ -21244,7 +21233,7 @@ POSSIBILITY OF SUCH DAMAGE. registers - SPIM0_SPIS0_TWIM0_TWIS0_UARTE0 + SERIAL0 19 SPIM @@ -22057,7 +22046,7 @@ POSSIBILITY OF SUCH DAMAGE. STALLSTAT - Stall status for EasyDMA RAM accesses. The fields in this register is set to STALL by hardware whenever a stall occurres and can be cleared (set to NOSTALL) by the CPU. + Stall status for EasyDMA RAM accesses. The fields in this register are set to STALL by hardware whenever a stall occurres and can be cleared (set to NOSTALL) by the CPU. 0x400 read-write 0x00000000 @@ -22710,7 +22699,7 @@ POSSIBILITY OF SUCH DAMAGE. registers - SPIM0_SPIS0_TWIM0_TWIS0_UARTE0 + SERIAL0 19 SPIS @@ -23739,7 +23728,7 @@ POSSIBILITY OF SUCH DAMAGE. registers - SPIM0_SPIS0_TWIM0_TWIS0_UARTE0 + SERIAL0 19 TWIM @@ -24482,24 +24471,6 @@ POSSIBILITY OF SUCH DAMAGE. - - LASTRX_SUSPEND - Shortcut between event LASTRX and task SUSPEND - 11 - 11 - - - Disabled - Disable shortcut - 0 - - - Enabled - Enable shortcut - 1 - - - LASTRX_STOP Shortcut between event LASTRX and task STOP @@ -25439,7 +25410,7 @@ POSSIBILITY OF SUCH DAMAGE. registers - SPIM0_SPIS0_TWIM0_TWIS0_UARTE0 + SERIAL0 19 TWIS @@ -26618,7 +26589,7 @@ POSSIBILITY OF SUCH DAMAGE. MATCH - Which of the addresses in {ADDRESS} matched the incoming address + Indication of which address in {ADDRESS} that matched the incoming address 0 0 @@ -26976,7 +26947,7 @@ POSSIBILITY OF SUCH DAMAGE. registers - SPIM0_SPIS0_TWIM0_TWIS0_UARTE0 + SERIAL0 19 UARTE @@ -28731,7 +28702,7 @@ POSSIBILITY OF SUCH DAMAGE. ERRORSRC - Error source Note : this register is read / write one to clear. + Error source 0x480 read-write oneToClear @@ -29103,7 +29074,7 @@ POSSIBILITY OF SUCH DAMAGE. Baud1M - 1Mega baud + 1 megabaud 0x10000000 @@ -30775,14 +30746,14 @@ POSSIBILITY OF SUCH DAMAGE. 0x800 ADDR - Description cluster: Configure the word-aligned start address of region n to protect + Description cluster: Start address of region to protect. The start address must be word-aligned. 0x000 read-writeonce 0x00000000 ADDR - Valid word-aligned start address of region n to protect. Address must point to a flash page boundary. + Start address of flash region n. The start address must point to a flash page boundary. 0 31 @@ -30790,7 +30761,7 @@ POSSIBILITY OF SUCH DAMAGE. SIZE - Description cluster: Size of region to protect counting from address ACL[n].ADDR. Write '0' as no effect. + Description cluster: Size of region to protect counting from address ACL[n].ADDR. Writing a '0' has no effect. 0x004 read-writeonce 0x00000000 @@ -30812,36 +30783,36 @@ POSSIBILITY OF SUCH DAMAGE. WRITE - Configure write and erase permissions for region n. Write '0' has no effect. + Configure write and erase permissions for region n. Writing a '0' has no effect. 1 1 Enable - Allow write and erase instructions to region n + Allow write and erase instructions to region n. 0 Disable - Block write and erase instructions to region n + Block write and erase instructions to region n. 1 READ - Configure read permissions for region n. Write '0' has no effect. + Configure read permissions for region n. Writing a '0' has no effect. 2 2 Enable - Allow read instructions to region n + Allow read instructions to region n. 0 Disable - Block read instructions to region n + Block read instructions to region n. 1 @@ -30882,7 +30853,7 @@ POSSIBILITY OF SUCH DAMAGE. Busy - NVMC is busy (on-going write or erase operation) + NVMC is busy (ongoing write or erase operation) 0 @@ -30967,7 +30938,7 @@ POSSIBILITY OF SUCH DAMAGE. ERASEALL - Erase all non-volatile memory including UICR registers. Note that erasing must be enabled by setting CONFIG.WEN = Een before the non-volatile memory can be erased. + Erase all non-volatile memory including UICR registers. Before the non-volatile memory can be erased, erasing must be enabled by setting CONFIG.WEN=Een. 0 0 @@ -36751,7 +36722,7 @@ POSSIBILITY OF SUCH DAMAGE. PIN0 - Status on whether PIN0 has met criteria set in PIN_CNF0.SENSE register. Write '1' to clear. + Status on whether PIN[0] has met criteria set in PIN_CNF[0].SENSE register. Write '1' to clear. 0 0 @@ -36769,7 +36740,7 @@ POSSIBILITY OF SUCH DAMAGE. PIN1 - Status on whether PIN1 has met criteria set in PIN_CNF1.SENSE register. Write '1' to clear. + Status on whether PIN[1] has met criteria set in PIN_CNF[1].SENSE register. Write '1' to clear. 1 1 @@ -36787,7 +36758,7 @@ POSSIBILITY OF SUCH DAMAGE. PIN2 - Status on whether PIN2 has met criteria set in PIN_CNF2.SENSE register. Write '1' to clear. + Status on whether PIN[2] has met criteria set in PIN_CNF[2].SENSE register. Write '1' to clear. 2 2 @@ -36805,7 +36776,7 @@ POSSIBILITY OF SUCH DAMAGE. PIN3 - Status on whether PIN3 has met criteria set in PIN_CNF3.SENSE register. Write '1' to clear. + Status on whether PIN[3] has met criteria set in PIN_CNF[3].SENSE register. Write '1' to clear. 3 3 @@ -36823,7 +36794,7 @@ POSSIBILITY OF SUCH DAMAGE. PIN4 - Status on whether PIN4 has met criteria set in PIN_CNF4.SENSE register. Write '1' to clear. + Status on whether PIN[4] has met criteria set in PIN_CNF[4].SENSE register. Write '1' to clear. 4 4 @@ -36841,7 +36812,7 @@ POSSIBILITY OF SUCH DAMAGE. PIN5 - Status on whether PIN5 has met criteria set in PIN_CNF5.SENSE register. Write '1' to clear. + Status on whether PIN[5] has met criteria set in PIN_CNF[5].SENSE register. Write '1' to clear. 5 5 @@ -36859,7 +36830,7 @@ POSSIBILITY OF SUCH DAMAGE. PIN6 - Status on whether PIN6 has met criteria set in PIN_CNF6.SENSE register. Write '1' to clear. + Status on whether PIN[6] has met criteria set in PIN_CNF[6].SENSE register. Write '1' to clear. 6 6 @@ -36877,7 +36848,7 @@ POSSIBILITY OF SUCH DAMAGE. PIN7 - Status on whether PIN7 has met criteria set in PIN_CNF7.SENSE register. Write '1' to clear. + Status on whether PIN[7] has met criteria set in PIN_CNF[7].SENSE register. Write '1' to clear. 7 7 @@ -36895,7 +36866,7 @@ POSSIBILITY OF SUCH DAMAGE. PIN8 - Status on whether PIN8 has met criteria set in PIN_CNF8.SENSE register. Write '1' to clear. + Status on whether PIN[8] has met criteria set in PIN_CNF[8].SENSE register. Write '1' to clear. 8 8 @@ -36913,7 +36884,7 @@ POSSIBILITY OF SUCH DAMAGE. PIN9 - Status on whether PIN9 has met criteria set in PIN_CNF9.SENSE register. Write '1' to clear. + Status on whether PIN[9] has met criteria set in PIN_CNF[9].SENSE register. Write '1' to clear. 9 9 @@ -36931,7 +36902,7 @@ POSSIBILITY OF SUCH DAMAGE. PIN10 - Status on whether PIN10 has met criteria set in PIN_CNF10.SENSE register. Write '1' to clear. + Status on whether PIN[10] has met criteria set in PIN_CNF[10].SENSE register. Write '1' to clear. 10 10 @@ -36949,7 +36920,7 @@ POSSIBILITY OF SUCH DAMAGE. PIN11 - Status on whether PIN11 has met criteria set in PIN_CNF11.SENSE register. Write '1' to clear. + Status on whether PIN[11] has met criteria set in PIN_CNF[11].SENSE register. Write '1' to clear. 11 11 @@ -36967,7 +36938,7 @@ POSSIBILITY OF SUCH DAMAGE. PIN12 - Status on whether PIN12 has met criteria set in PIN_CNF12.SENSE register. Write '1' to clear. + Status on whether PIN[12] has met criteria set in PIN_CNF[12].SENSE register. Write '1' to clear. 12 12 @@ -36985,7 +36956,7 @@ POSSIBILITY OF SUCH DAMAGE. PIN13 - Status on whether PIN13 has met criteria set in PIN_CNF13.SENSE register. Write '1' to clear. + Status on whether PIN[13] has met criteria set in PIN_CNF[13].SENSE register. Write '1' to clear. 13 13 @@ -37003,7 +36974,7 @@ POSSIBILITY OF SUCH DAMAGE. PIN14 - Status on whether PIN14 has met criteria set in PIN_CNF14.SENSE register. Write '1' to clear. + Status on whether PIN[14] has met criteria set in PIN_CNF[14].SENSE register. Write '1' to clear. 14 14 @@ -37021,7 +36992,7 @@ POSSIBILITY OF SUCH DAMAGE. PIN15 - Status on whether PIN15 has met criteria set in PIN_CNF15.SENSE register. Write '1' to clear. + Status on whether PIN[15] has met criteria set in PIN_CNF[15].SENSE register. Write '1' to clear. 15 15 @@ -37039,7 +37010,7 @@ POSSIBILITY OF SUCH DAMAGE. PIN16 - Status on whether PIN16 has met criteria set in PIN_CNF16.SENSE register. Write '1' to clear. + Status on whether PIN[16] has met criteria set in PIN_CNF[16].SENSE register. Write '1' to clear. 16 16 @@ -37057,7 +37028,7 @@ POSSIBILITY OF SUCH DAMAGE. PIN17 - Status on whether PIN17 has met criteria set in PIN_CNF17.SENSE register. Write '1' to clear. + Status on whether PIN[17] has met criteria set in PIN_CNF[17].SENSE register. Write '1' to clear. 17 17 @@ -37075,7 +37046,7 @@ POSSIBILITY OF SUCH DAMAGE. PIN18 - Status on whether PIN18 has met criteria set in PIN_CNF18.SENSE register. Write '1' to clear. + Status on whether PIN[18] has met criteria set in PIN_CNF[18].SENSE register. Write '1' to clear. 18 18 @@ -37093,7 +37064,7 @@ POSSIBILITY OF SUCH DAMAGE. PIN19 - Status on whether PIN19 has met criteria set in PIN_CNF19.SENSE register. Write '1' to clear. + Status on whether PIN[19] has met criteria set in PIN_CNF[19].SENSE register. Write '1' to clear. 19 19 @@ -37111,7 +37082,7 @@ POSSIBILITY OF SUCH DAMAGE. PIN20 - Status on whether PIN20 has met criteria set in PIN_CNF20.SENSE register. Write '1' to clear. + Status on whether PIN[20] has met criteria set in PIN_CNF[20].SENSE register. Write '1' to clear. 20 20 @@ -37129,7 +37100,7 @@ POSSIBILITY OF SUCH DAMAGE. PIN21 - Status on whether PIN21 has met criteria set in PIN_CNF21.SENSE register. Write '1' to clear. + Status on whether PIN[21] has met criteria set in PIN_CNF[21].SENSE register. Write '1' to clear. 21 21 @@ -37147,7 +37118,7 @@ POSSIBILITY OF SUCH DAMAGE. PIN22 - Status on whether PIN22 has met criteria set in PIN_CNF22.SENSE register. Write '1' to clear. + Status on whether PIN[22] has met criteria set in PIN_CNF[22].SENSE register. Write '1' to clear. 22 22 @@ -37165,7 +37136,7 @@ POSSIBILITY OF SUCH DAMAGE. PIN23 - Status on whether PIN23 has met criteria set in PIN_CNF23.SENSE register. Write '1' to clear. + Status on whether PIN[23] has met criteria set in PIN_CNF[23].SENSE register. Write '1' to clear. 23 23 @@ -37183,7 +37154,7 @@ POSSIBILITY OF SUCH DAMAGE. PIN24 - Status on whether PIN24 has met criteria set in PIN_CNF24.SENSE register. Write '1' to clear. + Status on whether PIN[24] has met criteria set in PIN_CNF[24].SENSE register. Write '1' to clear. 24 24 @@ -37201,7 +37172,7 @@ POSSIBILITY OF SUCH DAMAGE. PIN25 - Status on whether PIN25 has met criteria set in PIN_CNF25.SENSE register. Write '1' to clear. + Status on whether PIN[25] has met criteria set in PIN_CNF[25].SENSE register. Write '1' to clear. 25 25 @@ -37219,7 +37190,7 @@ POSSIBILITY OF SUCH DAMAGE. PIN26 - Status on whether PIN26 has met criteria set in PIN_CNF26.SENSE register. Write '1' to clear. + Status on whether PIN[26] has met criteria set in PIN_CNF[26].SENSE register. Write '1' to clear. 26 26 @@ -37237,7 +37208,7 @@ POSSIBILITY OF SUCH DAMAGE. PIN27 - Status on whether PIN27 has met criteria set in PIN_CNF27.SENSE register. Write '1' to clear. + Status on whether PIN[27] has met criteria set in PIN_CNF[27].SENSE register. Write '1' to clear. 27 27 @@ -37255,7 +37226,7 @@ POSSIBILITY OF SUCH DAMAGE. PIN28 - Status on whether PIN28 has met criteria set in PIN_CNF28.SENSE register. Write '1' to clear. + Status on whether PIN[28] has met criteria set in PIN_CNF[28].SENSE register. Write '1' to clear. 28 28 @@ -37273,7 +37244,7 @@ POSSIBILITY OF SUCH DAMAGE. PIN29 - Status on whether PIN29 has met criteria set in PIN_CNF29.SENSE register. Write '1' to clear. + Status on whether PIN[29] has met criteria set in PIN_CNF[29].SENSE register. Write '1' to clear. 29 29 @@ -37291,7 +37262,7 @@ POSSIBILITY OF SUCH DAMAGE. PIN30 - Status on whether PIN30 has met criteria set in PIN_CNF30.SENSE register. Write '1' to clear. + Status on whether PIN[30] has met criteria set in PIN_CNF[30].SENSE register. Write '1' to clear. 30 30 @@ -37309,7 +37280,7 @@ POSSIBILITY OF SUCH DAMAGE. PIN31 - Status on whether PIN31 has met criteria set in PIN_CNF31.SENSE register. Write '1' to clear. + Status on whether PIN[31] has met criteria set in PIN_CNF[31].SENSE register. Write '1' to clear. 31 31 diff --git a/mdk/nrf5340_network_bitfields.h b/mdk/nrf5340_network_bitfields.h index 212bf59509..83cf42981b 100644 --- a/mdk/nrf5340_network_bitfields.h +++ b/mdk/nrf5340_network_bitfields.h @@ -1,6 +1,8 @@ /* -Copyright (c) 2010 - 2020, Nordic Semiconductor ASA All rights reserved. +Copyright (c) 2010 - 2021, Nordic Semiconductor ASA All rights reserved. + +SPDX-License-Identifier: BSD-3-Clause Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: @@ -213,7 +215,7 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: AAR_NIRK */ /* Description: Number of IRKs */ -/* Bits 4..0 : Number of Identity root keys available in the IRK data structure */ +/* Bits 4..0 : Number of Identity Root Keys available in the IRK data structure */ #define AAR_NIRK_NIRK_Pos (0UL) /*!< Position of NIRK field. */ #define AAR_NIRK_NIRK_Msk (0x1FUL << AAR_NIRK_NIRK_Pos) /*!< Bit mask of NIRK field. */ @@ -243,14 +245,14 @@ POSSIBILITY OF SUCH DAMAGE. /* Description: Access control lists */ /* Register: ACL_ACL_ADDR */ -/* Description: Description cluster: Configure the word-aligned start address of region n to protect */ +/* Description: Description cluster: Start address of region to protect. The start address must be word-aligned. */ -/* Bits 31..0 : Valid word-aligned start address of region n to protect. Address must point to a flash page boundary. */ +/* Bits 31..0 : Start address of flash region n. The start address must point to a flash page boundary. */ #define ACL_ACL_ADDR_ADDR_Pos (0UL) /*!< Position of ADDR field. */ #define ACL_ACL_ADDR_ADDR_Msk (0xFFFFFFFFUL << ACL_ACL_ADDR_ADDR_Pos) /*!< Bit mask of ADDR field. */ /* Register: ACL_ACL_SIZE */ -/* Description: Description cluster: Size of region to protect counting from address ACL[n].ADDR. Write '0' as no effect. */ +/* Description: Description cluster: Size of region to protect counting from address ACL[n].ADDR. Writing a '0' has no effect. */ /* Bits 31..0 : Size of flash region n in bytes. Must be a multiple of the flash page size. */ #define ACL_ACL_SIZE_SIZE_Pos (0UL) /*!< Position of SIZE field. */ @@ -259,17 +261,17 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: ACL_ACL_PERM */ /* Description: Description cluster: Access permissions for region n as defined by start address ACL[n].ADDR and size ACL[n].SIZE */ -/* Bit 2 : Configure read permissions for region n. Write '0' has no effect. */ +/* Bit 2 : Configure read permissions for region n. Writing a '0' has no effect. */ #define ACL_ACL_PERM_READ_Pos (2UL) /*!< Position of READ field. */ #define ACL_ACL_PERM_READ_Msk (0x1UL << ACL_ACL_PERM_READ_Pos) /*!< Bit mask of READ field. */ -#define ACL_ACL_PERM_READ_Enable (0UL) /*!< Allow read instructions to region n */ -#define ACL_ACL_PERM_READ_Disable (1UL) /*!< Block read instructions to region n */ +#define ACL_ACL_PERM_READ_Enable (0UL) /*!< Allow read instructions to region n. */ +#define ACL_ACL_PERM_READ_Disable (1UL) /*!< Block read instructions to region n. */ -/* Bit 1 : Configure write and erase permissions for region n. Write '0' has no effect. */ +/* Bit 1 : Configure write and erase permissions for region n. Writing a '0' has no effect. */ #define ACL_ACL_PERM_WRITE_Pos (1UL) /*!< Position of WRITE field. */ #define ACL_ACL_PERM_WRITE_Msk (0x1UL << ACL_ACL_PERM_WRITE_Pos) /*!< Bit mask of WRITE field. */ -#define ACL_ACL_PERM_WRITE_Enable (0UL) /*!< Allow write and erase instructions to region n */ -#define ACL_ACL_PERM_WRITE_Disable (1UL) /*!< Block write and erase instructions to region n */ +#define ACL_ACL_PERM_WRITE_Enable (0UL) /*!< Allow write and erase instructions to region n. */ +#define ACL_ACL_PERM_WRITE_Disable (1UL) /*!< Block write and erase instructions to region n. */ /* Peripheral: MUTEX */ @@ -527,8 +529,8 @@ POSSIBILITY OF SUCH DAMAGE. #define CCM_MODE_DATARATE_Msk (0x3UL << CCM_MODE_DATARATE_Pos) /*!< Bit mask of DATARATE field. */ #define CCM_MODE_DATARATE_1Mbit (0UL) /*!< 1 Mbps */ #define CCM_MODE_DATARATE_2Mbit (1UL) /*!< 2 Mbps */ -#define CCM_MODE_DATARATE_125Kbps (2UL) /*!< 125 Kbps */ -#define CCM_MODE_DATARATE_500Kbps (3UL) /*!< 500 Kbps */ +#define CCM_MODE_DATARATE_125Kbps (2UL) /*!< 125 kbps */ +#define CCM_MODE_DATARATE_500Kbps (3UL) /*!< 500 kbps */ /* Bit 0 : The mode of operation to be used. Settings in this register apply whenever either the KSGEN task or the CRYPT task is triggered. */ #define CCM_MODE_MODE_Pos (0UL) /*!< Position of MODE field. */ @@ -580,8 +582,8 @@ POSSIBILITY OF SUCH DAMAGE. #define CCM_RATEOVERRIDE_RATEOVERRIDE_Msk (0x3UL << CCM_RATEOVERRIDE_RATEOVERRIDE_Pos) /*!< Bit mask of RATEOVERRIDE field. */ #define CCM_RATEOVERRIDE_RATEOVERRIDE_1Mbit (0UL) /*!< 1 Mbps */ #define CCM_RATEOVERRIDE_RATEOVERRIDE_2Mbit (1UL) /*!< 2 Mbps */ -#define CCM_RATEOVERRIDE_RATEOVERRIDE_125Kbps (2UL) /*!< 125 Kbps */ -#define CCM_RATEOVERRIDE_RATEOVERRIDE_500Kbps (3UL) /*!< 500 Kbps */ +#define CCM_RATEOVERRIDE_RATEOVERRIDE_125Kbps (2UL) /*!< 125 kbps */ +#define CCM_RATEOVERRIDE_RATEOVERRIDE_500Kbps (3UL) /*!< 500 kbps */ /* Register: CCM_HEADERMASK */ /* Description: Header (S0) mask. */ @@ -912,7 +914,6 @@ POSSIBILITY OF SUCH DAMAGE. /* Bits 1..0 : Active clock source */ #define CLOCK_LFCLKSTAT_SRC_Pos (0UL) /*!< Position of SRC field. */ #define CLOCK_LFCLKSTAT_SRC_Msk (0x3UL << CLOCK_LFCLKSTAT_SRC_Pos) /*!< Bit mask of SRC field. */ -#define CLOCK_LFCLKSTAT_SRC_LFULP (0UL) /*!< 32.768 kHz ultra-low power RC oscillator */ #define CLOCK_LFCLKSTAT_SRC_LFRC (1UL) /*!< 32.768 kHz RC oscillator */ #define CLOCK_LFCLKSTAT_SRC_LFXO (2UL) /*!< 32.768 kHz crystal oscillator */ #define CLOCK_LFCLKSTAT_SRC_LFSYNT (3UL) /*!< 32.768 kHz synthesized from HFCLK */ @@ -923,7 +924,6 @@ POSSIBILITY OF SUCH DAMAGE. /* Bits 1..0 : Clock source */ #define CLOCK_LFCLKSRCCOPY_SRC_Pos (0UL) /*!< Position of SRC field. */ #define CLOCK_LFCLKSRCCOPY_SRC_Msk (0x3UL << CLOCK_LFCLKSRCCOPY_SRC_Pos) /*!< Bit mask of SRC field. */ -#define CLOCK_LFCLKSRCCOPY_SRC_LFULP (0UL) /*!< 32.768 kHz ultra-low power RC oscillator */ #define CLOCK_LFCLKSRCCOPY_SRC_LFRC (1UL) /*!< 32.768 kHz RC oscillator */ #define CLOCK_LFCLKSRCCOPY_SRC_LFXO (2UL) /*!< 32.768 kHz crystal oscillator */ #define CLOCK_LFCLKSRCCOPY_SRC_LFSYNT (3UL) /*!< 32.768 kHz synthesized from HFCLK */ @@ -943,7 +943,6 @@ POSSIBILITY OF SUCH DAMAGE. /* Bits 1..0 : Select which LFCLK source is started by the LFCLKSTART task */ #define CLOCK_LFCLKSRC_SRC_Pos (0UL) /*!< Position of SRC field. */ #define CLOCK_LFCLKSRC_SRC_Msk (0x3UL << CLOCK_LFCLKSRC_SRC_Pos) /*!< Bit mask of SRC field. */ -#define CLOCK_LFCLKSRC_SRC_LFULP (0UL) /*!< 32.768 kHz ultra-low power RC oscillator */ #define CLOCK_LFCLKSRC_SRC_LFRC (1UL) /*!< 32.768 kHz RC oscillator */ #define CLOCK_LFCLKSRC_SRC_LFXO (2UL) /*!< 32.768 kHz crystal oscillator */ #define CLOCK_LFCLKSRC_SRC_LFSYNT (3UL) /*!< 32.768 kHz synthesized from HFCLK */ @@ -1344,17 +1343,17 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: CTI_DEVTYPE */ /* Description: Device Type Identifier register */ -/* Bits 7..4 : Sub-classification of the type of the debug component as specified in the ARM Architecture Specification within +/* Bits 7..4 : Sub-classification of the type of the debug component as specified in the Arm Architecture Specification within the major classification as specified in the MAJOR field. */ #define CTI_DEVTYPE_SUB_Pos (4UL) /*!< Position of SUB field. */ #define CTI_DEVTYPE_SUB_Msk (0xFUL << CTI_DEVTYPE_SUB_Pos) /*!< Bit mask of SUB field. */ -#define CTI_DEVTYPE_SUB_Crosstrigger (0b0001UL) /*!< Indicates that this component is a sub-triggering component. */ +#define CTI_DEVTYPE_SUB_Crosstrigger (1UL) /*!< Indicates that this component is a sub-triggering component. */ -/* Bits 3..0 : Major classification of the type of the debug component as specified in the ARM Architecture Specification for this +/* Bits 3..0 : Major classification of the type of the debug component as specified in the Arm Architecture Specification for this debug and trace component. */ #define CTI_DEVTYPE_MAJOR_Pos (0UL) /*!< Position of MAJOR field. */ #define CTI_DEVTYPE_MAJOR_Msk (0xFUL << CTI_DEVTYPE_MAJOR_Pos) /*!< Bit mask of MAJOR field. */ -#define CTI_DEVTYPE_MAJOR_Controller (0b0100UL) /*!< Indicates that this component allows a debugger to control other components in a CoreSight SoC-400 system. */ +#define CTI_DEVTYPE_MAJOR_Controller (4UL) /*!< Indicates that this component allows a debugger to control other components in an Arm CoreSight SoC-400 system. */ /* Register: CTI_PIDR4 */ /* Description: Peripheral ID4 Register */ @@ -1366,7 +1365,7 @@ POSSIBILITY OF SUCH DAMAGE. /* Bits 3..0 : Together, PIDR1.DES_0, PIDR2.DES_1, and PIDR4.DES_2 identify the designer of the component. */ #define CTI_PIDR4_DES_2_Pos (0UL) /*!< Position of DES_2 field. */ #define CTI_PIDR4_DES_2_Msk (0xFUL << CTI_PIDR4_DES_2_Pos) /*!< Bit mask of DES_2 field. */ -#define CTI_PIDR4_DES_2_Code (0b0100UL) /*!< JEDEC continuation code */ +#define CTI_PIDR4_DES_2_Code (4UL) /*!< JEDEC continuation code. */ /* Register: CTI_PIDR0 */ /* Description: Peripheral ID0 Register */ @@ -1382,12 +1381,12 @@ POSSIBILITY OF SUCH DAMAGE. /* Bits 7..4 : Together, PIDR1.DES_0, PIDR2.DES_1, and PIDR4.DES_2 identify the designer of the component. */ #define CTI_PIDR1_DES_0_Pos (4UL) /*!< Position of DES_0 field. */ #define CTI_PIDR1_DES_0_Msk (0xFUL << CTI_PIDR1_DES_0_Pos) /*!< Bit mask of DES_0 field. */ -#define CTI_PIDR1_DES_0_Arm (0b1011UL) /*!< ARM. Bits[3:0] of the JEDEC JEP106 Identity Code */ +#define CTI_PIDR1_DES_0_Arm (11UL) /*!< Arm. Bits[3:0] of the JEDEC JEP106 Identity Code */ /* Bits 3..0 : Bits[11:8] of the 12-bit part number of the component. The designer of the component assigns this part number. */ #define CTI_PIDR1_PART_1_Pos (0UL) /*!< Position of PART_1 field. */ #define CTI_PIDR1_PART_1_Msk (0xFUL << CTI_PIDR1_PART_1_Pos) /*!< Bit mask of PART_1 field. */ -#define CTI_PIDR1_PART_1_PartnumberH (0b1101UL) /*!< Indicates bits[11:8] of the part number of the component. */ +#define CTI_PIDR1_PART_1_PartnumberH (13UL) /*!< Indicates bits[11:8] of the part number of the component. */ /* Register: CTI_PIDR2 */ /* Description: Peripheral ID2 Register */ @@ -1395,7 +1394,7 @@ POSSIBILITY OF SUCH DAMAGE. /* Bits 7..4 : Peripheral revision */ #define CTI_PIDR2_REVISION_Pos (4UL) /*!< Position of REVISION field. */ #define CTI_PIDR2_REVISION_Msk (0xFUL << CTI_PIDR2_REVISION_Pos) /*!< Bit mask of REVISION field. */ -#define CTI_PIDR2_REVISION_Rev0p0 (0b0000UL) /*!< This device is at r0p0 */ +#define CTI_PIDR2_REVISION_Rev0p0 (0UL) /*!< This device is at r0p0 */ /* Bit 3 : Always 1. Indicates that the JEDEC-assigned designer ID is used. */ #define CTI_PIDR2_JEDEC_Pos (3UL) /*!< Position of JEDEC field. */ @@ -1404,23 +1403,23 @@ POSSIBILITY OF SUCH DAMAGE. /* Bits 2..0 : Together, PIDR1.DES_0, PIDR2.DES_1, and PIDR4.DES_2 identify the designer of the component. */ #define CTI_PIDR2_DES_1_Pos (0UL) /*!< Position of DES_1 field. */ #define CTI_PIDR2_DES_1_Msk (0x7UL << CTI_PIDR2_DES_1_Pos) /*!< Bit mask of DES_1 field. */ -#define CTI_PIDR2_DES_1_Arm (0b011UL) /*!< ARM. Bits[6:4] of the JEDEC JEP106 Identity Code */ +#define CTI_PIDR2_DES_1_Arm (3UL) /*!< Arm. Bits[6:4] of the JEDEC JEP106 Identity Code */ /* Register: CTI_PIDR3 */ /* Description: Peripheral ID3 Register */ /* Bits 7..4 : Indicates minor errata fixes specific to the revision of the component being used, for example metal fixes after - implementation. In most cases, this field is 0b0000. ARM recommends that the component designers ensure that a + implementation. In most cases, this field is 0b0000. Arm recommends that the component designers ensure that a metal fix can change this field if required, for example, by driving it from registers that reset to 0b0000. */ #define CTI_PIDR3_REVAND_Pos (4UL) /*!< Position of REVAND field. */ #define CTI_PIDR3_REVAND_Msk (0xFUL << CTI_PIDR3_REVAND_Pos) /*!< Bit mask of REVAND field. */ -#define CTI_PIDR3_REVAND_NoErrata (0b000UL) /*!< Indicates that there are no errata fixes to this component. */ +#define CTI_PIDR3_REVAND_NoErrata (0UL) /*!< Indicates that there are no errata fixes to this component. */ /* Bits 3..0 : Customer Modified. Indicates whether the customer has modified the behavior of the component. In most cases, this field is 0b0000. Customers change this value when they make authorized modifications to this component. */ #define CTI_PIDR3_CMOD_Pos (0UL) /*!< Position of CMOD field. */ #define CTI_PIDR3_CMOD_Msk (0xFUL << CTI_PIDR3_CMOD_Pos) /*!< Bit mask of CMOD field. */ -#define CTI_PIDR3_CMOD_Unmodified (0b000UL) /*!< Indicates that the customer has not modified this component. */ +#define CTI_PIDR3_CMOD_Unmodified (0UL) /*!< Indicates that the customer has not modified this component. */ /* Register: CTI_CIDR0 */ /* Description: Component ID0 Register */ @@ -1437,12 +1436,12 @@ POSSIBILITY OF SUCH DAMAGE. Contains bits[15:12] of the component identification code */ #define CTI_CIDR1_CLASS_Pos (4UL) /*!< Position of CLASS field. */ #define CTI_CIDR1_CLASS_Msk (0xFUL << CTI_CIDR1_CLASS_Pos) /*!< Bit mask of CLASS field. */ -#define CTI_CIDR1_CLASS_Coresight (0b1001UL) /*!< Indicates that the component is a CoreSight component. */ +#define CTI_CIDR1_CLASS_Coresight (9UL) /*!< Indicates that the component is a CoreSight component. */ /* Bits 3..0 : Preamble[1]. Contains bits[11:8] of the component identification code. */ #define CTI_CIDR1_PRMBL_1_Pos (0UL) /*!< Position of PRMBL_1 field. */ #define CTI_CIDR1_PRMBL_1_Msk (0xFUL << CTI_CIDR1_PRMBL_1_Pos) /*!< Bit mask of PRMBL_1 field. */ -#define CTI_CIDR1_PRMBL_1_Value (0b0000UL) /*!< Bits[11:8] of the identification code. */ +#define CTI_CIDR1_PRMBL_1_Value (0UL) /*!< Bits[11:8] of the identification code. */ /* Register: CTI_CIDR2 */ /* Description: Component ID2 Register */ @@ -1524,12 +1523,14 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: CTRLAPPERI_APPROTECT_DISABLE */ /* Description: This register disables the APPROTECT register and enables debug access to non-secure mode. */ -/* Bits 31..0 : Disable APPROTECT and enable debug access to non-secure mode until the next pin reset if the KEY fields match. The current APPROTECT value as configured from UICR is bypassed if the value of the KEY fields are non-zero and the KEY fields match on both the CPU and debugger sides. */ +/* Bits 31..0 : If the value of the KEY field is non-zero, and the KEY fields match on both the + CPU and debugger sides, disable APPROTECT and enable debug access to non-secure mode until + the next pin reset, brown-out reset, power-on reset, or watchog timer reset. After reset the debugger side register has a fixed KEY value. To enable debug access, both CTRL-AP and UICR.APPROTECT protection needs to be disabled. */ #define CTRLAPPERI_APPROTECT_DISABLE_KEY_Pos (0UL) /*!< Position of KEY field. */ #define CTRLAPPERI_APPROTECT_DISABLE_KEY_Msk (0xFFFFFFFFUL << CTRLAPPERI_APPROTECT_DISABLE_KEY_Pos) /*!< Bit mask of KEY field. */ /* Register: CTRLAPPERI_STATUS */ -/* Description: Status bits for CTRL-AP peripheral */ +/* Description: Status bits for CTRL-AP peripheral. */ /* Bit 2 : Status bit for device debug interface mode */ #define CTRLAPPERI_STATUS_DBGIFACEMODE_Pos (2UL) /*!< Position of DBGIFACEMODE field. */ @@ -1537,11 +1538,11 @@ POSSIBILITY OF SUCH DAMAGE. #define CTRLAPPERI_STATUS_DBGIFACEMODE_Disabled (0UL) /*!< No debugger attached */ #define CTRLAPPERI_STATUS_DBGIFACEMODE_Enabled (1UL) /*!< Debugger is attached and device is in debug interface mode */ -/* Bit 0 : Status bit for access port protection in non-secure mode */ -#define CTRLAPPERI_STATUS_APPROTECT_Pos (0UL) /*!< Position of APPROTECT field. */ -#define CTRLAPPERI_STATUS_APPROTECT_Msk (0x1UL << CTRLAPPERI_STATUS_APPROTECT_Pos) /*!< Bit mask of APPROTECT field. */ -#define CTRLAPPERI_STATUS_APPROTECT_Disabled (0UL) /*!< Non-secure mode access port protection is currently disabled */ -#define CTRLAPPERI_STATUS_APPROTECT_Enabled (1UL) /*!< Non-secure mode access port protection is currently enabled */ +/* Bit 0 : Status bit for UICR part of access port protection at last reset. */ +#define CTRLAPPERI_STATUS_UICRAPPROTECT_Pos (0UL) /*!< Position of UICRAPPROTECT field. */ +#define CTRLAPPERI_STATUS_UICRAPPROTECT_Msk (0x1UL << CTRLAPPERI_STATUS_UICRAPPROTECT_Pos) /*!< Bit mask of UICRAPPROTECT field. */ +#define CTRLAPPERI_STATUS_UICRAPPROTECT_Enabled (0UL) /*!< APPROTECT was enabled in UICR */ +#define CTRLAPPERI_STATUS_UICRAPPROTECT_Disabled (1UL) /*!< APPROTECT wasdisabled in UICR */ /* Peripheral: DCNF */ @@ -2577,7 +2578,7 @@ POSSIBILITY OF SUCH DAMAGE. /* Bits 31..0 : Package option */ #define FICR_INFO_PACKAGE_PACKAGE_Pos (0UL) /*!< Position of PACKAGE field. */ #define FICR_INFO_PACKAGE_PACKAGE_Msk (0xFFFFFFFFUL << FICR_INFO_PACKAGE_PACKAGE_Pos) /*!< Bit mask of PACKAGE field. */ -#define FICR_INFO_PACKAGE_PACKAGE_QF (0x2000UL) /*!< QFxx - 94 pin QFN */ +#define FICR_INFO_PACKAGE_PACKAGE_QK (0x2000UL) /*!< QKxx - 94-pin aQFN */ #define FICR_INFO_PACKAGE_PACKAGE_Unspecified (0xFFFFFFFFUL) /*!< Unspecified */ /* Register: FICR_INFO_RAM */ @@ -3650,7 +3651,7 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 0 : NVMC is ready or busy */ #define NVMC_READY_READY_Pos (0UL) /*!< Position of READY field. */ #define NVMC_READY_READY_Msk (0x1UL << NVMC_READY_READY_Pos) /*!< Bit mask of READY field. */ -#define NVMC_READY_READY_Busy (0UL) /*!< NVMC is busy (on-going write or erase operation) */ +#define NVMC_READY_READY_Busy (0UL) /*!< NVMC is busy (ongoing write or erase operation) */ #define NVMC_READY_READY_Ready (1UL) /*!< NVMC is ready */ /* Register: NVMC_READYNEXT */ @@ -3676,7 +3677,7 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: NVMC_ERASEALL */ /* Description: Register for erasing all non-volatile user memory */ -/* Bit 0 : Erase all non-volatile memory including UICR registers. Note that erasing must be enabled by setting CONFIG.WEN = Een before the non-volatile memory can be erased. */ +/* Bit 0 : Erase all non-volatile memory including UICR registers. Before the non-volatile memory can be erased, erasing must be enabled by setting CONFIG.WEN=Een. */ #define NVMC_ERASEALL_ERASEALL_Pos (0UL) /*!< Position of ERASEALL field. */ #define NVMC_ERASEALL_ERASEALL_Msk (0x1UL << NVMC_ERASEALL_ERASEALL_Pos) /*!< Bit mask of ERASEALL field. */ #define NVMC_ERASEALL_ERASEALL_NoOperation (0UL) /*!< No operation */ @@ -5218,193 +5219,193 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: GPIO_LATCH */ /* Description: Latch register indicating what GPIO pins that have met the criteria set in the PIN_CNF[n].SENSE registers */ -/* Bit 31 : Status on whether PIN31 has met criteria set in PIN_CNF31.SENSE register. Write '1' to clear. */ +/* Bit 31 : Status on whether PIN[31] has met criteria set in PIN_CNF[31].SENSE register. Write '1' to clear. */ #define GPIO_LATCH_PIN31_Pos (31UL) /*!< Position of PIN31 field. */ #define GPIO_LATCH_PIN31_Msk (0x1UL << GPIO_LATCH_PIN31_Pos) /*!< Bit mask of PIN31 field. */ #define GPIO_LATCH_PIN31_NotLatched (0UL) /*!< Criteria has not been met */ #define GPIO_LATCH_PIN31_Latched (1UL) /*!< Criteria has been met */ -/* Bit 30 : Status on whether PIN30 has met criteria set in PIN_CNF30.SENSE register. Write '1' to clear. */ +/* Bit 30 : Status on whether PIN[30] has met criteria set in PIN_CNF[30].SENSE register. Write '1' to clear. */ #define GPIO_LATCH_PIN30_Pos (30UL) /*!< Position of PIN30 field. */ #define GPIO_LATCH_PIN30_Msk (0x1UL << GPIO_LATCH_PIN30_Pos) /*!< Bit mask of PIN30 field. */ #define GPIO_LATCH_PIN30_NotLatched (0UL) /*!< Criteria has not been met */ #define GPIO_LATCH_PIN30_Latched (1UL) /*!< Criteria has been met */ -/* Bit 29 : Status on whether PIN29 has met criteria set in PIN_CNF29.SENSE register. Write '1' to clear. */ +/* Bit 29 : Status on whether PIN[29] has met criteria set in PIN_CNF[29].SENSE register. Write '1' to clear. */ #define GPIO_LATCH_PIN29_Pos (29UL) /*!< Position of PIN29 field. */ #define GPIO_LATCH_PIN29_Msk (0x1UL << GPIO_LATCH_PIN29_Pos) /*!< Bit mask of PIN29 field. */ #define GPIO_LATCH_PIN29_NotLatched (0UL) /*!< Criteria has not been met */ #define GPIO_LATCH_PIN29_Latched (1UL) /*!< Criteria has been met */ -/* Bit 28 : Status on whether PIN28 has met criteria set in PIN_CNF28.SENSE register. Write '1' to clear. */ +/* Bit 28 : Status on whether PIN[28] has met criteria set in PIN_CNF[28].SENSE register. Write '1' to clear. */ #define GPIO_LATCH_PIN28_Pos (28UL) /*!< Position of PIN28 field. */ #define GPIO_LATCH_PIN28_Msk (0x1UL << GPIO_LATCH_PIN28_Pos) /*!< Bit mask of PIN28 field. */ #define GPIO_LATCH_PIN28_NotLatched (0UL) /*!< Criteria has not been met */ #define GPIO_LATCH_PIN28_Latched (1UL) /*!< Criteria has been met */ -/* Bit 27 : Status on whether PIN27 has met criteria set in PIN_CNF27.SENSE register. Write '1' to clear. */ +/* Bit 27 : Status on whether PIN[27] has met criteria set in PIN_CNF[27].SENSE register. Write '1' to clear. */ #define GPIO_LATCH_PIN27_Pos (27UL) /*!< Position of PIN27 field. */ #define GPIO_LATCH_PIN27_Msk (0x1UL << GPIO_LATCH_PIN27_Pos) /*!< Bit mask of PIN27 field. */ #define GPIO_LATCH_PIN27_NotLatched (0UL) /*!< Criteria has not been met */ #define GPIO_LATCH_PIN27_Latched (1UL) /*!< Criteria has been met */ -/* Bit 26 : Status on whether PIN26 has met criteria set in PIN_CNF26.SENSE register. Write '1' to clear. */ +/* Bit 26 : Status on whether PIN[26] has met criteria set in PIN_CNF[26].SENSE register. Write '1' to clear. */ #define GPIO_LATCH_PIN26_Pos (26UL) /*!< Position of PIN26 field. */ #define GPIO_LATCH_PIN26_Msk (0x1UL << GPIO_LATCH_PIN26_Pos) /*!< Bit mask of PIN26 field. */ #define GPIO_LATCH_PIN26_NotLatched (0UL) /*!< Criteria has not been met */ #define GPIO_LATCH_PIN26_Latched (1UL) /*!< Criteria has been met */ -/* Bit 25 : Status on whether PIN25 has met criteria set in PIN_CNF25.SENSE register. Write '1' to clear. */ +/* Bit 25 : Status on whether PIN[25] has met criteria set in PIN_CNF[25].SENSE register. Write '1' to clear. */ #define GPIO_LATCH_PIN25_Pos (25UL) /*!< Position of PIN25 field. */ #define GPIO_LATCH_PIN25_Msk (0x1UL << GPIO_LATCH_PIN25_Pos) /*!< Bit mask of PIN25 field. */ #define GPIO_LATCH_PIN25_NotLatched (0UL) /*!< Criteria has not been met */ #define GPIO_LATCH_PIN25_Latched (1UL) /*!< Criteria has been met */ -/* Bit 24 : Status on whether PIN24 has met criteria set in PIN_CNF24.SENSE register. Write '1' to clear. */ +/* Bit 24 : Status on whether PIN[24] has met criteria set in PIN_CNF[24].SENSE register. Write '1' to clear. */ #define GPIO_LATCH_PIN24_Pos (24UL) /*!< Position of PIN24 field. */ #define GPIO_LATCH_PIN24_Msk (0x1UL << GPIO_LATCH_PIN24_Pos) /*!< Bit mask of PIN24 field. */ #define GPIO_LATCH_PIN24_NotLatched (0UL) /*!< Criteria has not been met */ #define GPIO_LATCH_PIN24_Latched (1UL) /*!< Criteria has been met */ -/* Bit 23 : Status on whether PIN23 has met criteria set in PIN_CNF23.SENSE register. Write '1' to clear. */ +/* Bit 23 : Status on whether PIN[23] has met criteria set in PIN_CNF[23].SENSE register. Write '1' to clear. */ #define GPIO_LATCH_PIN23_Pos (23UL) /*!< Position of PIN23 field. */ #define GPIO_LATCH_PIN23_Msk (0x1UL << GPIO_LATCH_PIN23_Pos) /*!< Bit mask of PIN23 field. */ #define GPIO_LATCH_PIN23_NotLatched (0UL) /*!< Criteria has not been met */ #define GPIO_LATCH_PIN23_Latched (1UL) /*!< Criteria has been met */ -/* Bit 22 : Status on whether PIN22 has met criteria set in PIN_CNF22.SENSE register. Write '1' to clear. */ +/* Bit 22 : Status on whether PIN[22] has met criteria set in PIN_CNF[22].SENSE register. Write '1' to clear. */ #define GPIO_LATCH_PIN22_Pos (22UL) /*!< Position of PIN22 field. */ #define GPIO_LATCH_PIN22_Msk (0x1UL << GPIO_LATCH_PIN22_Pos) /*!< Bit mask of PIN22 field. */ #define GPIO_LATCH_PIN22_NotLatched (0UL) /*!< Criteria has not been met */ #define GPIO_LATCH_PIN22_Latched (1UL) /*!< Criteria has been met */ -/* Bit 21 : Status on whether PIN21 has met criteria set in PIN_CNF21.SENSE register. Write '1' to clear. */ +/* Bit 21 : Status on whether PIN[21] has met criteria set in PIN_CNF[21].SENSE register. Write '1' to clear. */ #define GPIO_LATCH_PIN21_Pos (21UL) /*!< Position of PIN21 field. */ #define GPIO_LATCH_PIN21_Msk (0x1UL << GPIO_LATCH_PIN21_Pos) /*!< Bit mask of PIN21 field. */ #define GPIO_LATCH_PIN21_NotLatched (0UL) /*!< Criteria has not been met */ #define GPIO_LATCH_PIN21_Latched (1UL) /*!< Criteria has been met */ -/* Bit 20 : Status on whether PIN20 has met criteria set in PIN_CNF20.SENSE register. Write '1' to clear. */ +/* Bit 20 : Status on whether PIN[20] has met criteria set in PIN_CNF[20].SENSE register. Write '1' to clear. */ #define GPIO_LATCH_PIN20_Pos (20UL) /*!< Position of PIN20 field. */ #define GPIO_LATCH_PIN20_Msk (0x1UL << GPIO_LATCH_PIN20_Pos) /*!< Bit mask of PIN20 field. */ #define GPIO_LATCH_PIN20_NotLatched (0UL) /*!< Criteria has not been met */ #define GPIO_LATCH_PIN20_Latched (1UL) /*!< Criteria has been met */ -/* Bit 19 : Status on whether PIN19 has met criteria set in PIN_CNF19.SENSE register. Write '1' to clear. */ +/* Bit 19 : Status on whether PIN[19] has met criteria set in PIN_CNF[19].SENSE register. Write '1' to clear. */ #define GPIO_LATCH_PIN19_Pos (19UL) /*!< Position of PIN19 field. */ #define GPIO_LATCH_PIN19_Msk (0x1UL << GPIO_LATCH_PIN19_Pos) /*!< Bit mask of PIN19 field. */ #define GPIO_LATCH_PIN19_NotLatched (0UL) /*!< Criteria has not been met */ #define GPIO_LATCH_PIN19_Latched (1UL) /*!< Criteria has been met */ -/* Bit 18 : Status on whether PIN18 has met criteria set in PIN_CNF18.SENSE register. Write '1' to clear. */ +/* Bit 18 : Status on whether PIN[18] has met criteria set in PIN_CNF[18].SENSE register. Write '1' to clear. */ #define GPIO_LATCH_PIN18_Pos (18UL) /*!< Position of PIN18 field. */ #define GPIO_LATCH_PIN18_Msk (0x1UL << GPIO_LATCH_PIN18_Pos) /*!< Bit mask of PIN18 field. */ #define GPIO_LATCH_PIN18_NotLatched (0UL) /*!< Criteria has not been met */ #define GPIO_LATCH_PIN18_Latched (1UL) /*!< Criteria has been met */ -/* Bit 17 : Status on whether PIN17 has met criteria set in PIN_CNF17.SENSE register. Write '1' to clear. */ +/* Bit 17 : Status on whether PIN[17] has met criteria set in PIN_CNF[17].SENSE register. Write '1' to clear. */ #define GPIO_LATCH_PIN17_Pos (17UL) /*!< Position of PIN17 field. */ #define GPIO_LATCH_PIN17_Msk (0x1UL << GPIO_LATCH_PIN17_Pos) /*!< Bit mask of PIN17 field. */ #define GPIO_LATCH_PIN17_NotLatched (0UL) /*!< Criteria has not been met */ #define GPIO_LATCH_PIN17_Latched (1UL) /*!< Criteria has been met */ -/* Bit 16 : Status on whether PIN16 has met criteria set in PIN_CNF16.SENSE register. Write '1' to clear. */ +/* Bit 16 : Status on whether PIN[16] has met criteria set in PIN_CNF[16].SENSE register. Write '1' to clear. */ #define GPIO_LATCH_PIN16_Pos (16UL) /*!< Position of PIN16 field. */ #define GPIO_LATCH_PIN16_Msk (0x1UL << GPIO_LATCH_PIN16_Pos) /*!< Bit mask of PIN16 field. */ #define GPIO_LATCH_PIN16_NotLatched (0UL) /*!< Criteria has not been met */ #define GPIO_LATCH_PIN16_Latched (1UL) /*!< Criteria has been met */ -/* Bit 15 : Status on whether PIN15 has met criteria set in PIN_CNF15.SENSE register. Write '1' to clear. */ +/* Bit 15 : Status on whether PIN[15] has met criteria set in PIN_CNF[15].SENSE register. Write '1' to clear. */ #define GPIO_LATCH_PIN15_Pos (15UL) /*!< Position of PIN15 field. */ #define GPIO_LATCH_PIN15_Msk (0x1UL << GPIO_LATCH_PIN15_Pos) /*!< Bit mask of PIN15 field. */ #define GPIO_LATCH_PIN15_NotLatched (0UL) /*!< Criteria has not been met */ #define GPIO_LATCH_PIN15_Latched (1UL) /*!< Criteria has been met */ -/* Bit 14 : Status on whether PIN14 has met criteria set in PIN_CNF14.SENSE register. Write '1' to clear. */ +/* Bit 14 : Status on whether PIN[14] has met criteria set in PIN_CNF[14].SENSE register. Write '1' to clear. */ #define GPIO_LATCH_PIN14_Pos (14UL) /*!< Position of PIN14 field. */ #define GPIO_LATCH_PIN14_Msk (0x1UL << GPIO_LATCH_PIN14_Pos) /*!< Bit mask of PIN14 field. */ #define GPIO_LATCH_PIN14_NotLatched (0UL) /*!< Criteria has not been met */ #define GPIO_LATCH_PIN14_Latched (1UL) /*!< Criteria has been met */ -/* Bit 13 : Status on whether PIN13 has met criteria set in PIN_CNF13.SENSE register. Write '1' to clear. */ +/* Bit 13 : Status on whether PIN[13] has met criteria set in PIN_CNF[13].SENSE register. Write '1' to clear. */ #define GPIO_LATCH_PIN13_Pos (13UL) /*!< Position of PIN13 field. */ #define GPIO_LATCH_PIN13_Msk (0x1UL << GPIO_LATCH_PIN13_Pos) /*!< Bit mask of PIN13 field. */ #define GPIO_LATCH_PIN13_NotLatched (0UL) /*!< Criteria has not been met */ #define GPIO_LATCH_PIN13_Latched (1UL) /*!< Criteria has been met */ -/* Bit 12 : Status on whether PIN12 has met criteria set in PIN_CNF12.SENSE register. Write '1' to clear. */ +/* Bit 12 : Status on whether PIN[12] has met criteria set in PIN_CNF[12].SENSE register. Write '1' to clear. */ #define GPIO_LATCH_PIN12_Pos (12UL) /*!< Position of PIN12 field. */ #define GPIO_LATCH_PIN12_Msk (0x1UL << GPIO_LATCH_PIN12_Pos) /*!< Bit mask of PIN12 field. */ #define GPIO_LATCH_PIN12_NotLatched (0UL) /*!< Criteria has not been met */ #define GPIO_LATCH_PIN12_Latched (1UL) /*!< Criteria has been met */ -/* Bit 11 : Status on whether PIN11 has met criteria set in PIN_CNF11.SENSE register. Write '1' to clear. */ +/* Bit 11 : Status on whether PIN[11] has met criteria set in PIN_CNF[11].SENSE register. Write '1' to clear. */ #define GPIO_LATCH_PIN11_Pos (11UL) /*!< Position of PIN11 field. */ #define GPIO_LATCH_PIN11_Msk (0x1UL << GPIO_LATCH_PIN11_Pos) /*!< Bit mask of PIN11 field. */ #define GPIO_LATCH_PIN11_NotLatched (0UL) /*!< Criteria has not been met */ #define GPIO_LATCH_PIN11_Latched (1UL) /*!< Criteria has been met */ -/* Bit 10 : Status on whether PIN10 has met criteria set in PIN_CNF10.SENSE register. Write '1' to clear. */ +/* Bit 10 : Status on whether PIN[10] has met criteria set in PIN_CNF[10].SENSE register. Write '1' to clear. */ #define GPIO_LATCH_PIN10_Pos (10UL) /*!< Position of PIN10 field. */ #define GPIO_LATCH_PIN10_Msk (0x1UL << GPIO_LATCH_PIN10_Pos) /*!< Bit mask of PIN10 field. */ #define GPIO_LATCH_PIN10_NotLatched (0UL) /*!< Criteria has not been met */ #define GPIO_LATCH_PIN10_Latched (1UL) /*!< Criteria has been met */ -/* Bit 9 : Status on whether PIN9 has met criteria set in PIN_CNF9.SENSE register. Write '1' to clear. */ +/* Bit 9 : Status on whether PIN[9] has met criteria set in PIN_CNF[9].SENSE register. Write '1' to clear. */ #define GPIO_LATCH_PIN9_Pos (9UL) /*!< Position of PIN9 field. */ #define GPIO_LATCH_PIN9_Msk (0x1UL << GPIO_LATCH_PIN9_Pos) /*!< Bit mask of PIN9 field. */ #define GPIO_LATCH_PIN9_NotLatched (0UL) /*!< Criteria has not been met */ #define GPIO_LATCH_PIN9_Latched (1UL) /*!< Criteria has been met */ -/* Bit 8 : Status on whether PIN8 has met criteria set in PIN_CNF8.SENSE register. Write '1' to clear. */ +/* Bit 8 : Status on whether PIN[8] has met criteria set in PIN_CNF[8].SENSE register. Write '1' to clear. */ #define GPIO_LATCH_PIN8_Pos (8UL) /*!< Position of PIN8 field. */ #define GPIO_LATCH_PIN8_Msk (0x1UL << GPIO_LATCH_PIN8_Pos) /*!< Bit mask of PIN8 field. */ #define GPIO_LATCH_PIN8_NotLatched (0UL) /*!< Criteria has not been met */ #define GPIO_LATCH_PIN8_Latched (1UL) /*!< Criteria has been met */ -/* Bit 7 : Status on whether PIN7 has met criteria set in PIN_CNF7.SENSE register. Write '1' to clear. */ +/* Bit 7 : Status on whether PIN[7] has met criteria set in PIN_CNF[7].SENSE register. Write '1' to clear. */ #define GPIO_LATCH_PIN7_Pos (7UL) /*!< Position of PIN7 field. */ #define GPIO_LATCH_PIN7_Msk (0x1UL << GPIO_LATCH_PIN7_Pos) /*!< Bit mask of PIN7 field. */ #define GPIO_LATCH_PIN7_NotLatched (0UL) /*!< Criteria has not been met */ #define GPIO_LATCH_PIN7_Latched (1UL) /*!< Criteria has been met */ -/* Bit 6 : Status on whether PIN6 has met criteria set in PIN_CNF6.SENSE register. Write '1' to clear. */ +/* Bit 6 : Status on whether PIN[6] has met criteria set in PIN_CNF[6].SENSE register. Write '1' to clear. */ #define GPIO_LATCH_PIN6_Pos (6UL) /*!< Position of PIN6 field. */ #define GPIO_LATCH_PIN6_Msk (0x1UL << GPIO_LATCH_PIN6_Pos) /*!< Bit mask of PIN6 field. */ #define GPIO_LATCH_PIN6_NotLatched (0UL) /*!< Criteria has not been met */ #define GPIO_LATCH_PIN6_Latched (1UL) /*!< Criteria has been met */ -/* Bit 5 : Status on whether PIN5 has met criteria set in PIN_CNF5.SENSE register. Write '1' to clear. */ +/* Bit 5 : Status on whether PIN[5] has met criteria set in PIN_CNF[5].SENSE register. Write '1' to clear. */ #define GPIO_LATCH_PIN5_Pos (5UL) /*!< Position of PIN5 field. */ #define GPIO_LATCH_PIN5_Msk (0x1UL << GPIO_LATCH_PIN5_Pos) /*!< Bit mask of PIN5 field. */ #define GPIO_LATCH_PIN5_NotLatched (0UL) /*!< Criteria has not been met */ #define GPIO_LATCH_PIN5_Latched (1UL) /*!< Criteria has been met */ -/* Bit 4 : Status on whether PIN4 has met criteria set in PIN_CNF4.SENSE register. Write '1' to clear. */ +/* Bit 4 : Status on whether PIN[4] has met criteria set in PIN_CNF[4].SENSE register. Write '1' to clear. */ #define GPIO_LATCH_PIN4_Pos (4UL) /*!< Position of PIN4 field. */ #define GPIO_LATCH_PIN4_Msk (0x1UL << GPIO_LATCH_PIN4_Pos) /*!< Bit mask of PIN4 field. */ #define GPIO_LATCH_PIN4_NotLatched (0UL) /*!< Criteria has not been met */ #define GPIO_LATCH_PIN4_Latched (1UL) /*!< Criteria has been met */ -/* Bit 3 : Status on whether PIN3 has met criteria set in PIN_CNF3.SENSE register. Write '1' to clear. */ +/* Bit 3 : Status on whether PIN[3] has met criteria set in PIN_CNF[3].SENSE register. Write '1' to clear. */ #define GPIO_LATCH_PIN3_Pos (3UL) /*!< Position of PIN3 field. */ #define GPIO_LATCH_PIN3_Msk (0x1UL << GPIO_LATCH_PIN3_Pos) /*!< Bit mask of PIN3 field. */ #define GPIO_LATCH_PIN3_NotLatched (0UL) /*!< Criteria has not been met */ #define GPIO_LATCH_PIN3_Latched (1UL) /*!< Criteria has been met */ -/* Bit 2 : Status on whether PIN2 has met criteria set in PIN_CNF2.SENSE register. Write '1' to clear. */ +/* Bit 2 : Status on whether PIN[2] has met criteria set in PIN_CNF[2].SENSE register. Write '1' to clear. */ #define GPIO_LATCH_PIN2_Pos (2UL) /*!< Position of PIN2 field. */ #define GPIO_LATCH_PIN2_Msk (0x1UL << GPIO_LATCH_PIN2_Pos) /*!< Bit mask of PIN2 field. */ #define GPIO_LATCH_PIN2_NotLatched (0UL) /*!< Criteria has not been met */ #define GPIO_LATCH_PIN2_Latched (1UL) /*!< Criteria has been met */ -/* Bit 1 : Status on whether PIN1 has met criteria set in PIN_CNF1.SENSE register. Write '1' to clear. */ +/* Bit 1 : Status on whether PIN[1] has met criteria set in PIN_CNF[1].SENSE register. Write '1' to clear. */ #define GPIO_LATCH_PIN1_Pos (1UL) /*!< Position of PIN1 field. */ #define GPIO_LATCH_PIN1_Msk (0x1UL << GPIO_LATCH_PIN1_Pos) /*!< Bit mask of PIN1 field. */ #define GPIO_LATCH_PIN1_NotLatched (0UL) /*!< Criteria has not been met */ #define GPIO_LATCH_PIN1_Latched (1UL) /*!< Criteria has been met */ -/* Bit 0 : Status on whether PIN0 has met criteria set in PIN_CNF0.SENSE register. Write '1' to clear. */ +/* Bit 0 : Status on whether PIN[0] has met criteria set in PIN_CNF[0].SENSE register. Write '1' to clear. */ #define GPIO_LATCH_PIN0_Pos (0UL) /*!< Position of PIN0 field. */ #define GPIO_LATCH_PIN0_Msk (0x1UL << GPIO_LATCH_PIN0_Pos) /*!< Bit mask of PIN0 field. */ #define GPIO_LATCH_PIN0_NotLatched (0UL) /*!< Criteria has not been met */ @@ -6052,9 +6053,9 @@ POSSIBILITY OF SUCH DAMAGE. #define RADIO_EVENTS_FRAMESTART_EVENTS_FRAMESTART_Generated (1UL) /*!< Event generated */ /* Register: RADIO_EVENTS_EDEND */ -/* Description: Sampling of energy detection complete. A new ED sample is ready for readout from the RADIO.EDSAMPLE register */ +/* Description: Sampling of energy detection complete. A new ED sample is ready for readout from the RADIO.EDSAMPLE register. */ -/* Bit 0 : Sampling of energy detection complete. A new ED sample is ready for readout from the RADIO.EDSAMPLE register */ +/* Bit 0 : Sampling of energy detection complete. A new ED sample is ready for readout from the RADIO.EDSAMPLE register. */ #define RADIO_EVENTS_EDEND_EVENTS_EDEND_Pos (0UL) /*!< Position of EVENTS_EDEND field. */ #define RADIO_EVENTS_EDEND_EVENTS_EDEND_Msk (0x1UL << RADIO_EVENTS_EDEND_EVENTS_EDEND_Pos) /*!< Bit mask of EVENTS_EDEND field. */ #define RADIO_EVENTS_EDEND_EVENTS_EDEND_NotGenerated (0UL) /*!< Event not generated */ @@ -7019,11 +7020,11 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: RADIO_FREQUENCY */ /* Description: Frequency */ -/* Bit 8 : Channel map selection. */ +/* Bit 8 : Channel map selection */ #define RADIO_FREQUENCY_MAP_Pos (8UL) /*!< Position of MAP field. */ #define RADIO_FREQUENCY_MAP_Msk (0x1UL << RADIO_FREQUENCY_MAP_Pos) /*!< Bit mask of MAP field. */ -#define RADIO_FREQUENCY_MAP_Default (0UL) /*!< Channel map between 2400 MHZ .. 2500 MHz */ -#define RADIO_FREQUENCY_MAP_Low (1UL) /*!< Channel map between 2360 MHZ .. 2460 MHz */ +#define RADIO_FREQUENCY_MAP_Default (0UL) /*!< Channel map between 2400 MHz and 2500 MHz */ +#define RADIO_FREQUENCY_MAP_Low (1UL) /*!< Channel map between 2360 MHz and 2460 MHz */ /* Bits 6..0 : Radio channel frequency */ #define RADIO_FREQUENCY_FREQUENCY_Pos (0UL) /*!< Position of FREQUENCY field. */ @@ -7060,8 +7061,8 @@ POSSIBILITY OF SUCH DAMAGE. #define RADIO_MODE_MODE_Nrf_2Mbit (1UL) /*!< 2 Mbps Nordic proprietary radio mode */ #define RADIO_MODE_MODE_Ble_1Mbit (3UL) /*!< 1 Mbps BLE */ #define RADIO_MODE_MODE_Ble_2Mbit (4UL) /*!< 2 Mbps BLE */ -#define RADIO_MODE_MODE_Ble_LR125Kbit (5UL) /*!< Long range 125 kbps TX, 125 kbps and 500 kbps RX */ -#define RADIO_MODE_MODE_Ble_LR500Kbit (6UL) /*!< Long range 500 kbps TX, 125 kbps and 500 kbps RX */ +#define RADIO_MODE_MODE_Ble_LR125Kbit (5UL) /*!< Long Range 125 kbps TX, 125 kbps and 500 kbps RX */ +#define RADIO_MODE_MODE_Ble_LR500Kbit (6UL) /*!< Long Range 500 kbps TX, 125 kbps and 500 kbps RX */ #define RADIO_MODE_MODE_Ieee802154_250Kbit (15UL) /*!< IEEE 802.15.4-2006 250 kbps */ /* Register: RADIO_PCNF0 */ @@ -7083,9 +7084,9 @@ POSSIBILITY OF SUCH DAMAGE. #define RADIO_PCNF0_PLEN_8bit (0UL) /*!< 8-bit preamble */ #define RADIO_PCNF0_PLEN_16bit (1UL) /*!< 16-bit preamble */ #define RADIO_PCNF0_PLEN_32bitZero (2UL) /*!< 32-bit zero preamble - used for IEEE 802.15.4 */ -#define RADIO_PCNF0_PLEN_LongRange (3UL) /*!< Preamble - used for BLE long range */ +#define RADIO_PCNF0_PLEN_LongRange (3UL) /*!< Preamble - used for Bluetooth LE Long Range */ -/* Bits 23..22 : Length of code indicator - long range */ +/* Bits 23..22 : Length of code indicator - Long Range */ #define RADIO_PCNF0_CILEN_Pos (22UL) /*!< Position of CILEN field. */ #define RADIO_PCNF0_CILEN_Msk (0x3UL << RADIO_PCNF0_CILEN_Pos) /*!< Bit mask of CILEN field. */ @@ -7095,15 +7096,15 @@ POSSIBILITY OF SUCH DAMAGE. #define RADIO_PCNF0_S1INCL_Automatic (0UL) /*!< Include S1 field in RAM only if S1LEN > 0 */ #define RADIO_PCNF0_S1INCL_Include (1UL) /*!< Always include S1 field in RAM independent of S1LEN */ -/* Bits 19..16 : Length on air of S1 field in number of bits. */ +/* Bits 19..16 : Length on air of S1 field in number of bits */ #define RADIO_PCNF0_S1LEN_Pos (16UL) /*!< Position of S1LEN field. */ #define RADIO_PCNF0_S1LEN_Msk (0xFUL << RADIO_PCNF0_S1LEN_Pos) /*!< Bit mask of S1LEN field. */ -/* Bit 8 : Length on air of S0 field in number of bytes. */ +/* Bit 8 : Length on air of S0 field in number of bytes */ #define RADIO_PCNF0_S0LEN_Pos (8UL) /*!< Position of S0LEN field. */ #define RADIO_PCNF0_S0LEN_Msk (0x1UL << RADIO_PCNF0_S0LEN_Pos) /*!< Bit mask of S0LEN field. */ -/* Bits 3..0 : Length on air of LENGTH field in number of bits. */ +/* Bits 3..0 : Length on air of LENGTH field in number of bits */ #define RADIO_PCNF0_LFLEN_Pos (0UL) /*!< Position of LFLEN field. */ #define RADIO_PCNF0_LFLEN_Msk (0xFUL << RADIO_PCNF0_LFLEN_Pos) /*!< Bit mask of LFLEN field. */ @@ -7254,7 +7255,7 @@ POSSIBILITY OF SUCH DAMAGE. #define RADIO_CRCCNF_SKIPADDR_Skip (1UL) /*!< CRC calculation does not include address field. The CRC calculation will start at the first byte after the address. */ #define RADIO_CRCCNF_SKIPADDR_Ieee802154 (2UL) /*!< CRC calculation as per 802.15.4 standard. Starting at first byte after length field. */ -/* Bits 1..0 : CRC length in number of bytes. */ +/* Bits 1..0 : CRC length in number of bytes For MODE Ble_LR125Kbit and Ble_LR500Kbit, only LEN set to 3 is supported */ #define RADIO_CRCCNF_LEN_Pos (0UL) /*!< Position of LEN field. */ #define RADIO_CRCCNF_LEN_Msk (0x3UL << RADIO_CRCCNF_LEN_Pos) /*!< Bit mask of LEN field. */ #define RADIO_CRCCNF_LEN_Disabled (0UL) /*!< CRC length is zero and CRC calculation is disabled */ @@ -7279,14 +7280,14 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: RADIO_TIFS */ /* Description: Interframe spacing in us */ -/* Bits 9..0 : Interframe spacing in us */ +/* Bits 9..0 : Interframe spacing in us. */ #define RADIO_TIFS_TIFS_Pos (0UL) /*!< Position of TIFS field. */ #define RADIO_TIFS_TIFS_Msk (0x3FFUL << RADIO_TIFS_TIFS_Pos) /*!< Bit mask of TIFS field. */ /* Register: RADIO_RSSISAMPLE */ /* Description: RSSI sample */ -/* Bits 6..0 : RSSI sample */ +/* Bits 6..0 : RSSI sample. */ #define RADIO_RSSISAMPLE_RSSISAMPLE_Pos (0UL) /*!< Position of RSSISAMPLE field. */ #define RADIO_RSSISAMPLE_RSSISAMPLE_Msk (0x7FUL << RADIO_RSSISAMPLE_RSSISAMPLE_Pos) /*!< Bit mask of RSSISAMPLE field. */ @@ -7445,7 +7446,7 @@ POSSIBILITY OF SUCH DAMAGE. #define RADIO_MODECNF0_RU_Pos (0UL) /*!< Position of RU field. */ #define RADIO_MODECNF0_RU_Msk (0x1UL << RADIO_MODECNF0_RU_Pos) /*!< Bit mask of RU field. */ #define RADIO_MODECNF0_RU_Default (0UL) /*!< Default ramp-up time (tRXEN and tTXEN), compatible with firmware written for nRF51 */ -#define RADIO_MODECNF0_RU_Fast (1UL) /*!< Fast ramp-up (tRXEN,FAST and tTXEN,FAST), see electrical specification for more information */ +#define RADIO_MODECNF0_RU_Fast (1UL) /*!< Fast ramp-up (tRXEN,FAST and tTXEN,FAST), see electrical specifications for more information */ /* Register: RADIO_SFD */ /* Description: IEEE 802.15.4 start of frame delimiter */ @@ -7513,32 +7514,32 @@ POSSIBILITY OF SUCH DAMAGE. #define RADIO_CTEINLINECONF_S0CONF_Pos (16UL) /*!< Position of S0CONF field. */ #define RADIO_CTEINLINECONF_S0CONF_Msk (0xFFUL << RADIO_CTEINLINECONF_S0CONF_Pos) /*!< Bit mask of S0CONF field. */ -/* Bits 15..13 : Spacing between samples for the samples in the SWITCHING period when CTEINLINEMODE is set */ +/* Bits 15..13 : Spacing between samples for the samples in the SWITCHING period when CTEINLINEMODE is set. */ #define RADIO_CTEINLINECONF_CTEINLINERXMODE2US_Pos (13UL) /*!< Position of CTEINLINERXMODE2US field. */ #define RADIO_CTEINLINECONF_CTEINLINERXMODE2US_Msk (0x7UL << RADIO_CTEINLINECONF_CTEINLINERXMODE2US_Pos) /*!< Bit mask of CTEINLINERXMODE2US field. */ -#define RADIO_CTEINLINECONF_CTEINLINERXMODE2US_4us (1UL) /*!< 4us */ -#define RADIO_CTEINLINECONF_CTEINLINERXMODE2US_2us (2UL) /*!< 2us */ -#define RADIO_CTEINLINECONF_CTEINLINERXMODE2US_1us (3UL) /*!< 1us */ -#define RADIO_CTEINLINECONF_CTEINLINERXMODE2US_500ns (4UL) /*!< 0.5us */ -#define RADIO_CTEINLINECONF_CTEINLINERXMODE2US_250ns (5UL) /*!< 0.25us */ -#define RADIO_CTEINLINECONF_CTEINLINERXMODE2US_125ns (6UL) /*!< 0.125us */ - -/* Bits 12..10 : Spacing between samples for the samples in the SWITCHING period when CTEINLINEMODE is set */ +#define RADIO_CTEINLINECONF_CTEINLINERXMODE2US_4us (1UL) /*!< 4 us */ +#define RADIO_CTEINLINECONF_CTEINLINERXMODE2US_2us (2UL) /*!< 2 us */ +#define RADIO_CTEINLINECONF_CTEINLINERXMODE2US_1us (3UL) /*!< 1 us */ +#define RADIO_CTEINLINECONF_CTEINLINERXMODE2US_500ns (4UL) /*!< 0.5 us */ +#define RADIO_CTEINLINECONF_CTEINLINERXMODE2US_250ns (5UL) /*!< 0.25 us */ +#define RADIO_CTEINLINECONF_CTEINLINERXMODE2US_125ns (6UL) /*!< 0.125 us */ + +/* Bits 12..10 : Spacing between samples for the samples in the SWITCHING period when CTEINLINEMODE is set. */ #define RADIO_CTEINLINECONF_CTEINLINERXMODE1US_Pos (10UL) /*!< Position of CTEINLINERXMODE1US field. */ #define RADIO_CTEINLINECONF_CTEINLINERXMODE1US_Msk (0x7UL << RADIO_CTEINLINECONF_CTEINLINERXMODE1US_Pos) /*!< Bit mask of CTEINLINERXMODE1US field. */ -#define RADIO_CTEINLINECONF_CTEINLINERXMODE1US_4us (1UL) /*!< 4us */ -#define RADIO_CTEINLINECONF_CTEINLINERXMODE1US_2us (2UL) /*!< 2us */ -#define RADIO_CTEINLINECONF_CTEINLINERXMODE1US_1us (3UL) /*!< 1us */ -#define RADIO_CTEINLINECONF_CTEINLINERXMODE1US_500ns (4UL) /*!< 0.5us */ -#define RADIO_CTEINLINECONF_CTEINLINERXMODE1US_250ns (5UL) /*!< 0.25us */ -#define RADIO_CTEINLINECONF_CTEINLINERXMODE1US_125ns (6UL) /*!< 0.125us */ +#define RADIO_CTEINLINECONF_CTEINLINERXMODE1US_4us (1UL) /*!< 4 us */ +#define RADIO_CTEINLINECONF_CTEINLINERXMODE1US_2us (2UL) /*!< 2 us */ +#define RADIO_CTEINLINECONF_CTEINLINERXMODE1US_1us (3UL) /*!< 1 us */ +#define RADIO_CTEINLINECONF_CTEINLINERXMODE1US_500ns (4UL) /*!< 0.5 us */ +#define RADIO_CTEINLINECONF_CTEINLINERXMODE1US_250ns (5UL) /*!< 0.25 us */ +#define RADIO_CTEINLINECONF_CTEINLINERXMODE1US_125ns (6UL) /*!< 0.125 us */ /* Bits 7..6 : Max range of CTETime */ #define RADIO_CTEINLINECONF_CTETIMEVALIDRANGE_Pos (6UL) /*!< Position of CTETIMEVALIDRANGE field. */ #define RADIO_CTEINLINECONF_CTETIMEVALIDRANGE_Msk (0x3UL << RADIO_CTEINLINECONF_CTETIMEVALIDRANGE_Pos) /*!< Bit mask of CTETIMEVALIDRANGE field. */ -#define RADIO_CTEINLINECONF_CTETIMEVALIDRANGE_20 (0UL) /*!< 20 in 8us unit (default) Set to 20 if parsed CTETime is larger han 20 */ -#define RADIO_CTEINLINECONF_CTETIMEVALIDRANGE_31 (1UL) /*!< 31 in 8us unit */ -#define RADIO_CTEINLINECONF_CTETIMEVALIDRANGE_63 (2UL) /*!< 63 in 8us unit */ +#define RADIO_CTEINLINECONF_CTETIMEVALIDRANGE_20 (0UL) /*!< 20 in 8 us unit (default) Set to 20 if parsed CTETime is larger than 20 */ +#define RADIO_CTEINLINECONF_CTETIMEVALIDRANGE_31 (1UL) /*!< 31 in 8 us unit */ +#define RADIO_CTEINLINECONF_CTETIMEVALIDRANGE_63 (2UL) /*!< 63 in 8 us unit */ /* Bit 4 : Sampling/switching if CRC is not OK */ #define RADIO_CTEINLINECONF_CTEERRORHANDLING_Pos (4UL) /*!< Position of CTEERRORHANDLING field. */ @@ -7573,12 +7574,12 @@ POSSIBILITY OF SUCH DAMAGE. /* Bits 18..16 : Interval between samples in the SWITCHING period when CTEINLINECTRLEN is 0 */ #define RADIO_DFECTRL1_TSAMPLESPACING_Pos (16UL) /*!< Position of TSAMPLESPACING field. */ #define RADIO_DFECTRL1_TSAMPLESPACING_Msk (0x7UL << RADIO_DFECTRL1_TSAMPLESPACING_Pos) /*!< Bit mask of TSAMPLESPACING field. */ -#define RADIO_DFECTRL1_TSAMPLESPACING_4us (1UL) /*!< 4us */ -#define RADIO_DFECTRL1_TSAMPLESPACING_2us (2UL) /*!< 2us */ -#define RADIO_DFECTRL1_TSAMPLESPACING_1us (3UL) /*!< 1us */ -#define RADIO_DFECTRL1_TSAMPLESPACING_500ns (4UL) /*!< 0.5us */ -#define RADIO_DFECTRL1_TSAMPLESPACING_250ns (5UL) /*!< 0.25us */ -#define RADIO_DFECTRL1_TSAMPLESPACING_125ns (6UL) /*!< 0.125us */ +#define RADIO_DFECTRL1_TSAMPLESPACING_4us (1UL) /*!< 4 us */ +#define RADIO_DFECTRL1_TSAMPLESPACING_2us (2UL) /*!< 2 us */ +#define RADIO_DFECTRL1_TSAMPLESPACING_1us (3UL) /*!< 1 us */ +#define RADIO_DFECTRL1_TSAMPLESPACING_500ns (4UL) /*!< 0.5 us */ +#define RADIO_DFECTRL1_TSAMPLESPACING_250ns (5UL) /*!< 0.25 us */ +#define RADIO_DFECTRL1_TSAMPLESPACING_125ns (6UL) /*!< 0.125 us */ /* Bit 15 : Whether to sample I/Q or magnitude/phase */ #define RADIO_DFECTRL1_SAMPLETYPE_Pos (15UL) /*!< Position of SAMPLETYPE field. */ @@ -7589,19 +7590,19 @@ POSSIBILITY OF SUCH DAMAGE. /* Bits 14..12 : Interval between samples in the REFERENCE period */ #define RADIO_DFECTRL1_TSAMPLESPACINGREF_Pos (12UL) /*!< Position of TSAMPLESPACINGREF field. */ #define RADIO_DFECTRL1_TSAMPLESPACINGREF_Msk (0x7UL << RADIO_DFECTRL1_TSAMPLESPACINGREF_Pos) /*!< Bit mask of TSAMPLESPACINGREF field. */ -#define RADIO_DFECTRL1_TSAMPLESPACINGREF_4us (1UL) /*!< 4us */ -#define RADIO_DFECTRL1_TSAMPLESPACINGREF_2us (2UL) /*!< 2us */ -#define RADIO_DFECTRL1_TSAMPLESPACINGREF_1us (3UL) /*!< 1us */ -#define RADIO_DFECTRL1_TSAMPLESPACINGREF_500ns (4UL) /*!< 0.5us */ -#define RADIO_DFECTRL1_TSAMPLESPACINGREF_250ns (5UL) /*!< 0.25us */ -#define RADIO_DFECTRL1_TSAMPLESPACINGREF_125ns (6UL) /*!< 0.125us */ +#define RADIO_DFECTRL1_TSAMPLESPACINGREF_4us (1UL) /*!< 4 us */ +#define RADIO_DFECTRL1_TSAMPLESPACINGREF_2us (2UL) /*!< 2 us */ +#define RADIO_DFECTRL1_TSAMPLESPACINGREF_1us (3UL) /*!< 1 us */ +#define RADIO_DFECTRL1_TSAMPLESPACINGREF_500ns (4UL) /*!< 0.5 us */ +#define RADIO_DFECTRL1_TSAMPLESPACINGREF_250ns (5UL) /*!< 0.25 us */ +#define RADIO_DFECTRL1_TSAMPLESPACINGREF_125ns (6UL) /*!< 0.125 us */ /* Bits 10..8 : Interval between every time the antenna is changed in the SWITCHING state */ #define RADIO_DFECTRL1_TSWITCHSPACING_Pos (8UL) /*!< Position of TSWITCHSPACING field. */ #define RADIO_DFECTRL1_TSWITCHSPACING_Msk (0x7UL << RADIO_DFECTRL1_TSWITCHSPACING_Pos) /*!< Bit mask of TSWITCHSPACING field. */ -#define RADIO_DFECTRL1_TSWITCHSPACING_4us (1UL) /*!< 4us */ -#define RADIO_DFECTRL1_TSWITCHSPACING_2us (2UL) /*!< 2us */ -#define RADIO_DFECTRL1_TSWITCHSPACING_1us (3UL) /*!< 1us */ +#define RADIO_DFECTRL1_TSWITCHSPACING_4us (1UL) /*!< 4 us */ +#define RADIO_DFECTRL1_TSWITCHSPACING_2us (2UL) /*!< 2 us */ +#define RADIO_DFECTRL1_TSWITCHSPACING_1us (3UL) /*!< 1 us */ /* Bit 7 : Add CTE extension and do antenna switching/sampling in this extension */ #define RADIO_DFECTRL1_DFEINEXTENSION_Pos (7UL) /*!< Position of DFEINEXTENSION field. */ @@ -7616,18 +7617,18 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: RADIO_DFECTRL2 */ /* Description: Start offset for Direction finding */ -/* Bits 27..16 : Signed value offset before starting sampling in number of 16M cycles relative to the beginning of the REFERENCE state - 12 us after switching start */ +/* Bits 27..16 : Signed value offset in number of 16 MHz clock cycles for fine tuning of the sampling instant for all IQ samples. With TSAMPLEOFFSET=0 the first sample is taken immediately at the start of the reference period */ #define RADIO_DFECTRL2_TSAMPLEOFFSET_Pos (16UL) /*!< Position of TSAMPLEOFFSET field. */ #define RADIO_DFECTRL2_TSAMPLEOFFSET_Msk (0xFFFUL << RADIO_DFECTRL2_TSAMPLEOFFSET_Pos) /*!< Bit mask of TSAMPLEOFFSET field. */ -/* Bits 12..0 : Signed value offset after the end of the CRC before starting switching in number of 16M cycles */ +/* Bits 12..0 : Signed value offset after the end of the CRC before starting switching in number of 16 MHz clock cycles */ #define RADIO_DFECTRL2_TSWITCHOFFSET_Pos (0UL) /*!< Position of TSWITCHOFFSET field. */ #define RADIO_DFECTRL2_TSWITCHOFFSET_Msk (0x1FFFUL << RADIO_DFECTRL2_TSWITCHOFFSET_Pos) /*!< Bit mask of TSWITCHOFFSET field. */ /* Register: RADIO_SWITCHPATTERN */ /* Description: GPIO patterns to be used for each antenna */ -/* Bits 7..0 : Fill array of GPIO patterns for antenna control */ +/* Bits 7..0 : Fill array of GPIO patterns for antenna control. */ #define RADIO_SWITCHPATTERN_SWITCHPATTERN_Pos (0UL) /*!< Position of SWITCHPATTERN field. */ #define RADIO_SWITCHPATTERN_SWITCHPATTERN_Msk (0xFFUL << RADIO_SWITCHPATTERN_SWITCHPATTERN_Pos) /*!< Bit mask of SWITCHPATTERN field. */ @@ -8331,7 +8332,7 @@ POSSIBILITY OF SUCH DAMAGE. #define RTC_COUNTER_COUNTER_Msk (0xFFFFFFUL << RTC_COUNTER_COUNTER_Pos) /*!< Bit mask of COUNTER field. */ /* Register: RTC_PRESCALER */ -/* Description: 12-bit prescaler for counter frequency (32768/(PRESCALER+1)). Must be written when RTC is stopped. */ +/* Description: 12-bit prescaler for counter frequency (32768 / (PRESCALER + 1)). Must be written when RTC is stopped. */ /* Bits 11..0 : Prescaler value */ #define RTC_PRESCALER_PRESCALER_Pos (0UL) /*!< Position of PRESCALER field. */ @@ -8628,7 +8629,7 @@ POSSIBILITY OF SUCH DAMAGE. #define SPIM_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */ /* Register: SPIM_STALLSTAT */ -/* Description: Stall status for EasyDMA RAM accesses. The fields in this register is set to STALL by hardware whenever a stall occurres and can be cleared (set to NOSTALL) by the CPU. */ +/* Description: Stall status for EasyDMA RAM accesses. The fields in this register are set to STALL by hardware whenever a stall occurres and can be cleared (set to NOSTALL) by the CPU. */ /* Bit 1 : Stall status for EasyDMA RAM writes */ #define SPIM_STALLSTAT_RX_Pos (1UL) /*!< Position of RX field. */ @@ -9335,121 +9336,121 @@ POSSIBILITY OF SUCH DAMAGE. #define TEMP_TEMP_TEMP_Msk (0xFFFFFFFFUL << TEMP_TEMP_TEMP_Pos) /*!< Bit mask of TEMP field. */ /* Register: TEMP_A0 */ -/* Description: Slope of 1st piece wise linear function */ +/* Description: Slope of first piecewise linear function */ -/* Bits 11..0 : Slope of 1st piece wise linear function */ +/* Bits 11..0 : Slope of first piecewise linear function */ #define TEMP_A0_A0_Pos (0UL) /*!< Position of A0 field. */ #define TEMP_A0_A0_Msk (0xFFFUL << TEMP_A0_A0_Pos) /*!< Bit mask of A0 field. */ /* Register: TEMP_A1 */ -/* Description: Slope of 2nd piece wise linear function */ +/* Description: Slope of second piecewise linear function */ -/* Bits 11..0 : Slope of 2nd piece wise linear function */ +/* Bits 11..0 : Slope of second piecewise linear function */ #define TEMP_A1_A1_Pos (0UL) /*!< Position of A1 field. */ #define TEMP_A1_A1_Msk (0xFFFUL << TEMP_A1_A1_Pos) /*!< Bit mask of A1 field. */ /* Register: TEMP_A2 */ -/* Description: Slope of 3rd piece wise linear function */ +/* Description: Slope of third piecewise linear function */ -/* Bits 11..0 : Slope of 3rd piece wise linear function */ +/* Bits 11..0 : Slope of third piecewise linear function */ #define TEMP_A2_A2_Pos (0UL) /*!< Position of A2 field. */ #define TEMP_A2_A2_Msk (0xFFFUL << TEMP_A2_A2_Pos) /*!< Bit mask of A2 field. */ /* Register: TEMP_A3 */ -/* Description: Slope of 4th piece wise linear function */ +/* Description: Slope of fourth piecewise linear function */ -/* Bits 11..0 : Slope of 4th piece wise linear function */ +/* Bits 11..0 : Slope of fourth piecewise linear function */ #define TEMP_A3_A3_Pos (0UL) /*!< Position of A3 field. */ #define TEMP_A3_A3_Msk (0xFFFUL << TEMP_A3_A3_Pos) /*!< Bit mask of A3 field. */ /* Register: TEMP_A4 */ -/* Description: Slope of 5th piece wise linear function */ +/* Description: Slope of fifth piecewise linear function */ -/* Bits 11..0 : Slope of 5th piece wise linear function */ +/* Bits 11..0 : Slope of fifth piecewise linear function */ #define TEMP_A4_A4_Pos (0UL) /*!< Position of A4 field. */ #define TEMP_A4_A4_Msk (0xFFFUL << TEMP_A4_A4_Pos) /*!< Bit mask of A4 field. */ /* Register: TEMP_A5 */ -/* Description: Slope of 6th piece wise linear function */ +/* Description: Slope of sixth piecewise linear function */ -/* Bits 11..0 : Slope of 6th piece wise linear function */ +/* Bits 11..0 : Slope of sixth piecewise linear function */ #define TEMP_A5_A5_Pos (0UL) /*!< Position of A5 field. */ #define TEMP_A5_A5_Msk (0xFFFUL << TEMP_A5_A5_Pos) /*!< Bit mask of A5 field. */ /* Register: TEMP_B0 */ -/* Description: y-intercept of 1st piece wise linear function */ +/* Description: y-intercept of first piecewise linear function */ -/* Bits 11..0 : y-intercept of 1st piece wise linear function */ +/* Bits 11..0 : y-intercept of first piecewise linear function */ #define TEMP_B0_B0_Pos (0UL) /*!< Position of B0 field. */ #define TEMP_B0_B0_Msk (0xFFFUL << TEMP_B0_B0_Pos) /*!< Bit mask of B0 field. */ /* Register: TEMP_B1 */ -/* Description: y-intercept of 2nd piece wise linear function */ +/* Description: y-intercept of second piecewise linear function */ -/* Bits 11..0 : y-intercept of 2nd piece wise linear function */ +/* Bits 11..0 : y-intercept of second piecewise linear function */ #define TEMP_B1_B1_Pos (0UL) /*!< Position of B1 field. */ #define TEMP_B1_B1_Msk (0xFFFUL << TEMP_B1_B1_Pos) /*!< Bit mask of B1 field. */ /* Register: TEMP_B2 */ -/* Description: y-intercept of 3rd piece wise linear function */ +/* Description: y-intercept of third piecewise linear function */ -/* Bits 11..0 : y-intercept of 3rd piece wise linear function */ +/* Bits 11..0 : y-intercept of third piecewise linear function */ #define TEMP_B2_B2_Pos (0UL) /*!< Position of B2 field. */ #define TEMP_B2_B2_Msk (0xFFFUL << TEMP_B2_B2_Pos) /*!< Bit mask of B2 field. */ /* Register: TEMP_B3 */ -/* Description: y-intercept of 4th piece wise linear function */ +/* Description: y-intercept of fourth piecewise linear function */ -/* Bits 11..0 : y-intercept of 4th piece wise linear function */ +/* Bits 11..0 : y-intercept of fourth piecewise linear function */ #define TEMP_B3_B3_Pos (0UL) /*!< Position of B3 field. */ #define TEMP_B3_B3_Msk (0xFFFUL << TEMP_B3_B3_Pos) /*!< Bit mask of B3 field. */ /* Register: TEMP_B4 */ -/* Description: y-intercept of 5th piece wise linear function */ +/* Description: y-intercept of fifth piecewise linear function */ -/* Bits 11..0 : y-intercept of 5th piece wise linear function */ +/* Bits 11..0 : y-intercept of fifth piecewise linear function */ #define TEMP_B4_B4_Pos (0UL) /*!< Position of B4 field. */ #define TEMP_B4_B4_Msk (0xFFFUL << TEMP_B4_B4_Pos) /*!< Bit mask of B4 field. */ /* Register: TEMP_B5 */ -/* Description: y-intercept of 6th piece wise linear function */ +/* Description: y-intercept of sixth piecewise linear function */ -/* Bits 11..0 : y-intercept of 6th piece wise linear function */ +/* Bits 11..0 : y-intercept of sixth piecewise linear function */ #define TEMP_B5_B5_Pos (0UL) /*!< Position of B5 field. */ #define TEMP_B5_B5_Msk (0xFFFUL << TEMP_B5_B5_Pos) /*!< Bit mask of B5 field. */ /* Register: TEMP_T0 */ -/* Description: End point of 1st piece wise linear function */ +/* Description: Endpoint of first piecewise linear function */ -/* Bits 7..0 : End point of 1st piece wise linear function */ +/* Bits 7..0 : Endpoint of first piecewise linear function */ #define TEMP_T0_T0_Pos (0UL) /*!< Position of T0 field. */ #define TEMP_T0_T0_Msk (0xFFUL << TEMP_T0_T0_Pos) /*!< Bit mask of T0 field. */ /* Register: TEMP_T1 */ -/* Description: End point of 2nd piece wise linear function */ +/* Description: Endpoint of second piecewise linear function */ -/* Bits 7..0 : End point of 2nd piece wise linear function */ +/* Bits 7..0 : Endpoint of second piecewise linear function */ #define TEMP_T1_T1_Pos (0UL) /*!< Position of T1 field. */ #define TEMP_T1_T1_Msk (0xFFUL << TEMP_T1_T1_Pos) /*!< Bit mask of T1 field. */ /* Register: TEMP_T2 */ -/* Description: End point of 3rd piece wise linear function */ +/* Description: Endpoint of third piecewise linear function */ -/* Bits 7..0 : End point of 3rd piece wise linear function */ +/* Bits 7..0 : Endpoint of third piecewise linear function */ #define TEMP_T2_T2_Pos (0UL) /*!< Position of T2 field. */ #define TEMP_T2_T2_Msk (0xFFUL << TEMP_T2_T2_Pos) /*!< Bit mask of T2 field. */ /* Register: TEMP_T3 */ -/* Description: End point of 4th piece wise linear function */ +/* Description: Endpoint of fourth piecewise linear function */ -/* Bits 7..0 : End point of 4th piece wise linear function */ +/* Bits 7..0 : Endpoint of fourth piecewise linear function */ #define TEMP_T3_T3_Pos (0UL) /*!< Position of T3 field. */ #define TEMP_T3_T3_Msk (0xFFUL << TEMP_T3_T3_Pos) /*!< Bit mask of T3 field. */ /* Register: TEMP_T4 */ -/* Description: End point of 5th piece wise linear function */ +/* Description: Endpoint of fifth piecewise linear function */ -/* Bits 7..0 : End point of 5th piece wise linear function */ +/* Bits 7..0 : Endpoint of fifth piecewise linear function */ #define TEMP_T4_T4_Pos (0UL) /*!< Position of T4 field. */ #define TEMP_T4_T4_Msk (0xFFUL << TEMP_T4_T4_Pos) /*!< Bit mask of T4 field. */ @@ -10189,12 +10190,6 @@ POSSIBILITY OF SUCH DAMAGE. #define TWIM_SHORTS_LASTRX_STOP_Disabled (0UL) /*!< Disable shortcut */ #define TWIM_SHORTS_LASTRX_STOP_Enabled (1UL) /*!< Enable shortcut */ -/* Bit 11 : Shortcut between event LASTRX and task SUSPEND */ -#define TWIM_SHORTS_LASTRX_SUSPEND_Pos (11UL) /*!< Position of LASTRX_SUSPEND field. */ -#define TWIM_SHORTS_LASTRX_SUSPEND_Msk (0x1UL << TWIM_SHORTS_LASTRX_SUSPEND_Pos) /*!< Bit mask of LASTRX_SUSPEND field. */ -#define TWIM_SHORTS_LASTRX_SUSPEND_Disabled (0UL) /*!< Disable shortcut */ -#define TWIM_SHORTS_LASTRX_SUSPEND_Enabled (1UL) /*!< Enable shortcut */ - /* Bit 10 : Shortcut between event LASTRX and task STARTTX */ #define TWIM_SHORTS_LASTRX_STARTTX_Pos (10UL) /*!< Position of LASTRX_STARTTX field. */ #define TWIM_SHORTS_LASTRX_STARTTX_Msk (0x1UL << TWIM_SHORTS_LASTRX_STARTTX_Pos) /*!< Bit mask of LASTRX_STARTTX field. */ @@ -10919,7 +10914,7 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: TWIS_MATCH */ /* Description: Status register indicating which address had a match */ -/* Bit 0 : Which of the addresses in {ADDRESS} matched the incoming address */ +/* Bit 0 : Indication of which address in {ADDRESS} that matched the incoming address */ #define TWIS_MATCH_MATCH_Pos (0UL) /*!< Position of MATCH field. */ #define TWIS_MATCH_MATCH_Msk (0x1UL << TWIS_MATCH_MATCH_Pos) /*!< Bit mask of MATCH field. */ @@ -11651,7 +11646,7 @@ POSSIBILITY OF SUCH DAMAGE. #define UARTE_INTENCLR_CTS_Clear (1UL) /*!< Disable */ /* Register: UARTE_ERRORSRC */ -/* Description: Error source Note : this register is read / write one to clear. */ +/* Description: Error source */ /* Bit 3 : Break condition */ #define UARTE_ERRORSRC_BREAK_Pos (3UL) /*!< Position of BREAK field. */ @@ -11777,7 +11772,7 @@ POSSIBILITY OF SUCH DAMAGE. #define UARTE_BAUDRATE_BAUDRATE_Baud250000 (0x04000000UL) /*!< 250000 baud */ #define UARTE_BAUDRATE_BAUDRATE_Baud460800 (0x07400000UL) /*!< 460800 baud (actual rate: 457143) */ #define UARTE_BAUDRATE_BAUDRATE_Baud921600 (0x0F000000UL) /*!< 921600 baud (actual rate: 941176) */ -#define UARTE_BAUDRATE_BAUDRATE_Baud1M (0x10000000UL) /*!< 1Mega baud */ +#define UARTE_BAUDRATE_BAUDRATE_Baud1M (0x10000000UL) /*!< 1 megabaud */ /* Register: UARTE_RXD_PTR */ /* Description: Data pointer */ @@ -11856,11 +11851,11 @@ POSSIBILITY OF SUCH DAMAGE. /* Description: Access port protection */ /* Bits 31..0 : Blocks debugger read/write access to all CPU registers and memory mapped - addresses Using any value except Unprotected will lead to the protection being enabled. */ + addresses. */ #define UICR_APPROTECT_PALL_Pos (0UL) /*!< Position of PALL field. */ #define UICR_APPROTECT_PALL_Msk (0xFFFFFFFFUL << UICR_APPROTECT_PALL_Pos) /*!< Bit mask of PALL field. */ #define UICR_APPROTECT_PALL_Protected (0x00000000UL) /*!< Protected */ -#define UICR_APPROTECT_PALL_Unprotected (0xFFFFFFFFUL) /*!< Unprotected */ +#define UICR_APPROTECT_PALL_Unprotected (0x50FA50FAUL) /*!< Unprotected */ /* Register: UICR_ERASEPROTECT */ /* Description: Erase protection */ @@ -12053,17 +12048,17 @@ POSSIBILITY OF SUCH DAMAGE. /* Description: Watchdog Timer */ /* Register: WDT_TASKS_START */ -/* Description: Start the watchdog */ +/* Description: Start WDT */ -/* Bit 0 : Start the watchdog */ +/* Bit 0 : Start WDT */ #define WDT_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */ #define WDT_TASKS_START_TASKS_START_Msk (0x1UL << WDT_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */ #define WDT_TASKS_START_TASKS_START_Trigger (1UL) /*!< Trigger task */ /* Register: WDT_TASKS_STOP */ -/* Description: Stop the watchdog timer. */ +/* Description: Stop WDT */ -/* Bit 0 : Stop the watchdog timer. */ +/* Bit 0 : Stop WDT */ #define WDT_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */ #define WDT_TASKS_STOP_TASKS_STOP_Msk (0x1UL << WDT_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */ #define WDT_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */ @@ -12209,10 +12204,10 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: WDT_RUNSTATUS */ /* Description: Run status */ -/* Bit 0 : Indicates whether or not the watchdog is running */ +/* Bit 0 : Indicates whether or not WDT is running */ #define WDT_RUNSTATUS_RUNSTATUSWDT_Pos (0UL) /*!< Position of RUNSTATUSWDT field. */ #define WDT_RUNSTATUS_RUNSTATUSWDT_Msk (0x1UL << WDT_RUNSTATUS_RUNSTATUSWDT_Pos) /*!< Bit mask of RUNSTATUSWDT field. */ -#define WDT_RUNSTATUS_RUNSTATUSWDT_NotRunning (0UL) /*!< Watchdog not running */ +#define WDT_RUNSTATUS_RUNSTATUSWDT_NotRunning (0UL) /*!< Watchdog is not running */ #define WDT_RUNSTATUS_RUNSTATUSWDT_Running (1UL) /*!< Watchdog is running */ /* Register: WDT_REQSTATUS */ @@ -12327,31 +12322,31 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: WDT_CONFIG */ /* Description: Configuration register */ -/* Bit 6 : Allow stopping the watchdog */ +/* Bit 6 : Allow stopping WDT */ #define WDT_CONFIG_STOPEN_Pos (6UL) /*!< Position of STOPEN field. */ #define WDT_CONFIG_STOPEN_Msk (0x1UL << WDT_CONFIG_STOPEN_Pos) /*!< Bit mask of STOPEN field. */ -#define WDT_CONFIG_STOPEN_Disable (0UL) /*!< Do not allow stopping the watchdog */ -#define WDT_CONFIG_STOPEN_Enable (1UL) /*!< Allow stopping the watchdog */ +#define WDT_CONFIG_STOPEN_Disable (0UL) /*!< Do not allow stopping WDT */ +#define WDT_CONFIG_STOPEN_Enable (1UL) /*!< Allow stopping WDT */ -/* Bit 3 : Configure the watchdog to either be paused, or kept running, while the CPU is halted by the debugger */ +/* Bit 3 : Configure WDT to either be paused, or kept running, while the CPU is halted by the debugger */ #define WDT_CONFIG_HALT_Pos (3UL) /*!< Position of HALT field. */ #define WDT_CONFIG_HALT_Msk (0x1UL << WDT_CONFIG_HALT_Pos) /*!< Bit mask of HALT field. */ -#define WDT_CONFIG_HALT_Pause (0UL) /*!< Pause watchdog while the CPU is halted by the debugger */ -#define WDT_CONFIG_HALT_Run (1UL) /*!< Keep the watchdog running while the CPU is halted by the debugger */ +#define WDT_CONFIG_HALT_Pause (0UL) /*!< Pause WDT while the CPU is halted by the debugger */ +#define WDT_CONFIG_HALT_Run (1UL) /*!< Keep WDT running while the CPU is halted by the debugger */ -/* Bit 0 : Configure the watchdog to either be paused, or kept running, while the CPU is sleeping */ +/* Bit 0 : Configure WDT to either be paused, or kept running, while the CPU is sleeping */ #define WDT_CONFIG_SLEEP_Pos (0UL) /*!< Position of SLEEP field. */ #define WDT_CONFIG_SLEEP_Msk (0x1UL << WDT_CONFIG_SLEEP_Pos) /*!< Bit mask of SLEEP field. */ -#define WDT_CONFIG_SLEEP_Pause (0UL) /*!< Pause watchdog while the CPU is sleeping */ -#define WDT_CONFIG_SLEEP_Run (1UL) /*!< Keep the watchdog running while the CPU is sleeping */ +#define WDT_CONFIG_SLEEP_Pause (0UL) /*!< Pause WDT while the CPU is sleeping */ +#define WDT_CONFIG_SLEEP_Run (1UL) /*!< Keep WDT running while the CPU is sleeping */ /* Register: WDT_TSEN */ -/* Description: Task Stop Enable */ +/* Description: Task stop enable */ -/* Bits 31..0 : Task stop enable register */ +/* Bits 31..0 : Allow stopping WDT */ #define WDT_TSEN_TSEN_Pos (0UL) /*!< Position of TSEN field. */ #define WDT_TSEN_TSEN_Msk (0xFFFFFFFFUL << WDT_TSEN_TSEN_Pos) /*!< Bit mask of TSEN field. */ -#define WDT_TSEN_TSEN_Enable (0x6E524635UL) /*!< Value to allow stopping the watchdog */ +#define WDT_TSEN_TSEN_Enable (0x6E524635UL) /*!< Value to allow stopping WDT */ /* Register: WDT_RR */ /* Description: Description collection: Reload request n */ diff --git a/mdk/nrf5340_network_name_change.h b/mdk/nrf5340_network_name_change.h new file mode 100644 index 0000000000..ec363e7eba --- /dev/null +++ b/mdk/nrf5340_network_name_change.h @@ -0,0 +1,51 @@ +/* + +Copyright (c) 2010 - 2021, Nordic Semiconductor ASA All rights reserved. + +SPDX-License-Identifier: BSD-3-Clause + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + +1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + +2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + +3. Neither the name of Nordic Semiconductor ASA nor the names of its + contributors may be used to endorse or promote products derived from this + software without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE +ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE +LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +POSSIBILITY OF SUCH DAMAGE. + +*/ + +#ifndef NRF5340_NETWORK_NAME_CHANGE_H +#define NRF5340_NETWORK_NAME_CHANGE_H + +/*lint ++flb "Enter library region */ + +/* This file is given to prevent your SW from not compiling with the updates made to nrf5340_network.h and + * nrf5340_network_bitfields.h. The macros defined in this file were available previously. Do not use these + * macros on purpose. Use the ones defined in nrf5340_network.h and nrf5340_network_bitfields.h instead. + */ + +/* The serial box interrupt ISRs were renamed. Adding old names as macros. */ +#define SPIM0_SPIS0_TWIM0_TWIS0_UARTE0_IRQHandler SERIAL0_IRQHandler +#define SPIM0_SPIS0_TWIM0_TWIS0_UARTE0_IRQn SERIAL0_IRQn + + /*lint --flb "Leave library region" */ + +#endif /* NRF5340_NETWORK_NAME_CHANGE_H */ diff --git a/mdk/nrf5340_network_peripherals.h b/mdk/nrf5340_network_peripherals.h index 2081d49a2e..1c1e43a3b3 100644 --- a/mdk/nrf5340_network_peripherals.h +++ b/mdk/nrf5340_network_peripherals.h @@ -1,6 +1,8 @@ /* -Copyright (c) 2010 - 2020, Nordic Semiconductor ASA All rights reserved. +Copyright (c) 2010 - 2021, Nordic Semiconductor ASA All rights reserved. + +SPDX-License-Identifier: BSD-3-Clause Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: diff --git a/mdk/nrf53_erratas.h b/mdk/nrf53_erratas.h index dae90e4e62..4efda57785 100644 --- a/mdk/nrf53_erratas.h +++ b/mdk/nrf53_erratas.h @@ -3,7 +3,9 @@ /* -Copyright (c) 2010 - 2020, Nordic Semiconductor ASA All rights reserved. +Copyright (c) 2010 - 2021, Nordic Semiconductor ASA All rights reserved. + +SPDX-License-Identifier: BSD-3-Clause Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: @@ -129,6 +131,7 @@ static bool nrf53_errata_116(void) __UNUSED; static bool nrf53_errata_117(void) __UNUSED; static bool nrf53_errata_119(void) __UNUSED; static bool nrf53_errata_121(void) __UNUSED; +static bool nrf53_errata_122(void) __UNUSED; /* ========= Errata 1 ========= */ #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) @@ -1771,16 +1774,7 @@ static bool nrf53_errata_36(void) } /* ========= Errata 37 ========= */ -#if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) - #if defined(NRF_APPLICATION) || \ - defined(NRF_NETWORK) - #define NRF53_ERRATA_37_PRESENT 1 - #else - #define NRF53_ERRATA_37_PRESENT 0 - #endif -#else - #define NRF53_ERRATA_37_PRESENT 0 -#endif +#define NRF53_ERRATA_37_PRESENT 0 #ifndef NRF53_ERRATA_37_ENABLE_WORKAROUND #define NRF53_ERRATA_37_ENABLE_WORKAROUND NRF53_ERRATA_37_PRESENT @@ -1791,36 +1785,6 @@ static bool nrf53_errata_37(void) #ifndef NRF53_SERIES return false; #else - #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) - #if defined(NRF_APPLICATION) - uint32_t var1 = *(uint32_t *)0x00FF0130ul; - uint32_t var2 = *(uint32_t *)0x00FF0134ul; - #elif defined(NRF_NETWORK) - uint32_t var1 = *(uint32_t *)0x01FF0130ul; - uint32_t var2 = *(uint32_t *)0x01FF0134ul; - #endif - #endif - #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) - #if defined (NRF_APPLICATION)\ - || defined (NRF_NETWORK) - if (var1 == 0x07) - { - switch(var2) - { - case 0x02ul: - return true; - case 0x03ul: - return true; - case 0x04ul: - return true; - case 0x05ul: - return true; - default: - return true; - } - } - #endif - #endif return false; #endif } @@ -2067,11 +2031,11 @@ static bool nrf53_errata_46(void) case 0x03ul: return true; case 0x04ul: - return true; + return false; case 0x05ul: - return true; + return false; default: - return true; + return false; } } #endif @@ -2897,11 +2861,11 @@ static bool nrf53_errata_67(void) case 0x03ul: return true; case 0x04ul: - return true; + return false; case 0x05ul: - return true; + return false; default: - return true; + return false; } } #endif @@ -4136,15 +4100,7 @@ static bool nrf53_errata_99(void) } /* ========= Errata 103 ========= */ -#if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) - #if defined(NRF_NETWORK) - #define NRF53_ERRATA_103_PRESENT 1 - #else - #define NRF53_ERRATA_103_PRESENT 0 - #endif -#else - #define NRF53_ERRATA_103_PRESENT 0 -#endif +#define NRF53_ERRATA_103_PRESENT 0 #ifndef NRF53_ERRATA_103_ENABLE_WORKAROUND #define NRF53_ERRATA_103_ENABLE_WORKAROUND NRF53_ERRATA_103_PRESENT @@ -4155,32 +4111,6 @@ static bool nrf53_errata_103(void) #ifndef NRF53_SERIES return false; #else - #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) - #if defined(NRF_NETWORK) - uint32_t var1 = *(uint32_t *)0x01FF0130ul; - uint32_t var2 = *(uint32_t *)0x01FF0134ul; - #endif - #endif - #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) - #if defined (NRF_NETWORK) - if (var1 == 0x07) - { - switch(var2) - { - case 0x02ul: - return true; - case 0x03ul: - return true; - case 0x04ul: - return true; - case 0x05ul: - return true; - default: - return true; - } - } - #endif - #endif return false; #endif } @@ -4835,4 +4765,54 @@ static bool nrf53_errata_121(void) #endif } +/* ========= Errata 122 ========= */ +#if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_NETWORK) + #define NRF53_ERRATA_122_PRESENT 1 + #else + #define NRF53_ERRATA_122_PRESENT 0 + #endif +#else + #define NRF53_ERRATA_122_PRESENT 0 +#endif + +#ifndef NRF53_ERRATA_122_ENABLE_WORKAROUND + #define NRF53_ERRATA_122_ENABLE_WORKAROUND NRF53_ERRATA_122_PRESENT +#endif + +static bool nrf53_errata_122(void) +{ + #ifndef NRF53_SERIES + return false; + #else + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_NETWORK) + uint32_t var1 = *(uint32_t *)0x01FF0130ul; + uint32_t var2 = *(uint32_t *)0x01FF0134ul; + #endif + #endif + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined (NRF_NETWORK) + if (var1 == 0x07) + { + switch(var2) + { + case 0x02ul: + return false; + case 0x03ul: + return false; + case 0x04ul: + return true; + case 0x05ul: + return true; + default: + return true; + } + } + #endif + #endif + return false; + #endif +} + #endif /* NRF53_ERRATAS_H */ diff --git a/mdk/nrf9160.h b/mdk/nrf9160.h index 1b00430e49..333bc313e2 100644 --- a/mdk/nrf9160.h +++ b/mdk/nrf9160.h @@ -1,5 +1,7 @@ /* - * Copyright (c) 2010 - 2020, Nordic Semiconductor ASA All rights reserved. + * Copyright (c) 2010 - 2021, Nordic Semiconductor ASA All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: @@ -30,10 +32,10 @@ * @file nrf9160.h * @brief CMSIS HeaderFile * @version 1 - * @date 04. November 2020 - * @note Generated by SVDConv V3.3.35 on Wednesday, 04.11.2020 13:48:09 + * @date 29. April 2021 + * @note Generated by SVDConv V3.3.35 on Thursday, 29.04.2021 12:43:58 * from File 'nrf9160.svd', - * last modified on Wednesday, 04.11.2020 12:48:02 + * last modified on Thursday, 29.04.2021 10:43:41 */ diff --git a/mdk/nrf9160.svd b/mdk/nrf9160.svd index c380c6e92a..2e77527d99 100644 --- a/mdk/nrf9160.svd +++ b/mdk/nrf9160.svd @@ -8,7 +8,9 @@ 1 nrf9160 reference description for radio MCU with ARM 32-bit Cortex-M33 Microcontroller -Copyright (c) 2010 - 2020, Nordic Semiconductor ASA All rights reserved.\n +Copyright (c) 2010 - 2021, Nordic Semiconductor ASA All rights reserved.\n +\n +SPDX-License-Identifier: BSD-3-Clause\n \n Redistribution and use in source and binary forms, with or without\n modification, are permitted provided that the following conditions are met:\n diff --git a/mdk/nrf9160_bitfields.h b/mdk/nrf9160_bitfields.h index e26ff169a5..83e7cc2389 100644 --- a/mdk/nrf9160_bitfields.h +++ b/mdk/nrf9160_bitfields.h @@ -1,6 +1,8 @@ /* -Copyright (c) 2010 - 2020, Nordic Semiconductor ASA All rights reserved. +Copyright (c) 2010 - 2021, Nordic Semiconductor ASA All rights reserved. + +SPDX-License-Identifier: BSD-3-Clause Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: diff --git a/mdk/nrf9160_name_change.h b/mdk/nrf9160_name_change.h index d2f6606b92..e3b4dbb72d 100644 --- a/mdk/nrf9160_name_change.h +++ b/mdk/nrf9160_name_change.h @@ -1,6 +1,8 @@ /* -Copyright (c) 2010 - 2020, Nordic Semiconductor ASA All rights reserved. +Copyright (c) 2010 - 2021, Nordic Semiconductor ASA All rights reserved. + +SPDX-License-Identifier: BSD-3-Clause Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: diff --git a/mdk/nrf9160_peripherals.h b/mdk/nrf9160_peripherals.h index 796928e964..18fcd0a773 100644 --- a/mdk/nrf9160_peripherals.h +++ b/mdk/nrf9160_peripherals.h @@ -1,6 +1,8 @@ /* -Copyright (c) 2010 - 2020, Nordic Semiconductor ASA All rights reserved. +Copyright (c) 2010 - 2021, Nordic Semiconductor ASA All rights reserved. + +SPDX-License-Identifier: BSD-3-Clause Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: diff --git a/mdk/nrf91_erratas.h b/mdk/nrf91_erratas.h index 4ca11dfb92..b58d58e08d 100644 --- a/mdk/nrf91_erratas.h +++ b/mdk/nrf91_erratas.h @@ -3,7 +3,9 @@ /* -Copyright (c) 2010 - 2020, Nordic Semiconductor ASA All rights reserved. +Copyright (c) 2010 - 2021, Nordic Semiconductor ASA All rights reserved. + +SPDX-License-Identifier: BSD-3-Clause Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: diff --git a/mdk/nrf_erratas.h b/mdk/nrf_erratas.h index 73a87d7d03..bcf4026bd3 100644 --- a/mdk/nrf_erratas.h +++ b/mdk/nrf_erratas.h @@ -1,6 +1,8 @@ /* -Copyright (c) 2010 - 2020, Nordic Semiconductor ASA All rights reserved. +Copyright (c) 2010 - 2021, Nordic Semiconductor ASA All rights reserved. + +SPDX-License-Identifier: BSD-3-Clause Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: diff --git a/mdk/nrf_peripherals.h b/mdk/nrf_peripherals.h index b99f089502..3f982920df 100644 --- a/mdk/nrf_peripherals.h +++ b/mdk/nrf_peripherals.h @@ -1,6 +1,8 @@ /* -Copyright (c) 2010 - 2020, Nordic Semiconductor ASA All rights reserved. +Copyright (c) 2010 - 2021, Nordic Semiconductor ASA All rights reserved. + +SPDX-License-Identifier: BSD-3-Clause Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: diff --git a/mdk/ses_startup_nrf5340_application.s b/mdk/ses_startup_nrf5340_application.s index 49c9085cea..5f0eadf9d0 100644 --- a/mdk/ses_startup_nrf5340_application.s +++ b/mdk/ses_startup_nrf5340_application.s @@ -163,11 +163,11 @@ _vectors: ISR_HANDLER CLOCK_POWER_IRQHandler ISR_RESERVED_DUMMY /*Reserved */ ISR_RESERVED_DUMMY /*Reserved */ - ISR_HANDLER SPIM0_SPIS0_TWIM0_TWIS0_UARTE0_IRQHandler - ISR_HANDLER SPIM1_SPIS1_TWIM1_TWIS1_UARTE1_IRQHandler + ISR_HANDLER SERIAL0_IRQHandler + ISR_HANDLER SERIAL1_IRQHandler ISR_HANDLER SPIM4_IRQHandler - ISR_HANDLER SPIM2_SPIS2_TWIM2_TWIS2_UARTE2_IRQHandler - ISR_HANDLER SPIM3_SPIS3_TWIM3_TWIS3_UARTE3_IRQHandler + ISR_HANDLER SERIAL2_IRQHandler + ISR_HANDLER SERIAL3_IRQHandler ISR_HANDLER GPIOTE0_IRQHandler ISR_HANDLER SAADC_IRQHandler ISR_HANDLER TIMER0_IRQHandler diff --git a/mdk/ses_startup_nrf5340_network.s b/mdk/ses_startup_nrf5340_network.s index b7846093eb..413d528f52 100644 --- a/mdk/ses_startup_nrf5340_network.s +++ b/mdk/ses_startup_nrf5340_network.s @@ -174,7 +174,7 @@ _vectors: ISR_HANDLER TEMP_IRQHandler ISR_HANDLER RTC0_IRQHandler ISR_HANDLER IPC_IRQHandler - ISR_HANDLER SPIM0_SPIS0_TWIM0_TWIS0_UARTE0_IRQHandler + ISR_HANDLER SERIAL0_IRQHandler ISR_HANDLER EGU0_IRQHandler ISR_RESERVED_DUMMY /*Reserved */ ISR_HANDLER RTC1_IRQHandler diff --git a/mdk/system_nrf.h b/mdk/system_nrf.h index 9cdb88dac8..bbc17985e0 100644 --- a/mdk/system_nrf.h +++ b/mdk/system_nrf.h @@ -1,6 +1,6 @@ /* -Copyright (c) 2009-2020 ARM Limited. All rights reserved. +Copyright (c) 2009-2021 ARM Limited. All rights reserved. SPDX-License-Identifier: Apache-2.0 diff --git a/mdk/system_nrf51.c b/mdk/system_nrf51.c index 98d5d9115f..3c036c8cbd 100644 --- a/mdk/system_nrf51.c +++ b/mdk/system_nrf51.c @@ -1,6 +1,6 @@ /* -Copyright (c) 2009-2020 ARM Limited. All rights reserved. +Copyright (c) 2009-2021 ARM Limited. All rights reserved. SPDX-License-Identifier: Apache-2.0 diff --git a/mdk/system_nrf51.h b/mdk/system_nrf51.h index 100cb74955..9db78f961c 100644 --- a/mdk/system_nrf51.h +++ b/mdk/system_nrf51.h @@ -1,6 +1,6 @@ /* -Copyright (c) 2009-2020 ARM Limited. All rights reserved. +Copyright (c) 2009-2021 ARM Limited. All rights reserved. SPDX-License-Identifier: Apache-2.0 diff --git a/mdk/system_nrf52.c b/mdk/system_nrf52.c index 89d1703f83..c86045fa47 100644 --- a/mdk/system_nrf52.c +++ b/mdk/system_nrf52.c @@ -1,6 +1,6 @@ /* -Copyright (c) 2009-2020 ARM Limited. All rights reserved. +Copyright (c) 2009-2021 ARM Limited. All rights reserved. SPDX-License-Identifier: Apache-2.0 @@ -29,6 +29,7 @@ NOTICE: This file has been modified by Nordic Semiconductor ASA. #include "nrf_peripherals.h" #include "nrf_erratas.h" #include "system_nrf52.h" +#include "system_nrf52_approtect.h" #define __SYSTEM_CLOCK_64M (64000000UL) @@ -268,6 +269,8 @@ void SystemInit(void) __ISB(); #endif + nrf52_handle_approtect(); + /* Configure NFCT pins as GPIOs if NFCT is not to be used in your code. If CONFIG_NFCT_PINS_AS_GPIOS is not defined, two GPIOs (see Product Specification to see which ones) will be reserved for NFC and will not be available as normal GPIOs. */ @@ -301,11 +304,9 @@ void SystemInit(void) make sure NFC pins are mapped as GPIO. */ #if defined (DEVELOP_IN_NRF52832) && defined(NRF52810_XXAA) \ || defined (DEVELOP_IN_NRF52840) && defined(NRF52811_XXAA) - if (((*((uint32_t *)0x10001200) & (1 << 0)) != 0) || ((*((uint32_t *)0x10001204) & (1 << 0)) != 0)){ + if ((*((uint32_t *)0x1000120C) & (1 << 0)) != 0){ nvmc_config(NVMC_CONFIG_WEN_Wen); - *((uint32_t *)0x10001200) = 0; - nvmc_wait(); - *((uint32_t *)0x10001204) = 0; + *((uint32_t *)0x1000120C) = 0; nvmc_wait(); nvmc_config(NVMC_CONFIG_WEN_Ren); NVIC_SystemReset(); diff --git a/mdk/system_nrf52.h b/mdk/system_nrf52.h index df39498ac5..bd3919cb02 100644 --- a/mdk/system_nrf52.h +++ b/mdk/system_nrf52.h @@ -1,6 +1,6 @@ /* -Copyright (c) 2009-2020 ARM Limited. All rights reserved. +Copyright (c) 2009-2021 ARM Limited. All rights reserved. SPDX-License-Identifier: Apache-2.0 diff --git a/mdk/system_nrf52805.c b/mdk/system_nrf52805.c index 7252c02428..cd1ba1b3ae 100644 --- a/mdk/system_nrf52805.c +++ b/mdk/system_nrf52805.c @@ -1,6 +1,8 @@ /* -Copyright (c) 2010 - 2020, Nordic Semiconductor ASA All rights reserved. +Copyright (c) 2010 - 2021, Nordic Semiconductor ASA All rights reserved. + +SPDX-License-Identifier: BSD-3-Clause Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: diff --git a/mdk/system_nrf52805.h b/mdk/system_nrf52805.h index 133c20fcc1..57e0a6bb71 100644 --- a/mdk/system_nrf52805.h +++ b/mdk/system_nrf52805.h @@ -1,6 +1,6 @@ /* -Copyright (c) 2009-2020 ARM Limited. All rights reserved. +Copyright (c) 2009-2021 ARM Limited. All rights reserved. SPDX-License-Identifier: Apache-2.0 diff --git a/mdk/system_nrf52810.c b/mdk/system_nrf52810.c index 7252c02428..cd1ba1b3ae 100644 --- a/mdk/system_nrf52810.c +++ b/mdk/system_nrf52810.c @@ -1,6 +1,8 @@ /* -Copyright (c) 2010 - 2020, Nordic Semiconductor ASA All rights reserved. +Copyright (c) 2010 - 2021, Nordic Semiconductor ASA All rights reserved. + +SPDX-License-Identifier: BSD-3-Clause Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: diff --git a/mdk/system_nrf52810.h b/mdk/system_nrf52810.h index d8c9df883a..8b2958eff9 100644 --- a/mdk/system_nrf52810.h +++ b/mdk/system_nrf52810.h @@ -1,6 +1,6 @@ /* -Copyright (c) 2009-2020 ARM Limited. All rights reserved. +Copyright (c) 2009-2021 ARM Limited. All rights reserved. SPDX-License-Identifier: Apache-2.0 diff --git a/mdk/system_nrf52811.c b/mdk/system_nrf52811.c index 7252c02428..cd1ba1b3ae 100644 --- a/mdk/system_nrf52811.c +++ b/mdk/system_nrf52811.c @@ -1,6 +1,8 @@ /* -Copyright (c) 2010 - 2020, Nordic Semiconductor ASA All rights reserved. +Copyright (c) 2010 - 2021, Nordic Semiconductor ASA All rights reserved. + +SPDX-License-Identifier: BSD-3-Clause Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: diff --git a/mdk/system_nrf52811.h b/mdk/system_nrf52811.h index 2cf256f0b4..6212d0aa4f 100644 --- a/mdk/system_nrf52811.h +++ b/mdk/system_nrf52811.h @@ -1,6 +1,6 @@ /* -Copyright (c) 2009-2020 ARM Limited. All rights reserved. +Copyright (c) 2009-2021 ARM Limited. All rights reserved. SPDX-License-Identifier: Apache-2.0 diff --git a/mdk/system_nrf52820.c b/mdk/system_nrf52820.c index 7252c02428..cd1ba1b3ae 100644 --- a/mdk/system_nrf52820.c +++ b/mdk/system_nrf52820.c @@ -1,6 +1,8 @@ /* -Copyright (c) 2010 - 2020, Nordic Semiconductor ASA All rights reserved. +Copyright (c) 2010 - 2021, Nordic Semiconductor ASA All rights reserved. + +SPDX-License-Identifier: BSD-3-Clause Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: diff --git a/mdk/system_nrf52820.h b/mdk/system_nrf52820.h index a2a326dd19..5b5b77dd27 100644 --- a/mdk/system_nrf52820.h +++ b/mdk/system_nrf52820.h @@ -1,6 +1,6 @@ /* -Copyright (c) 2009-2020 ARM Limited. All rights reserved. +Copyright (c) 2009-2021 ARM Limited. All rights reserved. SPDX-License-Identifier: Apache-2.0 diff --git a/mdk/system_nrf52833.c b/mdk/system_nrf52833.c index 7252c02428..cd1ba1b3ae 100644 --- a/mdk/system_nrf52833.c +++ b/mdk/system_nrf52833.c @@ -1,6 +1,8 @@ /* -Copyright (c) 2010 - 2020, Nordic Semiconductor ASA All rights reserved. +Copyright (c) 2010 - 2021, Nordic Semiconductor ASA All rights reserved. + +SPDX-License-Identifier: BSD-3-Clause Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: diff --git a/mdk/system_nrf52833.h b/mdk/system_nrf52833.h index 3dc83a90bf..342967a84f 100644 --- a/mdk/system_nrf52833.h +++ b/mdk/system_nrf52833.h @@ -1,6 +1,6 @@ /* -Copyright (c) 2009-2020 ARM Limited. All rights reserved. +Copyright (c) 2009-2021 ARM Limited. All rights reserved. SPDX-License-Identifier: Apache-2.0 diff --git a/mdk/system_nrf52840.c b/mdk/system_nrf52840.c index 7252c02428..cd1ba1b3ae 100644 --- a/mdk/system_nrf52840.c +++ b/mdk/system_nrf52840.c @@ -1,6 +1,8 @@ /* -Copyright (c) 2010 - 2020, Nordic Semiconductor ASA All rights reserved. +Copyright (c) 2010 - 2021, Nordic Semiconductor ASA All rights reserved. + +SPDX-License-Identifier: BSD-3-Clause Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: diff --git a/mdk/system_nrf52840.h b/mdk/system_nrf52840.h index dee70679ed..3df49a461f 100644 --- a/mdk/system_nrf52840.h +++ b/mdk/system_nrf52840.h @@ -1,6 +1,6 @@ /* -Copyright (c) 2009-2020 ARM Limited. All rights reserved. +Copyright (c) 2009-2021 ARM Limited. All rights reserved. SPDX-License-Identifier: Apache-2.0 diff --git a/mdk/system_nrf52_approtect.h b/mdk/system_nrf52_approtect.h new file mode 100644 index 0000000000..86a8b65b49 --- /dev/null +++ b/mdk/system_nrf52_approtect.h @@ -0,0 +1,65 @@ +/* + +Copyright (c) 2009-2021 ARM Limited. All rights reserved. + + SPDX-License-Identifier: Apache-2.0 + +Licensed under the Apache License, Version 2.0 (the License); you may +not use this file except in compliance with the License. +You may obtain a copy of the License at + + www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an AS IS BASIS, WITHOUT +WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. + +NOTICE: This file has been modified by Nordic Semiconductor ASA. + +*/ + +#ifndef SYSTEM_NRF52_APPROTECT_H +#define SYSTEM_NRF52_APPROTECT_H + +#include "nrf.h" +#include "nrf_erratas.h" + +#ifdef __cplusplus +extern "C" { +#endif + + +/* Function that handles firmware-driven enabling or disabling of APPROTECT on devices where it is supported. + If ENABLE_APPROTECT is defined, the FW will lock the fw branch of the APPROTECT mechanism, + preventing it from being opened. + Otherwise, the fw branch state is loaded from UICR, emulating the legacy APPROTECT behavior. + + The same mechanism is implemented for SECURE APPROTECT, with the macros + ENABLE_SECURE_APPROTECT and ENABLE_SECURE_APPROTECT_USER_HANDLING. */ +static inline void nrf52_handle_approtect(void) +{ + #if NRF52_ERRATA_249_PRESENT + #if defined (ENABLE_APPROTECT) + if (nrf52_errata_249()) + { + /* Prevent processor from unlocking APPROTECT soft branch after this point. */ + NRF_APPROTECT->FORCEPROTECT = APPROTECT_FORCEPROTECT_FORCEPROTECT_Force; + } + #else + if (nrf52_errata_249()) + { + /* Load APPROTECT soft branch from UICR. + If UICR->APPROTECT is disabled, POWER->APPROTECT will be disabled. */ + NRF_APPROTECT->DISABLE = NRF_UICR->APPROTECT; + } + #endif + #endif +} + +#ifdef __cplusplus +} +#endif + +#endif /* SYSTEM_NRF52_APPROTECT_H */ diff --git a/mdk/system_nrf5340_application.c b/mdk/system_nrf5340_application.c index 1f45282f86..867b0efcc6 100644 --- a/mdk/system_nrf5340_application.c +++ b/mdk/system_nrf5340_application.c @@ -1,6 +1,6 @@ /* -Copyright (c) 2009-2020 ARM Limited. All rights reserved. +Copyright (c) 2009-2021 ARM Limited. All rights reserved. SPDX-License-Identifier: Apache-2.0 @@ -75,7 +75,7 @@ void SystemInit(void) /* Set all ARM SAU regions to NonSecure if TrustZone extensions are enabled. * Nordic SPU should handle Secure Attribution tasks */ #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - SAU->CTRL |= (1 << SAU_CTRL_ALLNS_Pos); + SAU->CTRL |= (1 << SAU_CTRL_ALLNS_Pos); #endif /* Workaround for Errata 97 "ERASEPROTECT, APPROTECT, or startup problems" found at the Errata document @@ -98,7 +98,7 @@ void SystemInit(void) /* IAR will complain about the order of volatile pointer accesses. */ #pragma diag_suppress=Pa082 #endif - *NRF_FICR_S->TRIMCNF[index].ADDR = NRF_FICR_S->TRIMCNF[index].DATA; + *((volatile uint32_t *)NRF_FICR_S->TRIMCNF[index].ADDR) = NRF_FICR_S->TRIMCNF[index].DATA; #if defined ( __ICCARM__ ) #pragma diag_default=Pa082 #endif diff --git a/mdk/system_nrf5340_application.h b/mdk/system_nrf5340_application.h index 5ff93a3090..3d5f24a4ac 100644 --- a/mdk/system_nrf5340_application.h +++ b/mdk/system_nrf5340_application.h @@ -1,6 +1,6 @@ /* -Copyright (c) 2009-2020 ARM Limited. All rights reserved. +Copyright (c) 2009-2021 ARM Limited. All rights reserved. SPDX-License-Identifier: Apache-2.0 diff --git a/mdk/system_nrf5340_network.c b/mdk/system_nrf5340_network.c index df0ee84db9..4688b9753f 100644 --- a/mdk/system_nrf5340_network.c +++ b/mdk/system_nrf5340_network.c @@ -1,6 +1,6 @@ /* -Copyright (c) 2009-2020 ARM Limited. All rights reserved. +Copyright (c) 2009-2021 ARM Limited. All rights reserved. SPDX-License-Identifier: Apache-2.0 @@ -33,7 +33,7 @@ NOTICE: This file has been modified by Nordic Semiconductor ASA. /*lint ++flb "Enter library region" */ -#define __SYSTEM_CLOCK (64000000UL) /*!< NRF5340 network core uses a fixed System Clock Frequency of 32MHz */ +#define __SYSTEM_CLOCK (64000000UL) /*!< NRF5340 network core uses a fixed System Clock Frequency of 64MHz */ #if defined ( __CC_ARM ) uint32_t SystemCoreClock __attribute__((used)) = __SYSTEM_CLOCK; @@ -58,7 +58,7 @@ void SystemInit(void) /* IAR will complain about the order of volatile pointer accesses. */ #pragma diag_suppress=Pa082 #endif - *NRF_FICR_NS->TRIMCNF[index].ADDR = NRF_FICR_NS->TRIMCNF[index].DATA; + *((volatile uint32_t *)NRF_FICR_NS->TRIMCNF[index].ADDR) = NRF_FICR_NS->TRIMCNF[index].DATA; #if defined ( __ICCARM__ ) #pragma diag_default=Pa082 #endif diff --git a/mdk/system_nrf5340_network.h b/mdk/system_nrf5340_network.h index 890f9563e3..ab26179824 100644 --- a/mdk/system_nrf5340_network.h +++ b/mdk/system_nrf5340_network.h @@ -1,6 +1,6 @@ /* -Copyright (c) 2009-2020 ARM Limited. All rights reserved. +Copyright (c) 2009-2021 ARM Limited. All rights reserved. SPDX-License-Identifier: Apache-2.0 diff --git a/mdk/system_nrf53_approtect.h b/mdk/system_nrf53_approtect.h index 7f6db0c946..1863e68d10 100644 --- a/mdk/system_nrf53_approtect.h +++ b/mdk/system_nrf53_approtect.h @@ -1,6 +1,6 @@ /* -Copyright (c) 2009-2020 ARM Limited. All rights reserved. +Copyright (c) 2009-2021 ARM Limited. All rights reserved. SPDX-License-Identifier: Apache-2.0 diff --git a/mdk/system_nrf9160.c b/mdk/system_nrf9160.c index 47b198039b..0363d41fb2 100644 --- a/mdk/system_nrf9160.c +++ b/mdk/system_nrf9160.c @@ -1,6 +1,6 @@ /* -Copyright (c) 2009-2020 ARM Limited. All rights reserved. +Copyright (c) 2009-2021 ARM Limited. All rights reserved. SPDX-License-Identifier: Apache-2.0 diff --git a/mdk/system_nrf9160.h b/mdk/system_nrf9160.h index 4863b126ad..1afad0619b 100644 --- a/mdk/system_nrf9160.h +++ b/mdk/system_nrf9160.h @@ -1,6 +1,6 @@ /* -Copyright (c) 2009-2020 ARM Limited. All rights reserved. +Copyright (c) 2009-2021 ARM Limited. All rights reserved. SPDX-License-Identifier: Apache-2.0 diff --git a/nrfx.h b/nrfx.h index 9783e11a71..e5bda37650 100644 --- a/nrfx.h +++ b/nrfx.h @@ -1,7 +1,9 @@ /* - * Copyright (c) 2017 - 2020, Nordic Semiconductor ASA + * Copyright (c) 2017 - 2021, Nordic Semiconductor ASA * All rights reserved. * + * SPDX-License-Identifier: BSD-3-Clause + * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * diff --git a/soc/nrfx_atomic.c b/soc/nrfx_atomic.c index 60130330d2..af7586c66d 100644 --- a/soc/nrfx_atomic.c +++ b/soc/nrfx_atomic.c @@ -1,7 +1,9 @@ /* - * Copyright (c) 2018 - 2020, Nordic Semiconductor ASA + * Copyright (c) 2018 - 2021, Nordic Semiconductor ASA * All rights reserved. * + * SPDX-License-Identifier: BSD-3-Clause + * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * diff --git a/soc/nrfx_atomic.h b/soc/nrfx_atomic.h index 30d72cc594..aa761dd762 100644 --- a/soc/nrfx_atomic.h +++ b/soc/nrfx_atomic.h @@ -1,7 +1,9 @@ /* - * Copyright (c) 2016 - 2020, Nordic Semiconductor ASA + * Copyright (c) 2016 - 2021, Nordic Semiconductor ASA * All rights reserved. * + * SPDX-License-Identifier: BSD-3-Clause + * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * diff --git a/soc/nrfx_atomic_internal.h b/soc/nrfx_atomic_internal.h index 27e5c99817..349ec119c8 100644 --- a/soc/nrfx_atomic_internal.h +++ b/soc/nrfx_atomic_internal.h @@ -1,7 +1,9 @@ /* - * Copyright (c) 2016 - 2020, Nordic Semiconductor ASA + * Copyright (c) 2016 - 2021, Nordic Semiconductor ASA * All rights reserved. * + * SPDX-License-Identifier: BSD-3-Clause + * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * diff --git a/soc/nrfx_coredep.h b/soc/nrfx_coredep.h index 15bb9f3b66..f597d8bfb8 100644 --- a/soc/nrfx_coredep.h +++ b/soc/nrfx_coredep.h @@ -1,7 +1,9 @@ /* - * Copyright (c) 2018 - 2020, Nordic Semiconductor ASA + * Copyright (c) 2018 - 2021, Nordic Semiconductor ASA * All rights reserved. * + * SPDX-License-Identifier: BSD-3-Clause + * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * diff --git a/soc/nrfx_irqs.h b/soc/nrfx_irqs.h index b3d833351d..43591c8b02 100644 --- a/soc/nrfx_irqs.h +++ b/soc/nrfx_irqs.h @@ -1,7 +1,9 @@ /* - * Copyright (c) 2017 - 2020, Nordic Semiconductor ASA + * Copyright (c) 2017 - 2021, Nordic Semiconductor ASA * All rights reserved. * + * SPDX-License-Identifier: BSD-3-Clause + * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * diff --git a/soc/nrfx_irqs_nrf51.h b/soc/nrfx_irqs_nrf51.h index 96647ff759..9375140f41 100644 --- a/soc/nrfx_irqs_nrf51.h +++ b/soc/nrfx_irqs_nrf51.h @@ -1,7 +1,9 @@ /* - * Copyright (c) 2017 - 2020, Nordic Semiconductor ASA + * Copyright (c) 2017 - 2021, Nordic Semiconductor ASA * All rights reserved. * + * SPDX-License-Identifier: BSD-3-Clause + * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * diff --git a/soc/nrfx_irqs_nrf52805.h b/soc/nrfx_irqs_nrf52805.h index fbbd0a9011..e549296f4e 100644 --- a/soc/nrfx_irqs_nrf52805.h +++ b/soc/nrfx_irqs_nrf52805.h @@ -1,7 +1,9 @@ /* - * Copyright (c) 2020, Nordic Semiconductor ASA + * Copyright (c) 2020 - 2021, Nordic Semiconductor ASA * All rights reserved. * + * SPDX-License-Identifier: BSD-3-Clause + * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * diff --git a/soc/nrfx_irqs_nrf52810.h b/soc/nrfx_irqs_nrf52810.h index 4f5990a512..124edc5d52 100644 --- a/soc/nrfx_irqs_nrf52810.h +++ b/soc/nrfx_irqs_nrf52810.h @@ -1,7 +1,9 @@ /* - * Copyright (c) 2017 - 2020, Nordic Semiconductor ASA + * Copyright (c) 2017 - 2021, Nordic Semiconductor ASA * All rights reserved. * + * SPDX-License-Identifier: BSD-3-Clause + * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * diff --git a/soc/nrfx_irqs_nrf52811.h b/soc/nrfx_irqs_nrf52811.h index a43c7c2a87..1956286d9b 100644 --- a/soc/nrfx_irqs_nrf52811.h +++ b/soc/nrfx_irqs_nrf52811.h @@ -1,7 +1,9 @@ /* - * Copyright (c) 2017 - 2020, Nordic Semiconductor ASA + * Copyright (c) 2017 - 2021, Nordic Semiconductor ASA * All rights reserved. * + * SPDX-License-Identifier: BSD-3-Clause + * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * diff --git a/soc/nrfx_irqs_nrf52820.h b/soc/nrfx_irqs_nrf52820.h index 7c002eb4f3..b4f3a4ff89 100644 --- a/soc/nrfx_irqs_nrf52820.h +++ b/soc/nrfx_irqs_nrf52820.h @@ -1,7 +1,9 @@ /* - * Copyright (c) 2020, Nordic Semiconductor ASA + * Copyright (c) 2020 - 2021, Nordic Semiconductor ASA * All rights reserved. * + * SPDX-License-Identifier: BSD-3-Clause + * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * diff --git a/soc/nrfx_irqs_nrf52832.h b/soc/nrfx_irqs_nrf52832.h index 310498ef65..def1ea3ea7 100644 --- a/soc/nrfx_irqs_nrf52832.h +++ b/soc/nrfx_irqs_nrf52832.h @@ -1,7 +1,9 @@ /* - * Copyright (c) 2017 - 2020, Nordic Semiconductor ASA + * Copyright (c) 2017 - 2021, Nordic Semiconductor ASA * All rights reserved. * + * SPDX-License-Identifier: BSD-3-Clause + * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * diff --git a/soc/nrfx_irqs_nrf52833.h b/soc/nrfx_irqs_nrf52833.h index 32944bc7de..ab21966ad5 100644 --- a/soc/nrfx_irqs_nrf52833.h +++ b/soc/nrfx_irqs_nrf52833.h @@ -1,7 +1,9 @@ /* - * Copyright (c) 2019 - 2020, Nordic Semiconductor ASA + * Copyright (c) 2019 - 2021, Nordic Semiconductor ASA * All rights reserved. * + * SPDX-License-Identifier: BSD-3-Clause + * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * diff --git a/soc/nrfx_irqs_nrf52840.h b/soc/nrfx_irqs_nrf52840.h index 1f85026b7c..16f6fd7076 100644 --- a/soc/nrfx_irqs_nrf52840.h +++ b/soc/nrfx_irqs_nrf52840.h @@ -1,7 +1,9 @@ /* - * Copyright (c) 2017 - 2020, Nordic Semiconductor ASA + * Copyright (c) 2017 - 2021, Nordic Semiconductor ASA * All rights reserved. * + * SPDX-License-Identifier: BSD-3-Clause + * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * diff --git a/soc/nrfx_irqs_nrf5340_application.h b/soc/nrfx_irqs_nrf5340_application.h index 15d1e2504b..5493191317 100644 --- a/soc/nrfx_irqs_nrf5340_application.h +++ b/soc/nrfx_irqs_nrf5340_application.h @@ -1,7 +1,9 @@ /* - * Copyright (c) 2019 - 2020, Nordic Semiconductor ASA + * Copyright (c) 2019 - 2021, Nordic Semiconductor ASA * All rights reserved. * + * SPDX-License-Identifier: BSD-3-Clause + * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * @@ -45,51 +47,51 @@ extern "C" { // CLOCK_POWER_IRQn #define nrfx_power_clock_irq_handler CLOCK_POWER_IRQHandler -// SPIM0_SPIS0_TWIM0_TWIS0_UARTE0_IRQn +// SERIAL0_IRQn #if NRFX_CHECK(NRFX_PRS_ENABLED) && NRFX_CHECK(NRFX_PRS_BOX_0_ENABLED) -#define nrfx_prs_box_0_irq_handler SPIM0_SPIS0_TWIM0_TWIS0_UARTE0_IRQHandler +#define nrfx_prs_box_0_irq_handler SERIAL0_IRQHandler #else -#define nrfx_spim_0_irq_handler SPIM0_SPIS0_TWIM0_TWIS0_UARTE0_IRQHandler -#define nrfx_spis_0_irq_handler SPIM0_SPIS0_TWIM0_TWIS0_UARTE0_IRQHandler -#define nrfx_twim_0_irq_handler SPIM0_SPIS0_TWIM0_TWIS0_UARTE0_IRQHandler -#define nrfx_twis_0_irq_handler SPIM0_SPIS0_TWIM0_TWIS0_UARTE0_IRQHandler -#define nrfx_uarte_0_irq_handler SPIM0_SPIS0_TWIM0_TWIS0_UARTE0_IRQHandler +#define nrfx_spim_0_irq_handler SERIAL0_IRQHandler +#define nrfx_spis_0_irq_handler SERIAL0_IRQHandler +#define nrfx_twim_0_irq_handler SERIAL0_IRQHandler +#define nrfx_twis_0_irq_handler SERIAL0_IRQHandler +#define nrfx_uarte_0_irq_handler SERIAL0_IRQHandler #endif -// SPIM1_SPIS1_TWIM1_TWIS1_UARTE1_IRQn +// SERIAL1_IRQn #if NRFX_CHECK(NRFX_PRS_ENABLED) && NRFX_CHECK(NRFX_PRS_BOX_1_ENABLED) -#define nrfx_prs_box_1_irq_handler SPIM1_SPIS1_TWIM1_TWIS1_UARTE1_IRQHandler +#define nrfx_prs_box_1_irq_handler SERIAL1_IRQHandler #else -#define nrfx_spim_1_irq_handler SPIM1_SPIS1_TWIM1_TWIS1_UARTE1_IRQHandler -#define nrfx_spis_1_irq_handler SPIM1_SPIS1_TWIM1_TWIS1_UARTE1_IRQHandler -#define nrfx_twim_1_irq_handler SPIM1_SPIS1_TWIM1_TWIS1_UARTE1_IRQHandler -#define nrfx_twis_1_irq_handler SPIM1_SPIS1_TWIM1_TWIS1_UARTE1_IRQHandler -#define nrfx_uarte_1_irq_handler SPIM1_SPIS1_TWIM1_TWIS1_UARTE1_IRQHandler +#define nrfx_spim_1_irq_handler SERIAL1_IRQHandler +#define nrfx_spis_1_irq_handler SERIAL1_IRQHandler +#define nrfx_twim_1_irq_handler SERIAL1_IRQHandler +#define nrfx_twis_1_irq_handler SERIAL1_IRQHandler +#define nrfx_uarte_1_irq_handler SERIAL1_IRQHandler #endif // SPIM4_IRQn #define nrfx_spim_4_irq_handler SPIM4_IRQHandler -// SPIM2_SPIS2_TWIM2_TWIS2_UARTE2_IRQn +// SERIAL2_IRQn #if NRFX_CHECK(NRFX_PRS_ENABLED) && NRFX_CHECK(NRFX_PRS_BOX_2_ENABLED) -#define nrfx_prs_box_2_irq_handler SPIM2_SPIS2_TWIM2_TWIS2_UARTE2_IRQHandler +#define nrfx_prs_box_2_irq_handler SERIAL2_IRQHandler #else -#define nrfx_spim_2_irq_handler SPIM2_SPIS2_TWIM2_TWIS2_UARTE2_IRQHandler -#define nrfx_spis_2_irq_handler SPIM2_SPIS2_TWIM2_TWIS2_UARTE2_IRQHandler -#define nrfx_twim_2_irq_handler SPIM2_SPIS2_TWIM2_TWIS2_UARTE2_IRQHandler -#define nrfx_twis_2_irq_handler SPIM2_SPIS2_TWIM2_TWIS2_UARTE2_IRQHandler -#define nrfx_uarte_2_irq_handler SPIM2_SPIS2_TWIM2_TWIS2_UARTE2_IRQHandler +#define nrfx_spim_2_irq_handler SERIAL2_IRQHandler +#define nrfx_spis_2_irq_handler SERIAL2_IRQHandler +#define nrfx_twim_2_irq_handler SERIAL2_IRQHandler +#define nrfx_twis_2_irq_handler SERIAL2_IRQHandler +#define nrfx_uarte_2_irq_handler SERIAL2_IRQHandler #endif -// SPIM3_SPIS3_TWIM3_TWIS3_UARTE3_IRQn +// SERIAL3_IRQn #if NRFX_CHECK(NRFX_PRS_ENABLED) && NRFX_CHECK(NRFX_PRS_BOX_3_ENABLED) -#define nrfx_prs_box_3_irq_handler SPIM3_SPIS3_TWIM3_TWIS3_UARTE3_IRQHandler +#define nrfx_prs_box_3_irq_handler SERIAL3_IRQHandler #else -#define nrfx_spim_3_irq_handler SPIM3_SPIS3_TWIM3_TWIS3_UARTE3_IRQHandler -#define nrfx_spis_3_irq_handler SPIM3_SPIS3_TWIM3_TWIS3_UARTE3_IRQHandler -#define nrfx_twim_3_irq_handler SPIM3_SPIS3_TWIM3_TWIS3_UARTE3_IRQHandler -#define nrfx_twis_3_irq_handler SPIM3_SPIS3_TWIM3_TWIS3_UARTE3_IRQHandler -#define nrfx_uarte_3_irq_handler SPIM3_SPIS3_TWIM3_TWIS3_UARTE3_IRQHandler +#define nrfx_spim_3_irq_handler SERIAL3_IRQHandler +#define nrfx_spis_3_irq_handler SERIAL3_IRQHandler +#define nrfx_twim_3_irq_handler SERIAL3_IRQHandler +#define nrfx_twis_3_irq_handler SERIAL3_IRQHandler +#define nrfx_uarte_3_irq_handler SERIAL3_IRQHandler #endif // GPIOTE0_IRQn diff --git a/soc/nrfx_irqs_nrf5340_network.h b/soc/nrfx_irqs_nrf5340_network.h index db2c395d19..8f8925305b 100644 --- a/soc/nrfx_irqs_nrf5340_network.h +++ b/soc/nrfx_irqs_nrf5340_network.h @@ -1,7 +1,9 @@ /* - * Copyright (c) 2019 - 2020, Nordic Semiconductor ASA + * Copyright (c) 2019 - 2021, Nordic Semiconductor ASA * All rights reserved. * + * SPDX-License-Identifier: BSD-3-Clause + * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * @@ -66,15 +68,15 @@ extern "C" { // IPC_IRQn #define nrfx_ipc_irq_handler IPC_IRQHandler -// SPIM0_SPIS0_TWIM0_TWIS0_UARTE0_IRQn +// SERIAL0_IRQn #if NRFX_CHECK(NRFX_PRS_ENABLED) && NRFX_CHECK(NRFX_PRS_BOX_0_ENABLED) -#define nrfx_prs_box_0_irq_handler SPIM0_SPIS0_TWIM0_TWIS0_UARTE0_IRQHandler +#define nrfx_prs_box_0_irq_handler SERIAL0_IRQHandler #else -#define nrfx_spim_0_irq_handler SPIM0_SPIS0_TWIM0_TWIS0_UARTE0_IRQHandler -#define nrfx_spis_0_irq_handler SPIM0_SPIS0_TWIM0_TWIS0_UARTE0_IRQHandler -#define nrfx_twim_0_irq_handler SPIM0_SPIS0_TWIM0_TWIS0_UARTE0_IRQHandler -#define nrfx_twis_0_irq_handler SPIM0_SPIS0_TWIM0_TWIS0_UARTE0_IRQHandler -#define nrfx_uarte_0_irq_handler SPIM0_SPIS0_TWIM0_TWIS0_UARTE0_IRQHandler +#define nrfx_spim_0_irq_handler SERIAL0_IRQHandler +#define nrfx_spis_0_irq_handler SERIAL0_IRQHandler +#define nrfx_twim_0_irq_handler SERIAL0_IRQHandler +#define nrfx_twis_0_irq_handler SERIAL0_IRQHandler +#define nrfx_uarte_0_irq_handler SERIAL0_IRQHandler #endif // EGU0_IRQn diff --git a/soc/nrfx_irqs_nrf9160.h b/soc/nrfx_irqs_nrf9160.h index dab9878c31..f25f664312 100644 --- a/soc/nrfx_irqs_nrf9160.h +++ b/soc/nrfx_irqs_nrf9160.h @@ -1,7 +1,9 @@ /* - * Copyright (c) 2018 - 2020, Nordic Semiconductor ASA + * Copyright (c) 2018 - 2021, Nordic Semiconductor ASA * All rights reserved. * + * SPDX-License-Identifier: BSD-3-Clause + * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * diff --git a/templates/nrfx_config.h b/templates/nrfx_config.h index 520bbb0c59..dccf675dca 100644 --- a/templates/nrfx_config.h +++ b/templates/nrfx_config.h @@ -1,7 +1,9 @@ /* - * Copyright (c) 2019 - 2020, Nordic Semiconductor ASA + * Copyright (c) 2019 - 2021, Nordic Semiconductor ASA * All rights reserved. * + * SPDX-License-Identifier: BSD-3-Clause + * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * diff --git a/templates/nrfx_config_nrf51.h b/templates/nrfx_config_nrf51.h index 5f0e45cf5d..d3099a81ab 100644 --- a/templates/nrfx_config_nrf51.h +++ b/templates/nrfx_config_nrf51.h @@ -1,7 +1,9 @@ /* - * Copyright (c) 2017 - 2020, Nordic Semiconductor ASA + * Copyright (c) 2017 - 2021, Nordic Semiconductor ASA * All rights reserved. * + * SPDX-License-Identifier: BSD-3-Clause + * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * diff --git a/templates/nrfx_config_nrf52805.h b/templates/nrfx_config_nrf52805.h index 290e468ac8..9ccb5bcbd3 100644 --- a/templates/nrfx_config_nrf52805.h +++ b/templates/nrfx_config_nrf52805.h @@ -1,7 +1,9 @@ /* - * Copyright (c) 2020, Nordic Semiconductor ASA + * Copyright (c) 2020 - 2021, Nordic Semiconductor ASA * All rights reserved. * + * SPDX-License-Identifier: BSD-3-Clause + * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * diff --git a/templates/nrfx_config_nrf52810.h b/templates/nrfx_config_nrf52810.h index cd7015115c..c23a8b1a01 100644 --- a/templates/nrfx_config_nrf52810.h +++ b/templates/nrfx_config_nrf52810.h @@ -1,7 +1,9 @@ /* - * Copyright (c) 2017 - 2020, Nordic Semiconductor ASA + * Copyright (c) 2017 - 2021, Nordic Semiconductor ASA * All rights reserved. * + * SPDX-License-Identifier: BSD-3-Clause + * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * diff --git a/templates/nrfx_config_nrf52811.h b/templates/nrfx_config_nrf52811.h index 43e1bbd3a4..fcc4ef3a8d 100644 --- a/templates/nrfx_config_nrf52811.h +++ b/templates/nrfx_config_nrf52811.h @@ -1,7 +1,9 @@ /* - * Copyright (c) 2018 - 2020, Nordic Semiconductor ASA + * Copyright (c) 2018 - 2021, Nordic Semiconductor ASA * All rights reserved. * + * SPDX-License-Identifier: BSD-3-Clause + * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * diff --git a/templates/nrfx_config_nrf52820.h b/templates/nrfx_config_nrf52820.h index f22a2145b1..0dcf0af050 100644 --- a/templates/nrfx_config_nrf52820.h +++ b/templates/nrfx_config_nrf52820.h @@ -1,7 +1,9 @@ /* - * Copyright (c) 2020, Nordic Semiconductor ASA + * Copyright (c) 2020 - 2021, Nordic Semiconductor ASA * All rights reserved. * + * SPDX-License-Identifier: BSD-3-Clause + * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * diff --git a/templates/nrfx_config_nrf52832.h b/templates/nrfx_config_nrf52832.h index e266d12454..2ebe2f5160 100644 --- a/templates/nrfx_config_nrf52832.h +++ b/templates/nrfx_config_nrf52832.h @@ -1,7 +1,9 @@ /* - * Copyright (c) 2017 - 2020, Nordic Semiconductor ASA + * Copyright (c) 2017 - 2021, Nordic Semiconductor ASA * All rights reserved. * + * SPDX-License-Identifier: BSD-3-Clause + * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * diff --git a/templates/nrfx_config_nrf52833.h b/templates/nrfx_config_nrf52833.h index da93dcf2cf..1b65157eb3 100644 --- a/templates/nrfx_config_nrf52833.h +++ b/templates/nrfx_config_nrf52833.h @@ -1,7 +1,9 @@ /* - * Copyright (c) 2019 - 2020, Nordic Semiconductor ASA + * Copyright (c) 2019 - 2021, Nordic Semiconductor ASA * All rights reserved. * + * SPDX-License-Identifier: BSD-3-Clause + * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * diff --git a/templates/nrfx_config_nrf52840.h b/templates/nrfx_config_nrf52840.h index 75a2648518..682aead829 100644 --- a/templates/nrfx_config_nrf52840.h +++ b/templates/nrfx_config_nrf52840.h @@ -1,7 +1,9 @@ /* - * Copyright (c) 2017 - 2020, Nordic Semiconductor ASA + * Copyright (c) 2017 - 2021, Nordic Semiconductor ASA * All rights reserved. * + * SPDX-License-Identifier: BSD-3-Clause + * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * diff --git a/templates/nrfx_config_nrf5340_application.h b/templates/nrfx_config_nrf5340_application.h index a93d1d25cd..1a5ab391a4 100644 --- a/templates/nrfx_config_nrf5340_application.h +++ b/templates/nrfx_config_nrf5340_application.h @@ -1,7 +1,9 @@ /* - * Copyright (c) 2019 - 2020, Nordic Semiconductor ASA + * Copyright (c) 2019 - 2021, Nordic Semiconductor ASA * All rights reserved. * + * SPDX-License-Identifier: BSD-3-Clause + * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * diff --git a/templates/nrfx_config_nrf5340_network.h b/templates/nrfx_config_nrf5340_network.h index 1a6489c5a2..9d07ba6697 100644 --- a/templates/nrfx_config_nrf5340_network.h +++ b/templates/nrfx_config_nrf5340_network.h @@ -1,7 +1,9 @@ /* - * Copyright (c) 2019 - 2020, Nordic Semiconductor ASA + * Copyright (c) 2019 - 2021, Nordic Semiconductor ASA * All rights reserved. * + * SPDX-License-Identifier: BSD-3-Clause + * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * diff --git a/templates/nrfx_config_nrf9160.h b/templates/nrfx_config_nrf9160.h index 4ab38dedc9..64b7cbc4d0 100644 --- a/templates/nrfx_config_nrf9160.h +++ b/templates/nrfx_config_nrf9160.h @@ -1,7 +1,9 @@ /* - * Copyright (c) 2018 - 2020, Nordic Semiconductor ASA + * Copyright (c) 2018 - 2021, Nordic Semiconductor ASA * All rights reserved. * + * SPDX-License-Identifier: BSD-3-Clause + * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * diff --git a/templates/nrfx_glue.h b/templates/nrfx_glue.h index 87cf9ef439..57f46ecb9b 100644 --- a/templates/nrfx_glue.h +++ b/templates/nrfx_glue.h @@ -1,7 +1,9 @@ /* - * Copyright (c) 2017 - 2020, Nordic Semiconductor ASA + * Copyright (c) 2017 - 2021, Nordic Semiconductor ASA * All rights reserved. * + * SPDX-License-Identifier: BSD-3-Clause + * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * diff --git a/templates/nrfx_log.h b/templates/nrfx_log.h index 80d8efbdf1..cbbb2f9eb4 100644 --- a/templates/nrfx_log.h +++ b/templates/nrfx_log.h @@ -1,7 +1,9 @@ /* - * Copyright (c) 2017 - 2020, Nordic Semiconductor ASA + * Copyright (c) 2017 - 2021, Nordic Semiconductor ASA * All rights reserved. * + * SPDX-License-Identifier: BSD-3-Clause + * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: *