diff --git a/CHANGELOG.md b/CHANGELOG.md index 4407d0e1d9..d9134fd1fd 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -1,6 +1,30 @@ # Changelog All notable changes to this project are documented in this file. +## [2.3.0] - 2020-08-19 +### Added +- Added support for nRF52805. +- Implemented workaround for nRF52 Series anomaly 197 in the POWER HAL. +- Implemented workaround for nRF52 Series anomalies 211 and 223 in the USBD driver. +- Added support for the nRF53 Series in the QSPI HAL. +- Added function in the GPIO HAL that returns port index. +- Introduced a QSPI HAL symbol that indicates the availability of the QSPI mode 1. +- Introduced shortcut functionality in the CCM HAL. +- Added function in the TIMER HAL for setting the specified shortcuts. +- Added optional two-stage start procedure of the LFXO in the CLOCK driver. + +### Changed +- Updated MDK to 8.35.0. +- Divided network and application core-specific functionalities for nRF5340 in the RESET HAL and the reset reason helper. + +### Fixed +- Corrected assertions in the NVMC driver. +- Corrected return types in the CCM HAL. +- Fixed setting of program memory access mode for secure code in the NVMC driver. +- Removed usage of the NRF_UICR symbol on non-secure targets in address validity checks in the NVMC driver. +- Fixed an error message in the SPIM driver that prevented successful compilation with logging enabled. +- Fixed unused parameters in the PPI HAL. + ## [2.2.0] - 2020-04-28 ### Added - Added support for nRF52820. diff --git a/README.md b/README.md index 3c28f87822..0772a3fac4 100644 --- a/README.md +++ b/README.md @@ -13,6 +13,7 @@ SoCs, as well as startup and initialization files for them. ## Supported SoCs * nRF51 Series +* nRF52805 * nRF52810 * nRF52811 * nRF52820 diff --git a/doc/drv_supp_matrix.dox b/doc/drv_supp_matrix.dox index dcb30dd92d..ea2f1e5193 100644 --- a/doc/drv_supp_matrix.dox +++ b/doc/drv_supp_matrix.dox @@ -1,61 +1,82 @@ /** -@page nrfx_drv_supp_matrix Driver support matrix -The following matrix shows which drivers are supported by specific Nordic SoCs. -@{ - -Driver | nRF51 Series | nRF52810/nRF52811 | nRF52820 | nRF52832 | nRF52833 | nRF52840 | nRF5340 | nRF9160 | ------------------|--------------|-------------------|--------------| -------------| -------------| -------------| -------------| -------------| -@ref nrf_aar |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagRedCross | -@ref nrf_acl |@tagRedCross |@tagRedCross |@tagGreenTick |@tagRedCross |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagRedCross | -@ref nrf_adc |@tagGreenTick |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross | -@ref nrf_bprot |@tagRedCross |@tagGreenTick |@tagRedCross |@tagGreenTick |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross | -@ref nrf_cache |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagGreenTick |@tagRedCross | -@ref nrf_ccm |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagRedCross | -@ref nrf_clock |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick | -@ref nrf_comp |@tagRedCross |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagRedCross | -@ref nrf_systick |@tagRedCross |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick | -@ref nrf_dcnf |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagGreenTick |@tagRedCross | -@ref nrf_dppi |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagGreenTick |@tagGreenTick | -@ref nrf_ecb |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagRedCross | -@ref nrf_egu |@tagRedCross |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick | -@ref nrf_ficr |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick | -@ref nrf_fpu |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagGreenTick |@tagRedCross | -@ref nrf_gpio |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick | -@ref nrf_gpiote |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick | -@ref nrf_i2s |@tagRedCross |@tagRedCross |@tagRedCross |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick | -@ref nrf_ipc |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagGreenTick |@tagGreenTick | -@ref nrf_kmu |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagGreenTick |@tagGreenTick | -@ref nrf_lpcomp |@tagGreenTick |@tagRedCross |@tagRedCross |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagRedCross | -@ref nrf_mpu |@tagGreenTick |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross | -@ref nrf_mutex |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagGreenTick |@tagRedCross | -@ref nrf_mwu |@tagRedCross |@tagRedCross |@tagRedCross |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagRedCross |@tagRedCross | -@ref nrf_nfct |@tagRedCross |@tagRedCross |@tagRedCross |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagRedCross | -@ref nrf_nvmc |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick | -@ref nrf_pdm |@tagRedCross |@tagGreenTick |@tagRedCross |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick | -@ref nrf_power |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick | -@ref nrf_ppi |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagRedCross |@tagRedCross | -@ref nrf_pwm |@tagRedCross |@tagGreenTick |@tagRedCross |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick | -@ref nrf_qdec |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagRedCross | -@ref nrf_qspi |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagGreenTick |@tagGreenTick |@tagRedCross | -@ref nrf_radio |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagRedCross | -@ref nrf_reset |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagGreenTick |@tagRedCross | -@ref nrf_rng |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagRedCross | -@ref nrf_rtc |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick | -@ref nrf_saadc |@tagRedCross |@tagGreenTick |@tagRedCross |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick | -@ref nrf_spi |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagRedCross |@tagRedCross | -@ref nrf_spim |@tagRedCross |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick | -@ref nrf_spis |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick | -@ref nrf_spu |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagGreenTick |@tagGreenTick | -@ref nrf_temp |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagRedCross | -@ref nrf_timer |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick | -@ref nrf_twi |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagRedCross |@tagRedCross | -@ref nrf_twim |@tagRedCross |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick | -@ref nrf_twis |@tagRedCross |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick | -@ref nrf_uart |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagRedCross |@tagRedCross | -@ref nrf_uarte |@tagRedCross |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick | -@ref nrf_usbd |@tagRedCross |@tagRedCross |@tagGreenTick |@tagRedCross |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagRedCross | -@ref nrf_vmc |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagGreenTick |@tagGreenTick | -@ref nrf_wdt |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick | - -@} +@page nrfx_drv_supp_matrix Driver support overview + +This page lists nrfx driver components supported by each SoC: +- @ref nrfx_drv_supp_matrix_table "Driver support matrix" +- @ref nrfx_drv_supp_matrix_list "Driver support lists" + +@anchor nrfx_drv_supp_matrix_table +@par Driver support matrix + +The following matrix provides a comparative overview of which drivers are supported by specific Nordic SoCs. + +| Driver | nRF51 Series | nRF52805 | nRF52810/nRF52811 | nRF52820 | nRF52832 | nRF52833 | nRF52840 | nRF5340 | nRF9160 | +|------------------|--------------|--------------|-------------------|--------------|--------------|--------------|--------------|--------------|--------------| +| @ref nrf_aar |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagRedCross | +| @ref nrf_acl |@tagRedCross |@tagRedCross |@tagRedCross |@tagGreenTick |@tagRedCross |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagRedCross | +| @ref nrf_adc |@tagGreenTick |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross | +| @ref nrf_bprot |@tagRedCross |@tagGreenTick |@tagGreenTick |@tagRedCross |@tagGreenTick |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross | +| @ref nrf_cache |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagGreenTick |@tagRedCross | +| @ref nrf_ccm |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagRedCross | +| @ref nrf_clock |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick | +| @ref nrf_comp |@tagRedCross |@tagRedCross |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagRedCross | +| @ref nrf_systick |@tagRedCross |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick | +| @ref nrf_dcnf |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagGreenTick |@tagRedCross | +| @ref nrf_dppi |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagGreenTick |@tagGreenTick | +| @ref nrf_ecb |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagRedCross | +| @ref nrf_egu |@tagRedCross |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick | +| @ref nrf_ficr |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick | +| @ref nrf_fpu |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagGreenTick |@tagRedCross | +| @ref nrf_gpio |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick | +| @ref nrf_gpiote |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick | +| @ref nrf_i2s |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick | +| @ref nrf_ipc |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagGreenTick |@tagGreenTick | +| @ref nrf_kmu |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagGreenTick |@tagGreenTick | +| @ref nrf_lpcomp |@tagGreenTick |@tagRedCross |@tagRedCross |@tagRedCross |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagRedCross | +| @ref nrf_mpu |@tagGreenTick |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross | +| @ref nrf_mutex |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagGreenTick |@tagRedCross | +| @ref nrf_mwu |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagRedCross |@tagRedCross | +| @ref nrf_nfct |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagRedCross | +| @ref nrf_nvmc |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick | +| @ref nrf_pdm |@tagRedCross |@tagRedCross |@tagGreenTick |@tagRedCross |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick | +| @ref nrf_power |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick | +| @ref nrf_ppi |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagRedCross |@tagRedCross | +| @ref nrf_pwm |@tagRedCross |@tagRedCross |@tagGreenTick |@tagRedCross |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick | +| @ref nrf_qdec |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagRedCross | +| @ref nrf_qspi |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagGreenTick |@tagGreenTick |@tagRedCross | +| @ref nrf_radio |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagRedCross | +| @ref nrf_reset |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagGreenTick |@tagRedCross | +| @ref nrf_rng |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagRedCross | +| @ref nrf_rtc |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick | +| @ref nrf_saadc |@tagRedCross |@tagGreenTick |@tagGreenTick |@tagRedCross |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick | +| @ref nrf_spi |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagRedCross |@tagRedCross | +| @ref nrf_spim |@tagRedCross |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick | +| @ref nrf_spis |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick | +| @ref nrf_spu |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagGreenTick |@tagGreenTick | +| @ref nrf_temp |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagRedCross | +| @ref nrf_timer |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick | +| @ref nrf_twi |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagRedCross |@tagRedCross | +| @ref nrf_twim |@tagRedCross |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick | +| @ref nrf_twis |@tagRedCross |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick | +| @ref nrf_uart |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagRedCross |@tagRedCross | +| @ref nrf_uarte |@tagRedCross |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick | +| @ref nrf_usbd |@tagRedCross |@tagRedCross |@tagRedCross |@tagGreenTick |@tagRedCross |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagRedCross | +| @ref nrf_vmc |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagRedCross |@tagGreenTick |@tagGreenTick | +| @ref nrf_wdt |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick | + +@anchor nrfx_drv_supp_matrix_list +@par Driver support lists + +The following pages list supported drivers by SoC: + +- @subpage nrf51_series_drivers +- @subpage nrf52805_drivers +- @subpage nrf52810_drivers +- @subpage nrf52820_drivers +- @subpage nrf52832_drivers +- @subpage nrf52833_drivers +- @subpage nrf52840_drivers +- @subpage nrf5340_drivers +- @subpage nrf9160_drivers + */ diff --git a/doc/main_page.dox b/doc/main_page.dox index f2232d0aef..72c2a79242 100644 --- a/doc/main_page.dox +++ b/doc/main_page.dox @@ -1,7 +1,7 @@ /** -@mainpage Introduction +@mainpage Introduction and configuration -@em nrfx is a standalone set of drivers for peripherals present in Nordic +nrfx is a standalone set of drivers for peripherals present in Nordic Semiconductor's SoCs. It originated as an extract from the nRF5 SDK. The intention was to provide drivers that can be used in various environments without the necessity to integrate other parts of the SDK into them. @@ -14,7 +14,7 @@ for a given SoC. @section nrfx_integration Integration -The purpose of @em nrfx is to make it possible to use the same set of peripheral +The purpose of nrfx is to make it possible to use the same set of peripheral drivers in various environments, from RTOSes to bare metal applications. Hence, for a given host environment, a light integration layer must be provided that implements certain specific routines, like interrupt management, critical @@ -30,7 +30,7 @@ versions can be placed in any location within the host environment that the used compiler can access via include paths. In addition, the following locations should be specified as include paths -([nrfx] stands for the @em nrfx root folder location): +([nrfx] stands for the nrfx root folder location): @code [nrfx]/ [nrfx]/drivers/include @@ -80,7 +80,7 @@ driver for more information regarding configuration options available for it. @section nrfx_additional_reqs Additional requirements Nordic SoCs are based on ARM® Cortex™-M series processors. Before you can -start developing with @em nrfx, you must add the CMSIS header files to include +start developing with nrfx, you must add the CMSIS header files to include paths during the compilation process. Download these files from the following website: diff --git a/doc/nrf51_series.dox b/doc/nrf51_series.dox index dd788ed89c..df195ca873 100644 --- a/doc/nrf51_series.dox +++ b/doc/nrf51_series.dox @@ -1,5 +1,9 @@ /** -@page nrf51_series_drivers nRF51 Series Drivers +@page nrf51_series_drivers nRF51 Series drivers + +This page lists nrfx driver components supported by the nRF51 Series SoCs. +For a complete overview, see @ref nrfx_drv_supp_matrix. + @{ @ref nrf_aar diff --git a/doc/nrf52805.dox b/doc/nrf52805.dox new file mode 100644 index 0000000000..ce106c54c5 --- /dev/null +++ b/doc/nrf52805.dox @@ -0,0 +1,68 @@ +/** +@page nrf52805_drivers nRF52805 drivers + +This page lists nrfx driver components supported by the nRF52805 SoCs. +For a complete overview, see @ref nrfx_drv_supp_matrix. + +@{ + +@ref nrf_aar + +@ref nrf_bprot + +@ref nrf_ccm + +@ref nrf_clock + +@ref nrf_systick + +@ref nrf_ecb + +@ref nrf_egu + +@ref nrf_ficr + +@ref nrf_gpio + +@ref nrf_gpiote + +@ref nrf_nvmc + +@ref nrf_power + +@ref nrf_ppi + +@ref nrf_qdec + +@ref nrf_radio + +@ref nrf_rng + +@ref nrf_rtc + +@ref nrf_saadc + +@ref nrf_spi + +@ref nrf_spim + +@ref nrf_spis + +@ref nrf_temp + +@ref nrf_timer + +@ref nrf_twi + +@ref nrf_twim + +@ref nrf_twis + +@ref nrf_uart + +@ref nrf_uarte + +@ref nrf_wdt + +@} +*/ diff --git a/doc/nrf52810.dox b/doc/nrf52810.dox index 9ca4bba911..0c653bd738 100644 --- a/doc/nrf52810.dox +++ b/doc/nrf52810.dox @@ -1,5 +1,9 @@ /** -@page nrf52810_drivers nRF52810/nRF52811 Drivers +@page nrf52810_drivers nRF52810/nRF52811 drivers + +This page lists nrfx driver components supported by the nRF52810/nRF52811 SoC. +For a complete overview, see @ref nrfx_drv_supp_matrix. + @{ @ref nrf_aar diff --git a/doc/nrf52820.dox b/doc/nrf52820.dox index c2019aac20..bbaa49cfb5 100644 --- a/doc/nrf52820.dox +++ b/doc/nrf52820.dox @@ -1,5 +1,9 @@ /** -@page nrf52820_drivers nRF52820 Drivers +@page nrf52820_drivers nRF52820 drivers + +This page lists nrfx driver components supported by the nRF52820 SoC. +For a complete overview, see @ref nrfx_drv_supp_matrix. + @{ @ref nrf_aar diff --git a/doc/nrf52832.dox b/doc/nrf52832.dox index 2b393e8da9..b0d93b2a38 100644 --- a/doc/nrf52832.dox +++ b/doc/nrf52832.dox @@ -1,5 +1,9 @@ /** -@page nrf52832_drivers nRF52832 Drivers +@page nrf52832_drivers nRF52832 drivers + +This page lists nrfx driver components supported by the nRF52832 SoC. +For a complete overview, see @ref nrfx_drv_supp_matrix. + @{ @ref nrf_aar diff --git a/doc/nrf52833.dox b/doc/nrf52833.dox index f8e8461c20..ac4a8ace7c 100644 --- a/doc/nrf52833.dox +++ b/doc/nrf52833.dox @@ -1,5 +1,9 @@ /** -@page nrf52833_drivers nRF52833 Drivers +@page nrf52833_drivers nRF52833 drivers + +This page lists nrfx driver components supported by the nRF52833 SoC. +For a complete overview, see @ref nrfx_drv_supp_matrix. + @{ @ref nrf_aar diff --git a/doc/nrf52840.dox b/doc/nrf52840.dox index 329957bb74..2fadc11dfc 100644 --- a/doc/nrf52840.dox +++ b/doc/nrf52840.dox @@ -1,5 +1,9 @@ /** -@page nrf52840_drivers nRF52840 Drivers +@page nrf52840_drivers nRF52840 drivers + +This page lists nrfx driver components supported by the nRF52840 SoC. +For a complete overview, see @ref nrfx_drv_supp_matrix. + @{ @ref nrf_aar diff --git a/doc/nrf5340.dox b/doc/nrf5340.dox index fcd8468426..b51861d9ab 100644 --- a/doc/nrf5340.dox +++ b/doc/nrf5340.dox @@ -1,5 +1,9 @@ /** @page nrf5340_drivers nRF5340 drivers + +This page lists nrfx driver components supported by the nRF5340 SoC. +For a complete overview, see @ref nrfx_drv_supp_matrix. + @{ @ref nrf_aar diff --git a/doc/nrf9160.dox b/doc/nrf9160.dox index f5d7fa88ad..360774d908 100644 --- a/doc/nrf9160.dox +++ b/doc/nrf9160.dox @@ -1,5 +1,9 @@ /** @page nrf9160_drivers nRF9160 drivers + +This page lists nrfx driver components supported by the nRF9160 SoC. +For a complete overview, see @ref nrfx_drv_supp_matrix. + @{ @ref nrf_clock diff --git a/doc/nrfx.doxyfile b/doc/nrfx.doxyfile index 43bbf50976..d320acb598 100644 --- a/doc/nrfx.doxyfile +++ b/doc/nrfx.doxyfile @@ -40,7 +40,7 @@ PROJECT_NAME = "nrfx" ### EDIT THIS ### -PROJECT_NUMBER = "2.2" +PROJECT_NUMBER = "2.3" # Using the PROJECT_BRIEF tag one can provide an optional one line description # for a project that appears at the top of each page and should give viewer a @@ -235,8 +235,8 @@ TAB_SIZE = 4 # newlines (in the resulting output). You can put ^^ in the value part of an # alias to insert a newline as if a physical newline was in the original file. -ALIASES = "tagGreenTick=@htmlonly
✔
@endhtmlonly" \ - "tagRedCross=@htmlonly
✖
@endhtmlonly" +ALIASES = tagGreenTick="@htmlonly
✔
@endhtmlonly" \ + tagRedCross="@htmlonly
✖
@endhtmlonly" # This tag can be used to specify a number of word-keyword mappings (TCL only). # A mapping has the form "name=value". For example adding "class=itcl::class" @@ -795,6 +795,7 @@ INPUT = ../helpers \ ../hal \ ../soc \ ../templates \ + ../CHANGELOG.md \ config_dox \ . diff --git a/drivers/include/nrfx_clock.h b/drivers/include/nrfx_clock.h index 08cbee180c..75109b1264 100644 --- a/drivers/include/nrfx_clock.h +++ b/drivers/include/nrfx_clock.h @@ -106,15 +106,16 @@ void nrfx_clock_stop(nrf_clock_domain_t domain); * * XTAL source is assumed for domains with multiple sources. * - * @param[in] domain Clock domain. - * @param[out] clk_src Clock source that is running. Set to NULL if not needed. - * Ignored for HFCLKAUDIO domain. Typecast it to @ref nrf_clock_lfclk_t for - * LFCLK and @ref nrf_clock_hfclk_t for HFCLK and HFCLK192M. + * @param[in] domain Clock domain. + * @param[out] p_clk_src Pointer to a clock source that is running. Set to NULL if not needed. + * Ignored for HFCLKAUDIO domain. Variable pointed by @p p_clk_src + * must be of either @ref nrf_clock_lfclk_t type for LFCLK + * or @ref nrf_clock_hfclk_t type for HFCLK and HFCLK192M. * * @retval true The clock domain is running. * @retval false The clock domain is not running. */ -NRFX_STATIC_INLINE bool nrfx_clock_is_running(nrf_clock_domain_t domain, void * clk_src); +NRFX_STATIC_INLINE bool nrfx_clock_is_running(nrf_clock_domain_t domain, void * p_clk_src); #if NRF_CLOCK_HAS_HFCLK_DIV || NRF_CLOCK_HAS_HFCLK_192M /** @@ -318,9 +319,9 @@ NRFX_STATIC_INLINE uint32_t nrfx_clock_ppi_event_addr(nrf_clock_event_t event) return nrf_clock_event_address_get(NRF_CLOCK, event); } -NRFX_STATIC_INLINE bool nrfx_clock_is_running(nrf_clock_domain_t domain, void * clk_src) +NRFX_STATIC_INLINE bool nrfx_clock_is_running(nrf_clock_domain_t domain, void * p_clk_src) { - return nrf_clock_is_running(NRF_CLOCK, domain, clk_src); + return nrf_clock_is_running(NRF_CLOCK, domain, p_clk_src); } NRFX_STATIC_INLINE bool nrfx_clock_hfclk_is_running(void) diff --git a/drivers/src/nrfx_clock.c b/drivers/src/nrfx_clock.c index 95a31d4ff8..2355c18b5f 100644 --- a/drivers/src/nrfx_clock.c +++ b/drivers/src/nrfx_clock.c @@ -43,11 +43,17 @@ extern bool nrfx_power_irq_enabled; #endif +#if defined(CLOCK_LFCLKSRC_SRC_RC) || defined(__NRFX_DOXYGEN__) + #define LF_SRC_RC CLOCK_LFCLKSRC_SRC_RC +#else + #define LF_SRC_RC CLOCK_LFCLKSRC_SRC_LFRC +#endif + #if NRFX_CHECK(NRFX_CLOCK_CONFIG_LF_CAL_ENABLED) #if (NRF_CLOCK_HAS_CALIBRATION == 0) #error "Calibration is not available in the SoC that is used." #endif - #if (NRFX_CLOCK_CONFIG_LF_SRC != CLOCK_LFCLKSRC_SRC_RC) + #if (NRFX_CLOCK_CONFIG_LF_SRC != LF_SRC_RC) #error "Calibration can be performed only for the RC Oscillator." #endif #endif @@ -79,6 +85,30 @@ extern bool nrfx_power_irq_enabled; #define USE_WORKAROUND_FOR_ANOMALY_201 1 #endif +#if defined(CLOCK_LFCLKSRC_SRC_Xtal) + #define LF_SRC_LFXO CLOCK_LFCLKSRC_SRC_Xtal +#else + #define LF_SRC_LFXO CLOCK_LFCLKSRC_SRC_LFXO +#endif + +#if defined(NRF_CLOCK_USE_EXTERNAL_LFCLK_SOURCES) + #define LF_SRC_XTAL_LOW (CLOCK_LFCLKSRC_SRC_Xtal | \ + (CLOCK_LFCLKSRC_EXTERNAL_Enabled << CLOCK_LFCLKSRC_EXTERNAL_Pos)) + #define LF_SRC_XTAL_FULL (CLOCK_LFCLKSRC_SRC_Xtal | \ + (CLOCK_LFCLKSRC_BYPASS_Enabled << CLOCK_LFCLKSRC_BYPASS_Pos) | \ + (CLOCK_LFCLKSRC_EXTERNAL_Enabled << CLOCK_LFCLKSRC_EXTERNAL_Pos)) +#else + #define LF_SRC_XTAL_LOW LF_SRC_LFXO + #define LF_SRC_XTAL_FULL LF_SRC_LFXO +#endif + +#if NRFX_CHECK(NRFX_CLOCK_CONFIG_LFXO_TWO_STAGE_ENABLED) && \ + NRFX_CLOCK_CONFIG_LF_SRC != LF_SRC_LFXO && \ + NRFX_CLOCK_CONFIG_LF_SRC != LF_SRC_XTAL_LOW && \ + NRFX_CLOCK_CONFIG_LF_SRC != LF_SRC_XTAL_FULL + #error "Two-stage LFXO start procedure enabled but LFCLK source is not set to LFXO!" +#endif + #if NRFX_CHECK(NRFX_CLOCK_CONFIG_LF_CAL_ENABLED) typedef enum { @@ -173,7 +203,9 @@ void nrfx_clock_enable(void) { NRFX_ASSERT(m_clock_cb.module_initialized); nrfx_power_clock_irq_init(); +#if !NRFX_CHECK(NRFX_CLOCK_CONFIG_LFXO_TWO_STAGE_ENABLED) nrf_clock_lf_src_set(NRF_CLOCK, (nrf_clock_lfclk_t)NRFX_CLOCK_CONFIG_LF_SRC); +#endif #if NRF_CLOCK_HAS_HFCLKSRC nrf_clock_hf_src_set(NRF_CLOCK, NRF_CLOCK_HFCLK_HIGH_ACCURACY); #endif @@ -233,6 +265,25 @@ void nrfx_clock_start(nrf_clock_domain_t domain) switch (domain) { case NRF_CLOCK_DOMAIN_LFCLK: +#if NRFX_CHECK(NRFX_CLOCK_CONFIG_LFXO_TWO_STAGE_ENABLED) + { + nrf_clock_lfclk_t lfclksrc; + if (nrf_clock_is_running(NRF_CLOCK, NRF_CLOCK_DOMAIN_LFCLK, &lfclksrc) && + lfclksrc == NRFX_CLOCK_CONFIG_LF_SRC) + { + // If the two-stage LFXO procedure has finished already + // use the configured LF clock source. + nrf_clock_lf_src_set(NRF_CLOCK, (nrf_clock_lfclk_t)NRFX_CLOCK_CONFIG_LF_SRC); + } + else + { + // If the two-stage LFXO procedure hasn't started yet + // or the RC stage is in progress, + // use the RC oscillator as LF clock source. + nrf_clock_lf_src_set(NRF_CLOCK, NRF_CLOCK_LFCLK_RC); + } + } +#endif // NRFX_CHECK(NRFX_CLOCK_CONFIG_LFXO_TWO_STAGE_ENABLED) nrf_clock_event_clear(NRF_CLOCK, NRF_CLOCK_EVENT_LFCLKSTARTED); nrf_clock_int_enable(NRF_CLOCK, NRF_CLOCK_INT_LF_STARTED_MASK); #if NRFX_CHECK(USE_WORKAROUND_FOR_ANOMALY_132) @@ -480,9 +531,23 @@ void nrfx_clock_irq_handler(void) { nrf_clock_event_clear(NRF_CLOCK, NRF_CLOCK_EVENT_LFCLKSTARTED); NRFX_LOG_DEBUG("Event: NRF_CLOCK_EVENT_LFCLKSTARTED"); - nrf_clock_int_disable(NRF_CLOCK, NRF_CLOCK_INT_LF_STARTED_MASK); - m_clock_cb.event_handler(NRFX_CLOCK_EVT_LFCLK_STARTED); +#if NRFX_CHECK(NRFX_CLOCK_CONFIG_LFXO_TWO_STAGE_ENABLED) + nrf_clock_lfclk_t lfclksrc; + (void)nrf_clock_is_running(NRF_CLOCK, NRF_CLOCK_DOMAIN_LFCLK, &lfclksrc); + if (lfclksrc == NRF_CLOCK_LFCLK_RC) + { + // After the LFRC oscillator start switch to external source. + nrf_clock_lf_src_set(NRF_CLOCK, (nrf_clock_lfclk_t)NRFX_CLOCK_CONFIG_LF_SRC); + nrf_clock_task_trigger(NRF_CLOCK, NRF_CLOCK_TASK_LFCLKSTART); + } + else +#endif + { + // After the LF clock external source start invoke user callback. + nrf_clock_int_disable(NRF_CLOCK, NRF_CLOCK_INT_LF_STARTED_MASK); + m_clock_cb.event_handler(NRFX_CLOCK_EVT_LFCLK_STARTED); + } } #if NRFX_CHECK(NRFX_CLOCK_CONFIG_LF_CAL_ENABLED) diff --git a/drivers/src/nrfx_nvmc.c b/drivers/src/nrfx_nvmc.c index 061138bedb..85027d7adb 100644 --- a/drivers/src/nrfx_nvmc.c +++ b/drivers/src/nrfx_nvmc.c @@ -80,7 +80,8 @@ * * This value is used to determine whether the partial erase is still in progress. */ -#if defined(NRF52810_XXAA) || defined(NRF52811_XXAA) || defined(NRF52840_XXAA) +#if defined(NRF52805_XXAA) || defined(NRF52810_XXAA) || \ + defined(NRF52811_XXAA) || defined(NRF52840_XXAA) #define NVMC_PAGE_ERASE_DURATION_MS 85 #elif defined(NRF52820_XXAA) || defined(NRF52833_XXAA) || defined(NRF9160_XXAA) || \ defined(NRF5340_XXAA_APPLICATION) || defined(NRF5340_XXAA_NETWORK) @@ -152,17 +153,20 @@ __STATIC_INLINE bool is_halfword_aligned(uint32_t addr) return ((addr & 0x1u) == 0u); } -__STATIC_INLINE bool is_valid_address(uint32_t addr) +__STATIC_INLINE bool is_valid_address(uint32_t addr, bool uicr_allowed) { if ((addr - NVMC_FLASH_BASE_ADDRESS) < flash_total_size_get()) { return true; } #if !defined(NRF_TRUSTZONE_NONSECURE) - if ((addr - (uint32_t)NRF_UICR) < sizeof(NRF_UICR_Type)) + if (uicr_allowed && + (addr - (uint32_t)NRF_UICR) < sizeof(NRF_UICR_Type)) { return true; } +#else + (void)uicr_allowed; #endif return false; @@ -253,7 +257,7 @@ static void nvmc_words_write(uint32_t addr, void const * src, uint32_t num_words nrfx_err_t nrfx_nvmc_page_erase(uint32_t addr) { - NRFX_ASSERT(is_valid_address(addr)); + NRFX_ASSERT(is_valid_address(addr, false)); if (!is_page_aligned_check(addr)) { @@ -295,7 +299,7 @@ void nrfx_nvmc_all_erase(void) #if defined(NRF_NVMC_PARTIAL_ERASE_PRESENT) nrfx_err_t nrfx_nvmc_page_partial_erase_init(uint32_t addr, uint32_t duration_ms) { - NRFX_ASSERT(is_valid_address(addr)); + NRFX_ASSERT(is_valid_address(addr, false)); if (!is_page_aligned_check(addr)) { @@ -341,7 +345,7 @@ bool nrfx_nvmc_page_partial_erase_continue(void) bool nrfx_nvmc_byte_writable_check(uint32_t addr, uint8_t val_to_check) { - NRFX_ASSERT(is_valid_address(addr)); + NRFX_ASSERT(is_valid_address(addr, true)); uint8_t val_on_addr = *(uint8_t const *)addr; return (val_to_check & val_on_addr) == val_to_check; @@ -349,7 +353,7 @@ bool nrfx_nvmc_byte_writable_check(uint32_t addr, uint8_t val_to_check) bool nrfx_nvmc_halfword_writable_check(uint32_t addr, uint16_t val_to_check) { - NRFX_ASSERT(is_valid_address(addr)); + NRFX_ASSERT(is_valid_address(addr, true)); NRFX_ASSERT(is_halfword_aligned(addr)); uint16_t val_on_addr; @@ -367,7 +371,7 @@ bool nrfx_nvmc_halfword_writable_check(uint32_t addr, uint16_t val_to_check) bool nrfx_nvmc_word_writable_check(uint32_t addr, uint32_t val_to_check) { - NRFX_ASSERT(is_valid_address(addr)); + NRFX_ASSERT(is_valid_address(addr, true)); NRFX_ASSERT(nrfx_is_word_aligned((void const *)addr)); uint32_t val_on_addr = *(uint32_t const *)addr; @@ -376,7 +380,7 @@ bool nrfx_nvmc_word_writable_check(uint32_t addr, uint32_t val_to_check) void nrfx_nvmc_byte_write(uint32_t addr, uint8_t value) { - NRFX_ASSERT(is_valid_address(addr)); + NRFX_ASSERT(is_valid_address(addr, true)); uint32_t aligned_addr = addr & ~(0x03UL); @@ -385,7 +389,7 @@ void nrfx_nvmc_byte_write(uint32_t addr, uint8_t value) void nrfx_nvmc_halfword_write(uint32_t addr, uint16_t value) { - NRFX_ASSERT(is_valid_address(addr)); + NRFX_ASSERT(is_valid_address(addr, true)); NRFX_ASSERT(is_halfword_aligned(addr)); uint32_t aligned_addr = addr & ~(0x03UL); @@ -395,7 +399,7 @@ void nrfx_nvmc_halfword_write(uint32_t addr, uint16_t value) void nrfx_nvmc_word_write(uint32_t addr, uint32_t value) { - NRFX_ASSERT(is_valid_address(addr)); + NRFX_ASSERT(is_valid_address(addr, true)); NRFX_ASSERT(nrfx_is_word_aligned((void const *)addr)); nvmc_write_mode_set(); @@ -407,7 +411,7 @@ void nrfx_nvmc_word_write(uint32_t addr, uint32_t value) void nrfx_nvmc_bytes_write(uint32_t addr, void const * src, uint32_t num_bytes) { - NRFX_ASSERT(is_valid_address(addr)); + NRFX_ASSERT(is_valid_address(addr, true)); nvmc_write_mode_set(); @@ -469,7 +473,7 @@ void nrfx_nvmc_bytes_write(uint32_t addr, void const * src, uint32_t num_bytes) void nrfx_nvmc_words_write(uint32_t addr, void const * src, uint32_t num_words) { - NRFX_ASSERT(is_valid_address(addr)); + NRFX_ASSERT(is_valid_address(addr, true)); NRFX_ASSERT(nrfx_is_word_aligned((void const *)addr)); NRFX_ASSERT(nrfx_is_word_aligned(src)); diff --git a/drivers/src/nrfx_saadc.c b/drivers/src/nrfx_saadc.c index 4a4236fc53..f9d931b437 100644 --- a/drivers/src/nrfx_saadc.c +++ b/drivers/src/nrfx_saadc.c @@ -286,7 +286,7 @@ nrfx_err_t nrfx_saadc_channels_config(nrfx_saadc_channel_t const * p_channels, p_channels[i].channel_index, &p_channels[i].channel_config); - NRFX_ASSERT(p_channels[i].pin_p); + NRFX_ASSERT(p_channels[i].pin_p != NRF_SAADC_INPUT_DISABLED); m_cb.channels_pselp[p_channels[i].channel_index] = p_channels[i].pin_p; m_cb.channels_pseln[p_channels[i].channel_index] = p_channels[i].pin_n; m_cb.channels_configured |= 1U << p_channels[i].channel_index; diff --git a/drivers/src/nrfx_usbd.c b/drivers/src/nrfx_usbd.c index 496cc0e05d..41749e984a 100644 --- a/drivers/src/nrfx_usbd.c +++ b/drivers/src/nrfx_usbd.c @@ -83,6 +83,11 @@ #define NRFX_USBD_DMAREQ_PROCESS_DEBUG 1 #endif +#ifndef NRFX_USBD_USE_WORKAROUND_FOR_ANOMALY_211 +/* Anomaly 211 - Device remains in SUSPEND too long when host resumes + a bus activity (sending SOF packets) without a RESUME condition. */ +#define NRFX_USBD_USE_WORKAROUND_FOR_ANOMALY_211 0 +#endif /** * @defgroup nrfx_usbd_int USB Device driver internal part @@ -268,6 +273,11 @@ static nrfx_atomic_t m_ep_dma_waiting; */ static bool m_dma_pending; +/** + * @brief First time enabling after reset. Used in nRF52 errata 223. + */ +static bool m_first_enable = true; + /** * @brief The structure that would hold transfer configuration to every endpoint * @@ -1447,6 +1457,126 @@ static void usbd_dmareq_process(void) } } } + +/** + * @brief Wait for a specified eventcause and clear it afterwards. + */ +static inline void usbd_eventcause_wait_and_clear(nrf_usbd_eventcause_mask_t eventcause) +{ + while (0 == (eventcause & nrf_usbd_eventcause_get(NRF_USBD))) + { + /* Empty loop */ + } + nrf_usbd_eventcause_clear(NRF_USBD, eventcause); +} + +/** + * @brief Begin errata 171. + */ +static inline void usbd_errata_171_begin(void) +{ + NRFX_CRITICAL_SECTION_ENTER(); + if (*((volatile uint32_t *)(0x4006EC00)) == 0x00000000) + { + *((volatile uint32_t *)(0x4006EC00)) = 0x00009375; + *((volatile uint32_t *)(0x4006EC14)) = 0x000000C0; + *((volatile uint32_t *)(0x4006EC00)) = 0x00009375; + } + else + { + *((volatile uint32_t *)(0x4006EC14)) = 0x000000C0; + } + NRFX_CRITICAL_SECTION_EXIT(); +} + +/** + * @brief End errata 171. + */ +static inline void usbd_errata_171_end(void) +{ + NRFX_CRITICAL_SECTION_ENTER(); + if (*((volatile uint32_t *)(0x4006EC00)) == 0x00000000) + { + *((volatile uint32_t *)(0x4006EC00)) = 0x00009375; + *((volatile uint32_t *)(0x4006EC14)) = 0x00000000; + *((volatile uint32_t *)(0x4006EC00)) = 0x00009375; + } + else + { + *((volatile uint32_t *)(0x4006EC14)) = 0x00000000; + } + NRFX_CRITICAL_SECTION_EXIT(); +} + +/** + * @brief Begin erratas 187 and 211. + */ +static inline void usbd_errata_187_211_begin(void) +{ + NRFX_CRITICAL_SECTION_ENTER(); + if (*((volatile uint32_t *)(0x4006EC00)) == 0x00000000) + { + *((volatile uint32_t *)(0x4006EC00)) = 0x00009375; + *((volatile uint32_t *)(0x4006ED14)) = 0x00000003; + *((volatile uint32_t *)(0x4006EC00)) = 0x00009375; + } + else + { + *((volatile uint32_t *)(0x4006ED14)) = 0x00000003; + } + NRFX_CRITICAL_SECTION_EXIT(); +} + +/** + * @brief End erratas 187 and 211. + */ +static inline void usbd_errata_187_211_end(void) +{ + NRFX_CRITICAL_SECTION_ENTER(); + if (*((volatile uint32_t *)(0x4006EC00)) == 0x00000000) + { + *((volatile uint32_t *)(0x4006EC00)) = 0x00009375; + *((volatile uint32_t *)(0x4006ED14)) = 0x00000000; + *((volatile uint32_t *)(0x4006EC00)) = 0x00009375; + } + else + { + *((volatile uint32_t *)(0x4006ED14)) = 0x00000000; + } + NRFX_CRITICAL_SECTION_EXIT(); +} + +/** + * @brief Enable USBD peripheral. + */ +static void usbd_enable(void) +{ + if (nrfx_usbd_errata_187()) + { + usbd_errata_187_211_begin(); + } + + if (nrfx_usbd_errata_171()) + { + usbd_errata_171_begin(); + } + + /* Enable the peripheral */ + nrf_usbd_enable(NRF_USBD); + + /* Waiting for peripheral to enable, this should take a few us */ + usbd_eventcause_wait_and_clear(NRF_USBD_EVENTCAUSE_READY_MASK); + + if (nrfx_usbd_errata_171()) + { + usbd_errata_171_end(); + } + + if (nrfx_usbd_errata_187()) + { + usbd_errata_187_211_end(); + } +} /** @} */ /** @@ -1572,6 +1702,7 @@ void nrfx_usbd_uninit(void) return; } + void nrfx_usbd_enable(void) { NRFX_ASSERT(m_drv_state == NRFX_DRV_STATE_INITIALIZED); @@ -1579,62 +1710,24 @@ void nrfx_usbd_enable(void) /* Prepare for READY event receiving */ nrf_usbd_eventcause_clear(NRF_USBD, NRF_USBD_EVENTCAUSE_READY_MASK); - if (nrfx_usbd_errata_187()) - { - NRFX_CRITICAL_SECTION_ENTER(); - if (*((volatile uint32_t *)(0x4006EC00)) == 0x00000000) - { - *((volatile uint32_t *)(0x4006EC00)) = 0x00009375; - *((volatile uint32_t *)(0x4006ED14)) = 0x00000003; - *((volatile uint32_t *)(0x4006EC00)) = 0x00009375; - } - else - { - *((volatile uint32_t *)(0x4006ED14)) = 0x00000003; - } - NRFX_CRITICAL_SECTION_EXIT(); - } + usbd_enable(); - if (nrfx_usbd_errata_171()) + if (nrfx_usbd_errata_223() && m_first_enable) { - NRFX_CRITICAL_SECTION_ENTER(); - if (*((volatile uint32_t *)(0x4006EC00)) == 0x00000000) - { - *((volatile uint32_t *)(0x4006EC00)) = 0x00009375; - *((volatile uint32_t *)(0x4006EC14)) = 0x000000C0; - *((volatile uint32_t *)(0x4006EC00)) = 0x00009375; - } - else - { - *((volatile uint32_t *)(0x4006EC14)) = 0x000000C0; - } - NRFX_CRITICAL_SECTION_EXIT(); - } + nrf_usbd_disable(NRF_USBD); - /* Enable the peripheral */ - nrf_usbd_enable(NRF_USBD); - /* Waiting for peripheral to enable, this should take a few us */ - while (0 == (NRF_USBD_EVENTCAUSE_READY_MASK & nrf_usbd_eventcause_get(NRF_USBD))) - { - /* Empty loop */ + usbd_enable(); + + m_first_enable = false; } - nrf_usbd_eventcause_clear(NRF_USBD, NRF_USBD_EVENTCAUSE_READY_MASK); - if (nrfx_usbd_errata_171()) +#if NRFX_USBD_USE_WORKAROUND_FOR_ANOMALY_211 + if (nrfx_usbd_errata_187() || nrfx_usbd_errata_211()) +#else + if (nrfx_usbd_errata_187()) +#endif { - NRFX_CRITICAL_SECTION_ENTER(); - if (*((volatile uint32_t *)(0x4006EC00)) == 0x00000000) - { - *((volatile uint32_t *)(0x4006EC00)) = 0x00009375; - *((volatile uint32_t *)(0x4006EC14)) = 0x00000000; - *((volatile uint32_t *)(0x4006EC00)) = 0x00009375; - } - else - { - *((volatile uint32_t *)(0x4006EC14)) = 0x00000000; - } - - NRFX_CRITICAL_SECTION_EXIT(); + usbd_errata_187_211_begin(); } if (nrfx_usbd_errata_166()) @@ -1663,20 +1756,13 @@ void nrfx_usbd_enable(void) m_drv_state = NRFX_DRV_STATE_POWERED_ON; +#if NRFX_USBD_USE_WORKAROUND_FOR_ANOMALY_211 + if (nrfx_usbd_errata_187() && !nrfx_usbd_errata_211()) +#else if (nrfx_usbd_errata_187()) +#endif { - NRFX_CRITICAL_SECTION_ENTER(); - if (*((volatile uint32_t *)(0x4006EC00)) == 0x00000000) - { - *((volatile uint32_t *)(0x4006EC00)) = 0x00009375; - *((volatile uint32_t *)(0x4006ED14)) = 0x00000000; - *((volatile uint32_t *)(0x4006EC00)) = 0x00009375; - } - else - { - *((volatile uint32_t *)(0x4006ED14)) = 0x00000000; - } - NRFX_CRITICAL_SECTION_EXIT(); + usbd_errata_187_211_end(); } } @@ -1692,6 +1778,13 @@ void nrfx_usbd_disable(void) nrf_usbd_disable(NRF_USBD); usbd_dma_pending_clear(); m_drv_state = NRFX_DRV_STATE_INITIALIZED; + +#if NRFX_USBD_USE_WORKAROUND_FOR_ANOMALY_211 + if (nrfx_usbd_errata_211()) + { + usbd_errata_187_211_end(); + } +#endif } void nrfx_usbd_start(bool enable_sof) diff --git a/drivers/src/nrfx_usbd_errata.h b/drivers/src/nrfx_usbd_errata.h index 054a534e1d..2e1512d4e9 100644 --- a/drivers/src/nrfx_usbd_errata.h +++ b/drivers/src/nrfx_usbd_errata.h @@ -68,4 +68,16 @@ static inline bool nrfx_usbd_errata_199(void) return NRFX_USBD_ERRATA_ENABLE && nrf52_errata_199(); } +/* Errata: Device remains in SUSPEND too long. */ +static inline bool nrfx_usbd_errata_211(void) +{ + return NRFX_USBD_ERRATA_ENABLE && nrf52_errata_211(); +} + +/* Errata: Unexpected behavior after reset. **/ +static inline bool nrfx_usbd_errata_223(void) +{ + return NRFX_USBD_ERRATA_ENABLE && nrf52_errata_223(); +} + #endif // NRFX_USBD_ERRATA_H__ diff --git a/drivers/src/prs/nrfx_prs.h b/drivers/src/prs/nrfx_prs.h index a61face72b..90e738e347 100644 --- a/drivers/src/prs/nrfx_prs.h +++ b/drivers/src/prs/nrfx_prs.h @@ -51,7 +51,7 @@ extern "C" { #define NRFX_PRS_BOX_0_ADDR NRF_SPI0 // SPI1, SPIS1, TWI1 #define NRFX_PRS_BOX_1_ADDR NRF_SPI1 -#elif defined(NRF52810_XXAA) +#elif defined(NRF52805_XXAA) || defined(NRF52810_XXAA) // TWIM0, TWIS0, TWI0 #define NRFX_PRS_BOX_0_ADDR NRF_TWIM0 // SPIM0, SPIS0, SPI0 diff --git a/hal/nrf_aar.h b/hal/nrf_aar.h index 0b35faec6b..d42b8d12f6 100644 --- a/hal/nrf_aar.h +++ b/hal/nrf_aar.h @@ -269,10 +269,7 @@ NRF_STATIC_INLINE void nrf_aar_event_clear(NRF_AAR_Type * p_reg, nrf_aar_event_t aar_event) { *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)aar_event)) = 0; -#if __CORTEX_M == 0x04 - volatile uint32_t dummy = *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)aar_event)); - (void)dummy; -#endif + nrf_event_readback((uint8_t *)p_reg + (uint32_t)aar_event); } NRF_STATIC_INLINE uint32_t nrf_aar_event_address_get(NRF_AAR_Type const * p_reg, diff --git a/hal/nrf_ccm.h b/hal/nrf_ccm.h index 189eca2c3a..13adfb5f89 100644 --- a/hal/nrf_ccm.h +++ b/hal/nrf_ccm.h @@ -64,6 +64,12 @@ typedef enum NRF_CCM_EVENT_ERROR = offsetof(NRF_CCM_Type, EVENTS_ERROR), ///< CCM error event. } nrf_ccm_event_t; +/** @brief Types of CCM shorts. */ +typedef enum +{ + NRF_CCM_SHORT_ENDKSGEN_CRYPT_MASK = CCM_SHORTS_ENDKSGEN_CRYPT_Msk, ///< Shortcut for starting encryption/decryption when the key-stream generation is complete. +} nrf_ccm_short_mask_t; + /** @brief CCM interrupts. */ typedef enum { @@ -166,6 +172,33 @@ NRF_STATIC_INLINE bool nrf_ccm_event_check(NRF_CCM_Type const * p_reg, NRF_STATIC_INLINE uint32_t nrf_ccm_event_address_get(NRF_CCM_Type const * p_reg, nrf_ccm_event_t event); +/** + * @brief Function for enabling the specified shortcuts. + * + * @param[in] p_reg Pointer to the structure of registers of the peripheral. + * @param[in] mask Shortcuts to be enabled. + */ +NRF_STATIC_INLINE void nrf_ccm_shorts_enable(NRF_CCM_Type * p_reg, + uint32_t mask); + +/** + * @brief Function for disabling the specified shortcuts. + * + * @param[in] p_reg Pointer to the structure of registers of the peripheral. + * @param[in] mask Shortcuts to be disabled. + */ +NRF_STATIC_INLINE void nrf_ccm_shorts_disable(NRF_CCM_Type * p_reg, + uint32_t mask); + +/** + * @brief Function for setting the specified shortcuts. + * + * @param[in] p_reg Pointer to the structure of registers of the peripheral. + * @param[in] mask Shortcuts to be set. + */ +NRF_STATIC_INLINE void nrf_ccm_shorts_set(NRF_CCM_Type * p_reg, + uint32_t mask); + /** * @brief Function for enabling specified interrupts. * @@ -342,10 +375,7 @@ NRF_STATIC_INLINE void nrf_ccm_event_clear(NRF_CCM_Type * p_reg, nrf_ccm_event_t event) { *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL; -#if __CORTEX_M == 0x04 - volatile uint32_t dummy = *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)); - (void)dummy; -#endif + nrf_event_readback((uint8_t *)p_reg + (uint32_t)event); } NRF_STATIC_INLINE bool nrf_ccm_event_check(NRF_CCM_Type const * p_reg, @@ -360,6 +390,25 @@ NRF_STATIC_INLINE uint32_t nrf_ccm_event_address_get(NRF_CCM_Type const * p_reg, return ((uint32_t)p_reg + (uint32_t)event); } + +NRF_STATIC_INLINE void nrf_ccm_shorts_enable(NRF_CCM_Type * p_reg, + uint32_t mask) +{ + p_reg->SHORTS |= mask; +} + +NRF_STATIC_INLINE void nrf_ccm_shorts_disable(NRF_CCM_Type * p_reg, + uint32_t mask) +{ + p_reg->SHORTS &= ~(mask); +} + +NRF_STATIC_INLINE void nrf_ccm_shorts_set(NRF_CCM_Type * p_reg, + uint32_t mask) +{ + p_reg->SHORTS = mask; +} + NRF_STATIC_INLINE void nrf_ccm_int_enable(NRF_CCM_Type * p_reg, uint32_t mask) { p_reg->INTENSET = mask; diff --git a/hal/nrf_clock.h b/hal/nrf_clock.h index 465aba60a6..3ec013f153 100644 --- a/hal/nrf_clock.h +++ b/hal/nrf_clock.h @@ -743,10 +743,7 @@ NRF_STATIC_INLINE uint32_t nrf_clock_event_address_get(NRF_CLOCK_Type const * p_ NRF_STATIC_INLINE void nrf_clock_event_clear(NRF_CLOCK_Type * p_reg, nrf_clock_event_t event) { *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL; -#if __CORTEX_M == 0x04 - volatile uint32_t dummy = *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)); - (void)dummy; -#endif + nrf_event_readback((uint8_t *)p_reg + (uint32_t)event); } NRF_STATIC_INLINE bool nrf_clock_event_check(NRF_CLOCK_Type const * p_reg, nrf_clock_event_t event) diff --git a/hal/nrf_common.h b/hal/nrf_common.h new file mode 100644 index 0000000000..063941c940 --- /dev/null +++ b/hal/nrf_common.h @@ -0,0 +1,60 @@ +/* + * Copyright (c) 2020, Nordic Semiconductor ASA + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef NRF_COMMON_H__ +#define NRF_COMMON_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#ifndef NRFX_EVENT_READBACK_ENABLED +#define NRFX_EVENT_READBACK_ENABLED 1 +#endif + +#ifndef NRF_DECLARE_ONLY + +NRF_STATIC_INLINE void nrf_event_readback(void * p_event_reg) +{ +#if NRFX_CHECK(NRFX_EVENT_READBACK_ENABLED) && !defined(NRF51) + (void)*((volatile uint32_t *)(p_event_reg)); +#else + (void)p_event_reg; +#endif +} + +#endif // NRF_DECLARE_ONLY + +#ifdef __cplusplus +} +#endif + +#endif // NRF_COMMON_H__ diff --git a/hal/nrf_comp.h b/hal/nrf_comp.h index 674e804e1b..8a0781e188 100644 --- a/hal/nrf_comp.h +++ b/hal/nrf_comp.h @@ -480,10 +480,7 @@ NRF_STATIC_INLINE void nrf_comp_task_trigger(NRF_COMP_Type * p_reg, nrf_comp_tas NRF_STATIC_INLINE void nrf_comp_event_clear(NRF_COMP_Type * p_reg, nrf_comp_event_t event) { *( (volatile uint32_t *)( (uint8_t *)p_reg + (uint32_t)event) ) = 0; -#if __CORTEX_M == 0x04 - volatile uint32_t dummy = *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)); - (void)dummy; -#endif + nrf_event_readback((uint8_t *)p_reg + (uint32_t)event); } NRF_STATIC_INLINE bool nrf_comp_event_check(NRF_COMP_Type const * p_reg, nrf_comp_event_t event) diff --git a/hal/nrf_ecb.h b/hal/nrf_ecb.h index e734e14ae2..ec4f10d6f4 100644 --- a/hal/nrf_ecb.h +++ b/hal/nrf_ecb.h @@ -178,10 +178,7 @@ NRF_STATIC_INLINE uint32_t nrf_ecb_task_address_get(NRF_ECB_Type const * p_reg, NRF_STATIC_INLINE void nrf_ecb_event_clear(NRF_ECB_Type * p_reg, nrf_ecb_event_t event) { *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL; -#if __CORTEX_M == 0x04 - volatile uint32_t dummy = *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)); - (void)dummy; -#endif + nrf_event_readback((uint8_t *)p_reg + (uint32_t)event); } NRF_STATIC_INLINE bool nrf_ecb_event_check(NRF_ECB_Type const * p_reg, nrf_ecb_event_t event) diff --git a/hal/nrf_egu.h b/hal/nrf_egu.h index 83086d78ab..bdeebead65 100644 --- a/hal/nrf_egu.h +++ b/hal/nrf_egu.h @@ -324,10 +324,7 @@ NRF_STATIC_INLINE void nrf_egu_event_clear(NRF_EGU_Type * p_reg, nrf_egu_event_t { NRFX_ASSERT(p_reg); *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)egu_event)) = 0x0UL; -#if __CORTEX_M == 0x04 - volatile uint32_t dummy = *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)egu_event)); - (void)dummy; -#endif + nrf_event_readback((uint8_t *)p_reg + (uint32_t)egu_event); } NRF_STATIC_INLINE uint32_t nrf_egu_event_address_get(NRF_EGU_Type const * p_reg, diff --git a/hal/nrf_gpio.h b/hal/nrf_gpio.h index b2650a5170..05edf993a3 100644 --- a/hal/nrf_gpio.h +++ b/hal/nrf_gpio.h @@ -143,9 +143,10 @@ typedef enum /** @brief Enumerator used for selecting the MCU/Subsystem to control the specified pin. */ typedef enum { - NRF_GPIO_PIN_MCUSEL_APP = GPIO_PIN_CNF_MCUSEL_AppMCU, ///< Pin controlled by Application MCU. - NRF_GPIO_PIN_MCUSEL_NETWORK = GPIO_PIN_CNF_MCUSEL_NetworkMCU, ///< Pin controlled by Network MCU. - NRF_GPIO_PIN_MCUSEL_TND = GPIO_PIN_CNF_MCUSEL_TND, ///< Pin controlled by Trace and Debug Subsystem. + NRF_GPIO_PIN_MCUSEL_APP = GPIO_PIN_CNF_MCUSEL_AppMCU, ///< Pin controlled by Application MCU. + NRF_GPIO_PIN_MCUSEL_NETWORK = GPIO_PIN_CNF_MCUSEL_NetworkMCU, ///< Pin controlled by Network MCU. + NRF_GPIO_PIN_MCUSEL_PERIPHERAL = GPIO_PIN_CNF_MCUSEL_Peripheral, ///< Pin controlled by dedicated peripheral. + NRF_GPIO_PIN_MCUSEL_TND = GPIO_PIN_CNF_MCUSEL_TND, ///< Pin controlled by Trace and Debug Subsystem. } nrf_gpio_pin_mcusel_t; #endif @@ -511,37 +512,47 @@ NRF_STATIC_INLINE void nrf_gpio_pin_mcu_select(uint32_t pin_number, nrf_gpio_pin */ NRF_STATIC_INLINE bool nrf_gpio_pin_present_check(uint32_t pin_number); +/** + * @brief Function for extracting port number and the relative pin number + * from the absolute pin number. + * + * @param[in,out] p_pin Pointer to the absolute pin number overridden by the pin number + * that is relative to the port. + * + * @return Port number. +*/ +NRF_STATIC_INLINE uint32_t nrf_gpio_pin_port_number_extract(uint32_t * p_pin); + #ifndef NRF_DECLARE_ONLY /** * @brief Function for extracting port and the relative pin number from the absolute pin number. * - * @param[in,out] p_pin Pointer to the absolute pin number overriden by the pin number that is relative to the port. + * @param[in,out] p_pin Pointer to the absolute pin number overridden by the pin number + * that is relative to the port. * * @return Pointer to port register set. */ NRF_STATIC_INLINE NRF_GPIO_Type * nrf_gpio_pin_port_decode(uint32_t * p_pin) { NRFX_ASSERT(nrf_gpio_pin_present_check(*p_pin)); -#if (GPIO_COUNT == 1) - return NRF_P0; -#else - if (*p_pin < P0_PIN_NUM) - { - return NRF_P0; - } - else + + switch (nrf_gpio_pin_port_number_extract(p_pin)) { - *p_pin = *p_pin & 0x1F; - return NRF_P1; - } + default: + NRFX_ASSERT(0); +#if defined(P0_FEATURE_PINS_PRESENT) + case 0: return NRF_P0; #endif +#if defined(P1_FEATURE_PINS_PRESENT) + case 1: return NRF_P1; +#endif + } } NRF_STATIC_INLINE void nrf_gpio_range_cfg_output(uint32_t pin_range_start, uint32_t pin_range_end) { - /*lint -e{845} // A zero has been given as right argument to operator '|'" */ for (; pin_range_start <= pin_range_end; pin_range_start++) { nrf_gpio_cfg_output(pin_range_start); @@ -553,7 +564,6 @@ NRF_STATIC_INLINE void nrf_gpio_range_cfg_input(uint32_t pin_range_st uint32_t pin_range_end, nrf_gpio_pin_pull_t pull_config) { - /*lint -e{845} // A zero has been given as right argument to operator '|'" */ for (; pin_range_start <= pin_range_end; pin_range_start++) { nrf_gpio_cfg_input(pin_range_start, pull_config); @@ -618,7 +628,6 @@ NRF_STATIC_INLINE void nrf_gpio_cfg_default(uint32_t pin_number) NRF_STATIC_INLINE void nrf_gpio_cfg_watcher(uint32_t pin_number) { NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number); - /*lint -e{845} // A zero has been given as right argument to operator '|'" */ uint32_t cnf = reg->PIN_CNF[pin_number] & ~GPIO_PIN_CNF_INPUT_Msk; reg->PIN_CNF[pin_number] = cnf | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos); @@ -628,7 +637,6 @@ NRF_STATIC_INLINE void nrf_gpio_cfg_watcher(uint32_t pin_number) NRF_STATIC_INLINE void nrf_gpio_input_disconnect(uint32_t pin_number) { NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number); - /*lint -e{845} // A zero has been given as right argument to operator '|'" */ uint32_t cnf = reg->PIN_CNF[pin_number] & ~GPIO_PIN_CNF_INPUT_Msk; reg->PIN_CNF[pin_number] = cnf | (GPIO_PIN_CNF_INPUT_Disconnect << GPIO_PIN_CNF_INPUT_Pos); @@ -653,7 +661,6 @@ NRF_STATIC_INLINE void nrf_gpio_cfg_sense_set(uint32_t pin_number, nrf_gpio_pin_sense_t sense_config) { NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number); - /*lint -e{845} // A zero has been given as right argument to operator '|'" */ uint32_t cnf = reg->PIN_CNF[pin_number] & ~GPIO_PIN_CNF_SENSE_Msk; reg->PIN_CNF[pin_number] = cnf | (sense_config << GPIO_PIN_CNF_SENSE_Pos); @@ -933,6 +940,14 @@ NRF_STATIC_INLINE bool nrf_gpio_pin_present_check(uint32_t pin_number) return (mask & (1UL << pin_number)) ? true : false; } +NRF_STATIC_INLINE uint32_t nrf_gpio_pin_port_number_extract(uint32_t * p_pin) +{ + uint32_t pin_number = *p_pin; + *p_pin = pin_number & 0x1F; + + return pin_number >> 5; +} + #endif // NRF_DECLARE_ONLY /** @} */ diff --git a/hal/nrf_gpiote.h b/hal/nrf_gpiote.h index 8f3321da20..2a0d52e235 100644 --- a/hal/nrf_gpiote.h +++ b/hal/nrf_gpiote.h @@ -441,10 +441,7 @@ NRF_STATIC_INLINE bool nrf_gpiote_event_check(NRF_GPIOTE_Type const * p_reg, NRF_STATIC_INLINE void nrf_gpiote_event_clear(NRF_GPIOTE_Type * p_reg, nrf_gpiote_event_t event) { *((volatile uint32_t *)nrf_gpiote_event_address_get(p_reg, event)) = 0; -#if __CORTEX_M == 0x04 - volatile uint32_t dummy = *((volatile uint32_t *)nrf_gpiote_event_address_get(p_reg, event)); - (void)dummy; -#endif + nrf_event_readback((void *)nrf_gpiote_event_address_get(p_reg, event)); } NRF_STATIC_INLINE uint32_t nrf_gpiote_event_address_get(NRF_GPIOTE_Type const * p_reg, diff --git a/hal/nrf_i2s.h b/hal/nrf_i2s.h index f87a20c919..7744ebb6a1 100644 --- a/hal/nrf_i2s.h +++ b/hal/nrf_i2s.h @@ -525,10 +525,7 @@ NRF_STATIC_INLINE void nrf_i2s_event_clear(NRF_I2S_Type * p_reg, nrf_i2s_event_t event) { *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL; -#if __CORTEX_M == 0x04 - volatile uint32_t dummy = *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)); - (void)dummy; -#endif + nrf_event_readback((uint8_t *)p_reg + (uint32_t)event); } NRF_STATIC_INLINE bool nrf_i2s_event_check(NRF_I2S_Type const * p_reg, diff --git a/hal/nrf_lpcomp.h b/hal/nrf_lpcomp.h index 777f6ea599..a0e976cd5d 100644 --- a/hal/nrf_lpcomp.h +++ b/hal/nrf_lpcomp.h @@ -406,10 +406,7 @@ NRF_STATIC_INLINE void nrf_lpcomp_task_trigger(NRF_LPCOMP_Type * p_reg, nrf_lpco NRF_STATIC_INLINE void nrf_lpcomp_event_clear(NRF_LPCOMP_Type * p_reg, nrf_lpcomp_event_t event) { *( (volatile uint32_t *)( (uint8_t *)p_reg + (uint32_t)event) ) = 0; -#if __CORTEX_M == 0x04 - volatile uint32_t dummy = *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)); - (void)dummy; -#endif + nrf_event_readback((uint8_t *)p_reg + (uint32_t)event); } NRF_STATIC_INLINE bool nrf_lpcomp_event_check(NRF_LPCOMP_Type const * p_reg, diff --git a/hal/nrf_mwu.h b/hal/nrf_mwu.h index 4fbf445468..b25f1e225e 100644 --- a/hal/nrf_mwu.h +++ b/hal/nrf_mwu.h @@ -287,10 +287,7 @@ NRF_STATIC_INLINE void nrf_mwu_event_clear(NRF_MWU_Type * p_reg, nrf_mwu_event_t event) { *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0; -#if __CORTEX_M == 0x04 - volatile uint32_t dummy = *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)); - (void)dummy; -#endif + nrf_event_readback((uint8_t *)p_reg + (uint32_t)event); } NRF_STATIC_INLINE uint32_t nrf_mwu_event_address_get(NRF_MWU_Type const * p_reg, diff --git a/hal/nrf_pdm.h b/hal/nrf_pdm.h index a78e7ebb50..0a36766f5a 100644 --- a/hal/nrf_pdm.h +++ b/hal/nrf_pdm.h @@ -449,10 +449,7 @@ NRF_STATIC_INLINE bool nrf_pdm_event_check(NRF_PDM_Type const * p_reg, nrf_pdm_e NRF_STATIC_INLINE void nrf_pdm_event_clear(NRF_PDM_Type * p_reg, nrf_pdm_event_t event) { *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL; -#if __CORTEX_M == 0x04 - volatile uint32_t dummy = *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)); - (void)dummy; -#endif + nrf_event_readback((uint8_t *)p_reg + (uint32_t)event); } NRF_STATIC_INLINE uint32_t nrf_pdm_event_address_get(NRF_PDM_Type const * p_reg, diff --git a/hal/nrf_power.h b/hal/nrf_power.h index 64887eda41..d47560895c 100644 --- a/hal/nrf_power.h +++ b/hal/nrf_power.h @@ -33,6 +33,7 @@ #define NRF_POWER_H__ #include +#include #ifdef __cplusplus extern "C" { @@ -876,10 +877,7 @@ NRF_STATIC_INLINE uint32_t nrf_power_task_address_get(NRF_POWER_Type const * p_r NRF_STATIC_INLINE void nrf_power_event_clear(NRF_POWER_Type * p_reg, nrf_power_event_t event) { *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL; -#if __CORTEX_M == 0x04 - volatile uint32_t dummy = *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)); - (void)dummy; -#endif + nrf_event_readback((uint8_t *)p_reg + (uint32_t)event); } NRF_STATIC_INLINE bool nrf_power_event_check(NRF_POWER_Type const * p_reg, nrf_power_event_t event) @@ -1149,6 +1147,11 @@ NRF_STATIC_INLINE uint32_t nrf_power_rampower_mask_get(NRF_POWER_Type const * p_ #if NRF_POWER_HAS_DCDCEN_VDDH NRF_STATIC_INLINE void nrf_power_dcdcen_vddh_set(NRF_POWER_Type * p_reg, bool enable) { + if (nrf52_errata_197()) + { + // Workaround for anomaly 197 "POWER: DCDC of REG0 not functional". + *(volatile uint32_t *)0x40000638ul = 1ul; + } p_reg->DCDCEN0 = (enable ? POWER_DCDCEN0_DCDCEN_Enabled : POWER_DCDCEN0_DCDCEN_Disabled) << POWER_DCDCEN0_DCDCEN_Pos; } diff --git a/hal/nrf_ppi.h b/hal/nrf_ppi.h index 85fa32dccb..2284c35df6 100644 --- a/hal/nrf_ppi.h +++ b/hal/nrf_ppi.h @@ -59,12 +59,14 @@ typedef enum NRF_PPI_CHANNEL7 = PPI_CHEN_CH7_Pos, /**< Channel 7. */ NRF_PPI_CHANNEL8 = PPI_CHEN_CH8_Pos, /**< Channel 8. */ NRF_PPI_CHANNEL9 = PPI_CHEN_CH9_Pos, /**< Channel 9. */ +#if (PPI_CH_NUM > 10) || defined(__NRFX_DOXYGEN__) NRF_PPI_CHANNEL10 = PPI_CHEN_CH10_Pos, /**< Channel 10. */ NRF_PPI_CHANNEL11 = PPI_CHEN_CH11_Pos, /**< Channel 11. */ NRF_PPI_CHANNEL12 = PPI_CHEN_CH12_Pos, /**< Channel 12. */ NRF_PPI_CHANNEL13 = PPI_CHEN_CH13_Pos, /**< Channel 13. */ NRF_PPI_CHANNEL14 = PPI_CHEN_CH14_Pos, /**< Channel 14. */ NRF_PPI_CHANNEL15 = PPI_CHEN_CH15_Pos, /**< Channel 15. */ +#endif #if (PPI_CH_NUM > 16) || defined(__NRFX_DOXYGEN__) NRF_PPI_CHANNEL16 = PPI_CHEN_CH16_Pos, /**< Channel 16. */ NRF_PPI_CHANNEL17 = PPI_CHEN_CH17_Pos, /**< Channel 17. */ @@ -546,6 +548,7 @@ NRF_STATIC_INLINE uint32_t nrf_ppi_task_group_disable_address_get(NRF_PPI_Type c NRF_STATIC_INLINE nrf_ppi_task_t nrf_ppi_group_enable_task_get(NRF_PPI_Type const * p_reg, uint8_t index) { + (void)p_reg; NRFX_ASSERT(index < PPI_GROUP_NUM); return (nrf_ppi_task_t)NRFX_OFFSETOF(NRF_PPI_Type, TASKS_CHG[index].EN); } @@ -553,6 +556,7 @@ NRF_STATIC_INLINE nrf_ppi_task_t nrf_ppi_group_enable_task_get(NRF_PPI_Type cons NRF_STATIC_INLINE nrf_ppi_task_t nrf_ppi_group_disable_task_get(NRF_PPI_Type const * p_reg, uint8_t index) { + (void)p_reg; NRFX_ASSERT(index < PPI_GROUP_NUM); return (nrf_ppi_task_t)NRFX_OFFSETOF(NRF_PPI_Type, TASKS_CHG[index].DIS); } diff --git a/hal/nrf_pwm.h b/hal/nrf_pwm.h index 272f2cb36e..b9fb052779 100644 --- a/hal/nrf_pwm.h +++ b/hal/nrf_pwm.h @@ -552,10 +552,7 @@ NRF_STATIC_INLINE void nrf_pwm_event_clear(NRF_PWM_Type * p_reg, nrf_pwm_event_t event) { *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL; -#if __CORTEX_M == 0x04 - volatile uint32_t dummy = *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)); - (void)dummy; -#endif + nrf_event_readback((uint8_t *)p_reg + (uint32_t)event); } NRF_STATIC_INLINE bool nrf_pwm_event_check(NRF_PWM_Type const * p_reg, diff --git a/hal/nrf_qdec.h b/hal/nrf_qdec.h index 8f163044c1..363d1229fd 100644 --- a/hal/nrf_qdec.h +++ b/hal/nrf_qdec.h @@ -578,10 +578,7 @@ NRF_STATIC_INLINE uint32_t nrf_qdec_task_address_get(NRF_QDEC_Type const * p_reg NRF_STATIC_INLINE void nrf_qdec_event_clear(NRF_QDEC_Type * p_reg, nrf_qdec_event_t event) { *( (volatile uint32_t *)( (uint8_t *)p_reg + (uint32_t)event) ) = 0; -#if __CORTEX_M == 0x04 - volatile uint32_t dummy = *((volatile uint32_t *)((uint8_t *)p_reg + event)); - (void)dummy; -#endif + nrf_event_readback((uint8_t *)p_reg + (uint32_t)event); } NRF_STATIC_INLINE bool nrf_qdec_event_check(NRF_QDEC_Type const * p_reg, nrf_qdec_event_t event) diff --git a/hal/nrf_qspi.h b/hal/nrf_qspi.h index 69eca9a4bf..a6283349fa 100644 --- a/hal/nrf_qspi.h +++ b/hal/nrf_qspi.h @@ -33,6 +33,7 @@ #define NRF_QSPI_H__ #include +#include #ifdef __cplusplus extern "C" { @@ -66,6 +67,13 @@ extern "C" { #define NRF_QSPI_HAS_DMA_ENC 0 #endif +#if defined(QSPI_IFCONFIG1_SPIMODE_MODE3) || defined(__NRFX_DOXYGEN__) +/** @brief Symbol indicating whether support for QSPI mode 1 is present. */ +#define NRF_QSPI_HAS_MODE_1 1 +#else +#define NRF_QSPI_HAS_MODE_1 0 +#endif + #if defined(NRF53_SERIES) || defined(__NRFX_DOXYGEN__) /** @brief Value representing QSPI base clock frequency. */ #define NRF_QSPI_BASE_CLOCK_FREQ 96000000uL @@ -177,7 +185,9 @@ typedef enum typedef enum { NRF_QSPI_MODE_0 = QSPI_IFCONFIG1_SPIMODE_MODE0, /**< Mode 0 (CPOL=0, CPHA=0). */ +#if NRF_QSPI_HAS_MODE_1 NRF_QSPI_MODE_1 = QSPI_IFCONFIG1_SPIMODE_MODE3 /**< Mode 1 (CPOL=1, CPHA=1). */ +#endif } nrf_qspi_spi_mode_t; /** @brief Addressing configuration mode. */ @@ -665,9 +675,11 @@ NRF_STATIC_INLINE void nrf_qspi_enable(NRF_QSPI_Type * p_reg) NRF_STATIC_INLINE void nrf_qspi_disable(NRF_QSPI_Type * p_reg) { - // Workaround for nRF52840 anomaly 122: Current consumption is too high. - *(volatile uint32_t *)0x40029054ul = 1ul; - + if (nrf52_errata_122()) + { + // Workaround for anomaly 122: "QSPI: QSPI uses current after being disabled". + *(volatile uint32_t *)0x40029054ul = 1ul; + } p_reg->ENABLE = (QSPI_ENABLE_ENABLE_Disabled << QSPI_ENABLE_ENABLE_Pos); } diff --git a/hal/nrf_radio.h b/hal/nrf_radio.h index d3e087d340..8965d8b10e 100644 --- a/hal/nrf_radio.h +++ b/hal/nrf_radio.h @@ -530,7 +530,9 @@ NRF_STATIC_INLINE uint8_t nrf_radio_dai_get(NRF_RADIO_Type const * p_reg); * @retval 1 The payload is greater than PCNF1.MAXLEN. */ NRF_STATIC_INLINE uint8_t nrf_radio_pdustat_get(NRF_RADIO_Type const * p_reg); +#endif // defined(RADIO_PDUSTAT_PDUSTAT_Msk) || defined(__NRFX_DOXYGEN__) +#if defined(RADIO_PDUSTAT_CISTAT_Msk) || defined(__NRFX_DOXYGEN__) /** * @brief Function for getting status on what rate packet is received with in Long Range. * @@ -540,7 +542,7 @@ NRF_STATIC_INLINE uint8_t nrf_radio_pdustat_get(NRF_RADIO_Type const * p_reg); * @retval 1 The frame is received at 500kbps. */ NRF_STATIC_INLINE uint8_t nrf_radio_cistat_get(NRF_RADIO_Type const * p_reg); -#endif // defined(RADIO_PDUSTAT_PDUSTAT_Msk) || defined(__NRFX_DOXYGEN__) +#endif // defined(RADIO_PDUSTAT_CISTAT_Msk) || defined(__NRFX_DOXYGEN__) /** * @brief Function for setting packet pointer to given location in memory. @@ -1051,10 +1053,7 @@ NRF_STATIC_INLINE uint32_t nrf_radio_task_address_get(NRF_RADIO_Type const * p_r NRF_STATIC_INLINE void nrf_radio_event_clear(NRF_RADIO_Type * p_reg, nrf_radio_event_t event) { *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL; -#if __CORTEX_M == 0x04 - volatile uint32_t dummy = *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)); - (void)dummy; -#endif + nrf_event_readback((uint8_t *)p_reg + (uint32_t)event); } NRF_STATIC_INLINE bool nrf_radio_event_check(NRF_RADIO_Type const * p_reg, nrf_radio_event_t event) @@ -1129,12 +1128,14 @@ NRF_STATIC_INLINE uint8_t nrf_radio_pdustat_get(NRF_RADIO_Type const * p_reg) { return (uint8_t)(p_reg->PDUSTAT & RADIO_PDUSTAT_PDUSTAT_Msk); } +#endif +#if defined(RADIO_PDUSTAT_CISTAT_Msk) NRF_STATIC_INLINE uint8_t nrf_radio_cistat_get(NRF_RADIO_Type const * p_reg) { return (uint8_t)((p_reg->PDUSTAT & RADIO_PDUSTAT_CISTAT_Msk) >> RADIO_PDUSTAT_CISTAT_Pos); } -#endif // defined(RADIO_PDUSTAT_PDUSTAT_Msk) +#endif NRF_STATIC_INLINE void nrf_radio_packetptr_set(NRF_RADIO_Type * p_reg, void const * p_packet) { diff --git a/hal/nrf_reset.h b/hal/nrf_reset.h index b9292c0453..a9e83ac633 100644 --- a/hal/nrf_reset.h +++ b/hal/nrf_reset.h @@ -38,6 +38,20 @@ extern "C" { #endif +#if defined(NRF5340_XXAA_NETWORK) || defined(__NRFX_DOXYGEN__) +/** @brief Presence of Network core RESET functionality. */ +#define NRF_RESET_HAS_NETWORK 1 +#else +#define NRF_RESET_HAS_NETWORK 0 +#endif + +#if defined(NRF5340_XXAA_APPLICATION) || defined(__NRFX_DOXYGEN__) +/** @brief Presence of Application core RESET functionality. */ +#define NRF_RESET_HAS_APPLICATION 1 +#else +#define NRF_RESET_HAS_APPLICATION 0 +#endif + /** * @defgroup nrf_reset_hal RESET HAL * @{ @@ -56,14 +70,18 @@ typedef enum NRF_RESET_RESETREAS_OFF_MASK = RESET_RESETREAS_OFF_Msk, ///< Bit mask of OFF field. NRF_RESET_RESETREAS_LPCOMP_MASK = RESET_RESETREAS_LPCOMP_Msk, ///< Bit mask of LPCOMP field. NRF_RESET_RESETREAS_DIF_MASK = RESET_RESETREAS_DIF_Msk, ///< Bit mask of DIF field. +#if NRF_RESET_HAS_NETWORK NRF_RESET_RESETREAS_LSREQ_MASK = RESET_RESETREAS_LSREQ_Msk, ///< Bit mask of LSREQ field. NRF_RESET_RESETREAS_LLOCKUP_MASK = RESET_RESETREAS_LLOCKUP_Msk, ///< Bit mask of LLOCKUP field. NRF_RESET_RESETREAS_LDOG_MASK = RESET_RESETREAS_LDOG_Msk, ///< Bit mask of LDOG field. NRF_RESET_RESETREAS_MFORCEOFF_MASK = RESET_RESETREAS_MFORCEOFF_Msk, ///< Bit mask of MFORCEOFF field. +#endif NRF_RESET_RESETREAS_NFC_MASK = RESET_RESETREAS_NFC_Msk, ///< Bit mask of NFC field. NRF_RESET_RESETREAS_DOG1_MASK = RESET_RESETREAS_DOG1_Msk, ///< Bit mask of DOG1 field. NRF_RESET_RESETREAS_VBUS_MASK = RESET_RESETREAS_VBUS_Msk, ///< Bit mask of VBUS field. +#if NRF_RESET_HAS_NETWORK NRF_RESET_RESETREAS_LCTRLAP_MASK = RESET_RESETREAS_LCTRLAP_Msk, ///< Bit mask of LCTRLAP field. +#endif } nrf_reset_resetreas_mask_t; /** @@ -88,6 +106,7 @@ NRF_STATIC_INLINE uint32_t nrf_reset_resetreas_get(NRF_RESET_Type const * p_reg) */ NRF_STATIC_INLINE void nrf_reset_resetreas_clear(NRF_RESET_Type * p_reg, uint32_t mask); +#if NRF_RESET_HAS_APPLICATION /** * @brief Function for setting the force off signal for the Network core. * @@ -98,6 +117,7 @@ NRF_STATIC_INLINE void nrf_reset_resetreas_clear(NRF_RESET_Type * p_reg, uint32_ * False if the force off signal is to be released. */ NRF_STATIC_INLINE void nrf_reset_network_force_off(NRF_RESET_Type * p_reg, bool hold); +#endif // NRF_RESET_HAS_APPLICATION #ifndef NRF_DECLARE_ONLY @@ -111,11 +131,13 @@ NRF_STATIC_INLINE void nrf_reset_resetreas_clear(NRF_RESET_Type * p_reg, uint32_ p_reg->RESETREAS = mask; } +#if NRF_RESET_HAS_APPLICATION NRF_STATIC_INLINE void nrf_reset_network_force_off(NRF_RESET_Type * p_reg, bool hold) { p_reg->NETWORK.FORCEOFF = (hold ? RESET_NETWORK_FORCEOFF_FORCEOFF_Hold : RESET_NETWORK_FORCEOFF_FORCEOFF_Release); } +#endif // NRF_RESET_HAS_APPLICATION #endif // NRF_DECLARE_ONLY diff --git a/hal/nrf_rng.h b/hal/nrf_rng.h index 26698e0a0e..20c1c9dcd4 100644 --- a/hal/nrf_rng.h +++ b/hal/nrf_rng.h @@ -227,10 +227,7 @@ NRF_STATIC_INLINE uint32_t nrf_rng_event_address_get(NRF_RNG_Type const * p_reg, NRF_STATIC_INLINE void nrf_rng_event_clear(NRF_RNG_Type * p_reg, nrf_rng_event_t rng_event) { *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)rng_event)) = 0x0UL; -#if __CORTEX_M == 0x04 - volatile uint32_t dummy = *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)rng_event)); - (void)dummy; -#endif + nrf_event_readback((uint8_t *)p_reg + (uint32_t)rng_event); } NRF_STATIC_INLINE bool nrf_rng_event_check(NRF_RNG_Type const * p_reg, nrf_rng_event_t rng_event) diff --git a/hal/nrf_rtc.h b/hal/nrf_rtc.h index 710b9439b2..ebaf4e6e9e 100644 --- a/hal/nrf_rtc.h +++ b/hal/nrf_rtc.h @@ -352,10 +352,7 @@ NRF_STATIC_INLINE bool nrf_rtc_event_check(NRF_RTC_Type const * p_reg, nrf_rtc_e NRF_STATIC_INLINE void nrf_rtc_event_clear(NRF_RTC_Type * p_reg, nrf_rtc_event_t event) { *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0; -#if __CORTEX_M == 0x04 - volatile uint32_t dummy = *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)); - (void)dummy; -#endif + nrf_event_readback((uint8_t *)p_reg + (uint32_t)event); } NRF_STATIC_INLINE uint32_t nrf_rtc_counter_get(NRF_RTC_Type const * p_reg) diff --git a/hal/nrf_saadc.h b/hal/nrf_saadc.h index fef39a39a2..2e662f5128 100644 --- a/hal/nrf_saadc.h +++ b/hal/nrf_saadc.h @@ -650,10 +650,7 @@ NRF_STATIC_INLINE bool nrf_saadc_event_check(NRF_SAADC_Type const * p_reg, nrf_s NRF_STATIC_INLINE void nrf_saadc_event_clear(NRF_SAADC_Type * p_reg, nrf_saadc_event_t event) { *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL; -#if __CORTEX_M == 0x04 - volatile uint32_t dummy = *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)); - (void)dummy; -#endif + nrf_event_readback((uint8_t *)p_reg + (uint32_t)event); } NRF_STATIC_INLINE uint32_t nrf_saadc_event_address_get(NRF_SAADC_Type const * p_reg, diff --git a/hal/nrf_spi.h b/hal/nrf_spi.h index 57a89bf1e7..fd1871f383 100644 --- a/hal/nrf_spi.h +++ b/hal/nrf_spi.h @@ -258,10 +258,7 @@ NRF_STATIC_INLINE void nrf_spi_event_clear(NRF_SPI_Type * p_reg, nrf_spi_event_t event) { *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL; -#if __CORTEX_M == 0x04 - volatile uint32_t dummy = *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)); - (void)dummy; -#endif + nrf_event_readback((uint8_t *)p_reg + (uint32_t)event); } NRF_STATIC_INLINE bool nrf_spi_event_check(NRF_SPI_Type const * p_reg, diff --git a/hal/nrf_spim.h b/hal/nrf_spim.h index c286f76d4e..c5a6a889bc 100644 --- a/hal/nrf_spim.h +++ b/hal/nrf_spim.h @@ -590,10 +590,7 @@ NRF_STATIC_INLINE void nrf_spim_event_clear(NRF_SPIM_Type * p_reg, nrf_spim_event_t event) { *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL; -#if __CORTEX_M == 0x04 - volatile uint32_t dummy = *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)); - (void)dummy; -#endif + nrf_event_readback((uint8_t *)p_reg + (uint32_t)event); } NRF_STATIC_INLINE bool nrf_spim_event_check(NRF_SPIM_Type const * p_reg, diff --git a/hal/nrf_spis.h b/hal/nrf_spis.h index caf5411c01..18b692b969 100644 --- a/hal/nrf_spis.h +++ b/hal/nrf_spis.h @@ -466,10 +466,7 @@ NRF_STATIC_INLINE void nrf_spis_event_clear(NRF_SPIS_Type * p_reg, nrf_spis_event_t event) { *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL; -#if __CORTEX_M == 0x04 - volatile uint32_t dummy = *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)); - (void)dummy; -#endif + nrf_event_readback((uint8_t *)p_reg + (uint32_t)event); } NRF_STATIC_INLINE bool nrf_spis_event_check(NRF_SPIS_Type const * p_reg, diff --git a/hal/nrf_temp.h b/hal/nrf_temp.h index 56e1d4308e..e2aad0f301 100644 --- a/hal/nrf_temp.h +++ b/hal/nrf_temp.h @@ -187,10 +187,7 @@ NRF_STATIC_INLINE uint32_t nrf_temp_event_address_get(NRF_TEMP_Type const * p_re NRF_STATIC_INLINE void nrf_temp_event_clear(NRF_TEMP_Type * p_reg, nrf_temp_event_t event) { *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0; -#if __CORTEX_M == 0x04 - volatile uint32_t dummy = *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)); - (void)dummy; -#endif + nrf_event_readback((uint8_t *)p_reg + (uint32_t)event); } NRF_STATIC_INLINE bool nrf_temp_event_check(NRF_TEMP_Type const * p_reg, nrf_temp_event_t event) diff --git a/hal/nrf_timer.h b/hal/nrf_timer.h index 86bf4ccf9d..eda7fe2e63 100644 --- a/hal/nrf_timer.h +++ b/hal/nrf_timer.h @@ -323,6 +323,15 @@ NRF_STATIC_INLINE void nrf_timer_shorts_enable(NRF_TIMER_Type * p_reg, NRF_STATIC_INLINE void nrf_timer_shorts_disable(NRF_TIMER_Type * p_reg, uint32_t mask); +/** + * @brief Function for setting the specified shortcuts. + * + * @param[in] p_reg Pointer to the structure of registers of the peripheral. + * @param[in] mask Shortcuts to be set. + */ +NRF_STATIC_INLINE void nrf_timer_shorts_set(NRF_TIMER_Type * p_reg, + uint32_t mask); + /** * @brief Function for enabling the specified interrupts. * @@ -563,10 +572,7 @@ NRF_STATIC_INLINE void nrf_timer_event_clear(NRF_TIMER_Type * p_reg, nrf_timer_event_t event) { *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL; -#if __CORTEX_M == 0x04 - volatile uint32_t dummy = *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)); - (void)dummy; -#endif + nrf_event_readback((uint8_t *)p_reg + (uint32_t)event); } NRF_STATIC_INLINE bool nrf_timer_event_check(NRF_TIMER_Type const * p_reg, @@ -593,6 +599,12 @@ NRF_STATIC_INLINE void nrf_timer_shorts_disable(NRF_TIMER_Type * p_reg, p_reg->SHORTS &= ~(mask); } +NRF_STATIC_INLINE void nrf_timer_shorts_set(NRF_TIMER_Type * p_reg, + uint32_t mask) +{ + p_reg->SHORTS = mask; +} + NRF_STATIC_INLINE void nrf_timer_int_enable(NRF_TIMER_Type * p_reg, uint32_t mask) { diff --git a/hal/nrf_twi.h b/hal/nrf_twi.h index b39f5f08a9..107c391bb1 100644 --- a/hal/nrf_twi.h +++ b/hal/nrf_twi.h @@ -324,10 +324,7 @@ NRF_STATIC_INLINE void nrf_twi_event_clear(NRF_TWI_Type * p_reg, nrf_twi_event_t event) { *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL; -#if __CORTEX_M == 0x04 - volatile uint32_t dummy = *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)); - (void)dummy; -#endif + nrf_event_readback((uint8_t *)p_reg + (uint32_t)event); } NRF_STATIC_INLINE bool nrf_twi_event_check(NRF_TWI_Type const * p_reg, diff --git a/hal/nrf_twim.h b/hal/nrf_twim.h index 18a94a0c7e..c5ed69b731 100644 --- a/hal/nrf_twim.h +++ b/hal/nrf_twim.h @@ -444,10 +444,7 @@ NRF_STATIC_INLINE void nrf_twim_event_clear(NRF_TWIM_Type * p_reg, nrf_twim_event_t event) { *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL; -#if __CORTEX_M == 0x04 - volatile uint32_t dummy = *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)); - (void)dummy; -#endif + nrf_event_readback((uint8_t *)p_reg + (uint32_t)event); } NRF_STATIC_INLINE bool nrf_twim_event_check(NRF_TWIM_Type const * p_reg, diff --git a/hal/nrf_twis.h b/hal/nrf_twis.h index 111a3694b7..6b5d5c34eb 100644 --- a/hal/nrf_twis.h +++ b/hal/nrf_twis.h @@ -565,10 +565,7 @@ NRF_STATIC_INLINE uint32_t nrf_twis_task_address_get(NRF_TWIS_Type const * p_reg NRF_STATIC_INLINE void nrf_twis_event_clear(NRF_TWIS_Type * p_reg, nrf_twis_event_t event) { *(nrf_twis_getRegPtr(p_reg, (uint32_t)event)) = 0UL; -#if __CORTEX_M == 0x04 - volatile uint32_t dummy = *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)); - (void)dummy; -#endif + nrf_event_readback((uint8_t *)p_reg + (uint32_t)event); } NRF_STATIC_INLINE bool nrf_twis_event_check(NRF_TWIS_Type const * p_reg, nrf_twis_event_t event) diff --git a/hal/nrf_uart.h b/hal/nrf_uart.h index 23bb553fc6..cbafa0a8ac 100644 --- a/hal/nrf_uart.h +++ b/hal/nrf_uart.h @@ -367,10 +367,7 @@ NRF_STATIC_INLINE void nrf_uart_baudrate_set(NRF_UART_Type * p_reg, nrf_uart_bau NRF_STATIC_INLINE void nrf_uart_event_clear(NRF_UART_Type * p_reg, nrf_uart_event_t event) { *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL; -#if __CORTEX_M == 0x04 - volatile uint32_t dummy = *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)); - (void)dummy; -#endif + nrf_event_readback((uint8_t *)p_reg + (uint32_t)event); } NRF_STATIC_INLINE bool nrf_uart_event_check(NRF_UART_Type const * p_reg, nrf_uart_event_t event) diff --git a/hal/nrf_uarte.h b/hal/nrf_uarte.h index 12f9386bca..fd1848d23d 100644 --- a/hal/nrf_uarte.h +++ b/hal/nrf_uarte.h @@ -469,10 +469,7 @@ NRF_STATIC_INLINE uint32_t nrf_uarte_rx_amount_get(NRF_UARTE_Type const * p_reg) NRF_STATIC_INLINE void nrf_uarte_event_clear(NRF_UARTE_Type * p_reg, nrf_uarte_event_t event) { *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL; -#if __CORTEX_M == 0x04 - volatile uint32_t dummy = *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)); - (void)dummy; -#endif + nrf_event_readback((uint8_t *)p_reg + (uint32_t)event); } NRF_STATIC_INLINE bool nrf_uarte_event_check(NRF_UARTE_Type const * p_reg, diff --git a/hal/nrf_wdt.h b/hal/nrf_wdt.h index 79f866c408..8df6be8295 100644 --- a/hal/nrf_wdt.h +++ b/hal/nrf_wdt.h @@ -317,10 +317,7 @@ NRF_STATIC_INLINE void nrf_wdt_task_trigger(NRF_WDT_Type * p_reg, nrf_wdt_task_t NRF_STATIC_INLINE void nrf_wdt_event_clear(NRF_WDT_Type * p_reg, nrf_wdt_event_t event) { *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL; -#if __CORTEX_M == 0x04 - volatile uint32_t dummy = *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)); - (void)dummy; -#endif + nrf_event_readback((uint8_t *)p_reg + (uint32_t)event); } NRF_STATIC_INLINE bool nrf_wdt_event_check(NRF_WDT_Type const * p_reg, nrf_wdt_event_t event) diff --git a/helpers/nrfx_reset_reason.h b/helpers/nrfx_reset_reason.h index 52033160b1..7b12be601b 100644 --- a/helpers/nrfx_reset_reason.h +++ b/helpers/nrfx_reset_reason.h @@ -78,6 +78,7 @@ typedef enum NRFX_RESET_REASON_DIF_MASK = RESET_RESETREAS_DIF_Msk, /**< Reset due to wakeup from System OFF mode when wakeup is triggered by entering the debug * interface mode. */ +#if NRF_RESET_HAS_NETWORK NRFX_RESET_REASON_LSREQ_MASK = RESET_RESETREAS_LSREQ_Msk, /**< Reset from network soft reset detected. */ NRFX_RESET_REASON_LLOCKUP_MASK = RESET_RESETREAS_LLOCKUP_Msk, @@ -86,14 +87,17 @@ typedef enum /**< Reset from network watchdog timer detected. */ NRFX_RESET_REASON_MFORCEOFF_MASK = RESET_RESETREAS_MFORCEOFF_Msk, /**< Force off reset from application core detected. */ +#endif // NRF_RESET_HAS_NETWORK NRFX_RESET_REASON_NFC_MASK = RESET_RESETREAS_NFC_Msk, /**< Reset after wakeup from System OFF mode due to NRF field being detected. */ NRFX_RESET_REASON_DOG1_MASK = RESET_RESETREAS_DOG1_Msk, /**< Reset from application watchdog timer 1 detected. */ NRFX_RESET_REASON_VBUS_MASK = RESET_RESETREAS_VBUS_Msk, /**< Reset after wakeup from System OFF mode due to VBUS rising into valid range. */ +#if NRF_RESET_HAS_NETWORK NRFX_RESET_REASON_LCTRLAP_MASK = RESET_RESETREAS_LCTRLAP_Msk, /**< Reset from network CTRL-AP detected. */ +#endif // NRF_RESET_HAS_NETWORK #else NRFX_RESET_REASON_RESETPIN_MASK = POWER_RESETREAS_RESETPIN_Msk, NRFX_RESET_REASON_DOG_MASK = POWER_RESETREAS_DOG_Msk, diff --git a/mdk/arm_startup_nrf52805.s b/mdk/arm_startup_nrf52805.s index f2c50add7b..bcbbfc4508 100644 --- a/mdk/arm_startup_nrf52805.s +++ b/mdk/arm_startup_nrf52805.s @@ -102,7 +102,7 @@ __Vectors DCD __initial_sp ; Top of Stack DCD CCM_AAR_IRQHandler DCD WDT_IRQHandler DCD RTC1_IRQHandler - DCD 0 ; Reserved + DCD QDEC_IRQHandler DCD 0 ; Reserved DCD SWI0_EGU0_IRQHandler DCD SWI1_EGU1_IRQHandler @@ -281,6 +281,7 @@ Default_Handler PROC EXPORT CCM_AAR_IRQHandler [WEAK] EXPORT WDT_IRQHandler [WEAK] EXPORT RTC1_IRQHandler [WEAK] + EXPORT QDEC_IRQHandler [WEAK] EXPORT SWI0_EGU0_IRQHandler [WEAK] EXPORT SWI1_EGU1_IRQHandler [WEAK] EXPORT SWI2_IRQHandler [WEAK] @@ -304,6 +305,7 @@ ECB_IRQHandler CCM_AAR_IRQHandler WDT_IRQHandler RTC1_IRQHandler +QDEC_IRQHandler SWI0_EGU0_IRQHandler SWI1_EGU1_IRQHandler SWI2_IRQHandler diff --git a/mdk/compiler_abstraction.h b/mdk/compiler_abstraction.h index a686b5cc6d..77a495ab08 100644 --- a/mdk/compiler_abstraction.h +++ b/mdk/compiler_abstraction.h @@ -35,6 +35,18 @@ POSSIBILITY OF SUCH DAMAGE. /*lint ++flb "Enter library region" */ +#ifndef NRF_STRING_CONCATENATE_IMPL + #define NRF_STRING_CONCATENATE_IMPL(lhs, rhs) lhs ## rhs +#endif +#ifndef NRF_STRING_CONCATENATE + #define NRF_STRING_CONCATENATE(lhs, rhs) NRF_STRING_CONCATENATE_IMPL(lhs, rhs) +#endif +#if __LINT__ == 1 + #ifndef NRF_STATIC_ASSERT + #define NRF_STATIC_ASSERT(cond, msg) + #endif +#endif + #if defined ( __CC_ARM ) #ifndef __ASM @@ -62,6 +74,11 @@ POSSIBILITY OF SUCH DAMAGE. #endif #define GET_SP() __current_sp() + + #ifndef NRF_STATIC_ASSERT + #define NRF_STATIC_ASSERT(cond, msg) \ + ;enum { NRF_STRING_CONCATENATE(static_assert_on_line_, __LINE__) = 1 / (!!(cond)) } + #endif #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) @@ -91,6 +108,10 @@ POSSIBILITY OF SUCH DAMAGE. #define GET_SP() __current_sp() + #ifndef NRF_STATIC_ASSERT + #define NRF_STATIC_ASSERT(cond, msg) _Static_assert(cond, msg) + #endif + #elif defined ( __ICCARM__ ) #ifndef __ASM @@ -120,7 +141,11 @@ POSSIBILITY OF SUCH DAMAGE. #define GET_SP() __get_SP() -#elif defined ( __GNUC__ ) + #ifndef NRF_STATIC_ASSERT + #define NRF_STATIC_ASSERT(cond, msg) static_assert(cond, msg) + #endif + +#elif defined ( __GNUC__ ) || defined ( __clang__ ) #ifndef __ASM #define __ASM __asm @@ -155,6 +180,10 @@ POSSIBILITY OF SUCH DAMAGE. return stack_pointer; } + #ifndef NRF_STATIC_ASSERT + #define NRF_STATIC_ASSERT(cond, msg) _Static_assert(cond, msg) + #endif + #elif defined ( __TASKING__ ) #ifndef __ASM @@ -184,8 +213,28 @@ POSSIBILITY OF SUCH DAMAGE. #define GET_SP() __get_MSP() + #ifndef NRF_STATIC_ASSERT + #define NRF_STATIC_ASSERT(cond, msg) static_assert(cond, msg) + #endif + #endif +#define NRF_MDK_VERSION_ASSERT_AT_LEAST(major, minor, micro) \ + NRF_STATIC_ASSERT( \ + ( \ + (major < MDK_MAJOR_VERSION) || \ + (major == MDK_MAJOR_VERSION && minor < MDK_MINOR_VERSION) || \ + (major == MDK_MAJOR_VERSION && minor == MDK_MINOR_VERSION && micro < MDK_MICRO_VERSION) \ + ), "MDK version mismatch.") + +#define NRF_MDK_VERSION_ASSERT_EXACT(major, minor, micro) \ + NRF_STATIC_ASSERT( \ + ( \ + (major != MDK_MAJOR_VERSION) || \ + (major != MDK_MAJOR_VERSION) || \ + (major != MDK_MAJOR_VERSION) \ + ), "MDK version mismatch.") + /*lint --flb "Leave library region" */ #endif diff --git a/mdk/gcc_startup_nrf51.S b/mdk/gcc_startup_nrf51.S index aff26f2085..4665eac6c1 100644 --- a/mdk/gcc_startup_nrf51.S +++ b/mdk/gcc_startup_nrf51.S @@ -156,10 +156,11 @@ Reset_Handler: * __etext: LMA of start of the section to copy from. Usually end of text * __data_start__: VMA of start of the section to copy to. * __bss_start__: VMA of end of the section to copy to. Normally __data_end__ is used, but by using __bss_start__ - * the user can add their own initialized data section before BSS section with the INTERT AFTER command. + * the user can add their own initialized data section before BSS section with the INSERT AFTER command. * * All addresses must be aligned to 4 bytes boundary. */ +#ifndef __STARTUP_SKIP_ETEXT ldr r1, =__etext ldr r2, =__data_start__ ldr r3, =__bss_start__ @@ -174,6 +175,7 @@ Reset_Handler: bgt .L_loop1 .L_loop1_done: +#endif /* This part of work usually is done in C library startup code. Otherwise, * define __STARTUP_CLEAR_BSS to enable it in this startup. This section diff --git a/mdk/gcc_startup_nrf52.S b/mdk/gcc_startup_nrf52.S index dc9d5c62ba..1e9997f2c0 100644 --- a/mdk/gcc_startup_nrf52.S +++ b/mdk/gcc_startup_nrf52.S @@ -222,10 +222,11 @@ Reset_Handler: * __etext: LMA of start of the section to copy from. Usually end of text * __data_start__: VMA of start of the section to copy to. * __bss_start__: VMA of end of the section to copy to. Normally __data_end__ is used, but by using __bss_start__ - * the user can add their own initialized data section before BSS section with the INTERT AFTER command. + * the user can add their own initialized data section before BSS section with the INSERT AFTER command. * * All addresses must be aligned to 4 bytes boundary. */ +#ifndef __STARTUP_SKIP_ETEXT ldr r1, =__etext ldr r2, =__data_start__ ldr r3, =__bss_start__ @@ -240,6 +241,7 @@ Reset_Handler: bgt .L_loop1 .L_loop1_done: +#endif /* This part of work usually is done in C library startup code. Otherwise, * define __STARTUP_CLEAR_BSS to enable it in this startup. This section diff --git a/mdk/gcc_startup_nrf52805.S b/mdk/gcc_startup_nrf52805.S index dd661e6843..da82da7697 100644 --- a/mdk/gcc_startup_nrf52805.S +++ b/mdk/gcc_startup_nrf52805.S @@ -108,7 +108,7 @@ __isr_vector: .long CCM_AAR_IRQHandler .long WDT_IRQHandler .long RTC1_IRQHandler - .long 0 /*Reserved */ + .long QDEC_IRQHandler .long 0 /*Reserved */ .long SWI0_EGU0_IRQHandler .long SWI1_EGU1_IRQHandler @@ -222,10 +222,11 @@ Reset_Handler: * __etext: LMA of start of the section to copy from. Usually end of text * __data_start__: VMA of start of the section to copy to. * __bss_start__: VMA of end of the section to copy to. Normally __data_end__ is used, but by using __bss_start__ - * the user can add their own initialized data section before BSS section with the INTERT AFTER command. + * the user can add their own initialized data section before BSS section with the INSERT AFTER command. * * All addresses must be aligned to 4 bytes boundary. */ +#ifndef __STARTUP_SKIP_ETEXT ldr r1, =__etext ldr r2, =__data_start__ ldr r3, =__bss_start__ @@ -240,6 +241,7 @@ Reset_Handler: bgt .L_loop1 .L_loop1_done: +#endif /* This part of work usually is done in C library startup code. Otherwise, * define __STARTUP_CLEAR_BSS to enable it in this startup. This section @@ -380,6 +382,7 @@ Default_Handler: IRQ CCM_AAR_IRQHandler IRQ WDT_IRQHandler IRQ RTC1_IRQHandler + IRQ QDEC_IRQHandler IRQ SWI0_EGU0_IRQHandler IRQ SWI1_EGU1_IRQHandler IRQ SWI2_IRQHandler diff --git a/mdk/gcc_startup_nrf52810.S b/mdk/gcc_startup_nrf52810.S index 6524dbccf9..dc84105e58 100644 --- a/mdk/gcc_startup_nrf52810.S +++ b/mdk/gcc_startup_nrf52810.S @@ -245,10 +245,11 @@ skip: * __etext: LMA of start of the section to copy from. Usually end of text * __data_start__: VMA of start of the section to copy to. * __bss_start__: VMA of end of the section to copy to. Normally __data_end__ is used, but by using __bss_start__ - * the user can add their own initialized data section before BSS section with the INTERT AFTER command. + * the user can add their own initialized data section before BSS section with the INSERT AFTER command. * * All addresses must be aligned to 4 bytes boundary. */ +#ifndef __STARTUP_SKIP_ETEXT ldr r1, =__etext ldr r2, =__data_start__ ldr r3, =__bss_start__ @@ -263,6 +264,7 @@ skip: bgt .L_loop1 .L_loop1_done: +#endif /* This part of work usually is done in C library startup code. Otherwise, * define __STARTUP_CLEAR_BSS to enable it in this startup. This section diff --git a/mdk/gcc_startup_nrf52811.S b/mdk/gcc_startup_nrf52811.S index f2eaba7c46..f6929fcc47 100644 --- a/mdk/gcc_startup_nrf52811.S +++ b/mdk/gcc_startup_nrf52811.S @@ -222,10 +222,11 @@ Reset_Handler: * __etext: LMA of start of the section to copy from. Usually end of text * __data_start__: VMA of start of the section to copy to. * __bss_start__: VMA of end of the section to copy to. Normally __data_end__ is used, but by using __bss_start__ - * the user can add their own initialized data section before BSS section with the INTERT AFTER command. + * the user can add their own initialized data section before BSS section with the INSERT AFTER command. * * All addresses must be aligned to 4 bytes boundary. */ +#ifndef __STARTUP_SKIP_ETEXT ldr r1, =__etext ldr r2, =__data_start__ ldr r3, =__bss_start__ @@ -240,6 +241,7 @@ Reset_Handler: bgt .L_loop1 .L_loop1_done: +#endif /* This part of work usually is done in C library startup code. Otherwise, * define __STARTUP_CLEAR_BSS to enable it in this startup. This section diff --git a/mdk/gcc_startup_nrf52820.S b/mdk/gcc_startup_nrf52820.S index 94c4abb9cd..8e4c2d8bc2 100644 --- a/mdk/gcc_startup_nrf52820.S +++ b/mdk/gcc_startup_nrf52820.S @@ -222,10 +222,11 @@ Reset_Handler: * __etext: LMA of start of the section to copy from. Usually end of text * __data_start__: VMA of start of the section to copy to. * __bss_start__: VMA of end of the section to copy to. Normally __data_end__ is used, but by using __bss_start__ - * the user can add their own initialized data section before BSS section with the INTERT AFTER command. + * the user can add their own initialized data section before BSS section with the INSERT AFTER command. * * All addresses must be aligned to 4 bytes boundary. */ +#ifndef __STARTUP_SKIP_ETEXT ldr r1, =__etext ldr r2, =__data_start__ ldr r3, =__bss_start__ @@ -240,6 +241,7 @@ Reset_Handler: bgt .L_loop1 .L_loop1_done: +#endif /* This part of work usually is done in C library startup code. Otherwise, * define __STARTUP_CLEAR_BSS to enable it in this startup. This section diff --git a/mdk/gcc_startup_nrf52833.S b/mdk/gcc_startup_nrf52833.S index 1e1b03e51e..16030a7eee 100644 --- a/mdk/gcc_startup_nrf52833.S +++ b/mdk/gcc_startup_nrf52833.S @@ -222,10 +222,11 @@ Reset_Handler: * __etext: LMA of start of the section to copy from. Usually end of text * __data_start__: VMA of start of the section to copy to. * __bss_start__: VMA of end of the section to copy to. Normally __data_end__ is used, but by using __bss_start__ - * the user can add their own initialized data section before BSS section with the INTERT AFTER command. + * the user can add their own initialized data section before BSS section with the INSERT AFTER command. * * All addresses must be aligned to 4 bytes boundary. */ +#ifndef __STARTUP_SKIP_ETEXT ldr r1, =__etext ldr r2, =__data_start__ ldr r3, =__bss_start__ @@ -240,6 +241,7 @@ Reset_Handler: bgt .L_loop1 .L_loop1_done: +#endif /* This part of work usually is done in C library startup code. Otherwise, * define __STARTUP_CLEAR_BSS to enable it in this startup. This section diff --git a/mdk/gcc_startup_nrf52840.S b/mdk/gcc_startup_nrf52840.S index ada1448fa9..d7f793d5a7 100644 --- a/mdk/gcc_startup_nrf52840.S +++ b/mdk/gcc_startup_nrf52840.S @@ -222,10 +222,11 @@ Reset_Handler: * __etext: LMA of start of the section to copy from. Usually end of text * __data_start__: VMA of start of the section to copy to. * __bss_start__: VMA of end of the section to copy to. Normally __data_end__ is used, but by using __bss_start__ - * the user can add their own initialized data section before BSS section with the INTERT AFTER command. + * the user can add their own initialized data section before BSS section with the INSERT AFTER command. * * All addresses must be aligned to 4 bytes boundary. */ +#ifndef __STARTUP_SKIP_ETEXT ldr r1, =__etext ldr r2, =__data_start__ ldr r3, =__bss_start__ @@ -240,6 +241,7 @@ Reset_Handler: bgt .L_loop1 .L_loop1_done: +#endif /* This part of work usually is done in C library startup code. Otherwise, * define __STARTUP_CLEAR_BSS to enable it in this startup. This section diff --git a/mdk/gcc_startup_nrf5340_application.S b/mdk/gcc_startup_nrf5340_application.S index 755141dc7e..a1d7ad0dc5 100644 --- a/mdk/gcc_startup_nrf5340_application.S +++ b/mdk/gcc_startup_nrf5340_application.S @@ -350,10 +350,11 @@ Reset_Handler: * __etext: LMA of start of the section to copy from. Usually end of text * __data_start__: VMA of start of the section to copy to. * __bss_start__: VMA of end of the section to copy to. Normally __data_end__ is used, but by using __bss_start__ - * the user can add their own initialized data section before BSS section with the INTERT AFTER command. + * the user can add their own initialized data section before BSS section with the INSERT AFTER command. * * All addresses must be aligned to 4 bytes boundary. */ +#ifndef __STARTUP_SKIP_ETEXT ldr r1, =__etext ldr r2, =__data_start__ ldr r3, =__bss_start__ @@ -368,6 +369,7 @@ Reset_Handler: bgt .L_loop1 .L_loop1_done: +#endif /* This part of work usually is done in C library startup code. Otherwise, * define __STARTUP_CLEAR_BSS to enable it in this startup. This section diff --git a/mdk/gcc_startup_nrf5340_network.S b/mdk/gcc_startup_nrf5340_network.S index 0be2c33198..fcbd8cd7d6 100644 --- a/mdk/gcc_startup_nrf5340_network.S +++ b/mdk/gcc_startup_nrf5340_network.S @@ -239,10 +239,11 @@ Reset_Handler: * __etext: LMA of start of the section to copy from. Usually end of text * __data_start__: VMA of start of the section to copy to. * __bss_start__: VMA of end of the section to copy to. Normally __data_end__ is used, but by using __bss_start__ - * the user can add their own initialized data section before BSS section with the INTERT AFTER command. + * the user can add their own initialized data section before BSS section with the INSERT AFTER command. * * All addresses must be aligned to 4 bytes boundary. */ +#ifndef __STARTUP_SKIP_ETEXT ldr r1, =__etext ldr r2, =__data_start__ ldr r3, =__bss_start__ @@ -257,6 +258,7 @@ Reset_Handler: bgt .L_loop1 .L_loop1_done: +#endif /* This part of work usually is done in C library startup code. Otherwise, * define __STARTUP_CLEAR_BSS to enable it in this startup. This section diff --git a/mdk/gcc_startup_nrf9160.S b/mdk/gcc_startup_nrf9160.S index 2737d06d66..81b4187289 100644 --- a/mdk/gcc_startup_nrf9160.S +++ b/mdk/gcc_startup_nrf9160.S @@ -350,10 +350,11 @@ Reset_Handler: * __etext: LMA of start of the section to copy from. Usually end of text * __data_start__: VMA of start of the section to copy to. * __bss_start__: VMA of end of the section to copy to. Normally __data_end__ is used, but by using __bss_start__ - * the user can add their own initialized data section before BSS section with the INTERT AFTER command. + * the user can add their own initialized data section before BSS section with the INSERT AFTER command. * * All addresses must be aligned to 4 bytes boundary. */ +#ifndef __STARTUP_SKIP_ETEXT ldr r1, =__etext ldr r2, =__data_start__ ldr r3, =__bss_start__ @@ -368,6 +369,7 @@ Reset_Handler: bgt .L_loop1 .L_loop1_done: +#endif /* This part of work usually is done in C library startup code. Otherwise, * define __STARTUP_CLEAR_BSS to enable it in this startup. This section diff --git a/mdk/iar_startup_nrf52805.s b/mdk/iar_startup_nrf52805.s index 79a6880c62..62508371f4 100644 --- a/mdk/iar_startup_nrf52805.s +++ b/mdk/iar_startup_nrf52805.s @@ -103,7 +103,7 @@ __vector_table DCD CCM_AAR_IRQHandler DCD WDT_IRQHandler DCD RTC1_IRQHandler - DCD 0 ; Reserved + DCD QDEC_IRQHandler DCD 0 ; Reserved DCD SWI0_EGU0_IRQHandler DCD SWI1_EGU1_IRQHandler @@ -351,6 +351,11 @@ WDT_IRQHandler RTC1_IRQHandler B . + PUBWEAK QDEC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +QDEC_IRQHandler + B . + PUBWEAK SWI0_EGU0_IRQHandler SECTION .text:CODE:REORDER:NOROOT(1) SWI0_EGU0_IRQHandler diff --git a/mdk/nrf.h b/mdk/nrf.h index 18783ae867..660ddc3318 100644 --- a/mdk/nrf.h +++ b/mdk/nrf.h @@ -35,8 +35,8 @@ POSSIBILITY OF SUCH DAMAGE. /* MDK version */ #define MDK_MAJOR_VERSION 8 -#define MDK_MINOR_VERSION 32 -#define MDK_MICRO_VERSION 1 +#define MDK_MINOR_VERSION 35 +#define MDK_MICRO_VERSION 0 /* Define NRF51_SERIES for common use in nRF51 series devices. Only if not previously defined. */ #if defined (NRF51) ||\ @@ -116,81 +116,71 @@ POSSIBILITY OF SUCH DAMAGE. #endif #endif -#if defined(_WIN32) - /* Do not include nrf specific files when building for PC host */ -#elif defined(__unix) - /* Do not include nrf specific files when building for PC host */ -#elif defined(__APPLE__) - /* Do not include nrf specific files when building for PC host */ -#else - - /* Device selection for device includes. */ - #if defined (NRF51) - #include "nrf51.h" - #include "nrf51_bitfields.h" - #include "nrf51_deprecated.h" - - #elif defined (NRF52805_XXAA) - #include "nrf52805.h" - #include "nrf52805_bitfields.h" - #include "nrf51_to_nrf52810.h" - #include "nrf52_to_nrf52810.h" - #include "nrf52810_to_nrf52811.h" - #elif defined (NRF52810_XXAA) - #include "nrf52810.h" - #include "nrf52810_bitfields.h" - #include "nrf51_to_nrf52810.h" - #include "nrf52_to_nrf52810.h" - #include "nrf52810_name_change.h" - #elif defined (NRF52811_XXAA) - #include "nrf52811.h" - #include "nrf52811_bitfields.h" - #include "nrf51_to_nrf52810.h" - #include "nrf52_to_nrf52810.h" - #include "nrf52810_to_nrf52811.h" - #elif defined (NRF52820_XXAA) - #include "nrf52820.h" - #include "nrf52820_bitfields.h" - #include "nrf51_to_nrf52.h" - #include "nrf52_to_nrf52833.h" - #include "nrf52833_to_nrf52820.h" - #elif defined (NRF52832_XXAA) || defined (NRF52832_XXAB) - #include "nrf52.h" - #include "nrf52_bitfields.h" - #include "nrf51_to_nrf52.h" - #include "nrf52_name_change.h" - #elif defined (NRF52833_XXAA) - #include "nrf52833.h" - #include "nrf52833_bitfields.h" - #include "nrf52_to_nrf52833.h" - #include "nrf51_to_nrf52.h" - #elif defined (NRF52840_XXAA) - #include "nrf52840.h" - #include "nrf52840_bitfields.h" - #include "nrf51_to_nrf52840.h" - #include "nrf52_to_nrf52840.h" - - #elif defined (NRF5340_XXAA) - #if defined(NRF_APPLICATION) - #include "nrf5340_application.h" - #include "nrf5340_application_bitfields.h" - #elif defined (NRF_NETWORK) - #include "nrf5340_network.h" - #include "nrf5340_network_bitfields.h" - #endif +/* Device selection for device includes. */ +#if defined (NRF51) + #include "nrf51.h" + #include "nrf51_bitfields.h" + #include "nrf51_deprecated.h" + +#elif defined (NRF52805_XXAA) + #include "nrf52805.h" + #include "nrf52805_bitfields.h" + #include "nrf51_to_nrf52810.h" + #include "nrf52_to_nrf52810.h" + #include "nrf52810_to_nrf52811.h" +#elif defined (NRF52810_XXAA) + #include "nrf52810.h" + #include "nrf52810_bitfields.h" + #include "nrf51_to_nrf52810.h" + #include "nrf52_to_nrf52810.h" + #include "nrf52810_name_change.h" +#elif defined (NRF52811_XXAA) + #include "nrf52811.h" + #include "nrf52811_bitfields.h" + #include "nrf51_to_nrf52810.h" + #include "nrf52_to_nrf52810.h" + #include "nrf52810_to_nrf52811.h" +#elif defined (NRF52820_XXAA) + #include "nrf52820.h" + #include "nrf52820_bitfields.h" + #include "nrf51_to_nrf52.h" + #include "nrf52_to_nrf52833.h" + #include "nrf52833_to_nrf52820.h" +#elif defined (NRF52832_XXAA) || defined (NRF52832_XXAB) + #include "nrf52.h" + #include "nrf52_bitfields.h" + #include "nrf51_to_nrf52.h" + #include "nrf52_name_change.h" +#elif defined (NRF52833_XXAA) + #include "nrf52833.h" + #include "nrf52833_bitfields.h" + #include "nrf52_to_nrf52833.h" + #include "nrf51_to_nrf52.h" +#elif defined (NRF52840_XXAA) + #include "nrf52840.h" + #include "nrf52840_bitfields.h" + #include "nrf51_to_nrf52840.h" + #include "nrf52_to_nrf52840.h" + +#elif defined (NRF5340_XXAA) + #if defined(NRF_APPLICATION) + #include "nrf5340_application.h" + #include "nrf5340_application_bitfields.h" + #elif defined (NRF_NETWORK) + #include "nrf5340_network.h" + #include "nrf5340_network_bitfields.h" + #endif - #elif defined (NRF9160_XXAA) - #include "nrf9160.h" - #include "nrf9160_bitfields.h" - #include "nrf9160_name_change.h" - - #else - #error "Device must be defined. See nrf.h." - #endif /* NRF51, NRF52805_XXAA, NRF52810_XXAA, NRF52811_XXAA, NRF52820_XXAA, NRF52832_XXAA, NRF52832_XXAB, NRF52833_XXAA, NRF52840_XXAA, NRF5340_XXAA_APPLICATION, NRF5340_XXAA_NETWORK, NRF9160_XXAA */ +#elif defined (NRF9160_XXAA) + #include "nrf9160.h" + #include "nrf9160_bitfields.h" + #include "nrf9160_name_change.h" - #include "compiler_abstraction.h" +#else + #error "Device must be defined. See nrf.h." +#endif /* NRF51, NRF52805_XXAA, NRF52810_XXAA, NRF52811_XXAA, NRF52820_XXAA, NRF52832_XXAA, NRF52832_XXAB, NRF52833_XXAA, NRF52840_XXAA, NRF5340_XXAA_APPLICATION, NRF5340_XXAA_NETWORK, NRF9160_XXAA */ -#endif /* _WIN32 || __unix || __APPLE__ */ +#include "compiler_abstraction.h" #endif /* NRF_H */ diff --git a/mdk/nrf51.h b/mdk/nrf51.h index 3beac35dfd..b1ebabf9f0 100644 --- a/mdk/nrf51.h +++ b/mdk/nrf51.h @@ -30,10 +30,10 @@ * @file nrf51.h * @brief CMSIS HeaderFile * @version 522 - * @date 04. March 2020 - * @note Generated by SVDConv V3.3.25 on Wednesday, 04.03.2020 14:56:51 + * @date 14. August 2020 + * @note Generated by SVDConv V3.3.35 on Friday, 14.08.2020 15:02:12 * from File 'nrf51.svd', - * last modified on Wednesday, 04.03.2020 13:56:43 + * last modified on Friday, 14.08.2020 13:02:06 */ diff --git a/mdk/nrf51422_peripherals.h b/mdk/nrf51422_peripherals.h index 1d309429e0..790f0b3359 100644 --- a/mdk/nrf51422_peripherals.h +++ b/mdk/nrf51422_peripherals.h @@ -71,6 +71,8 @@ POSSIBILITY OF SUCH DAMAGE. #define RADIO_PRESENT #define RADIO_COUNT 1 +#define RADIO_TXPOWER_TXPOWER_Max RADIO_TXPOWER_TXPOWER_Pos4dBm + /* Accelerated Address Resolver */ #define AAR_PRESENT #define AAR_COUNT 1 diff --git a/mdk/nrf51422_xxaa.ld b/mdk/nrf51422_xxaa.ld new file mode 100644 index 0000000000..a36a3c4dde --- /dev/null +++ b/mdk/nrf51422_xxaa.ld @@ -0,0 +1,13 @@ +/* Linker script to configure memory regions. */ + +SEARCH_DIR(.) +GROUP(-lgcc -lc -lnosys) + +MEMORY +{ + FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 0x40000 + RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x4000 +} + + +INCLUDE "nrf_common.ld" diff --git a/mdk/nrf51422_xxab.ld b/mdk/nrf51422_xxab.ld new file mode 100644 index 0000000000..7bfec18577 --- /dev/null +++ b/mdk/nrf51422_xxab.ld @@ -0,0 +1,13 @@ +/* Linker script to configure memory regions. */ + +SEARCH_DIR(.) +GROUP(-lgcc -lc -lnosys) + +MEMORY +{ + FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 0x20000 + RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x4000 +} + + +INCLUDE "nrf_common.ld" diff --git a/mdk/nrf51422_xxac.ld b/mdk/nrf51422_xxac.ld new file mode 100644 index 0000000000..a6e98ba330 --- /dev/null +++ b/mdk/nrf51422_xxac.ld @@ -0,0 +1,13 @@ +/* Linker script to configure memory regions. */ + +SEARCH_DIR(.) +GROUP(-lgcc -lc -lnosys) + +MEMORY +{ + FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 0x40000 + RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x8000 +} + + +INCLUDE "nrf_common.ld" diff --git a/mdk/nrf51801_peripherals.h b/mdk/nrf51801_peripherals.h index 3fac4ff29e..8aa5a3b137 100644 --- a/mdk/nrf51801_peripherals.h +++ b/mdk/nrf51801_peripherals.h @@ -71,6 +71,8 @@ POSSIBILITY OF SUCH DAMAGE. #define RADIO_PRESENT #define RADIO_COUNT 1 +#define RADIO_TXPOWER_TXPOWER_Max RADIO_TXPOWER_TXPOWER_Pos4dBm + /* Accelerated Address Resolver */ #define AAR_PRESENT #define AAR_COUNT 1 diff --git a/mdk/nrf51801_xxab.ld b/mdk/nrf51801_xxab.ld new file mode 100644 index 0000000000..4f274676c4 --- /dev/null +++ b/mdk/nrf51801_xxab.ld @@ -0,0 +1,13 @@ +/* Linker script to configure memory regions. */ + +SEARCH_DIR(.) +GROUP(-lgcc -lc -lnosys) + +MEMORY +{ + FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 0x30000 + RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x4000 +} + + +INCLUDE "nrf_common.ld" diff --git a/mdk/nrf51802_peripherals.h b/mdk/nrf51802_peripherals.h index 106a6c5fcb..9a685ab633 100644 --- a/mdk/nrf51802_peripherals.h +++ b/mdk/nrf51802_peripherals.h @@ -71,6 +71,8 @@ POSSIBILITY OF SUCH DAMAGE. #define RADIO_PRESENT #define RADIO_COUNT 1 +#define RADIO_TXPOWER_TXPOWER_Max RADIO_TXPOWER_TXPOWER_Pos4dBm + /* Accelerated Address Resolver */ #define AAR_PRESENT #define AAR_COUNT 1 diff --git a/mdk/nrf51802_xxaa.ld b/mdk/nrf51802_xxaa.ld new file mode 100644 index 0000000000..a36a3c4dde --- /dev/null +++ b/mdk/nrf51802_xxaa.ld @@ -0,0 +1,13 @@ +/* Linker script to configure memory regions. */ + +SEARCH_DIR(.) +GROUP(-lgcc -lc -lnosys) + +MEMORY +{ + FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 0x40000 + RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x4000 +} + + +INCLUDE "nrf_common.ld" diff --git a/mdk/nrf51822_peripherals.h b/mdk/nrf51822_peripherals.h index 1dc6467460..2c819c6b1d 100644 --- a/mdk/nrf51822_peripherals.h +++ b/mdk/nrf51822_peripherals.h @@ -72,6 +72,8 @@ POSSIBILITY OF SUCH DAMAGE. #define RADIO_PRESENT #define RADIO_COUNT 1 +#define RADIO_TXPOWER_TXPOWER_Max RADIO_TXPOWER_TXPOWER_Pos4dBm + /* Accelerated Address Resolver */ #define AAR_PRESENT #define AAR_COUNT 1 diff --git a/mdk/nrf51822_xxaa.ld b/mdk/nrf51822_xxaa.ld new file mode 100644 index 0000000000..a36a3c4dde --- /dev/null +++ b/mdk/nrf51822_xxaa.ld @@ -0,0 +1,13 @@ +/* Linker script to configure memory regions. */ + +SEARCH_DIR(.) +GROUP(-lgcc -lc -lnosys) + +MEMORY +{ + FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 0x40000 + RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x4000 +} + + +INCLUDE "nrf_common.ld" diff --git a/mdk/nrf51822_xxab.ld b/mdk/nrf51822_xxab.ld new file mode 100644 index 0000000000..7bfec18577 --- /dev/null +++ b/mdk/nrf51822_xxab.ld @@ -0,0 +1,13 @@ +/* Linker script to configure memory regions. */ + +SEARCH_DIR(.) +GROUP(-lgcc -lc -lnosys) + +MEMORY +{ + FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 0x20000 + RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x4000 +} + + +INCLUDE "nrf_common.ld" diff --git a/mdk/nrf51822_xxac.ld b/mdk/nrf51822_xxac.ld new file mode 100644 index 0000000000..a6e98ba330 --- /dev/null +++ b/mdk/nrf51822_xxac.ld @@ -0,0 +1,13 @@ +/* Linker script to configure memory regions. */ + +SEARCH_DIR(.) +GROUP(-lgcc -lc -lnosys) + +MEMORY +{ + FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 0x40000 + RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x8000 +} + + +INCLUDE "nrf_common.ld" diff --git a/mdk/nrf51824_peripherals.h b/mdk/nrf51824_peripherals.h index 87b93ebb8d..63aff43135 100644 --- a/mdk/nrf51824_peripherals.h +++ b/mdk/nrf51824_peripherals.h @@ -72,6 +72,8 @@ POSSIBILITY OF SUCH DAMAGE. #define RADIO_PRESENT #define RADIO_COUNT 1 +#define RADIO_TXPOWER_TXPOWER_Max RADIO_TXPOWER_TXPOWER_Pos4dBm + /* Accelerated Address Resolver */ #define AAR_PRESENT #define AAR_COUNT 1 diff --git a/mdk/nrf51824_xxaa.ld b/mdk/nrf51824_xxaa.ld new file mode 100644 index 0000000000..a36a3c4dde --- /dev/null +++ b/mdk/nrf51824_xxaa.ld @@ -0,0 +1,13 @@ +/* Linker script to configure memory regions. */ + +SEARCH_DIR(.) +GROUP(-lgcc -lc -lnosys) + +MEMORY +{ + FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 0x40000 + RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x4000 +} + + +INCLUDE "nrf_common.ld" diff --git a/mdk/nrf51_common.ld b/mdk/nrf51_common.ld index 6f5e4c554c..98a10037f1 100644 --- a/mdk/nrf51_common.ld +++ b/mdk/nrf51_common.ld @@ -89,6 +89,7 @@ SECTIONS } > FLASH __exidx_end = .; + . = ALIGN(4); __etext = .; .data : AT (__etext) diff --git a/mdk/nrf51_erratas.h b/mdk/nrf51_erratas.h index 67104bfec9..44a0f928f1 100644 --- a/mdk/nrf51_erratas.h +++ b/mdk/nrf51_erratas.h @@ -158,6 +158,8 @@ static bool nrf51_errata_1(void) return false; case 0x0Dul: return false; + default: + return false; } } #endif @@ -207,6 +209,8 @@ static bool nrf51_errata_2(void) return false; case 0x0Dul: return false; + default: + return false; } } #endif @@ -256,6 +260,8 @@ static bool nrf51_errata_3(void) return false; case 0x0Dul: return false; + default: + return false; } } #endif @@ -323,6 +329,8 @@ static bool nrf51_errata_6(void) return false; case 0x0Dul: return false; + default: + return false; } } #endif @@ -372,6 +380,8 @@ static bool nrf51_errata_7(void) return false; case 0x0Dul: return false; + default: + return false; } } #endif @@ -421,6 +431,8 @@ static bool nrf51_errata_8(void) return false; case 0x0Dul: return false; + default: + return false; } } #endif @@ -470,6 +482,8 @@ static bool nrf51_errata_9(void) return false; case 0x0Dul: return false; + default: + return false; } } #endif @@ -519,6 +533,8 @@ static bool nrf51_errata_10(void) return false; case 0x0Dul: return false; + default: + return false; } } #endif @@ -568,6 +584,8 @@ static bool nrf51_errata_11(void) return false; case 0x0Dul: return false; + default: + return false; } } #endif @@ -617,6 +635,8 @@ static bool nrf51_errata_12(void) return false; case 0x0Dul: return false; + default: + return false; } } #endif @@ -666,6 +686,8 @@ static bool nrf51_errata_13(void) return false; case 0x0Dul: return false; + default: + return false; } } #endif @@ -715,6 +737,8 @@ static bool nrf51_errata_14(void) return false; case 0x0Dul: return false; + default: + return false; } } #endif @@ -764,6 +788,8 @@ static bool nrf51_errata_15(void) return false; case 0x0Dul: return false; + default: + return false; } } #endif @@ -813,6 +839,8 @@ static bool nrf51_errata_16(void) return false; case 0x0Dul: return false; + default: + return false; } } #endif @@ -862,6 +890,8 @@ static bool nrf51_errata_17(void) return false; case 0x0Dul: return false; + default: + return false; } } #endif @@ -911,6 +941,8 @@ static bool nrf51_errata_18(void) return false; case 0x0Dul: return false; + default: + return false; } } #endif @@ -960,6 +992,8 @@ static bool nrf51_errata_19(void) return false; case 0x0Dul: return false; + default: + return false; } } #endif @@ -1009,6 +1043,8 @@ static bool nrf51_errata_20(void) return false; case 0x0Dul: return false; + default: + return false; } } #endif @@ -1058,6 +1094,8 @@ static bool nrf51_errata_21(void) return false; case 0x0Dul: return false; + default: + return false; } } #endif @@ -1107,6 +1145,8 @@ static bool nrf51_errata_22(void) return false; case 0x0Dul: return false; + default: + return false; } } #endif @@ -1156,6 +1196,8 @@ static bool nrf51_errata_23(void) return false; case 0x0Dul: return false; + default: + return false; } } #endif @@ -1205,6 +1247,8 @@ static bool nrf51_errata_24(void) return false; case 0x0Dul: return false; + default: + return false; } } #endif @@ -1254,6 +1298,8 @@ static bool nrf51_errata_25(void) return false; case 0x0Dul: return false; + default: + return false; } } #endif @@ -1303,6 +1349,8 @@ static bool nrf51_errata_26(void) return false; case 0x0Dul: return false; + default: + return false; } } #endif @@ -1352,6 +1400,8 @@ static bool nrf51_errata_27(void) return false; case 0x0Dul: return false; + default: + return false; } } #endif @@ -1401,6 +1451,8 @@ static bool nrf51_errata_28(void) return false; case 0x0Dul: return false; + default: + return false; } } #endif @@ -1450,6 +1502,8 @@ static bool nrf51_errata_29(void) return false; case 0x0Dul: return false; + default: + return false; } } #endif @@ -1499,6 +1553,8 @@ static bool nrf51_errata_30(void) return false; case 0x0Dul: return false; + default: + return false; } } #endif @@ -1548,6 +1604,8 @@ static bool nrf51_errata_31(void) return false; case 0x0Dul: return false; + default: + return false; } } #endif @@ -1597,6 +1655,8 @@ static bool nrf51_errata_32(void) return false; case 0x0Dul: return false; + default: + return false; } } #endif @@ -1646,6 +1706,8 @@ static bool nrf51_errata_33(void) return false; case 0x0Dul: return false; + default: + return false; } } #endif @@ -1695,6 +1757,8 @@ static bool nrf51_errata_34(void) return false; case 0x0Dul: return false; + default: + return false; } } #endif @@ -1744,6 +1808,8 @@ static bool nrf51_errata_35(void) return false; case 0x0Dul: return false; + default: + return false; } } #endif @@ -1793,6 +1859,8 @@ static bool nrf51_errata_36(void) return false; case 0x0Dul: return false; + default: + return false; } } #endif @@ -1842,6 +1910,8 @@ static bool nrf51_errata_37(void) return false; case 0x0Dul: return false; + default: + return false; } } #endif @@ -1891,6 +1961,8 @@ static bool nrf51_errata_38(void) return true; case 0x0Dul: return true; + default: + return true; } } #endif @@ -1940,6 +2012,8 @@ static bool nrf51_errata_39(void) return false; case 0x0Dul: return false; + default: + return false; } } #endif @@ -1989,6 +2063,8 @@ static bool nrf51_errata_40(void) return false; case 0x0Dul: return false; + default: + return false; } } #endif @@ -2038,6 +2114,8 @@ static bool nrf51_errata_41(void) return false; case 0x0Dul: return false; + default: + return false; } } #endif @@ -2087,6 +2165,8 @@ static bool nrf51_errata_42(void) return false; case 0x0Dul: return false; + default: + return false; } } #endif @@ -2136,6 +2216,8 @@ static bool nrf51_errata_43(void) return false; case 0x0Dul: return false; + default: + return false; } } #endif @@ -2185,6 +2267,8 @@ static bool nrf51_errata_44(void) return false; case 0x0Dul: return false; + default: + return false; } } #endif @@ -2234,6 +2318,8 @@ static bool nrf51_errata_45(void) return false; case 0x0Dul: return false; + default: + return false; } } #endif @@ -2283,6 +2369,8 @@ static bool nrf51_errata_46(void) return true; case 0x0Dul: return false; + default: + return false; } } #endif @@ -2332,6 +2420,8 @@ static bool nrf51_errata_47(void) return false; case 0x0Dul: return false; + default: + return false; } } #endif @@ -2381,6 +2471,8 @@ static bool nrf51_errata_48(void) return false; case 0x0Dul: return false; + default: + return false; } } #endif @@ -2430,6 +2522,8 @@ static bool nrf51_errata_49(void) return false; case 0x0Dul: return false; + default: + return false; } } #endif @@ -2524,6 +2618,8 @@ static bool nrf51_errata_55(void) return false; case 0x0Dul: return false; + default: + return false; } } #endif @@ -2573,6 +2669,8 @@ static bool nrf51_errata_56(void) return false; case 0x0Dul: return false; + default: + return false; } } #endif @@ -2622,6 +2720,8 @@ static bool nrf51_errata_57(void) return false; case 0x0Dul: return false; + default: + return false; } } #endif @@ -2671,6 +2771,8 @@ static bool nrf51_errata_58(void) return false; case 0x0Dul: return false; + default: + return false; } } #endif @@ -2720,6 +2822,8 @@ static bool nrf51_errata_59(void) return false; case 0x0Dul: return false; + default: + return false; } } #endif @@ -2769,6 +2873,8 @@ static bool nrf51_errata_60(void) return false; case 0x0Dul: return false; + default: + return false; } } #endif @@ -2818,6 +2924,8 @@ static bool nrf51_errata_61(void) return true; case 0x0Dul: return true; + default: + return true; } } #endif @@ -2867,6 +2975,8 @@ static bool nrf51_errata_62(void) return false; case 0x0Dul: return false; + default: + return false; } } #endif @@ -2916,6 +3026,8 @@ static bool nrf51_errata_63(void) return false; case 0x0Dul: return false; + default: + return false; } } #endif @@ -2965,6 +3077,8 @@ static bool nrf51_errata_64(void) return false; case 0x0Dul: return false; + default: + return false; } } #endif @@ -3014,6 +3128,8 @@ static bool nrf51_errata_65(void) return false; case 0x0Dul: return false; + default: + return false; } } #endif @@ -3063,6 +3179,8 @@ static bool nrf51_errata_66(void) return true; case 0x0Dul: return false; + default: + return false; } } #endif @@ -3112,6 +3230,8 @@ static bool nrf51_errata_67(void) return true; case 0x0Dul: return true; + default: + return true; } } #endif @@ -3161,6 +3281,8 @@ static bool nrf51_errata_68(void) return false; case 0x0Dul: return false; + default: + return false; } } #endif @@ -3210,6 +3332,8 @@ static bool nrf51_errata_69(void) return true; case 0x0Dul: return false; + default: + return false; } } #endif @@ -3259,6 +3383,8 @@ static bool nrf51_errata_70(void) return true; case 0x0Dul: return true; + default: + return true; } } #endif @@ -3308,6 +3434,8 @@ static bool nrf51_errata_71(void) return true; case 0x0Dul: return false; + default: + return false; } } #endif @@ -3357,6 +3485,8 @@ static bool nrf51_errata_72(void) return true; case 0x0Dul: return true; + default: + return true; } } #endif @@ -3406,6 +3536,8 @@ static bool nrf51_errata_73(void) return true; case 0x0Dul: return false; + default: + return false; } } #endif @@ -3455,6 +3587,8 @@ static bool nrf51_errata_74(void) return true; case 0x0Dul: return false; + default: + return false; } } #endif @@ -3504,6 +3638,8 @@ static bool nrf51_errata_75(void) return true; case 0x0Dul: return true; + default: + return true; } } #endif @@ -3553,6 +3689,8 @@ static bool nrf51_errata_76(void) return false; case 0x0Dul: return true; + default: + return true; } } #endif @@ -3611,6 +3749,8 @@ static bool nrf51_errata_78(void) return true; case 0x0Dul: return false; + default: + return false; } } #endif diff --git a/mdk/nrf51_peripherals.h b/mdk/nrf51_peripherals.h index 99efebd2b2..d6457c0d98 100644 --- a/mdk/nrf51_peripherals.h +++ b/mdk/nrf51_peripherals.h @@ -69,6 +69,8 @@ POSSIBILITY OF SUCH DAMAGE. #define RADIO_PRESENT #define RADIO_COUNT 1 +#define RADIO_TXPOWER_TXPOWER_Max RADIO_TXPOWER_TXPOWER_Pos4dBm + /* Accelerated Address Resolver */ #define AAR_PRESENT #define AAR_COUNT 1 diff --git a/mdk/nrf52.h b/mdk/nrf52.h index f58aac8330..ae4404943b 100644 --- a/mdk/nrf52.h +++ b/mdk/nrf52.h @@ -30,10 +30,10 @@ * @file nrf52.h * @brief CMSIS HeaderFile * @version 1 - * @date 04. March 2020 - * @note Generated by SVDConv V3.3.25 on Wednesday, 04.03.2020 14:56:52 + * @date 14. August 2020 + * @note Generated by SVDConv V3.3.35 on Friday, 14.08.2020 15:02:13 * from File 'nrf52.svd', - * last modified on Wednesday, 04.03.2020 13:56:43 + * last modified on Friday, 14.08.2020 13:02:06 */ diff --git a/mdk/nrf52805.h b/mdk/nrf52805.h index f82df087f9..2a2f7813b8 100644 --- a/mdk/nrf52805.h +++ b/mdk/nrf52805.h @@ -30,10 +30,10 @@ * @file nrf52805.h * @brief CMSIS HeaderFile * @version 1 - * @date 04. March 2020 - * @note Generated by SVDConv V3.3.25 on Wednesday, 04.03.2020 14:56:51 + * @date 14. August 2020 + * @note Generated by SVDConv V3.3.35 on Friday, 14.08.2020 15:02:13 * from File 'nrf52805.svd', - * last modified on Wednesday, 04.03.2020 13:56:43 + * last modified on Friday, 14.08.2020 13:02:06 */ @@ -98,6 +98,7 @@ typedef enum { CCM_AAR_IRQn = 15, /*!< 15 CCM_AAR */ WDT_IRQn = 16, /*!< 16 WDT */ RTC1_IRQn = 17, /*!< 17 RTC1 */ + QDEC_IRQn = 18, /*!< 18 QDEC */ SWI0_EGU0_IRQn = 20, /*!< 20 SWI0_EGU0 */ SWI1_EGU1_IRQn = 21, /*!< 21 SWI1_EGU1 */ SWI2_IRQn = 22, /*!< 22 SWI2 */ @@ -451,6 +452,16 @@ typedef struct { } SAADC_RESULT_Type; /*!< Size = 12 (0xc) */ +/** + * @brief QDEC_PSEL [PSEL] (Unspecified) + */ +typedef struct { + __IOM uint32_t LED; /*!< (@ 0x00000000) Pin select for LED signal */ + __IOM uint32_t A; /*!< (@ 0x00000004) Pin select for A signal */ + __IOM uint32_t B; /*!< (@ 0x00000008) Pin select for B signal */ +} QDEC_PSEL_Type; /*!< Size = 12 (0xc) */ + + /** * @brief PPI_TASKS_CHG [TASKS_CHG] (Channel group tasks) */ @@ -464,8 +475,8 @@ typedef struct { * @brief PPI_CH [CH] (PPI Channel) */ typedef struct { - __IOM uint32_t EEP; /*!< (@ 0x00000000) Description cluster: Channel n event end-point */ - __IOM uint32_t TEP; /*!< (@ 0x00000004) Description cluster: Channel n task end-point */ + __IOM uint32_t EEP; /*!< (@ 0x00000000) Description cluster: Channel n event endpoint */ + __IOM uint32_t TEP; /*!< (@ 0x00000004) Description cluster: Channel n task endpoint */ } PPI_CH_Type; /*!< Size = 8 (0x8) */ @@ -473,7 +484,7 @@ typedef struct { * @brief PPI_FORK [FORK] (Fork) */ typedef struct { - __IOM uint32_t TEP; /*!< (@ 0x00000000) Description cluster: Channel n task end-point */ + __IOM uint32_t TEP; /*!< (@ 0x00000000) Description cluster: Channel n task endpoint */ } PPI_FORK_Type; /*!< Size = 4 (0x4) */ @@ -667,7 +678,7 @@ typedef struct { /*!< (@ 0x50000000) P0 Structure __IOM uint32_t LATCH; /*!< (@ 0x00000520) Latch register indicating what GPIO pins that have met the criteria set in the PIN_CNF[n].SENSE registers */ - __IOM uint32_t DETECTMODE; /*!< (@ 0x00000524) Select between default DETECT signal behaviour + __IOM uint32_t DETECTMODE; /*!< (@ 0x00000524) Select between default DETECT signal behavior and LDETECT mode */ __IM uint32_t RESERVED1[118]; __IOM uint32_t PIN_CNF[32]; /*!< (@ 0x00000700) Description collection: Configuration of GPIO @@ -717,9 +728,9 @@ typedef struct { /*!< (@ 0x40001000) RADIO Struct TX path */ __IOM uint32_t EVENTS_RXREADY; /*!< (@ 0x00000158) RADIO has ramped up and is ready to be started RX path */ - __IOM uint32_t EVENTS_MHRMATCH; /*!< (@ 0x0000015C) MAC header match found */ - __IM uint32_t RESERVED4[3]; - __IOM uint32_t EVENTS_PHYEND; /*!< (@ 0x0000016C) Generated when last bit is sent on air */ + __IM uint32_t RESERVED4[4]; + __IOM uint32_t EVENTS_PHYEND; /*!< (@ 0x0000016C) Generated when last bit is sent on air, or received + from air */ __IM uint32_t RESERVED5[36]; __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ __IM uint32_t RESERVED6[64]; @@ -859,8 +870,8 @@ typedef struct { /*!< (@ 0x40002000) UARTE0 Struc __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ __IM uint32_t RESERVED9[93]; - __IOM uint32_t ERRORSRC; /*!< (@ 0x00000480) Error source Note : this register is read / write - one to clear. */ + __IOM uint32_t ERRORSRC; /*!< (@ 0x00000480) Error source This register is read/write one + to clear. */ __IM uint32_t RESERVED10[31]; __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable UART */ __IM uint32_t RESERVED11; @@ -955,9 +966,8 @@ typedef struct { /*!< (@ 0x40003000) TWIM0 Struct __IM uint32_t RESERVED4[7]; __IOM uint32_t EVENTS_ERROR; /*!< (@ 0x00000124) TWI error */ __IM uint32_t RESERVED5[8]; - __IOM uint32_t EVENTS_SUSPENDED; /*!< (@ 0x00000148) Last byte has been sent out after the SUSPEND - task has been issued, TWI traffic is now - suspended. */ + __IOM uint32_t EVENTS_SUSPENDED; /*!< (@ 0x00000148) SUSPEND task has been issued, TWI traffic is + now suspended. */ __IOM uint32_t EVENTS_RXSTARTED; /*!< (@ 0x0000014C) Receive sequence started */ __IOM uint32_t EVENTS_TXSTARTED; /*!< (@ 0x00000150) Transmit sequence started */ __IM uint32_t RESERVED6[2]; @@ -1203,7 +1213,7 @@ typedef struct { /*!< (@ 0x40006000) GPIOTE Struc __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ __IM uint32_t RESERVED5[129]; __IOM uint32_t CONFIG[8]; /*!< (@ 0x00000510) Description collection: Configuration for OUT[n], - SET[n] and CLR[n] tasks and IN[n] event */ + SET[n], and CLR[n] tasks and IN[n] event */ } NRF_GPIOTE_Type; /*!< Size = 1328 (0x530) */ @@ -1354,25 +1364,25 @@ typedef struct { /*!< (@ 0x4000C000) TEMP Structu __IM uint32_t RESERVED2[127]; __IM int32_t TEMP; /*!< (@ 0x00000508) Temperature in degC (0.25deg steps) */ __IM uint32_t RESERVED3[5]; - __IOM uint32_t A0; /*!< (@ 0x00000520) Slope of 1st piece wise linear function */ - __IOM uint32_t A1; /*!< (@ 0x00000524) Slope of 2nd piece wise linear function */ - __IOM uint32_t A2; /*!< (@ 0x00000528) Slope of 3rd piece wise linear function */ - __IOM uint32_t A3; /*!< (@ 0x0000052C) Slope of 4th piece wise linear function */ - __IOM uint32_t A4; /*!< (@ 0x00000530) Slope of 5th piece wise linear function */ - __IOM uint32_t A5; /*!< (@ 0x00000534) Slope of 6th piece wise linear function */ + __IOM uint32_t A0; /*!< (@ 0x00000520) Slope of first piecewise linear function */ + __IOM uint32_t A1; /*!< (@ 0x00000524) Slope of second piecewise linear function */ + __IOM uint32_t A2; /*!< (@ 0x00000528) Slope of third piecewise linear function */ + __IOM uint32_t A3; /*!< (@ 0x0000052C) Slope of fourth piecewise linear function */ + __IOM uint32_t A4; /*!< (@ 0x00000530) Slope of fifth piecewise linear function */ + __IOM uint32_t A5; /*!< (@ 0x00000534) Slope of sixth piecewise linear function */ __IM uint32_t RESERVED4[2]; - __IOM uint32_t B0; /*!< (@ 0x00000540) y-intercept of 1st piece wise linear function */ - __IOM uint32_t B1; /*!< (@ 0x00000544) y-intercept of 2nd piece wise linear function */ - __IOM uint32_t B2; /*!< (@ 0x00000548) y-intercept of 3rd piece wise linear function */ - __IOM uint32_t B3; /*!< (@ 0x0000054C) y-intercept of 4th piece wise linear function */ - __IOM uint32_t B4; /*!< (@ 0x00000550) y-intercept of 5th piece wise linear function */ - __IOM uint32_t B5; /*!< (@ 0x00000554) y-intercept of 6th piece wise linear function */ + __IOM uint32_t B0; /*!< (@ 0x00000540) y-intercept of first piecewise linear function */ + __IOM uint32_t B1; /*!< (@ 0x00000544) y-intercept of second piecewise linear function */ + __IOM uint32_t B2; /*!< (@ 0x00000548) y-intercept of third piecewise linear function */ + __IOM uint32_t B3; /*!< (@ 0x0000054C) y-intercept of fourth piecewise linear function */ + __IOM uint32_t B4; /*!< (@ 0x00000550) y-intercept of fifth piecewise linear function */ + __IOM uint32_t B5; /*!< (@ 0x00000554) y-intercept of sixth piecewise linear function */ __IM uint32_t RESERVED5[2]; - __IOM uint32_t T0; /*!< (@ 0x00000560) End point of 1st piece wise linear function */ - __IOM uint32_t T1; /*!< (@ 0x00000564) End point of 2nd piece wise linear function */ - __IOM uint32_t T2; /*!< (@ 0x00000568) End point of 3rd piece wise linear function */ - __IOM uint32_t T3; /*!< (@ 0x0000056C) End point of 4th piece wise linear function */ - __IOM uint32_t T4; /*!< (@ 0x00000570) End point of 5th piece wise linear function */ + __IOM uint32_t T0; /*!< (@ 0x00000560) End point of first piecewise linear function */ + __IOM uint32_t T1; /*!< (@ 0x00000564) End point of second piecewise linear function */ + __IOM uint32_t T2; /*!< (@ 0x00000568) End point of third piecewise linear function */ + __IOM uint32_t T3; /*!< (@ 0x0000056C) End point of fourth piecewise linear function */ + __IOM uint32_t T4; /*!< (@ 0x00000570) End point of fifth piecewise linear function */ } NRF_TEMP_Type; /*!< Size = 1396 (0x574) */ @@ -1473,7 +1483,7 @@ typedef struct { /*!< (@ 0x4000F000) AAR Structur */ typedef struct { /*!< (@ 0x4000F000) CCM Structure */ - __OM uint32_t TASKS_KSGEN; /*!< (@ 0x00000000) Start generation of key-stream. This operation + __OM uint32_t TASKS_KSGEN; /*!< (@ 0x00000000) Start generation of keystream. This operation will stop by itself when completed. */ __OM uint32_t TASKS_CRYPT; /*!< (@ 0x00000004) Start encryption/decryption. This operation will stop by itself when completed. */ @@ -1482,7 +1492,7 @@ typedef struct { /*!< (@ 0x4000F000) CCM Structur the contents of the RATEOVERRIDE register for any ongoing encryption/decryption */ __IM uint32_t RESERVED[60]; - __IOM uint32_t EVENTS_ENDKSGEN; /*!< (@ 0x00000100) Key-stream generation complete */ + __IOM uint32_t EVENTS_ENDKSGEN; /*!< (@ 0x00000100) Keystream generation complete */ __IOM uint32_t EVENTS_ENDCRYPT; /*!< (@ 0x00000104) Encrypt/decrypt complete */ __IOM uint32_t EVENTS_ERROR; /*!< (@ 0x00000108) Deprecated register - CCM error event */ __IM uint32_t RESERVED1[61]; @@ -1500,7 +1510,7 @@ typedef struct { /*!< (@ 0x4000F000) CCM Structur __IOM uint32_t INPTR; /*!< (@ 0x0000050C) Input pointer */ __IOM uint32_t OUTPTR; /*!< (@ 0x00000510) Output pointer */ __IOM uint32_t SCRATCHPTR; /*!< (@ 0x00000514) Pointer to data area used for temporary storage */ - __IOM uint32_t MAXPACKETSIZE; /*!< (@ 0x00000518) Length of key-stream generated when MODE.LENGTH + __IOM uint32_t MAXPACKETSIZE; /*!< (@ 0x00000518) Length of keystream generated when MODE.LENGTH = Extended. */ __IOM uint32_t RATEOVERRIDE; /*!< (@ 0x0000051C) Data rate override setting. */ } NRF_CCM_Type; /*!< Size = 1312 (0x520) */ @@ -1536,13 +1546,62 @@ typedef struct { /*!< (@ 0x40010000) WDT Structur +/* =========================================================================================================================== */ +/* ================ QDEC ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Quadrature Decoder (QDEC) + */ + +typedef struct { /*!< (@ 0x40012000) QDEC Structure */ + __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Task starting the quadrature decoder */ + __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Task stopping the quadrature decoder */ + __OM uint32_t TASKS_READCLRACC; /*!< (@ 0x00000008) Read and clear ACC and ACCDBL */ + __OM uint32_t TASKS_RDCLRACC; /*!< (@ 0x0000000C) Read and clear ACC */ + __OM uint32_t TASKS_RDCLRDBL; /*!< (@ 0x00000010) Read and clear ACCDBL */ + __IM uint32_t RESERVED[59]; + __IOM uint32_t EVENTS_SAMPLERDY; /*!< (@ 0x00000100) Event being generated for every new sample value + written to the SAMPLE register */ + __IOM uint32_t EVENTS_REPORTRDY; /*!< (@ 0x00000104) Non-null report ready */ + __IOM uint32_t EVENTS_ACCOF; /*!< (@ 0x00000108) ACC or ACCDBL register overflow */ + __IOM uint32_t EVENTS_DBLRDY; /*!< (@ 0x0000010C) Double displacement(s) detected */ + __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000110) QDEC has been stopped */ + __IM uint32_t RESERVED1[59]; + __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ + __IM uint32_t RESERVED2[64]; + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t RESERVED3[125]; + __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable the quadrature decoder */ + __IOM uint32_t LEDPOL; /*!< (@ 0x00000504) LED output pin polarity */ + __IOM uint32_t SAMPLEPER; /*!< (@ 0x00000508) Sample period */ + __IM int32_t SAMPLE; /*!< (@ 0x0000050C) Motion sample value */ + __IOM uint32_t REPORTPER; /*!< (@ 0x00000510) Number of samples to be taken before REPORTRDY + and DBLRDY events can be generated */ + __IM int32_t ACC; /*!< (@ 0x00000514) Register accumulating the valid transitions */ + __IM int32_t ACCREAD; /*!< (@ 0x00000518) Snapshot of the ACC register, updated by the + READCLRACC or RDCLRACC task */ + __IOM QDEC_PSEL_Type PSEL; /*!< (@ 0x0000051C) Unspecified */ + __IOM uint32_t DBFEN; /*!< (@ 0x00000528) Enable input debounce filters */ + __IM uint32_t RESERVED4[5]; + __IOM uint32_t LEDPRE; /*!< (@ 0x00000540) Time period the LED is switched ON prior to sampling */ + __IM uint32_t ACCDBL; /*!< (@ 0x00000544) Register accumulating the number of detected + double transitions */ + __IM uint32_t ACCDBLREAD; /*!< (@ 0x00000548) Snapshot of the ACCDBL, updated by the READCLRACC + or RDCLRDBL task */ +} NRF_QDEC_Type; /*!< Size = 1356 (0x54c) */ + + + /* =========================================================================================================================== */ /* ================ EGU0 ================ */ /* =========================================================================================================================== */ /** - * @brief Event Generator Unit 0 (EGU0) + * @brief Event generator unit 0 (EGU0) */ typedef struct { /*!< (@ 0x40014000) EGU0 Structure */ @@ -1581,7 +1640,7 @@ typedef struct { /*!< (@ 0x40014000) SWI0 Structu /** - * @brief Non-volatile memory controller (NVMC) + * @brief Non Volatile Memory Controller (NVMC) */ typedef struct { /*!< (@ 0x4001E000) NVMC Structure */ @@ -1591,16 +1650,16 @@ typedef struct { /*!< (@ 0x4001E000) NVMC Structu __IOM uint32_t CONFIG; /*!< (@ 0x00000504) Configuration register */ union { - __IOM uint32_t ERASEPAGE; /*!< (@ 0x00000508) Register for erasing a page in code area */ - __IOM uint32_t ERASEPCR1; /*!< (@ 0x00000508) Deprecated register - Register for erasing a - page in code area. Equivalent to ERASEPAGE. */ + __OM uint32_t ERASEPAGE; /*!< (@ 0x00000508) Register for erasing a page in code area */ + __OM uint32_t ERASEPCR1; /*!< (@ 0x00000508) Deprecated register - Register for erasing a + page in code area, equivalent to ERASEPAGE */ }; - __IOM uint32_t ERASEALL; /*!< (@ 0x0000050C) Register for erasing all non-volatile user memory */ - __IOM uint32_t ERASEPCR0; /*!< (@ 0x00000510) Deprecated register - Register for erasing a - page in code area. Equivalent to ERASEPAGE. */ - __IOM uint32_t ERASEUICR; /*!< (@ 0x00000514) Register for erasing user information configuration + __OM uint32_t ERASEALL; /*!< (@ 0x0000050C) Register for erasing all non-volatile user memory */ + __OM uint32_t ERASEPCR0; /*!< (@ 0x00000510) Deprecated register - Register for erasing a + page in code area, equivalent to ERASEPAGE */ + __OM uint32_t ERASEUICR; /*!< (@ 0x00000514) Register for erasing user information configuration registers */ - __IOM uint32_t ERASEPAGEPARTIAL; /*!< (@ 0x00000518) Register for partial erase of a page in code + __OM uint32_t ERASEPAGEPARTIAL; /*!< (@ 0x00000518) Register for partial erase of a page in code area */ __IOM uint32_t ERASEPAGEPARTIALCFG; /*!< (@ 0x0000051C) Register for partial erase configuration */ } NRF_NVMC_Type; /*!< Size = 1312 (0x520) */ @@ -1623,8 +1682,8 @@ typedef struct { /*!< (@ 0x4001F000) PPI Structur __IOM uint32_t CHENSET; /*!< (@ 0x00000504) Channel enable set register */ __IOM uint32_t CHENCLR; /*!< (@ 0x00000508) Channel enable clear register */ __IM uint32_t RESERVED1; - __IOM PPI_CH_Type CH[20]; /*!< (@ 0x00000510) PPI Channel */ - __IM uint32_t RESERVED2[148]; + __IOM PPI_CH_Type CH[10]; /*!< (@ 0x00000510) PPI Channel */ + __IM uint32_t RESERVED2[168]; __IOM uint32_t CHG[6]; /*!< (@ 0x00000800) Description collection: Channel group n */ __IM uint32_t RESERVED3[62]; __IOM PPI_FORK_Type FORK[32]; /*!< (@ 0x00000910) Fork */ @@ -1671,6 +1730,7 @@ typedef struct { /*!< (@ 0x4001F000) PPI Structur #define NRF_CCM_BASE 0x4000F000UL #define NRF_WDT_BASE 0x40010000UL #define NRF_RTC1_BASE 0x40011000UL +#define NRF_QDEC_BASE 0x40012000UL #define NRF_EGU0_BASE 0x40014000UL #define NRF_SWI0_BASE 0x40014000UL #define NRF_EGU1_BASE 0x40015000UL @@ -1722,6 +1782,7 @@ typedef struct { /*!< (@ 0x4001F000) PPI Structur #define NRF_CCM ((NRF_CCM_Type*) NRF_CCM_BASE) #define NRF_WDT ((NRF_WDT_Type*) NRF_WDT_BASE) #define NRF_RTC1 ((NRF_RTC_Type*) NRF_RTC1_BASE) +#define NRF_QDEC ((NRF_QDEC_Type*) NRF_QDEC_BASE) #define NRF_EGU0 ((NRF_EGU_Type*) NRF_EGU0_BASE) #define NRF_SWI0 ((NRF_SWI_Type*) NRF_SWI0_BASE) #define NRF_EGU1 ((NRF_EGU_Type*) NRF_EGU1_BASE) diff --git a/mdk/nrf52805.svd b/mdk/nrf52805.svd index 1f17edc21b..bb09b2ea51 100644 --- a/mdk/nrf52805.svd +++ b/mdk/nrf52805.svd @@ -3898,7 +3898,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets the pin high; writing a '0' has no effect + Write: a '1' sets the pin high; a '0' has no effect 1 @@ -3925,7 +3925,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets the pin high; writing a '0' has no effect + Write: a '1' sets the pin high; a '0' has no effect 1 @@ -3952,7 +3952,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets the pin high; writing a '0' has no effect + Write: a '1' sets the pin high; a '0' has no effect 1 @@ -3979,7 +3979,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets the pin high; writing a '0' has no effect + Write: a '1' sets the pin high; a '0' has no effect 1 @@ -4006,7 +4006,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets the pin high; writing a '0' has no effect + Write: a '1' sets the pin high; a '0' has no effect 1 @@ -4033,7 +4033,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets the pin high; writing a '0' has no effect + Write: a '1' sets the pin high; a '0' has no effect 1 @@ -4060,7 +4060,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets the pin high; writing a '0' has no effect + Write: a '1' sets the pin high; a '0' has no effect 1 @@ -4087,7 +4087,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets the pin high; writing a '0' has no effect + Write: a '1' sets the pin high; a '0' has no effect 1 @@ -4114,7 +4114,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets the pin high; writing a '0' has no effect + Write: a '1' sets the pin high; a '0' has no effect 1 @@ -4141,7 +4141,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets the pin high; writing a '0' has no effect + Write: a '1' sets the pin high; a '0' has no effect 1 @@ -4168,7 +4168,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets the pin high; writing a '0' has no effect + Write: a '1' sets the pin high; a '0' has no effect 1 @@ -4195,7 +4195,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets the pin high; writing a '0' has no effect + Write: a '1' sets the pin high; a '0' has no effect 1 @@ -4222,7 +4222,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets the pin high; writing a '0' has no effect + Write: a '1' sets the pin high; a '0' has no effect 1 @@ -4249,7 +4249,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets the pin high; writing a '0' has no effect + Write: a '1' sets the pin high; a '0' has no effect 1 @@ -4276,7 +4276,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets the pin high; writing a '0' has no effect + Write: a '1' sets the pin high; a '0' has no effect 1 @@ -4303,7 +4303,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets the pin high; writing a '0' has no effect + Write: a '1' sets the pin high; a '0' has no effect 1 @@ -4330,7 +4330,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets the pin high; writing a '0' has no effect + Write: a '1' sets the pin high; a '0' has no effect 1 @@ -4357,7 +4357,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets the pin high; writing a '0' has no effect + Write: a '1' sets the pin high; a '0' has no effect 1 @@ -4384,7 +4384,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets the pin high; writing a '0' has no effect + Write: a '1' sets the pin high; a '0' has no effect 1 @@ -4411,7 +4411,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets the pin high; writing a '0' has no effect + Write: a '1' sets the pin high; a '0' has no effect 1 @@ -4438,7 +4438,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets the pin high; writing a '0' has no effect + Write: a '1' sets the pin high; a '0' has no effect 1 @@ -4465,7 +4465,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets the pin high; writing a '0' has no effect + Write: a '1' sets the pin high; a '0' has no effect 1 @@ -4492,7 +4492,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets the pin high; writing a '0' has no effect + Write: a '1' sets the pin high; a '0' has no effect 1 @@ -4519,7 +4519,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets the pin high; writing a '0' has no effect + Write: a '1' sets the pin high; a '0' has no effect 1 @@ -4546,7 +4546,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets the pin high; writing a '0' has no effect + Write: a '1' sets the pin high; a '0' has no effect 1 @@ -4573,7 +4573,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets the pin high; writing a '0' has no effect + Write: a '1' sets the pin high; a '0' has no effect 1 @@ -4600,7 +4600,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets the pin high; writing a '0' has no effect + Write: a '1' sets the pin high; a '0' has no effect 1 @@ -4627,7 +4627,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets the pin high; writing a '0' has no effect + Write: a '1' sets the pin high; a '0' has no effect 1 @@ -4654,7 +4654,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets the pin high; writing a '0' has no effect + Write: a '1' sets the pin high; a '0' has no effect 1 @@ -4681,7 +4681,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets the pin high; writing a '0' has no effect + Write: a '1' sets the pin high; a '0' has no effect 1 @@ -4708,7 +4708,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets the pin high; writing a '0' has no effect + Write: a '1' sets the pin high; a '0' has no effect 1 @@ -4735,7 +4735,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets the pin high; writing a '0' has no effect + Write: a '1' sets the pin high; a '0' has no effect 1 @@ -4771,7 +4771,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect + Write: a '1' sets the pin low; a '0' has no effect 1 @@ -4798,7 +4798,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect + Write: a '1' sets the pin low; a '0' has no effect 1 @@ -4825,7 +4825,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect + Write: a '1' sets the pin low; a '0' has no effect 1 @@ -4852,7 +4852,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect + Write: a '1' sets the pin low; a '0' has no effect 1 @@ -4879,7 +4879,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect + Write: a '1' sets the pin low; a '0' has no effect 1 @@ -4906,7 +4906,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect + Write: a '1' sets the pin low; a '0' has no effect 1 @@ -4933,7 +4933,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect + Write: a '1' sets the pin low; a '0' has no effect 1 @@ -4960,7 +4960,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect + Write: a '1' sets the pin low; a '0' has no effect 1 @@ -4987,7 +4987,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect + Write: a '1' sets the pin low; a '0' has no effect 1 @@ -5014,7 +5014,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect + Write: a '1' sets the pin low; a '0' has no effect 1 @@ -5041,7 +5041,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect + Write: a '1' sets the pin low; a '0' has no effect 1 @@ -5068,7 +5068,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect + Write: a '1' sets the pin low; a '0' has no effect 1 @@ -5095,7 +5095,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect + Write: a '1' sets the pin low; a '0' has no effect 1 @@ -5122,7 +5122,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect + Write: a '1' sets the pin low; a '0' has no effect 1 @@ -5149,7 +5149,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect + Write: a '1' sets the pin low; a '0' has no effect 1 @@ -5176,7 +5176,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect + Write: a '1' sets the pin low; a '0' has no effect 1 @@ -5203,7 +5203,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect + Write: a '1' sets the pin low; a '0' has no effect 1 @@ -5230,7 +5230,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect + Write: a '1' sets the pin low; a '0' has no effect 1 @@ -5257,7 +5257,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect + Write: a '1' sets the pin low; a '0' has no effect 1 @@ -5284,7 +5284,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect + Write: a '1' sets the pin low; a '0' has no effect 1 @@ -5311,7 +5311,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect + Write: a '1' sets the pin low; a '0' has no effect 1 @@ -5338,7 +5338,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect + Write: a '1' sets the pin low; a '0' has no effect 1 @@ -5365,7 +5365,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect + Write: a '1' sets the pin low; a '0' has no effect 1 @@ -5392,7 +5392,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect + Write: a '1' sets the pin low; a '0' has no effect 1 @@ -5419,7 +5419,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect + Write: a '1' sets the pin low; a '0' has no effect 1 @@ -5446,7 +5446,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect + Write: a '1' sets the pin low; a '0' has no effect 1 @@ -5473,7 +5473,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect + Write: a '1' sets the pin low; a '0' has no effect 1 @@ -5500,7 +5500,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect + Write: a '1' sets the pin low; a '0' has no effect 1 @@ -5527,7 +5527,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect + Write: a '1' sets the pin low; a '0' has no effect 1 @@ -5554,7 +5554,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect + Write: a '1' sets the pin low; a '0' has no effect 1 @@ -5581,7 +5581,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect + Write: a '1' sets the pin low; a '0' has no effect 1 @@ -5608,7 +5608,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets the pin low; writing a '0' has no effect + Write: a '1' sets the pin low; a '0' has no effect 1 @@ -6812,7 +6812,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets pin to output; writing a '0' has no effect + Write: a '1' sets pin to output; a '0' has no effect 1 @@ -6839,7 +6839,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets pin to output; writing a '0' has no effect + Write: a '1' sets pin to output; a '0' has no effect 1 @@ -6866,7 +6866,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets pin to output; writing a '0' has no effect + Write: a '1' sets pin to output; a '0' has no effect 1 @@ -6893,7 +6893,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets pin to output; writing a '0' has no effect + Write: a '1' sets pin to output; a '0' has no effect 1 @@ -6920,7 +6920,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets pin to output; writing a '0' has no effect + Write: a '1' sets pin to output; a '0' has no effect 1 @@ -6947,7 +6947,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets pin to output; writing a '0' has no effect + Write: a '1' sets pin to output; a '0' has no effect 1 @@ -6974,7 +6974,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets pin to output; writing a '0' has no effect + Write: a '1' sets pin to output; a '0' has no effect 1 @@ -7001,7 +7001,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets pin to output; writing a '0' has no effect + Write: a '1' sets pin to output; a '0' has no effect 1 @@ -7028,7 +7028,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets pin to output; writing a '0' has no effect + Write: a '1' sets pin to output; a '0' has no effect 1 @@ -7055,7 +7055,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets pin to output; writing a '0' has no effect + Write: a '1' sets pin to output; a '0' has no effect 1 @@ -7082,7 +7082,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets pin to output; writing a '0' has no effect + Write: a '1' sets pin to output; a '0' has no effect 1 @@ -7109,7 +7109,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets pin to output; writing a '0' has no effect + Write: a '1' sets pin to output; a '0' has no effect 1 @@ -7136,7 +7136,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets pin to output; writing a '0' has no effect + Write: a '1' sets pin to output; a '0' has no effect 1 @@ -7163,7 +7163,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets pin to output; writing a '0' has no effect + Write: a '1' sets pin to output; a '0' has no effect 1 @@ -7190,7 +7190,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets pin to output; writing a '0' has no effect + Write: a '1' sets pin to output; a '0' has no effect 1 @@ -7217,7 +7217,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets pin to output; writing a '0' has no effect + Write: a '1' sets pin to output; a '0' has no effect 1 @@ -7244,7 +7244,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets pin to output; writing a '0' has no effect + Write: a '1' sets pin to output; a '0' has no effect 1 @@ -7271,7 +7271,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets pin to output; writing a '0' has no effect + Write: a '1' sets pin to output; a '0' has no effect 1 @@ -7298,7 +7298,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets pin to output; writing a '0' has no effect + Write: a '1' sets pin to output; a '0' has no effect 1 @@ -7325,7 +7325,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets pin to output; writing a '0' has no effect + Write: a '1' sets pin to output; a '0' has no effect 1 @@ -7352,7 +7352,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets pin to output; writing a '0' has no effect + Write: a '1' sets pin to output; a '0' has no effect 1 @@ -7379,7 +7379,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets pin to output; writing a '0' has no effect + Write: a '1' sets pin to output; a '0' has no effect 1 @@ -7406,7 +7406,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets pin to output; writing a '0' has no effect + Write: a '1' sets pin to output; a '0' has no effect 1 @@ -7433,7 +7433,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets pin to output; writing a '0' has no effect + Write: a '1' sets pin to output; a '0' has no effect 1 @@ -7460,7 +7460,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets pin to output; writing a '0' has no effect + Write: a '1' sets pin to output; a '0' has no effect 1 @@ -7487,7 +7487,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets pin to output; writing a '0' has no effect + Write: a '1' sets pin to output; a '0' has no effect 1 @@ -7514,7 +7514,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets pin to output; writing a '0' has no effect + Write: a '1' sets pin to output; a '0' has no effect 1 @@ -7541,7 +7541,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets pin to output; writing a '0' has no effect + Write: a '1' sets pin to output; a '0' has no effect 1 @@ -7568,7 +7568,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets pin to output; writing a '0' has no effect + Write: a '1' sets pin to output; a '0' has no effect 1 @@ -7595,7 +7595,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets pin to output; writing a '0' has no effect + Write: a '1' sets pin to output; a '0' has no effect 1 @@ -7622,7 +7622,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets pin to output; writing a '0' has no effect + Write: a '1' sets pin to output; a '0' has no effect 1 @@ -7649,7 +7649,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Set - Write: writing a '1' sets pin to output; writing a '0' has no effect + Write: a '1' sets pin to output; a '0' has no effect 1 @@ -7685,7 +7685,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect + Write: a '1' sets pin to input; a '0' has no effect 1 @@ -7712,7 +7712,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect + Write: a '1' sets pin to input; a '0' has no effect 1 @@ -7739,7 +7739,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect + Write: a '1' sets pin to input; a '0' has no effect 1 @@ -7766,7 +7766,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect + Write: a '1' sets pin to input; a '0' has no effect 1 @@ -7793,7 +7793,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect + Write: a '1' sets pin to input; a '0' has no effect 1 @@ -7820,7 +7820,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect + Write: a '1' sets pin to input; a '0' has no effect 1 @@ -7847,7 +7847,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect + Write: a '1' sets pin to input; a '0' has no effect 1 @@ -7874,7 +7874,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect + Write: a '1' sets pin to input; a '0' has no effect 1 @@ -7901,7 +7901,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect + Write: a '1' sets pin to input; a '0' has no effect 1 @@ -7928,7 +7928,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect + Write: a '1' sets pin to input; a '0' has no effect 1 @@ -7955,7 +7955,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect + Write: a '1' sets pin to input; a '0' has no effect 1 @@ -7982,7 +7982,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect + Write: a '1' sets pin to input; a '0' has no effect 1 @@ -8009,7 +8009,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect + Write: a '1' sets pin to input; a '0' has no effect 1 @@ -8036,7 +8036,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect + Write: a '1' sets pin to input; a '0' has no effect 1 @@ -8063,7 +8063,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect + Write: a '1' sets pin to input; a '0' has no effect 1 @@ -8090,7 +8090,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect + Write: a '1' sets pin to input; a '0' has no effect 1 @@ -8117,7 +8117,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect + Write: a '1' sets pin to input; a '0' has no effect 1 @@ -8144,7 +8144,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect + Write: a '1' sets pin to input; a '0' has no effect 1 @@ -8171,7 +8171,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect + Write: a '1' sets pin to input; a '0' has no effect 1 @@ -8198,7 +8198,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect + Write: a '1' sets pin to input; a '0' has no effect 1 @@ -8225,7 +8225,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect + Write: a '1' sets pin to input; a '0' has no effect 1 @@ -8252,7 +8252,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect + Write: a '1' sets pin to input; a '0' has no effect 1 @@ -8279,7 +8279,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect + Write: a '1' sets pin to input; a '0' has no effect 1 @@ -8306,7 +8306,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect + Write: a '1' sets pin to input; a '0' has no effect 1 @@ -8333,7 +8333,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect + Write: a '1' sets pin to input; a '0' has no effect 1 @@ -8360,7 +8360,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect + Write: a '1' sets pin to input; a '0' has no effect 1 @@ -8387,7 +8387,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect + Write: a '1' sets pin to input; a '0' has no effect 1 @@ -8414,7 +8414,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect + Write: a '1' sets pin to input; a '0' has no effect 1 @@ -8441,7 +8441,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect + Write: a '1' sets pin to input; a '0' has no effect 1 @@ -8468,7 +8468,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect + Write: a '1' sets pin to input; a '0' has no effect 1 @@ -8495,7 +8495,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect + Write: a '1' sets pin to input; a '0' has no effect 1 @@ -8522,7 +8522,7 @@ POSSIBILITY OF SUCH DAMAGE.\n write Clear - Write: writing a '1' sets pin to input; writing a '0' has no effect + Write: a '1' sets pin to input; a '0' has no effect 1 @@ -9115,13 +9115,13 @@ POSSIBILITY OF SUCH DAMAGE.\n DETECTMODE - Select between default DETECT signal behaviour and LDETECT mode + Select between default DETECT signal behavior and LDETECT mode 0x524 read-write DETECTMODE - Select between default DETECT signal behaviour and LDETECT mode + Select between default DETECT signal behavior and LDETECT mode 0 0 @@ -9132,7 +9132,7 @@ POSSIBILITY OF SUCH DAMAGE.\n LDETECT - Use the latched LDETECT behaviour + Use the latched LDETECT behavior 1 @@ -9825,41 +9825,15 @@ POSSIBILITY OF SUCH DAMAGE.\n - - EVENTS_MHRMATCH - MAC header match found - 0x15C - read-write - - - EVENTS_MHRMATCH - MAC header match found - 0 - 0 - - - NotGenerated - Event not generated - 0 - - - Generated - Event generated - 1 - - - - - EVENTS_PHYEND - Generated when last bit is sent on air + Generated when last bit is sent on air, or received from air 0x16C read-write EVENTS_PHYEND - Generated when last bit is sent on air + Generated when last bit is sent on air, or received from air 0 0 @@ -10458,33 +10432,6 @@ POSSIBILITY OF SUCH DAMAGE.\n - - MHRMATCH - Write '1' to enable interrupt for event MHRMATCH - 23 - 23 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - PHYEND Write '1' to enable interrupt for event PHYEND @@ -10871,33 +10818,6 @@ POSSIBILITY OF SUCH DAMAGE.\n - - MHRMATCH - Write '1' to disable interrupt for event MHRMATCH - 23 - 23 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - PHYEND Write '1' to disable interrupt for event PHYEND @@ -11051,7 +10971,7 @@ POSSIBILITY OF SUCH DAMAGE.\n MAP - Channel map selection. + Channel map selection 8 8 @@ -11179,19 +11099,19 @@ POSSIBILITY OF SUCH DAMAGE.\n LFLEN - Length on air of LENGTH field in number of bits. + Length on air of LENGTH field in number of bits 0 3 S0LEN - Length on air of S0 field in number of bytes. + Length on air of S0 field in number of bytes 8 8 S1LEN - Length on air of S1 field in number of bits. + Length on air of S1 field in number of bits 16 19 @@ -11579,7 +11499,7 @@ POSSIBILITY OF SUCH DAMAGE.\n LEN - CRC length in number of bytes. + CRC length in number of bytes 0 1 @@ -11662,7 +11582,7 @@ POSSIBILITY OF SUCH DAMAGE.\n TIFS - Interframe spacing in us + Interframe spacing in us. 0 9 @@ -11676,7 +11596,7 @@ POSSIBILITY OF SUCH DAMAGE.\n RSSISAMPLE - RSSI sample + RSSI sample. 0 6 @@ -12024,7 +11944,7 @@ POSSIBILITY OF SUCH DAMAGE.\n Fast - Fast ramp-up (tRXEN,FAST and tTXEN,FAST), see electrical specification for more information + Fast ramp-up (tRXEN,FAST and tTXEN,FAST), see electrical specifications for more information 1 @@ -14466,7 +14386,7 @@ POSSIBILITY OF SUCH DAMAGE.\n ERRORSRC - Error source Note : this register is read / write one to clear. + Error source This register is read/write one to clear. 0x480 read-write oneToClear @@ -14814,7 +14734,7 @@ POSSIBILITY OF SUCH DAMAGE.\n Baud1M - 1Mega baud + 1 megabaud 0x10000000 @@ -16064,13 +15984,13 @@ POSSIBILITY OF SUCH DAMAGE.\n EVENTS_SUSPENDED - Last byte has been sent out after the SUSPEND task has been issued, TWI traffic is now suspended. + SUSPEND task has been issued, TWI traffic is now suspended. 0x148 read-write EVENTS_SUSPENDED - Last byte has been sent out after the SUSPEND task has been issued, TWI traffic is now suspended. + SUSPEND task has been issued, TWI traffic is now suspended. 0 0 @@ -18046,7 +17966,7 @@ POSSIBILITY OF SUCH DAMAGE.\n MATCH - Which of the addresses in {ADDRESS} matched the incoming address + Indication of which address in {ADDRESS} that matched the incoming address 0 0 @@ -18646,7 +18566,7 @@ POSSIBILITY OF SUCH DAMAGE.\n TXD - TX data to send. Double buffered + TX data to send. Double buffered. 0 7 @@ -21217,7 +21137,7 @@ POSSIBILITY OF SUCH DAMAGE.\n 0x8 0x4 CONFIG[%s] - Description collection: Configuration for OUT[n], SET[n] and CLR[n] tasks and IN[n] event + Description collection: Configuration for OUT[n], SET[n], and CLR[n] tasks and IN[n] event 0x510 read-write @@ -21246,7 +21166,7 @@ POSSIBILITY OF SUCH DAMAGE.\n PSEL - GPIO number associated with SET[n], CLR[n] and OUT[n] tasks and IN[n] event + GPIO number associated with SET[n], CLR[n], and OUT[n] tasks and IN[n] event 8 12 @@ -25876,14 +25796,14 @@ POSSIBILITY OF SUCH DAMAGE.\n A0 - Slope of 1st piece wise linear function + Slope of first piecewise linear function 0x520 read-write 0x00000326 A0 - Slope of 1st piece wise linear function + Slope of first piecewise linear function 0 11 @@ -25891,14 +25811,14 @@ POSSIBILITY OF SUCH DAMAGE.\n A1 - Slope of 2nd piece wise linear function + Slope of second piecewise linear function 0x524 read-write 0x00000348 A1 - Slope of 2nd piece wise linear function + Slope of second piecewise linear function 0 11 @@ -25906,14 +25826,14 @@ POSSIBILITY OF SUCH DAMAGE.\n A2 - Slope of 3rd piece wise linear function + Slope of third piecewise linear function 0x528 read-write 0x000003AA A2 - Slope of 3rd piece wise linear function + Slope of third piecewise linear function 0 11 @@ -25921,14 +25841,14 @@ POSSIBILITY OF SUCH DAMAGE.\n A3 - Slope of 4th piece wise linear function + Slope of fourth piecewise linear function 0x52C read-write 0x0000040E A3 - Slope of 4th piece wise linear function + Slope of fourth piecewise linear function 0 11 @@ -25936,14 +25856,14 @@ POSSIBILITY OF SUCH DAMAGE.\n A4 - Slope of 5th piece wise linear function + Slope of fifth piecewise linear function 0x530 read-write 0x000004BD A4 - Slope of 5th piece wise linear function + Slope of fifth piecewise linear function 0 11 @@ -25951,14 +25871,14 @@ POSSIBILITY OF SUCH DAMAGE.\n A5 - Slope of 6th piece wise linear function + Slope of sixth piecewise linear function 0x534 read-write 0x000005A3 A5 - Slope of 6th piece wise linear function + Slope of sixth piecewise linear function 0 11 @@ -25966,14 +25886,14 @@ POSSIBILITY OF SUCH DAMAGE.\n B0 - y-intercept of 1st piece wise linear function + y-intercept of first piecewise linear function 0x540 read-write 0x00003FEF B0 - y-intercept of 1st piece wise linear function + y-intercept of first piecewise linear function 0 13 @@ -25981,14 +25901,14 @@ POSSIBILITY OF SUCH DAMAGE.\n B1 - y-intercept of 2nd piece wise linear function + y-intercept of second piecewise linear function 0x544 read-write 0x00003FBE B1 - y-intercept of 2nd piece wise linear function + y-intercept of second piecewise linear function 0 13 @@ -25996,14 +25916,14 @@ POSSIBILITY OF SUCH DAMAGE.\n B2 - y-intercept of 3rd piece wise linear function + y-intercept of third piecewise linear function 0x548 read-write 0x00003FBE B2 - y-intercept of 3rd piece wise linear function + y-intercept of third piecewise linear function 0 13 @@ -26011,14 +25931,14 @@ POSSIBILITY OF SUCH DAMAGE.\n B3 - y-intercept of 4th piece wise linear function + y-intercept of fourth piecewise linear function 0x54C read-write 0x00000012 B3 - y-intercept of 4th piece wise linear function + y-intercept of fourth piecewise linear function 0 13 @@ -26026,14 +25946,14 @@ POSSIBILITY OF SUCH DAMAGE.\n B4 - y-intercept of 5th piece wise linear function + y-intercept of fifth piecewise linear function 0x550 read-write 0x00000124 B4 - y-intercept of 5th piece wise linear function + y-intercept of fifth piecewise linear function 0 13 @@ -26041,14 +25961,14 @@ POSSIBILITY OF SUCH DAMAGE.\n B5 - y-intercept of 6th piece wise linear function + y-intercept of sixth piecewise linear function 0x554 read-write 0x0000027C B5 - y-intercept of 6th piece wise linear function + y-intercept of sixth piecewise linear function 0 13 @@ -26056,14 +25976,14 @@ POSSIBILITY OF SUCH DAMAGE.\n T0 - End point of 1st piece wise linear function + End point of first piecewise linear function 0x560 read-write 0x000000E2 T0 - End point of 1st piece wise linear function + End point of first piecewise linear function 0 7 @@ -26071,14 +25991,14 @@ POSSIBILITY OF SUCH DAMAGE.\n T1 - End point of 2nd piece wise linear function + End point of second piecewise linear function 0x564 read-write 0x00000000 T1 - End point of 2nd piece wise linear function + End point of second piecewise linear function 0 7 @@ -26086,14 +26006,14 @@ POSSIBILITY OF SUCH DAMAGE.\n T2 - End point of 3rd piece wise linear function + End point of third piecewise linear function 0x568 read-write 0x00000019 T2 - End point of 3rd piece wise linear function + End point of third piecewise linear function 0 7 @@ -26101,14 +26021,14 @@ POSSIBILITY OF SUCH DAMAGE.\n T3 - End point of 4th piece wise linear function + End point of fourth piecewise linear function 0x56C read-write 0x0000003C T3 - End point of 4th piece wise linear function + End point of fourth piecewise linear function 0 7 @@ -26116,14 +26036,14 @@ POSSIBILITY OF SUCH DAMAGE.\n T4 - End point of 5th piece wise linear function + End point of fifth piecewise linear function 0x570 read-write 0x00000050 T4 - End point of 5th piece wise linear function + End point of fifth piecewise linear function 0 7 @@ -27035,13 +26955,13 @@ POSSIBILITY OF SUCH DAMAGE.\n TASKS_KSGEN - Start generation of key-stream. This operation will stop by itself when completed. + Start generation of keystream. This operation will stop by itself when completed. 0x000 write-only TASKS_KSGEN - Start generation of key-stream. This operation will stop by itself when completed. + Start generation of keystream. This operation will stop by itself when completed. 0 0 @@ -27119,13 +27039,13 @@ POSSIBILITY OF SUCH DAMAGE.\n EVENTS_ENDKSGEN - Key-stream generation complete + Keystream generation complete 0x100 read-write EVENTS_ENDKSGEN - Key-stream generation complete + Keystream generation complete 0 0 @@ -27512,12 +27432,12 @@ POSSIBILITY OF SUCH DAMAGE.\n Default - Default length. Effective length of LENGTH field in encrypted/decrypted packet is 5 bits. A key-stream for packet payloads up to 27 bytes will be generated. + Default length. Effective length of LENGTH field in encrypted/decrypted packet is 5 bits. A keystream for packet payloads up to 27 bytes will be generated. 0 Extended - Extended length. Effective length of LENGTH field in encrypted/decrypted packet is 8 bits. A key-stream for packet payloads up to MAXPACKETSIZE bytes will be generated. + Extended length. Effective length of LENGTH field in encrypted/decrypted packet is 8 bits. A keystream for packet payloads up to MAXPACKETSIZE bytes will be generated. 1 @@ -27574,7 +27494,7 @@ POSSIBILITY OF SUCH DAMAGE.\n SCRATCHPTR - Pointer to a scratch data area used for temporary storage during key-stream generation, + Pointer to a scratch data area used for temporary storage during keystream generation, MIC generation and encryption/decryption. 0 31 @@ -27583,14 +27503,14 @@ POSSIBILITY OF SUCH DAMAGE.\n MAXPACKETSIZE - Length of key-stream generated when MODE.LENGTH = Extended. + Length of keystream generated when MODE.LENGTH = Extended. 0x518 read-write 0x000000FB MAXPACKETSIZE - Length of key-stream generated when MODE.LENGTH = Extended. This value must be greater or equal to the subsequent packet payload to be encrypted/decrypted. + Length of keystream generated when MODE.LENGTH = Extended. This value must be greater or equal to the subsequent packet payload to be encrypted/decrypted. 0 7 @@ -28195,33 +28115,30 @@ POSSIBILITY OF SUCH DAMAGE.\n - EGU0 - Event Generator Unit 0 - 0x40014000 - EGU + QDEC + Quadrature Decoder + 0x40012000 0 0x1000 registers - SWI0_EGU0 - 20 + QDEC + 18 - EGU + QDEC 0x20 - 0x10 - 0x4 - TASKS_TRIGGER[%s] - Description collection: Trigger n for triggering the corresponding TRIGGERED[n] event + TASKS_START + Task starting the quadrature decoder 0x000 write-only - TASKS_TRIGGER - Trigger n for triggering the corresponding TRIGGERED[n] event + TASKS_START + Task starting the quadrature decoder 0 0 @@ -28235,27 +28152,20 @@ POSSIBILITY OF SUCH DAMAGE.\n - 0x10 - 0x4 - EVENTS_TRIGGERED[%s] - Description collection: Event number n generated by triggering the corresponding TRIGGER[n] task - 0x100 - read-write + TASKS_STOP + Task stopping the quadrature decoder + 0x004 + write-only - EVENTS_TRIGGERED - Event number n generated by triggering the corresponding TRIGGER[n] task + TASKS_STOP + Task stopping the quadrature decoder 0 0 - NotGenerated - Event not generated - 0 - - - Generated - Event generated + Trigger + Trigger task 1 @@ -28263,295 +28173,326 @@ POSSIBILITY OF SUCH DAMAGE.\n - INTEN - Enable or disable interrupt - 0x300 - read-write + TASKS_READCLRACC + Read and clear ACC and ACCDBL + 0x008 + write-only - TRIGGERED0 - Enable or disable interrupt for event TRIGGERED[0] + TASKS_READCLRACC + Read and clear ACC and ACCDBL 0 0 - Disabled - Disable - 0 - - - Enabled - Enable + Trigger + Trigger task 1 + + + + TASKS_RDCLRACC + Read and clear ACC + 0x00C + write-only + - TRIGGERED1 - Enable or disable interrupt for event TRIGGERED[1] - 1 - 1 + TASKS_RDCLRACC + Read and clear ACC + 0 + 0 - Disabled - Disable - 0 - - - Enabled - Enable + Trigger + Trigger task 1 + + + + TASKS_RDCLRDBL + Read and clear ACCDBL + 0x010 + write-only + - TRIGGERED2 - Enable or disable interrupt for event TRIGGERED[2] - 2 - 2 + TASKS_RDCLRDBL + Read and clear ACCDBL + 0 + 0 - Disabled - Disable - 0 - - - Enabled - Enable + Trigger + Trigger task 1 + + + + EVENTS_SAMPLERDY + Event being generated for every new sample value written to the SAMPLE register + 0x100 + read-write + - TRIGGERED3 - Enable or disable interrupt for event TRIGGERED[3] - 3 - 3 + EVENTS_SAMPLERDY + Event being generated for every new sample value written to the SAMPLE register + 0 + 0 - Disabled - Disable + NotGenerated + Event not generated 0 - Enabled - Enable + Generated + Event generated 1 + + + + EVENTS_REPORTRDY + Non-null report ready + 0x104 + read-write + - TRIGGERED4 - Enable or disable interrupt for event TRIGGERED[4] - 4 - 4 + EVENTS_REPORTRDY + Non-null report ready + 0 + 0 - Disabled - Disable + NotGenerated + Event not generated 0 - Enabled - Enable + Generated + Event generated 1 + + + + EVENTS_ACCOF + ACC or ACCDBL register overflow + 0x108 + read-write + - TRIGGERED5 - Enable or disable interrupt for event TRIGGERED[5] - 5 - 5 + EVENTS_ACCOF + ACC or ACCDBL register overflow + 0 + 0 - Disabled - Disable + NotGenerated + Event not generated 0 - Enabled - Enable + Generated + Event generated 1 + + + + EVENTS_DBLRDY + Double displacement(s) detected + 0x10C + read-write + - TRIGGERED6 - Enable or disable interrupt for event TRIGGERED[6] - 6 - 6 + EVENTS_DBLRDY + Double displacement(s) detected + 0 + 0 - Disabled - Disable + NotGenerated + Event not generated 0 - Enabled - Enable + Generated + Event generated 1 + + + + EVENTS_STOPPED + QDEC has been stopped + 0x110 + read-write + - TRIGGERED7 - Enable or disable interrupt for event TRIGGERED[7] - 7 - 7 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - TRIGGERED8 - Enable or disable interrupt for event TRIGGERED[8] - 8 - 8 + EVENTS_STOPPED + QDEC has been stopped + 0 + 0 - Disabled - Disable + NotGenerated + Event not generated 0 - Enabled - Enable + Generated + Event generated 1 + + + + SHORTS + Shortcuts between local events and tasks + 0x200 + read-write + - TRIGGERED9 - Enable or disable interrupt for event TRIGGERED[9] - 9 - 9 + REPORTRDY_READCLRACC + Shortcut between event REPORTRDY and task READCLRACC + 0 + 0 Disabled - Disable + Disable shortcut 0 Enabled - Enable + Enable shortcut 1 - TRIGGERED10 - Enable or disable interrupt for event TRIGGERED[10] - 10 - 10 + SAMPLERDY_STOP + Shortcut between event SAMPLERDY and task STOP + 1 + 1 Disabled - Disable + Disable shortcut 0 Enabled - Enable + Enable shortcut 1 - TRIGGERED11 - Enable or disable interrupt for event TRIGGERED[11] - 11 - 11 + REPORTRDY_RDCLRACC + Shortcut between event REPORTRDY and task RDCLRACC + 2 + 2 Disabled - Disable + Disable shortcut 0 Enabled - Enable + Enable shortcut 1 - TRIGGERED12 - Enable or disable interrupt for event TRIGGERED[12] - 12 - 12 + REPORTRDY_STOP + Shortcut between event REPORTRDY and task STOP + 3 + 3 Disabled - Disable + Disable shortcut 0 Enabled - Enable + Enable shortcut 1 - TRIGGERED13 - Enable or disable interrupt for event TRIGGERED[13] - 13 - 13 + DBLRDY_RDCLRDBL + Shortcut between event DBLRDY and task RDCLRDBL + 4 + 4 Disabled - Disable + Disable shortcut 0 Enabled - Enable + Enable shortcut 1 - TRIGGERED14 - Enable or disable interrupt for event TRIGGERED[14] - 14 - 14 + DBLRDY_STOP + Shortcut between event DBLRDY and task STOP + 5 + 5 Disabled - Disable + Disable shortcut 0 Enabled - Enable + Enable shortcut 1 - TRIGGERED15 - Enable or disable interrupt for event TRIGGERED[15] - 15 - 15 + SAMPLERDY_READCLRACC + Shortcut between event SAMPLERDY and task READCLRACC + 6 + 6 Disabled - Disable + Disable shortcut 0 Enabled - Enable + Enable shortcut 1 @@ -28565,8 +28506,8 @@ POSSIBILITY OF SUCH DAMAGE.\n read-write - TRIGGERED0 - Write '1' to enable interrupt for event TRIGGERED[0] + SAMPLERDY + Write '1' to enable interrupt for event SAMPLERDY 0 0 @@ -28592,8 +28533,8 @@ POSSIBILITY OF SUCH DAMAGE.\n - TRIGGERED1 - Write '1' to enable interrupt for event TRIGGERED[1] + REPORTRDY + Write '1' to enable interrupt for event REPORTRDY 1 1 @@ -28619,8 +28560,8 @@ POSSIBILITY OF SUCH DAMAGE.\n - TRIGGERED2 - Write '1' to enable interrupt for event TRIGGERED[2] + ACCOF + Write '1' to enable interrupt for event ACCOF 2 2 @@ -28646,8 +28587,8 @@ POSSIBILITY OF SUCH DAMAGE.\n - TRIGGERED3 - Write '1' to enable interrupt for event TRIGGERED[3] + DBLRDY + Write '1' to enable interrupt for event DBLRDY 3 3 @@ -28673,8 +28614,8 @@ POSSIBILITY OF SUCH DAMAGE.\n - TRIGGERED4 - Write '1' to enable interrupt for event TRIGGERED[4] + STOPPED + Write '1' to enable interrupt for event STOPPED 4 4 @@ -28699,11 +28640,19 @@ POSSIBILITY OF SUCH DAMAGE.\n + + + + INTENCLR + Disable interrupt + 0x308 + read-write + - TRIGGERED5 - Write '1' to enable interrupt for event TRIGGERED[5] - 5 - 5 + SAMPLERDY + Write '1' to disable interrupt for event SAMPLERDY + 0 + 0 read @@ -28720,17 +28669,17 @@ POSSIBILITY OF SUCH DAMAGE.\n write - Set - Enable + Clear + Disable 1 - TRIGGERED6 - Write '1' to enable interrupt for event TRIGGERED[6] - 6 - 6 + REPORTRDY + Write '1' to disable interrupt for event REPORTRDY + 1 + 1 read @@ -28747,17 +28696,17 @@ POSSIBILITY OF SUCH DAMAGE.\n write - Set - Enable + Clear + Disable 1 - TRIGGERED7 - Write '1' to enable interrupt for event TRIGGERED[7] - 7 - 7 + ACCOF + Write '1' to disable interrupt for event ACCOF + 2 + 2 read @@ -28774,17 +28723,17 @@ POSSIBILITY OF SUCH DAMAGE.\n write - Set - Enable + Clear + Disable 1 - TRIGGERED8 - Write '1' to enable interrupt for event TRIGGERED[8] - 8 - 8 + DBLRDY + Write '1' to disable interrupt for event DBLRDY + 3 + 3 read @@ -28801,17 +28750,17 @@ POSSIBILITY OF SUCH DAMAGE.\n write - Set - Enable + Clear + Disable 1 - TRIGGERED9 - Write '1' to enable interrupt for event TRIGGERED[9] - 9 - 9 + STOPPED + Write '1' to disable interrupt for event STOPPED + 4 + 4 read @@ -28828,538 +28777,795 @@ POSSIBILITY OF SUCH DAMAGE.\n write - Set - Enable + Clear + Disable 1 + + + + ENABLE + Enable the quadrature decoder + 0x500 + read-write + - TRIGGERED10 - Write '1' to enable interrupt for event TRIGGERED[10] - 10 - 10 + ENABLE + Enable or disable the quadrature decoder + 0 + 0 - read Disabled - Read: Disabled + Disable 0 Enabled - Read: Enabled - 1 - - - - write - - Set Enable 1 + + + + LEDPOL + LED output pin polarity + 0x504 + read-write + - TRIGGERED11 - Write '1' to enable interrupt for event TRIGGERED[11] - 11 - 11 + LEDPOL + LED output pin polarity + 0 + 0 - read - Disabled - Read: Disabled + ActiveLow + Led active on output pin low 0 - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable + ActiveHigh + Led active on output pin high 1 + + + + SAMPLEPER + Sample period + 0x508 + read-write + - TRIGGERED12 - Write '1' to enable interrupt for event TRIGGERED[12] - 12 - 12 + SAMPLEPER + Sample period. The SAMPLE register will be updated for every new sample + 0 + 3 - read - Disabled - Read: Disabled + 128us + 128 us 0 - Enabled - Read: Enabled + 256us + 256 us 1 - - - write - Set - Enable - 1 - - - - - TRIGGERED13 - Write '1' to enable interrupt for event TRIGGERED[13] - 13 - 13 - - read - - Disabled - Read: Disabled - 0 + 512us + 512 us + 2 - Enabled - Read: Enabled - 1 + 1024us + 1024 us + 3 - - - write - Set - Enable - 1 + 2048us + 2048 us + 4 - - - - TRIGGERED14 - Write '1' to enable interrupt for event TRIGGERED[14] - 14 - 14 - - read - Disabled - Read: Disabled - 0 + 4096us + 4096 us + 5 - Enabled - Read: Enabled - 1 + 8192us + 8192 us + 6 - - - write - Set - Enable - 1 + 16384us + 16384 us + 7 - - - - TRIGGERED15 - Write '1' to enable interrupt for event TRIGGERED[15] - 15 - 15 - - read - Disabled - Read: Disabled - 0 + 32ms + 32768 us + 8 - Enabled - Read: Enabled - 1 + 65ms + 65536 us + 9 - - - write - Set - Enable - 1 + 131ms + 131072 us + 10 - INTENCLR - Disable interrupt - 0x308 - read-write + SAMPLE + Motion sample value + 0x50C + read-only + int32_t - TRIGGERED0 - Write '1' to disable interrupt for event TRIGGERED[0] + SAMPLE + Last motion sample 0 - 0 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - + 31 + + + + REPORTPER + Number of samples to be taken before REPORTRDY and DBLRDY events can be generated + 0x510 + read-write + - TRIGGERED1 - Write '1' to disable interrupt for event TRIGGERED[1] - 1 - 1 + REPORTPER + Specifies the number of samples to be accumulated in the ACC register before the REPORTRDY and DBLRDY events can be generated. + 0 + 3 - read - Disabled - Read: Disabled + 10Smpl + 10 samples/report 0 - Enabled - Read: Enabled + 40Smpl + 40 samples/report 1 - - - write - Clear - Disable - 1 + 80Smpl + 80 samples/report + 2 - - - - TRIGGERED2 - Write '1' to disable interrupt for event TRIGGERED[2] - 2 - 2 - - read - Disabled - Read: Disabled - 0 + 120Smpl + 120 samples/report + 3 - Enabled - Read: Enabled - 1 + 160Smpl + 160 samples/report + 4 - - - write - Clear - Disable - 1 + 200Smpl + 200 samples/report + 5 - - - - TRIGGERED3 - Write '1' to disable interrupt for event TRIGGERED[3] - 3 - 3 - - read - Disabled - Read: Disabled - 0 + 240Smpl + 240 samples/report + 6 - Enabled - Read: Enabled - 1 + 280Smpl + 280 samples/report + 7 - - - write - Clear - Disable - 1 + 1Smpl + 1 sample/report + 8 + + + + ACC + Register accumulating the valid transitions + 0x514 + read-only + int32_t + - TRIGGERED4 - Write '1' to disable interrupt for event TRIGGERED[4] - 4 - 4 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - + ACC + Register accumulating all valid samples (not double transition) read from the SAMPLE register. + 0 + 31 + + + + ACCREAD + Snapshot of the ACC register, updated by the READCLRACC or RDCLRACC task + 0x518 + read-only + int32_t + - TRIGGERED5 - Write '1' to disable interrupt for event TRIGGERED[5] - 5 - 5 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - + ACCREAD + Snapshot of the ACC register. + 0 + 31 - - TRIGGERED6 - Write '1' to disable interrupt for event TRIGGERED[6] - 6 - 6 - - read - - Disabled - Read: Disabled + + + + PSEL + Unspecified + QDEC_PSEL + read-write + 0x51C + + LED + Pin select for LED signal + 0x000 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + A + Pin select for A signal + 0x004 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + B + Pin select for B signal + 0x008 + read-write + 0xFFFFFFFF + + + PIN + Pin number + 0 + 4 + + + CONNECT + Connection + 31 + 31 + + + Disconnected + Disconnect + 1 + + + Connected + Connect + 0 + + + + + + + + DBFEN + Enable input debounce filters + 0x528 + read-write + + + DBFEN + Enable input debounce filters + 0 + 0 + + + Disabled + Debounce input filters disabled 0 Enabled - Read: Enabled + Debounce input filters enabled 1 + + + + + LEDPRE + Time period the LED is switched ON prior to sampling + 0x540 + read-write + 0x00000010 + + + LEDPRE + Period in us the LED is switched on prior to sampling + 0 + 8 + + + + + ACCDBL + Register accumulating the number of detected double transitions + 0x544 + read-only + + + ACCDBL + Register accumulating the number of detected double or illegal transitions. ( SAMPLE = 2 ). + 0 + 3 + + + + + ACCDBLREAD + Snapshot of the ACCDBL, updated by the READCLRACC or RDCLRDBL task + 0x548 + read-only + + + ACCDBLREAD + Snapshot of the ACCDBL register. This field is updated when the READCLRACC or RDCLRDBL task is triggered. + 0 + 3 + + + + + + + EGU0 + Event generator unit 0 + 0x40014000 + EGU + + 0 + 0x1000 + registers + + + SWI0_EGU0 + 20 + + EGU + 0x20 + + + 0x10 + 0x4 + TASKS_TRIGGER[%s] + Description collection: Trigger n for triggering the corresponding TRIGGERED[n] event + 0x000 + write-only + + + TASKS_TRIGGER + Trigger n for triggering the corresponding TRIGGERED[n] event + 0 + 0 - write - Clear - Disable + Trigger + Trigger task 1 + + + + 0x10 + 0x4 + EVENTS_TRIGGERED[%s] + Description collection: Event number n generated by triggering the corresponding TRIGGER[n] task + 0x100 + read-write + - TRIGGERED7 - Write '1' to disable interrupt for event TRIGGERED[7] - 7 - 7 + EVENTS_TRIGGERED + Event number n generated by triggering the corresponding TRIGGER[n] task + 0 + 0 - read - Disabled - Read: Disabled + NotGenerated + Event not generated 0 - Enabled - Read: Enabled + Generated + Event generated 1 + + + + + INTEN + Enable or disable interrupt + 0x300 + read-write + + + TRIGGERED0 + Enable or disable interrupt for event TRIGGERED[0] + 0 + 0 - write - Clear + Disabled Disable + 0 + + + Enabled + Enable 1 - TRIGGERED8 - Write '1' to disable interrupt for event TRIGGERED[8] - 8 - 8 + TRIGGERED1 + Enable or disable interrupt for event TRIGGERED[1] + 1 + 1 - read Disabled - Read: Disabled + Disable 0 Enabled - Read: Enabled + Enable 1 + + + TRIGGERED2 + Enable or disable interrupt for event TRIGGERED[2] + 2 + 2 - write - Clear + Disabled Disable - 1 + 0 - - + + Enabled + Enable + 1 + + + - TRIGGERED9 - Write '1' to disable interrupt for event TRIGGERED[9] - 9 - 9 + TRIGGERED3 + Enable or disable interrupt for event TRIGGERED[3] + 3 + 3 - read Disabled - Read: Disabled + Disable 0 Enabled - Read: Enabled + Enable 1 + + + TRIGGERED4 + Enable or disable interrupt for event TRIGGERED[4] + 4 + 4 - write - Clear + Disabled Disable + 0 + + + Enabled + Enable 1 - TRIGGERED10 - Write '1' to disable interrupt for event TRIGGERED[10] - 10 - 10 + TRIGGERED5 + Enable or disable interrupt for event TRIGGERED[5] + 5 + 5 - read Disabled - Read: Disabled + Disable 0 Enabled - Read: Enabled + Enable 1 + + + TRIGGERED6 + Enable or disable interrupt for event TRIGGERED[6] + 6 + 6 - write - Clear + Disabled Disable + 0 + + + Enabled + Enable 1 - TRIGGERED11 - Write '1' to disable interrupt for event TRIGGERED[11] - 11 - 11 + TRIGGERED7 + Enable or disable interrupt for event TRIGGERED[7] + 7 + 7 - read Disabled - Read: Disabled + Disable 0 Enabled - Read: Enabled + Enable 1 + + + TRIGGERED8 + Enable or disable interrupt for event TRIGGERED[8] + 8 + 8 - write - Clear + Disabled Disable + 0 + + + Enabled + Enable 1 - TRIGGERED12 - Write '1' to disable interrupt for event TRIGGERED[12] - 12 - 12 + TRIGGERED9 + Enable or disable interrupt for event TRIGGERED[9] + 9 + 9 - read Disabled - Read: Disabled + Disable 0 Enabled - Read: Enabled + Enable 1 + + + TRIGGERED10 + Enable or disable interrupt for event TRIGGERED[10] + 10 + 10 - write - Clear + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + TRIGGERED11 + Enable or disable interrupt for event TRIGGERED[11] + 11 + 11 + + + Disabled Disable + 0 + + + Enabled + Enable + 1 + + + + + TRIGGERED12 + Enable or disable interrupt for event TRIGGERED[12] + 12 + 12 + + + Disabled + Disable + 0 + + + Enabled + Enable 1 TRIGGERED13 - Write '1' to disable interrupt for event TRIGGERED[13] + Enable or disable interrupt for event TRIGGERED[13] 13 13 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + TRIGGERED14 + Enable or disable interrupt for event TRIGGERED[14] + 14 + 14 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + TRIGGERED15 + Enable or disable interrupt for event TRIGGERED[15] + 15 + 15 + + + Disabled + Disable + 0 + + + Enabled + Enable + 1 + + + + + + + INTENSET + Enable interrupt + 0x304 + read-write + + + TRIGGERED0 + Write '1' to enable interrupt for event TRIGGERED[0] + 0 + 0 read @@ -29376,17 +29582,17 @@ POSSIBILITY OF SUCH DAMAGE.\n write - Clear - Disable + Set + Enable 1 - TRIGGERED14 - Write '1' to disable interrupt for event TRIGGERED[14] - 14 - 14 + TRIGGERED1 + Write '1' to enable interrupt for event TRIGGERED[1] + 1 + 1 read @@ -29403,17 +29609,17 @@ POSSIBILITY OF SUCH DAMAGE.\n write - Clear - Disable + Set + Enable 1 - TRIGGERED15 - Write '1' to disable interrupt for event TRIGGERED[15] - 15 - 15 + TRIGGERED2 + Write '1' to enable interrupt for event TRIGGERED[2] + 2 + 2 read @@ -29430,935 +29636,1048 @@ POSSIBILITY OF SUCH DAMAGE.\n write - Clear - Disable + Set + Enable 1 - - - - - - SWI0 - Software interrupt 0 - 0x40014000 - EGU0 - SWI - - 0 - 0x1000 - registers - - - SWI0_EGU0 - 20 - - SWI - 0x20 - - - UNUSED - Unused. - 0x000 - 0x00000000 - read-only - - - - - EGU1 - Event Generator Unit 1 - 0x40015000 - - SWI1_EGU1 - 21 - - - - SWI1 - Software interrupt 1 - 0x40015000 - EGU1 - - SWI1_EGU1 - 21 - - - - SWI2 - Software interrupt 2 - 0x40016000 - - SWI2 - 22 - - - - SWI3 - Software interrupt 3 - 0x40017000 - - SWI3 - 23 - - - - SWI4 - Software interrupt 4 - 0x40018000 - - SWI4 - 24 - - - - SWI5 - Software interrupt 5 - 0x40019000 - - SWI5 - 25 - - - - NVMC - Non-volatile memory controller - 0x4001E000 - - 0 - 0x1000 - registers - - NVMC - 0x20 - - - READY - Ready flag - 0x400 - read-only - 0x00000001 - - READY - NVMC is ready or busy - 0 - 0 + TRIGGERED3 + Write '1' to enable interrupt for event TRIGGERED[3] + 3 + 3 + read - Busy - NVMC is busy (ongoing write or erase operation) + Disabled + Read: Disabled 0 - Ready - NVMC is ready + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable 1 - - - - CONFIG - Configuration register - 0x504 - read-write - - WEN - Program memory access mode. It is strongly recommended to activate erase and write modes only when they are actively used. - 0 - 1 + TRIGGERED4 + Write '1' to enable interrupt for event TRIGGERED[4] + 4 + 4 + read - Ren - Read only access + Disabled + Read: Disabled 0 - Wen - Write enabled + Enabled + Read: Enabled 1 + + + write - Een - Erase enabled - 2 + Set + Enable + 1 - - - - ERASEPAGE - Register for erasing a page in code area - 0x508 - read-write - - - ERASEPAGE - Register for starting erase of a page in code area. - 0 - 31 - - - - - ERASEPCR1 - Deprecated register - Register for erasing a page in code area. Equivalent to ERASEPAGE. - 0x508 - read-write - ERASEPAGE - - - ERASEPCR1 - Register for erasing a page in code area. Equivalent to ERASEPAGE. - 0 - 31 - - - - - ERASEALL - Register for erasing all non-volatile user memory - 0x50C - read-write - - ERASEALL - Erase all non-volatile memory including UICR registers. Note that the erase must be enabled using CONFIG.WEN before the non-volatile memory can be erased. - 0 - 0 + TRIGGERED5 + Write '1' to enable interrupt for event TRIGGERED[5] + 5 + 5 + read - NoOperation - No operation + Disabled + Read: Disabled 0 - Erase - Start erase of chip + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable 1 - - - - ERASEPCR0 - Deprecated register - Register for erasing a page in code area. Equivalent to ERASEPAGE. - 0x510 - read-write - - - ERASEPCR0 - Register for starting erase of a page in code area. Equivalent to ERASEPAGE. - 0 - 31 - - - - - ERASEUICR - Register for erasing user information configuration registers - 0x514 - read-write - - ERASEUICR - Register starting erase of all user information configuration registers. Note that the erase must be enabled using CONFIG.WEN before the UICR can be erased. - 0 - 0 + TRIGGERED6 + Write '1' to enable interrupt for event TRIGGERED[6] + 6 + 6 + read - NoOperation - No operation + Disabled + Read: Disabled 0 - Erase - Start erase of UICR + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable 1 - - - - ERASEPAGEPARTIAL - Register for partial erase of a page in code area - 0x518 - read-write - - ERASEPAGEPARTIAL - Register for starting partial erase of a page in code area - 0 - 31 + TRIGGERED7 + Write '1' to enable interrupt for event TRIGGERED[7] + 7 + 7 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + - - - - ERASEPAGEPARTIALCFG - Register for partial erase configuration - 0x51C - read-write - 0x0000000A - - DURATION - Duration of the partial erase in milliseconds - 0 - 6 + TRIGGERED8 + Write '1' to enable interrupt for event TRIGGERED[8] + 8 + 8 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + - - - - - - PPI - Programmable Peripheral Interconnect - 0x4001F000 - - 0 - 0x1000 - registers - - PPI - 0x20 - - - 6 - 0x008 - TASKS_CHG[%s] - Channel group tasks - PPI_TASKS_CHG - write-only - 0x000 - - EN - Description cluster: Enable channel group n - 0x000 - write-only - - - EN - Enable channel group n - 0 - 0 - - - Trigger - Trigger task - 1 - - - - - - - DIS - Description cluster: Disable channel group n - 0x004 - write-only - - - DIS - Disable channel group n - 0 - 0 - - - Trigger - Trigger task - 1 - - - - - - + + TRIGGERED9 + Write '1' to enable interrupt for event TRIGGERED[9] + 9 + 9 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + TRIGGERED10 + Write '1' to enable interrupt for event TRIGGERED[10] + 10 + 10 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + TRIGGERED11 + Write '1' to enable interrupt for event TRIGGERED[11] + 11 + 11 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + TRIGGERED12 + Write '1' to enable interrupt for event TRIGGERED[12] + 12 + 12 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + TRIGGERED13 + Write '1' to enable interrupt for event TRIGGERED[13] + 13 + 13 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + TRIGGERED14 + Write '1' to enable interrupt for event TRIGGERED[14] + 14 + 14 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + TRIGGERED15 + Write '1' to enable interrupt for event TRIGGERED[15] + 15 + 15 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + + + - CHEN - Channel enable register - 0x500 + INTENCLR + Disable interrupt + 0x308 read-write - CH0 - Enable or disable channel 0 + TRIGGERED0 + Write '1' to disable interrupt for event TRIGGERED[0] 0 0 + read Disabled - Disable channel + Read: Disabled 0 Enabled - Enable channel + Read: Enabled + 1 + + + + write + + Clear + Disable 1 - CH1 - Enable or disable channel 1 + TRIGGERED1 + Write '1' to disable interrupt for event TRIGGERED[1] 1 1 + read Disabled - Disable channel + Read: Disabled 0 Enabled - Enable channel + Read: Enabled + 1 + + + + write + + Clear + Disable 1 - CH2 - Enable or disable channel 2 + TRIGGERED2 + Write '1' to disable interrupt for event TRIGGERED[2] 2 2 + read Disabled - Disable channel + Read: Disabled 0 Enabled - Enable channel + Read: Enabled + 1 + + + + write + + Clear + Disable 1 - CH3 - Enable or disable channel 3 + TRIGGERED3 + Write '1' to disable interrupt for event TRIGGERED[3] 3 3 + read Disabled - Disable channel + Read: Disabled 0 Enabled - Enable channel + Read: Enabled + 1 + + + + write + + Clear + Disable 1 - CH4 - Enable or disable channel 4 + TRIGGERED4 + Write '1' to disable interrupt for event TRIGGERED[4] 4 4 + read Disabled - Disable channel + Read: Disabled 0 Enabled - Enable channel + Read: Enabled + 1 + + + + write + + Clear + Disable 1 - CH5 - Enable or disable channel 5 + TRIGGERED5 + Write '1' to disable interrupt for event TRIGGERED[5] 5 5 + read Disabled - Disable channel + Read: Disabled 0 Enabled - Enable channel + Read: Enabled + 1 + + + + write + + Clear + Disable 1 - CH6 - Enable or disable channel 6 + TRIGGERED6 + Write '1' to disable interrupt for event TRIGGERED[6] 6 6 + read Disabled - Disable channel + Read: Disabled 0 Enabled - Enable channel + Read: Enabled 1 - - - CH7 - Enable or disable channel 7 - 7 - 7 + write - Disabled - Disable channel - 0 - - - Enabled - Enable channel + Clear + Disable 1 - CH8 - Enable or disable channel 8 - 8 - 8 + TRIGGERED7 + Write '1' to disable interrupt for event TRIGGERED[7] + 7 + 7 + read Disabled - Disable channel + Read: Disabled 0 Enabled - Enable channel + Read: Enabled 1 - - - CH9 - Enable or disable channel 9 - 9 - 9 + write - Disabled - Disable channel - 0 - - - Enabled - Enable channel + Clear + Disable 1 - CH10 - Enable or disable channel 10 - 10 - 10 + TRIGGERED8 + Write '1' to disable interrupt for event TRIGGERED[8] + 8 + 8 + read Disabled - Disable channel + Read: Disabled 0 Enabled - Enable channel + Read: Enabled 1 - - - CH11 - Enable or disable channel 11 - 11 - 11 + write - Disabled - Disable channel - 0 - - - Enabled - Enable channel + Clear + Disable 1 - CH12 - Enable or disable channel 12 - 12 - 12 + TRIGGERED9 + Write '1' to disable interrupt for event TRIGGERED[9] + 9 + 9 + read Disabled - Disable channel + Read: Disabled 0 Enabled - Enable channel + Read: Enabled 1 - - - CH13 - Enable or disable channel 13 - 13 - 13 + write - Disabled - Disable channel - 0 - - - Enabled - Enable channel + Clear + Disable 1 - CH14 - Enable or disable channel 14 - 14 - 14 + TRIGGERED10 + Write '1' to disable interrupt for event TRIGGERED[10] + 10 + 10 + read Disabled - Disable channel + Read: Disabled 0 Enabled - Enable channel + Read: Enabled 1 - - - CH15 - Enable or disable channel 15 - 15 - 15 + write - Disabled - Disable channel - 0 - - - Enabled - Enable channel + Clear + Disable 1 - CH16 - Enable or disable channel 16 - 16 - 16 + TRIGGERED11 + Write '1' to disable interrupt for event TRIGGERED[11] + 11 + 11 + read Disabled - Disable channel + Read: Disabled 0 Enabled - Enable channel + Read: Enabled 1 - - - CH17 - Enable or disable channel 17 - 17 - 17 + write - Disabled - Disable channel - 0 - - - Enabled - Enable channel + Clear + Disable 1 - CH18 - Enable or disable channel 18 - 18 - 18 + TRIGGERED12 + Write '1' to disable interrupt for event TRIGGERED[12] + 12 + 12 + read Disabled - Disable channel + Read: Disabled 0 Enabled - Enable channel + Read: Enabled 1 - - - CH19 - Enable or disable channel 19 - 19 - 19 + write - Disabled - Disable channel - 0 - - - Enabled - Enable channel + Clear + Disable 1 - CH20 - Enable or disable channel 20 - 20 - 20 + TRIGGERED13 + Write '1' to disable interrupt for event TRIGGERED[13] + 13 + 13 + read Disabled - Disable channel + Read: Disabled 0 Enabled - Enable channel + Read: Enabled 1 - - - CH21 - Enable or disable channel 21 - 21 - 21 + write - Disabled - Disable channel - 0 - - - Enabled - Enable channel + Clear + Disable 1 - CH22 - Enable or disable channel 22 - 22 - 22 + TRIGGERED14 + Write '1' to disable interrupt for event TRIGGERED[14] + 14 + 14 + read Disabled - Disable channel + Read: Disabled 0 Enabled - Enable channel + Read: Enabled 1 - - - CH23 - Enable or disable channel 23 - 23 - 23 + write - Disabled - Disable channel - 0 - - - Enabled - Enable channel + Clear + Disable 1 - CH24 - Enable or disable channel 24 - 24 - 24 + TRIGGERED15 + Write '1' to disable interrupt for event TRIGGERED[15] + 15 + 15 + read Disabled - Disable channel + Read: Disabled 0 Enabled - Enable channel + Read: Enabled + 1 + + + + write + + Clear + Disable 1 + + + + + + SWI0 + Software interrupt 0 + 0x40014000 + EGU0 + SWI + + 0 + 0x1000 + registers + + + SWI0_EGU0 + 20 + + SWI + 0x20 + + + UNUSED + Unused. + 0x000 + 0x00000000 + read-only + + + + + EGU1 + Event generator unit 1 + 0x40015000 + + SWI1_EGU1 + 21 + + + + SWI1 + Software interrupt 1 + 0x40015000 + EGU1 + + SWI1_EGU1 + 21 + + + + SWI2 + Software interrupt 2 + 0x40016000 + + SWI2 + 22 + + + + SWI3 + Software interrupt 3 + 0x40017000 + + SWI3 + 23 + + + + SWI4 + Software interrupt 4 + 0x40018000 + + SWI4 + 24 + + + + SWI5 + Software interrupt 5 + 0x40019000 + + SWI5 + 25 + + + + NVMC + Non Volatile Memory Controller + 0x4001E000 + + 0 + 0x1000 + registers + + NVMC + 0x20 + + + READY + Ready flag + 0x400 + read-only + 0x00000001 + - CH25 - Enable or disable channel 25 - 25 - 25 + READY + NVMC is ready or busy + 0 + 0 - Disabled - Disable channel + Busy + NVMC is busy (on-going write or erase operation) 0 - Enabled - Enable channel + Ready + NVMC is ready 1 + + + + CONFIG + Configuration register + 0x504 + read-write + - CH26 - Enable or disable channel 26 - 26 - 26 + WEN + Program memory access mode. It is strongly recommended to only activate erase and write modes when they are actively used. + 0 + 1 - Disabled - Disable channel + Ren + Read only access 0 - Enabled - Enable channel + Wen + Write enabled 1 - - - - CH27 - Enable or disable channel 27 - 27 - 27 - - - Disabled - Disable channel - 0 - - Enabled - Enable channel - 1 + Een + Erase enabled + 2 + + + + ERASEPAGE + Register for erasing a page in code area + 0x508 + write-only + - CH28 - Enable or disable channel 28 - 28 - 28 - - - Disabled - Disable channel - 0 - - - Enabled - Enable channel - 1 - - + ERASEPAGE + Register for starting erase of a page in code area + 0 + 31 + + + + ERASEPCR1 + Deprecated register - Register for erasing a page in code area, equivalent to ERASEPAGE + 0x508 + write-only + ERASEPAGE + - CH29 - Enable or disable channel 29 - 29 - 29 - - - Disabled - Disable channel - 0 - - - Enabled - Enable channel - 1 - - + ERASEPCR1 + Register for erasing a page in code area, equivalent to ERASEPAGE + 0 + 31 + + + + ERASEALL + Register for erasing all non-volatile user memory + 0x50C + write-only + - CH30 - Enable or disable channel 30 - 30 - 30 + ERASEALL + Erase all non-volatile memory including UICR registers. The erase must be enabled using CONFIG.WEN before the non-volatile memory can be erased. + 0 + 0 - Disabled - Disable channel + NoOperation + No operation 0 - Enabled - Enable channel + Erase + Start chip erase 1 + + + + ERASEPCR0 + Deprecated register - Register for erasing a page in code area, equivalent to ERASEPAGE + 0x510 + write-only + - CH31 - Enable or disable channel 31 - 31 + ERASEPCR0 + Register for starting erase of a page in code area, equivalent to ERASEPAGE + 0 31 + + + + + ERASEUICR + Register for erasing user information configuration registers + 0x514 + write-only + + + ERASEUICR + Register starting erase of all user information configuration registers. The erase must be enabled using CONFIG.WEN before the UICR can be erased. + 0 + 0 - Disabled - Disable channel + NoOperation + No operation 0 - Enabled - Enable channel + Erase + Start erase of UICR 1 @@ -30366,557 +30685,515 @@ POSSIBILITY OF SUCH DAMAGE.\n - CHENSET - Channel enable set register - 0x504 + ERASEPAGEPARTIAL + Register for partial erase of a page in code area + 0x518 + write-only + + + ERASEPAGEPARTIAL + Register for starting partial erase of a page in code area + 0 + 31 + + + + + ERASEPAGEPARTIALCFG + Register for partial erase configuration + 0x51C + read-write + 0x0000000A + + + DURATION + Duration of the partial erase in milliseconds + 0 + 6 + + + + + + + PPI + Programmable Peripheral Interconnect + 0x4001F000 + + 0 + 0x1000 + registers + + PPI + 0x20 + + + 6 + 0x008 + TASKS_CHG[%s] + Channel group tasks + PPI_TASKS_CHG + write-only + 0x000 + + EN + Description cluster: Enable channel group n + 0x000 + write-only + + + EN + Enable channel group n + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + DIS + Description cluster: Disable channel group n + 0x004 + write-only + + + DIS + Disable channel group n + 0 + 0 + + + Trigger + Trigger task + 1 + + + + + + + + CHEN + Channel enable register + 0x500 read-write - oneToSet CH0 - Channel 0 enable set register. Writing '0' has no effect + Enable or disable channel 0 0 0 - read Disabled - Read: channel disabled + Disable channel 0 Enabled - Read: channel enabled - 1 - - - - write - - Set - Write: Enable channel + Enable channel 1 CH1 - Channel 1 enable set register. Writing '0' has no effect + Enable or disable channel 1 1 1 - read Disabled - Read: channel disabled + Disable channel 0 Enabled - Read: channel enabled - 1 - - - - write - - Set - Write: Enable channel + Enable channel 1 CH2 - Channel 2 enable set register. Writing '0' has no effect + Enable or disable channel 2 2 2 - read Disabled - Read: channel disabled + Disable channel 0 Enabled - Read: channel enabled - 1 - - - - write - - Set - Write: Enable channel + Enable channel 1 CH3 - Channel 3 enable set register. Writing '0' has no effect + Enable or disable channel 3 3 3 - read Disabled - Read: channel disabled + Disable channel 0 Enabled - Read: channel enabled - 1 - - - - write - - Set - Write: Enable channel + Enable channel 1 CH4 - Channel 4 enable set register. Writing '0' has no effect + Enable or disable channel 4 4 4 - read Disabled - Read: channel disabled + Disable channel 0 Enabled - Read: channel enabled - 1 - - - - write - - Set - Write: Enable channel + Enable channel 1 CH5 - Channel 5 enable set register. Writing '0' has no effect + Enable or disable channel 5 5 5 - read Disabled - Read: channel disabled + Disable channel 0 Enabled - Read: channel enabled - 1 - - - - write - - Set - Write: Enable channel + Enable channel 1 CH6 - Channel 6 enable set register. Writing '0' has no effect + Enable or disable channel 6 6 6 - read Disabled - Read: channel disabled + Disable channel 0 Enabled - Read: channel enabled - 1 - - - - write - - Set - Write: Enable channel + Enable channel 1 CH7 - Channel 7 enable set register. Writing '0' has no effect + Enable or disable channel 7 7 7 - read Disabled - Read: channel disabled + Disable channel 0 Enabled - Read: channel enabled - 1 - - - - write - - Set - Write: Enable channel + Enable channel 1 CH8 - Channel 8 enable set register. Writing '0' has no effect + Enable or disable channel 8 8 8 - read Disabled - Read: channel disabled + Disable channel 0 Enabled - Read: channel enabled - 1 - - - - write - - Set - Write: Enable channel + Enable channel 1 CH9 - Channel 9 enable set register. Writing '0' has no effect + Enable or disable channel 9 9 9 - read Disabled - Read: channel disabled + Disable channel 0 Enabled - Read: channel enabled - 1 - - - - write - - Set - Write: Enable channel + Enable channel 1 - CH10 - Channel 10 enable set register. Writing '0' has no effect - 10 - 10 + CH20 + Enable or disable channel 20 + 20 + 20 - read Disabled - Read: channel disabled + Disable channel 0 Enabled - Read: channel enabled - 1 - - - - write - - Set - Write: Enable channel + Enable channel 1 - CH11 - Channel 11 enable set register. Writing '0' has no effect - 11 - 11 + CH21 + Enable or disable channel 21 + 21 + 21 - read Disabled - Read: channel disabled + Disable channel 0 Enabled - Read: channel enabled - 1 - - - - write - - Set - Write: Enable channel + Enable channel 1 - CH12 - Channel 12 enable set register. Writing '0' has no effect - 12 - 12 + CH22 + Enable or disable channel 22 + 22 + 22 - read Disabled - Read: channel disabled + Disable channel 0 Enabled - Read: channel enabled - 1 - - - - write - - Set - Write: Enable channel + Enable channel 1 - CH13 - Channel 13 enable set register. Writing '0' has no effect - 13 - 13 + CH23 + Enable or disable channel 23 + 23 + 23 - read Disabled - Read: channel disabled + Disable channel 0 Enabled - Read: channel enabled - 1 - - - - write - - Set - Write: Enable channel + Enable channel 1 - CH14 - Channel 14 enable set register. Writing '0' has no effect - 14 - 14 + CH24 + Enable or disable channel 24 + 24 + 24 - read Disabled - Read: channel disabled + Disable channel 0 Enabled - Read: channel enabled + Enable channel 1 + + + CH25 + Enable or disable channel 25 + 25 + 25 - write - Set - Write: Enable channel + Disabled + Disable channel + 0 + + + Enabled + Enable channel 1 - CH15 - Channel 15 enable set register. Writing '0' has no effect - 15 - 15 + CH26 + Enable or disable channel 26 + 26 + 26 - read Disabled - Read: channel disabled + Disable channel 0 Enabled - Read: channel enabled - 1 - - - - write - - Set - Write: Enable channel + Enable channel 1 - CH16 - Channel 16 enable set register. Writing '0' has no effect - 16 - 16 + CH27 + Enable or disable channel 27 + 27 + 27 - read Disabled - Read: channel disabled + Disable channel 0 Enabled - Read: channel enabled - 1 - - - - write - - Set - Write: Enable channel + Enable channel 1 - CH17 - Channel 17 enable set register. Writing '0' has no effect - 17 - 17 + CH28 + Enable or disable channel 28 + 28 + 28 - read Disabled - Read: channel disabled + Disable channel 0 Enabled - Read: channel enabled - 1 - - - - write - - Set - Write: Enable channel + Enable channel 1 - CH18 - Channel 18 enable set register. Writing '0' has no effect - 18 - 18 + CH29 + Enable or disable channel 29 + 29 + 29 - read Disabled - Read: channel disabled + Disable channel 0 Enabled - Read: channel enabled - 1 - - - - write - - Set - Write: Enable channel + Enable channel 1 - CH19 - Channel 19 enable set register. Writing '0' has no effect - 19 - 19 + CH30 + Enable or disable channel 30 + 30 + 30 - read Disabled - Read: channel disabled + Disable channel 0 Enabled - Read: channel enabled + Enable channel 1 + + + CH31 + Enable or disable channel 31 + 31 + 31 - write - Set - Write: Enable channel + Disabled + Disable channel + 0 + + + Enabled + Enable channel 1 + + + + CHENSET + Channel enable set register + 0x504 + read-write + oneToSet + - CH20 - Channel 20 enable set register. Writing '0' has no effect - 20 - 20 + CH0 + Channel 0 enable set register. Writing '0' has no effect. + 0 + 0 read @@ -30940,10 +31217,10 @@ POSSIBILITY OF SUCH DAMAGE.\n - CH21 - Channel 21 enable set register. Writing '0' has no effect - 21 - 21 + CH1 + Channel 1 enable set register. Writing '0' has no effect. + 1 + 1 read @@ -30967,10 +31244,10 @@ POSSIBILITY OF SUCH DAMAGE.\n - CH22 - Channel 22 enable set register. Writing '0' has no effect - 22 - 22 + CH2 + Channel 2 enable set register. Writing '0' has no effect. + 2 + 2 read @@ -30994,10 +31271,10 @@ POSSIBILITY OF SUCH DAMAGE.\n - CH23 - Channel 23 enable set register. Writing '0' has no effect - 23 - 23 + CH3 + Channel 3 enable set register. Writing '0' has no effect. + 3 + 3 read @@ -31021,10 +31298,10 @@ POSSIBILITY OF SUCH DAMAGE.\n - CH24 - Channel 24 enable set register. Writing '0' has no effect - 24 - 24 + CH4 + Channel 4 enable set register. Writing '0' has no effect. + 4 + 4 read @@ -31048,10 +31325,10 @@ POSSIBILITY OF SUCH DAMAGE.\n - CH25 - Channel 25 enable set register. Writing '0' has no effect - 25 - 25 + CH5 + Channel 5 enable set register. Writing '0' has no effect. + 5 + 5 read @@ -31075,10 +31352,10 @@ POSSIBILITY OF SUCH DAMAGE.\n - CH26 - Channel 26 enable set register. Writing '0' has no effect - 26 - 26 + CH6 + Channel 6 enable set register. Writing '0' has no effect. + 6 + 6 read @@ -31102,10 +31379,10 @@ POSSIBILITY OF SUCH DAMAGE.\n - CH27 - Channel 27 enable set register. Writing '0' has no effect - 27 - 27 + CH7 + Channel 7 enable set register. Writing '0' has no effect. + 7 + 7 read @@ -31129,10 +31406,10 @@ POSSIBILITY OF SUCH DAMAGE.\n - CH28 - Channel 28 enable set register. Writing '0' has no effect - 28 - 28 + CH8 + Channel 8 enable set register. Writing '0' has no effect. + 8 + 8 read @@ -31156,10 +31433,10 @@ POSSIBILITY OF SUCH DAMAGE.\n - CH29 - Channel 29 enable set register. Writing '0' has no effect - 29 - 29 + CH9 + Channel 9 enable set register. Writing '0' has no effect. + 9 + 9 read @@ -31183,10 +31460,10 @@ POSSIBILITY OF SUCH DAMAGE.\n - CH30 - Channel 30 enable set register. Writing '0' has no effect - 30 - 30 + CH20 + Channel 20 enable set register. Writing '0' has no effect. + 20 + 20 read @@ -31210,10 +31487,10 @@ POSSIBILITY OF SUCH DAMAGE.\n - CH31 - Channel 31 enable set register. Writing '0' has no effect - 31 - 31 + CH21 + Channel 21 enable set register. Writing '0' has no effect. + 21 + 21 read @@ -31236,20 +31513,11 @@ POSSIBILITY OF SUCH DAMAGE.\n - - - - CHENCLR - Channel enable clear register - 0x508 - read-write - oneToClear - - CH0 - Channel 0 enable clear register. Writing '0' has no effect - 0 - 0 + CH22 + Channel 22 enable set register. Writing '0' has no effect. + 22 + 22 read @@ -31266,17 +31534,17 @@ POSSIBILITY OF SUCH DAMAGE.\n write - Clear - Write: disable channel + Set + Write: Enable channel 1 - CH1 - Channel 1 enable clear register. Writing '0' has no effect - 1 - 1 + CH23 + Channel 23 enable set register. Writing '0' has no effect. + 23 + 23 read @@ -31293,17 +31561,17 @@ POSSIBILITY OF SUCH DAMAGE.\n write - Clear - Write: disable channel + Set + Write: Enable channel 1 - CH2 - Channel 2 enable clear register. Writing '0' has no effect - 2 - 2 + CH24 + Channel 24 enable set register. Writing '0' has no effect. + 24 + 24 read @@ -31320,17 +31588,17 @@ POSSIBILITY OF SUCH DAMAGE.\n write - Clear - Write: disable channel + Set + Write: Enable channel 1 - CH3 - Channel 3 enable clear register. Writing '0' has no effect - 3 - 3 + CH25 + Channel 25 enable set register. Writing '0' has no effect. + 25 + 25 read @@ -31347,17 +31615,17 @@ POSSIBILITY OF SUCH DAMAGE.\n write - Clear - Write: disable channel + Set + Write: Enable channel 1 - CH4 - Channel 4 enable clear register. Writing '0' has no effect - 4 - 4 + CH26 + Channel 26 enable set register. Writing '0' has no effect. + 26 + 26 read @@ -31374,17 +31642,17 @@ POSSIBILITY OF SUCH DAMAGE.\n write - Clear - Write: disable channel + Set + Write: Enable channel 1 - CH5 - Channel 5 enable clear register. Writing '0' has no effect - 5 - 5 + CH27 + Channel 27 enable set register. Writing '0' has no effect. + 27 + 27 read @@ -31401,17 +31669,17 @@ POSSIBILITY OF SUCH DAMAGE.\n write - Clear - Write: disable channel + Set + Write: Enable channel 1 - CH6 - Channel 6 enable clear register. Writing '0' has no effect - 6 - 6 + CH28 + Channel 28 enable set register. Writing '0' has no effect. + 28 + 28 read @@ -31428,17 +31696,17 @@ POSSIBILITY OF SUCH DAMAGE.\n write - Clear - Write: disable channel + Set + Write: Enable channel 1 - CH7 - Channel 7 enable clear register. Writing '0' has no effect - 7 - 7 + CH29 + Channel 29 enable set register. Writing '0' has no effect. + 29 + 29 read @@ -31455,17 +31723,17 @@ POSSIBILITY OF SUCH DAMAGE.\n write - Clear - Write: disable channel + Set + Write: Enable channel 1 - CH8 - Channel 8 enable clear register. Writing '0' has no effect - 8 - 8 + CH30 + Channel 30 enable set register. Writing '0' has no effect. + 30 + 30 read @@ -31482,17 +31750,17 @@ POSSIBILITY OF SUCH DAMAGE.\n write - Clear - Write: disable channel + Set + Write: Enable channel 1 - CH9 - Channel 9 enable clear register. Writing '0' has no effect - 9 - 9 + CH31 + Channel 31 enable set register. Writing '0' has no effect. + 31 + 31 read @@ -31509,17 +31777,26 @@ POSSIBILITY OF SUCH DAMAGE.\n write - Clear - Write: disable channel + Set + Write: Enable channel 1 + + + + CHENCLR + Channel enable clear register + 0x508 + read-write + oneToClear + - CH10 - Channel 10 enable clear register. Writing '0' has no effect - 10 - 10 + CH0 + Channel 0 enable clear register. Writing '0' has no effect. + 0 + 0 read @@ -31543,10 +31820,10 @@ POSSIBILITY OF SUCH DAMAGE.\n - CH11 - Channel 11 enable clear register. Writing '0' has no effect - 11 - 11 + CH1 + Channel 1 enable clear register. Writing '0' has no effect. + 1 + 1 read @@ -31570,10 +31847,10 @@ POSSIBILITY OF SUCH DAMAGE.\n - CH12 - Channel 12 enable clear register. Writing '0' has no effect - 12 - 12 + CH2 + Channel 2 enable clear register. Writing '0' has no effect. + 2 + 2 read @@ -31597,10 +31874,10 @@ POSSIBILITY OF SUCH DAMAGE.\n - CH13 - Channel 13 enable clear register. Writing '0' has no effect - 13 - 13 + CH3 + Channel 3 enable clear register. Writing '0' has no effect. + 3 + 3 read @@ -31624,10 +31901,10 @@ POSSIBILITY OF SUCH DAMAGE.\n - CH14 - Channel 14 enable clear register. Writing '0' has no effect - 14 - 14 + CH4 + Channel 4 enable clear register. Writing '0' has no effect. + 4 + 4 read @@ -31651,10 +31928,10 @@ POSSIBILITY OF SUCH DAMAGE.\n - CH15 - Channel 15 enable clear register. Writing '0' has no effect - 15 - 15 + CH5 + Channel 5 enable clear register. Writing '0' has no effect. + 5 + 5 read @@ -31678,10 +31955,10 @@ POSSIBILITY OF SUCH DAMAGE.\n - CH16 - Channel 16 enable clear register. Writing '0' has no effect - 16 - 16 + CH6 + Channel 6 enable clear register. Writing '0' has no effect. + 6 + 6 read @@ -31705,10 +31982,10 @@ POSSIBILITY OF SUCH DAMAGE.\n - CH17 - Channel 17 enable clear register. Writing '0' has no effect - 17 - 17 + CH7 + Channel 7 enable clear register. Writing '0' has no effect. + 7 + 7 read @@ -31732,10 +32009,10 @@ POSSIBILITY OF SUCH DAMAGE.\n - CH18 - Channel 18 enable clear register. Writing '0' has no effect - 18 - 18 + CH8 + Channel 8 enable clear register. Writing '0' has no effect. + 8 + 8 read @@ -31759,10 +32036,10 @@ POSSIBILITY OF SUCH DAMAGE.\n - CH19 - Channel 19 enable clear register. Writing '0' has no effect - 19 - 19 + CH9 + Channel 9 enable clear register. Writing '0' has no effect. + 9 + 9 read @@ -31787,7 +32064,7 @@ POSSIBILITY OF SUCH DAMAGE.\n CH20 - Channel 20 enable clear register. Writing '0' has no effect + Channel 20 enable clear register. Writing '0' has no effect. 20 20 @@ -31814,7 +32091,7 @@ POSSIBILITY OF SUCH DAMAGE.\n CH21 - Channel 21 enable clear register. Writing '0' has no effect + Channel 21 enable clear register. Writing '0' has no effect. 21 21 @@ -31841,7 +32118,7 @@ POSSIBILITY OF SUCH DAMAGE.\n CH22 - Channel 22 enable clear register. Writing '0' has no effect + Channel 22 enable clear register. Writing '0' has no effect. 22 22 @@ -31868,7 +32145,7 @@ POSSIBILITY OF SUCH DAMAGE.\n CH23 - Channel 23 enable clear register. Writing '0' has no effect + Channel 23 enable clear register. Writing '0' has no effect. 23 23 @@ -31895,7 +32172,7 @@ POSSIBILITY OF SUCH DAMAGE.\n CH24 - Channel 24 enable clear register. Writing '0' has no effect + Channel 24 enable clear register. Writing '0' has no effect. 24 24 @@ -31922,7 +32199,7 @@ POSSIBILITY OF SUCH DAMAGE.\n CH25 - Channel 25 enable clear register. Writing '0' has no effect + Channel 25 enable clear register. Writing '0' has no effect. 25 25 @@ -31949,7 +32226,7 @@ POSSIBILITY OF SUCH DAMAGE.\n CH26 - Channel 26 enable clear register. Writing '0' has no effect + Channel 26 enable clear register. Writing '0' has no effect. 26 26 @@ -31976,7 +32253,7 @@ POSSIBILITY OF SUCH DAMAGE.\n CH27 - Channel 27 enable clear register. Writing '0' has no effect + Channel 27 enable clear register. Writing '0' has no effect. 27 27 @@ -32003,7 +32280,7 @@ POSSIBILITY OF SUCH DAMAGE.\n CH28 - Channel 28 enable clear register. Writing '0' has no effect + Channel 28 enable clear register. Writing '0' has no effect. 28 28 @@ -32030,7 +32307,7 @@ POSSIBILITY OF SUCH DAMAGE.\n CH29 - Channel 29 enable clear register. Writing '0' has no effect + Channel 29 enable clear register. Writing '0' has no effect. 29 29 @@ -32057,7 +32334,7 @@ POSSIBILITY OF SUCH DAMAGE.\n CH30 - Channel 30 enable clear register. Writing '0' has no effect + Channel 30 enable clear register. Writing '0' has no effect. 30 30 @@ -32084,7 +32361,7 @@ POSSIBILITY OF SUCH DAMAGE.\n CH31 - Channel 31 enable clear register. Writing '0' has no effect + Channel 31 enable clear register. Writing '0' has no effect. 31 31 @@ -32112,7 +32389,7 @@ POSSIBILITY OF SUCH DAMAGE.\n - 20 + 10 0x008 CH[%s] PPI Channel @@ -32121,7 +32398,7 @@ POSSIBILITY OF SUCH DAMAGE.\n 0x510 EEP - Description cluster: Channel n event end-point + Description cluster: Channel n event endpoint 0x000 read-write @@ -32135,7 +32412,7 @@ POSSIBILITY OF SUCH DAMAGE.\n TEP - Description cluster: Channel n task end-point + Description cluster: Channel n task endpoint 0x004 read-write @@ -32336,186 +32613,6 @@ POSSIBILITY OF SUCH DAMAGE.\n - - CH10 - Include or exclude channel 10 - 10 - 10 - - - Excluded - Exclude - 0 - - - Included - Include - 1 - - - - - CH11 - Include or exclude channel 11 - 11 - 11 - - - Excluded - Exclude - 0 - - - Included - Include - 1 - - - - - CH12 - Include or exclude channel 12 - 12 - 12 - - - Excluded - Exclude - 0 - - - Included - Include - 1 - - - - - CH13 - Include or exclude channel 13 - 13 - 13 - - - Excluded - Exclude - 0 - - - Included - Include - 1 - - - - - CH14 - Include or exclude channel 14 - 14 - 14 - - - Excluded - Exclude - 0 - - - Included - Include - 1 - - - - - CH15 - Include or exclude channel 15 - 15 - 15 - - - Excluded - Exclude - 0 - - - Included - Include - 1 - - - - - CH16 - Include or exclude channel 16 - 16 - 16 - - - Excluded - Exclude - 0 - - - Included - Include - 1 - - - - - CH17 - Include or exclude channel 17 - 17 - 17 - - - Excluded - Exclude - 0 - - - Included - Include - 1 - - - - - CH18 - Include or exclude channel 18 - 18 - 18 - - - Excluded - Exclude - 0 - - - Included - Include - 1 - - - - - CH19 - Include or exclude channel 19 - 19 - 19 - - - Excluded - Exclude - 0 - - - Included - Include - 1 - - - CH20 Include or exclude channel 20 @@ -32744,7 +32841,7 @@ POSSIBILITY OF SUCH DAMAGE.\n 0x910 TEP - Description cluster: Channel n task end-point + Description cluster: Channel n task endpoint 0x000 read-write diff --git a/mdk/nrf52805_bitfields.h b/mdk/nrf52805_bitfields.h index e236ebfd2b..c60555c687 100644 --- a/mdk/nrf52805_bitfields.h +++ b/mdk/nrf52805_bitfields.h @@ -485,9 +485,9 @@ POSSIBILITY OF SUCH DAMAGE. /* Description: AES CCM Mode Encryption */ /* Register: CCM_TASKS_KSGEN */ -/* Description: Start generation of key-stream. This operation will stop by itself when completed. */ +/* Description: Start generation of keystream. This operation will stop by itself when completed. */ -/* Bit 0 : Start generation of key-stream. This operation will stop by itself when completed. */ +/* Bit 0 : Start generation of keystream. This operation will stop by itself when completed. */ #define CCM_TASKS_KSGEN_TASKS_KSGEN_Pos (0UL) /*!< Position of TASKS_KSGEN field. */ #define CCM_TASKS_KSGEN_TASKS_KSGEN_Msk (0x1UL << CCM_TASKS_KSGEN_TASKS_KSGEN_Pos) /*!< Bit mask of TASKS_KSGEN field. */ #define CCM_TASKS_KSGEN_TASKS_KSGEN_Trigger (1UL) /*!< Trigger task */ @@ -517,9 +517,9 @@ POSSIBILITY OF SUCH DAMAGE. #define CCM_TASKS_RATEOVERRIDE_TASKS_RATEOVERRIDE_Trigger (1UL) /*!< Trigger task */ /* Register: CCM_EVENTS_ENDKSGEN */ -/* Description: Key-stream generation complete */ +/* Description: Keystream generation complete */ -/* Bit 0 : Key-stream generation complete */ +/* Bit 0 : Keystream generation complete */ #define CCM_EVENTS_ENDKSGEN_EVENTS_ENDKSGEN_Pos (0UL) /*!< Position of EVENTS_ENDKSGEN field. */ #define CCM_EVENTS_ENDKSGEN_EVENTS_ENDKSGEN_Msk (0x1UL << CCM_EVENTS_ENDKSGEN_EVENTS_ENDKSGEN_Pos) /*!< Bit mask of EVENTS_ENDKSGEN field. */ #define CCM_EVENTS_ENDKSGEN_EVENTS_ENDKSGEN_NotGenerated (0UL) /*!< Event not generated */ @@ -624,8 +624,8 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 24 : Packet length configuration */ #define CCM_MODE_LENGTH_Pos (24UL) /*!< Position of LENGTH field. */ #define CCM_MODE_LENGTH_Msk (0x1UL << CCM_MODE_LENGTH_Pos) /*!< Bit mask of LENGTH field. */ -#define CCM_MODE_LENGTH_Default (0UL) /*!< Default length. Effective length of LENGTH field in encrypted/decrypted packet is 5 bits. A key-stream for packet payloads up to 27 bytes will be generated. */ -#define CCM_MODE_LENGTH_Extended (1UL) /*!< Extended length. Effective length of LENGTH field in encrypted/decrypted packet is 8 bits. A key-stream for packet payloads up to MAXPACKETSIZE bytes will be generated. */ +#define CCM_MODE_LENGTH_Default (0UL) /*!< Default length. Effective length of LENGTH field in encrypted/decrypted packet is 5 bits. A keystream for packet payloads up to 27 bytes will be generated. */ +#define CCM_MODE_LENGTH_Extended (1UL) /*!< Extended length. Effective length of LENGTH field in encrypted/decrypted packet is 8 bits. A keystream for packet payloads up to MAXPACKETSIZE bytes will be generated. */ /* Bits 17..16 : Radio data rate that the CCM shall run synchronous with */ #define CCM_MODE_DATARATE_Pos (16UL) /*!< Position of DATARATE field. */ @@ -665,15 +665,15 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: CCM_SCRATCHPTR */ /* Description: Pointer to data area used for temporary storage */ -/* Bits 31..0 : Pointer to a scratch data area used for temporary storage during key-stream generation, +/* Bits 31..0 : Pointer to a scratch data area used for temporary storage during keystream generation, MIC generation and encryption/decryption. */ #define CCM_SCRATCHPTR_SCRATCHPTR_Pos (0UL) /*!< Position of SCRATCHPTR field. */ #define CCM_SCRATCHPTR_SCRATCHPTR_Msk (0xFFFFFFFFUL << CCM_SCRATCHPTR_SCRATCHPTR_Pos) /*!< Bit mask of SCRATCHPTR field. */ /* Register: CCM_MAXPACKETSIZE */ -/* Description: Length of key-stream generated when MODE.LENGTH = Extended. */ +/* Description: Length of keystream generated when MODE.LENGTH = Extended. */ -/* Bits 7..0 : Length of key-stream generated when MODE.LENGTH = Extended. This value must be greater or equal to the subsequent packet payload to be encrypted/decrypted. */ +/* Bits 7..0 : Length of keystream generated when MODE.LENGTH = Extended. This value must be greater or equal to the subsequent packet payload to be encrypted/decrypted. */ #define CCM_MAXPACKETSIZE_MAXPACKETSIZE_Pos (0UL) /*!< Position of MAXPACKETSIZE field. */ #define CCM_MAXPACKETSIZE_MAXPACKETSIZE_Msk (0xFFUL << CCM_MAXPACKETSIZE_MAXPACKETSIZE_Pos) /*!< Bit mask of MAXPACKETSIZE field. */ @@ -1015,7 +1015,7 @@ POSSIBILITY OF SUCH DAMAGE. /* Peripheral: EGU */ -/* Description: Event Generator Unit 0 */ +/* Description: Event generator unit 0 */ /* Register: EGU_TASKS_TRIGGER */ /* Description: Description collection: Trigger n for triggering the corresponding TRIGGERED[n] event */ @@ -1771,7 +1771,7 @@ POSSIBILITY OF SUCH DAMAGE. #define GPIOTE_INTENCLR_IN0_Clear (1UL) /*!< Disable */ /* Register: GPIOTE_CONFIG */ -/* Description: Description collection: Configuration for OUT[n], SET[n] and CLR[n] tasks and IN[n] event */ +/* Description: Description collection: Configuration for OUT[n], SET[n], and CLR[n] tasks and IN[n] event */ /* Bit 20 : When in task mode: Initial value of the output when the GPIOTE channel is configured. When in event mode: No effect. */ #define GPIOTE_CONFIG_OUTINIT_Pos (20UL) /*!< Position of OUTINIT field. */ @@ -1787,7 +1787,7 @@ POSSIBILITY OF SUCH DAMAGE. #define GPIOTE_CONFIG_POLARITY_HiToLo (2UL) /*!< Task mode: Clear pin from OUT[n] task. Event mode: Generate IN[n] event when falling edge on pin. */ #define GPIOTE_CONFIG_POLARITY_Toggle (3UL) /*!< Task mode: Toggle pin from OUT[n]. Event mode: Generate IN[n] when any change on pin. */ -/* Bits 12..8 : GPIO number associated with SET[n], CLR[n] and OUT[n] tasks and IN[n] event */ +/* Bits 12..8 : GPIO number associated with SET[n], CLR[n], and OUT[n] tasks and IN[n] event */ #define GPIOTE_CONFIG_PSEL_Pos (8UL) /*!< Position of PSEL field. */ #define GPIOTE_CONFIG_PSEL_Msk (0x1FUL << GPIOTE_CONFIG_PSEL_Pos) /*!< Bit mask of PSEL field. */ @@ -1800,7 +1800,7 @@ POSSIBILITY OF SUCH DAMAGE. /* Peripheral: NVMC */ -/* Description: Non-volatile memory controller */ +/* Description: Non Volatile Memory Controller */ /* Register: NVMC_READY */ /* Description: Ready flag */ @@ -1808,13 +1808,13 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 0 : NVMC is ready or busy */ #define NVMC_READY_READY_Pos (0UL) /*!< Position of READY field. */ #define NVMC_READY_READY_Msk (0x1UL << NVMC_READY_READY_Pos) /*!< Bit mask of READY field. */ -#define NVMC_READY_READY_Busy (0UL) /*!< NVMC is busy (ongoing write or erase operation) */ +#define NVMC_READY_READY_Busy (0UL) /*!< NVMC is busy (on-going write or erase operation) */ #define NVMC_READY_READY_Ready (1UL) /*!< NVMC is ready */ /* Register: NVMC_CONFIG */ /* Description: Configuration register */ -/* Bits 1..0 : Program memory access mode. It is strongly recommended to activate erase and write modes only when they are actively used. */ +/* Bits 1..0 : Program memory access mode. It is strongly recommended to only activate erase and write modes when they are actively used. */ #define NVMC_CONFIG_WEN_Pos (0UL) /*!< Position of WEN field. */ #define NVMC_CONFIG_WEN_Msk (0x3UL << NVMC_CONFIG_WEN_Pos) /*!< Bit mask of WEN field. */ #define NVMC_CONFIG_WEN_Ren (0UL) /*!< Read only access */ @@ -1824,37 +1824,37 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: NVMC_ERASEPAGE */ /* Description: Register for erasing a page in code area */ -/* Bits 31..0 : Register for starting erase of a page in code area. */ +/* Bits 31..0 : Register for starting erase of a page in code area */ #define NVMC_ERASEPAGE_ERASEPAGE_Pos (0UL) /*!< Position of ERASEPAGE field. */ #define NVMC_ERASEPAGE_ERASEPAGE_Msk (0xFFFFFFFFUL << NVMC_ERASEPAGE_ERASEPAGE_Pos) /*!< Bit mask of ERASEPAGE field. */ /* Register: NVMC_ERASEPCR1 */ -/* Description: Deprecated register - Register for erasing a page in code area. Equivalent to ERASEPAGE. */ +/* Description: Deprecated register - Register for erasing a page in code area, equivalent to ERASEPAGE */ -/* Bits 31..0 : Register for erasing a page in code area. Equivalent to ERASEPAGE. */ +/* Bits 31..0 : Register for erasing a page in code area, equivalent to ERASEPAGE */ #define NVMC_ERASEPCR1_ERASEPCR1_Pos (0UL) /*!< Position of ERASEPCR1 field. */ #define NVMC_ERASEPCR1_ERASEPCR1_Msk (0xFFFFFFFFUL << NVMC_ERASEPCR1_ERASEPCR1_Pos) /*!< Bit mask of ERASEPCR1 field. */ /* Register: NVMC_ERASEALL */ /* Description: Register for erasing all non-volatile user memory */ -/* Bit 0 : Erase all non-volatile memory including UICR registers. Note that the erase must be enabled using CONFIG.WEN before the non-volatile memory can be erased. */ +/* Bit 0 : Erase all non-volatile memory including UICR registers. The erase must be enabled using CONFIG.WEN before the non-volatile memory can be erased. */ #define NVMC_ERASEALL_ERASEALL_Pos (0UL) /*!< Position of ERASEALL field. */ #define NVMC_ERASEALL_ERASEALL_Msk (0x1UL << NVMC_ERASEALL_ERASEALL_Pos) /*!< Bit mask of ERASEALL field. */ #define NVMC_ERASEALL_ERASEALL_NoOperation (0UL) /*!< No operation */ -#define NVMC_ERASEALL_ERASEALL_Erase (1UL) /*!< Start erase of chip */ +#define NVMC_ERASEALL_ERASEALL_Erase (1UL) /*!< Start chip erase */ /* Register: NVMC_ERASEPCR0 */ -/* Description: Deprecated register - Register for erasing a page in code area. Equivalent to ERASEPAGE. */ +/* Description: Deprecated register - Register for erasing a page in code area, equivalent to ERASEPAGE */ -/* Bits 31..0 : Register for starting erase of a page in code area. Equivalent to ERASEPAGE. */ +/* Bits 31..0 : Register for starting erase of a page in code area, equivalent to ERASEPAGE */ #define NVMC_ERASEPCR0_ERASEPCR0_Pos (0UL) /*!< Position of ERASEPCR0 field. */ #define NVMC_ERASEPCR0_ERASEPCR0_Msk (0xFFFFFFFFUL << NVMC_ERASEPCR0_ERASEPCR0_Pos) /*!< Bit mask of ERASEPCR0 field. */ /* Register: NVMC_ERASEUICR */ /* Description: Register for erasing user information configuration registers */ -/* Bit 0 : Register starting erase of all user information configuration registers. Note that the erase must be enabled using CONFIG.WEN before the UICR can be erased. */ +/* Bit 0 : Register starting erase of all user information configuration registers. The erase must be enabled using CONFIG.WEN before the UICR can be erased. */ #define NVMC_ERASEUICR_ERASEUICR_Pos (0UL) /*!< Position of ERASEUICR field. */ #define NVMC_ERASEUICR_ERASEUICR_Msk (0x1UL << NVMC_ERASEUICR_ERASEUICR_Pos) /*!< Bit mask of ERASEUICR field. */ #define NVMC_ERASEUICR_ERASEUICR_NoOperation (0UL) /*!< No operation */ @@ -2081,224 +2081,224 @@ POSSIBILITY OF SUCH DAMAGE. #define GPIO_OUTSET_PIN31_Msk (0x1UL << GPIO_OUTSET_PIN31_Pos) /*!< Bit mask of PIN31 field. */ #define GPIO_OUTSET_PIN31_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTSET_PIN31_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTSET_PIN31_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ +#define GPIO_OUTSET_PIN31_Set (1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */ /* Bit 30 : Pin 30 */ #define GPIO_OUTSET_PIN30_Pos (30UL) /*!< Position of PIN30 field. */ #define GPIO_OUTSET_PIN30_Msk (0x1UL << GPIO_OUTSET_PIN30_Pos) /*!< Bit mask of PIN30 field. */ #define GPIO_OUTSET_PIN30_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTSET_PIN30_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTSET_PIN30_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ +#define GPIO_OUTSET_PIN30_Set (1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */ /* Bit 29 : Pin 29 */ #define GPIO_OUTSET_PIN29_Pos (29UL) /*!< Position of PIN29 field. */ #define GPIO_OUTSET_PIN29_Msk (0x1UL << GPIO_OUTSET_PIN29_Pos) /*!< Bit mask of PIN29 field. */ #define GPIO_OUTSET_PIN29_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTSET_PIN29_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTSET_PIN29_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ +#define GPIO_OUTSET_PIN29_Set (1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */ /* Bit 28 : Pin 28 */ #define GPIO_OUTSET_PIN28_Pos (28UL) /*!< Position of PIN28 field. */ #define GPIO_OUTSET_PIN28_Msk (0x1UL << GPIO_OUTSET_PIN28_Pos) /*!< Bit mask of PIN28 field. */ #define GPIO_OUTSET_PIN28_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTSET_PIN28_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTSET_PIN28_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ +#define GPIO_OUTSET_PIN28_Set (1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */ /* Bit 27 : Pin 27 */ #define GPIO_OUTSET_PIN27_Pos (27UL) /*!< Position of PIN27 field. */ #define GPIO_OUTSET_PIN27_Msk (0x1UL << GPIO_OUTSET_PIN27_Pos) /*!< Bit mask of PIN27 field. */ #define GPIO_OUTSET_PIN27_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTSET_PIN27_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTSET_PIN27_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ +#define GPIO_OUTSET_PIN27_Set (1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */ /* Bit 26 : Pin 26 */ #define GPIO_OUTSET_PIN26_Pos (26UL) /*!< Position of PIN26 field. */ #define GPIO_OUTSET_PIN26_Msk (0x1UL << GPIO_OUTSET_PIN26_Pos) /*!< Bit mask of PIN26 field. */ #define GPIO_OUTSET_PIN26_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTSET_PIN26_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTSET_PIN26_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ +#define GPIO_OUTSET_PIN26_Set (1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */ /* Bit 25 : Pin 25 */ #define GPIO_OUTSET_PIN25_Pos (25UL) /*!< Position of PIN25 field. */ #define GPIO_OUTSET_PIN25_Msk (0x1UL << GPIO_OUTSET_PIN25_Pos) /*!< Bit mask of PIN25 field. */ #define GPIO_OUTSET_PIN25_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTSET_PIN25_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTSET_PIN25_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ +#define GPIO_OUTSET_PIN25_Set (1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */ /* Bit 24 : Pin 24 */ #define GPIO_OUTSET_PIN24_Pos (24UL) /*!< Position of PIN24 field. */ #define GPIO_OUTSET_PIN24_Msk (0x1UL << GPIO_OUTSET_PIN24_Pos) /*!< Bit mask of PIN24 field. */ #define GPIO_OUTSET_PIN24_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTSET_PIN24_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTSET_PIN24_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ +#define GPIO_OUTSET_PIN24_Set (1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */ /* Bit 23 : Pin 23 */ #define GPIO_OUTSET_PIN23_Pos (23UL) /*!< Position of PIN23 field. */ #define GPIO_OUTSET_PIN23_Msk (0x1UL << GPIO_OUTSET_PIN23_Pos) /*!< Bit mask of PIN23 field. */ #define GPIO_OUTSET_PIN23_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTSET_PIN23_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTSET_PIN23_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ +#define GPIO_OUTSET_PIN23_Set (1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */ /* Bit 22 : Pin 22 */ #define GPIO_OUTSET_PIN22_Pos (22UL) /*!< Position of PIN22 field. */ #define GPIO_OUTSET_PIN22_Msk (0x1UL << GPIO_OUTSET_PIN22_Pos) /*!< Bit mask of PIN22 field. */ #define GPIO_OUTSET_PIN22_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTSET_PIN22_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTSET_PIN22_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ +#define GPIO_OUTSET_PIN22_Set (1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */ /* Bit 21 : Pin 21 */ #define GPIO_OUTSET_PIN21_Pos (21UL) /*!< Position of PIN21 field. */ #define GPIO_OUTSET_PIN21_Msk (0x1UL << GPIO_OUTSET_PIN21_Pos) /*!< Bit mask of PIN21 field. */ #define GPIO_OUTSET_PIN21_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTSET_PIN21_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTSET_PIN21_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ +#define GPIO_OUTSET_PIN21_Set (1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */ /* Bit 20 : Pin 20 */ #define GPIO_OUTSET_PIN20_Pos (20UL) /*!< Position of PIN20 field. */ #define GPIO_OUTSET_PIN20_Msk (0x1UL << GPIO_OUTSET_PIN20_Pos) /*!< Bit mask of PIN20 field. */ #define GPIO_OUTSET_PIN20_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTSET_PIN20_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTSET_PIN20_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ +#define GPIO_OUTSET_PIN20_Set (1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */ /* Bit 19 : Pin 19 */ #define GPIO_OUTSET_PIN19_Pos (19UL) /*!< Position of PIN19 field. */ #define GPIO_OUTSET_PIN19_Msk (0x1UL << GPIO_OUTSET_PIN19_Pos) /*!< Bit mask of PIN19 field. */ #define GPIO_OUTSET_PIN19_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTSET_PIN19_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTSET_PIN19_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ +#define GPIO_OUTSET_PIN19_Set (1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */ /* Bit 18 : Pin 18 */ #define GPIO_OUTSET_PIN18_Pos (18UL) /*!< Position of PIN18 field. */ #define GPIO_OUTSET_PIN18_Msk (0x1UL << GPIO_OUTSET_PIN18_Pos) /*!< Bit mask of PIN18 field. */ #define GPIO_OUTSET_PIN18_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTSET_PIN18_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTSET_PIN18_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ +#define GPIO_OUTSET_PIN18_Set (1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */ /* Bit 17 : Pin 17 */ #define GPIO_OUTSET_PIN17_Pos (17UL) /*!< Position of PIN17 field. */ #define GPIO_OUTSET_PIN17_Msk (0x1UL << GPIO_OUTSET_PIN17_Pos) /*!< Bit mask of PIN17 field. */ #define GPIO_OUTSET_PIN17_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTSET_PIN17_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTSET_PIN17_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ +#define GPIO_OUTSET_PIN17_Set (1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */ /* Bit 16 : Pin 16 */ #define GPIO_OUTSET_PIN16_Pos (16UL) /*!< Position of PIN16 field. */ #define GPIO_OUTSET_PIN16_Msk (0x1UL << GPIO_OUTSET_PIN16_Pos) /*!< Bit mask of PIN16 field. */ #define GPIO_OUTSET_PIN16_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTSET_PIN16_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTSET_PIN16_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ +#define GPIO_OUTSET_PIN16_Set (1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */ /* Bit 15 : Pin 15 */ #define GPIO_OUTSET_PIN15_Pos (15UL) /*!< Position of PIN15 field. */ #define GPIO_OUTSET_PIN15_Msk (0x1UL << GPIO_OUTSET_PIN15_Pos) /*!< Bit mask of PIN15 field. */ #define GPIO_OUTSET_PIN15_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTSET_PIN15_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTSET_PIN15_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ +#define GPIO_OUTSET_PIN15_Set (1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */ /* Bit 14 : Pin 14 */ #define GPIO_OUTSET_PIN14_Pos (14UL) /*!< Position of PIN14 field. */ #define GPIO_OUTSET_PIN14_Msk (0x1UL << GPIO_OUTSET_PIN14_Pos) /*!< Bit mask of PIN14 field. */ #define GPIO_OUTSET_PIN14_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTSET_PIN14_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTSET_PIN14_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ +#define GPIO_OUTSET_PIN14_Set (1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */ /* Bit 13 : Pin 13 */ #define GPIO_OUTSET_PIN13_Pos (13UL) /*!< Position of PIN13 field. */ #define GPIO_OUTSET_PIN13_Msk (0x1UL << GPIO_OUTSET_PIN13_Pos) /*!< Bit mask of PIN13 field. */ #define GPIO_OUTSET_PIN13_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTSET_PIN13_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTSET_PIN13_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ +#define GPIO_OUTSET_PIN13_Set (1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */ /* Bit 12 : Pin 12 */ #define GPIO_OUTSET_PIN12_Pos (12UL) /*!< Position of PIN12 field. */ #define GPIO_OUTSET_PIN12_Msk (0x1UL << GPIO_OUTSET_PIN12_Pos) /*!< Bit mask of PIN12 field. */ #define GPIO_OUTSET_PIN12_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTSET_PIN12_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTSET_PIN12_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ +#define GPIO_OUTSET_PIN12_Set (1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */ /* Bit 11 : Pin 11 */ #define GPIO_OUTSET_PIN11_Pos (11UL) /*!< Position of PIN11 field. */ #define GPIO_OUTSET_PIN11_Msk (0x1UL << GPIO_OUTSET_PIN11_Pos) /*!< Bit mask of PIN11 field. */ #define GPIO_OUTSET_PIN11_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTSET_PIN11_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTSET_PIN11_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ +#define GPIO_OUTSET_PIN11_Set (1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */ /* Bit 10 : Pin 10 */ #define GPIO_OUTSET_PIN10_Pos (10UL) /*!< Position of PIN10 field. */ #define GPIO_OUTSET_PIN10_Msk (0x1UL << GPIO_OUTSET_PIN10_Pos) /*!< Bit mask of PIN10 field. */ #define GPIO_OUTSET_PIN10_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTSET_PIN10_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTSET_PIN10_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ +#define GPIO_OUTSET_PIN10_Set (1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */ /* Bit 9 : Pin 9 */ #define GPIO_OUTSET_PIN9_Pos (9UL) /*!< Position of PIN9 field. */ #define GPIO_OUTSET_PIN9_Msk (0x1UL << GPIO_OUTSET_PIN9_Pos) /*!< Bit mask of PIN9 field. */ #define GPIO_OUTSET_PIN9_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTSET_PIN9_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTSET_PIN9_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ +#define GPIO_OUTSET_PIN9_Set (1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */ /* Bit 8 : Pin 8 */ #define GPIO_OUTSET_PIN8_Pos (8UL) /*!< Position of PIN8 field. */ #define GPIO_OUTSET_PIN8_Msk (0x1UL << GPIO_OUTSET_PIN8_Pos) /*!< Bit mask of PIN8 field. */ #define GPIO_OUTSET_PIN8_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTSET_PIN8_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTSET_PIN8_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ +#define GPIO_OUTSET_PIN8_Set (1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */ /* Bit 7 : Pin 7 */ #define GPIO_OUTSET_PIN7_Pos (7UL) /*!< Position of PIN7 field. */ #define GPIO_OUTSET_PIN7_Msk (0x1UL << GPIO_OUTSET_PIN7_Pos) /*!< Bit mask of PIN7 field. */ #define GPIO_OUTSET_PIN7_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTSET_PIN7_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTSET_PIN7_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ +#define GPIO_OUTSET_PIN7_Set (1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */ /* Bit 6 : Pin 6 */ #define GPIO_OUTSET_PIN6_Pos (6UL) /*!< Position of PIN6 field. */ #define GPIO_OUTSET_PIN6_Msk (0x1UL << GPIO_OUTSET_PIN6_Pos) /*!< Bit mask of PIN6 field. */ #define GPIO_OUTSET_PIN6_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTSET_PIN6_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTSET_PIN6_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ +#define GPIO_OUTSET_PIN6_Set (1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */ /* Bit 5 : Pin 5 */ #define GPIO_OUTSET_PIN5_Pos (5UL) /*!< Position of PIN5 field. */ #define GPIO_OUTSET_PIN5_Msk (0x1UL << GPIO_OUTSET_PIN5_Pos) /*!< Bit mask of PIN5 field. */ #define GPIO_OUTSET_PIN5_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTSET_PIN5_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTSET_PIN5_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ +#define GPIO_OUTSET_PIN5_Set (1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */ /* Bit 4 : Pin 4 */ #define GPIO_OUTSET_PIN4_Pos (4UL) /*!< Position of PIN4 field. */ #define GPIO_OUTSET_PIN4_Msk (0x1UL << GPIO_OUTSET_PIN4_Pos) /*!< Bit mask of PIN4 field. */ #define GPIO_OUTSET_PIN4_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTSET_PIN4_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTSET_PIN4_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ +#define GPIO_OUTSET_PIN4_Set (1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */ /* Bit 3 : Pin 3 */ #define GPIO_OUTSET_PIN3_Pos (3UL) /*!< Position of PIN3 field. */ #define GPIO_OUTSET_PIN3_Msk (0x1UL << GPIO_OUTSET_PIN3_Pos) /*!< Bit mask of PIN3 field. */ #define GPIO_OUTSET_PIN3_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTSET_PIN3_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTSET_PIN3_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ +#define GPIO_OUTSET_PIN3_Set (1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */ /* Bit 2 : Pin 2 */ #define GPIO_OUTSET_PIN2_Pos (2UL) /*!< Position of PIN2 field. */ #define GPIO_OUTSET_PIN2_Msk (0x1UL << GPIO_OUTSET_PIN2_Pos) /*!< Bit mask of PIN2 field. */ #define GPIO_OUTSET_PIN2_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTSET_PIN2_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTSET_PIN2_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ +#define GPIO_OUTSET_PIN2_Set (1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */ /* Bit 1 : Pin 1 */ #define GPIO_OUTSET_PIN1_Pos (1UL) /*!< Position of PIN1 field. */ #define GPIO_OUTSET_PIN1_Msk (0x1UL << GPIO_OUTSET_PIN1_Pos) /*!< Bit mask of PIN1 field. */ #define GPIO_OUTSET_PIN1_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTSET_PIN1_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTSET_PIN1_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ +#define GPIO_OUTSET_PIN1_Set (1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */ /* Bit 0 : Pin 0 */ #define GPIO_OUTSET_PIN0_Pos (0UL) /*!< Position of PIN0 field. */ #define GPIO_OUTSET_PIN0_Msk (0x1UL << GPIO_OUTSET_PIN0_Pos) /*!< Bit mask of PIN0 field. */ #define GPIO_OUTSET_PIN0_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTSET_PIN0_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTSET_PIN0_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ +#define GPIO_OUTSET_PIN0_Set (1UL) /*!< Write: a '1' sets the pin high; a '0' has no effect */ /* Register: GPIO_OUTCLR */ /* Description: Clear individual bits in GPIO port */ @@ -2308,224 +2308,224 @@ POSSIBILITY OF SUCH DAMAGE. #define GPIO_OUTCLR_PIN31_Msk (0x1UL << GPIO_OUTCLR_PIN31_Pos) /*!< Bit mask of PIN31 field. */ #define GPIO_OUTCLR_PIN31_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTCLR_PIN31_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTCLR_PIN31_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ +#define GPIO_OUTCLR_PIN31_Clear (1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */ /* Bit 30 : Pin 30 */ #define GPIO_OUTCLR_PIN30_Pos (30UL) /*!< Position of PIN30 field. */ #define GPIO_OUTCLR_PIN30_Msk (0x1UL << GPIO_OUTCLR_PIN30_Pos) /*!< Bit mask of PIN30 field. */ #define GPIO_OUTCLR_PIN30_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTCLR_PIN30_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTCLR_PIN30_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ +#define GPIO_OUTCLR_PIN30_Clear (1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */ /* Bit 29 : Pin 29 */ #define GPIO_OUTCLR_PIN29_Pos (29UL) /*!< Position of PIN29 field. */ #define GPIO_OUTCLR_PIN29_Msk (0x1UL << GPIO_OUTCLR_PIN29_Pos) /*!< Bit mask of PIN29 field. */ #define GPIO_OUTCLR_PIN29_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTCLR_PIN29_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTCLR_PIN29_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ +#define GPIO_OUTCLR_PIN29_Clear (1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */ /* Bit 28 : Pin 28 */ #define GPIO_OUTCLR_PIN28_Pos (28UL) /*!< Position of PIN28 field. */ #define GPIO_OUTCLR_PIN28_Msk (0x1UL << GPIO_OUTCLR_PIN28_Pos) /*!< Bit mask of PIN28 field. */ #define GPIO_OUTCLR_PIN28_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTCLR_PIN28_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTCLR_PIN28_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ +#define GPIO_OUTCLR_PIN28_Clear (1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */ /* Bit 27 : Pin 27 */ #define GPIO_OUTCLR_PIN27_Pos (27UL) /*!< Position of PIN27 field. */ #define GPIO_OUTCLR_PIN27_Msk (0x1UL << GPIO_OUTCLR_PIN27_Pos) /*!< Bit mask of PIN27 field. */ #define GPIO_OUTCLR_PIN27_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTCLR_PIN27_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTCLR_PIN27_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ +#define GPIO_OUTCLR_PIN27_Clear (1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */ /* Bit 26 : Pin 26 */ #define GPIO_OUTCLR_PIN26_Pos (26UL) /*!< Position of PIN26 field. */ #define GPIO_OUTCLR_PIN26_Msk (0x1UL << GPIO_OUTCLR_PIN26_Pos) /*!< Bit mask of PIN26 field. */ #define GPIO_OUTCLR_PIN26_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTCLR_PIN26_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTCLR_PIN26_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ +#define GPIO_OUTCLR_PIN26_Clear (1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */ /* Bit 25 : Pin 25 */ #define GPIO_OUTCLR_PIN25_Pos (25UL) /*!< Position of PIN25 field. */ #define GPIO_OUTCLR_PIN25_Msk (0x1UL << GPIO_OUTCLR_PIN25_Pos) /*!< Bit mask of PIN25 field. */ #define GPIO_OUTCLR_PIN25_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTCLR_PIN25_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTCLR_PIN25_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ +#define GPIO_OUTCLR_PIN25_Clear (1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */ /* Bit 24 : Pin 24 */ #define GPIO_OUTCLR_PIN24_Pos (24UL) /*!< Position of PIN24 field. */ #define GPIO_OUTCLR_PIN24_Msk (0x1UL << GPIO_OUTCLR_PIN24_Pos) /*!< Bit mask of PIN24 field. */ #define GPIO_OUTCLR_PIN24_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTCLR_PIN24_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTCLR_PIN24_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ +#define GPIO_OUTCLR_PIN24_Clear (1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */ /* Bit 23 : Pin 23 */ #define GPIO_OUTCLR_PIN23_Pos (23UL) /*!< Position of PIN23 field. */ #define GPIO_OUTCLR_PIN23_Msk (0x1UL << GPIO_OUTCLR_PIN23_Pos) /*!< Bit mask of PIN23 field. */ #define GPIO_OUTCLR_PIN23_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTCLR_PIN23_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTCLR_PIN23_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ +#define GPIO_OUTCLR_PIN23_Clear (1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */ /* Bit 22 : Pin 22 */ #define GPIO_OUTCLR_PIN22_Pos (22UL) /*!< Position of PIN22 field. */ #define GPIO_OUTCLR_PIN22_Msk (0x1UL << GPIO_OUTCLR_PIN22_Pos) /*!< Bit mask of PIN22 field. */ #define GPIO_OUTCLR_PIN22_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTCLR_PIN22_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTCLR_PIN22_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ +#define GPIO_OUTCLR_PIN22_Clear (1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */ /* Bit 21 : Pin 21 */ #define GPIO_OUTCLR_PIN21_Pos (21UL) /*!< Position of PIN21 field. */ #define GPIO_OUTCLR_PIN21_Msk (0x1UL << GPIO_OUTCLR_PIN21_Pos) /*!< Bit mask of PIN21 field. */ #define GPIO_OUTCLR_PIN21_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTCLR_PIN21_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTCLR_PIN21_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ +#define GPIO_OUTCLR_PIN21_Clear (1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */ /* Bit 20 : Pin 20 */ #define GPIO_OUTCLR_PIN20_Pos (20UL) /*!< Position of PIN20 field. */ #define GPIO_OUTCLR_PIN20_Msk (0x1UL << GPIO_OUTCLR_PIN20_Pos) /*!< Bit mask of PIN20 field. */ #define GPIO_OUTCLR_PIN20_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTCLR_PIN20_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTCLR_PIN20_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ +#define GPIO_OUTCLR_PIN20_Clear (1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */ /* Bit 19 : Pin 19 */ #define GPIO_OUTCLR_PIN19_Pos (19UL) /*!< Position of PIN19 field. */ #define GPIO_OUTCLR_PIN19_Msk (0x1UL << GPIO_OUTCLR_PIN19_Pos) /*!< Bit mask of PIN19 field. */ #define GPIO_OUTCLR_PIN19_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTCLR_PIN19_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTCLR_PIN19_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ +#define GPIO_OUTCLR_PIN19_Clear (1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */ /* Bit 18 : Pin 18 */ #define GPIO_OUTCLR_PIN18_Pos (18UL) /*!< Position of PIN18 field. */ #define GPIO_OUTCLR_PIN18_Msk (0x1UL << GPIO_OUTCLR_PIN18_Pos) /*!< Bit mask of PIN18 field. */ #define GPIO_OUTCLR_PIN18_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTCLR_PIN18_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTCLR_PIN18_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ +#define GPIO_OUTCLR_PIN18_Clear (1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */ /* Bit 17 : Pin 17 */ #define GPIO_OUTCLR_PIN17_Pos (17UL) /*!< Position of PIN17 field. */ #define GPIO_OUTCLR_PIN17_Msk (0x1UL << GPIO_OUTCLR_PIN17_Pos) /*!< Bit mask of PIN17 field. */ #define GPIO_OUTCLR_PIN17_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTCLR_PIN17_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTCLR_PIN17_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ +#define GPIO_OUTCLR_PIN17_Clear (1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */ /* Bit 16 : Pin 16 */ #define GPIO_OUTCLR_PIN16_Pos (16UL) /*!< Position of PIN16 field. */ #define GPIO_OUTCLR_PIN16_Msk (0x1UL << GPIO_OUTCLR_PIN16_Pos) /*!< Bit mask of PIN16 field. */ #define GPIO_OUTCLR_PIN16_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTCLR_PIN16_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTCLR_PIN16_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ +#define GPIO_OUTCLR_PIN16_Clear (1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */ /* Bit 15 : Pin 15 */ #define GPIO_OUTCLR_PIN15_Pos (15UL) /*!< Position of PIN15 field. */ #define GPIO_OUTCLR_PIN15_Msk (0x1UL << GPIO_OUTCLR_PIN15_Pos) /*!< Bit mask of PIN15 field. */ #define GPIO_OUTCLR_PIN15_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTCLR_PIN15_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTCLR_PIN15_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ +#define GPIO_OUTCLR_PIN15_Clear (1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */ /* Bit 14 : Pin 14 */ #define GPIO_OUTCLR_PIN14_Pos (14UL) /*!< Position of PIN14 field. */ #define GPIO_OUTCLR_PIN14_Msk (0x1UL << GPIO_OUTCLR_PIN14_Pos) /*!< Bit mask of PIN14 field. */ #define GPIO_OUTCLR_PIN14_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTCLR_PIN14_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTCLR_PIN14_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ +#define GPIO_OUTCLR_PIN14_Clear (1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */ /* Bit 13 : Pin 13 */ #define GPIO_OUTCLR_PIN13_Pos (13UL) /*!< Position of PIN13 field. */ #define GPIO_OUTCLR_PIN13_Msk (0x1UL << GPIO_OUTCLR_PIN13_Pos) /*!< Bit mask of PIN13 field. */ #define GPIO_OUTCLR_PIN13_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTCLR_PIN13_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTCLR_PIN13_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ +#define GPIO_OUTCLR_PIN13_Clear (1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */ /* Bit 12 : Pin 12 */ #define GPIO_OUTCLR_PIN12_Pos (12UL) /*!< Position of PIN12 field. */ #define GPIO_OUTCLR_PIN12_Msk (0x1UL << GPIO_OUTCLR_PIN12_Pos) /*!< Bit mask of PIN12 field. */ #define GPIO_OUTCLR_PIN12_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTCLR_PIN12_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTCLR_PIN12_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ +#define GPIO_OUTCLR_PIN12_Clear (1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */ /* Bit 11 : Pin 11 */ #define GPIO_OUTCLR_PIN11_Pos (11UL) /*!< Position of PIN11 field. */ #define GPIO_OUTCLR_PIN11_Msk (0x1UL << GPIO_OUTCLR_PIN11_Pos) /*!< Bit mask of PIN11 field. */ #define GPIO_OUTCLR_PIN11_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTCLR_PIN11_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTCLR_PIN11_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ +#define GPIO_OUTCLR_PIN11_Clear (1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */ /* Bit 10 : Pin 10 */ #define GPIO_OUTCLR_PIN10_Pos (10UL) /*!< Position of PIN10 field. */ #define GPIO_OUTCLR_PIN10_Msk (0x1UL << GPIO_OUTCLR_PIN10_Pos) /*!< Bit mask of PIN10 field. */ #define GPIO_OUTCLR_PIN10_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTCLR_PIN10_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTCLR_PIN10_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ +#define GPIO_OUTCLR_PIN10_Clear (1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */ /* Bit 9 : Pin 9 */ #define GPIO_OUTCLR_PIN9_Pos (9UL) /*!< Position of PIN9 field. */ #define GPIO_OUTCLR_PIN9_Msk (0x1UL << GPIO_OUTCLR_PIN9_Pos) /*!< Bit mask of PIN9 field. */ #define GPIO_OUTCLR_PIN9_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTCLR_PIN9_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTCLR_PIN9_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ +#define GPIO_OUTCLR_PIN9_Clear (1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */ /* Bit 8 : Pin 8 */ #define GPIO_OUTCLR_PIN8_Pos (8UL) /*!< Position of PIN8 field. */ #define GPIO_OUTCLR_PIN8_Msk (0x1UL << GPIO_OUTCLR_PIN8_Pos) /*!< Bit mask of PIN8 field. */ #define GPIO_OUTCLR_PIN8_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTCLR_PIN8_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTCLR_PIN8_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ +#define GPIO_OUTCLR_PIN8_Clear (1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */ /* Bit 7 : Pin 7 */ #define GPIO_OUTCLR_PIN7_Pos (7UL) /*!< Position of PIN7 field. */ #define GPIO_OUTCLR_PIN7_Msk (0x1UL << GPIO_OUTCLR_PIN7_Pos) /*!< Bit mask of PIN7 field. */ #define GPIO_OUTCLR_PIN7_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTCLR_PIN7_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTCLR_PIN7_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ +#define GPIO_OUTCLR_PIN7_Clear (1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */ /* Bit 6 : Pin 6 */ #define GPIO_OUTCLR_PIN6_Pos (6UL) /*!< Position of PIN6 field. */ #define GPIO_OUTCLR_PIN6_Msk (0x1UL << GPIO_OUTCLR_PIN6_Pos) /*!< Bit mask of PIN6 field. */ #define GPIO_OUTCLR_PIN6_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTCLR_PIN6_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTCLR_PIN6_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ +#define GPIO_OUTCLR_PIN6_Clear (1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */ /* Bit 5 : Pin 5 */ #define GPIO_OUTCLR_PIN5_Pos (5UL) /*!< Position of PIN5 field. */ #define GPIO_OUTCLR_PIN5_Msk (0x1UL << GPIO_OUTCLR_PIN5_Pos) /*!< Bit mask of PIN5 field. */ #define GPIO_OUTCLR_PIN5_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTCLR_PIN5_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTCLR_PIN5_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ +#define GPIO_OUTCLR_PIN5_Clear (1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */ /* Bit 4 : Pin 4 */ #define GPIO_OUTCLR_PIN4_Pos (4UL) /*!< Position of PIN4 field. */ #define GPIO_OUTCLR_PIN4_Msk (0x1UL << GPIO_OUTCLR_PIN4_Pos) /*!< Bit mask of PIN4 field. */ #define GPIO_OUTCLR_PIN4_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTCLR_PIN4_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTCLR_PIN4_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ +#define GPIO_OUTCLR_PIN4_Clear (1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */ /* Bit 3 : Pin 3 */ #define GPIO_OUTCLR_PIN3_Pos (3UL) /*!< Position of PIN3 field. */ #define GPIO_OUTCLR_PIN3_Msk (0x1UL << GPIO_OUTCLR_PIN3_Pos) /*!< Bit mask of PIN3 field. */ #define GPIO_OUTCLR_PIN3_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTCLR_PIN3_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTCLR_PIN3_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ +#define GPIO_OUTCLR_PIN3_Clear (1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */ /* Bit 2 : Pin 2 */ #define GPIO_OUTCLR_PIN2_Pos (2UL) /*!< Position of PIN2 field. */ #define GPIO_OUTCLR_PIN2_Msk (0x1UL << GPIO_OUTCLR_PIN2_Pos) /*!< Bit mask of PIN2 field. */ #define GPIO_OUTCLR_PIN2_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTCLR_PIN2_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTCLR_PIN2_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ +#define GPIO_OUTCLR_PIN2_Clear (1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */ /* Bit 1 : Pin 1 */ #define GPIO_OUTCLR_PIN1_Pos (1UL) /*!< Position of PIN1 field. */ #define GPIO_OUTCLR_PIN1_Msk (0x1UL << GPIO_OUTCLR_PIN1_Pos) /*!< Bit mask of PIN1 field. */ #define GPIO_OUTCLR_PIN1_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTCLR_PIN1_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTCLR_PIN1_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ +#define GPIO_OUTCLR_PIN1_Clear (1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */ /* Bit 0 : Pin 0 */ #define GPIO_OUTCLR_PIN0_Pos (0UL) /*!< Position of PIN0 field. */ #define GPIO_OUTCLR_PIN0_Msk (0x1UL << GPIO_OUTCLR_PIN0_Pos) /*!< Bit mask of PIN0 field. */ #define GPIO_OUTCLR_PIN0_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTCLR_PIN0_High (1UL) /*!< Read: pin driver is high */ -#define GPIO_OUTCLR_PIN0_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ +#define GPIO_OUTCLR_PIN0_Clear (1UL) /*!< Write: a '1' sets the pin low; a '0' has no effect */ /* Register: GPIO_IN */ /* Description: Read GPIO port */ @@ -2925,224 +2925,224 @@ POSSIBILITY OF SUCH DAMAGE. #define GPIO_DIRSET_PIN31_Msk (0x1UL << GPIO_DIRSET_PIN31_Pos) /*!< Bit mask of PIN31 field. */ #define GPIO_DIRSET_PIN31_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRSET_PIN31_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRSET_PIN31_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ +#define GPIO_DIRSET_PIN31_Set (1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */ /* Bit 30 : Set as output pin 30 */ #define GPIO_DIRSET_PIN30_Pos (30UL) /*!< Position of PIN30 field. */ #define GPIO_DIRSET_PIN30_Msk (0x1UL << GPIO_DIRSET_PIN30_Pos) /*!< Bit mask of PIN30 field. */ #define GPIO_DIRSET_PIN30_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRSET_PIN30_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRSET_PIN30_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ +#define GPIO_DIRSET_PIN30_Set (1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */ /* Bit 29 : Set as output pin 29 */ #define GPIO_DIRSET_PIN29_Pos (29UL) /*!< Position of PIN29 field. */ #define GPIO_DIRSET_PIN29_Msk (0x1UL << GPIO_DIRSET_PIN29_Pos) /*!< Bit mask of PIN29 field. */ #define GPIO_DIRSET_PIN29_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRSET_PIN29_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRSET_PIN29_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ +#define GPIO_DIRSET_PIN29_Set (1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */ /* Bit 28 : Set as output pin 28 */ #define GPIO_DIRSET_PIN28_Pos (28UL) /*!< Position of PIN28 field. */ #define GPIO_DIRSET_PIN28_Msk (0x1UL << GPIO_DIRSET_PIN28_Pos) /*!< Bit mask of PIN28 field. */ #define GPIO_DIRSET_PIN28_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRSET_PIN28_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRSET_PIN28_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ +#define GPIO_DIRSET_PIN28_Set (1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */ /* Bit 27 : Set as output pin 27 */ #define GPIO_DIRSET_PIN27_Pos (27UL) /*!< Position of PIN27 field. */ #define GPIO_DIRSET_PIN27_Msk (0x1UL << GPIO_DIRSET_PIN27_Pos) /*!< Bit mask of PIN27 field. */ #define GPIO_DIRSET_PIN27_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRSET_PIN27_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRSET_PIN27_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ +#define GPIO_DIRSET_PIN27_Set (1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */ /* Bit 26 : Set as output pin 26 */ #define GPIO_DIRSET_PIN26_Pos (26UL) /*!< Position of PIN26 field. */ #define GPIO_DIRSET_PIN26_Msk (0x1UL << GPIO_DIRSET_PIN26_Pos) /*!< Bit mask of PIN26 field. */ #define GPIO_DIRSET_PIN26_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRSET_PIN26_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRSET_PIN26_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ +#define GPIO_DIRSET_PIN26_Set (1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */ /* Bit 25 : Set as output pin 25 */ #define GPIO_DIRSET_PIN25_Pos (25UL) /*!< Position of PIN25 field. */ #define GPIO_DIRSET_PIN25_Msk (0x1UL << GPIO_DIRSET_PIN25_Pos) /*!< Bit mask of PIN25 field. */ #define GPIO_DIRSET_PIN25_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRSET_PIN25_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRSET_PIN25_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ +#define GPIO_DIRSET_PIN25_Set (1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */ /* Bit 24 : Set as output pin 24 */ #define GPIO_DIRSET_PIN24_Pos (24UL) /*!< Position of PIN24 field. */ #define GPIO_DIRSET_PIN24_Msk (0x1UL << GPIO_DIRSET_PIN24_Pos) /*!< Bit mask of PIN24 field. */ #define GPIO_DIRSET_PIN24_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRSET_PIN24_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRSET_PIN24_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ +#define GPIO_DIRSET_PIN24_Set (1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */ /* Bit 23 : Set as output pin 23 */ #define GPIO_DIRSET_PIN23_Pos (23UL) /*!< Position of PIN23 field. */ #define GPIO_DIRSET_PIN23_Msk (0x1UL << GPIO_DIRSET_PIN23_Pos) /*!< Bit mask of PIN23 field. */ #define GPIO_DIRSET_PIN23_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRSET_PIN23_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRSET_PIN23_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ +#define GPIO_DIRSET_PIN23_Set (1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */ /* Bit 22 : Set as output pin 22 */ #define GPIO_DIRSET_PIN22_Pos (22UL) /*!< Position of PIN22 field. */ #define GPIO_DIRSET_PIN22_Msk (0x1UL << GPIO_DIRSET_PIN22_Pos) /*!< Bit mask of PIN22 field. */ #define GPIO_DIRSET_PIN22_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRSET_PIN22_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRSET_PIN22_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ +#define GPIO_DIRSET_PIN22_Set (1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */ /* Bit 21 : Set as output pin 21 */ #define GPIO_DIRSET_PIN21_Pos (21UL) /*!< Position of PIN21 field. */ #define GPIO_DIRSET_PIN21_Msk (0x1UL << GPIO_DIRSET_PIN21_Pos) /*!< Bit mask of PIN21 field. */ #define GPIO_DIRSET_PIN21_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRSET_PIN21_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRSET_PIN21_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ +#define GPIO_DIRSET_PIN21_Set (1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */ /* Bit 20 : Set as output pin 20 */ #define GPIO_DIRSET_PIN20_Pos (20UL) /*!< Position of PIN20 field. */ #define GPIO_DIRSET_PIN20_Msk (0x1UL << GPIO_DIRSET_PIN20_Pos) /*!< Bit mask of PIN20 field. */ #define GPIO_DIRSET_PIN20_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRSET_PIN20_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRSET_PIN20_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ +#define GPIO_DIRSET_PIN20_Set (1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */ /* Bit 19 : Set as output pin 19 */ #define GPIO_DIRSET_PIN19_Pos (19UL) /*!< Position of PIN19 field. */ #define GPIO_DIRSET_PIN19_Msk (0x1UL << GPIO_DIRSET_PIN19_Pos) /*!< Bit mask of PIN19 field. */ #define GPIO_DIRSET_PIN19_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRSET_PIN19_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRSET_PIN19_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ +#define GPIO_DIRSET_PIN19_Set (1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */ /* Bit 18 : Set as output pin 18 */ #define GPIO_DIRSET_PIN18_Pos (18UL) /*!< Position of PIN18 field. */ #define GPIO_DIRSET_PIN18_Msk (0x1UL << GPIO_DIRSET_PIN18_Pos) /*!< Bit mask of PIN18 field. */ #define GPIO_DIRSET_PIN18_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRSET_PIN18_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRSET_PIN18_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ +#define GPIO_DIRSET_PIN18_Set (1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */ /* Bit 17 : Set as output pin 17 */ #define GPIO_DIRSET_PIN17_Pos (17UL) /*!< Position of PIN17 field. */ #define GPIO_DIRSET_PIN17_Msk (0x1UL << GPIO_DIRSET_PIN17_Pos) /*!< Bit mask of PIN17 field. */ #define GPIO_DIRSET_PIN17_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRSET_PIN17_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRSET_PIN17_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ +#define GPIO_DIRSET_PIN17_Set (1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */ /* Bit 16 : Set as output pin 16 */ #define GPIO_DIRSET_PIN16_Pos (16UL) /*!< Position of PIN16 field. */ #define GPIO_DIRSET_PIN16_Msk (0x1UL << GPIO_DIRSET_PIN16_Pos) /*!< Bit mask of PIN16 field. */ #define GPIO_DIRSET_PIN16_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRSET_PIN16_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRSET_PIN16_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ +#define GPIO_DIRSET_PIN16_Set (1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */ /* Bit 15 : Set as output pin 15 */ #define GPIO_DIRSET_PIN15_Pos (15UL) /*!< Position of PIN15 field. */ #define GPIO_DIRSET_PIN15_Msk (0x1UL << GPIO_DIRSET_PIN15_Pos) /*!< Bit mask of PIN15 field. */ #define GPIO_DIRSET_PIN15_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRSET_PIN15_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRSET_PIN15_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ +#define GPIO_DIRSET_PIN15_Set (1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */ /* Bit 14 : Set as output pin 14 */ #define GPIO_DIRSET_PIN14_Pos (14UL) /*!< Position of PIN14 field. */ #define GPIO_DIRSET_PIN14_Msk (0x1UL << GPIO_DIRSET_PIN14_Pos) /*!< Bit mask of PIN14 field. */ #define GPIO_DIRSET_PIN14_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRSET_PIN14_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRSET_PIN14_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ +#define GPIO_DIRSET_PIN14_Set (1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */ /* Bit 13 : Set as output pin 13 */ #define GPIO_DIRSET_PIN13_Pos (13UL) /*!< Position of PIN13 field. */ #define GPIO_DIRSET_PIN13_Msk (0x1UL << GPIO_DIRSET_PIN13_Pos) /*!< Bit mask of PIN13 field. */ #define GPIO_DIRSET_PIN13_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRSET_PIN13_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRSET_PIN13_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ +#define GPIO_DIRSET_PIN13_Set (1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */ /* Bit 12 : Set as output pin 12 */ #define GPIO_DIRSET_PIN12_Pos (12UL) /*!< Position of PIN12 field. */ #define GPIO_DIRSET_PIN12_Msk (0x1UL << GPIO_DIRSET_PIN12_Pos) /*!< Bit mask of PIN12 field. */ #define GPIO_DIRSET_PIN12_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRSET_PIN12_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRSET_PIN12_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ +#define GPIO_DIRSET_PIN12_Set (1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */ /* Bit 11 : Set as output pin 11 */ #define GPIO_DIRSET_PIN11_Pos (11UL) /*!< Position of PIN11 field. */ #define GPIO_DIRSET_PIN11_Msk (0x1UL << GPIO_DIRSET_PIN11_Pos) /*!< Bit mask of PIN11 field. */ #define GPIO_DIRSET_PIN11_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRSET_PIN11_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRSET_PIN11_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ +#define GPIO_DIRSET_PIN11_Set (1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */ /* Bit 10 : Set as output pin 10 */ #define GPIO_DIRSET_PIN10_Pos (10UL) /*!< Position of PIN10 field. */ #define GPIO_DIRSET_PIN10_Msk (0x1UL << GPIO_DIRSET_PIN10_Pos) /*!< Bit mask of PIN10 field. */ #define GPIO_DIRSET_PIN10_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRSET_PIN10_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRSET_PIN10_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ +#define GPIO_DIRSET_PIN10_Set (1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */ /* Bit 9 : Set as output pin 9 */ #define GPIO_DIRSET_PIN9_Pos (9UL) /*!< Position of PIN9 field. */ #define GPIO_DIRSET_PIN9_Msk (0x1UL << GPIO_DIRSET_PIN9_Pos) /*!< Bit mask of PIN9 field. */ #define GPIO_DIRSET_PIN9_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRSET_PIN9_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRSET_PIN9_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ +#define GPIO_DIRSET_PIN9_Set (1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */ /* Bit 8 : Set as output pin 8 */ #define GPIO_DIRSET_PIN8_Pos (8UL) /*!< Position of PIN8 field. */ #define GPIO_DIRSET_PIN8_Msk (0x1UL << GPIO_DIRSET_PIN8_Pos) /*!< Bit mask of PIN8 field. */ #define GPIO_DIRSET_PIN8_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRSET_PIN8_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRSET_PIN8_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ +#define GPIO_DIRSET_PIN8_Set (1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */ /* Bit 7 : Set as output pin 7 */ #define GPIO_DIRSET_PIN7_Pos (7UL) /*!< Position of PIN7 field. */ #define GPIO_DIRSET_PIN7_Msk (0x1UL << GPIO_DIRSET_PIN7_Pos) /*!< Bit mask of PIN7 field. */ #define GPIO_DIRSET_PIN7_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRSET_PIN7_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRSET_PIN7_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ +#define GPIO_DIRSET_PIN7_Set (1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */ /* Bit 6 : Set as output pin 6 */ #define GPIO_DIRSET_PIN6_Pos (6UL) /*!< Position of PIN6 field. */ #define GPIO_DIRSET_PIN6_Msk (0x1UL << GPIO_DIRSET_PIN6_Pos) /*!< Bit mask of PIN6 field. */ #define GPIO_DIRSET_PIN6_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRSET_PIN6_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRSET_PIN6_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ +#define GPIO_DIRSET_PIN6_Set (1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */ /* Bit 5 : Set as output pin 5 */ #define GPIO_DIRSET_PIN5_Pos (5UL) /*!< Position of PIN5 field. */ #define GPIO_DIRSET_PIN5_Msk (0x1UL << GPIO_DIRSET_PIN5_Pos) /*!< Bit mask of PIN5 field. */ #define GPIO_DIRSET_PIN5_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRSET_PIN5_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRSET_PIN5_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ +#define GPIO_DIRSET_PIN5_Set (1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */ /* Bit 4 : Set as output pin 4 */ #define GPIO_DIRSET_PIN4_Pos (4UL) /*!< Position of PIN4 field. */ #define GPIO_DIRSET_PIN4_Msk (0x1UL << GPIO_DIRSET_PIN4_Pos) /*!< Bit mask of PIN4 field. */ #define GPIO_DIRSET_PIN4_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRSET_PIN4_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRSET_PIN4_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ +#define GPIO_DIRSET_PIN4_Set (1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */ /* Bit 3 : Set as output pin 3 */ #define GPIO_DIRSET_PIN3_Pos (3UL) /*!< Position of PIN3 field. */ #define GPIO_DIRSET_PIN3_Msk (0x1UL << GPIO_DIRSET_PIN3_Pos) /*!< Bit mask of PIN3 field. */ #define GPIO_DIRSET_PIN3_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRSET_PIN3_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRSET_PIN3_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ +#define GPIO_DIRSET_PIN3_Set (1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */ /* Bit 2 : Set as output pin 2 */ #define GPIO_DIRSET_PIN2_Pos (2UL) /*!< Position of PIN2 field. */ #define GPIO_DIRSET_PIN2_Msk (0x1UL << GPIO_DIRSET_PIN2_Pos) /*!< Bit mask of PIN2 field. */ #define GPIO_DIRSET_PIN2_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRSET_PIN2_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRSET_PIN2_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ +#define GPIO_DIRSET_PIN2_Set (1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */ /* Bit 1 : Set as output pin 1 */ #define GPIO_DIRSET_PIN1_Pos (1UL) /*!< Position of PIN1 field. */ #define GPIO_DIRSET_PIN1_Msk (0x1UL << GPIO_DIRSET_PIN1_Pos) /*!< Bit mask of PIN1 field. */ #define GPIO_DIRSET_PIN1_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRSET_PIN1_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRSET_PIN1_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ +#define GPIO_DIRSET_PIN1_Set (1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */ /* Bit 0 : Set as output pin 0 */ #define GPIO_DIRSET_PIN0_Pos (0UL) /*!< Position of PIN0 field. */ #define GPIO_DIRSET_PIN0_Msk (0x1UL << GPIO_DIRSET_PIN0_Pos) /*!< Bit mask of PIN0 field. */ #define GPIO_DIRSET_PIN0_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRSET_PIN0_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRSET_PIN0_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ +#define GPIO_DIRSET_PIN0_Set (1UL) /*!< Write: a '1' sets pin to output; a '0' has no effect */ /* Register: GPIO_DIRCLR */ /* Description: DIR clear register */ @@ -3152,224 +3152,224 @@ POSSIBILITY OF SUCH DAMAGE. #define GPIO_DIRCLR_PIN31_Msk (0x1UL << GPIO_DIRCLR_PIN31_Pos) /*!< Bit mask of PIN31 field. */ #define GPIO_DIRCLR_PIN31_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRCLR_PIN31_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRCLR_PIN31_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ +#define GPIO_DIRCLR_PIN31_Clear (1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */ /* Bit 30 : Set as input pin 30 */ #define GPIO_DIRCLR_PIN30_Pos (30UL) /*!< Position of PIN30 field. */ #define GPIO_DIRCLR_PIN30_Msk (0x1UL << GPIO_DIRCLR_PIN30_Pos) /*!< Bit mask of PIN30 field. */ #define GPIO_DIRCLR_PIN30_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRCLR_PIN30_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRCLR_PIN30_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ +#define GPIO_DIRCLR_PIN30_Clear (1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */ /* Bit 29 : Set as input pin 29 */ #define GPIO_DIRCLR_PIN29_Pos (29UL) /*!< Position of PIN29 field. */ #define GPIO_DIRCLR_PIN29_Msk (0x1UL << GPIO_DIRCLR_PIN29_Pos) /*!< Bit mask of PIN29 field. */ #define GPIO_DIRCLR_PIN29_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRCLR_PIN29_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRCLR_PIN29_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ +#define GPIO_DIRCLR_PIN29_Clear (1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */ /* Bit 28 : Set as input pin 28 */ #define GPIO_DIRCLR_PIN28_Pos (28UL) /*!< Position of PIN28 field. */ #define GPIO_DIRCLR_PIN28_Msk (0x1UL << GPIO_DIRCLR_PIN28_Pos) /*!< Bit mask of PIN28 field. */ #define GPIO_DIRCLR_PIN28_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRCLR_PIN28_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRCLR_PIN28_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ +#define GPIO_DIRCLR_PIN28_Clear (1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */ /* Bit 27 : Set as input pin 27 */ #define GPIO_DIRCLR_PIN27_Pos (27UL) /*!< Position of PIN27 field. */ #define GPIO_DIRCLR_PIN27_Msk (0x1UL << GPIO_DIRCLR_PIN27_Pos) /*!< Bit mask of PIN27 field. */ #define GPIO_DIRCLR_PIN27_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRCLR_PIN27_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRCLR_PIN27_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ +#define GPIO_DIRCLR_PIN27_Clear (1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */ /* Bit 26 : Set as input pin 26 */ #define GPIO_DIRCLR_PIN26_Pos (26UL) /*!< Position of PIN26 field. */ #define GPIO_DIRCLR_PIN26_Msk (0x1UL << GPIO_DIRCLR_PIN26_Pos) /*!< Bit mask of PIN26 field. */ #define GPIO_DIRCLR_PIN26_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRCLR_PIN26_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRCLR_PIN26_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ +#define GPIO_DIRCLR_PIN26_Clear (1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */ /* Bit 25 : Set as input pin 25 */ #define GPIO_DIRCLR_PIN25_Pos (25UL) /*!< Position of PIN25 field. */ #define GPIO_DIRCLR_PIN25_Msk (0x1UL << GPIO_DIRCLR_PIN25_Pos) /*!< Bit mask of PIN25 field. */ #define GPIO_DIRCLR_PIN25_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRCLR_PIN25_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRCLR_PIN25_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ +#define GPIO_DIRCLR_PIN25_Clear (1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */ /* Bit 24 : Set as input pin 24 */ #define GPIO_DIRCLR_PIN24_Pos (24UL) /*!< Position of PIN24 field. */ #define GPIO_DIRCLR_PIN24_Msk (0x1UL << GPIO_DIRCLR_PIN24_Pos) /*!< Bit mask of PIN24 field. */ #define GPIO_DIRCLR_PIN24_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRCLR_PIN24_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRCLR_PIN24_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ +#define GPIO_DIRCLR_PIN24_Clear (1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */ /* Bit 23 : Set as input pin 23 */ #define GPIO_DIRCLR_PIN23_Pos (23UL) /*!< Position of PIN23 field. */ #define GPIO_DIRCLR_PIN23_Msk (0x1UL << GPIO_DIRCLR_PIN23_Pos) /*!< Bit mask of PIN23 field. */ #define GPIO_DIRCLR_PIN23_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRCLR_PIN23_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRCLR_PIN23_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ +#define GPIO_DIRCLR_PIN23_Clear (1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */ /* Bit 22 : Set as input pin 22 */ #define GPIO_DIRCLR_PIN22_Pos (22UL) /*!< Position of PIN22 field. */ #define GPIO_DIRCLR_PIN22_Msk (0x1UL << GPIO_DIRCLR_PIN22_Pos) /*!< Bit mask of PIN22 field. */ #define GPIO_DIRCLR_PIN22_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRCLR_PIN22_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRCLR_PIN22_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ +#define GPIO_DIRCLR_PIN22_Clear (1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */ /* Bit 21 : Set as input pin 21 */ #define GPIO_DIRCLR_PIN21_Pos (21UL) /*!< Position of PIN21 field. */ #define GPIO_DIRCLR_PIN21_Msk (0x1UL << GPIO_DIRCLR_PIN21_Pos) /*!< Bit mask of PIN21 field. */ #define GPIO_DIRCLR_PIN21_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRCLR_PIN21_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRCLR_PIN21_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ +#define GPIO_DIRCLR_PIN21_Clear (1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */ /* Bit 20 : Set as input pin 20 */ #define GPIO_DIRCLR_PIN20_Pos (20UL) /*!< Position of PIN20 field. */ #define GPIO_DIRCLR_PIN20_Msk (0x1UL << GPIO_DIRCLR_PIN20_Pos) /*!< Bit mask of PIN20 field. */ #define GPIO_DIRCLR_PIN20_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRCLR_PIN20_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRCLR_PIN20_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ +#define GPIO_DIRCLR_PIN20_Clear (1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */ /* Bit 19 : Set as input pin 19 */ #define GPIO_DIRCLR_PIN19_Pos (19UL) /*!< Position of PIN19 field. */ #define GPIO_DIRCLR_PIN19_Msk (0x1UL << GPIO_DIRCLR_PIN19_Pos) /*!< Bit mask of PIN19 field. */ #define GPIO_DIRCLR_PIN19_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRCLR_PIN19_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRCLR_PIN19_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ +#define GPIO_DIRCLR_PIN19_Clear (1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */ /* Bit 18 : Set as input pin 18 */ #define GPIO_DIRCLR_PIN18_Pos (18UL) /*!< Position of PIN18 field. */ #define GPIO_DIRCLR_PIN18_Msk (0x1UL << GPIO_DIRCLR_PIN18_Pos) /*!< Bit mask of PIN18 field. */ #define GPIO_DIRCLR_PIN18_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRCLR_PIN18_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRCLR_PIN18_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ +#define GPIO_DIRCLR_PIN18_Clear (1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */ /* Bit 17 : Set as input pin 17 */ #define GPIO_DIRCLR_PIN17_Pos (17UL) /*!< Position of PIN17 field. */ #define GPIO_DIRCLR_PIN17_Msk (0x1UL << GPIO_DIRCLR_PIN17_Pos) /*!< Bit mask of PIN17 field. */ #define GPIO_DIRCLR_PIN17_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRCLR_PIN17_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRCLR_PIN17_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ +#define GPIO_DIRCLR_PIN17_Clear (1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */ /* Bit 16 : Set as input pin 16 */ #define GPIO_DIRCLR_PIN16_Pos (16UL) /*!< Position of PIN16 field. */ #define GPIO_DIRCLR_PIN16_Msk (0x1UL << GPIO_DIRCLR_PIN16_Pos) /*!< Bit mask of PIN16 field. */ #define GPIO_DIRCLR_PIN16_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRCLR_PIN16_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRCLR_PIN16_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ +#define GPIO_DIRCLR_PIN16_Clear (1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */ /* Bit 15 : Set as input pin 15 */ #define GPIO_DIRCLR_PIN15_Pos (15UL) /*!< Position of PIN15 field. */ #define GPIO_DIRCLR_PIN15_Msk (0x1UL << GPIO_DIRCLR_PIN15_Pos) /*!< Bit mask of PIN15 field. */ #define GPIO_DIRCLR_PIN15_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRCLR_PIN15_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRCLR_PIN15_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ +#define GPIO_DIRCLR_PIN15_Clear (1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */ /* Bit 14 : Set as input pin 14 */ #define GPIO_DIRCLR_PIN14_Pos (14UL) /*!< Position of PIN14 field. */ #define GPIO_DIRCLR_PIN14_Msk (0x1UL << GPIO_DIRCLR_PIN14_Pos) /*!< Bit mask of PIN14 field. */ #define GPIO_DIRCLR_PIN14_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRCLR_PIN14_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRCLR_PIN14_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ +#define GPIO_DIRCLR_PIN14_Clear (1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */ /* Bit 13 : Set as input pin 13 */ #define GPIO_DIRCLR_PIN13_Pos (13UL) /*!< Position of PIN13 field. */ #define GPIO_DIRCLR_PIN13_Msk (0x1UL << GPIO_DIRCLR_PIN13_Pos) /*!< Bit mask of PIN13 field. */ #define GPIO_DIRCLR_PIN13_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRCLR_PIN13_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRCLR_PIN13_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ +#define GPIO_DIRCLR_PIN13_Clear (1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */ /* Bit 12 : Set as input pin 12 */ #define GPIO_DIRCLR_PIN12_Pos (12UL) /*!< Position of PIN12 field. */ #define GPIO_DIRCLR_PIN12_Msk (0x1UL << GPIO_DIRCLR_PIN12_Pos) /*!< Bit mask of PIN12 field. */ #define GPIO_DIRCLR_PIN12_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRCLR_PIN12_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRCLR_PIN12_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ +#define GPIO_DIRCLR_PIN12_Clear (1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */ /* Bit 11 : Set as input pin 11 */ #define GPIO_DIRCLR_PIN11_Pos (11UL) /*!< Position of PIN11 field. */ #define GPIO_DIRCLR_PIN11_Msk (0x1UL << GPIO_DIRCLR_PIN11_Pos) /*!< Bit mask of PIN11 field. */ #define GPIO_DIRCLR_PIN11_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRCLR_PIN11_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRCLR_PIN11_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ +#define GPIO_DIRCLR_PIN11_Clear (1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */ /* Bit 10 : Set as input pin 10 */ #define GPIO_DIRCLR_PIN10_Pos (10UL) /*!< Position of PIN10 field. */ #define GPIO_DIRCLR_PIN10_Msk (0x1UL << GPIO_DIRCLR_PIN10_Pos) /*!< Bit mask of PIN10 field. */ #define GPIO_DIRCLR_PIN10_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRCLR_PIN10_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRCLR_PIN10_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ +#define GPIO_DIRCLR_PIN10_Clear (1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */ /* Bit 9 : Set as input pin 9 */ #define GPIO_DIRCLR_PIN9_Pos (9UL) /*!< Position of PIN9 field. */ #define GPIO_DIRCLR_PIN9_Msk (0x1UL << GPIO_DIRCLR_PIN9_Pos) /*!< Bit mask of PIN9 field. */ #define GPIO_DIRCLR_PIN9_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRCLR_PIN9_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRCLR_PIN9_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ +#define GPIO_DIRCLR_PIN9_Clear (1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */ /* Bit 8 : Set as input pin 8 */ #define GPIO_DIRCLR_PIN8_Pos (8UL) /*!< Position of PIN8 field. */ #define GPIO_DIRCLR_PIN8_Msk (0x1UL << GPIO_DIRCLR_PIN8_Pos) /*!< Bit mask of PIN8 field. */ #define GPIO_DIRCLR_PIN8_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRCLR_PIN8_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRCLR_PIN8_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ +#define GPIO_DIRCLR_PIN8_Clear (1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */ /* Bit 7 : Set as input pin 7 */ #define GPIO_DIRCLR_PIN7_Pos (7UL) /*!< Position of PIN7 field. */ #define GPIO_DIRCLR_PIN7_Msk (0x1UL << GPIO_DIRCLR_PIN7_Pos) /*!< Bit mask of PIN7 field. */ #define GPIO_DIRCLR_PIN7_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRCLR_PIN7_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRCLR_PIN7_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ +#define GPIO_DIRCLR_PIN7_Clear (1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */ /* Bit 6 : Set as input pin 6 */ #define GPIO_DIRCLR_PIN6_Pos (6UL) /*!< Position of PIN6 field. */ #define GPIO_DIRCLR_PIN6_Msk (0x1UL << GPIO_DIRCLR_PIN6_Pos) /*!< Bit mask of PIN6 field. */ #define GPIO_DIRCLR_PIN6_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRCLR_PIN6_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRCLR_PIN6_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ +#define GPIO_DIRCLR_PIN6_Clear (1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */ /* Bit 5 : Set as input pin 5 */ #define GPIO_DIRCLR_PIN5_Pos (5UL) /*!< Position of PIN5 field. */ #define GPIO_DIRCLR_PIN5_Msk (0x1UL << GPIO_DIRCLR_PIN5_Pos) /*!< Bit mask of PIN5 field. */ #define GPIO_DIRCLR_PIN5_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRCLR_PIN5_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRCLR_PIN5_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ +#define GPIO_DIRCLR_PIN5_Clear (1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */ /* Bit 4 : Set as input pin 4 */ #define GPIO_DIRCLR_PIN4_Pos (4UL) /*!< Position of PIN4 field. */ #define GPIO_DIRCLR_PIN4_Msk (0x1UL << GPIO_DIRCLR_PIN4_Pos) /*!< Bit mask of PIN4 field. */ #define GPIO_DIRCLR_PIN4_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRCLR_PIN4_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRCLR_PIN4_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ +#define GPIO_DIRCLR_PIN4_Clear (1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */ /* Bit 3 : Set as input pin 3 */ #define GPIO_DIRCLR_PIN3_Pos (3UL) /*!< Position of PIN3 field. */ #define GPIO_DIRCLR_PIN3_Msk (0x1UL << GPIO_DIRCLR_PIN3_Pos) /*!< Bit mask of PIN3 field. */ #define GPIO_DIRCLR_PIN3_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRCLR_PIN3_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRCLR_PIN3_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ +#define GPIO_DIRCLR_PIN3_Clear (1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */ /* Bit 2 : Set as input pin 2 */ #define GPIO_DIRCLR_PIN2_Pos (2UL) /*!< Position of PIN2 field. */ #define GPIO_DIRCLR_PIN2_Msk (0x1UL << GPIO_DIRCLR_PIN2_Pos) /*!< Bit mask of PIN2 field. */ #define GPIO_DIRCLR_PIN2_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRCLR_PIN2_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRCLR_PIN2_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ +#define GPIO_DIRCLR_PIN2_Clear (1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */ /* Bit 1 : Set as input pin 1 */ #define GPIO_DIRCLR_PIN1_Pos (1UL) /*!< Position of PIN1 field. */ #define GPIO_DIRCLR_PIN1_Msk (0x1UL << GPIO_DIRCLR_PIN1_Pos) /*!< Bit mask of PIN1 field. */ #define GPIO_DIRCLR_PIN1_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRCLR_PIN1_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRCLR_PIN1_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ +#define GPIO_DIRCLR_PIN1_Clear (1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */ /* Bit 0 : Set as input pin 0 */ #define GPIO_DIRCLR_PIN0_Pos (0UL) /*!< Position of PIN0 field. */ #define GPIO_DIRCLR_PIN0_Msk (0x1UL << GPIO_DIRCLR_PIN0_Pos) /*!< Bit mask of PIN0 field. */ #define GPIO_DIRCLR_PIN0_Input (0UL) /*!< Read: pin set as input */ #define GPIO_DIRCLR_PIN0_Output (1UL) /*!< Read: pin set as output */ -#define GPIO_DIRCLR_PIN0_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ +#define GPIO_DIRCLR_PIN0_Clear (1UL) /*!< Write: a '1' sets pin to input; a '0' has no effect */ /* Register: GPIO_LATCH */ /* Description: Latch register indicating what GPIO pins that have met the criteria set in the PIN_CNF[n].SENSE registers */ @@ -3567,13 +3567,13 @@ POSSIBILITY OF SUCH DAMAGE. #define GPIO_LATCH_PIN0_Latched (1UL) /*!< Criteria has been met */ /* Register: GPIO_DETECTMODE */ -/* Description: Select between default DETECT signal behaviour and LDETECT mode */ +/* Description: Select between default DETECT signal behavior and LDETECT mode */ -/* Bit 0 : Select between default DETECT signal behaviour and LDETECT mode */ +/* Bit 0 : Select between default DETECT signal behavior and LDETECT mode */ #define GPIO_DETECTMODE_DETECTMODE_Pos (0UL) /*!< Position of DETECTMODE field. */ #define GPIO_DETECTMODE_DETECTMODE_Msk (0x1UL << GPIO_DETECTMODE_DETECTMODE_Pos) /*!< Bit mask of DETECTMODE field. */ #define GPIO_DETECTMODE_DETECTMODE_Default (0UL) /*!< DETECT directly connected to PIN DETECT signals */ -#define GPIO_DETECTMODE_DETECTMODE_LDETECT (1UL) /*!< Use the latched LDETECT behaviour */ +#define GPIO_DETECTMODE_DETECTMODE_LDETECT (1UL) /*!< Use the latched LDETECT behavior */ /* Register: GPIO_PIN_CNF */ /* Description: Description collection: Configuration of GPIO pins */ @@ -3974,66 +3974,6 @@ POSSIBILITY OF SUCH DAMAGE. #define PPI_CHEN_CH20_Disabled (0UL) /*!< Disable channel */ #define PPI_CHEN_CH20_Enabled (1UL) /*!< Enable channel */ -/* Bit 19 : Enable or disable channel 19 */ -#define PPI_CHEN_CH19_Pos (19UL) /*!< Position of CH19 field. */ -#define PPI_CHEN_CH19_Msk (0x1UL << PPI_CHEN_CH19_Pos) /*!< Bit mask of CH19 field. */ -#define PPI_CHEN_CH19_Disabled (0UL) /*!< Disable channel */ -#define PPI_CHEN_CH19_Enabled (1UL) /*!< Enable channel */ - -/* Bit 18 : Enable or disable channel 18 */ -#define PPI_CHEN_CH18_Pos (18UL) /*!< Position of CH18 field. */ -#define PPI_CHEN_CH18_Msk (0x1UL << PPI_CHEN_CH18_Pos) /*!< Bit mask of CH18 field. */ -#define PPI_CHEN_CH18_Disabled (0UL) /*!< Disable channel */ -#define PPI_CHEN_CH18_Enabled (1UL) /*!< Enable channel */ - -/* Bit 17 : Enable or disable channel 17 */ -#define PPI_CHEN_CH17_Pos (17UL) /*!< Position of CH17 field. */ -#define PPI_CHEN_CH17_Msk (0x1UL << PPI_CHEN_CH17_Pos) /*!< Bit mask of CH17 field. */ -#define PPI_CHEN_CH17_Disabled (0UL) /*!< Disable channel */ -#define PPI_CHEN_CH17_Enabled (1UL) /*!< Enable channel */ - -/* Bit 16 : Enable or disable channel 16 */ -#define PPI_CHEN_CH16_Pos (16UL) /*!< Position of CH16 field. */ -#define PPI_CHEN_CH16_Msk (0x1UL << PPI_CHEN_CH16_Pos) /*!< Bit mask of CH16 field. */ -#define PPI_CHEN_CH16_Disabled (0UL) /*!< Disable channel */ -#define PPI_CHEN_CH16_Enabled (1UL) /*!< Enable channel */ - -/* Bit 15 : Enable or disable channel 15 */ -#define PPI_CHEN_CH15_Pos (15UL) /*!< Position of CH15 field. */ -#define PPI_CHEN_CH15_Msk (0x1UL << PPI_CHEN_CH15_Pos) /*!< Bit mask of CH15 field. */ -#define PPI_CHEN_CH15_Disabled (0UL) /*!< Disable channel */ -#define PPI_CHEN_CH15_Enabled (1UL) /*!< Enable channel */ - -/* Bit 14 : Enable or disable channel 14 */ -#define PPI_CHEN_CH14_Pos (14UL) /*!< Position of CH14 field. */ -#define PPI_CHEN_CH14_Msk (0x1UL << PPI_CHEN_CH14_Pos) /*!< Bit mask of CH14 field. */ -#define PPI_CHEN_CH14_Disabled (0UL) /*!< Disable channel */ -#define PPI_CHEN_CH14_Enabled (1UL) /*!< Enable channel */ - -/* Bit 13 : Enable or disable channel 13 */ -#define PPI_CHEN_CH13_Pos (13UL) /*!< Position of CH13 field. */ -#define PPI_CHEN_CH13_Msk (0x1UL << PPI_CHEN_CH13_Pos) /*!< Bit mask of CH13 field. */ -#define PPI_CHEN_CH13_Disabled (0UL) /*!< Disable channel */ -#define PPI_CHEN_CH13_Enabled (1UL) /*!< Enable channel */ - -/* Bit 12 : Enable or disable channel 12 */ -#define PPI_CHEN_CH12_Pos (12UL) /*!< Position of CH12 field. */ -#define PPI_CHEN_CH12_Msk (0x1UL << PPI_CHEN_CH12_Pos) /*!< Bit mask of CH12 field. */ -#define PPI_CHEN_CH12_Disabled (0UL) /*!< Disable channel */ -#define PPI_CHEN_CH12_Enabled (1UL) /*!< Enable channel */ - -/* Bit 11 : Enable or disable channel 11 */ -#define PPI_CHEN_CH11_Pos (11UL) /*!< Position of CH11 field. */ -#define PPI_CHEN_CH11_Msk (0x1UL << PPI_CHEN_CH11_Pos) /*!< Bit mask of CH11 field. */ -#define PPI_CHEN_CH11_Disabled (0UL) /*!< Disable channel */ -#define PPI_CHEN_CH11_Enabled (1UL) /*!< Enable channel */ - -/* Bit 10 : Enable or disable channel 10 */ -#define PPI_CHEN_CH10_Pos (10UL) /*!< Position of CH10 field. */ -#define PPI_CHEN_CH10_Msk (0x1UL << PPI_CHEN_CH10_Pos) /*!< Bit mask of CH10 field. */ -#define PPI_CHEN_CH10_Disabled (0UL) /*!< Disable channel */ -#define PPI_CHEN_CH10_Enabled (1UL) /*!< Enable channel */ - /* Bit 9 : Enable or disable channel 9 */ #define PPI_CHEN_CH9_Pos (9UL) /*!< Position of CH9 field. */ #define PPI_CHEN_CH9_Msk (0x1UL << PPI_CHEN_CH9_Pos) /*!< Bit mask of CH9 field. */ @@ -4097,224 +4037,154 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: PPI_CHENSET */ /* Description: Channel enable set register */ -/* Bit 31 : Channel 31 enable set register. Writing '0' has no effect */ +/* Bit 31 : Channel 31 enable set register. Writing '0' has no effect. */ #define PPI_CHENSET_CH31_Pos (31UL) /*!< Position of CH31 field. */ #define PPI_CHENSET_CH31_Msk (0x1UL << PPI_CHENSET_CH31_Pos) /*!< Bit mask of CH31 field. */ #define PPI_CHENSET_CH31_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENSET_CH31_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENSET_CH31_Set (1UL) /*!< Write: Enable channel */ -/* Bit 30 : Channel 30 enable set register. Writing '0' has no effect */ +/* Bit 30 : Channel 30 enable set register. Writing '0' has no effect. */ #define PPI_CHENSET_CH30_Pos (30UL) /*!< Position of CH30 field. */ #define PPI_CHENSET_CH30_Msk (0x1UL << PPI_CHENSET_CH30_Pos) /*!< Bit mask of CH30 field. */ #define PPI_CHENSET_CH30_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENSET_CH30_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENSET_CH30_Set (1UL) /*!< Write: Enable channel */ -/* Bit 29 : Channel 29 enable set register. Writing '0' has no effect */ +/* Bit 29 : Channel 29 enable set register. Writing '0' has no effect. */ #define PPI_CHENSET_CH29_Pos (29UL) /*!< Position of CH29 field. */ #define PPI_CHENSET_CH29_Msk (0x1UL << PPI_CHENSET_CH29_Pos) /*!< Bit mask of CH29 field. */ #define PPI_CHENSET_CH29_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENSET_CH29_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENSET_CH29_Set (1UL) /*!< Write: Enable channel */ -/* Bit 28 : Channel 28 enable set register. Writing '0' has no effect */ +/* Bit 28 : Channel 28 enable set register. Writing '0' has no effect. */ #define PPI_CHENSET_CH28_Pos (28UL) /*!< Position of CH28 field. */ #define PPI_CHENSET_CH28_Msk (0x1UL << PPI_CHENSET_CH28_Pos) /*!< Bit mask of CH28 field. */ #define PPI_CHENSET_CH28_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENSET_CH28_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENSET_CH28_Set (1UL) /*!< Write: Enable channel */ -/* Bit 27 : Channel 27 enable set register. Writing '0' has no effect */ +/* Bit 27 : Channel 27 enable set register. Writing '0' has no effect. */ #define PPI_CHENSET_CH27_Pos (27UL) /*!< Position of CH27 field. */ #define PPI_CHENSET_CH27_Msk (0x1UL << PPI_CHENSET_CH27_Pos) /*!< Bit mask of CH27 field. */ #define PPI_CHENSET_CH27_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENSET_CH27_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENSET_CH27_Set (1UL) /*!< Write: Enable channel */ -/* Bit 26 : Channel 26 enable set register. Writing '0' has no effect */ +/* Bit 26 : Channel 26 enable set register. Writing '0' has no effect. */ #define PPI_CHENSET_CH26_Pos (26UL) /*!< Position of CH26 field. */ #define PPI_CHENSET_CH26_Msk (0x1UL << PPI_CHENSET_CH26_Pos) /*!< Bit mask of CH26 field. */ #define PPI_CHENSET_CH26_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENSET_CH26_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENSET_CH26_Set (1UL) /*!< Write: Enable channel */ -/* Bit 25 : Channel 25 enable set register. Writing '0' has no effect */ +/* Bit 25 : Channel 25 enable set register. Writing '0' has no effect. */ #define PPI_CHENSET_CH25_Pos (25UL) /*!< Position of CH25 field. */ #define PPI_CHENSET_CH25_Msk (0x1UL << PPI_CHENSET_CH25_Pos) /*!< Bit mask of CH25 field. */ #define PPI_CHENSET_CH25_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENSET_CH25_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENSET_CH25_Set (1UL) /*!< Write: Enable channel */ -/* Bit 24 : Channel 24 enable set register. Writing '0' has no effect */ +/* Bit 24 : Channel 24 enable set register. Writing '0' has no effect. */ #define PPI_CHENSET_CH24_Pos (24UL) /*!< Position of CH24 field. */ #define PPI_CHENSET_CH24_Msk (0x1UL << PPI_CHENSET_CH24_Pos) /*!< Bit mask of CH24 field. */ #define PPI_CHENSET_CH24_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENSET_CH24_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENSET_CH24_Set (1UL) /*!< Write: Enable channel */ -/* Bit 23 : Channel 23 enable set register. Writing '0' has no effect */ +/* Bit 23 : Channel 23 enable set register. Writing '0' has no effect. */ #define PPI_CHENSET_CH23_Pos (23UL) /*!< Position of CH23 field. */ #define PPI_CHENSET_CH23_Msk (0x1UL << PPI_CHENSET_CH23_Pos) /*!< Bit mask of CH23 field. */ #define PPI_CHENSET_CH23_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENSET_CH23_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENSET_CH23_Set (1UL) /*!< Write: Enable channel */ -/* Bit 22 : Channel 22 enable set register. Writing '0' has no effect */ +/* Bit 22 : Channel 22 enable set register. Writing '0' has no effect. */ #define PPI_CHENSET_CH22_Pos (22UL) /*!< Position of CH22 field. */ #define PPI_CHENSET_CH22_Msk (0x1UL << PPI_CHENSET_CH22_Pos) /*!< Bit mask of CH22 field. */ #define PPI_CHENSET_CH22_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENSET_CH22_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENSET_CH22_Set (1UL) /*!< Write: Enable channel */ -/* Bit 21 : Channel 21 enable set register. Writing '0' has no effect */ +/* Bit 21 : Channel 21 enable set register. Writing '0' has no effect. */ #define PPI_CHENSET_CH21_Pos (21UL) /*!< Position of CH21 field. */ #define PPI_CHENSET_CH21_Msk (0x1UL << PPI_CHENSET_CH21_Pos) /*!< Bit mask of CH21 field. */ #define PPI_CHENSET_CH21_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENSET_CH21_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENSET_CH21_Set (1UL) /*!< Write: Enable channel */ -/* Bit 20 : Channel 20 enable set register. Writing '0' has no effect */ +/* Bit 20 : Channel 20 enable set register. Writing '0' has no effect. */ #define PPI_CHENSET_CH20_Pos (20UL) /*!< Position of CH20 field. */ #define PPI_CHENSET_CH20_Msk (0x1UL << PPI_CHENSET_CH20_Pos) /*!< Bit mask of CH20 field. */ #define PPI_CHENSET_CH20_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENSET_CH20_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENSET_CH20_Set (1UL) /*!< Write: Enable channel */ -/* Bit 19 : Channel 19 enable set register. Writing '0' has no effect */ -#define PPI_CHENSET_CH19_Pos (19UL) /*!< Position of CH19 field. */ -#define PPI_CHENSET_CH19_Msk (0x1UL << PPI_CHENSET_CH19_Pos) /*!< Bit mask of CH19 field. */ -#define PPI_CHENSET_CH19_Disabled (0UL) /*!< Read: channel disabled */ -#define PPI_CHENSET_CH19_Enabled (1UL) /*!< Read: channel enabled */ -#define PPI_CHENSET_CH19_Set (1UL) /*!< Write: Enable channel */ - -/* Bit 18 : Channel 18 enable set register. Writing '0' has no effect */ -#define PPI_CHENSET_CH18_Pos (18UL) /*!< Position of CH18 field. */ -#define PPI_CHENSET_CH18_Msk (0x1UL << PPI_CHENSET_CH18_Pos) /*!< Bit mask of CH18 field. */ -#define PPI_CHENSET_CH18_Disabled (0UL) /*!< Read: channel disabled */ -#define PPI_CHENSET_CH18_Enabled (1UL) /*!< Read: channel enabled */ -#define PPI_CHENSET_CH18_Set (1UL) /*!< Write: Enable channel */ - -/* Bit 17 : Channel 17 enable set register. Writing '0' has no effect */ -#define PPI_CHENSET_CH17_Pos (17UL) /*!< Position of CH17 field. */ -#define PPI_CHENSET_CH17_Msk (0x1UL << PPI_CHENSET_CH17_Pos) /*!< Bit mask of CH17 field. */ -#define PPI_CHENSET_CH17_Disabled (0UL) /*!< Read: channel disabled */ -#define PPI_CHENSET_CH17_Enabled (1UL) /*!< Read: channel enabled */ -#define PPI_CHENSET_CH17_Set (1UL) /*!< Write: Enable channel */ - -/* Bit 16 : Channel 16 enable set register. Writing '0' has no effect */ -#define PPI_CHENSET_CH16_Pos (16UL) /*!< Position of CH16 field. */ -#define PPI_CHENSET_CH16_Msk (0x1UL << PPI_CHENSET_CH16_Pos) /*!< Bit mask of CH16 field. */ -#define PPI_CHENSET_CH16_Disabled (0UL) /*!< Read: channel disabled */ -#define PPI_CHENSET_CH16_Enabled (1UL) /*!< Read: channel enabled */ -#define PPI_CHENSET_CH16_Set (1UL) /*!< Write: Enable channel */ - -/* Bit 15 : Channel 15 enable set register. Writing '0' has no effect */ -#define PPI_CHENSET_CH15_Pos (15UL) /*!< Position of CH15 field. */ -#define PPI_CHENSET_CH15_Msk (0x1UL << PPI_CHENSET_CH15_Pos) /*!< Bit mask of CH15 field. */ -#define PPI_CHENSET_CH15_Disabled (0UL) /*!< Read: channel disabled */ -#define PPI_CHENSET_CH15_Enabled (1UL) /*!< Read: channel enabled */ -#define PPI_CHENSET_CH15_Set (1UL) /*!< Write: Enable channel */ - -/* Bit 14 : Channel 14 enable set register. Writing '0' has no effect */ -#define PPI_CHENSET_CH14_Pos (14UL) /*!< Position of CH14 field. */ -#define PPI_CHENSET_CH14_Msk (0x1UL << PPI_CHENSET_CH14_Pos) /*!< Bit mask of CH14 field. */ -#define PPI_CHENSET_CH14_Disabled (0UL) /*!< Read: channel disabled */ -#define PPI_CHENSET_CH14_Enabled (1UL) /*!< Read: channel enabled */ -#define PPI_CHENSET_CH14_Set (1UL) /*!< Write: Enable channel */ - -/* Bit 13 : Channel 13 enable set register. Writing '0' has no effect */ -#define PPI_CHENSET_CH13_Pos (13UL) /*!< Position of CH13 field. */ -#define PPI_CHENSET_CH13_Msk (0x1UL << PPI_CHENSET_CH13_Pos) /*!< Bit mask of CH13 field. */ -#define PPI_CHENSET_CH13_Disabled (0UL) /*!< Read: channel disabled */ -#define PPI_CHENSET_CH13_Enabled (1UL) /*!< Read: channel enabled */ -#define PPI_CHENSET_CH13_Set (1UL) /*!< Write: Enable channel */ - -/* Bit 12 : Channel 12 enable set register. Writing '0' has no effect */ -#define PPI_CHENSET_CH12_Pos (12UL) /*!< Position of CH12 field. */ -#define PPI_CHENSET_CH12_Msk (0x1UL << PPI_CHENSET_CH12_Pos) /*!< Bit mask of CH12 field. */ -#define PPI_CHENSET_CH12_Disabled (0UL) /*!< Read: channel disabled */ -#define PPI_CHENSET_CH12_Enabled (1UL) /*!< Read: channel enabled */ -#define PPI_CHENSET_CH12_Set (1UL) /*!< Write: Enable channel */ - -/* Bit 11 : Channel 11 enable set register. Writing '0' has no effect */ -#define PPI_CHENSET_CH11_Pos (11UL) /*!< Position of CH11 field. */ -#define PPI_CHENSET_CH11_Msk (0x1UL << PPI_CHENSET_CH11_Pos) /*!< Bit mask of CH11 field. */ -#define PPI_CHENSET_CH11_Disabled (0UL) /*!< Read: channel disabled */ -#define PPI_CHENSET_CH11_Enabled (1UL) /*!< Read: channel enabled */ -#define PPI_CHENSET_CH11_Set (1UL) /*!< Write: Enable channel */ - -/* Bit 10 : Channel 10 enable set register. Writing '0' has no effect */ -#define PPI_CHENSET_CH10_Pos (10UL) /*!< Position of CH10 field. */ -#define PPI_CHENSET_CH10_Msk (0x1UL << PPI_CHENSET_CH10_Pos) /*!< Bit mask of CH10 field. */ -#define PPI_CHENSET_CH10_Disabled (0UL) /*!< Read: channel disabled */ -#define PPI_CHENSET_CH10_Enabled (1UL) /*!< Read: channel enabled */ -#define PPI_CHENSET_CH10_Set (1UL) /*!< Write: Enable channel */ - -/* Bit 9 : Channel 9 enable set register. Writing '0' has no effect */ +/* Bit 9 : Channel 9 enable set register. Writing '0' has no effect. */ #define PPI_CHENSET_CH9_Pos (9UL) /*!< Position of CH9 field. */ #define PPI_CHENSET_CH9_Msk (0x1UL << PPI_CHENSET_CH9_Pos) /*!< Bit mask of CH9 field. */ #define PPI_CHENSET_CH9_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENSET_CH9_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENSET_CH9_Set (1UL) /*!< Write: Enable channel */ -/* Bit 8 : Channel 8 enable set register. Writing '0' has no effect */ +/* Bit 8 : Channel 8 enable set register. Writing '0' has no effect. */ #define PPI_CHENSET_CH8_Pos (8UL) /*!< Position of CH8 field. */ #define PPI_CHENSET_CH8_Msk (0x1UL << PPI_CHENSET_CH8_Pos) /*!< Bit mask of CH8 field. */ #define PPI_CHENSET_CH8_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENSET_CH8_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENSET_CH8_Set (1UL) /*!< Write: Enable channel */ -/* Bit 7 : Channel 7 enable set register. Writing '0' has no effect */ +/* Bit 7 : Channel 7 enable set register. Writing '0' has no effect. */ #define PPI_CHENSET_CH7_Pos (7UL) /*!< Position of CH7 field. */ #define PPI_CHENSET_CH7_Msk (0x1UL << PPI_CHENSET_CH7_Pos) /*!< Bit mask of CH7 field. */ #define PPI_CHENSET_CH7_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENSET_CH7_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENSET_CH7_Set (1UL) /*!< Write: Enable channel */ -/* Bit 6 : Channel 6 enable set register. Writing '0' has no effect */ +/* Bit 6 : Channel 6 enable set register. Writing '0' has no effect. */ #define PPI_CHENSET_CH6_Pos (6UL) /*!< Position of CH6 field. */ #define PPI_CHENSET_CH6_Msk (0x1UL << PPI_CHENSET_CH6_Pos) /*!< Bit mask of CH6 field. */ #define PPI_CHENSET_CH6_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENSET_CH6_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENSET_CH6_Set (1UL) /*!< Write: Enable channel */ -/* Bit 5 : Channel 5 enable set register. Writing '0' has no effect */ +/* Bit 5 : Channel 5 enable set register. Writing '0' has no effect. */ #define PPI_CHENSET_CH5_Pos (5UL) /*!< Position of CH5 field. */ #define PPI_CHENSET_CH5_Msk (0x1UL << PPI_CHENSET_CH5_Pos) /*!< Bit mask of CH5 field. */ #define PPI_CHENSET_CH5_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENSET_CH5_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENSET_CH5_Set (1UL) /*!< Write: Enable channel */ -/* Bit 4 : Channel 4 enable set register. Writing '0' has no effect */ +/* Bit 4 : Channel 4 enable set register. Writing '0' has no effect. */ #define PPI_CHENSET_CH4_Pos (4UL) /*!< Position of CH4 field. */ #define PPI_CHENSET_CH4_Msk (0x1UL << PPI_CHENSET_CH4_Pos) /*!< Bit mask of CH4 field. */ #define PPI_CHENSET_CH4_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENSET_CH4_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENSET_CH4_Set (1UL) /*!< Write: Enable channel */ -/* Bit 3 : Channel 3 enable set register. Writing '0' has no effect */ +/* Bit 3 : Channel 3 enable set register. Writing '0' has no effect. */ #define PPI_CHENSET_CH3_Pos (3UL) /*!< Position of CH3 field. */ #define PPI_CHENSET_CH3_Msk (0x1UL << PPI_CHENSET_CH3_Pos) /*!< Bit mask of CH3 field. */ #define PPI_CHENSET_CH3_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENSET_CH3_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENSET_CH3_Set (1UL) /*!< Write: Enable channel */ -/* Bit 2 : Channel 2 enable set register. Writing '0' has no effect */ +/* Bit 2 : Channel 2 enable set register. Writing '0' has no effect. */ #define PPI_CHENSET_CH2_Pos (2UL) /*!< Position of CH2 field. */ #define PPI_CHENSET_CH2_Msk (0x1UL << PPI_CHENSET_CH2_Pos) /*!< Bit mask of CH2 field. */ #define PPI_CHENSET_CH2_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENSET_CH2_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENSET_CH2_Set (1UL) /*!< Write: Enable channel */ -/* Bit 1 : Channel 1 enable set register. Writing '0' has no effect */ +/* Bit 1 : Channel 1 enable set register. Writing '0' has no effect. */ #define PPI_CHENSET_CH1_Pos (1UL) /*!< Position of CH1 field. */ #define PPI_CHENSET_CH1_Msk (0x1UL << PPI_CHENSET_CH1_Pos) /*!< Bit mask of CH1 field. */ #define PPI_CHENSET_CH1_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENSET_CH1_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENSET_CH1_Set (1UL) /*!< Write: Enable channel */ -/* Bit 0 : Channel 0 enable set register. Writing '0' has no effect */ +/* Bit 0 : Channel 0 enable set register. Writing '0' has no effect. */ #define PPI_CHENSET_CH0_Pos (0UL) /*!< Position of CH0 field. */ #define PPI_CHENSET_CH0_Msk (0x1UL << PPI_CHENSET_CH0_Pos) /*!< Bit mask of CH0 field. */ #define PPI_CHENSET_CH0_Disabled (0UL) /*!< Read: channel disabled */ @@ -4324,224 +4194,154 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: PPI_CHENCLR */ /* Description: Channel enable clear register */ -/* Bit 31 : Channel 31 enable clear register. Writing '0' has no effect */ +/* Bit 31 : Channel 31 enable clear register. Writing '0' has no effect. */ #define PPI_CHENCLR_CH31_Pos (31UL) /*!< Position of CH31 field. */ #define PPI_CHENCLR_CH31_Msk (0x1UL << PPI_CHENCLR_CH31_Pos) /*!< Bit mask of CH31 field. */ #define PPI_CHENCLR_CH31_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENCLR_CH31_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENCLR_CH31_Clear (1UL) /*!< Write: disable channel */ -/* Bit 30 : Channel 30 enable clear register. Writing '0' has no effect */ +/* Bit 30 : Channel 30 enable clear register. Writing '0' has no effect. */ #define PPI_CHENCLR_CH30_Pos (30UL) /*!< Position of CH30 field. */ #define PPI_CHENCLR_CH30_Msk (0x1UL << PPI_CHENCLR_CH30_Pos) /*!< Bit mask of CH30 field. */ #define PPI_CHENCLR_CH30_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENCLR_CH30_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENCLR_CH30_Clear (1UL) /*!< Write: disable channel */ -/* Bit 29 : Channel 29 enable clear register. Writing '0' has no effect */ +/* Bit 29 : Channel 29 enable clear register. Writing '0' has no effect. */ #define PPI_CHENCLR_CH29_Pos (29UL) /*!< Position of CH29 field. */ #define PPI_CHENCLR_CH29_Msk (0x1UL << PPI_CHENCLR_CH29_Pos) /*!< Bit mask of CH29 field. */ #define PPI_CHENCLR_CH29_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENCLR_CH29_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENCLR_CH29_Clear (1UL) /*!< Write: disable channel */ -/* Bit 28 : Channel 28 enable clear register. Writing '0' has no effect */ +/* Bit 28 : Channel 28 enable clear register. Writing '0' has no effect. */ #define PPI_CHENCLR_CH28_Pos (28UL) /*!< Position of CH28 field. */ #define PPI_CHENCLR_CH28_Msk (0x1UL << PPI_CHENCLR_CH28_Pos) /*!< Bit mask of CH28 field. */ #define PPI_CHENCLR_CH28_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENCLR_CH28_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENCLR_CH28_Clear (1UL) /*!< Write: disable channel */ -/* Bit 27 : Channel 27 enable clear register. Writing '0' has no effect */ +/* Bit 27 : Channel 27 enable clear register. Writing '0' has no effect. */ #define PPI_CHENCLR_CH27_Pos (27UL) /*!< Position of CH27 field. */ #define PPI_CHENCLR_CH27_Msk (0x1UL << PPI_CHENCLR_CH27_Pos) /*!< Bit mask of CH27 field. */ #define PPI_CHENCLR_CH27_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENCLR_CH27_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENCLR_CH27_Clear (1UL) /*!< Write: disable channel */ -/* Bit 26 : Channel 26 enable clear register. Writing '0' has no effect */ +/* Bit 26 : Channel 26 enable clear register. Writing '0' has no effect. */ #define PPI_CHENCLR_CH26_Pos (26UL) /*!< Position of CH26 field. */ #define PPI_CHENCLR_CH26_Msk (0x1UL << PPI_CHENCLR_CH26_Pos) /*!< Bit mask of CH26 field. */ #define PPI_CHENCLR_CH26_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENCLR_CH26_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENCLR_CH26_Clear (1UL) /*!< Write: disable channel */ -/* Bit 25 : Channel 25 enable clear register. Writing '0' has no effect */ +/* Bit 25 : Channel 25 enable clear register. Writing '0' has no effect. */ #define PPI_CHENCLR_CH25_Pos (25UL) /*!< Position of CH25 field. */ #define PPI_CHENCLR_CH25_Msk (0x1UL << PPI_CHENCLR_CH25_Pos) /*!< Bit mask of CH25 field. */ #define PPI_CHENCLR_CH25_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENCLR_CH25_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENCLR_CH25_Clear (1UL) /*!< Write: disable channel */ -/* Bit 24 : Channel 24 enable clear register. Writing '0' has no effect */ +/* Bit 24 : Channel 24 enable clear register. Writing '0' has no effect. */ #define PPI_CHENCLR_CH24_Pos (24UL) /*!< Position of CH24 field. */ #define PPI_CHENCLR_CH24_Msk (0x1UL << PPI_CHENCLR_CH24_Pos) /*!< Bit mask of CH24 field. */ #define PPI_CHENCLR_CH24_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENCLR_CH24_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENCLR_CH24_Clear (1UL) /*!< Write: disable channel */ -/* Bit 23 : Channel 23 enable clear register. Writing '0' has no effect */ +/* Bit 23 : Channel 23 enable clear register. Writing '0' has no effect. */ #define PPI_CHENCLR_CH23_Pos (23UL) /*!< Position of CH23 field. */ #define PPI_CHENCLR_CH23_Msk (0x1UL << PPI_CHENCLR_CH23_Pos) /*!< Bit mask of CH23 field. */ #define PPI_CHENCLR_CH23_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENCLR_CH23_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENCLR_CH23_Clear (1UL) /*!< Write: disable channel */ -/* Bit 22 : Channel 22 enable clear register. Writing '0' has no effect */ +/* Bit 22 : Channel 22 enable clear register. Writing '0' has no effect. */ #define PPI_CHENCLR_CH22_Pos (22UL) /*!< Position of CH22 field. */ #define PPI_CHENCLR_CH22_Msk (0x1UL << PPI_CHENCLR_CH22_Pos) /*!< Bit mask of CH22 field. */ #define PPI_CHENCLR_CH22_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENCLR_CH22_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENCLR_CH22_Clear (1UL) /*!< Write: disable channel */ -/* Bit 21 : Channel 21 enable clear register. Writing '0' has no effect */ +/* Bit 21 : Channel 21 enable clear register. Writing '0' has no effect. */ #define PPI_CHENCLR_CH21_Pos (21UL) /*!< Position of CH21 field. */ #define PPI_CHENCLR_CH21_Msk (0x1UL << PPI_CHENCLR_CH21_Pos) /*!< Bit mask of CH21 field. */ #define PPI_CHENCLR_CH21_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENCLR_CH21_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENCLR_CH21_Clear (1UL) /*!< Write: disable channel */ -/* Bit 20 : Channel 20 enable clear register. Writing '0' has no effect */ +/* Bit 20 : Channel 20 enable clear register. Writing '0' has no effect. */ #define PPI_CHENCLR_CH20_Pos (20UL) /*!< Position of CH20 field. */ #define PPI_CHENCLR_CH20_Msk (0x1UL << PPI_CHENCLR_CH20_Pos) /*!< Bit mask of CH20 field. */ #define PPI_CHENCLR_CH20_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENCLR_CH20_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENCLR_CH20_Clear (1UL) /*!< Write: disable channel */ -/* Bit 19 : Channel 19 enable clear register. Writing '0' has no effect */ -#define PPI_CHENCLR_CH19_Pos (19UL) /*!< Position of CH19 field. */ -#define PPI_CHENCLR_CH19_Msk (0x1UL << PPI_CHENCLR_CH19_Pos) /*!< Bit mask of CH19 field. */ -#define PPI_CHENCLR_CH19_Disabled (0UL) /*!< Read: channel disabled */ -#define PPI_CHENCLR_CH19_Enabled (1UL) /*!< Read: channel enabled */ -#define PPI_CHENCLR_CH19_Clear (1UL) /*!< Write: disable channel */ - -/* Bit 18 : Channel 18 enable clear register. Writing '0' has no effect */ -#define PPI_CHENCLR_CH18_Pos (18UL) /*!< Position of CH18 field. */ -#define PPI_CHENCLR_CH18_Msk (0x1UL << PPI_CHENCLR_CH18_Pos) /*!< Bit mask of CH18 field. */ -#define PPI_CHENCLR_CH18_Disabled (0UL) /*!< Read: channel disabled */ -#define PPI_CHENCLR_CH18_Enabled (1UL) /*!< Read: channel enabled */ -#define PPI_CHENCLR_CH18_Clear (1UL) /*!< Write: disable channel */ - -/* Bit 17 : Channel 17 enable clear register. Writing '0' has no effect */ -#define PPI_CHENCLR_CH17_Pos (17UL) /*!< Position of CH17 field. */ -#define PPI_CHENCLR_CH17_Msk (0x1UL << PPI_CHENCLR_CH17_Pos) /*!< Bit mask of CH17 field. */ -#define PPI_CHENCLR_CH17_Disabled (0UL) /*!< Read: channel disabled */ -#define PPI_CHENCLR_CH17_Enabled (1UL) /*!< Read: channel enabled */ -#define PPI_CHENCLR_CH17_Clear (1UL) /*!< Write: disable channel */ - -/* Bit 16 : Channel 16 enable clear register. Writing '0' has no effect */ -#define PPI_CHENCLR_CH16_Pos (16UL) /*!< Position of CH16 field. */ -#define PPI_CHENCLR_CH16_Msk (0x1UL << PPI_CHENCLR_CH16_Pos) /*!< Bit mask of CH16 field. */ -#define PPI_CHENCLR_CH16_Disabled (0UL) /*!< Read: channel disabled */ -#define PPI_CHENCLR_CH16_Enabled (1UL) /*!< Read: channel enabled */ -#define PPI_CHENCLR_CH16_Clear (1UL) /*!< Write: disable channel */ - -/* Bit 15 : Channel 15 enable clear register. Writing '0' has no effect */ -#define PPI_CHENCLR_CH15_Pos (15UL) /*!< Position of CH15 field. */ -#define PPI_CHENCLR_CH15_Msk (0x1UL << PPI_CHENCLR_CH15_Pos) /*!< Bit mask of CH15 field. */ -#define PPI_CHENCLR_CH15_Disabled (0UL) /*!< Read: channel disabled */ -#define PPI_CHENCLR_CH15_Enabled (1UL) /*!< Read: channel enabled */ -#define PPI_CHENCLR_CH15_Clear (1UL) /*!< Write: disable channel */ - -/* Bit 14 : Channel 14 enable clear register. Writing '0' has no effect */ -#define PPI_CHENCLR_CH14_Pos (14UL) /*!< Position of CH14 field. */ -#define PPI_CHENCLR_CH14_Msk (0x1UL << PPI_CHENCLR_CH14_Pos) /*!< Bit mask of CH14 field. */ -#define PPI_CHENCLR_CH14_Disabled (0UL) /*!< Read: channel disabled */ -#define PPI_CHENCLR_CH14_Enabled (1UL) /*!< Read: channel enabled */ -#define PPI_CHENCLR_CH14_Clear (1UL) /*!< Write: disable channel */ - -/* Bit 13 : Channel 13 enable clear register. Writing '0' has no effect */ -#define PPI_CHENCLR_CH13_Pos (13UL) /*!< Position of CH13 field. */ -#define PPI_CHENCLR_CH13_Msk (0x1UL << PPI_CHENCLR_CH13_Pos) /*!< Bit mask of CH13 field. */ -#define PPI_CHENCLR_CH13_Disabled (0UL) /*!< Read: channel disabled */ -#define PPI_CHENCLR_CH13_Enabled (1UL) /*!< Read: channel enabled */ -#define PPI_CHENCLR_CH13_Clear (1UL) /*!< Write: disable channel */ - -/* Bit 12 : Channel 12 enable clear register. Writing '0' has no effect */ -#define PPI_CHENCLR_CH12_Pos (12UL) /*!< Position of CH12 field. */ -#define PPI_CHENCLR_CH12_Msk (0x1UL << PPI_CHENCLR_CH12_Pos) /*!< Bit mask of CH12 field. */ -#define PPI_CHENCLR_CH12_Disabled (0UL) /*!< Read: channel disabled */ -#define PPI_CHENCLR_CH12_Enabled (1UL) /*!< Read: channel enabled */ -#define PPI_CHENCLR_CH12_Clear (1UL) /*!< Write: disable channel */ - -/* Bit 11 : Channel 11 enable clear register. Writing '0' has no effect */ -#define PPI_CHENCLR_CH11_Pos (11UL) /*!< Position of CH11 field. */ -#define PPI_CHENCLR_CH11_Msk (0x1UL << PPI_CHENCLR_CH11_Pos) /*!< Bit mask of CH11 field. */ -#define PPI_CHENCLR_CH11_Disabled (0UL) /*!< Read: channel disabled */ -#define PPI_CHENCLR_CH11_Enabled (1UL) /*!< Read: channel enabled */ -#define PPI_CHENCLR_CH11_Clear (1UL) /*!< Write: disable channel */ - -/* Bit 10 : Channel 10 enable clear register. Writing '0' has no effect */ -#define PPI_CHENCLR_CH10_Pos (10UL) /*!< Position of CH10 field. */ -#define PPI_CHENCLR_CH10_Msk (0x1UL << PPI_CHENCLR_CH10_Pos) /*!< Bit mask of CH10 field. */ -#define PPI_CHENCLR_CH10_Disabled (0UL) /*!< Read: channel disabled */ -#define PPI_CHENCLR_CH10_Enabled (1UL) /*!< Read: channel enabled */ -#define PPI_CHENCLR_CH10_Clear (1UL) /*!< Write: disable channel */ - -/* Bit 9 : Channel 9 enable clear register. Writing '0' has no effect */ +/* Bit 9 : Channel 9 enable clear register. Writing '0' has no effect. */ #define PPI_CHENCLR_CH9_Pos (9UL) /*!< Position of CH9 field. */ #define PPI_CHENCLR_CH9_Msk (0x1UL << PPI_CHENCLR_CH9_Pos) /*!< Bit mask of CH9 field. */ #define PPI_CHENCLR_CH9_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENCLR_CH9_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENCLR_CH9_Clear (1UL) /*!< Write: disable channel */ -/* Bit 8 : Channel 8 enable clear register. Writing '0' has no effect */ +/* Bit 8 : Channel 8 enable clear register. Writing '0' has no effect. */ #define PPI_CHENCLR_CH8_Pos (8UL) /*!< Position of CH8 field. */ #define PPI_CHENCLR_CH8_Msk (0x1UL << PPI_CHENCLR_CH8_Pos) /*!< Bit mask of CH8 field. */ #define PPI_CHENCLR_CH8_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENCLR_CH8_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENCLR_CH8_Clear (1UL) /*!< Write: disable channel */ -/* Bit 7 : Channel 7 enable clear register. Writing '0' has no effect */ +/* Bit 7 : Channel 7 enable clear register. Writing '0' has no effect. */ #define PPI_CHENCLR_CH7_Pos (7UL) /*!< Position of CH7 field. */ #define PPI_CHENCLR_CH7_Msk (0x1UL << PPI_CHENCLR_CH7_Pos) /*!< Bit mask of CH7 field. */ #define PPI_CHENCLR_CH7_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENCLR_CH7_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENCLR_CH7_Clear (1UL) /*!< Write: disable channel */ -/* Bit 6 : Channel 6 enable clear register. Writing '0' has no effect */ +/* Bit 6 : Channel 6 enable clear register. Writing '0' has no effect. */ #define PPI_CHENCLR_CH6_Pos (6UL) /*!< Position of CH6 field. */ #define PPI_CHENCLR_CH6_Msk (0x1UL << PPI_CHENCLR_CH6_Pos) /*!< Bit mask of CH6 field. */ #define PPI_CHENCLR_CH6_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENCLR_CH6_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENCLR_CH6_Clear (1UL) /*!< Write: disable channel */ -/* Bit 5 : Channel 5 enable clear register. Writing '0' has no effect */ +/* Bit 5 : Channel 5 enable clear register. Writing '0' has no effect. */ #define PPI_CHENCLR_CH5_Pos (5UL) /*!< Position of CH5 field. */ #define PPI_CHENCLR_CH5_Msk (0x1UL << PPI_CHENCLR_CH5_Pos) /*!< Bit mask of CH5 field. */ #define PPI_CHENCLR_CH5_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENCLR_CH5_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENCLR_CH5_Clear (1UL) /*!< Write: disable channel */ -/* Bit 4 : Channel 4 enable clear register. Writing '0' has no effect */ +/* Bit 4 : Channel 4 enable clear register. Writing '0' has no effect. */ #define PPI_CHENCLR_CH4_Pos (4UL) /*!< Position of CH4 field. */ #define PPI_CHENCLR_CH4_Msk (0x1UL << PPI_CHENCLR_CH4_Pos) /*!< Bit mask of CH4 field. */ #define PPI_CHENCLR_CH4_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENCLR_CH4_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENCLR_CH4_Clear (1UL) /*!< Write: disable channel */ -/* Bit 3 : Channel 3 enable clear register. Writing '0' has no effect */ +/* Bit 3 : Channel 3 enable clear register. Writing '0' has no effect. */ #define PPI_CHENCLR_CH3_Pos (3UL) /*!< Position of CH3 field. */ #define PPI_CHENCLR_CH3_Msk (0x1UL << PPI_CHENCLR_CH3_Pos) /*!< Bit mask of CH3 field. */ #define PPI_CHENCLR_CH3_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENCLR_CH3_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENCLR_CH3_Clear (1UL) /*!< Write: disable channel */ -/* Bit 2 : Channel 2 enable clear register. Writing '0' has no effect */ +/* Bit 2 : Channel 2 enable clear register. Writing '0' has no effect. */ #define PPI_CHENCLR_CH2_Pos (2UL) /*!< Position of CH2 field. */ #define PPI_CHENCLR_CH2_Msk (0x1UL << PPI_CHENCLR_CH2_Pos) /*!< Bit mask of CH2 field. */ #define PPI_CHENCLR_CH2_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENCLR_CH2_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENCLR_CH2_Clear (1UL) /*!< Write: disable channel */ -/* Bit 1 : Channel 1 enable clear register. Writing '0' has no effect */ +/* Bit 1 : Channel 1 enable clear register. Writing '0' has no effect. */ #define PPI_CHENCLR_CH1_Pos (1UL) /*!< Position of CH1 field. */ #define PPI_CHENCLR_CH1_Msk (0x1UL << PPI_CHENCLR_CH1_Pos) /*!< Bit mask of CH1 field. */ #define PPI_CHENCLR_CH1_Disabled (0UL) /*!< Read: channel disabled */ #define PPI_CHENCLR_CH1_Enabled (1UL) /*!< Read: channel enabled */ #define PPI_CHENCLR_CH1_Clear (1UL) /*!< Write: disable channel */ -/* Bit 0 : Channel 0 enable clear register. Writing '0' has no effect */ +/* Bit 0 : Channel 0 enable clear register. Writing '0' has no effect. */ #define PPI_CHENCLR_CH0_Pos (0UL) /*!< Position of CH0 field. */ #define PPI_CHENCLR_CH0_Msk (0x1UL << PPI_CHENCLR_CH0_Pos) /*!< Bit mask of CH0 field. */ #define PPI_CHENCLR_CH0_Disabled (0UL) /*!< Read: channel disabled */ @@ -4549,14 +4349,14 @@ POSSIBILITY OF SUCH DAMAGE. #define PPI_CHENCLR_CH0_Clear (1UL) /*!< Write: disable channel */ /* Register: PPI_CH_EEP */ -/* Description: Description cluster: Channel n event end-point */ +/* Description: Description cluster: Channel n event endpoint */ /* Bits 31..0 : Pointer to event register. Accepts only addresses to registers from the Event group. */ #define PPI_CH_EEP_EEP_Pos (0UL) /*!< Position of EEP field. */ #define PPI_CH_EEP_EEP_Msk (0xFFFFFFFFUL << PPI_CH_EEP_EEP_Pos) /*!< Bit mask of EEP field. */ /* Register: PPI_CH_TEP */ -/* Description: Description cluster: Channel n task end-point */ +/* Description: Description cluster: Channel n task endpoint */ /* Bits 31..0 : Pointer to task register. Accepts only addresses to registers from the Task group. */ #define PPI_CH_TEP_TEP_Pos (0UL) /*!< Position of TEP field. */ @@ -4637,66 +4437,6 @@ POSSIBILITY OF SUCH DAMAGE. #define PPI_CHG_CH20_Excluded (0UL) /*!< Exclude */ #define PPI_CHG_CH20_Included (1UL) /*!< Include */ -/* Bit 19 : Include or exclude channel 19 */ -#define PPI_CHG_CH19_Pos (19UL) /*!< Position of CH19 field. */ -#define PPI_CHG_CH19_Msk (0x1UL << PPI_CHG_CH19_Pos) /*!< Bit mask of CH19 field. */ -#define PPI_CHG_CH19_Excluded (0UL) /*!< Exclude */ -#define PPI_CHG_CH19_Included (1UL) /*!< Include */ - -/* Bit 18 : Include or exclude channel 18 */ -#define PPI_CHG_CH18_Pos (18UL) /*!< Position of CH18 field. */ -#define PPI_CHG_CH18_Msk (0x1UL << PPI_CHG_CH18_Pos) /*!< Bit mask of CH18 field. */ -#define PPI_CHG_CH18_Excluded (0UL) /*!< Exclude */ -#define PPI_CHG_CH18_Included (1UL) /*!< Include */ - -/* Bit 17 : Include or exclude channel 17 */ -#define PPI_CHG_CH17_Pos (17UL) /*!< Position of CH17 field. */ -#define PPI_CHG_CH17_Msk (0x1UL << PPI_CHG_CH17_Pos) /*!< Bit mask of CH17 field. */ -#define PPI_CHG_CH17_Excluded (0UL) /*!< Exclude */ -#define PPI_CHG_CH17_Included (1UL) /*!< Include */ - -/* Bit 16 : Include or exclude channel 16 */ -#define PPI_CHG_CH16_Pos (16UL) /*!< Position of CH16 field. */ -#define PPI_CHG_CH16_Msk (0x1UL << PPI_CHG_CH16_Pos) /*!< Bit mask of CH16 field. */ -#define PPI_CHG_CH16_Excluded (0UL) /*!< Exclude */ -#define PPI_CHG_CH16_Included (1UL) /*!< Include */ - -/* Bit 15 : Include or exclude channel 15 */ -#define PPI_CHG_CH15_Pos (15UL) /*!< Position of CH15 field. */ -#define PPI_CHG_CH15_Msk (0x1UL << PPI_CHG_CH15_Pos) /*!< Bit mask of CH15 field. */ -#define PPI_CHG_CH15_Excluded (0UL) /*!< Exclude */ -#define PPI_CHG_CH15_Included (1UL) /*!< Include */ - -/* Bit 14 : Include or exclude channel 14 */ -#define PPI_CHG_CH14_Pos (14UL) /*!< Position of CH14 field. */ -#define PPI_CHG_CH14_Msk (0x1UL << PPI_CHG_CH14_Pos) /*!< Bit mask of CH14 field. */ -#define PPI_CHG_CH14_Excluded (0UL) /*!< Exclude */ -#define PPI_CHG_CH14_Included (1UL) /*!< Include */ - -/* Bit 13 : Include or exclude channel 13 */ -#define PPI_CHG_CH13_Pos (13UL) /*!< Position of CH13 field. */ -#define PPI_CHG_CH13_Msk (0x1UL << PPI_CHG_CH13_Pos) /*!< Bit mask of CH13 field. */ -#define PPI_CHG_CH13_Excluded (0UL) /*!< Exclude */ -#define PPI_CHG_CH13_Included (1UL) /*!< Include */ - -/* Bit 12 : Include or exclude channel 12 */ -#define PPI_CHG_CH12_Pos (12UL) /*!< Position of CH12 field. */ -#define PPI_CHG_CH12_Msk (0x1UL << PPI_CHG_CH12_Pos) /*!< Bit mask of CH12 field. */ -#define PPI_CHG_CH12_Excluded (0UL) /*!< Exclude */ -#define PPI_CHG_CH12_Included (1UL) /*!< Include */ - -/* Bit 11 : Include or exclude channel 11 */ -#define PPI_CHG_CH11_Pos (11UL) /*!< Position of CH11 field. */ -#define PPI_CHG_CH11_Msk (0x1UL << PPI_CHG_CH11_Pos) /*!< Bit mask of CH11 field. */ -#define PPI_CHG_CH11_Excluded (0UL) /*!< Exclude */ -#define PPI_CHG_CH11_Included (1UL) /*!< Include */ - -/* Bit 10 : Include or exclude channel 10 */ -#define PPI_CHG_CH10_Pos (10UL) /*!< Position of CH10 field. */ -#define PPI_CHG_CH10_Msk (0x1UL << PPI_CHG_CH10_Pos) /*!< Bit mask of CH10 field. */ -#define PPI_CHG_CH10_Excluded (0UL) /*!< Exclude */ -#define PPI_CHG_CH10_Included (1UL) /*!< Include */ - /* Bit 9 : Include or exclude channel 9 */ #define PPI_CHG_CH9_Pos (9UL) /*!< Position of CH9 field. */ #define PPI_CHG_CH9_Msk (0x1UL << PPI_CHG_CH9_Pos) /*!< Bit mask of CH9 field. */ @@ -4758,13 +4498,365 @@ POSSIBILITY OF SUCH DAMAGE. #define PPI_CHG_CH0_Included (1UL) /*!< Include */ /* Register: PPI_FORK_TEP */ -/* Description: Description cluster: Channel n task end-point */ +/* Description: Description cluster: Channel n task endpoint */ /* Bits 31..0 : Pointer to task register */ #define PPI_FORK_TEP_TEP_Pos (0UL) /*!< Position of TEP field. */ #define PPI_FORK_TEP_TEP_Msk (0xFFFFFFFFUL << PPI_FORK_TEP_TEP_Pos) /*!< Bit mask of TEP field. */ +/* Peripheral: QDEC */ +/* Description: Quadrature Decoder */ + +/* Register: QDEC_TASKS_START */ +/* Description: Task starting the quadrature decoder */ + +/* Bit 0 : Task starting the quadrature decoder */ +#define QDEC_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */ +#define QDEC_TASKS_START_TASKS_START_Msk (0x1UL << QDEC_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */ +#define QDEC_TASKS_START_TASKS_START_Trigger (1UL) /*!< Trigger task */ + +/* Register: QDEC_TASKS_STOP */ +/* Description: Task stopping the quadrature decoder */ + +/* Bit 0 : Task stopping the quadrature decoder */ +#define QDEC_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */ +#define QDEC_TASKS_STOP_TASKS_STOP_Msk (0x1UL << QDEC_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */ +#define QDEC_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */ + +/* Register: QDEC_TASKS_READCLRACC */ +/* Description: Read and clear ACC and ACCDBL */ + +/* Bit 0 : Read and clear ACC and ACCDBL */ +#define QDEC_TASKS_READCLRACC_TASKS_READCLRACC_Pos (0UL) /*!< Position of TASKS_READCLRACC field. */ +#define QDEC_TASKS_READCLRACC_TASKS_READCLRACC_Msk (0x1UL << QDEC_TASKS_READCLRACC_TASKS_READCLRACC_Pos) /*!< Bit mask of TASKS_READCLRACC field. */ +#define QDEC_TASKS_READCLRACC_TASKS_READCLRACC_Trigger (1UL) /*!< Trigger task */ + +/* Register: QDEC_TASKS_RDCLRACC */ +/* Description: Read and clear ACC */ + +/* Bit 0 : Read and clear ACC */ +#define QDEC_TASKS_RDCLRACC_TASKS_RDCLRACC_Pos (0UL) /*!< Position of TASKS_RDCLRACC field. */ +#define QDEC_TASKS_RDCLRACC_TASKS_RDCLRACC_Msk (0x1UL << QDEC_TASKS_RDCLRACC_TASKS_RDCLRACC_Pos) /*!< Bit mask of TASKS_RDCLRACC field. */ +#define QDEC_TASKS_RDCLRACC_TASKS_RDCLRACC_Trigger (1UL) /*!< Trigger task */ + +/* Register: QDEC_TASKS_RDCLRDBL */ +/* Description: Read and clear ACCDBL */ + +/* Bit 0 : Read and clear ACCDBL */ +#define QDEC_TASKS_RDCLRDBL_TASKS_RDCLRDBL_Pos (0UL) /*!< Position of TASKS_RDCLRDBL field. */ +#define QDEC_TASKS_RDCLRDBL_TASKS_RDCLRDBL_Msk (0x1UL << QDEC_TASKS_RDCLRDBL_TASKS_RDCLRDBL_Pos) /*!< Bit mask of TASKS_RDCLRDBL field. */ +#define QDEC_TASKS_RDCLRDBL_TASKS_RDCLRDBL_Trigger (1UL) /*!< Trigger task */ + +/* Register: QDEC_EVENTS_SAMPLERDY */ +/* Description: Event being generated for every new sample value written to the SAMPLE register */ + +/* Bit 0 : Event being generated for every new sample value written to the SAMPLE register */ +#define QDEC_EVENTS_SAMPLERDY_EVENTS_SAMPLERDY_Pos (0UL) /*!< Position of EVENTS_SAMPLERDY field. */ +#define QDEC_EVENTS_SAMPLERDY_EVENTS_SAMPLERDY_Msk (0x1UL << QDEC_EVENTS_SAMPLERDY_EVENTS_SAMPLERDY_Pos) /*!< Bit mask of EVENTS_SAMPLERDY field. */ +#define QDEC_EVENTS_SAMPLERDY_EVENTS_SAMPLERDY_NotGenerated (0UL) /*!< Event not generated */ +#define QDEC_EVENTS_SAMPLERDY_EVENTS_SAMPLERDY_Generated (1UL) /*!< Event generated */ + +/* Register: QDEC_EVENTS_REPORTRDY */ +/* Description: Non-null report ready */ + +/* Bit 0 : Non-null report ready */ +#define QDEC_EVENTS_REPORTRDY_EVENTS_REPORTRDY_Pos (0UL) /*!< Position of EVENTS_REPORTRDY field. */ +#define QDEC_EVENTS_REPORTRDY_EVENTS_REPORTRDY_Msk (0x1UL << QDEC_EVENTS_REPORTRDY_EVENTS_REPORTRDY_Pos) /*!< Bit mask of EVENTS_REPORTRDY field. */ +#define QDEC_EVENTS_REPORTRDY_EVENTS_REPORTRDY_NotGenerated (0UL) /*!< Event not generated */ +#define QDEC_EVENTS_REPORTRDY_EVENTS_REPORTRDY_Generated (1UL) /*!< Event generated */ + +/* Register: QDEC_EVENTS_ACCOF */ +/* Description: ACC or ACCDBL register overflow */ + +/* Bit 0 : ACC or ACCDBL register overflow */ +#define QDEC_EVENTS_ACCOF_EVENTS_ACCOF_Pos (0UL) /*!< Position of EVENTS_ACCOF field. */ +#define QDEC_EVENTS_ACCOF_EVENTS_ACCOF_Msk (0x1UL << QDEC_EVENTS_ACCOF_EVENTS_ACCOF_Pos) /*!< Bit mask of EVENTS_ACCOF field. */ +#define QDEC_EVENTS_ACCOF_EVENTS_ACCOF_NotGenerated (0UL) /*!< Event not generated */ +#define QDEC_EVENTS_ACCOF_EVENTS_ACCOF_Generated (1UL) /*!< Event generated */ + +/* Register: QDEC_EVENTS_DBLRDY */ +/* Description: Double displacement(s) detected */ + +/* Bit 0 : Double displacement(s) detected */ +#define QDEC_EVENTS_DBLRDY_EVENTS_DBLRDY_Pos (0UL) /*!< Position of EVENTS_DBLRDY field. */ +#define QDEC_EVENTS_DBLRDY_EVENTS_DBLRDY_Msk (0x1UL << QDEC_EVENTS_DBLRDY_EVENTS_DBLRDY_Pos) /*!< Bit mask of EVENTS_DBLRDY field. */ +#define QDEC_EVENTS_DBLRDY_EVENTS_DBLRDY_NotGenerated (0UL) /*!< Event not generated */ +#define QDEC_EVENTS_DBLRDY_EVENTS_DBLRDY_Generated (1UL) /*!< Event generated */ + +/* Register: QDEC_EVENTS_STOPPED */ +/* Description: QDEC has been stopped */ + +/* Bit 0 : QDEC has been stopped */ +#define QDEC_EVENTS_STOPPED_EVENTS_STOPPED_Pos (0UL) /*!< Position of EVENTS_STOPPED field. */ +#define QDEC_EVENTS_STOPPED_EVENTS_STOPPED_Msk (0x1UL << QDEC_EVENTS_STOPPED_EVENTS_STOPPED_Pos) /*!< Bit mask of EVENTS_STOPPED field. */ +#define QDEC_EVENTS_STOPPED_EVENTS_STOPPED_NotGenerated (0UL) /*!< Event not generated */ +#define QDEC_EVENTS_STOPPED_EVENTS_STOPPED_Generated (1UL) /*!< Event generated */ + +/* Register: QDEC_SHORTS */ +/* Description: Shortcuts between local events and tasks */ + +/* Bit 6 : Shortcut between event SAMPLERDY and task READCLRACC */ +#define QDEC_SHORTS_SAMPLERDY_READCLRACC_Pos (6UL) /*!< Position of SAMPLERDY_READCLRACC field. */ +#define QDEC_SHORTS_SAMPLERDY_READCLRACC_Msk (0x1UL << QDEC_SHORTS_SAMPLERDY_READCLRACC_Pos) /*!< Bit mask of SAMPLERDY_READCLRACC field. */ +#define QDEC_SHORTS_SAMPLERDY_READCLRACC_Disabled (0UL) /*!< Disable shortcut */ +#define QDEC_SHORTS_SAMPLERDY_READCLRACC_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 5 : Shortcut between event DBLRDY and task STOP */ +#define QDEC_SHORTS_DBLRDY_STOP_Pos (5UL) /*!< Position of DBLRDY_STOP field. */ +#define QDEC_SHORTS_DBLRDY_STOP_Msk (0x1UL << QDEC_SHORTS_DBLRDY_STOP_Pos) /*!< Bit mask of DBLRDY_STOP field. */ +#define QDEC_SHORTS_DBLRDY_STOP_Disabled (0UL) /*!< Disable shortcut */ +#define QDEC_SHORTS_DBLRDY_STOP_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 4 : Shortcut between event DBLRDY and task RDCLRDBL */ +#define QDEC_SHORTS_DBLRDY_RDCLRDBL_Pos (4UL) /*!< Position of DBLRDY_RDCLRDBL field. */ +#define QDEC_SHORTS_DBLRDY_RDCLRDBL_Msk (0x1UL << QDEC_SHORTS_DBLRDY_RDCLRDBL_Pos) /*!< Bit mask of DBLRDY_RDCLRDBL field. */ +#define QDEC_SHORTS_DBLRDY_RDCLRDBL_Disabled (0UL) /*!< Disable shortcut */ +#define QDEC_SHORTS_DBLRDY_RDCLRDBL_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 3 : Shortcut between event REPORTRDY and task STOP */ +#define QDEC_SHORTS_REPORTRDY_STOP_Pos (3UL) /*!< Position of REPORTRDY_STOP field. */ +#define QDEC_SHORTS_REPORTRDY_STOP_Msk (0x1UL << QDEC_SHORTS_REPORTRDY_STOP_Pos) /*!< Bit mask of REPORTRDY_STOP field. */ +#define QDEC_SHORTS_REPORTRDY_STOP_Disabled (0UL) /*!< Disable shortcut */ +#define QDEC_SHORTS_REPORTRDY_STOP_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 2 : Shortcut between event REPORTRDY and task RDCLRACC */ +#define QDEC_SHORTS_REPORTRDY_RDCLRACC_Pos (2UL) /*!< Position of REPORTRDY_RDCLRACC field. */ +#define QDEC_SHORTS_REPORTRDY_RDCLRACC_Msk (0x1UL << QDEC_SHORTS_REPORTRDY_RDCLRACC_Pos) /*!< Bit mask of REPORTRDY_RDCLRACC field. */ +#define QDEC_SHORTS_REPORTRDY_RDCLRACC_Disabled (0UL) /*!< Disable shortcut */ +#define QDEC_SHORTS_REPORTRDY_RDCLRACC_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 1 : Shortcut between event SAMPLERDY and task STOP */ +#define QDEC_SHORTS_SAMPLERDY_STOP_Pos (1UL) /*!< Position of SAMPLERDY_STOP field. */ +#define QDEC_SHORTS_SAMPLERDY_STOP_Msk (0x1UL << QDEC_SHORTS_SAMPLERDY_STOP_Pos) /*!< Bit mask of SAMPLERDY_STOP field. */ +#define QDEC_SHORTS_SAMPLERDY_STOP_Disabled (0UL) /*!< Disable shortcut */ +#define QDEC_SHORTS_SAMPLERDY_STOP_Enabled (1UL) /*!< Enable shortcut */ + +/* Bit 0 : Shortcut between event REPORTRDY and task READCLRACC */ +#define QDEC_SHORTS_REPORTRDY_READCLRACC_Pos (0UL) /*!< Position of REPORTRDY_READCLRACC field. */ +#define QDEC_SHORTS_REPORTRDY_READCLRACC_Msk (0x1UL << QDEC_SHORTS_REPORTRDY_READCLRACC_Pos) /*!< Bit mask of REPORTRDY_READCLRACC field. */ +#define QDEC_SHORTS_REPORTRDY_READCLRACC_Disabled (0UL) /*!< Disable shortcut */ +#define QDEC_SHORTS_REPORTRDY_READCLRACC_Enabled (1UL) /*!< Enable shortcut */ + +/* Register: QDEC_INTENSET */ +/* Description: Enable interrupt */ + +/* Bit 4 : Write '1' to enable interrupt for event STOPPED */ +#define QDEC_INTENSET_STOPPED_Pos (4UL) /*!< Position of STOPPED field. */ +#define QDEC_INTENSET_STOPPED_Msk (0x1UL << QDEC_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ +#define QDEC_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */ +#define QDEC_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */ +#define QDEC_INTENSET_STOPPED_Set (1UL) /*!< Enable */ + +/* Bit 3 : Write '1' to enable interrupt for event DBLRDY */ +#define QDEC_INTENSET_DBLRDY_Pos (3UL) /*!< Position of DBLRDY field. */ +#define QDEC_INTENSET_DBLRDY_Msk (0x1UL << QDEC_INTENSET_DBLRDY_Pos) /*!< Bit mask of DBLRDY field. */ +#define QDEC_INTENSET_DBLRDY_Disabled (0UL) /*!< Read: Disabled */ +#define QDEC_INTENSET_DBLRDY_Enabled (1UL) /*!< Read: Enabled */ +#define QDEC_INTENSET_DBLRDY_Set (1UL) /*!< Enable */ + +/* Bit 2 : Write '1' to enable interrupt for event ACCOF */ +#define QDEC_INTENSET_ACCOF_Pos (2UL) /*!< Position of ACCOF field. */ +#define QDEC_INTENSET_ACCOF_Msk (0x1UL << QDEC_INTENSET_ACCOF_Pos) /*!< Bit mask of ACCOF field. */ +#define QDEC_INTENSET_ACCOF_Disabled (0UL) /*!< Read: Disabled */ +#define QDEC_INTENSET_ACCOF_Enabled (1UL) /*!< Read: Enabled */ +#define QDEC_INTENSET_ACCOF_Set (1UL) /*!< Enable */ + +/* Bit 1 : Write '1' to enable interrupt for event REPORTRDY */ +#define QDEC_INTENSET_REPORTRDY_Pos (1UL) /*!< Position of REPORTRDY field. */ +#define QDEC_INTENSET_REPORTRDY_Msk (0x1UL << QDEC_INTENSET_REPORTRDY_Pos) /*!< Bit mask of REPORTRDY field. */ +#define QDEC_INTENSET_REPORTRDY_Disabled (0UL) /*!< Read: Disabled */ +#define QDEC_INTENSET_REPORTRDY_Enabled (1UL) /*!< Read: Enabled */ +#define QDEC_INTENSET_REPORTRDY_Set (1UL) /*!< Enable */ + +/* Bit 0 : Write '1' to enable interrupt for event SAMPLERDY */ +#define QDEC_INTENSET_SAMPLERDY_Pos (0UL) /*!< Position of SAMPLERDY field. */ +#define QDEC_INTENSET_SAMPLERDY_Msk (0x1UL << QDEC_INTENSET_SAMPLERDY_Pos) /*!< Bit mask of SAMPLERDY field. */ +#define QDEC_INTENSET_SAMPLERDY_Disabled (0UL) /*!< Read: Disabled */ +#define QDEC_INTENSET_SAMPLERDY_Enabled (1UL) /*!< Read: Enabled */ +#define QDEC_INTENSET_SAMPLERDY_Set (1UL) /*!< Enable */ + +/* Register: QDEC_INTENCLR */ +/* Description: Disable interrupt */ + +/* Bit 4 : Write '1' to disable interrupt for event STOPPED */ +#define QDEC_INTENCLR_STOPPED_Pos (4UL) /*!< Position of STOPPED field. */ +#define QDEC_INTENCLR_STOPPED_Msk (0x1UL << QDEC_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ +#define QDEC_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */ +#define QDEC_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */ +#define QDEC_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */ + +/* Bit 3 : Write '1' to disable interrupt for event DBLRDY */ +#define QDEC_INTENCLR_DBLRDY_Pos (3UL) /*!< Position of DBLRDY field. */ +#define QDEC_INTENCLR_DBLRDY_Msk (0x1UL << QDEC_INTENCLR_DBLRDY_Pos) /*!< Bit mask of DBLRDY field. */ +#define QDEC_INTENCLR_DBLRDY_Disabled (0UL) /*!< Read: Disabled */ +#define QDEC_INTENCLR_DBLRDY_Enabled (1UL) /*!< Read: Enabled */ +#define QDEC_INTENCLR_DBLRDY_Clear (1UL) /*!< Disable */ + +/* Bit 2 : Write '1' to disable interrupt for event ACCOF */ +#define QDEC_INTENCLR_ACCOF_Pos (2UL) /*!< Position of ACCOF field. */ +#define QDEC_INTENCLR_ACCOF_Msk (0x1UL << QDEC_INTENCLR_ACCOF_Pos) /*!< Bit mask of ACCOF field. */ +#define QDEC_INTENCLR_ACCOF_Disabled (0UL) /*!< Read: Disabled */ +#define QDEC_INTENCLR_ACCOF_Enabled (1UL) /*!< Read: Enabled */ +#define QDEC_INTENCLR_ACCOF_Clear (1UL) /*!< Disable */ + +/* Bit 1 : Write '1' to disable interrupt for event REPORTRDY */ +#define QDEC_INTENCLR_REPORTRDY_Pos (1UL) /*!< Position of REPORTRDY field. */ +#define QDEC_INTENCLR_REPORTRDY_Msk (0x1UL << QDEC_INTENCLR_REPORTRDY_Pos) /*!< Bit mask of REPORTRDY field. */ +#define QDEC_INTENCLR_REPORTRDY_Disabled (0UL) /*!< Read: Disabled */ +#define QDEC_INTENCLR_REPORTRDY_Enabled (1UL) /*!< Read: Enabled */ +#define QDEC_INTENCLR_REPORTRDY_Clear (1UL) /*!< Disable */ + +/* Bit 0 : Write '1' to disable interrupt for event SAMPLERDY */ +#define QDEC_INTENCLR_SAMPLERDY_Pos (0UL) /*!< Position of SAMPLERDY field. */ +#define QDEC_INTENCLR_SAMPLERDY_Msk (0x1UL << QDEC_INTENCLR_SAMPLERDY_Pos) /*!< Bit mask of SAMPLERDY field. */ +#define QDEC_INTENCLR_SAMPLERDY_Disabled (0UL) /*!< Read: Disabled */ +#define QDEC_INTENCLR_SAMPLERDY_Enabled (1UL) /*!< Read: Enabled */ +#define QDEC_INTENCLR_SAMPLERDY_Clear (1UL) /*!< Disable */ + +/* Register: QDEC_ENABLE */ +/* Description: Enable the quadrature decoder */ + +/* Bit 0 : Enable or disable the quadrature decoder */ +#define QDEC_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ +#define QDEC_ENABLE_ENABLE_Msk (0x1UL << QDEC_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ +#define QDEC_ENABLE_ENABLE_Disabled (0UL) /*!< Disable */ +#define QDEC_ENABLE_ENABLE_Enabled (1UL) /*!< Enable */ + +/* Register: QDEC_LEDPOL */ +/* Description: LED output pin polarity */ + +/* Bit 0 : LED output pin polarity */ +#define QDEC_LEDPOL_LEDPOL_Pos (0UL) /*!< Position of LEDPOL field. */ +#define QDEC_LEDPOL_LEDPOL_Msk (0x1UL << QDEC_LEDPOL_LEDPOL_Pos) /*!< Bit mask of LEDPOL field. */ +#define QDEC_LEDPOL_LEDPOL_ActiveLow (0UL) /*!< Led active on output pin low */ +#define QDEC_LEDPOL_LEDPOL_ActiveHigh (1UL) /*!< Led active on output pin high */ + +/* Register: QDEC_SAMPLEPER */ +/* Description: Sample period */ + +/* Bits 3..0 : Sample period. The SAMPLE register will be updated for every new sample */ +#define QDEC_SAMPLEPER_SAMPLEPER_Pos (0UL) /*!< Position of SAMPLEPER field. */ +#define QDEC_SAMPLEPER_SAMPLEPER_Msk (0xFUL << QDEC_SAMPLEPER_SAMPLEPER_Pos) /*!< Bit mask of SAMPLEPER field. */ +#define QDEC_SAMPLEPER_SAMPLEPER_128us (0UL) /*!< 128 us */ +#define QDEC_SAMPLEPER_SAMPLEPER_256us (1UL) /*!< 256 us */ +#define QDEC_SAMPLEPER_SAMPLEPER_512us (2UL) /*!< 512 us */ +#define QDEC_SAMPLEPER_SAMPLEPER_1024us (3UL) /*!< 1024 us */ +#define QDEC_SAMPLEPER_SAMPLEPER_2048us (4UL) /*!< 2048 us */ +#define QDEC_SAMPLEPER_SAMPLEPER_4096us (5UL) /*!< 4096 us */ +#define QDEC_SAMPLEPER_SAMPLEPER_8192us (6UL) /*!< 8192 us */ +#define QDEC_SAMPLEPER_SAMPLEPER_16384us (7UL) /*!< 16384 us */ +#define QDEC_SAMPLEPER_SAMPLEPER_32ms (8UL) /*!< 32768 us */ +#define QDEC_SAMPLEPER_SAMPLEPER_65ms (9UL) /*!< 65536 us */ +#define QDEC_SAMPLEPER_SAMPLEPER_131ms (10UL) /*!< 131072 us */ + +/* Register: QDEC_SAMPLE */ +/* Description: Motion sample value */ + +/* Bits 31..0 : Last motion sample */ +#define QDEC_SAMPLE_SAMPLE_Pos (0UL) /*!< Position of SAMPLE field. */ +#define QDEC_SAMPLE_SAMPLE_Msk (0xFFFFFFFFUL << QDEC_SAMPLE_SAMPLE_Pos) /*!< Bit mask of SAMPLE field. */ + +/* Register: QDEC_REPORTPER */ +/* Description: Number of samples to be taken before REPORTRDY and DBLRDY events can be generated */ + +/* Bits 3..0 : Specifies the number of samples to be accumulated in the ACC register before the REPORTRDY and DBLRDY events can be generated. */ +#define QDEC_REPORTPER_REPORTPER_Pos (0UL) /*!< Position of REPORTPER field. */ +#define QDEC_REPORTPER_REPORTPER_Msk (0xFUL << QDEC_REPORTPER_REPORTPER_Pos) /*!< Bit mask of REPORTPER field. */ +#define QDEC_REPORTPER_REPORTPER_10Smpl (0UL) /*!< 10 samples/report */ +#define QDEC_REPORTPER_REPORTPER_40Smpl (1UL) /*!< 40 samples/report */ +#define QDEC_REPORTPER_REPORTPER_80Smpl (2UL) /*!< 80 samples/report */ +#define QDEC_REPORTPER_REPORTPER_120Smpl (3UL) /*!< 120 samples/report */ +#define QDEC_REPORTPER_REPORTPER_160Smpl (4UL) /*!< 160 samples/report */ +#define QDEC_REPORTPER_REPORTPER_200Smpl (5UL) /*!< 200 samples/report */ +#define QDEC_REPORTPER_REPORTPER_240Smpl (6UL) /*!< 240 samples/report */ +#define QDEC_REPORTPER_REPORTPER_280Smpl (7UL) /*!< 280 samples/report */ +#define QDEC_REPORTPER_REPORTPER_1Smpl (8UL) /*!< 1 sample/report */ + +/* Register: QDEC_ACC */ +/* Description: Register accumulating the valid transitions */ + +/* Bits 31..0 : Register accumulating all valid samples (not double transition) read from the SAMPLE register. */ +#define QDEC_ACC_ACC_Pos (0UL) /*!< Position of ACC field. */ +#define QDEC_ACC_ACC_Msk (0xFFFFFFFFUL << QDEC_ACC_ACC_Pos) /*!< Bit mask of ACC field. */ + +/* Register: QDEC_ACCREAD */ +/* Description: Snapshot of the ACC register, updated by the READCLRACC or RDCLRACC task */ + +/* Bits 31..0 : Snapshot of the ACC register. */ +#define QDEC_ACCREAD_ACCREAD_Pos (0UL) /*!< Position of ACCREAD field. */ +#define QDEC_ACCREAD_ACCREAD_Msk (0xFFFFFFFFUL << QDEC_ACCREAD_ACCREAD_Pos) /*!< Bit mask of ACCREAD field. */ + +/* Register: QDEC_PSEL_LED */ +/* Description: Pin select for LED signal */ + +/* Bit 31 : Connection */ +#define QDEC_PSEL_LED_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define QDEC_PSEL_LED_CONNECT_Msk (0x1UL << QDEC_PSEL_LED_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define QDEC_PSEL_LED_CONNECT_Connected (0UL) /*!< Connect */ +#define QDEC_PSEL_LED_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bits 4..0 : Pin number */ +#define QDEC_PSEL_LED_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define QDEC_PSEL_LED_PIN_Msk (0x1FUL << QDEC_PSEL_LED_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* Register: QDEC_PSEL_A */ +/* Description: Pin select for A signal */ + +/* Bit 31 : Connection */ +#define QDEC_PSEL_A_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define QDEC_PSEL_A_CONNECT_Msk (0x1UL << QDEC_PSEL_A_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define QDEC_PSEL_A_CONNECT_Connected (0UL) /*!< Connect */ +#define QDEC_PSEL_A_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bits 4..0 : Pin number */ +#define QDEC_PSEL_A_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define QDEC_PSEL_A_PIN_Msk (0x1FUL << QDEC_PSEL_A_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* Register: QDEC_PSEL_B */ +/* Description: Pin select for B signal */ + +/* Bit 31 : Connection */ +#define QDEC_PSEL_B_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ +#define QDEC_PSEL_B_CONNECT_Msk (0x1UL << QDEC_PSEL_B_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ +#define QDEC_PSEL_B_CONNECT_Connected (0UL) /*!< Connect */ +#define QDEC_PSEL_B_CONNECT_Disconnected (1UL) /*!< Disconnect */ + +/* Bits 4..0 : Pin number */ +#define QDEC_PSEL_B_PIN_Pos (0UL) /*!< Position of PIN field. */ +#define QDEC_PSEL_B_PIN_Msk (0x1FUL << QDEC_PSEL_B_PIN_Pos) /*!< Bit mask of PIN field. */ + +/* Register: QDEC_DBFEN */ +/* Description: Enable input debounce filters */ + +/* Bit 0 : Enable input debounce filters */ +#define QDEC_DBFEN_DBFEN_Pos (0UL) /*!< Position of DBFEN field. */ +#define QDEC_DBFEN_DBFEN_Msk (0x1UL << QDEC_DBFEN_DBFEN_Pos) /*!< Bit mask of DBFEN field. */ +#define QDEC_DBFEN_DBFEN_Disabled (0UL) /*!< Debounce input filters disabled */ +#define QDEC_DBFEN_DBFEN_Enabled (1UL) /*!< Debounce input filters enabled */ + +/* Register: QDEC_LEDPRE */ +/* Description: Time period the LED is switched ON prior to sampling */ + +/* Bits 8..0 : Period in us the LED is switched on prior to sampling */ +#define QDEC_LEDPRE_LEDPRE_Pos (0UL) /*!< Position of LEDPRE field. */ +#define QDEC_LEDPRE_LEDPRE_Msk (0x1FFUL << QDEC_LEDPRE_LEDPRE_Pos) /*!< Bit mask of LEDPRE field. */ + +/* Register: QDEC_ACCDBL */ +/* Description: Register accumulating the number of detected double transitions */ + +/* Bits 3..0 : Register accumulating the number of detected double or illegal transitions. ( SAMPLE = 2 ). */ +#define QDEC_ACCDBL_ACCDBL_Pos (0UL) /*!< Position of ACCDBL field. */ +#define QDEC_ACCDBL_ACCDBL_Msk (0xFUL << QDEC_ACCDBL_ACCDBL_Pos) /*!< Bit mask of ACCDBL field. */ + +/* Register: QDEC_ACCDBLREAD */ +/* Description: Snapshot of the ACCDBL, updated by the READCLRACC or RDCLRDBL task */ + +/* Bits 3..0 : Snapshot of the ACCDBL register. This field is updated when the READCLRACC or RDCLRDBL task is triggered. */ +#define QDEC_ACCDBLREAD_ACCDBLREAD_Pos (0UL) /*!< Position of ACCDBLREAD field. */ +#define QDEC_ACCDBLREAD_ACCDBLREAD_Msk (0xFUL << QDEC_ACCDBLREAD_ACCDBLREAD_Pos) /*!< Bit mask of ACCDBLREAD field. */ + + /* Peripheral: RADIO */ /* Description: 2.4 GHz radio */ @@ -4957,19 +5049,10 @@ POSSIBILITY OF SUCH DAMAGE. #define RADIO_EVENTS_RXREADY_EVENTS_RXREADY_NotGenerated (0UL) /*!< Event not generated */ #define RADIO_EVENTS_RXREADY_EVENTS_RXREADY_Generated (1UL) /*!< Event generated */ -/* Register: RADIO_EVENTS_MHRMATCH */ -/* Description: MAC header match found */ - -/* Bit 0 : MAC header match found */ -#define RADIO_EVENTS_MHRMATCH_EVENTS_MHRMATCH_Pos (0UL) /*!< Position of EVENTS_MHRMATCH field. */ -#define RADIO_EVENTS_MHRMATCH_EVENTS_MHRMATCH_Msk (0x1UL << RADIO_EVENTS_MHRMATCH_EVENTS_MHRMATCH_Pos) /*!< Bit mask of EVENTS_MHRMATCH field. */ -#define RADIO_EVENTS_MHRMATCH_EVENTS_MHRMATCH_NotGenerated (0UL) /*!< Event not generated */ -#define RADIO_EVENTS_MHRMATCH_EVENTS_MHRMATCH_Generated (1UL) /*!< Event generated */ - /* Register: RADIO_EVENTS_PHYEND */ -/* Description: Generated when last bit is sent on air */ +/* Description: Generated when last bit is sent on air, or received from air */ -/* Bit 0 : Generated when last bit is sent on air */ +/* Bit 0 : Generated when last bit is sent on air, or received from air */ #define RADIO_EVENTS_PHYEND_EVENTS_PHYEND_Pos (0UL) /*!< Position of EVENTS_PHYEND field. */ #define RADIO_EVENTS_PHYEND_EVENTS_PHYEND_Msk (0x1UL << RADIO_EVENTS_PHYEND_EVENTS_PHYEND_Pos) /*!< Bit mask of EVENTS_PHYEND field. */ #define RADIO_EVENTS_PHYEND_EVENTS_PHYEND_NotGenerated (0UL) /*!< Event not generated */ @@ -5060,13 +5143,6 @@ POSSIBILITY OF SUCH DAMAGE. #define RADIO_INTENSET_PHYEND_Enabled (1UL) /*!< Read: Enabled */ #define RADIO_INTENSET_PHYEND_Set (1UL) /*!< Enable */ -/* Bit 23 : Write '1' to enable interrupt for event MHRMATCH */ -#define RADIO_INTENSET_MHRMATCH_Pos (23UL) /*!< Position of MHRMATCH field. */ -#define RADIO_INTENSET_MHRMATCH_Msk (0x1UL << RADIO_INTENSET_MHRMATCH_Pos) /*!< Bit mask of MHRMATCH field. */ -#define RADIO_INTENSET_MHRMATCH_Disabled (0UL) /*!< Read: Disabled */ -#define RADIO_INTENSET_MHRMATCH_Enabled (1UL) /*!< Read: Enabled */ -#define RADIO_INTENSET_MHRMATCH_Set (1UL) /*!< Enable */ - /* Bit 22 : Write '1' to enable interrupt for event RXREADY */ #define RADIO_INTENSET_RXREADY_Pos (22UL) /*!< Position of RXREADY field. */ #define RADIO_INTENSET_RXREADY_Msk (0x1UL << RADIO_INTENSET_RXREADY_Pos) /*!< Bit mask of RXREADY field. */ @@ -5168,13 +5244,6 @@ POSSIBILITY OF SUCH DAMAGE. #define RADIO_INTENCLR_PHYEND_Enabled (1UL) /*!< Read: Enabled */ #define RADIO_INTENCLR_PHYEND_Clear (1UL) /*!< Disable */ -/* Bit 23 : Write '1' to disable interrupt for event MHRMATCH */ -#define RADIO_INTENCLR_MHRMATCH_Pos (23UL) /*!< Position of MHRMATCH field. */ -#define RADIO_INTENCLR_MHRMATCH_Msk (0x1UL << RADIO_INTENCLR_MHRMATCH_Pos) /*!< Bit mask of MHRMATCH field. */ -#define RADIO_INTENCLR_MHRMATCH_Disabled (0UL) /*!< Read: Disabled */ -#define RADIO_INTENCLR_MHRMATCH_Enabled (1UL) /*!< Read: Enabled */ -#define RADIO_INTENCLR_MHRMATCH_Clear (1UL) /*!< Disable */ - /* Bit 22 : Write '1' to disable interrupt for event RXREADY */ #define RADIO_INTENCLR_RXREADY_Pos (22UL) /*!< Position of RXREADY field. */ #define RADIO_INTENCLR_RXREADY_Msk (0x1UL << RADIO_INTENCLR_RXREADY_Pos) /*!< Bit mask of RXREADY field. */ @@ -5315,7 +5384,7 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: RADIO_FREQUENCY */ /* Description: Frequency */ -/* Bit 8 : Channel map selection. */ +/* Bit 8 : Channel map selection */ #define RADIO_FREQUENCY_MAP_Pos (8UL) /*!< Position of MAP field. */ #define RADIO_FREQUENCY_MAP_Msk (0x1UL << RADIO_FREQUENCY_MAP_Pos) /*!< Bit mask of MAP field. */ #define RADIO_FREQUENCY_MAP_Default (0UL) /*!< Channel map between 2400 MHZ .. 2500 MHz */ @@ -5374,15 +5443,15 @@ POSSIBILITY OF SUCH DAMAGE. #define RADIO_PCNF0_S1INCL_Automatic (0UL) /*!< Include S1 field in RAM only if S1LEN > 0 */ #define RADIO_PCNF0_S1INCL_Include (1UL) /*!< Always include S1 field in RAM independent of S1LEN */ -/* Bits 19..16 : Length on air of S1 field in number of bits. */ +/* Bits 19..16 : Length on air of S1 field in number of bits */ #define RADIO_PCNF0_S1LEN_Pos (16UL) /*!< Position of S1LEN field. */ #define RADIO_PCNF0_S1LEN_Msk (0xFUL << RADIO_PCNF0_S1LEN_Pos) /*!< Bit mask of S1LEN field. */ -/* Bit 8 : Length on air of S0 field in number of bytes. */ +/* Bit 8 : Length on air of S0 field in number of bytes */ #define RADIO_PCNF0_S0LEN_Pos (8UL) /*!< Position of S0LEN field. */ #define RADIO_PCNF0_S0LEN_Msk (0x1UL << RADIO_PCNF0_S0LEN_Pos) /*!< Bit mask of S0LEN field. */ -/* Bits 3..0 : Length on air of LENGTH field in number of bits. */ +/* Bits 3..0 : Length on air of LENGTH field in number of bits */ #define RADIO_PCNF0_LFLEN_Pos (0UL) /*!< Position of LFLEN field. */ #define RADIO_PCNF0_LFLEN_Msk (0xFUL << RADIO_PCNF0_LFLEN_Pos) /*!< Bit mask of LFLEN field. */ @@ -5532,7 +5601,7 @@ POSSIBILITY OF SUCH DAMAGE. #define RADIO_CRCCNF_SKIPADDR_Include (0UL) /*!< CRC calculation includes address field */ #define RADIO_CRCCNF_SKIPADDR_Skip (1UL) /*!< CRC calculation does not include address field. The CRC calculation will start at the first byte after the address. */ -/* Bits 1..0 : CRC length in number of bytes. */ +/* Bits 1..0 : CRC length in number of bytes */ #define RADIO_CRCCNF_LEN_Pos (0UL) /*!< Position of LEN field. */ #define RADIO_CRCCNF_LEN_Msk (0x3UL << RADIO_CRCCNF_LEN_Pos) /*!< Bit mask of LEN field. */ #define RADIO_CRCCNF_LEN_Disabled (0UL) /*!< CRC length is zero and CRC calculation is disabled */ @@ -5557,14 +5626,14 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: RADIO_TIFS */ /* Description: Interframe spacing in us */ -/* Bits 9..0 : Interframe spacing in us */ +/* Bits 9..0 : Interframe spacing in us. */ #define RADIO_TIFS_TIFS_Pos (0UL) /*!< Position of TIFS field. */ #define RADIO_TIFS_TIFS_Msk (0x3FFUL << RADIO_TIFS_TIFS_Pos) /*!< Bit mask of TIFS field. */ /* Register: RADIO_RSSISAMPLE */ /* Description: RSSI sample */ -/* Bits 6..0 : RSSI sample */ +/* Bits 6..0 : RSSI sample. */ #define RADIO_RSSISAMPLE_RSSISAMPLE_Pos (0UL) /*!< Position of RSSISAMPLE field. */ #define RADIO_RSSISAMPLE_RSSISAMPLE_Msk (0x7FUL << RADIO_RSSISAMPLE_RSSISAMPLE_Pos) /*!< Bit mask of RSSISAMPLE field. */ @@ -5709,7 +5778,7 @@ POSSIBILITY OF SUCH DAMAGE. #define RADIO_MODECNF0_RU_Pos (0UL) /*!< Position of RU field. */ #define RADIO_MODECNF0_RU_Msk (0x1UL << RADIO_MODECNF0_RU_Pos) /*!< Bit mask of RU field. */ #define RADIO_MODECNF0_RU_Default (0UL) /*!< Default ramp-up time (tRXEN and tTXEN), compatible with firmware written for nRF51 */ -#define RADIO_MODECNF0_RU_Fast (1UL) /*!< Fast ramp-up (tRXEN,FAST and tTXEN,FAST), see electrical specification for more information */ +#define RADIO_MODECNF0_RU_Fast (1UL) /*!< Fast ramp-up (tRXEN,FAST and tTXEN,FAST), see electrical specifications for more information */ /* Register: RADIO_POWER */ /* Description: Peripheral power control */ @@ -6928,7 +6997,7 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: SPI_TXD */ /* Description: TXD register */ -/* Bits 7..0 : TX data to send. Double buffered */ +/* Bits 7..0 : TX data to send. Double buffered. */ #define SPI_TXD_TXD_Pos (0UL) /*!< Position of TXD field. */ #define SPI_TXD_TXD_Msk (0xFFUL << SPI_TXD_TXD_Pos) /*!< Bit mask of TXD field. */ @@ -7628,121 +7697,121 @@ POSSIBILITY OF SUCH DAMAGE. #define TEMP_TEMP_TEMP_Msk (0xFFFFFFFFUL << TEMP_TEMP_TEMP_Pos) /*!< Bit mask of TEMP field. */ /* Register: TEMP_A0 */ -/* Description: Slope of 1st piece wise linear function */ +/* Description: Slope of first piecewise linear function */ -/* Bits 11..0 : Slope of 1st piece wise linear function */ +/* Bits 11..0 : Slope of first piecewise linear function */ #define TEMP_A0_A0_Pos (0UL) /*!< Position of A0 field. */ #define TEMP_A0_A0_Msk (0xFFFUL << TEMP_A0_A0_Pos) /*!< Bit mask of A0 field. */ /* Register: TEMP_A1 */ -/* Description: Slope of 2nd piece wise linear function */ +/* Description: Slope of second piecewise linear function */ -/* Bits 11..0 : Slope of 2nd piece wise linear function */ +/* Bits 11..0 : Slope of second piecewise linear function */ #define TEMP_A1_A1_Pos (0UL) /*!< Position of A1 field. */ #define TEMP_A1_A1_Msk (0xFFFUL << TEMP_A1_A1_Pos) /*!< Bit mask of A1 field. */ /* Register: TEMP_A2 */ -/* Description: Slope of 3rd piece wise linear function */ +/* Description: Slope of third piecewise linear function */ -/* Bits 11..0 : Slope of 3rd piece wise linear function */ +/* Bits 11..0 : Slope of third piecewise linear function */ #define TEMP_A2_A2_Pos (0UL) /*!< Position of A2 field. */ #define TEMP_A2_A2_Msk (0xFFFUL << TEMP_A2_A2_Pos) /*!< Bit mask of A2 field. */ /* Register: TEMP_A3 */ -/* Description: Slope of 4th piece wise linear function */ +/* Description: Slope of fourth piecewise linear function */ -/* Bits 11..0 : Slope of 4th piece wise linear function */ +/* Bits 11..0 : Slope of fourth piecewise linear function */ #define TEMP_A3_A3_Pos (0UL) /*!< Position of A3 field. */ #define TEMP_A3_A3_Msk (0xFFFUL << TEMP_A3_A3_Pos) /*!< Bit mask of A3 field. */ /* Register: TEMP_A4 */ -/* Description: Slope of 5th piece wise linear function */ +/* Description: Slope of fifth piecewise linear function */ -/* Bits 11..0 : Slope of 5th piece wise linear function */ +/* Bits 11..0 : Slope of fifth piecewise linear function */ #define TEMP_A4_A4_Pos (0UL) /*!< Position of A4 field. */ #define TEMP_A4_A4_Msk (0xFFFUL << TEMP_A4_A4_Pos) /*!< Bit mask of A4 field. */ /* Register: TEMP_A5 */ -/* Description: Slope of 6th piece wise linear function */ +/* Description: Slope of sixth piecewise linear function */ -/* Bits 11..0 : Slope of 6th piece wise linear function */ +/* Bits 11..0 : Slope of sixth piecewise linear function */ #define TEMP_A5_A5_Pos (0UL) /*!< Position of A5 field. */ #define TEMP_A5_A5_Msk (0xFFFUL << TEMP_A5_A5_Pos) /*!< Bit mask of A5 field. */ /* Register: TEMP_B0 */ -/* Description: y-intercept of 1st piece wise linear function */ +/* Description: y-intercept of first piecewise linear function */ -/* Bits 13..0 : y-intercept of 1st piece wise linear function */ +/* Bits 13..0 : y-intercept of first piecewise linear function */ #define TEMP_B0_B0_Pos (0UL) /*!< Position of B0 field. */ #define TEMP_B0_B0_Msk (0x3FFFUL << TEMP_B0_B0_Pos) /*!< Bit mask of B0 field. */ /* Register: TEMP_B1 */ -/* Description: y-intercept of 2nd piece wise linear function */ +/* Description: y-intercept of second piecewise linear function */ -/* Bits 13..0 : y-intercept of 2nd piece wise linear function */ +/* Bits 13..0 : y-intercept of second piecewise linear function */ #define TEMP_B1_B1_Pos (0UL) /*!< Position of B1 field. */ #define TEMP_B1_B1_Msk (0x3FFFUL << TEMP_B1_B1_Pos) /*!< Bit mask of B1 field. */ /* Register: TEMP_B2 */ -/* Description: y-intercept of 3rd piece wise linear function */ +/* Description: y-intercept of third piecewise linear function */ -/* Bits 13..0 : y-intercept of 3rd piece wise linear function */ +/* Bits 13..0 : y-intercept of third piecewise linear function */ #define TEMP_B2_B2_Pos (0UL) /*!< Position of B2 field. */ #define TEMP_B2_B2_Msk (0x3FFFUL << TEMP_B2_B2_Pos) /*!< Bit mask of B2 field. */ /* Register: TEMP_B3 */ -/* Description: y-intercept of 4th piece wise linear function */ +/* Description: y-intercept of fourth piecewise linear function */ -/* Bits 13..0 : y-intercept of 4th piece wise linear function */ +/* Bits 13..0 : y-intercept of fourth piecewise linear function */ #define TEMP_B3_B3_Pos (0UL) /*!< Position of B3 field. */ #define TEMP_B3_B3_Msk (0x3FFFUL << TEMP_B3_B3_Pos) /*!< Bit mask of B3 field. */ /* Register: TEMP_B4 */ -/* Description: y-intercept of 5th piece wise linear function */ +/* Description: y-intercept of fifth piecewise linear function */ -/* Bits 13..0 : y-intercept of 5th piece wise linear function */ +/* Bits 13..0 : y-intercept of fifth piecewise linear function */ #define TEMP_B4_B4_Pos (0UL) /*!< Position of B4 field. */ #define TEMP_B4_B4_Msk (0x3FFFUL << TEMP_B4_B4_Pos) /*!< Bit mask of B4 field. */ /* Register: TEMP_B5 */ -/* Description: y-intercept of 6th piece wise linear function */ +/* Description: y-intercept of sixth piecewise linear function */ -/* Bits 13..0 : y-intercept of 6th piece wise linear function */ +/* Bits 13..0 : y-intercept of sixth piecewise linear function */ #define TEMP_B5_B5_Pos (0UL) /*!< Position of B5 field. */ #define TEMP_B5_B5_Msk (0x3FFFUL << TEMP_B5_B5_Pos) /*!< Bit mask of B5 field. */ /* Register: TEMP_T0 */ -/* Description: End point of 1st piece wise linear function */ +/* Description: End point of first piecewise linear function */ -/* Bits 7..0 : End point of 1st piece wise linear function */ +/* Bits 7..0 : End point of first piecewise linear function */ #define TEMP_T0_T0_Pos (0UL) /*!< Position of T0 field. */ #define TEMP_T0_T0_Msk (0xFFUL << TEMP_T0_T0_Pos) /*!< Bit mask of T0 field. */ /* Register: TEMP_T1 */ -/* Description: End point of 2nd piece wise linear function */ +/* Description: End point of second piecewise linear function */ -/* Bits 7..0 : End point of 2nd piece wise linear function */ +/* Bits 7..0 : End point of second piecewise linear function */ #define TEMP_T1_T1_Pos (0UL) /*!< Position of T1 field. */ #define TEMP_T1_T1_Msk (0xFFUL << TEMP_T1_T1_Pos) /*!< Bit mask of T1 field. */ /* Register: TEMP_T2 */ -/* Description: End point of 3rd piece wise linear function */ +/* Description: End point of third piecewise linear function */ -/* Bits 7..0 : End point of 3rd piece wise linear function */ +/* Bits 7..0 : End point of third piecewise linear function */ #define TEMP_T2_T2_Pos (0UL) /*!< Position of T2 field. */ #define TEMP_T2_T2_Msk (0xFFUL << TEMP_T2_T2_Pos) /*!< Bit mask of T2 field. */ /* Register: TEMP_T3 */ -/* Description: End point of 4th piece wise linear function */ +/* Description: End point of fourth piecewise linear function */ -/* Bits 7..0 : End point of 4th piece wise linear function */ +/* Bits 7..0 : End point of fourth piecewise linear function */ #define TEMP_T3_T3_Pos (0UL) /*!< Position of T3 field. */ #define TEMP_T3_T3_Msk (0xFFUL << TEMP_T3_T3_Pos) /*!< Bit mask of T3 field. */ /* Register: TEMP_T4 */ -/* Description: End point of 5th piece wise linear function */ +/* Description: End point of fifth piecewise linear function */ -/* Bits 7..0 : End point of 5th piece wise linear function */ +/* Bits 7..0 : End point of fifth piecewise linear function */ #define TEMP_T4_T4_Pos (0UL) /*!< Position of T4 field. */ #define TEMP_T4_T4_Msk (0xFFUL << TEMP_T4_T4_Pos) /*!< Bit mask of T4 field. */ @@ -8360,9 +8429,9 @@ POSSIBILITY OF SUCH DAMAGE. #define TWIM_EVENTS_ERROR_EVENTS_ERROR_Generated (1UL) /*!< Event generated */ /* Register: TWIM_EVENTS_SUSPENDED */ -/* Description: Last byte has been sent out after the SUSPEND task has been issued, TWI traffic is now suspended. */ +/* Description: SUSPEND task has been issued, TWI traffic is now suspended. */ -/* Bit 0 : Last byte has been sent out after the SUSPEND task has been issued, TWI traffic is now suspended. */ +/* Bit 0 : SUSPEND task has been issued, TWI traffic is now suspended. */ #define TWIM_EVENTS_SUSPENDED_EVENTS_SUSPENDED_Pos (0UL) /*!< Position of EVENTS_SUSPENDED field. */ #define TWIM_EVENTS_SUSPENDED_EVENTS_SUSPENDED_Msk (0x1UL << TWIM_EVENTS_SUSPENDED_EVENTS_SUSPENDED_Pos) /*!< Bit mask of EVENTS_SUSPENDED field. */ #define TWIM_EVENTS_SUSPENDED_EVENTS_SUSPENDED_NotGenerated (0UL) /*!< Event not generated */ @@ -8991,7 +9060,7 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: TWIS_MATCH */ /* Description: Status register indicating which address had a match */ -/* Bit 0 : Which of the addresses in {ADDRESS} matched the incoming address */ +/* Bit 0 : Indication of which address in {ADDRESS} that matched the incoming address */ #define TWIS_MATCH_MATCH_Pos (0UL) /*!< Position of MATCH field. */ #define TWIS_MATCH_MATCH_Msk (0x1UL << TWIS_MATCH_MATCH_Pos) /*!< Bit mask of MATCH field. */ @@ -9858,7 +9927,7 @@ POSSIBILITY OF SUCH DAMAGE. #define UARTE_INTENCLR_CTS_Clear (1UL) /*!< Disable */ /* Register: UARTE_ERRORSRC */ -/* Description: Error source Note : this register is read / write one to clear. */ +/* Description: Error source This register is read/write one to clear. */ /* Bit 3 : Break condition */ #define UARTE_ERRORSRC_BREAK_Pos (3UL) /*!< Position of BREAK field. */ @@ -9968,7 +10037,7 @@ POSSIBILITY OF SUCH DAMAGE. #define UARTE_BAUDRATE_BAUDRATE_Baud250000 (0x04000000UL) /*!< 250000 baud */ #define UARTE_BAUDRATE_BAUDRATE_Baud460800 (0x07400000UL) /*!< 460800 baud (actual rate: 457143) */ #define UARTE_BAUDRATE_BAUDRATE_Baud921600 (0x0F000000UL) /*!< 921600 baud (actual rate: 941176) */ -#define UARTE_BAUDRATE_BAUDRATE_Baud1M (0x10000000UL) /*!< 1Mega baud */ +#define UARTE_BAUDRATE_BAUDRATE_Baud1M (0x10000000UL) /*!< 1 megabaud */ /* Register: UARTE_RXD_PTR */ /* Description: Data pointer */ diff --git a/mdk/nrf52805_peripherals.h b/mdk/nrf52805_peripherals.h index add55c9ecd..43a262e472 100644 --- a/mdk/nrf52805_peripherals.h +++ b/mdk/nrf52805_peripherals.h @@ -77,6 +77,8 @@ POSSIBILITY OF SUCH DAMAGE. #define RADIO_EASYDMA_MAXCNT_SIZE 8 +#define RADIO_TXPOWER_TXPOWER_Max RADIO_TXPOWER_TXPOWER_Pos4dBm + /* Accelerated Address Resolver */ #define AAR_PRESENT #define AAR_COUNT 1 @@ -140,11 +142,11 @@ POSSIBILITY OF SUCH DAMAGE. /* Serial Peripheral Interface Master */ #define SPI_PRESENT -#define SPI_COUNT 2 +#define SPI_COUNT 1 /* Serial Peripheral Interface Master with DMA */ #define SPIM_PRESENT -#define SPIM_COUNT 2 +#define SPIM_COUNT 1 #define SPIM0_MAX_DATARATE 8 #define SPIM1_MAX_DATARATE 8 @@ -163,7 +165,7 @@ POSSIBILITY OF SUCH DAMAGE. /* Serial Peripheral Interface Slave with DMA*/ #define SPIS_PRESENT -#define SPIS_COUNT 2 +#define SPIS_COUNT 1 #define SPIS0_EASYDMA_MAXCNT_SIZE 14 #define SPIS1_EASYDMA_MAXCNT_SIZE 14 @@ -194,6 +196,10 @@ POSSIBILITY OF SUCH DAMAGE. #define UARTE0_EASYDMA_MAXCNT_SIZE 14 +/* Quadrature Decoder */ +#define QDEC_PRESENT +#define QDEC_COUNT 1 + /* Successive Approximation Analog to Digital Converter */ #define SAADC_PRESENT #define SAADC_COUNT 1 diff --git a/mdk/nrf52810.h b/mdk/nrf52810.h index 238e2a38c3..732e842d1d 100644 --- a/mdk/nrf52810.h +++ b/mdk/nrf52810.h @@ -30,10 +30,10 @@ * @file nrf52810.h * @brief CMSIS HeaderFile * @version 1 - * @date 04. March 2020 - * @note Generated by SVDConv V3.3.25 on Wednesday, 04.03.2020 14:56:51 + * @date 14. August 2020 + * @note Generated by SVDConv V3.3.35 on Friday, 14.08.2020 15:02:13 * from File 'nrf52810.svd', - * last modified on Wednesday, 04.03.2020 13:56:43 + * last modified on Friday, 14.08.2020 13:02:06 */ diff --git a/mdk/nrf52810_peripherals.h b/mdk/nrf52810_peripherals.h index 7dc65b6a85..9f39a7091c 100644 --- a/mdk/nrf52810_peripherals.h +++ b/mdk/nrf52810_peripherals.h @@ -77,6 +77,8 @@ POSSIBILITY OF SUCH DAMAGE. #define RADIO_EASYDMA_MAXCNT_SIZE 8 +#define RADIO_TXPOWER_TXPOWER_Max RADIO_TXPOWER_TXPOWER_Pos4dBm + /* Accelerated Address Resolver */ #define AAR_PRESENT #define AAR_COUNT 1 diff --git a/mdk/nrf52810_to_nrf52811.h b/mdk/nrf52810_to_nrf52811.h index 2de13839c2..8e13c376d8 100644 --- a/mdk/nrf52810_to_nrf52811.h +++ b/mdk/nrf52810_to_nrf52811.h @@ -43,16 +43,15 @@ POSSIBILITY OF SUCH DAMAGE. /* Interrupt service routines handlers. */ #ifndef TWIM0_TWIS0_IRQHandler - #define TWIM0_TWIS0_IRQHandler TWIM0_TWIS0_SPIM1_SPIS1_IRQHandler + #define TWIM0_TWIS0_IRQHandler TWIM0_TWIS0_TWI0_SPIM1_SPIS1_SPI1_IRQHandler #endif /* Interrupt service routines index. */ #ifndef TWIM0_TWIS0_IRQn - #define TWIM0_TWIS0_IRQn TWIM0_TWIS0_SPIM1_SPIS1_IRQn + #define TWIM0_TWIS0_IRQn TWIM0_TWIS0_TWI0_SPIM1_SPIS1_SPI1_IRQn #endif - /*lint --flb "Leave library region" */ #endif /* NRF52810_TO_NRF52811_H */ diff --git a/mdk/nrf52811.h b/mdk/nrf52811.h index 000099ceb9..30a46af2d5 100644 --- a/mdk/nrf52811.h +++ b/mdk/nrf52811.h @@ -30,10 +30,10 @@ * @file nrf52811.h * @brief CMSIS HeaderFile * @version 1 - * @date 04. March 2020 - * @note Generated by SVDConv V3.3.25 on Wednesday, 04.03.2020 14:56:51 + * @date 14. August 2020 + * @note Generated by SVDConv V3.3.35 on Friday, 14.08.2020 15:02:13 * from File 'nrf52811.svd', - * last modified on Wednesday, 04.03.2020 13:56:44 + * last modified on Friday, 14.08.2020 13:02:06 */ diff --git a/mdk/nrf52811_peripherals.h b/mdk/nrf52811_peripherals.h index ce72fb9419..46951babfd 100644 --- a/mdk/nrf52811_peripherals.h +++ b/mdk/nrf52811_peripherals.h @@ -78,6 +78,8 @@ POSSIBILITY OF SUCH DAMAGE. #define RADIO_EASYDMA_MAXCNT_SIZE 8 #define RADIO_FEATURE_IEEE_802_15_4_PRESENT +#define RADIO_TXPOWER_TXPOWER_Max RADIO_TXPOWER_TXPOWER_Pos4dBm + /* Accelerated Address Resolver */ #define AAR_PRESENT #define AAR_COUNT 1 diff --git a/mdk/nrf52820.h b/mdk/nrf52820.h index 81e68bf909..2ff55f2e31 100644 --- a/mdk/nrf52820.h +++ b/mdk/nrf52820.h @@ -30,10 +30,10 @@ * @file nrf52820.h * @brief CMSIS HeaderFile * @version 1 - * @date 04. March 2020 - * @note Generated by SVDConv V3.3.25 on Wednesday, 04.03.2020 14:56:51 + * @date 14. August 2020 + * @note Generated by SVDConv V3.3.35 on Friday, 14.08.2020 15:02:13 * from File 'nrf52820.svd', - * last modified on Wednesday, 04.03.2020 13:56:44 + * last modified on Friday, 14.08.2020 13:02:07 */ diff --git a/mdk/nrf52820_peripherals.h b/mdk/nrf52820_peripherals.h index 2662e1a2e2..a613c0b2b5 100644 --- a/mdk/nrf52820_peripherals.h +++ b/mdk/nrf52820_peripherals.h @@ -45,7 +45,6 @@ POSSIBILITY OF SUCH DAMAGE. #define POWER_FEATURE_RAM_REGISTERS_COUNT 4 #define POWER_FEATURE_VDDH_PRESENT -#define POWER_FEATURE_VDDH_DCDC_PRESENT /* Non-Volatile Memory Controller */ #define NVMC_PRESENT @@ -78,6 +77,8 @@ POSSIBILITY OF SUCH DAMAGE. #define RADIO_EASYDMA_MAXCNT_SIZE 16 #define RADIO_FEATURE_IEEE_802_15_4_PRESENT +#define RADIO_TXPOWER_TXPOWER_Max RADIO_TXPOWER_TXPOWER_Pos8dBm + /* Accelerated Address Resolver */ #define AAR_PRESENT #define AAR_COUNT 1 diff --git a/mdk/nrf52832_peripherals.h b/mdk/nrf52832_peripherals.h index 3444bce522..af7ace555c 100644 --- a/mdk/nrf52832_peripherals.h +++ b/mdk/nrf52832_peripherals.h @@ -43,7 +43,11 @@ POSSIBILITY OF SUCH DAMAGE. #define POWER_COUNT 1 #define POWER_FEATURE_RAM_REGISTERS_PRESENT -#define POWER_FEATURE_RAM_REGISTERS_COUNT 8 +#if defined(NRF52832_XXAA) + #define POWER_FEATURE_RAM_REGISTERS_COUNT 8 +#elif defined(NRF52832_XXAB) + #define POWER_FEATURE_RAM_REGISTERS_COUNT 4 +#endif /* Non-Volatile Memory Controller */ #define NVMC_PRESENT @@ -79,7 +83,12 @@ POSSIBILITY OF SUCH DAMAGE. #define BPROT_PRESENT #define BPROT_REGIONS_SIZE 4096 -#define BPROT_REGIONS_NUM 128 + +#if defined(NRF52832_XXAA) + #define BPROT_REGIONS_NUM 128 +#elif defined(NRF52832_XXAB) + #define BPROT_REGIONS_NUM 64 +#endif /* Radio */ #define RADIO_PRESENT @@ -87,6 +96,8 @@ POSSIBILITY OF SUCH DAMAGE. #define RADIO_EASYDMA_MAXCNT_SIZE 8 +#define RADIO_TXPOWER_TXPOWER_Max RADIO_TXPOWER_TXPOWER_Pos4dBm + /* Accelerated Address Resolver */ #define AAR_PRESENT #define AAR_COUNT 1 diff --git a/mdk/nrf52833.h b/mdk/nrf52833.h index b179fb44d3..7b3bf495cf 100644 --- a/mdk/nrf52833.h +++ b/mdk/nrf52833.h @@ -30,10 +30,10 @@ * @file nrf52833.h * @brief CMSIS HeaderFile * @version 1 - * @date 04. March 2020 - * @note Generated by SVDConv V3.3.25 on Wednesday, 04.03.2020 14:56:52 + * @date 14. August 2020 + * @note Generated by SVDConv V3.3.35 on Friday, 14.08.2020 15:02:13 * from File 'nrf52833.svd', - * last modified on Wednesday, 04.03.2020 13:56:44 + * last modified on Friday, 14.08.2020 13:02:07 */ diff --git a/mdk/nrf52833_peripherals.h b/mdk/nrf52833_peripherals.h index 0cbf7ccc1f..70e62741f8 100644 --- a/mdk/nrf52833_peripherals.h +++ b/mdk/nrf52833_peripherals.h @@ -92,6 +92,8 @@ POSSIBILITY OF SUCH DAMAGE. #define RADIO_EASYDMA_MAXCNT_SIZE 8 #define RADIO_FEATURE_IEEE_802_15_4_PRESENT +#define RADIO_TXPOWER_TXPOWER_Max RADIO_TXPOWER_TXPOWER_Pos8dBm + /* Accelerated Address Resolver */ #define AAR_PRESENT #define AAR_COUNT 1 diff --git a/mdk/nrf52840.h b/mdk/nrf52840.h index 4c761c56d0..253bad025c 100644 --- a/mdk/nrf52840.h +++ b/mdk/nrf52840.h @@ -30,10 +30,10 @@ * @file nrf52840.h * @brief CMSIS HeaderFile * @version 1 - * @date 04. March 2020 - * @note Generated by SVDConv V3.3.25 on Wednesday, 04.03.2020 14:56:52 + * @date 14. August 2020 + * @note Generated by SVDConv V3.3.35 on Friday, 14.08.2020 15:02:14 * from File 'nrf52840.svd', - * last modified on Wednesday, 04.03.2020 13:56:44 + * last modified on Friday, 14.08.2020 13:02:07 */ @@ -938,9 +938,8 @@ typedef struct { /*!< (@ 0x10001000) UICR Structu NFC antenna or GPIO */ __IOM uint32_t DEBUGCTRL; /*!< (@ 0x00000210) Processor debug control */ __IM uint32_t RESERVED3[60]; - __IOM uint32_t REGOUT0; /*!< (@ 0x00000304) Output voltage from REG0 regulator stage. The - maximum output voltage from this stage is - given as VDDH - VREG0DROP. */ + __IOM uint32_t REGOUT0; /*!< (@ 0x00000304) GPIO reference voltage / external output supply + voltage in high voltage mode */ } NRF_UICR_Type; /*!< Size = 776 (0x308) */ @@ -1137,7 +1136,8 @@ typedef struct { /*!< (@ 0x40001000) RADIO Struct __IOM uint32_t EVENTS_RXREADY; /*!< (@ 0x00000158) RADIO has ramped up and is ready to be started RX path */ __IOM uint32_t EVENTS_MHRMATCH; /*!< (@ 0x0000015C) MAC header match found */ - __IM uint32_t RESERVED3[3]; + __IM uint32_t RESERVED3[2]; + __IOM uint32_t EVENTS_SYNC; /*!< (@ 0x00000168) Preamble indicator. */ __IOM uint32_t EVENTS_PHYEND; /*!< (@ 0x0000016C) Generated in Ble_LR125Kbit, Ble_LR500Kbit and Ieee802154_250Kbit modes when last bit is sent on air. */ @@ -2542,17 +2542,17 @@ typedef struct { /*!< (@ 0x40027000) USBD Structu have been captured on all endpoints reported in the EPSTATUS register */ __IOM uint32_t EVENTS_ENDEPIN[8]; /*!< (@ 0x00000108) Description collection: The whole EPIN[n] buffer - has been consumed. The buffer can be accessed - safely by software. */ + has been consumed. The RAM buffer can be + accessed safely by software. */ __IOM uint32_t EVENTS_EP0DATADONE; /*!< (@ 0x00000128) An acknowledged data transfer has taken place on the control endpoint */ __IOM uint32_t EVENTS_ENDISOIN; /*!< (@ 0x0000012C) The whole ISOIN buffer has been consumed. The - buffer can be accessed safely by software. */ + RAM buffer can be accessed safely by software. */ __IOM uint32_t EVENTS_ENDEPOUT[8]; /*!< (@ 0x00000130) Description collection: The whole EPOUT[n] buffer - has been consumed. The buffer can be accessed - safely by software. */ + has been consumed. The RAM buffer can be + accessed safely by software. */ __IOM uint32_t EVENTS_ENDISOOUT; /*!< (@ 0x00000150) The whole ISOOUT buffer has been consumed. The - buffer can be accessed safely by software. */ + RAM buffer can be accessed safely by software. */ __IOM uint32_t EVENTS_SOF; /*!< (@ 0x00000154) Signals that a SOF (start of frame) condition has been detected on USB lines */ __IOM uint32_t EVENTS_USBEVENT; /*!< (@ 0x00000158) An event or an error not covered by specific diff --git a/mdk/nrf52840.svd b/mdk/nrf52840.svd index 9f34997059..399571b681 100644 --- a/mdk/nrf52840.svd +++ b/mdk/nrf52840.svd @@ -1181,14 +1181,14 @@ POSSIBILITY OF SUCH DAMAGE.\n REGOUT0 - Output voltage from REG0 regulator stage. The maximum output voltage from this stage is given as VDDH - VREG0DROP. + GPIO reference voltage / external output supply voltage in high voltage mode 0x304 read-write 0xFFFFFFFF VOUT - Output voltage from REG0 regulator stage. + Output voltage from of REG0 regulator stage. The maximum output voltage from this stage is given as VDDH - VEXDIF. 0 2 @@ -11741,6 +11741,32 @@ POSSIBILITY OF SUCH DAMAGE.\n + + EVENTS_SYNC + Preamble indicator. + 0x168 + read-write + + + EVENTS_SYNC + Preamble indicator. + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + EVENTS_PHYEND Generated in Ble_LR125Kbit, Ble_LR500Kbit and Ieee802154_250Kbit modes when last bit is sent on air. @@ -12690,6 +12716,33 @@ POSSIBILITY OF SUCH DAMAGE.\n + + SYNC + Write '1' to enable interrupt for event SYNC + 26 + 26 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + PHYEND Write '1' to enable interrupt for event PHYEND @@ -13292,6 +13345,33 @@ POSSIBILITY OF SUCH DAMAGE.\n + + SYNC + Write '1' to disable interrupt for event SYNC + 26 + 26 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + PHYEND Write '1' to disable interrupt for event PHYEND @@ -32507,7 +32587,7 @@ POSSIBILITY OF SUCH DAMAGE.\n SCRATCHPTR - Pointer to a scratch data area used for temporary storage during resolution.A space of minimum 3 bytes must be reserved. + Pointer to a scratch data area used for temporary storage during resolution. A space of minimum 3 bytes must be reserved. 0 31 @@ -39805,7 +39885,7 @@ POSSIBILITY OF SUCH DAMAGE.\n SIZE - Size of flash region n in bytes. Must be a multiple of the flash page size, and the maximum region size is limited to 512kB. + Size of flash region n in bytes. Must be a multiple of the flash page size, and the maximum region size is limited to 512 kB. 0 31 @@ -49239,13 +49319,13 @@ POSSIBILITY OF SUCH DAMAGE.\n 0x8 0x4 EVENTS_ENDEPIN[%s] - Description collection: The whole EPIN[n] buffer has been consumed. The buffer can be accessed safely by software. + Description collection: The whole EPIN[n] buffer has been consumed. The RAM buffer can be accessed safely by software. 0x108 read-write EVENTS_ENDEPIN - The whole EPIN[n] buffer has been consumed. The buffer can be accessed safely by software. + The whole EPIN[n] buffer has been consumed. The RAM buffer can be accessed safely by software. 0 0 @@ -49291,13 +49371,13 @@ POSSIBILITY OF SUCH DAMAGE.\n EVENTS_ENDISOIN - The whole ISOIN buffer has been consumed. The buffer can be accessed safely by software. + The whole ISOIN buffer has been consumed. The RAM buffer can be accessed safely by software. 0x12C read-write EVENTS_ENDISOIN - The whole ISOIN buffer has been consumed. The buffer can be accessed safely by software. + The whole ISOIN buffer has been consumed. The RAM buffer can be accessed safely by software. 0 0 @@ -49319,13 +49399,13 @@ POSSIBILITY OF SUCH DAMAGE.\n 0x8 0x4 EVENTS_ENDEPOUT[%s] - Description collection: The whole EPOUT[n] buffer has been consumed. The buffer can be accessed safely by software. + Description collection: The whole EPOUT[n] buffer has been consumed. The RAM buffer can be accessed safely by software. 0x130 read-write EVENTS_ENDEPOUT - The whole EPOUT[n] buffer has been consumed. The buffer can be accessed safely by software. + The whole EPOUT[n] buffer has been consumed. The RAM buffer can be accessed safely by software. 0 0 @@ -49345,13 +49425,13 @@ POSSIBILITY OF SUCH DAMAGE.\n EVENTS_ENDISOOUT - The whole ISOOUT buffer has been consumed. The buffer can be accessed safely by software. + The whole ISOOUT buffer has been consumed. The RAM buffer can be accessed safely by software. 0x150 read-write EVENTS_ENDISOOUT - The whole ISOOUT buffer has been consumed. The buffer can be accessed safely by software. + The whole ISOOUT buffer has been consumed. The RAM buffer can be accessed safely by software. 0 0 @@ -53103,7 +53183,7 @@ POSSIBILITY OF SUCH DAMAGE.\n PTR - Data pointer + Data pointer. Accepts any address in Data RAM. 0 31 @@ -53152,7 +53232,7 @@ POSSIBILITY OF SUCH DAMAGE.\n PTR - Data pointer + Data pointer. Accepts any address in Data RAM. 0 31 @@ -53203,7 +53283,7 @@ POSSIBILITY OF SUCH DAMAGE.\n PTR - Data pointer + Data pointer. Accepts any address in Data RAM. 0 31 @@ -53252,7 +53332,7 @@ POSSIBILITY OF SUCH DAMAGE.\n PTR - Data pointer + Data pointer. Accepts any address in Data RAM. 0 31 diff --git a/mdk/nrf52840_bitfields.h b/mdk/nrf52840_bitfields.h index b4302ffd09..e91dd4dd1f 100644 --- a/mdk/nrf52840_bitfields.h +++ b/mdk/nrf52840_bitfields.h @@ -169,7 +169,7 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: AAR_SCRATCHPTR */ /* Description: Pointer to data area used for temporary storage */ -/* Bits 31..0 : Pointer to a scratch data area used for temporary storage during resolution.A space of minimum 3 bytes must be reserved. */ +/* Bits 31..0 : Pointer to a scratch data area used for temporary storage during resolution. A space of minimum 3 bytes must be reserved. */ #define AAR_SCRATCHPTR_SCRATCHPTR_Pos (0UL) /*!< Position of SCRATCHPTR field. */ #define AAR_SCRATCHPTR_SCRATCHPTR_Msk (0xFFFFFFFFUL << AAR_SCRATCHPTR_SCRATCHPTR_Pos) /*!< Bit mask of SCRATCHPTR field. */ @@ -187,7 +187,7 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: ACL_ACL_SIZE */ /* Description: Description cluster: Size of region to protect counting from address ACL[n].ADDR. Write '0' as no effect. */ -/* Bits 31..0 : Size of flash region n in bytes. Must be a multiple of the flash page size, and the maximum region size is limited to 512kB. */ +/* Bits 31..0 : Size of flash region n in bytes. Must be a multiple of the flash page size, and the maximum region size is limited to 512 kB. */ #define ACL_ACL_SIZE_SIZE_Pos (0UL) /*!< Position of SIZE field. */ #define ACL_ACL_SIZE_SIZE_Msk (0xFFFFFFFFUL << ACL_ACL_SIZE_SIZE_Pos) /*!< Bit mask of SIZE field. */ @@ -10284,6 +10284,15 @@ POSSIBILITY OF SUCH DAMAGE. #define RADIO_EVENTS_MHRMATCH_EVENTS_MHRMATCH_NotGenerated (0UL) /*!< Event not generated */ #define RADIO_EVENTS_MHRMATCH_EVENTS_MHRMATCH_Generated (1UL) /*!< Event generated */ +/* Register: RADIO_EVENTS_SYNC */ +/* Description: Preamble indicator. */ + +/* Bit 0 : Preamble indicator. */ +#define RADIO_EVENTS_SYNC_EVENTS_SYNC_Pos (0UL) /*!< Position of EVENTS_SYNC field. */ +#define RADIO_EVENTS_SYNC_EVENTS_SYNC_Msk (0x1UL << RADIO_EVENTS_SYNC_EVENTS_SYNC_Pos) /*!< Bit mask of EVENTS_SYNC field. */ +#define RADIO_EVENTS_SYNC_EVENTS_SYNC_NotGenerated (0UL) /*!< Event not generated */ +#define RADIO_EVENTS_SYNC_EVENTS_SYNC_Generated (1UL) /*!< Event generated */ + /* Register: RADIO_EVENTS_PHYEND */ /* Description: Generated in Ble_LR125Kbit, Ble_LR500Kbit and Ieee802154_250Kbit modes when last bit is sent on air. */ @@ -10420,6 +10429,13 @@ POSSIBILITY OF SUCH DAMAGE. #define RADIO_INTENSET_PHYEND_Enabled (1UL) /*!< Read: Enabled */ #define RADIO_INTENSET_PHYEND_Set (1UL) /*!< Enable */ +/* Bit 26 : Write '1' to enable interrupt for event SYNC */ +#define RADIO_INTENSET_SYNC_Pos (26UL) /*!< Position of SYNC field. */ +#define RADIO_INTENSET_SYNC_Msk (0x1UL << RADIO_INTENSET_SYNC_Pos) /*!< Bit mask of SYNC field. */ +#define RADIO_INTENSET_SYNC_Disabled (0UL) /*!< Read: Disabled */ +#define RADIO_INTENSET_SYNC_Enabled (1UL) /*!< Read: Enabled */ +#define RADIO_INTENSET_SYNC_Set (1UL) /*!< Enable */ + /* Bit 23 : Write '1' to enable interrupt for event MHRMATCH */ #define RADIO_INTENSET_MHRMATCH_Pos (23UL) /*!< Position of MHRMATCH field. */ #define RADIO_INTENSET_MHRMATCH_Msk (0x1UL << RADIO_INTENSET_MHRMATCH_Pos) /*!< Bit mask of MHRMATCH field. */ @@ -10577,6 +10593,13 @@ POSSIBILITY OF SUCH DAMAGE. #define RADIO_INTENCLR_PHYEND_Enabled (1UL) /*!< Read: Enabled */ #define RADIO_INTENCLR_PHYEND_Clear (1UL) /*!< Disable */ +/* Bit 26 : Write '1' to disable interrupt for event SYNC */ +#define RADIO_INTENCLR_SYNC_Pos (26UL) /*!< Position of SYNC field. */ +#define RADIO_INTENCLR_SYNC_Msk (0x1UL << RADIO_INTENCLR_SYNC_Pos) /*!< Bit mask of SYNC field. */ +#define RADIO_INTENCLR_SYNC_Disabled (0UL) /*!< Read: Disabled */ +#define RADIO_INTENCLR_SYNC_Enabled (1UL) /*!< Read: Enabled */ +#define RADIO_INTENCLR_SYNC_Clear (1UL) /*!< Disable */ + /* Bit 23 : Write '1' to disable interrupt for event MHRMATCH */ #define RADIO_INTENCLR_MHRMATCH_Pos (23UL) /*!< Position of MHRMATCH field. */ #define RADIO_INTENCLR_MHRMATCH_Msk (0x1UL << RADIO_INTENCLR_MHRMATCH_Pos) /*!< Bit mask of MHRMATCH field. */ @@ -15830,9 +15853,9 @@ POSSIBILITY OF SUCH DAMAGE. #define UICR_DEBUGCTRL_CPUNIDEN_Enabled (0xFFUL) /*!< Enable CPU ITM and ETM functionality (default behavior) */ /* Register: UICR_REGOUT0 */ -/* Description: Output voltage from REG0 regulator stage. The maximum output voltage from this stage is given as VDDH - VREG0DROP. */ +/* Description: GPIO reference voltage / external output supply voltage in high voltage mode */ -/* Bits 2..0 : Output voltage from REG0 regulator stage. */ +/* Bits 2..0 : Output voltage from of REG0 regulator stage. The maximum output voltage from this stage is given as VDDH - VEXDIF. */ #define UICR_REGOUT0_VOUT_Pos (0UL) /*!< Position of VOUT field. */ #define UICR_REGOUT0_VOUT_Msk (0x7UL << UICR_REGOUT0_VOUT_Pos) /*!< Bit mask of VOUT field. */ #define UICR_REGOUT0_VOUT_1V8 (0UL) /*!< 1.8 V */ @@ -15938,9 +15961,9 @@ POSSIBILITY OF SUCH DAMAGE. #define USBD_EVENTS_STARTED_EVENTS_STARTED_Generated (1UL) /*!< Event generated */ /* Register: USBD_EVENTS_ENDEPIN */ -/* Description: Description collection: The whole EPIN[n] buffer has been consumed. The buffer can be accessed safely by software. */ +/* Description: Description collection: The whole EPIN[n] buffer has been consumed. The RAM buffer can be accessed safely by software. */ -/* Bit 0 : The whole EPIN[n] buffer has been consumed. The buffer can be accessed safely by software. */ +/* Bit 0 : The whole EPIN[n] buffer has been consumed. The RAM buffer can be accessed safely by software. */ #define USBD_EVENTS_ENDEPIN_EVENTS_ENDEPIN_Pos (0UL) /*!< Position of EVENTS_ENDEPIN field. */ #define USBD_EVENTS_ENDEPIN_EVENTS_ENDEPIN_Msk (0x1UL << USBD_EVENTS_ENDEPIN_EVENTS_ENDEPIN_Pos) /*!< Bit mask of EVENTS_ENDEPIN field. */ #define USBD_EVENTS_ENDEPIN_EVENTS_ENDEPIN_NotGenerated (0UL) /*!< Event not generated */ @@ -15956,27 +15979,27 @@ POSSIBILITY OF SUCH DAMAGE. #define USBD_EVENTS_EP0DATADONE_EVENTS_EP0DATADONE_Generated (1UL) /*!< Event generated */ /* Register: USBD_EVENTS_ENDISOIN */ -/* Description: The whole ISOIN buffer has been consumed. The buffer can be accessed safely by software. */ +/* Description: The whole ISOIN buffer has been consumed. The RAM buffer can be accessed safely by software. */ -/* Bit 0 : The whole ISOIN buffer has been consumed. The buffer can be accessed safely by software. */ +/* Bit 0 : The whole ISOIN buffer has been consumed. The RAM buffer can be accessed safely by software. */ #define USBD_EVENTS_ENDISOIN_EVENTS_ENDISOIN_Pos (0UL) /*!< Position of EVENTS_ENDISOIN field. */ #define USBD_EVENTS_ENDISOIN_EVENTS_ENDISOIN_Msk (0x1UL << USBD_EVENTS_ENDISOIN_EVENTS_ENDISOIN_Pos) /*!< Bit mask of EVENTS_ENDISOIN field. */ #define USBD_EVENTS_ENDISOIN_EVENTS_ENDISOIN_NotGenerated (0UL) /*!< Event not generated */ #define USBD_EVENTS_ENDISOIN_EVENTS_ENDISOIN_Generated (1UL) /*!< Event generated */ /* Register: USBD_EVENTS_ENDEPOUT */ -/* Description: Description collection: The whole EPOUT[n] buffer has been consumed. The buffer can be accessed safely by software. */ +/* Description: Description collection: The whole EPOUT[n] buffer has been consumed. The RAM buffer can be accessed safely by software. */ -/* Bit 0 : The whole EPOUT[n] buffer has been consumed. The buffer can be accessed safely by software. */ +/* Bit 0 : The whole EPOUT[n] buffer has been consumed. The RAM buffer can be accessed safely by software. */ #define USBD_EVENTS_ENDEPOUT_EVENTS_ENDEPOUT_Pos (0UL) /*!< Position of EVENTS_ENDEPOUT field. */ #define USBD_EVENTS_ENDEPOUT_EVENTS_ENDEPOUT_Msk (0x1UL << USBD_EVENTS_ENDEPOUT_EVENTS_ENDEPOUT_Pos) /*!< Bit mask of EVENTS_ENDEPOUT field. */ #define USBD_EVENTS_ENDEPOUT_EVENTS_ENDEPOUT_NotGenerated (0UL) /*!< Event not generated */ #define USBD_EVENTS_ENDEPOUT_EVENTS_ENDEPOUT_Generated (1UL) /*!< Event generated */ /* Register: USBD_EVENTS_ENDISOOUT */ -/* Description: The whole ISOOUT buffer has been consumed. The buffer can be accessed safely by software. */ +/* Description: The whole ISOOUT buffer has been consumed. The RAM buffer can be accessed safely by software. */ -/* Bit 0 : The whole ISOOUT buffer has been consumed. The buffer can be accessed safely by software. */ +/* Bit 0 : The whole ISOOUT buffer has been consumed. The RAM buffer can be accessed safely by software. */ #define USBD_EVENTS_ENDISOOUT_EVENTS_ENDISOOUT_Pos (0UL) /*!< Position of EVENTS_ENDISOOUT field. */ #define USBD_EVENTS_ENDISOOUT_EVENTS_ENDISOOUT_Msk (0x1UL << USBD_EVENTS_ENDISOOUT_EVENTS_ENDISOOUT_Pos) /*!< Bit mask of EVENTS_ENDISOOUT field. */ #define USBD_EVENTS_ENDISOOUT_EVENTS_ENDISOOUT_NotGenerated (0UL) /*!< Event not generated */ @@ -17138,7 +17161,7 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: USBD_EPIN_PTR */ /* Description: Description cluster: Data pointer */ -/* Bits 31..0 : Data pointer */ +/* Bits 31..0 : Data pointer. Accepts any address in Data RAM. */ #define USBD_EPIN_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ #define USBD_EPIN_PTR_PTR_Msk (0xFFFFFFFFUL << USBD_EPIN_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ @@ -17159,7 +17182,7 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: USBD_ISOIN_PTR */ /* Description: Data pointer */ -/* Bits 31..0 : Data pointer */ +/* Bits 31..0 : Data pointer. Accepts any address in Data RAM. */ #define USBD_ISOIN_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ #define USBD_ISOIN_PTR_PTR_Msk (0xFFFFFFFFUL << USBD_ISOIN_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ @@ -17180,7 +17203,7 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: USBD_EPOUT_PTR */ /* Description: Description cluster: Data pointer */ -/* Bits 31..0 : Data pointer */ +/* Bits 31..0 : Data pointer. Accepts any address in Data RAM. */ #define USBD_EPOUT_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ #define USBD_EPOUT_PTR_PTR_Msk (0xFFFFFFFFUL << USBD_EPOUT_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ @@ -17201,7 +17224,7 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: USBD_ISOOUT_PTR */ /* Description: Data pointer */ -/* Bits 31..0 : Data pointer */ +/* Bits 31..0 : Data pointer. Accepts any address in Data RAM. */ #define USBD_ISOOUT_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ #define USBD_ISOOUT_PTR_PTR_Msk (0xFFFFFFFFUL << USBD_ISOOUT_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ diff --git a/mdk/nrf52840_peripherals.h b/mdk/nrf52840_peripherals.h index 0b90682e7e..822d6cd43b 100644 --- a/mdk/nrf52840_peripherals.h +++ b/mdk/nrf52840_peripherals.h @@ -92,6 +92,8 @@ POSSIBILITY OF SUCH DAMAGE. #define RADIO_EASYDMA_MAXCNT_SIZE 8 #define RADIO_FEATURE_IEEE_802_15_4_PRESENT +#define RADIO_TXPOWER_TXPOWER_Max RADIO_TXPOWER_TXPOWER_Pos8dBm + /* Accelerated Address Resolver */ #define AAR_PRESENT #define AAR_COUNT 1 diff --git a/mdk/nrf52840_xxaa.ld b/mdk/nrf52840_xxaa.ld index 3f4aa68dd9..89fac5704f 100644 --- a/mdk/nrf52840_xxaa.ld +++ b/mdk/nrf52840_xxaa.ld @@ -6,6 +6,7 @@ GROUP(-lgcc -lc -lnosys) MEMORY { FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 0x100000 + EXTFLASH (rx) : ORIGIN = 0x12000000, LENGTH = 0x8000000 RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x40000 CODE_RAM (rwx) : ORIGIN = 0x800000, LENGTH = 0x40000 } diff --git a/mdk/nrf52_common.ld b/mdk/nrf52_common.ld index 097beb4747..bb99b83079 100644 --- a/mdk/nrf52_common.ld +++ b/mdk/nrf52_common.ld @@ -89,6 +89,7 @@ SECTIONS } > FLASH __exidx_end = .; + . = ALIGN(4); __etext = .; .data : AT (__etext) diff --git a/mdk/nrf52_erratas.h b/mdk/nrf52_erratas.h index dd251d85e9..228d330ae2 100644 --- a/mdk/nrf52_erratas.h +++ b/mdk/nrf52_erratas.h @@ -194,6 +194,7 @@ static bool nrf52_errata_204(void) __UNUSED; static bool nrf52_errata_208(void) __UNUSED; static bool nrf52_errata_209(void) __UNUSED; static bool nrf52_errata_210(void) __UNUSED; +static bool nrf52_errata_211(void) __UNUSED; static bool nrf52_errata_212(void) __UNUSED; static bool nrf52_errata_213(void) __UNUSED; static bool nrf52_errata_214(void) __UNUSED; @@ -203,10 +204,16 @@ static bool nrf52_errata_217(void) __UNUSED; static bool nrf52_errata_218(void) __UNUSED; static bool nrf52_errata_219(void) __UNUSED; static bool nrf52_errata_220(void) __UNUSED; +static bool nrf52_errata_223(void) __UNUSED; static bool nrf52_errata_225(void) __UNUSED; static bool nrf52_errata_228(void) __UNUSED; static bool nrf52_errata_230(void) __UNUSED; static bool nrf52_errata_231(void) __UNUSED; +static bool nrf52_errata_232(void) __UNUSED; +static bool nrf52_errata_233(void) __UNUSED; +static bool nrf52_errata_236(void) __UNUSED; +static bool nrf52_errata_237(void) __UNUSED; +static bool nrf52_errata_248(void) __UNUSED; static bool nrf52_errata_1(void) { @@ -232,6 +239,8 @@ static bool nrf52_errata_1(void) return false; case 0x06ul: return false; + default: + return false; } } #endif @@ -263,6 +272,8 @@ static bool nrf52_errata_2(void) return false; case 0x06ul: return false; + default: + return false; } } #endif @@ -294,6 +305,8 @@ static bool nrf52_errata_3(void) return false; case 0x06ul: return false; + default: + return false; } } #endif @@ -325,6 +338,8 @@ static bool nrf52_errata_4(void) return false; case 0x06ul: return false; + default: + return false; } } #endif @@ -356,6 +371,8 @@ static bool nrf52_errata_7(void) return false; case 0x06ul: return false; + default: + return false; } } #endif @@ -387,6 +404,8 @@ static bool nrf52_errata_8(void) return false; case 0x06ul: return false; + default: + return false; } } #endif @@ -418,6 +437,8 @@ static bool nrf52_errata_9(void) return false; case 0x06ul: return false; + default: + return false; } } #endif @@ -449,6 +470,8 @@ static bool nrf52_errata_10(void) return false; case 0x06ul: return false; + default: + return false; } } #endif @@ -480,6 +503,8 @@ static bool nrf52_errata_11(void) return false; case 0x06ul: return false; + default: + return false; } } #endif @@ -522,6 +547,8 @@ static bool nrf52_errata_12(void) return true; case 0x06ul: return true; + default: + return true; } } #endif @@ -534,12 +561,8 @@ static bool nrf52_errata_15(void) #ifndef NRF52_SERIES return false; #else - #if defined (NRF52805_XXAA) || defined (DEVELOP_IN_NRF52805)\ - || defined (NRF52810_XXAA) || defined (DEVELOP_IN_NRF52810)\ - || defined (NRF52811_XXAA) || defined (DEVELOP_IN_NRF52811)\ - || defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ - || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832)\ - || defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) uint32_t var1; uint32_t var2; @@ -553,6 +576,12 @@ static bool nrf52_errata_15(void) var1 = *(uint32_t *)0x10000130ul; var2 = *(uint32_t *)0x10000134ul; } + #elif defined (NRF52805_XXAA) || defined (DEVELOP_IN_NRF52805)\ + || defined (NRF52810_XXAA) || defined (DEVELOP_IN_NRF52810)\ + || defined (NRF52811_XXAA) || defined (DEVELOP_IN_NRF52811)\ + || defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + uint32_t var1 = *(uint32_t *)0x10000130ul; + uint32_t var2 = *(uint32_t *)0x10000134ul; #endif #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) @@ -568,6 +597,8 @@ static bool nrf52_errata_15(void) return true; case 0x06ul: return true; + default: + return true; } } #endif @@ -584,6 +615,8 @@ static bool nrf52_errata_15(void) return false; case 0x03ul: return false; + default: + return false; } } #endif @@ -596,6 +629,8 @@ static bool nrf52_errata_15(void) return true; case 0x01ul: return true; + default: + return true; } } #endif @@ -606,6 +641,8 @@ static bool nrf52_errata_15(void) { case 0x00ul: return true; + default: + return true; } } #endif @@ -616,6 +653,8 @@ static bool nrf52_errata_15(void) { case 0x00ul: return true; + default: + return true; } } #endif @@ -647,6 +686,8 @@ static bool nrf52_errata_16(void) return false; case 0x06ul: return false; + default: + return false; } } #endif @@ -678,6 +719,8 @@ static bool nrf52_errata_17(void) return false; case 0x06ul: return false; + default: + return false; } } #endif @@ -690,14 +733,8 @@ static bool nrf52_errata_20(void) #ifndef NRF52_SERIES return false; #else - #if defined (NRF52805_XXAA) || defined (DEVELOP_IN_NRF52805)\ - || defined (NRF52810_XXAA) || defined (DEVELOP_IN_NRF52810)\ - || defined (NRF52811_XXAA) || defined (DEVELOP_IN_NRF52811)\ - || defined (NRF52820_XXAA) || defined (DEVELOP_IN_NRF52820)\ - || defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ - || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832)\ - || defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833)\ - || defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) uint32_t var1; uint32_t var2; @@ -711,6 +748,14 @@ static bool nrf52_errata_20(void) var1 = *(uint32_t *)0x10000130ul; var2 = *(uint32_t *)0x10000134ul; } + #elif defined (NRF52805_XXAA) || defined (DEVELOP_IN_NRF52805)\ + || defined (NRF52810_XXAA) || defined (DEVELOP_IN_NRF52810)\ + || defined (NRF52811_XXAA) || defined (DEVELOP_IN_NRF52811)\ + || defined (NRF52820_XXAA) || defined (DEVELOP_IN_NRF52820)\ + || defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833)\ + || defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + uint32_t var1 = *(uint32_t *)0x10000130ul; + uint32_t var2 = *(uint32_t *)0x10000134ul; #endif #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) @@ -726,6 +771,8 @@ static bool nrf52_errata_20(void) return true; case 0x06ul: return true; + default: + return true; } } #endif @@ -742,6 +789,8 @@ static bool nrf52_errata_20(void) return true; case 0x03ul: return true; + default: + return true; } } #endif @@ -754,6 +803,8 @@ static bool nrf52_errata_20(void) return true; case 0x01ul: return true; + default: + return true; } } #endif @@ -766,6 +817,8 @@ static bool nrf52_errata_20(void) return true; case 0x01ul: return true; + default: + return true; } } #endif @@ -776,6 +829,8 @@ static bool nrf52_errata_20(void) { case 0x00ul: return true; + default: + return true; } } #endif @@ -786,6 +841,8 @@ static bool nrf52_errata_20(void) { case 0x00ul: return true; + default: + return true; } } #endif @@ -798,6 +855,10 @@ static bool nrf52_errata_20(void) return true; case 0x01ul: return true; + case 0x02ul: + return true; + default: + return true; } } #endif @@ -829,6 +890,8 @@ static bool nrf52_errata_23(void) return false; case 0x06ul: return false; + default: + return false; } } #endif @@ -860,6 +923,8 @@ static bool nrf52_errata_24(void) return false; case 0x06ul: return false; + default: + return false; } } #endif @@ -891,6 +956,8 @@ static bool nrf52_errata_25(void) return false; case 0x06ul: return false; + default: + return false; } } #endif @@ -922,6 +989,8 @@ static bool nrf52_errata_26(void) return false; case 0x06ul: return false; + default: + return false; } } #endif @@ -953,6 +1022,8 @@ static bool nrf52_errata_27(void) return false; case 0x06ul: return false; + default: + return false; } } #endif @@ -984,6 +1055,8 @@ static bool nrf52_errata_28(void) return false; case 0x06ul: return false; + default: + return false; } } #endif @@ -1015,6 +1088,8 @@ static bool nrf52_errata_29(void) return false; case 0x06ul: return false; + default: + return false; } } #endif @@ -1046,6 +1121,8 @@ static bool nrf52_errata_30(void) return false; case 0x06ul: return false; + default: + return false; } } #endif @@ -1058,10 +1135,7 @@ static bool nrf52_errata_31(void) #ifndef NRF52_SERIES return false; #else - #if defined (NRF52805_XXAA) || defined (DEVELOP_IN_NRF52805)\ - || defined (NRF52810_XXAA) || defined (DEVELOP_IN_NRF52810)\ - || defined (NRF52811_XXAA) || defined (DEVELOP_IN_NRF52811)\ - || defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) uint32_t var1; uint32_t var2; @@ -1076,6 +1150,11 @@ static bool nrf52_errata_31(void) var1 = *(uint32_t *)0x10000130ul; var2 = *(uint32_t *)0x10000134ul; } + #elif defined (NRF52805_XXAA) || defined (DEVELOP_IN_NRF52805)\ + || defined (NRF52810_XXAA) || defined (DEVELOP_IN_NRF52810)\ + || defined (NRF52811_XXAA) || defined (DEVELOP_IN_NRF52811) + uint32_t var1 = *(uint32_t *)0x10000130ul; + uint32_t var2 = *(uint32_t *)0x10000134ul; #endif #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) @@ -1091,6 +1170,8 @@ static bool nrf52_errata_31(void) return true; case 0x06ul: return true; + default: + return true; } } #endif @@ -1103,6 +1184,8 @@ static bool nrf52_errata_31(void) return true; case 0x01ul: return true; + default: + return true; } } #endif @@ -1113,6 +1196,8 @@ static bool nrf52_errata_31(void) { case 0x00ul: return true; + default: + return true; } } #endif @@ -1123,6 +1208,8 @@ static bool nrf52_errata_31(void) { case 0x00ul: return true; + default: + return true; } } #endif @@ -1154,6 +1241,8 @@ static bool nrf52_errata_32(void) return false; case 0x06ul: return false; + default: + return false; } } #endif @@ -1185,6 +1274,8 @@ static bool nrf52_errata_33(void) return false; case 0x06ul: return false; + default: + return false; } } #endif @@ -1216,6 +1307,8 @@ static bool nrf52_errata_34(void) return false; case 0x06ul: return false; + default: + return false; } } #endif @@ -1247,6 +1340,8 @@ static bool nrf52_errata_35(void) return false; case 0x06ul: return false; + default: + return false; } } #endif @@ -1259,14 +1354,8 @@ static bool nrf52_errata_36(void) #ifndef NRF52_SERIES return false; #else - #if defined (NRF52805_XXAA) || defined (DEVELOP_IN_NRF52805)\ - || defined (NRF52810_XXAA) || defined (DEVELOP_IN_NRF52810)\ - || defined (NRF52811_XXAA) || defined (DEVELOP_IN_NRF52811)\ - || defined (NRF52820_XXAA) || defined (DEVELOP_IN_NRF52820)\ - || defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ - || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832)\ - || defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833)\ - || defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) uint32_t var1; uint32_t var2; @@ -1280,6 +1369,14 @@ static bool nrf52_errata_36(void) var1 = *(uint32_t *)0x10000130ul; var2 = *(uint32_t *)0x10000134ul; } + #elif defined (NRF52805_XXAA) || defined (DEVELOP_IN_NRF52805)\ + || defined (NRF52810_XXAA) || defined (DEVELOP_IN_NRF52810)\ + || defined (NRF52811_XXAA) || defined (DEVELOP_IN_NRF52811)\ + || defined (NRF52820_XXAA) || defined (DEVELOP_IN_NRF52820)\ + || defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833)\ + || defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + uint32_t var1 = *(uint32_t *)0x10000130ul; + uint32_t var2 = *(uint32_t *)0x10000134ul; #endif #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) @@ -1295,6 +1392,8 @@ static bool nrf52_errata_36(void) return true; case 0x06ul: return true; + default: + return true; } } #endif @@ -1311,6 +1410,8 @@ static bool nrf52_errata_36(void) return true; case 0x03ul: return true; + default: + return true; } } #endif @@ -1323,6 +1424,8 @@ static bool nrf52_errata_36(void) return true; case 0x01ul: return true; + default: + return true; } } #endif @@ -1335,6 +1438,8 @@ static bool nrf52_errata_36(void) return true; case 0x01ul: return true; + default: + return true; } } #endif @@ -1345,6 +1450,8 @@ static bool nrf52_errata_36(void) { case 0x00ul: return true; + default: + return true; } } #endif @@ -1355,6 +1462,8 @@ static bool nrf52_errata_36(void) { case 0x00ul: return true; + default: + return true; } } #endif @@ -1367,6 +1476,10 @@ static bool nrf52_errata_36(void) return true; case 0x01ul: return true; + case 0x02ul: + return true; + default: + return true; } } #endif @@ -1398,6 +1511,8 @@ static bool nrf52_errata_37(void) return false; case 0x06ul: return false; + default: + return false; } } #endif @@ -1429,6 +1544,8 @@ static bool nrf52_errata_38(void) return false; case 0x06ul: return false; + default: + return false; } } #endif @@ -1460,6 +1577,8 @@ static bool nrf52_errata_39(void) return false; case 0x06ul: return false; + default: + return false; } } #endif @@ -1491,6 +1610,8 @@ static bool nrf52_errata_40(void) return false; case 0x06ul: return false; + default: + return false; } } #endif @@ -1522,6 +1643,8 @@ static bool nrf52_errata_41(void) return false; case 0x06ul: return false; + default: + return false; } } #endif @@ -1553,6 +1676,8 @@ static bool nrf52_errata_42(void) return false; case 0x06ul: return false; + default: + return false; } } #endif @@ -1584,6 +1709,8 @@ static bool nrf52_errata_43(void) return false; case 0x06ul: return false; + default: + return false; } } #endif @@ -1615,6 +1742,8 @@ static bool nrf52_errata_44(void) return false; case 0x06ul: return false; + default: + return false; } } #endif @@ -1646,6 +1775,8 @@ static bool nrf52_errata_46(void) return false; case 0x06ul: return false; + default: + return false; } } #endif @@ -1677,6 +1808,8 @@ static bool nrf52_errata_47(void) return false; case 0x06ul: return false; + default: + return false; } } #endif @@ -1708,6 +1841,8 @@ static bool nrf52_errata_48(void) return false; case 0x06ul: return false; + default: + return false; } } #endif @@ -1739,6 +1874,8 @@ static bool nrf52_errata_49(void) return false; case 0x06ul: return false; + default: + return false; } } #endif @@ -1781,6 +1918,8 @@ static bool nrf52_errata_51(void) return true; case 0x06ul: return true; + default: + return true; } } #endif @@ -1794,8 +1933,7 @@ static bool nrf52_errata_54(void) return false; #else #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ - || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832)\ - || defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) uint32_t var1; uint32_t var2; @@ -1809,6 +1947,9 @@ static bool nrf52_errata_54(void) var1 = *(uint32_t *)0x10000130ul; var2 = *(uint32_t *)0x10000134ul; } + #elif defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + uint32_t var1 = *(uint32_t *)0x10000130ul; + uint32_t var2 = *(uint32_t *)0x10000134ul; #endif #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) @@ -1824,6 +1965,8 @@ static bool nrf52_errata_54(void) return true; case 0x06ul: return true; + default: + return true; } } #endif @@ -1840,6 +1983,8 @@ static bool nrf52_errata_54(void) return false; case 0x03ul: return false; + default: + return false; } } #endif @@ -1852,11 +1997,8 @@ static bool nrf52_errata_55(void) #ifndef NRF52_SERIES return false; #else - #if defined (NRF52820_XXAA) || defined (DEVELOP_IN_NRF52820)\ - || defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ - || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832)\ - || defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833)\ - || defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) uint32_t var1; uint32_t var2; @@ -1870,6 +2012,11 @@ static bool nrf52_errata_55(void) var1 = *(uint32_t *)0x10000130ul; var2 = *(uint32_t *)0x10000134ul; } + #elif defined (NRF52820_XXAA) || defined (DEVELOP_IN_NRF52820)\ + || defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833)\ + || defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + uint32_t var1 = *(uint32_t *)0x10000130ul; + uint32_t var2 = *(uint32_t *)0x10000134ul; #endif #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) @@ -1885,6 +2032,8 @@ static bool nrf52_errata_55(void) return true; case 0x06ul: return true; + default: + return true; } } #endif @@ -1901,6 +2050,8 @@ static bool nrf52_errata_55(void) return true; case 0x03ul: return true; + default: + return true; } } #endif @@ -1913,6 +2064,8 @@ static bool nrf52_errata_55(void) return true; case 0x01ul: return true; + default: + return true; } } #endif @@ -1925,6 +2078,10 @@ static bool nrf52_errata_55(void) return true; case 0x01ul: return true; + case 0x02ul: + return false; + default: + return false; } } #endif @@ -1956,6 +2113,8 @@ static bool nrf52_errata_57(void) return false; case 0x06ul: return false; + default: + return false; } } #endif @@ -1969,8 +2128,7 @@ static bool nrf52_errata_58(void) return false; #else #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ - || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832)\ - || defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) uint32_t var1; uint32_t var2; @@ -1984,6 +2142,9 @@ static bool nrf52_errata_58(void) var1 = *(uint32_t *)0x10000130ul; var2 = *(uint32_t *)0x10000134ul; } + #elif defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + uint32_t var1 = *(uint32_t *)0x10000130ul; + uint32_t var2 = *(uint32_t *)0x10000134ul; #endif #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) @@ -1999,6 +2160,8 @@ static bool nrf52_errata_58(void) return true; case 0x06ul: return true; + default: + return true; } } #endif @@ -2015,6 +2178,8 @@ static bool nrf52_errata_58(void) return false; case 0x03ul: return false; + default: + return false; } } #endif @@ -2046,6 +2211,8 @@ static bool nrf52_errata_62(void) return false; case 0x06ul: return false; + default: + return false; } } #endif @@ -2077,6 +2244,8 @@ static bool nrf52_errata_63(void) return false; case 0x06ul: return false; + default: + return false; } } #endif @@ -2119,6 +2288,8 @@ static bool nrf52_errata_64(void) return true; case 0x06ul: return true; + default: + return true; } } #endif @@ -2150,6 +2321,8 @@ static bool nrf52_errata_65(void) return false; case 0x06ul: return false; + default: + return false; } } #endif @@ -2162,14 +2335,8 @@ static bool nrf52_errata_66(void) #ifndef NRF52_SERIES return false; #else - #if defined (NRF52805_XXAA) || defined (DEVELOP_IN_NRF52805)\ - || defined (NRF52810_XXAA) || defined (DEVELOP_IN_NRF52810)\ - || defined (NRF52811_XXAA) || defined (DEVELOP_IN_NRF52811)\ - || defined (NRF52820_XXAA) || defined (DEVELOP_IN_NRF52820)\ - || defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ - || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832)\ - || defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833)\ - || defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) uint32_t var1; uint32_t var2; @@ -2183,6 +2350,14 @@ static bool nrf52_errata_66(void) var1 = *(uint32_t *)0x10000130ul; var2 = *(uint32_t *)0x10000134ul; } + #elif defined (NRF52805_XXAA) || defined (DEVELOP_IN_NRF52805)\ + || defined (NRF52810_XXAA) || defined (DEVELOP_IN_NRF52810)\ + || defined (NRF52811_XXAA) || defined (DEVELOP_IN_NRF52811)\ + || defined (NRF52820_XXAA) || defined (DEVELOP_IN_NRF52820)\ + || defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833)\ + || defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + uint32_t var1 = *(uint32_t *)0x10000130ul; + uint32_t var2 = *(uint32_t *)0x10000134ul; #endif #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) @@ -2198,6 +2373,8 @@ static bool nrf52_errata_66(void) return true; case 0x06ul: return true; + default: + return true; } } #endif @@ -2214,6 +2391,8 @@ static bool nrf52_errata_66(void) return true; case 0x03ul: return true; + default: + return true; } } #endif @@ -2226,6 +2405,8 @@ static bool nrf52_errata_66(void) return true; case 0x01ul: return true; + default: + return true; } } #endif @@ -2238,6 +2419,8 @@ static bool nrf52_errata_66(void) return true; case 0x01ul: return true; + default: + return true; } } #endif @@ -2248,6 +2431,8 @@ static bool nrf52_errata_66(void) { case 0x00ul: return true; + default: + return true; } } #endif @@ -2258,6 +2443,8 @@ static bool nrf52_errata_66(void) { case 0x00ul: return true; + default: + return true; } } #endif @@ -2270,6 +2457,10 @@ static bool nrf52_errata_66(void) return true; case 0x01ul: return true; + case 0x02ul: + return true; + default: + return true; } } #endif @@ -2312,6 +2503,8 @@ static bool nrf52_errata_67(void) return true; case 0x06ul: return true; + default: + return true; } } #endif @@ -2324,12 +2517,8 @@ static bool nrf52_errata_68(void) #ifndef NRF52_SERIES return false; #else - #if defined (NRF52805_XXAA) || defined (DEVELOP_IN_NRF52805)\ - || defined (NRF52810_XXAA) || defined (DEVELOP_IN_NRF52810)\ - || defined (NRF52811_XXAA) || defined (DEVELOP_IN_NRF52811)\ - || defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ - || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832)\ - || defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) uint32_t var1; uint32_t var2; @@ -2343,6 +2532,12 @@ static bool nrf52_errata_68(void) var1 = *(uint32_t *)0x10000130ul; var2 = *(uint32_t *)0x10000134ul; } + #elif defined (NRF52805_XXAA) || defined (DEVELOP_IN_NRF52805)\ + || defined (NRF52810_XXAA) || defined (DEVELOP_IN_NRF52810)\ + || defined (NRF52811_XXAA) || defined (DEVELOP_IN_NRF52811)\ + || defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + uint32_t var1 = *(uint32_t *)0x10000130ul; + uint32_t var2 = *(uint32_t *)0x10000134ul; #endif #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) @@ -2358,6 +2553,8 @@ static bool nrf52_errata_68(void) return true; case 0x06ul: return true; + default: + return true; } } #endif @@ -2374,6 +2571,8 @@ static bool nrf52_errata_68(void) return false; case 0x03ul: return false; + default: + return false; } } #endif @@ -2386,6 +2585,8 @@ static bool nrf52_errata_68(void) return true; case 0x01ul: return true; + default: + return true; } } #endif @@ -2396,6 +2597,8 @@ static bool nrf52_errata_68(void) { case 0x00ul: return true; + default: + return true; } } #endif @@ -2406,6 +2609,8 @@ static bool nrf52_errata_68(void) { case 0x00ul: return true; + default: + return true; } } #endif @@ -2437,6 +2642,8 @@ static bool nrf52_errata_70(void) return false; case 0x06ul: return false; + default: + return false; } } #endif @@ -2468,6 +2675,8 @@ static bool nrf52_errata_71(void) return false; case 0x06ul: return false; + default: + return false; } } #endif @@ -2510,6 +2719,8 @@ static bool nrf52_errata_72(void) return true; case 0x06ul: return true; + default: + return true; } } #endif @@ -2541,6 +2752,8 @@ static bool nrf52_errata_73(void) return false; case 0x06ul: return false; + default: + return false; } } #endif @@ -2583,6 +2796,8 @@ static bool nrf52_errata_74(void) return true; case 0x06ul: return true; + default: + return true; } } #endif @@ -2625,6 +2840,8 @@ static bool nrf52_errata_75(void) return true; case 0x06ul: return true; + default: + return true; } } #endif @@ -2667,6 +2884,8 @@ static bool nrf52_errata_76(void) return true; case 0x06ul: return true; + default: + return true; } } #endif @@ -2679,10 +2898,7 @@ static bool nrf52_errata_77(void) #ifndef NRF52_SERIES return false; #else - #if defined (NRF52805_XXAA) || defined (DEVELOP_IN_NRF52805)\ - || defined (NRF52810_XXAA) || defined (DEVELOP_IN_NRF52810)\ - || defined (NRF52811_XXAA) || defined (DEVELOP_IN_NRF52811)\ - || defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) uint32_t var1; uint32_t var2; @@ -2697,6 +2913,11 @@ static bool nrf52_errata_77(void) var1 = *(uint32_t *)0x10000130ul; var2 = *(uint32_t *)0x10000134ul; } + #elif defined (NRF52805_XXAA) || defined (DEVELOP_IN_NRF52805)\ + || defined (NRF52810_XXAA) || defined (DEVELOP_IN_NRF52810)\ + || defined (NRF52811_XXAA) || defined (DEVELOP_IN_NRF52811) + uint32_t var1 = *(uint32_t *)0x10000130ul; + uint32_t var2 = *(uint32_t *)0x10000134ul; #endif #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) @@ -2712,6 +2933,8 @@ static bool nrf52_errata_77(void) return true; case 0x06ul: return true; + default: + return true; } } #endif @@ -2724,6 +2947,8 @@ static bool nrf52_errata_77(void) return true; case 0x01ul: return true; + default: + return true; } } #endif @@ -2734,6 +2959,8 @@ static bool nrf52_errata_77(void) { case 0x00ul: return true; + default: + return true; } } #endif @@ -2744,6 +2971,8 @@ static bool nrf52_errata_77(void) { case 0x00ul: return true; + default: + return true; } } #endif @@ -2756,14 +2985,8 @@ static bool nrf52_errata_78(void) #ifndef NRF52_SERIES return false; #else - #if defined (NRF52805_XXAA) || defined (DEVELOP_IN_NRF52805)\ - || defined (NRF52810_XXAA) || defined (DEVELOP_IN_NRF52810)\ - || defined (NRF52811_XXAA) || defined (DEVELOP_IN_NRF52811)\ - || defined (NRF52820_XXAA) || defined (DEVELOP_IN_NRF52820)\ - || defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ - || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832)\ - || defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833)\ - || defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) uint32_t var1; uint32_t var2; @@ -2777,6 +3000,14 @@ static bool nrf52_errata_78(void) var1 = *(uint32_t *)0x10000130ul; var2 = *(uint32_t *)0x10000134ul; } + #elif defined (NRF52805_XXAA) || defined (DEVELOP_IN_NRF52805)\ + || defined (NRF52810_XXAA) || defined (DEVELOP_IN_NRF52810)\ + || defined (NRF52811_XXAA) || defined (DEVELOP_IN_NRF52811)\ + || defined (NRF52820_XXAA) || defined (DEVELOP_IN_NRF52820)\ + || defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833)\ + || defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + uint32_t var1 = *(uint32_t *)0x10000130ul; + uint32_t var2 = *(uint32_t *)0x10000134ul; #endif #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) @@ -2792,6 +3023,8 @@ static bool nrf52_errata_78(void) return true; case 0x06ul: return true; + default: + return true; } } #endif @@ -2808,6 +3041,8 @@ static bool nrf52_errata_78(void) return true; case 0x03ul: return true; + default: + return true; } } #endif @@ -2820,6 +3055,8 @@ static bool nrf52_errata_78(void) return true; case 0x01ul: return true; + default: + return true; } } #endif @@ -2832,6 +3069,8 @@ static bool nrf52_errata_78(void) return true; case 0x01ul: return true; + default: + return true; } } #endif @@ -2842,6 +3081,8 @@ static bool nrf52_errata_78(void) { case 0x00ul: return true; + default: + return true; } } #endif @@ -2852,6 +3093,8 @@ static bool nrf52_errata_78(void) { case 0x00ul: return true; + default: + return true; } } #endif @@ -2864,6 +3107,10 @@ static bool nrf52_errata_78(void) return true; case 0x01ul: return true; + case 0x02ul: + return true; + default: + return true; } } #endif @@ -2906,6 +3153,8 @@ static bool nrf52_errata_79(void) return true; case 0x06ul: return true; + default: + return true; } } #endif @@ -2918,12 +3167,8 @@ static bool nrf52_errata_81(void) #ifndef NRF52_SERIES return false; #else - #if defined (NRF52805_XXAA) || defined (DEVELOP_IN_NRF52805)\ - || defined (NRF52810_XXAA) || defined (DEVELOP_IN_NRF52810)\ - || defined (NRF52811_XXAA) || defined (DEVELOP_IN_NRF52811)\ - || defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ - || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832)\ - || defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) uint32_t var1; uint32_t var2; @@ -2937,6 +3182,12 @@ static bool nrf52_errata_81(void) var1 = *(uint32_t *)0x10000130ul; var2 = *(uint32_t *)0x10000134ul; } + #elif defined (NRF52805_XXAA) || defined (DEVELOP_IN_NRF52805)\ + || defined (NRF52810_XXAA) || defined (DEVELOP_IN_NRF52810)\ + || defined (NRF52811_XXAA) || defined (DEVELOP_IN_NRF52811)\ + || defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + uint32_t var1 = *(uint32_t *)0x10000130ul; + uint32_t var2 = *(uint32_t *)0x10000134ul; #endif #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) @@ -2952,6 +3203,8 @@ static bool nrf52_errata_81(void) return true; case 0x06ul: return true; + default: + return true; } } #endif @@ -2968,6 +3221,8 @@ static bool nrf52_errata_81(void) return true; case 0x03ul: return true; + default: + return true; } } #endif @@ -2980,6 +3235,8 @@ static bool nrf52_errata_81(void) return true; case 0x01ul: return true; + default: + return true; } } #endif @@ -2990,6 +3247,8 @@ static bool nrf52_errata_81(void) { case 0x00ul: return true; + default: + return true; } } #endif @@ -3000,6 +3259,8 @@ static bool nrf52_errata_81(void) { case 0x00ul: return true; + default: + return true; } } #endif @@ -3012,12 +3273,8 @@ static bool nrf52_errata_83(void) #ifndef NRF52_SERIES return false; #else - #if defined (NRF52805_XXAA) || defined (DEVELOP_IN_NRF52805)\ - || defined (NRF52810_XXAA) || defined (DEVELOP_IN_NRF52810)\ - || defined (NRF52811_XXAA) || defined (DEVELOP_IN_NRF52811)\ - || defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ - || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832)\ - || defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) uint32_t var1; uint32_t var2; @@ -3031,10 +3288,16 @@ static bool nrf52_errata_83(void) var1 = *(uint32_t *)0x10000130ul; var2 = *(uint32_t *)0x10000134ul; } - #endif - #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ - || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) - if (var1 == 0x06) + #elif defined (NRF52805_XXAA) || defined (DEVELOP_IN_NRF52805)\ + || defined (NRF52810_XXAA) || defined (DEVELOP_IN_NRF52810)\ + || defined (NRF52811_XXAA) || defined (DEVELOP_IN_NRF52811)\ + || defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + uint32_t var1 = *(uint32_t *)0x10000130ul; + uint32_t var2 = *(uint32_t *)0x10000134ul; + #endif + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + if (var1 == 0x06) { switch(var2) { @@ -3046,6 +3309,8 @@ static bool nrf52_errata_83(void) return true; case 0x06ul: return true; + default: + return true; } } #endif @@ -3062,6 +3327,8 @@ static bool nrf52_errata_83(void) return false; case 0x03ul: return false; + default: + return false; } } #endif @@ -3074,6 +3341,8 @@ static bool nrf52_errata_83(void) return true; case 0x01ul: return true; + default: + return true; } } #endif @@ -3084,6 +3353,8 @@ static bool nrf52_errata_83(void) { case 0x00ul: return true; + default: + return true; } } #endif @@ -3094,6 +3365,8 @@ static bool nrf52_errata_83(void) { case 0x00ul: return true; + default: + return true; } } #endif @@ -3136,6 +3409,8 @@ static bool nrf52_errata_84(void) return true; case 0x06ul: return true; + default: + return true; } } #endif @@ -3178,6 +3453,8 @@ static bool nrf52_errata_86(void) return true; case 0x06ul: return true; + default: + return true; } } #endif @@ -3190,11 +3467,8 @@ static bool nrf52_errata_87(void) #ifndef NRF52_SERIES return false; #else - #if defined (NRF52820_XXAA) || defined (DEVELOP_IN_NRF52820)\ - || defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ - || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832)\ - || defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833)\ - || defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) uint32_t var1; uint32_t var2; @@ -3208,6 +3482,11 @@ static bool nrf52_errata_87(void) var1 = *(uint32_t *)0x10000130ul; var2 = *(uint32_t *)0x10000134ul; } + #elif defined (NRF52820_XXAA) || defined (DEVELOP_IN_NRF52820)\ + || defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833)\ + || defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + uint32_t var1 = *(uint32_t *)0x10000130ul; + uint32_t var2 = *(uint32_t *)0x10000134ul; #endif #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) @@ -3223,6 +3502,8 @@ static bool nrf52_errata_87(void) return true; case 0x06ul: return true; + default: + return true; } } #endif @@ -3239,6 +3520,8 @@ static bool nrf52_errata_87(void) return true; case 0x03ul: return true; + default: + return true; } } #endif @@ -3251,6 +3534,8 @@ static bool nrf52_errata_87(void) return true; case 0x01ul: return true; + default: + return true; } } #endif @@ -3263,6 +3548,10 @@ static bool nrf52_errata_87(void) return true; case 0x01ul: return true; + case 0x02ul: + return true; + default: + return true; } } #endif @@ -3275,10 +3564,7 @@ static bool nrf52_errata_88(void) #ifndef NRF52_SERIES return false; #else - #if defined (NRF52805_XXAA) || defined (DEVELOP_IN_NRF52805)\ - || defined (NRF52810_XXAA) || defined (DEVELOP_IN_NRF52810)\ - || defined (NRF52811_XXAA) || defined (DEVELOP_IN_NRF52811)\ - || defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) uint32_t var1; uint32_t var2; @@ -3293,6 +3579,11 @@ static bool nrf52_errata_88(void) var1 = *(uint32_t *)0x10000130ul; var2 = *(uint32_t *)0x10000134ul; } + #elif defined (NRF52805_XXAA) || defined (DEVELOP_IN_NRF52805)\ + || defined (NRF52810_XXAA) || defined (DEVELOP_IN_NRF52810)\ + || defined (NRF52811_XXAA) || defined (DEVELOP_IN_NRF52811) + uint32_t var1 = *(uint32_t *)0x10000130ul; + uint32_t var2 = *(uint32_t *)0x10000134ul; #endif #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) @@ -3308,6 +3599,8 @@ static bool nrf52_errata_88(void) return true; case 0x06ul: return true; + default: + return true; } } #endif @@ -3320,6 +3613,8 @@ static bool nrf52_errata_88(void) return true; case 0x01ul: return true; + default: + return true; } } #endif @@ -3330,6 +3625,8 @@ static bool nrf52_errata_88(void) { case 0x00ul: return true; + default: + return true; } } #endif @@ -3340,6 +3637,8 @@ static bool nrf52_errata_88(void) { case 0x00ul: return true; + default: + return true; } } #endif @@ -3353,8 +3652,7 @@ static bool nrf52_errata_89(void) return false; #else #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ - || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832)\ - || defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) uint32_t var1; uint32_t var2; @@ -3368,6 +3666,9 @@ static bool nrf52_errata_89(void) var1 = *(uint32_t *)0x10000130ul; var2 = *(uint32_t *)0x10000134ul; } + #elif defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + uint32_t var1 = *(uint32_t *)0x10000130ul; + uint32_t var2 = *(uint32_t *)0x10000134ul; #endif #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) @@ -3383,6 +3684,8 @@ static bool nrf52_errata_89(void) return true; case 0x06ul: return true; + default: + return true; } } #endif @@ -3399,6 +3702,8 @@ static bool nrf52_errata_89(void) return false; case 0x03ul: return false; + default: + return false; } } #endif @@ -3441,6 +3746,8 @@ static bool nrf52_errata_91(void) return true; case 0x06ul: return true; + default: + return true; } } #endif @@ -3470,6 +3777,8 @@ static bool nrf52_errata_94(void) return false; case 0x03ul: return false; + default: + return false; } } #endif @@ -3499,6 +3808,8 @@ static bool nrf52_errata_96(void) return false; case 0x03ul: return false; + default: + return false; } } #endif @@ -3512,8 +3823,7 @@ static bool nrf52_errata_97(void) return false; #else #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ - || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832)\ - || defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) uint32_t var1; uint32_t var2; @@ -3527,6 +3837,9 @@ static bool nrf52_errata_97(void) var1 = *(uint32_t *)0x10000130ul; var2 = *(uint32_t *)0x10000134ul; } + #elif defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + uint32_t var1 = *(uint32_t *)0x10000130ul; + uint32_t var2 = *(uint32_t *)0x10000134ul; #endif #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) @@ -3542,6 +3855,8 @@ static bool nrf52_errata_97(void) return true; case 0x06ul: return true; + default: + return true; } } #endif @@ -3558,6 +3873,8 @@ static bool nrf52_errata_97(void) return false; case 0x03ul: return false; + default: + return false; } } #endif @@ -3587,6 +3904,8 @@ static bool nrf52_errata_98(void) return false; case 0x03ul: return false; + default: + return false; } } #endif @@ -3629,6 +3948,8 @@ static bool nrf52_errata_101(void) return true; case 0x06ul: return true; + default: + return true; } } #endif @@ -3671,6 +3992,8 @@ static bool nrf52_errata_102(void) return true; case 0x06ul: return false; + default: + return false; } } #endif @@ -3700,6 +4023,8 @@ static bool nrf52_errata_103(void) return false; case 0x03ul: return false; + default: + return false; } } #endif @@ -3729,6 +4054,8 @@ static bool nrf52_errata_104(void) return false; case 0x03ul: return false; + default: + return false; } } #endif @@ -3771,6 +4098,8 @@ static bool nrf52_errata_106(void) return true; case 0x06ul: return false; + default: + return false; } } #endif @@ -3813,6 +4142,8 @@ static bool nrf52_errata_107(void) return true; case 0x06ul: return false; + default: + return false; } } #endif @@ -3855,6 +4186,8 @@ static bool nrf52_errata_108(void) return true; case 0x06ul: return true; + default: + return true; } } #endif @@ -3897,6 +4230,8 @@ static bool nrf52_errata_109(void) return true; case 0x06ul: return true; + default: + return true; } } #endif @@ -3926,6 +4261,8 @@ static bool nrf52_errata_110(void) return false; case 0x03ul: return false; + default: + return false; } } #endif @@ -3955,6 +4292,8 @@ static bool nrf52_errata_111(void) return false; case 0x03ul: return false; + default: + return false; } } #endif @@ -3984,6 +4323,8 @@ static bool nrf52_errata_112(void) return false; case 0x03ul: return false; + default: + return false; } } #endif @@ -3997,8 +4338,7 @@ static bool nrf52_errata_113(void) return false; #else #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ - || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832)\ - || defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) uint32_t var1; uint32_t var2; @@ -4012,6 +4352,9 @@ static bool nrf52_errata_113(void) var1 = *(uint32_t *)0x10000130ul; var2 = *(uint32_t *)0x10000134ul; } + #elif defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + uint32_t var1 = *(uint32_t *)0x10000130ul; + uint32_t var2 = *(uint32_t *)0x10000134ul; #endif #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) @@ -4027,6 +4370,8 @@ static bool nrf52_errata_113(void) return true; case 0x06ul: return true; + default: + return true; } } #endif @@ -4043,6 +4388,8 @@ static bool nrf52_errata_113(void) return false; case 0x03ul: return false; + default: + return false; } } #endif @@ -4072,6 +4419,8 @@ static bool nrf52_errata_115(void) return false; case 0x03ul: return false; + default: + return false; } } #endif @@ -4101,6 +4450,8 @@ static bool nrf52_errata_116(void) return false; case 0x03ul: return false; + default: + return false; } } #endif @@ -4130,6 +4481,8 @@ static bool nrf52_errata_117(void) return false; case 0x03ul: return false; + default: + return false; } } #endif @@ -4159,6 +4512,8 @@ static bool nrf52_errata_118(void) return false; case 0x03ul: return false; + default: + return false; } } #endif @@ -4188,6 +4543,8 @@ static bool nrf52_errata_119(void) return false; case 0x03ul: return false; + default: + return false; } } #endif @@ -4217,6 +4574,8 @@ static bool nrf52_errata_120(void) return false; case 0x03ul: return false; + default: + return false; } } #endif @@ -4246,6 +4605,8 @@ static bool nrf52_errata_121(void) return false; case 0x03ul: return false; + default: + return false; } } #endif @@ -4275,6 +4636,8 @@ static bool nrf52_errata_122(void) return true; case 0x03ul: return true; + default: + return true; } } #endif @@ -4304,6 +4667,8 @@ static bool nrf52_errata_127(void) return false; case 0x03ul: return false; + default: + return false; } } #endif @@ -4333,6 +4698,8 @@ static bool nrf52_errata_128(void) return false; case 0x03ul: return false; + default: + return false; } } #endif @@ -4362,6 +4729,8 @@ static bool nrf52_errata_131(void) return false; case 0x03ul: return false; + default: + return false; } } #endif @@ -4404,6 +4773,8 @@ static bool nrf52_errata_132(void) return true; case 0x06ul: return true; + default: + return true; } } #endif @@ -4433,6 +4804,8 @@ static bool nrf52_errata_133(void) return false; case 0x03ul: return false; + default: + return false; } } #endif @@ -4462,6 +4835,8 @@ static bool nrf52_errata_134(void) return false; case 0x03ul: return false; + default: + return false; } } #endif @@ -4491,6 +4866,8 @@ static bool nrf52_errata_135(void) return false; case 0x03ul: return false; + default: + return false; } } #endif @@ -4503,14 +4880,8 @@ static bool nrf52_errata_136(void) #ifndef NRF52_SERIES return false; #else - #if defined (NRF52805_XXAA) || defined (DEVELOP_IN_NRF52805)\ - || defined (NRF52810_XXAA) || defined (DEVELOP_IN_NRF52810)\ - || defined (NRF52811_XXAA) || defined (DEVELOP_IN_NRF52811)\ - || defined (NRF52820_XXAA) || defined (DEVELOP_IN_NRF52820)\ - || defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ - || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832)\ - || defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833)\ - || defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) uint32_t var1; uint32_t var2; @@ -4524,6 +4895,14 @@ static bool nrf52_errata_136(void) var1 = *(uint32_t *)0x10000130ul; var2 = *(uint32_t *)0x10000134ul; } + #elif defined (NRF52805_XXAA) || defined (DEVELOP_IN_NRF52805)\ + || defined (NRF52810_XXAA) || defined (DEVELOP_IN_NRF52810)\ + || defined (NRF52811_XXAA) || defined (DEVELOP_IN_NRF52811)\ + || defined (NRF52820_XXAA) || defined (DEVELOP_IN_NRF52820)\ + || defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833)\ + || defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + uint32_t var1 = *(uint32_t *)0x10000130ul; + uint32_t var2 = *(uint32_t *)0x10000134ul; #endif #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) @@ -4539,6 +4918,8 @@ static bool nrf52_errata_136(void) return true; case 0x06ul: return true; + default: + return true; } } #endif @@ -4555,6 +4936,8 @@ static bool nrf52_errata_136(void) return true; case 0x03ul: return true; + default: + return true; } } #endif @@ -4567,6 +4950,8 @@ static bool nrf52_errata_136(void) return true; case 0x01ul: return true; + default: + return true; } } #endif @@ -4579,6 +4964,8 @@ static bool nrf52_errata_136(void) return true; case 0x01ul: return true; + default: + return true; } } #endif @@ -4589,6 +4976,8 @@ static bool nrf52_errata_136(void) { case 0x00ul: return true; + default: + return true; } } #endif @@ -4599,6 +4988,8 @@ static bool nrf52_errata_136(void) { case 0x00ul: return true; + default: + return true; } } #endif @@ -4611,6 +5002,10 @@ static bool nrf52_errata_136(void) return true; case 0x01ul: return true; + case 0x02ul: + return true; + default: + return true; } } #endif @@ -4653,6 +5048,8 @@ static bool nrf52_errata_138(void) return true; case 0x06ul: return true; + default: + return true; } } #endif @@ -4682,6 +5079,8 @@ static bool nrf52_errata_140(void) return false; case 0x03ul: return false; + default: + return false; } } #endif @@ -4724,6 +5123,8 @@ static bool nrf52_errata_141(void) return true; case 0x06ul: return true; + default: + return true; } } #endif @@ -4753,6 +5154,8 @@ static bool nrf52_errata_142(void) return false; case 0x03ul: return false; + default: + return false; } } #endif @@ -4766,8 +5169,7 @@ static bool nrf52_errata_143(void) return false; #else #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ - || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832)\ - || defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) uint32_t var1; uint32_t var2; @@ -4781,6 +5183,9 @@ static bool nrf52_errata_143(void) var1 = *(uint32_t *)0x10000130ul; var2 = *(uint32_t *)0x10000134ul; } + #elif defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + uint32_t var1 = *(uint32_t *)0x10000130ul; + uint32_t var2 = *(uint32_t *)0x10000134ul; #endif #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) @@ -4796,6 +5201,8 @@ static bool nrf52_errata_143(void) return true; case 0x06ul: return true; + default: + return true; } } #endif @@ -4812,6 +5219,8 @@ static bool nrf52_errata_143(void) return false; case 0x03ul: return false; + default: + return false; } } #endif @@ -4841,6 +5250,8 @@ static bool nrf52_errata_144(void) return false; case 0x03ul: return false; + default: + return false; } } #endif @@ -4870,6 +5281,8 @@ static bool nrf52_errata_145(void) return false; case 0x03ul: return false; + default: + return false; } } #endif @@ -4912,6 +5325,8 @@ static bool nrf52_errata_146(void) return true; case 0x06ul: return true; + default: + return true; } } #endif @@ -4941,6 +5356,8 @@ static bool nrf52_errata_147(void) return false; case 0x03ul: return false; + default: + return false; } } #endif @@ -4953,9 +5370,7 @@ static bool nrf52_errata_149(void) #ifndef NRF52_SERIES return false; #else - #if defined (NRF52810_XXAA) || defined (DEVELOP_IN_NRF52810)\ - || defined (NRF52811_XXAA) || defined (DEVELOP_IN_NRF52811)\ - || defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) uint32_t var1; uint32_t var2; @@ -4985,27 +5400,7 @@ static bool nrf52_errata_149(void) return true; case 0x06ul: return true; - } - } - #endif - #if defined (NRF52810_XXAA) || defined (DEVELOP_IN_NRF52810) - if (var1 == 0x0A) - { - switch(var2) - { - case 0x00ul: - return false; - case 0x01ul: - return true; - } - } - #endif - #if defined (NRF52811_XXAA) || defined (DEVELOP_IN_NRF52811) - if (var1 == 0x0E) - { - switch(var2) - { - case 0x00ul: + default: return true; } } @@ -5019,10 +5414,8 @@ static bool nrf52_errata_150(void) #ifndef NRF52_SERIES return false; #else - #if defined (NRF52810_XXAA) || defined (DEVELOP_IN_NRF52810)\ - || defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ - || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832)\ - || defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) uint32_t var1; uint32_t var2; @@ -5036,6 +5429,10 @@ static bool nrf52_errata_150(void) var1 = *(uint32_t *)0x10000130ul; var2 = *(uint32_t *)0x10000134ul; } + #elif defined (NRF52810_XXAA) || defined (DEVELOP_IN_NRF52810)\ + || defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + uint32_t var1 = *(uint32_t *)0x10000130ul; + uint32_t var2 = *(uint32_t *)0x10000134ul; #endif #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) @@ -5051,6 +5448,8 @@ static bool nrf52_errata_150(void) return true; case 0x06ul: return true; + default: + return true; } } #endif @@ -5067,6 +5466,8 @@ static bool nrf52_errata_150(void) return false; case 0x03ul: return false; + default: + return false; } } #endif @@ -5079,6 +5480,8 @@ static bool nrf52_errata_150(void) return true; case 0x01ul: return false; + default: + return false; } } #endif @@ -5108,6 +5511,8 @@ static bool nrf52_errata_151(void) return false; case 0x03ul: return false; + default: + return false; } } #endif @@ -5120,9 +5525,7 @@ static bool nrf52_errata_153(void) #ifndef NRF52_SERIES return false; #else - #if defined (NRF52820_XXAA) || defined (DEVELOP_IN_NRF52820)\ - || defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833)\ - || defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) uint32_t var1 = *(uint32_t *)0x10000130ul; uint32_t var2 = *(uint32_t *)0x10000134ul; #endif @@ -5139,29 +5542,7 @@ static bool nrf52_errata_153(void) return true; case 0x03ul: return true; - } - } - #endif - #if defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833) - if (var1 == 0x0D) - { - switch(var2) - { - case 0x00ul: - return false; - case 0x01ul: - return true; - } - } - #endif - #if defined (NRF52820_XXAA) || defined (DEVELOP_IN_NRF52820) - if (var1 == 0x10) - { - switch(var2) - { - case 0x00ul: - return true; - case 0x01ul: + default: return true; } } @@ -5192,6 +5573,8 @@ static bool nrf52_errata_154(void) return false; case 0x03ul: return false; + default: + return false; } } #endif @@ -5204,12 +5587,8 @@ static bool nrf52_errata_155(void) #ifndef NRF52_SERIES return false; #else - #if defined (NRF52805_XXAA) || defined (DEVELOP_IN_NRF52805)\ - || defined (NRF52810_XXAA) || defined (DEVELOP_IN_NRF52810)\ - || defined (NRF52811_XXAA) || defined (DEVELOP_IN_NRF52811)\ - || defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ - || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832)\ - || defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) uint32_t var1; uint32_t var2; @@ -5223,6 +5602,12 @@ static bool nrf52_errata_155(void) var1 = *(uint32_t *)0x10000130ul; var2 = *(uint32_t *)0x10000134ul; } + #elif defined (NRF52805_XXAA) || defined (DEVELOP_IN_NRF52805)\ + || defined (NRF52810_XXAA) || defined (DEVELOP_IN_NRF52810)\ + || defined (NRF52811_XXAA) || defined (DEVELOP_IN_NRF52811)\ + || defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + uint32_t var1 = *(uint32_t *)0x10000130ul; + uint32_t var2 = *(uint32_t *)0x10000134ul; #endif #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) @@ -5238,6 +5623,8 @@ static bool nrf52_errata_155(void) return true; case 0x06ul: return true; + default: + return true; } } #endif @@ -5254,6 +5641,8 @@ static bool nrf52_errata_155(void) return true; case 0x03ul: return true; + default: + return true; } } #endif @@ -5266,6 +5655,8 @@ static bool nrf52_errata_155(void) return true; case 0x01ul: return true; + default: + return true; } } #endif @@ -5276,6 +5667,8 @@ static bool nrf52_errata_155(void) { case 0x00ul: return true; + default: + return true; } } #endif @@ -5286,6 +5679,8 @@ static bool nrf52_errata_155(void) { case 0x00ul: return true; + default: + return true; } } #endif @@ -5298,12 +5693,8 @@ static bool nrf52_errata_156(void) #ifndef NRF52_SERIES return false; #else - #if defined (NRF52805_XXAA) || defined (DEVELOP_IN_NRF52805)\ - || defined (NRF52810_XXAA) || defined (DEVELOP_IN_NRF52810)\ - || defined (NRF52811_XXAA) || defined (DEVELOP_IN_NRF52811)\ - || defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ - || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832)\ - || defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) uint32_t var1; uint32_t var2; @@ -5317,6 +5708,12 @@ static bool nrf52_errata_156(void) var1 = *(uint32_t *)0x10000130ul; var2 = *(uint32_t *)0x10000134ul; } + #elif defined (NRF52805_XXAA) || defined (DEVELOP_IN_NRF52805)\ + || defined (NRF52810_XXAA) || defined (DEVELOP_IN_NRF52810)\ + || defined (NRF52811_XXAA) || defined (DEVELOP_IN_NRF52811)\ + || defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + uint32_t var1 = *(uint32_t *)0x10000130ul; + uint32_t var2 = *(uint32_t *)0x10000134ul; #endif #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) @@ -5332,6 +5729,8 @@ static bool nrf52_errata_156(void) return true; case 0x06ul: return true; + default: + return true; } } #endif @@ -5348,6 +5747,8 @@ static bool nrf52_errata_156(void) return false; case 0x03ul: return false; + default: + return false; } } #endif @@ -5360,6 +5761,8 @@ static bool nrf52_errata_156(void) return true; case 0x01ul: return true; + default: + return true; } } #endif @@ -5370,6 +5773,8 @@ static bool nrf52_errata_156(void) { case 0x00ul: return true; + default: + return true; } } #endif @@ -5380,6 +5785,8 @@ static bool nrf52_errata_156(void) { case 0x00ul: return true; + default: + return true; } } #endif @@ -5409,6 +5816,8 @@ static bool nrf52_errata_158(void) return false; case 0x03ul: return false; + default: + return false; } } #endif @@ -5438,6 +5847,8 @@ static bool nrf52_errata_160(void) return false; case 0x03ul: return false; + default: + return false; } } #endif @@ -5467,6 +5878,8 @@ static bool nrf52_errata_162(void) return false; case 0x03ul: return false; + default: + return false; } } #endif @@ -5509,6 +5922,8 @@ static bool nrf52_errata_163(void) return true; case 0x06ul: return false; + default: + return false; } } #endif @@ -5538,6 +5953,8 @@ static bool nrf52_errata_164(void) return false; case 0x03ul: return false; + default: + return false; } } #endif @@ -5567,6 +5984,8 @@ static bool nrf52_errata_166(void) return true; case 0x03ul: return true; + default: + return true; } } #endif @@ -5598,6 +6017,8 @@ static bool nrf52_errata_170(void) return true; case 0x03ul: return true; + default: + return true; } } #endif @@ -5610,6 +6031,8 @@ static bool nrf52_errata_170(void) return true; case 0x01ul: return true; + default: + return true; } } #endif @@ -5622,6 +6045,10 @@ static bool nrf52_errata_170(void) return true; case 0x01ul: return true; + case 0x02ul: + return false; + default: + return false; } } #endif @@ -5651,6 +6078,8 @@ static bool nrf52_errata_171(void) return true; case 0x03ul: return true; + default: + return true; } } #endif @@ -5680,6 +6109,8 @@ static bool nrf52_errata_172(void) return true; case 0x03ul: return true; + default: + return true; } } #endif @@ -5692,14 +6123,8 @@ static bool nrf52_errata_173(void) #ifndef NRF52_SERIES return false; #else - #if defined (NRF52805_XXAA) || defined (DEVELOP_IN_NRF52805)\ - || defined (NRF52810_XXAA) || defined (DEVELOP_IN_NRF52810)\ - || defined (NRF52811_XXAA) || defined (DEVELOP_IN_NRF52811)\ - || defined (NRF52820_XXAA) || defined (DEVELOP_IN_NRF52820)\ - || defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ - || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832)\ - || defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833)\ - || defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) uint32_t var1; uint32_t var2; @@ -5713,6 +6138,14 @@ static bool nrf52_errata_173(void) var1 = *(uint32_t *)0x10000130ul; var2 = *(uint32_t *)0x10000134ul; } + #elif defined (NRF52805_XXAA) || defined (DEVELOP_IN_NRF52805)\ + || defined (NRF52810_XXAA) || defined (DEVELOP_IN_NRF52810)\ + || defined (NRF52811_XXAA) || defined (DEVELOP_IN_NRF52811)\ + || defined (NRF52820_XXAA) || defined (DEVELOP_IN_NRF52820)\ + || defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833)\ + || defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + uint32_t var1 = *(uint32_t *)0x10000130ul; + uint32_t var2 = *(uint32_t *)0x10000134ul; #endif #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) @@ -5728,6 +6161,8 @@ static bool nrf52_errata_173(void) return true; case 0x06ul: return true; + default: + return true; } } #endif @@ -5744,6 +6179,8 @@ static bool nrf52_errata_173(void) return true; case 0x03ul: return true; + default: + return true; } } #endif @@ -5756,6 +6193,8 @@ static bool nrf52_errata_173(void) return true; case 0x01ul: return true; + default: + return true; } } #endif @@ -5768,6 +6207,8 @@ static bool nrf52_errata_173(void) return true; case 0x01ul: return true; + default: + return true; } } #endif @@ -5778,6 +6219,8 @@ static bool nrf52_errata_173(void) { case 0x00ul: return true; + default: + return true; } } #endif @@ -5788,6 +6231,8 @@ static bool nrf52_errata_173(void) { case 0x00ul: return true; + default: + return true; } } #endif @@ -5800,6 +6245,10 @@ static bool nrf52_errata_173(void) return true; case 0x01ul: return true; + case 0x02ul: + return true; + default: + return true; } } #endif @@ -5829,6 +6278,8 @@ static bool nrf52_errata_174(void) return true; case 0x03ul: return true; + default: + return true; } } #endif @@ -5841,14 +6292,8 @@ static bool nrf52_errata_176(void) #ifndef NRF52_SERIES return false; #else - #if defined (NRF52805_XXAA) || defined (DEVELOP_IN_NRF52805)\ - || defined (NRF52810_XXAA) || defined (DEVELOP_IN_NRF52810)\ - || defined (NRF52811_XXAA) || defined (DEVELOP_IN_NRF52811)\ - || defined (NRF52820_XXAA) || defined (DEVELOP_IN_NRF52820)\ - || defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ - || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832)\ - || defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833)\ - || defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) uint32_t var1; uint32_t var2; @@ -5862,6 +6307,14 @@ static bool nrf52_errata_176(void) var1 = *(uint32_t *)0x10000130ul; var2 = *(uint32_t *)0x10000134ul; } + #elif defined (NRF52805_XXAA) || defined (DEVELOP_IN_NRF52805)\ + || defined (NRF52810_XXAA) || defined (DEVELOP_IN_NRF52810)\ + || defined (NRF52811_XXAA) || defined (DEVELOP_IN_NRF52811)\ + || defined (NRF52820_XXAA) || defined (DEVELOP_IN_NRF52820)\ + || defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833)\ + || defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + uint32_t var1 = *(uint32_t *)0x10000130ul; + uint32_t var2 = *(uint32_t *)0x10000134ul; #endif #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) @@ -5877,6 +6330,8 @@ static bool nrf52_errata_176(void) return true; case 0x06ul: return true; + default: + return true; } } #endif @@ -5893,6 +6348,8 @@ static bool nrf52_errata_176(void) return true; case 0x03ul: return true; + default: + return true; } } #endif @@ -5905,6 +6362,8 @@ static bool nrf52_errata_176(void) return true; case 0x01ul: return true; + default: + return true; } } #endif @@ -5917,6 +6376,8 @@ static bool nrf52_errata_176(void) return true; case 0x01ul: return true; + default: + return true; } } #endif @@ -5927,6 +6388,8 @@ static bool nrf52_errata_176(void) { case 0x00ul: return true; + default: + return true; } } #endif @@ -5937,6 +6400,8 @@ static bool nrf52_errata_176(void) { case 0x00ul: return true; + default: + return true; } } #endif @@ -5949,6 +6414,10 @@ static bool nrf52_errata_176(void) return true; case 0x01ul: return true; + case 0x02ul: + return true; + default: + return true; } } #endif @@ -5991,6 +6460,8 @@ static bool nrf52_errata_178(void) return true; case 0x06ul: return true; + default: + return true; } } #endif @@ -6003,12 +6474,8 @@ static bool nrf52_errata_179(void) #ifndef NRF52_SERIES return false; #else - #if defined (NRF52805_XXAA) || defined (DEVELOP_IN_NRF52805)\ - || defined (NRF52810_XXAA) || defined (DEVELOP_IN_NRF52810)\ - || defined (NRF52811_XXAA) || defined (DEVELOP_IN_NRF52811)\ - || defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ - || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832)\ - || defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) uint32_t var1; uint32_t var2; @@ -6022,6 +6489,12 @@ static bool nrf52_errata_179(void) var1 = *(uint32_t *)0x10000130ul; var2 = *(uint32_t *)0x10000134ul; } + #elif defined (NRF52805_XXAA) || defined (DEVELOP_IN_NRF52805)\ + || defined (NRF52810_XXAA) || defined (DEVELOP_IN_NRF52810)\ + || defined (NRF52811_XXAA) || defined (DEVELOP_IN_NRF52811)\ + || defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + uint32_t var1 = *(uint32_t *)0x10000130ul; + uint32_t var2 = *(uint32_t *)0x10000134ul; #endif #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) @@ -6037,6 +6510,8 @@ static bool nrf52_errata_179(void) return true; case 0x06ul: return true; + default: + return true; } } #endif @@ -6053,6 +6528,8 @@ static bool nrf52_errata_179(void) return true; case 0x03ul: return true; + default: + return true; } } #endif @@ -6065,6 +6542,8 @@ static bool nrf52_errata_179(void) return true; case 0x01ul: return true; + default: + return true; } } #endif @@ -6075,6 +6554,8 @@ static bool nrf52_errata_179(void) { case 0x00ul: return true; + default: + return true; } } #endif @@ -6085,6 +6566,8 @@ static bool nrf52_errata_179(void) { case 0x00ul: return true; + default: + return true; } } #endif @@ -6114,6 +6597,8 @@ static bool nrf52_errata_180(void) return false; case 0x03ul: return false; + default: + return false; } } #endif @@ -6127,8 +6612,7 @@ static bool nrf52_errata_181(void) return false; #else #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ - || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832)\ - || defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) uint32_t var1; uint32_t var2; @@ -6142,6 +6626,9 @@ static bool nrf52_errata_181(void) var1 = *(uint32_t *)0x10000130ul; var2 = *(uint32_t *)0x10000134ul; } + #elif defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + uint32_t var1 = *(uint32_t *)0x10000130ul; + uint32_t var2 = *(uint32_t *)0x10000134ul; #endif #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) @@ -6157,6 +6644,8 @@ static bool nrf52_errata_181(void) return true; case 0x06ul: return false; + default: + return false; } } #endif @@ -6173,6 +6662,8 @@ static bool nrf52_errata_181(void) return false; case 0x03ul: return false; + default: + return false; } } #endif @@ -6204,6 +6695,8 @@ static bool nrf52_errata_182(void) return false; case 0x06ul: return true; + default: + return true; } } #endif @@ -6216,13 +6709,8 @@ static bool nrf52_errata_183(void) #ifndef NRF52_SERIES return false; #else - #if defined (NRF52810_XXAA) || defined (DEVELOP_IN_NRF52810)\ - || defined (NRF52811_XXAA) || defined (DEVELOP_IN_NRF52811)\ - || defined (NRF52820_XXAA) || defined (DEVELOP_IN_NRF52820)\ - || defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ - || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832)\ - || defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833)\ - || defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) uint32_t var1; uint32_t var2; @@ -6236,6 +6724,13 @@ static bool nrf52_errata_183(void) var1 = *(uint32_t *)0x10000130ul; var2 = *(uint32_t *)0x10000134ul; } + #elif defined (NRF52810_XXAA) || defined (DEVELOP_IN_NRF52810)\ + || defined (NRF52811_XXAA) || defined (DEVELOP_IN_NRF52811)\ + || defined (NRF52820_XXAA) || defined (DEVELOP_IN_NRF52820)\ + || defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833)\ + || defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + uint32_t var1 = *(uint32_t *)0x10000130ul; + uint32_t var2 = *(uint32_t *)0x10000134ul; #endif #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) @@ -6251,6 +6746,8 @@ static bool nrf52_errata_183(void) return true; case 0x06ul: return true; + default: + return true; } } #endif @@ -6267,6 +6764,8 @@ static bool nrf52_errata_183(void) return true; case 0x03ul: return true; + default: + return true; } } #endif @@ -6279,6 +6778,8 @@ static bool nrf52_errata_183(void) return true; case 0x01ul: return true; + default: + return true; } } #endif @@ -6291,6 +6792,8 @@ static bool nrf52_errata_183(void) return true; case 0x01ul: return true; + default: + return true; } } #endif @@ -6301,6 +6804,8 @@ static bool nrf52_errata_183(void) { case 0x00ul: return true; + default: + return true; } } #endif @@ -6313,6 +6818,10 @@ static bool nrf52_errata_183(void) return true; case 0x01ul: return true; + case 0x02ul: + return false; + default: + return false; } } #endif @@ -6347,6 +6856,8 @@ static bool nrf52_errata_184(void) return true; case 0x03ul: return true; + default: + return true; } } #endif @@ -6359,6 +6870,8 @@ static bool nrf52_errata_184(void) return true; case 0x01ul: return true; + default: + return true; } } #endif @@ -6371,6 +6884,8 @@ static bool nrf52_errata_184(void) return true; case 0x01ul: return true; + default: + return true; } } #endif @@ -6381,6 +6896,8 @@ static bool nrf52_errata_184(void) { case 0x00ul: return true; + default: + return true; } } #endif @@ -6391,6 +6908,8 @@ static bool nrf52_errata_184(void) { case 0x00ul: return true; + default: + return true; } } #endif @@ -6403,6 +6922,10 @@ static bool nrf52_errata_184(void) return true; case 0x01ul: return true; + case 0x02ul: + return true; + default: + return true; } } #endif @@ -6432,6 +6955,8 @@ static bool nrf52_errata_186(void) return false; case 0x03ul: return false; + default: + return false; } } #endif @@ -6463,6 +6988,8 @@ static bool nrf52_errata_187(void) return true; case 0x03ul: return true; + default: + return true; } } #endif @@ -6475,6 +7002,8 @@ static bool nrf52_errata_187(void) return true; case 0x01ul: return true; + default: + return true; } } #endif @@ -6487,6 +7016,10 @@ static bool nrf52_errata_187(void) return true; case 0x01ul: return true; + case 0x02ul: + return true; + default: + return true; } } #endif @@ -6516,6 +7049,8 @@ static bool nrf52_errata_189(void) return false; case 0x03ul: return false; + default: + return false; } } #endif @@ -6547,6 +7082,8 @@ static bool nrf52_errata_190(void) return true; case 0x03ul: return true; + default: + return true; } } #endif @@ -6559,6 +7096,8 @@ static bool nrf52_errata_190(void) return true; case 0x01ul: return true; + default: + return true; } } #endif @@ -6571,6 +7110,10 @@ static bool nrf52_errata_190(void) return true; case 0x01ul: return true; + case 0x02ul: + return false; + default: + return false; } } #endif @@ -6600,6 +7143,8 @@ static bool nrf52_errata_191(void) return true; case 0x03ul: return true; + default: + return true; } } #endif @@ -6612,10 +7157,8 @@ static bool nrf52_errata_192(void) #ifndef NRF52_SERIES return false; #else - #if defined (NRF52810_XXAA) || defined (DEVELOP_IN_NRF52810)\ - || defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ - || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832)\ - || defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) uint32_t var1; uint32_t var2; @@ -6629,6 +7172,10 @@ static bool nrf52_errata_192(void) var1 = *(uint32_t *)0x10000130ul; var2 = *(uint32_t *)0x10000134ul; } + #elif defined (NRF52810_XXAA) || defined (DEVELOP_IN_NRF52810)\ + || defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + uint32_t var1 = *(uint32_t *)0x10000130ul; + uint32_t var2 = *(uint32_t *)0x10000134ul; #endif #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) @@ -6644,6 +7191,8 @@ static bool nrf52_errata_192(void) return true; case 0x06ul: return true; + default: + return true; } } #endif @@ -6660,6 +7209,8 @@ static bool nrf52_errata_192(void) return true; case 0x03ul: return false; + default: + return false; } } #endif @@ -6672,6 +7223,8 @@ static bool nrf52_errata_192(void) return true; case 0x01ul: return false; + default: + return false; } } #endif @@ -6701,6 +7254,8 @@ static bool nrf52_errata_193(void) return true; case 0x03ul: return true; + default: + return true; } } #endif @@ -6713,11 +7268,8 @@ static bool nrf52_errata_194(void) #ifndef NRF52_SERIES return false; #else - #if defined (NRF52820_XXAA) || defined (DEVELOP_IN_NRF52820)\ - || defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ - || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832)\ - || defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833)\ - || defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) uint32_t var1; uint32_t var2; @@ -6731,6 +7283,11 @@ static bool nrf52_errata_194(void) var1 = *(uint32_t *)0x10000130ul; var2 = *(uint32_t *)0x10000134ul; } + #elif defined (NRF52820_XXAA) || defined (DEVELOP_IN_NRF52820)\ + || defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833)\ + || defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + uint32_t var1 = *(uint32_t *)0x10000130ul; + uint32_t var2 = *(uint32_t *)0x10000134ul; #endif #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) @@ -6746,6 +7303,8 @@ static bool nrf52_errata_194(void) return true; case 0x06ul: return true; + default: + return true; } } #endif @@ -6762,6 +7321,8 @@ static bool nrf52_errata_194(void) return true; case 0x03ul: return true; + default: + return true; } } #endif @@ -6774,6 +7335,8 @@ static bool nrf52_errata_194(void) return true; case 0x01ul: return true; + default: + return true; } } #endif @@ -6786,6 +7349,10 @@ static bool nrf52_errata_194(void) return true; case 0x01ul: return true; + case 0x02ul: + return false; + default: + return false; } } #endif @@ -6815,6 +7382,8 @@ static bool nrf52_errata_195(void) return true; case 0x03ul: return true; + default: + return true; } } #endif @@ -6827,11 +7396,8 @@ static bool nrf52_errata_196(void) #ifndef NRF52_SERIES return false; #else - #if defined (NRF52820_XXAA) || defined (DEVELOP_IN_NRF52820)\ - || defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ - || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832)\ - || defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833)\ - || defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) uint32_t var1; uint32_t var2; @@ -6845,6 +7411,11 @@ static bool nrf52_errata_196(void) var1 = *(uint32_t *)0x10000130ul; var2 = *(uint32_t *)0x10000134ul; } + #elif defined (NRF52820_XXAA) || defined (DEVELOP_IN_NRF52820)\ + || defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833)\ + || defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + uint32_t var1 = *(uint32_t *)0x10000130ul; + uint32_t var2 = *(uint32_t *)0x10000134ul; #endif #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) @@ -6860,6 +7431,8 @@ static bool nrf52_errata_196(void) return true; case 0x06ul: return true; + default: + return true; } } #endif @@ -6876,6 +7449,8 @@ static bool nrf52_errata_196(void) return true; case 0x03ul: return true; + default: + return true; } } #endif @@ -6888,6 +7463,8 @@ static bool nrf52_errata_196(void) return true; case 0x01ul: return true; + default: + return true; } } #endif @@ -6900,6 +7477,10 @@ static bool nrf52_errata_196(void) return true; case 0x01ul: return true; + case 0x02ul: + return false; + default: + return false; } } #endif @@ -6929,6 +7510,8 @@ static bool nrf52_errata_197(void) return true; case 0x03ul: return false; + default: + return false; } } #endif @@ -6958,6 +7541,8 @@ static bool nrf52_errata_198(void) return true; case 0x03ul: return true; + default: + return true; } } #endif @@ -6987,6 +7572,8 @@ static bool nrf52_errata_199(void) return true; case 0x03ul: return true; + default: + return true; } } #endif @@ -7016,6 +7603,8 @@ static bool nrf52_errata_200(void) return false; case 0x03ul: return false; + default: + return false; } } #endif @@ -7028,10 +7617,8 @@ static bool nrf52_errata_201(void) #ifndef NRF52_SERIES return false; #else - #if defined (NRF52810_XXAA) || defined (DEVELOP_IN_NRF52810)\ - || defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ - || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832)\ - || defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) uint32_t var1; uint32_t var2; @@ -7045,6 +7632,10 @@ static bool nrf52_errata_201(void) var1 = *(uint32_t *)0x10000130ul; var2 = *(uint32_t *)0x10000134ul; } + #elif defined (NRF52810_XXAA) || defined (DEVELOP_IN_NRF52810)\ + || defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + uint32_t var1 = *(uint32_t *)0x10000130ul; + uint32_t var2 = *(uint32_t *)0x10000134ul; #endif #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) @@ -7060,6 +7651,8 @@ static bool nrf52_errata_201(void) return true; case 0x06ul: return true; + default: + return true; } } #endif @@ -7076,6 +7669,8 @@ static bool nrf52_errata_201(void) return true; case 0x03ul: return false; + default: + return false; } } #endif @@ -7088,6 +7683,8 @@ static bool nrf52_errata_201(void) return true; case 0x01ul: return false; + default: + return false; } } #endif @@ -7117,6 +7714,8 @@ static bool nrf52_errata_202(void) return true; case 0x03ul: return false; + default: + return false; } } #endif @@ -7129,10 +7728,8 @@ static bool nrf52_errata_204(void) #ifndef NRF52_SERIES return false; #else - #if defined (NRF52810_XXAA) || defined (DEVELOP_IN_NRF52810)\ - || defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ - || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832)\ - || defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) uint32_t var1; uint32_t var2; @@ -7146,6 +7743,10 @@ static bool nrf52_errata_204(void) var1 = *(uint32_t *)0x10000130ul; var2 = *(uint32_t *)0x10000134ul; } + #elif defined (NRF52810_XXAA) || defined (DEVELOP_IN_NRF52810)\ + || defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + uint32_t var1 = *(uint32_t *)0x10000130ul; + uint32_t var2 = *(uint32_t *)0x10000134ul; #endif #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) @@ -7161,6 +7762,8 @@ static bool nrf52_errata_204(void) return true; case 0x06ul: return true; + default: + return true; } } #endif @@ -7177,6 +7780,8 @@ static bool nrf52_errata_204(void) return true; case 0x03ul: return true; + default: + return true; } } #endif @@ -7189,6 +7794,8 @@ static bool nrf52_errata_204(void) return true; case 0x01ul: return true; + default: + return true; } } #endif @@ -7218,6 +7825,8 @@ static bool nrf52_errata_208(void) return true; case 0x03ul: return true; + default: + return true; } } #endif @@ -7247,6 +7856,8 @@ static bool nrf52_errata_209(void) return true; case 0x03ul: return true; + default: + return true; } } #endif @@ -7259,14 +7870,8 @@ static bool nrf52_errata_210(void) #ifndef NRF52_SERIES return false; #else - #if defined (NRF52805_XXAA) || defined (DEVELOP_IN_NRF52805)\ - || defined (NRF52810_XXAA) || defined (DEVELOP_IN_NRF52810)\ - || defined (NRF52811_XXAA) || defined (DEVELOP_IN_NRF52811)\ - || defined (NRF52820_XXAA) || defined (DEVELOP_IN_NRF52820)\ - || defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ - || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832)\ - || defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833)\ - || defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) uint32_t var1; uint32_t var2; @@ -7280,6 +7885,14 @@ static bool nrf52_errata_210(void) var1 = *(uint32_t *)0x10000130ul; var2 = *(uint32_t *)0x10000134ul; } + #elif defined (NRF52805_XXAA) || defined (DEVELOP_IN_NRF52805)\ + || defined (NRF52810_XXAA) || defined (DEVELOP_IN_NRF52810)\ + || defined (NRF52811_XXAA) || defined (DEVELOP_IN_NRF52811)\ + || defined (NRF52820_XXAA) || defined (DEVELOP_IN_NRF52820)\ + || defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833)\ + || defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + uint32_t var1 = *(uint32_t *)0x10000130ul; + uint32_t var2 = *(uint32_t *)0x10000134ul; #endif #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) @@ -7295,6 +7908,8 @@ static bool nrf52_errata_210(void) return true; case 0x06ul: return true; + default: + return true; } } #endif @@ -7311,6 +7926,8 @@ static bool nrf52_errata_210(void) return true; case 0x03ul: return true; + default: + return true; } } #endif @@ -7323,6 +7940,8 @@ static bool nrf52_errata_210(void) return true; case 0x01ul: return true; + default: + return true; } } #endif @@ -7335,6 +7954,8 @@ static bool nrf52_errata_210(void) return true; case 0x01ul: return true; + default: + return true; } } #endif @@ -7345,6 +7966,8 @@ static bool nrf52_errata_210(void) { case 0x00ul: return true; + default: + return true; } } #endif @@ -7355,6 +7978,8 @@ static bool nrf52_errata_210(void) { case 0x00ul: return true; + default: + return true; } } #endif @@ -7367,6 +7992,10 @@ static bool nrf52_errata_210(void) return true; case 0x01ul: return true; + case 0x02ul: + return true; + default: + return true; } } #endif @@ -7374,49 +8003,16 @@ static bool nrf52_errata_210(void) #endif } -static bool nrf52_errata_212(void) +static bool nrf52_errata_211(void) { #ifndef NRF52_SERIES return false; #else - #if defined (NRF52805_XXAA) || defined (DEVELOP_IN_NRF52805)\ - || defined (NRF52810_XXAA) || defined (DEVELOP_IN_NRF52810)\ - || defined (NRF52811_XXAA) || defined (DEVELOP_IN_NRF52811)\ - || defined (NRF52820_XXAA) || defined (DEVELOP_IN_NRF52820)\ - || defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ - || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832)\ + #if defined (NRF52820_XXAA) || defined (DEVELOP_IN_NRF52820)\ || defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833)\ || defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) - uint32_t var1; - uint32_t var2; - - if (*(uint32_t *)0x10000130ul == 0xFFFFFFFF) - { - var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); - var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; - } - else - { - var1 = *(uint32_t *)0x10000130ul; - var2 = *(uint32_t *)0x10000134ul; - } - #endif - #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ - || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) - if (var1 == 0x06) - { - switch(var2) - { - case 0x03ul: - return false; - case 0x04ul: - return false; - case 0x05ul: - return true; - case 0x06ul: - return true; - } - } + uint32_t var1 = *(uint32_t *)0x10000130ul; + uint32_t var2 = *(uint32_t *)0x10000134ul; #endif #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) if (var1 == 0x08) @@ -7424,24 +8020,14 @@ static bool nrf52_errata_212(void) switch(var2) { case 0x00ul: - return true; - case 0x01ul: return false; + case 0x01ul: + return true; case 0x02ul: return true; case 0x03ul: return true; - } - } - #endif - #if defined (NRF52810_XXAA) || defined (DEVELOP_IN_NRF52810) - if (var1 == 0x0A) - { - switch(var2) - { - case 0x00ul: - return true; - case 0x01ul: + default: return true; } } @@ -7455,26 +8041,146 @@ static bool nrf52_errata_212(void) return true; case 0x01ul: return true; + default: + return true; } } #endif - #if defined (NRF52811_XXAA) || defined (DEVELOP_IN_NRF52811) - if (var1 == 0x0E) + #if defined (NRF52820_XXAA) || defined (DEVELOP_IN_NRF52820) + if (var1 == 0x10) { switch(var2) { case 0x00ul: return true; + case 0x01ul: + return true; + case 0x02ul: + return true; + default: + return true; } } #endif - #if defined (NRF52805_XXAA) || defined (DEVELOP_IN_NRF52805) - if (var1 == 0x0F) - { + return false; + #endif +} + +static bool nrf52_errata_212(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + uint32_t var1; + uint32_t var2; + + if (*(uint32_t *)0x10000130ul == 0xFFFFFFFF) + { + var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + } + else + { + var1 = *(uint32_t *)0x10000130ul; + var2 = *(uint32_t *)0x10000134ul; + } + #elif defined (NRF52805_XXAA) || defined (DEVELOP_IN_NRF52805)\ + || defined (NRF52810_XXAA) || defined (DEVELOP_IN_NRF52810)\ + || defined (NRF52811_XXAA) || defined (DEVELOP_IN_NRF52811)\ + || defined (NRF52820_XXAA) || defined (DEVELOP_IN_NRF52820)\ + || defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833)\ + || defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + uint32_t var1 = *(uint32_t *)0x10000130ul; + uint32_t var2 = *(uint32_t *)0x10000134ul; + #endif + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + if (var1 == 0x06) + { + switch(var2) + { + case 0x03ul: + return false; + case 0x04ul: + return false; + case 0x05ul: + return true; + case 0x06ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + if (var1 == 0x08) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return false; + case 0x02ul: + return true; + case 0x03ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52810_XXAA) || defined (DEVELOP_IN_NRF52810) + if (var1 == 0x0A) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833) + if (var1 == 0x0D) + { switch(var2) { case 0x00ul: return true; + case 0x01ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52811_XXAA) || defined (DEVELOP_IN_NRF52811) + if (var1 == 0x0E) + { + switch(var2) + { + case 0x00ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52805_XXAA) || defined (DEVELOP_IN_NRF52805) + if (var1 == 0x0F) + { + switch(var2) + { + case 0x00ul: + return true; + default: + return true; } } #endif @@ -7487,6 +8193,10 @@ static bool nrf52_errata_212(void) return true; case 0x01ul: return true; + case 0x02ul: + return false; + default: + return false; } } #endif @@ -7499,11 +8209,8 @@ static bool nrf52_errata_213(void) #ifndef NRF52_SERIES return false; #else - #if defined (NRF52810_XXAA) || defined (DEVELOP_IN_NRF52810)\ - || defined (NRF52811_XXAA) || defined (DEVELOP_IN_NRF52811)\ - || defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ - || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832)\ - || defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) uint32_t var1; uint32_t var2; @@ -7517,6 +8224,11 @@ static bool nrf52_errata_213(void) var1 = *(uint32_t *)0x10000130ul; var2 = *(uint32_t *)0x10000134ul; } + #elif defined (NRF52810_XXAA) || defined (DEVELOP_IN_NRF52810)\ + || defined (NRF52811_XXAA) || defined (DEVELOP_IN_NRF52811)\ + || defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + uint32_t var1 = *(uint32_t *)0x10000130ul; + uint32_t var2 = *(uint32_t *)0x10000134ul; #endif #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) @@ -7532,6 +8244,8 @@ static bool nrf52_errata_213(void) return true; case 0x06ul: return true; + default: + return true; } } #endif @@ -7548,6 +8262,8 @@ static bool nrf52_errata_213(void) return true; case 0x03ul: return true; + default: + return true; } } #endif @@ -7560,6 +8276,8 @@ static bool nrf52_errata_213(void) return true; case 0x01ul: return true; + default: + return true; } } #endif @@ -7570,6 +8288,8 @@ static bool nrf52_errata_213(void) { case 0x00ul: return true; + default: + return true; } } #endif @@ -7599,6 +8319,8 @@ static bool nrf52_errata_214(void) return true; case 0x03ul: return true; + default: + return true; } } #endif @@ -7628,6 +8350,8 @@ static bool nrf52_errata_215(void) return true; case 0x03ul: return true; + default: + return true; } } #endif @@ -7657,6 +8381,8 @@ static bool nrf52_errata_216(void) return true; case 0x03ul: return true; + default: + return true; } } #endif @@ -7684,6 +8410,8 @@ static bool nrf52_errata_217(void) return false; case 0x01ul: return true; + default: + return true; } } #endif @@ -7694,6 +8422,8 @@ static bool nrf52_errata_217(void) { case 0x00ul: return true; + default: + return true; } } #endif @@ -7704,6 +8434,8 @@ static bool nrf52_errata_217(void) { case 0x00ul: return true; + default: + return true; } } #endif @@ -7716,11 +8448,8 @@ static bool nrf52_errata_218(void) #ifndef NRF52_SERIES return false; #else - #if defined (NRF52820_XXAA) || defined (DEVELOP_IN_NRF52820)\ - || defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ - || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832)\ - || defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833)\ - || defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) uint32_t var1; uint32_t var2; @@ -7734,6 +8463,11 @@ static bool nrf52_errata_218(void) var1 = *(uint32_t *)0x10000130ul; var2 = *(uint32_t *)0x10000134ul; } + #elif defined (NRF52820_XXAA) || defined (DEVELOP_IN_NRF52820)\ + || defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833)\ + || defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + uint32_t var1 = *(uint32_t *)0x10000130ul; + uint32_t var2 = *(uint32_t *)0x10000134ul; #endif #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) @@ -7749,6 +8483,8 @@ static bool nrf52_errata_218(void) return true; case 0x06ul: return true; + default: + return true; } } #endif @@ -7765,6 +8501,8 @@ static bool nrf52_errata_218(void) return true; case 0x03ul: return true; + default: + return true; } } #endif @@ -7777,6 +8515,8 @@ static bool nrf52_errata_218(void) return true; case 0x01ul: return true; + default: + return true; } } #endif @@ -7789,6 +8529,10 @@ static bool nrf52_errata_218(void) return true; case 0x01ul: return true; + case 0x02ul: + return false; + default: + return false; } } #endif @@ -7801,14 +8545,8 @@ static bool nrf52_errata_219(void) #ifndef NRF52_SERIES return false; #else - #if defined (NRF52805_XXAA) || defined (DEVELOP_IN_NRF52805)\ - || defined (NRF52810_XXAA) || defined (DEVELOP_IN_NRF52810)\ - || defined (NRF52811_XXAA) || defined (DEVELOP_IN_NRF52811)\ - || defined (NRF52820_XXAA) || defined (DEVELOP_IN_NRF52820)\ - || defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ - || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832)\ - || defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833)\ - || defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) uint32_t var1; uint32_t var2; @@ -7822,6 +8560,14 @@ static bool nrf52_errata_219(void) var1 = *(uint32_t *)0x10000130ul; var2 = *(uint32_t *)0x10000134ul; } + #elif defined (NRF52805_XXAA) || defined (DEVELOP_IN_NRF52805)\ + || defined (NRF52810_XXAA) || defined (DEVELOP_IN_NRF52810)\ + || defined (NRF52811_XXAA) || defined (DEVELOP_IN_NRF52811)\ + || defined (NRF52820_XXAA) || defined (DEVELOP_IN_NRF52820)\ + || defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833)\ + || defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + uint32_t var1 = *(uint32_t *)0x10000130ul; + uint32_t var2 = *(uint32_t *)0x10000134ul; #endif #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) @@ -7837,6 +8583,8 @@ static bool nrf52_errata_219(void) return true; case 0x06ul: return true; + default: + return true; } } #endif @@ -7853,6 +8601,8 @@ static bool nrf52_errata_219(void) return true; case 0x03ul: return true; + default: + return true; } } #endif @@ -7865,6 +8615,8 @@ static bool nrf52_errata_219(void) return true; case 0x01ul: return true; + default: + return true; } } #endif @@ -7877,6 +8629,8 @@ static bool nrf52_errata_219(void) return true; case 0x01ul: return true; + default: + return true; } } #endif @@ -7887,6 +8641,8 @@ static bool nrf52_errata_219(void) { case 0x00ul: return true; + default: + return true; } } #endif @@ -7897,6 +8653,8 @@ static bool nrf52_errata_219(void) { case 0x00ul: return true; + default: + return true; } } #endif @@ -7909,6 +8667,10 @@ static bool nrf52_errata_219(void) return true; case 0x01ul: return true; + case 0x02ul: + return true; + default: + return true; } } #endif @@ -7951,6 +8713,52 @@ static bool nrf52_errata_220(void) return true; case 0x06ul: return true; + default: + return true; + } + } + #endif + return false; + #endif +} + +static bool nrf52_errata_223(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52820_XXAA) || defined (DEVELOP_IN_NRF52820)\ + || defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833) + uint32_t var1 = *(uint32_t *)0x10000130ul; + uint32_t var2 = *(uint32_t *)0x10000134ul; + #endif + #if defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833) + if (var1 == 0x0D) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52820_XXAA) || defined (DEVELOP_IN_NRF52820) + if (var1 == 0x10) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + case 0x02ul: + return true; + default: + return true; } } #endif @@ -7977,6 +8785,8 @@ static bool nrf52_errata_225(void) return true; case 0x01ul: return true; + default: + return true; } } #endif @@ -7989,6 +8799,10 @@ static bool nrf52_errata_225(void) return true; case 0x01ul: return true; + case 0x02ul: + return true; + default: + return true; } } #endif @@ -8022,6 +8836,8 @@ static bool nrf52_errata_228(void) return true; case 0x03ul: return true; + default: + return true; } } #endif @@ -8034,6 +8850,8 @@ static bool nrf52_errata_228(void) return false; case 0x01ul: return true; + default: + return true; } } #endif @@ -8046,6 +8864,8 @@ static bool nrf52_errata_228(void) return true; case 0x01ul: return true; + default: + return true; } } #endif @@ -8056,6 +8876,8 @@ static bool nrf52_errata_228(void) { case 0x00ul: return true; + default: + return true; } } #endif @@ -8068,6 +8890,10 @@ static bool nrf52_errata_228(void) return true; case 0x01ul: return true; + case 0x02ul: + return true; + default: + return true; } } #endif @@ -8093,6 +8919,10 @@ static bool nrf52_errata_230(void) return true; case 0x01ul: return false; + case 0x02ul: + return false; + default: + return false; } } #endif @@ -8118,6 +8948,204 @@ static bool nrf52_errata_231(void) return true; case 0x01ul: return false; + case 0x02ul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +static bool nrf52_errata_232(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52810_XXAA) || defined (DEVELOP_IN_NRF52810)\ + || defined (NRF52811_XXAA) || defined (DEVELOP_IN_NRF52811) + uint32_t var1 = *(uint32_t *)0x10000130ul; + uint32_t var2 = *(uint32_t *)0x10000134ul; + #endif + #if defined (NRF52810_XXAA) || defined (DEVELOP_IN_NRF52810) + if (var1 == 0x0A) + { + switch(var2) + { + case 0x00ul: + return false; + case 0x01ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52811_XXAA) || defined (DEVELOP_IN_NRF52811) + if (var1 == 0x0E) + { + switch(var2) + { + case 0x00ul: + return true; + default: + return true; + } + } + #endif + return false; + #endif +} + +static bool nrf52_errata_233(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52820_XXAA) || defined (DEVELOP_IN_NRF52820)\ + || defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833)\ + || defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + uint32_t var1 = *(uint32_t *)0x10000130ul; + uint32_t var2 = *(uint32_t *)0x10000134ul; + #endif + #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + if (var1 == 0x08) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + case 0x02ul: + return true; + case 0x03ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833) + if (var1 == 0x0D) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52820_XXAA) || defined (DEVELOP_IN_NRF52820) + if (var1 == 0x10) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + case 0x02ul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +static bool nrf52_errata_236(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52810_XXAA) || defined (DEVELOP_IN_NRF52810)\ + || defined (NRF52811_XXAA) || defined (DEVELOP_IN_NRF52811)\ + || defined (NRF52820_XXAA) || defined (DEVELOP_IN_NRF52820)\ + || defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833)\ + || defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + uint32_t var1 = *(uint32_t *)0x10000130ul; + uint32_t var2 = *(uint32_t *)0x10000134ul; + #endif + #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + if (var1 == 0x08) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + case 0x02ul: + return true; + case 0x03ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52810_XXAA) || defined (DEVELOP_IN_NRF52810) + if (var1 == 0x0A) + { + switch(var2) + { + case 0x00ul: + return false; + case 0x01ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833) + if (var1 == 0x0D) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52811_XXAA) || defined (DEVELOP_IN_NRF52811) + if (var1 == 0x0E) + { + switch(var2) + { + case 0x00ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52820_XXAA) || defined (DEVELOP_IN_NRF52820) + if (var1 == 0x10) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + case 0x02ul: + return false; + default: + return false; } } #endif @@ -8125,4 +9153,104 @@ static bool nrf52_errata_231(void) #endif } +static bool nrf52_errata_237(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52810_XXAA) || defined (DEVELOP_IN_NRF52810)\ + || defined (NRF52811_XXAA) || defined (DEVELOP_IN_NRF52811)\ + || defined (NRF52820_XXAA) || defined (DEVELOP_IN_NRF52820)\ + || defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833)\ + || defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + uint32_t var1 = *(uint32_t *)0x10000130ul; + uint32_t var2 = *(uint32_t *)0x10000134ul; + #endif + #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + if (var1 == 0x08) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + case 0x02ul: + return true; + case 0x03ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52810_XXAA) || defined (DEVELOP_IN_NRF52810) + if (var1 == 0x0A) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833) + if (var1 == 0x0D) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52811_XXAA) || defined (DEVELOP_IN_NRF52811) + if (var1 == 0x0E) + { + switch(var2) + { + case 0x00ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52820_XXAA) || defined (DEVELOP_IN_NRF52820) + if (var1 == 0x10) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + case 0x02ul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + +static bool nrf52_errata_248(void) +{ + #ifndef NRF52_SERIES + return false; + #else + return false; + #endif +} + #endif /* NRF52_ERRATAS_H */ diff --git a/mdk/nrf5340_application.h b/mdk/nrf5340_application.h index 7d53f5ebe9..32590ceb26 100644 --- a/mdk/nrf5340_application.h +++ b/mdk/nrf5340_application.h @@ -18,10 +18,10 @@ * @file nrf5340_application.h * @brief CMSIS HeaderFile * @version 1 - * @date 04. March 2020 - * @note Generated by SVDConv V3.3.25 on Wednesday, 04.03.2020 14:56:52 + * @date 14. August 2020 + * @note Generated by SVDConv V3.3.35 on Friday, 14.08.2020 15:02:14 * from File 'nrf5340_application.svd', - * last modified on Wednesday, 04.03.2020 13:56:45 + * last modified on Friday, 14.08.2020 13:02:07 */ @@ -128,7 +128,7 @@ typedef enum { #define __MPU_PRESENT 1 /*!< MPU present */ #define __FPU_PRESENT 1 /*!< FPU present */ #define __FPU_DP 0 /*!< Double Precision FPU */ -#define __SAU_REGION_PRESENT 0 /*!< SAU present */ +#define __SAUREGION_PRESENT 0 /*!< SAU region present */ /** @} */ /* End of group Configuration_of_CMSIS */ @@ -480,7 +480,7 @@ typedef struct { */ typedef struct { __IM uint32_t RESERVED; - __IOM uint32_t FORCEOFF; /*!< (@ 0x00000004) Force off power and clock in network core */ + __IOM uint32_t FORCEOFF; /*!< (@ 0x00000004) Force network core off */ } RESET_NETWORK_Type; /*!< Size = 8 (0x8) */ @@ -488,13 +488,15 @@ typedef struct { * @brief CTRLAPPERI_MAILBOX [MAILBOX] (Unspecified) */ typedef struct { - __IM uint32_t RXDATA; /*!< (@ 0x00000000) Data sent from the debugger to the CPU */ - __IM uint32_t RXSTATUS; /*!< (@ 0x00000004) Status to indicate if data sent from the debugger - to the CPU has been read */ + __IM uint32_t RXDATA; /*!< (@ 0x00000000) Data sent from the debugger to the CPU. */ + __IM uint32_t RXSTATUS; /*!< (@ 0x00000004) This register shows a status that indicates if + data sent from the debugger to the CPU has + been read. */ __IM uint32_t RESERVED[30]; - __IOM uint32_t TXDATA; /*!< (@ 0x00000080) Data sent from the CPU to the debugger */ - __IM uint32_t TXSTATUS; /*!< (@ 0x00000084) Status to indicate if data sent from the CPU - to the debugger has been read */ + __IOM uint32_t TXDATA; /*!< (@ 0x00000080) Data sent from the CPU to the debugger. */ + __IM uint32_t TXSTATUS; /*!< (@ 0x00000084) This register shows a status that indicates if + the data sent from the CPU to the debugger + has been read. */ } CTRLAPPERI_MAILBOX_Type; /*!< Size = 136 (0x88) */ @@ -502,9 +504,10 @@ typedef struct { * @brief CTRLAPPERI_ERASEPROTECT [ERASEPROTECT] (Unspecified) */ typedef struct { - __IOM uint32_t LOCK; /*!< (@ 0x00000000) Lock register ERASEPROTECT.DISABLE from being - written until next reset */ - __IOM uint32_t DISABLE; /*!< (@ 0x00000004) Disable ERASEPROTECT and perform ERASEALL */ + __IOM uint32_t LOCK; /*!< (@ 0x00000000) This register locks the ERASEPROTECT.DISABLE + register from being written until next reset. */ + __IOM uint32_t DISABLE; /*!< (@ 0x00000004) This register disables the ERASEPROTECT register + and performs an ERASEALL operation. */ } CTRLAPPERI_ERASEPROTECT_Type; /*!< Size = 8 (0x8) */ @@ -512,10 +515,10 @@ typedef struct { * @brief CTRLAPPERI_APPROTECT [APPROTECT] (Unspecified) */ typedef struct { - __IOM uint32_t LOCK; /*!< (@ 0x00000000) Lock register APPROTECT.DISABLE from being written - to until next reset */ - __IOM uint32_t DISABLE; /*!< (@ 0x00000004) Disable APPROTECT and enable debug access to - non-secure mode */ + __IOM uint32_t LOCK; /*!< (@ 0x00000000) This register locks the APPROTECT.DISABLE register + from being written to until next reset. */ + __IOM uint32_t DISABLE; /*!< (@ 0x00000004) This register disables the APPROTECT register + and enables debug access to non-secure mode. */ } CTRLAPPERI_APPROTECT_Type; /*!< Size = 8 (0x8) */ @@ -523,10 +526,10 @@ typedef struct { * @brief CTRLAPPERI_SECUREAPPROTECT [SECUREAPPROTECT] (Unspecified) */ typedef struct { - __IOM uint32_t LOCK; /*!< (@ 0x00000000) Lock register SECUREAPPROTECT.DISABLE from being - written until next reset */ - __IOM uint32_t DISABLE; /*!< (@ 0x00000004) Disable SECUREAPPROTECT and enable debug access - to secure mode */ + __IOM uint32_t LOCK; /*!< (@ 0x00000000) This register locks the SECUREAPPROTECT.DISABLE + register from being written until next reset. */ + __IOM uint32_t DISABLE; /*!< (@ 0x00000004) This register disables the SECUREAPPROTECT register + and enables debug access to secure mode. */ } CTRLAPPERI_SECUREAPPROTECT_Type; /*!< Size = 8 (0x8) */ @@ -936,7 +939,7 @@ typedef struct { __OM uint32_t NONCE0; /*!< (@ 0x00000010) Bits 31:0 of DMA NONCE */ __OM uint32_t NONCE1; /*!< (@ 0x00000014) Bits 63:32 of DMA NONCE */ __OM uint32_t NONCE2; /*!< (@ 0x00000018) Bits 95:64 of DMA NONCE */ - __IOM uint32_t ENABLE; /*!< (@ 0x0000001C) Enable stream cipher for XIP */ + __IOM uint32_t ENABLE; /*!< (@ 0x0000001C) Enable stream cipher for EasyDMA */ } QSPI_DMA_ENC_Type; /*!< Size = 32 (0x20) */ @@ -1458,16 +1461,15 @@ typedef struct { /*!< (@ 0x40005000) CLOCK_NS Str __IM uint32_t HFCLKRUN; /*!< (@ 0x00000408) Status indicating that HFCLKSTART task has been triggered */ __IM uint32_t HFCLKSTAT; /*!< (@ 0x0000040C) Status indicating which HFCLK128M/HFCLK64M source - is running Note: Value of this register - in any CLOCK instance reflects status only - due to configurations/actions in that CLOCK - instance. */ + is running This register value in any CLOCK + instance reflects status only due to configurations/action + in that CLOCK instance. */ __IM uint32_t RESERVED9; __IM uint32_t LFCLKRUN; /*!< (@ 0x00000414) Status indicating that LFCLKSTART task has been triggered */ __IM uint32_t LFCLKSTAT; /*!< (@ 0x00000418) Status indicating which LFCLK source is running - Note: Value of this register in any CLOCK - instance reflects status only due to configurations/action + This register value in any CLOCK instance + reflects status only due to configurations/actions in that CLOCK instance. */ __IM uint32_t LFCLKSRCCOPY; /*!< (@ 0x0000041C) Copy of LFCLKSRC register, set when LFCLKSTART task was triggered */ @@ -1486,12 +1488,12 @@ typedef struct { /*!< (@ 0x40005000) CLOCK_NS Str __IOM uint32_t HFCLKCTRL; /*!< (@ 0x00000558) HFCLK128M frequency configuration */ __IOM CLOCK_HFCLKAUDIO_Type HFCLKAUDIO; /*!< (@ 0x0000055C) Unspecified */ __IM uint32_t RESERVED13[4]; - __IM uint32_t HFCLKALWAYSRUN; /*!< (@ 0x00000570) Automatic or manual control of HFCLK128M/HFCLK64M */ - __IM uint32_t LFCLKALWAYSRUN; /*!< (@ 0x00000574) Automatic or manual control of LFCLK */ + __IOM uint32_t HFCLKALWAYSRUN; /*!< (@ 0x00000570) Automatic or manual control of HFCLK128M/HFCLK64M */ + __IOM uint32_t LFCLKALWAYSRUN; /*!< (@ 0x00000574) Automatic or manual control of LFCLK */ __IM uint32_t RESERVED14; - __IM uint32_t HFCLKAUDIOALWAYSRUN; /*!< (@ 0x0000057C) Automatic or manual control of HFCLKAUDIO */ + __IOM uint32_t HFCLKAUDIOALWAYSRUN; /*!< (@ 0x0000057C) Automatic or manual control of HFCLKAUDIO */ __IOM uint32_t HFCLK192MSRC; /*!< (@ 0x00000580) Clock source for HFCLK192M */ - __IM uint32_t HFCLK192MALWAYSRUN; /*!< (@ 0x00000584) Automatic or manual control of HFCLK192M */ + __IOM uint32_t HFCLK192MALWAYSRUN; /*!< (@ 0x00000584) Automatic or manual control of HFCLK192M */ __IM uint32_t RESERVED15[12]; __IOM uint32_t HFCLK192MCTRL; /*!< (@ 0x000005B8) HFCLK192M frequency configuration */ } NRF_CLOCK_Type; /*!< Size = 1468 (0x5bc) */ @@ -1509,8 +1511,8 @@ typedef struct { /*!< (@ 0x40005000) CLOCK_NS Str typedef struct { /*!< (@ 0x40005000) POWER_NS Structure */ __IM uint32_t RESERVED[30]; - __OM uint32_t TASKS_CONSTLAT; /*!< (@ 0x00000078) Enable constant latency mode */ - __OM uint32_t TASKS_LOWPWR; /*!< (@ 0x0000007C) Enable low power mode (variable latency) */ + __OM uint32_t TASKS_CONSTLAT; /*!< (@ 0x00000078) Enable Constant Latency mode */ + __OM uint32_t TASKS_LOWPWR; /*!< (@ 0x0000007C) Enable Low-Power mode (variable latency) */ __IM uint32_t RESERVED1[30]; __IOM uint32_t SUBSCRIBE_CONSTLAT; /*!< (@ 0x000000F8) Subscribe configuration for task CONSTLAT */ __IOM uint32_t SUBSCRIBE_LOWPWR; /*!< (@ 0x000000FC) Subscribe configuration for task LOWPWR */ @@ -1740,9 +1742,8 @@ typedef struct { /*!< (@ 0x40008000) TWIM0_NS Str __IM uint32_t RESERVED8[7]; __IOM uint32_t EVENTS_ERROR; /*!< (@ 0x00000124) TWI error */ __IM uint32_t RESERVED9[8]; - __IOM uint32_t EVENTS_SUSPENDED; /*!< (@ 0x00000148) Last byte has been sent out after the SUSPEND - task has been issued, TWI traffic is now - suspended. */ + __IOM uint32_t EVENTS_SUSPENDED; /*!< (@ 0x00000148) SUSPEND task has been issued, TWI traffic is + now suspended. */ __IOM uint32_t EVENTS_RXSTARTED; /*!< (@ 0x0000014C) Receive sequence started */ __IOM uint32_t EVENTS_TXSTARTED; /*!< (@ 0x00000150) Transmit sequence started */ __IM uint32_t RESERVED10[2]; @@ -1984,7 +1985,11 @@ typedef struct { /*!< (@ 0x5000D000) GPIOTE0_S St __IM uint32_t RESERVED6[65]; __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ - __IM uint32_t RESERVED7[129]; + __IM uint32_t RESERVED7[126]; + __IOM uint32_t LATENCY; /*!< (@ 0x00000504) Latency selection for Event mode (MODE=Event) + with rising or falling edge detection on + the pin. */ + __IM uint32_t RESERVED8[2]; __IOM uint32_t CONFIG[8]; /*!< (@ 0x00000510) Description collection: Configuration for OUT[n], SET[n], and CLR[n] tasks and IN[n] event */ } NRF_GPIOTE_Type; /*!< Size = 1328 (0x530) */ @@ -2489,9 +2494,9 @@ typedef struct { /*!< (@ 0x40026000) PDM0_NS Stru typedef struct { /*!< (@ 0x40028000) I2S0_NS Structure */ __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Starts continuous I2S transfer. Also starts MCK generator when this is enabled */ - __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stops I2S transfer. Also stops MCK generator. - Triggering this task will cause the event - STOPPED to be generated. */ + __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stops I2S transfer and MCK generator. Triggering + this task will cause the event STOPPED to + be generated. */ __IM uint32_t RESERVED[30]; __IOM uint32_t SUBSCRIBE_START; /*!< (@ 0x00000080) Subscribe configuration for task START */ __IOM uint32_t SUBSCRIBE_STOP; /*!< (@ 0x00000084) Subscribe configuration for task STOP */ @@ -2600,7 +2605,8 @@ typedef struct { /*!< (@ 0x4002B000) QSPI_NS Stru __IOM uint32_t SUBSCRIBE_DEACTIVATE; /*!< (@ 0x00000090) Subscribe configuration for task DEACTIVATE */ __IM uint32_t RESERVED1[27]; __IOM uint32_t EVENTS_READY; /*!< (@ 0x00000100) QSPI peripheral is ready. This event will be - generated as a response to any QSPI task. */ + generated as a response to all QSPI tasks + except DEACTIVATE. */ __IM uint32_t RESERVED2[31]; __IOM uint32_t PUBLISH_READY; /*!< (@ 0x00000180) Publish configuration for event READY */ __IM uint32_t RESERVED3[95]; @@ -3064,12 +3070,7 @@ typedef struct { /*!< (@ 0x40039000) NVMC_NS Stru __OM uint32_t ERASEALL; /*!< (@ 0x0000050C) Register for erasing all non-volatile user memory */ __IM uint32_t RESERVED4[3]; __IOM uint32_t ERASEPAGEPARTIALCFG; /*!< (@ 0x0000051C) Register for partial erase configuration */ - __IM uint32_t RESERVED5[8]; - __IOM uint32_t ICACHECNF; /*!< (@ 0x00000540) I-code cache configuration register */ - __IM uint32_t RESERVED6; - __IOM uint32_t IHIT; /*!< (@ 0x00000548) I-code cache hit counter */ - __IOM uint32_t IMISS; /*!< (@ 0x0000054C) I-code cache miss counter */ - __IM uint32_t RESERVED7[13]; + __IM uint32_t RESERVED5[25]; __IOM uint32_t CONFIGNS; /*!< (@ 0x00000584) Unspecified */ __OM uint32_t WRITEUICRNS; /*!< (@ 0x00000588) Non-secure APPROTECT enable register */ } NRF_NVMC_Type; /*!< Size = 1420 (0x58c) */ diff --git a/mdk/nrf5340_application.svd b/mdk/nrf5340_application.svd index 5317e3e756..92b9c595d3 100644 --- a/mdk/nrf5340_application.svd +++ b/mdk/nrf5340_application.svd @@ -323,9 +323,9 @@ POSSIBILITY OF SUCH DAMAGE. 31 - AAAA - AAAA - 0x41414141 + QKAA + QKAA + 0x514B4141 Unspecified @@ -888,7 +888,7 @@ POSSIBILITY OF SUCH DAMAGE. PALL Blocks debugger read/write access to all CPU registers and - memory mapped addresses Using any value not listed below will yield unexpected results. + memory mapped addresses Using any value except Unprotected will lead to the protection being enabled. 0 31 @@ -1027,7 +1027,7 @@ POSSIBILITY OF SUCH DAMAGE. PALL Blocks debugger read/write access to all secure CPU registers and secure memory - mapped addresses. Using any value not listed below will yield unexpected results. + mapped addresses. Using any value except Unprotected will lead to the protection being enabled. 0 31 @@ -1054,7 +1054,7 @@ POSSIBILITY OF SUCH DAMAGE. PALL - Blocks NVMC ERASEALL and CTRLAP ERASEALL functionality. Using any value not listed below will yield unexpected results. + Blocks NVMC ERASEALL and CTRLAP ERASEALL functionality. Using any value except Unprotected will lead to the protection being enabled. 0 31 @@ -1306,7 +1306,7 @@ POSSIBILITY OF SUCH DAMAGE. GLBEN - Enables or disables the CTI + Enables or disables the CTI. 0 0 @@ -1340,7 +1340,7 @@ POSSIBILITY OF SUCH DAMAGE. write Acknowledge - Clears the ctitrigout + Clears the ctitrigout. 1 @@ -1354,7 +1354,7 @@ POSSIBILITY OF SUCH DAMAGE. write Acknowledge - Clears the ctitrigout + Clears the ctitrigout. 1 @@ -1368,7 +1368,7 @@ POSSIBILITY OF SUCH DAMAGE. write Acknowledge - Clears the ctitrigout + Clears the ctitrigout. 1 @@ -1382,7 +1382,7 @@ POSSIBILITY OF SUCH DAMAGE. write Acknowledge - Clears the ctitrigout + Clears the ctitrigout. 1 @@ -1396,7 +1396,7 @@ POSSIBILITY OF SUCH DAMAGE. write Acknowledge - Clears the ctitrigout + Clears the ctitrigout. 1 @@ -1410,7 +1410,7 @@ POSSIBILITY OF SUCH DAMAGE. write Acknowledge - Clears the ctitrigout + Clears the ctitrigout. 1 @@ -1424,7 +1424,7 @@ POSSIBILITY OF SUCH DAMAGE. write Acknowledge - Clears the ctitrigout + Clears the ctitrigout. 1 @@ -1438,7 +1438,7 @@ POSSIBILITY OF SUCH DAMAGE. write Acknowledge - Clears the ctitrigout + Clears the ctitrigout. 1 @@ -1454,7 +1454,7 @@ POSSIBILITY OF SUCH DAMAGE. APPSET_0 - Application trigger event for channel 0 + Application trigger event for channel 0. 0 0 @@ -1481,7 +1481,7 @@ POSSIBILITY OF SUCH DAMAGE. APPSET_1 - Application trigger event for channel 1 + Application trigger event for channel 1. 1 1 @@ -1508,7 +1508,7 @@ POSSIBILITY OF SUCH DAMAGE. APPSET_2 - Application trigger event for channel 2 + Application trigger event for channel 2. 2 2 @@ -1535,7 +1535,7 @@ POSSIBILITY OF SUCH DAMAGE. APPSET_3 - Application trigger event for channel 3 + Application trigger event for channel 3. 3 3 @@ -1578,7 +1578,7 @@ POSSIBILITY OF SUCH DAMAGE. write Clear - Clears the event for channel 0 + Clears the event for channel 0. 1 @@ -1592,7 +1592,7 @@ POSSIBILITY OF SUCH DAMAGE. write Clear - Clears the event for channel 1 + Clears the event for channel 1. 1 @@ -1606,7 +1606,7 @@ POSSIBILITY OF SUCH DAMAGE. write Clear - Clears the event for channel 2 + Clears the event for channel 2. 1 @@ -1620,7 +1620,7 @@ POSSIBILITY OF SUCH DAMAGE. write Clear - Clears the event for channel 3 + Clears the event for channel 3. 1 @@ -1643,7 +1643,7 @@ POSSIBILITY OF SUCH DAMAGE. write Generate - Generates an event pulse on channel 0 + Generates an event pulse on channel 0. 1 @@ -1657,7 +1657,7 @@ POSSIBILITY OF SUCH DAMAGE. write Generate - Generates an event pulse on channel 1 + Generates an event pulse on channel 1. 1 @@ -1671,7 +1671,7 @@ POSSIBILITY OF SUCH DAMAGE. write Generate - Generates an event pulse on channel 2 + Generates an event pulse on channel 2. 1 @@ -1685,7 +1685,7 @@ POSSIBILITY OF SUCH DAMAGE. write Generate - Generates an event pulse on channel 3 + Generates an event pulse on channel 3. 1 @@ -1703,72 +1703,72 @@ POSSIBILITY OF SUCH DAMAGE. TRIGINEN_0 - Enables a cross trigger event to channel 0 when a ctitrigin input is activated + Enables a cross trigger event to channel 0 when a ctitrigin input is activated. 0 0 Disabled - Input trigger n events are ignored by channel 0 + Input trigger n events are ignored by channel 0. 0 Enabled - When an event is received on input trigger n (ctitrigin[n]) generate an event on channel 0 + When an event is received on input trigger n (ctitrigin[n]), generate an event on channel 0. 1 TRIGINEN_1 - Enables a cross trigger event to channel 1 when a ctitrigin input is activated + Enables a cross trigger event to channel 1 when a ctitrigin input is activated. 1 1 Disabled - Input trigger n events are ignored by channel 1 + Input trigger n events are ignored by channel 1. 0 Enabled - When an event is received on input trigger n (ctitrigin[n]) generate an event on channel 1 + When an event is received on input trigger n (ctitrigin[n]), generate an event on channel 1. 1 TRIGINEN_2 - Enables a cross trigger event to channel 2 when a ctitrigin input is activated + Enables a cross trigger event to channel 2 when a ctitrigin input is activated. 2 2 Disabled - Input trigger n events are ignored by channel 2 + Input trigger n events are ignored by channel 2. 0 Enabled - When an event is received on input trigger n (ctitrigin[n]) generate an event on channel 2 + When an event is received on input trigger n (ctitrigin[n]), generate an event on channel 2. 1 TRIGINEN_3 - Enables a cross trigger event to channel 3 when a ctitrigin input is activated + Enables a cross trigger event to channel 3 when a ctitrigin input is activated. 3 3 Disabled - Input trigger n events are ignored by channel 3 + Input trigger n events are ignored by channel 3. 0 Enabled - When an event is received on input trigger n (ctitrigin[n]) generate an event on channel 3 + When an event is received on input trigger n (ctitrigin[n]), generate an event on channel 3. 1 @@ -1786,72 +1786,72 @@ POSSIBILITY OF SUCH DAMAGE. TRIGOUTEN_0 - Enables a cross trigger event to ctitrigout when channel 0 when is activated + Enables a cross trigger event to ctitrigout when channel 0 is activated. 0 0 Disabled - Channel 0 is ignored by output trigger n + Channel 0 is ignored by output trigger n. 0 Enabled - When an event occur on channel 0, generate an event on output event n (ctitrigout[n]) + When an event occurs on channel 0, generate an event on output event n (ctitrigout[n]). 1 TRIGOUTEN_1 - Enables a cross trigger event to ctitrigout when channel 1 when is activated + Enables a cross trigger event to ctitrigout when channel 1 is activated. 1 1 Disabled - Channel 1 is ignored by output trigger n + Channel 1 is ignored by output trigger n. 0 Enabled - When an event occur on channel 1, generate an event on output event n (ctitrigout[n]) + When an event occurs on channel 1, generate an event on output event n (ctitrigout[n]). 1 TRIGOUTEN_2 - Enables a cross trigger event to ctitrigout when channel 2 when is activated + Enables a cross trigger event to ctitrigout when channel 2 is activated. 2 2 Disabled - Channel 2 is ignored by output trigger n + Channel 2 is ignored by output trigger n. 0 Enabled - When an event occur on channel 2, generate an event on output event n (ctitrigout[n]) + When an event occurs on channel 2, generate an event on output event n (ctitrigout[n]). 1 TRIGOUTEN_3 - Enables a cross trigger event to ctitrigout when channel 3 when is activated + Enables a cross trigger event to ctitrigout when channel 3 is activated. 3 3 Disabled - Channel 3 is ignored by output trigger n + Channel 3 is ignored by output trigger n. 0 Enabled - When an event occur on channel 3, generate an event on output event n (ctitrigout[n]) + When an event occurs on channel 3, generate an event on output event n (ctitrigout[n]). 1 @@ -1873,12 +1873,12 @@ POSSIBILITY OF SUCH DAMAGE. Active - Ctitrigin 0 is active + Ctitrigin 0 is active. 1 Inactive - Ctitrigin 0 is inactive + Ctitrigin 0 is inactive. 0 @@ -1891,12 +1891,12 @@ POSSIBILITY OF SUCH DAMAGE. Active - Ctitrigin 1 is active + Ctitrigin 1 is active. 1 Inactive - Ctitrigin 1 is inactive + Ctitrigin 1 is inactive. 0 @@ -1909,12 +1909,12 @@ POSSIBILITY OF SUCH DAMAGE. Active - Ctitrigin 2 is active + Ctitrigin 2 is active. 1 Inactive - Ctitrigin 2 is inactive + Ctitrigin 2 is inactive. 0 @@ -1927,12 +1927,12 @@ POSSIBILITY OF SUCH DAMAGE. Active - Ctitrigin 3 is active + Ctitrigin 3 is active. 1 Inactive - Ctitrigin 3 is inactive + Ctitrigin 3 is inactive. 0 @@ -1945,12 +1945,12 @@ POSSIBILITY OF SUCH DAMAGE. Active - Ctitrigin 4 is active + Ctitrigin 4 is active. 1 Inactive - Ctitrigin 4 is inactive + Ctitrigin 4 is inactive. 0 @@ -1963,12 +1963,12 @@ POSSIBILITY OF SUCH DAMAGE. Active - Ctitrigin 5 is active + Ctitrigin 5 is active. 1 Inactive - Ctitrigin 5 is inactive + Ctitrigin 5 is inactive. 0 @@ -1981,12 +1981,12 @@ POSSIBILITY OF SUCH DAMAGE. Active - Ctitrigin 6 is active + Ctitrigin 6 is active. 1 Inactive - Ctitrigin 6 is inactive + Ctitrigin 6 is inactive. 0 @@ -1999,12 +1999,12 @@ POSSIBILITY OF SUCH DAMAGE. Active - Ctitrigin 7 is active + Ctitrigin 7 is active. 1 Inactive - Ctitrigin 7 is inactive + Ctitrigin 7 is inactive. 0 @@ -2026,12 +2026,12 @@ POSSIBILITY OF SUCH DAMAGE. Active - Ctitrigout 0 is active + Ctitrigout 0 is active. 1 Inactive - Ctitrigout 0 is inactive + Ctitrigout 0 is inactive. 0 @@ -2044,12 +2044,12 @@ POSSIBILITY OF SUCH DAMAGE. Active - Ctitrigout 1 is active + Ctitrigout 1 is active. 1 Inactive - Ctitrigout 1 is inactive + Ctitrigout 1 is inactive. 0 @@ -2062,12 +2062,12 @@ POSSIBILITY OF SUCH DAMAGE. Active - Ctitrigout 2 is active + Ctitrigout 2 is active. 1 Inactive - Ctitrigout 2 is inactive + Ctitrigout 2 is inactive. 0 @@ -2080,12 +2080,12 @@ POSSIBILITY OF SUCH DAMAGE. Active - Ctitrigout 3 is active + Ctitrigout 3 is active. 1 Inactive - Ctitrigout 3 is inactive + Ctitrigout 3 is inactive. 0 @@ -2098,12 +2098,12 @@ POSSIBILITY OF SUCH DAMAGE. Active - Ctitrigout 4 is active + Ctitrigout 4 is active. 1 Inactive - Ctitrigout 4 is inactive + Ctitrigout 4 is inactive. 0 @@ -2116,12 +2116,12 @@ POSSIBILITY OF SUCH DAMAGE. Active - Ctitrigout 5 is active + Ctitrigout 5 is active. 1 Inactive - Ctitrigout 5 is inactive + Ctitrigout 5 is inactive. 0 @@ -2134,12 +2134,12 @@ POSSIBILITY OF SUCH DAMAGE. Active - Ctitrigout 6 is active + Ctitrigout 6 is active. 1 Inactive - Ctitrigout 6 is inactive + Ctitrigout 6 is inactive. 0 @@ -2152,12 +2152,12 @@ POSSIBILITY OF SUCH DAMAGE. Active - Ctitrigout 7 is active + Ctitrigout 7 is active. 1 Inactive - Ctitrigout 7 is inactive + Ctitrigout 7 is inactive. 0 @@ -2179,12 +2179,12 @@ POSSIBILITY OF SUCH DAMAGE. Active - Ctichin 0 is active + Ctichin 0 is active. 1 Inactive - Ctichin 0 is inactive + Ctichin 0 is inactive. 0 @@ -2197,12 +2197,12 @@ POSSIBILITY OF SUCH DAMAGE. Active - Ctichin 1 is active + Ctichin 1 is active. 1 Inactive - Ctichin 1 is inactive + Ctichin 1 is inactive. 0 @@ -2215,12 +2215,12 @@ POSSIBILITY OF SUCH DAMAGE. Active - Ctichin 2 is active + Ctichin 2 is active. 1 Inactive - Ctichin 2 is inactive + Ctichin 2 is inactive. 0 @@ -2233,12 +2233,12 @@ POSSIBILITY OF SUCH DAMAGE. Active - Ctichin 3 is active + Ctichin 3 is active. 1 Inactive - Ctichin 3 is inactive + Ctichin 3 is inactive. 0 @@ -2254,72 +2254,72 @@ POSSIBILITY OF SUCH DAMAGE. CTIGATEEN_0 - Enable ctichout0 + Enable ctichout0. 0 0 Enabled - Enable ctichout channel 0 propagation + Enable ctichout channel 0 propagation. 1 Disabled - Disable ctichout channel 0 propagation + Disable ctichout channel 0 propagation. 0 CTIGATEEN_1 - Enable ctichout1 + Enable ctichout1. 1 1 Enabled - Enable ctichout channel 1 propagation + Enable ctichout channel 1 propagation. 1 Disabled - Disable ctichout channel 1 propagation + Disable ctichout channel 1 propagation. 0 CTIGATEEN_2 - Enable ctichout2 + Enable ctichout2. 2 2 Enabled - Enable ctichout channel 2 propagation + Enable ctichout channel 2 propagation. 1 Disabled - Disable ctichout channel 2 propagation + Disable ctichout channel 2 propagation. 0 CTIGATEEN_3 - Enable ctichout3 + Enable ctichout3. 3 3 Enabled - Enable ctichout channel 3 propagation + Enable ctichout channel 3 propagation. 1 Disabled - Disable ctichout channel 3 propagation + Disable ctichout channel 3 propagation. 0 @@ -2335,7 +2335,7 @@ POSSIBILITY OF SUCH DAMAGE. Architecture - Contains the CTI device architecture + Contains the CTI device architecture. 0 0 @@ -2357,13 +2357,13 @@ POSSIBILITY OF SUCH DAMAGE. NUMTRIG - Number of ECT triggers available + Number of ECT triggers available. 8 15 NUMCH - Number of ECT channels available + Number of ECT channels available. 16 19 @@ -2379,13 +2379,13 @@ POSSIBILITY OF SUCH DAMAGE. MAJOR Major classification of the type of the debug component as specified in the ARM Architecture Specification for this - debug and trace component + debug and trace component. 0 3 Controller - Indicates that this component allows a debugger to control other components in a CoreSight SoC-400 system + Indicates that this component allows a debugger to control other components in a CoreSight SoC-400 system. 0b0100 @@ -2399,7 +2399,7 @@ POSSIBILITY OF SUCH DAMAGE. Crosstrigger - Indicates that this component is a sub-triggering component + Indicates that this component is a sub-triggering component. 0b0001 @@ -2415,7 +2415,7 @@ POSSIBILITY OF SUCH DAMAGE. DES_2 - Together, PIDR1.DES_0, PIDR2.DES_1, and PIDR4.DES_2 identify the designer of the component + Together, PIDR1.DES_0, PIDR2.DES_1, and PIDR4.DES_2 identify the designer of the component. 0 3 @@ -2428,7 +2428,7 @@ POSSIBILITY OF SUCH DAMAGE. SIZE - Always 0b0000. Indicates that the device only occupies 4KB of memory + Always 0b0000. Indicates that the device only occupies 4KB of memory. 4 7 @@ -2461,13 +2461,13 @@ POSSIBILITY OF SUCH DAMAGE. PART_0 - Bits[7:0] of the 12-bit part number of the component. The designer of the component assigns this part number + Bits[7:0] of the 12-bit part number of the component. The designer of the component assigns this part number. 0 7 PartnumberL - Indicates bits[7:0] of the part number of the component + Indicates bits[7:0] of the part number of the component. 0x21 @@ -2483,20 +2483,20 @@ POSSIBILITY OF SUCH DAMAGE. PART_1 - Bits[11:8] of the 12-bit part number of the component. The designer of the component assigns this part number + Bits[11:8] of the 12-bit part number of the component. The designer of the component assigns this part number. 0 3 PartnumberH - Indicates bits[11:8] of the part number of the component + Indicates bits[11:8] of the part number of the component. 0b1101 DES_0 - Together, PIDR1.DES_0, PIDR2.DES_1, and PIDR4.DES_2 identify the designer of the component + Together, PIDR1.DES_0, PIDR2.DES_1, and PIDR4.DES_2 identify the designer of the component. 4 7 @@ -2518,7 +2518,7 @@ POSSIBILITY OF SUCH DAMAGE. DES_1 - Together, PIDR1.DES_0, PIDR2.DES_1, and PIDR4.DES_2 identify the designer of the component + Together, PIDR1.DES_0, PIDR2.DES_1, and PIDR4.DES_2 identify the designer of the component. 0 2 @@ -2531,7 +2531,7 @@ POSSIBILITY OF SUCH DAMAGE. JEDEC - Always 1. Indicates that the JEDEC-assigned designer ID is used + Always 1. Indicates that the JEDEC-assigned designer ID is used. 3 3 @@ -2566,7 +2566,7 @@ POSSIBILITY OF SUCH DAMAGE. Unmodified - Indicates that the customer has not modified this component + Indicates that the customer has not modified this component. 0b000 @@ -2581,7 +2581,7 @@ POSSIBILITY OF SUCH DAMAGE. NoErrata - Indicates that there are no errata fixes to this component + Indicates that there are no errata fixes to this component. 0b000 @@ -2597,13 +2597,13 @@ POSSIBILITY OF SUCH DAMAGE. PRMBL_0 - Preamble[0]. Contains bits[7:0] of the component identification code + Preamble[0]. Contains bits[7:0] of the component identification code. 0 7 Value - Bits[7:0] of the identification code + Bits[7:0] of the identification code. 0x0D @@ -2619,13 +2619,13 @@ POSSIBILITY OF SUCH DAMAGE. PRMBL_1 - Preamble[1]. Contains bits[11:8] of the component identification code + Preamble[1]. Contains bits[11:8] of the component identification code. 0 3 Value - Bits[11:8] of the identification code + Bits[11:8] of the identification code. 0b0000 @@ -2639,7 +2639,7 @@ POSSIBILITY OF SUCH DAMAGE. Coresight - Indicates that the component is a CoreSight component + Indicates that the component is a CoreSight component. 0b1001 @@ -2655,13 +2655,13 @@ POSSIBILITY OF SUCH DAMAGE. PRMBL_2 - Preamble[2]. Contains bits[23:16] of the component identification code + Preamble[2]. Contains bits[23:16] of the component identification code. 0 7 Value - Bits[23:16] of the identification code + Bits[23:16] of the identification code. 0x05 @@ -2677,13 +2677,13 @@ POSSIBILITY OF SUCH DAMAGE. PRMBL_3 - Preamble[3]. Contains bits[31:24] of the component identification code + Preamble[3]. Contains bits[31:24] of the component identification code. 0 7 Value - Bits[31:24] of the identification code + Bits[31:24] of the identification code. 0xB1 @@ -6779,7 +6779,7 @@ POSSIBILITY OF SUCH DAMAGE. Disabled - Disable (use with xtal or low-swing external source) + Disable (use with crystal or low-swing external source) 0 @@ -8470,7 +8470,7 @@ POSSIBILITY OF SUCH DAMAGE. HFCLKSTAT - Status indicating which HFCLK128M/HFCLK64M source is running Note: Value of this register in any CLOCK instance reflects status only due to configurations/actions in that CLOCK instance. + Status indicating which HFCLK128M/HFCLK64M source is running This register value in any CLOCK instance reflects status only due to configurations/actions in that CLOCK instance. 0x40C read-only @@ -8558,7 +8558,7 @@ POSSIBILITY OF SUCH DAMAGE. LFCLKSTAT - Status indicating which LFCLK source is running Note: Value of this register in any CLOCK instance reflects status only due to configurations/actions in that CLOCK instance. + Status indicating which LFCLK source is running This register value in any CLOCK instance reflects status only due to configurations/actions in that CLOCK instance. 0x418 read-only @@ -8898,7 +8898,7 @@ POSSIBILITY OF SUCH DAMAGE. HCLK High frequency clock HCLK 0 - 0 + 1 Div1 @@ -8940,7 +8940,7 @@ POSSIBILITY OF SUCH DAMAGE. HFCLKALWAYSRUN Automatic or manual control of HFCLK128M/HFCLK64M 0x570 - read-only + read-write ALWAYSRUN @@ -8966,7 +8966,7 @@ POSSIBILITY OF SUCH DAMAGE. LFCLKALWAYSRUN Automatic or manual control of LFCLK 0x574 - read-only + read-write ALWAYSRUN @@ -8992,7 +8992,7 @@ POSSIBILITY OF SUCH DAMAGE. HFCLKAUDIOALWAYSRUN Automatic or manual control of HFCLKAUDIO 0x57C - read-only + read-write ALWAYSRUN @@ -9045,7 +9045,7 @@ POSSIBILITY OF SUCH DAMAGE. HFCLK192MALWAYSRUN Automatic or manual control of HFCLK192M 0x584 - read-only + read-write ALWAYSRUN @@ -9123,13 +9123,13 @@ POSSIBILITY OF SUCH DAMAGE. TASKS_CONSTLAT - Enable constant latency mode + Enable Constant Latency mode 0x78 write-only TASKS_CONSTLAT - Enable constant latency mode + Enable Constant Latency mode 0 0 @@ -9144,13 +9144,13 @@ POSSIBILITY OF SUCH DAMAGE. TASKS_LOWPWR - Enable low power mode (variable latency) + Enable Low-Power mode (variable latency) 0x7C write-only TASKS_LOWPWR - Enable low power mode (variable latency) + Enable Low-Power mode (variable latency) 0 0 @@ -9804,7 +9804,7 @@ POSSIBILITY OF SUCH DAMAGE. DIF - Reset due to wakeup from System OFF mode when wakeup is triggered by entering the debug interface mode + Reset due to wakeup from System OFF mode when wakeup is triggered by entering the Debug Interface mode 7 7 @@ -9820,78 +9820,6 @@ POSSIBILITY OF SUCH DAMAGE. - - LSREQ - Reset from network soft reset detected - 16 - 16 - - - NotDetected - Not detected - 0 - - - Detected - Detected - 1 - - - - - LLOCKUP - Reset from network CPU lockup detected - 17 - 17 - - - NotDetected - Not detected - 0 - - - Detected - Detected - 1 - - - - - LDOG - Reset from network watchdog timer detected - 18 - 18 - - - NotDetected - Not detected - 0 - - - Detected - Detected - 1 - - - - - MFORCEOFF - Force off reset from application core detected - 23 - 23 - - - NotDetected - Not detected - 0 - - - Detected - Detected - 1 - - - NFC Reset after wakeup from System OFF mode due to NFC field being detected @@ -9946,24 +9874,6 @@ POSSIBILITY OF SUCH DAMAGE. - - LCTRLAP - Reset from network CTRL-AP detected - 27 - 27 - - - NotDetected - Not detected - 0 - - - Detected - Detected - 1 - - - @@ -9974,25 +9884,25 @@ POSSIBILITY OF SUCH DAMAGE. 0x610 FORCEOFF - Force off power and clock in network core + Force network core off 0x004 read-write 0x00000001 FORCEOFF - Force off power and clock in network core + Force network core off 0 0 Release - Release force off signal + Release Force-OFF 0 Hold - Hold force off signal + Hold Force-OFF 1 @@ -10056,7 +9966,7 @@ POSSIBILITY OF SUCH DAMAGE. 0x400 RXDATA - Data sent from the debugger to the CPU + Data sent from the debugger to the CPU. 0x000 read-only 0x00000000 @@ -10071,7 +9981,7 @@ POSSIBILITY OF SUCH DAMAGE. RXSTATUS - Status to indicate if data sent from the debugger to the CPU has been read + This register shows a status that indicates if data sent from the debugger to the CPU has been read. 0x004 read-only 0x00000000 @@ -10098,7 +10008,7 @@ POSSIBILITY OF SUCH DAMAGE. TXDATA - Data sent from the CPU to the debugger + Data sent from the CPU to the debugger. 0x80 read-write 0x00000000 @@ -10113,7 +10023,7 @@ POSSIBILITY OF SUCH DAMAGE. TXSTATUS - Status to indicate if data sent from the CPU to the debugger has been read + This register shows a status that indicates if the data sent from the CPU to the debugger has been read. 0x84 read-only 0x00000000 @@ -10147,14 +10057,14 @@ POSSIBILITY OF SUCH DAMAGE. 0x500 LOCK - Lock register ERASEPROTECT.DISABLE from being written until next reset + This register locks the ERASEPROTECT.DISABLE register from being written until next reset. 0x000 read-writeonce 0x00000000 LOCK - Lock register ERASEPROTECT.DISABLE from being written until next reset + Lock ERASEPROTECT.DISABLE register from being written until next reset 0 0 @@ -10174,14 +10084,14 @@ POSSIBILITY OF SUCH DAMAGE. DISABLE - Disable ERASEPROTECT and perform ERASEALL + This register disables the ERASEPROTECT register and performs an ERASEALL operation. 0x004 read-write 0x00000000 KEY - The ERASEALL sequence will be initiated if value of KEY fields are non-zero and KEY fields match on both CPU and debugger side + The ERASEALL sequence is initiated if the value of the KEY fields are non-zero and the KEY fields match on both the CPU and debugger sides. 0 31 @@ -10196,14 +10106,14 @@ POSSIBILITY OF SUCH DAMAGE. 0x540 LOCK - Lock register APPROTECT.DISABLE from being written to until next reset + This register locks the APPROTECT.DISABLE register from being written to until next reset. 0x000 read-writeonce 0x00000000 LOCK - Lock register APPROTECT.DISABLE from being written to until next reset + Lock the APPROTECT.DISABLE register from being written to until next reset 0 0 @@ -10223,14 +10133,14 @@ POSSIBILITY OF SUCH DAMAGE. DISABLE - Disable APPROTECT and enable debug access to non-secure mode + This register disables the APPROTECT register and enables debug access to non-secure mode. 0x004 read-write 0x00000000 KEY - Disable APPROTECT and enable debug access to non-secure mode until next pin reset if KEY fields match The current APPROTECT value as configured from UICR is bypassed if value of KEY fields are non-zero and KEY fields match on both CPU and debugger side + Disable APPROTECT and enable debug access to non-secure mode until the next pin reset if the KEY fields match. The current APPROTECT value as configured from UICR is bypassed if the value of the KEY fields are non-zero and the KEY fields match on both the CPU and debugger sides. 0 31 @@ -10245,7 +10155,7 @@ POSSIBILITY OF SUCH DAMAGE. 0x548 LOCK - Lock register SECUREAPPROTECT.DISABLE from being written until next reset + This register locks the SECUREAPPROTECT.DISABLE register from being written until next reset. 0x000 read-writeonce 0x00000000 @@ -10272,14 +10182,14 @@ POSSIBILITY OF SUCH DAMAGE. DISABLE - Disable SECUREAPPROTECT and enable debug access to secure mode + This register disables the SECUREAPPROTECT register and enables debug access to secure mode. 0x004 read-write 0x00000000 KEY - Disable SECUREAPPROTECT and enable debug of secure mode until next pin reset if KEY fields match The current SECUREAPPROTECT value as configured from UICR is bypassed if value of KEY fields are non-zero and KEY fields match on both CPU and debugger side + Disable SECUREAPPROTECT and enable debug of secure mode until the next pin reset if the KEY fields match. The current SECUREAPPROTECT value as configured from UICR is bypassed if the value of the KEY fields are non-zero and the KEY fields match on both the CPU and debugger sides. 0 31 @@ -10294,55 +10204,55 @@ POSSIBILITY OF SUCH DAMAGE. 0x00000000 - DBGIFACEMODE - Status bit for device debug interface mode + APPROTECT + Status bit for access port protection in non-secure mode 0 0 Disabled - No debugger attached + Non-secure mode access port protection is currently disabled 0 Enabled - Debugger is attached and device is in debug interface mode + Non-secure mode access port protection is currently enabled 1 - APPROTECT - Status bit for access port protection in non-secure mode + SECUREAPPROTECT + Status bit for access port protection in secure mode 1 1 Disabled - Non-secure mode access port protection is currently disabled + Secure mode access port protection is currently disabled 0 Enabled - Non-secure mode access port protection is currently enabled + Secure mode access port protection is currently enabled 1 - SECUREAPPROTECT - Status bit for access port protection in secure mode + DBGIFACEMODE + Status bit for device debug interface mode 2 2 Disabled - Secure mode access port protection is currently disabled + No debugger attached 0 Enabled - Secure mode access port protection is currently enabled + Debugger is attached and device is in debug interface mode 1 @@ -13186,13 +13096,13 @@ POSSIBILITY OF SUCH DAMAGE. EVENTS_SUSPENDED - Last byte has been sent out after the SUSPEND task has been issued, TWI traffic is now suspended. + SUSPEND task has been issued, TWI traffic is now suspended. 0x148 read-write EVENTS_SUSPENDED - Last byte has been sent out after the SUSPEND task has been issued, TWI traffic is now suspended. + SUSPEND task has been issued, TWI traffic is now suspended. 0 0 @@ -19659,6 +19569,33 @@ POSSIBILITY OF SUCH DAMAGE. + + LATENCY + Latency selection for Event mode (MODE=Event) with rising or falling edge detection on the pin. + 0x504 + read-write + 0x00000001 + + + LATENCY + Latency setting + 0 + 0 + + + LowPower + Low power setting, for signals with minimum hold time tGPIOTE,HOLD,LP; refer to Electrical specification section + 0 + + + LowLatency + Low latency setting, for signals with minimum hold time tGPIOTE,HOLD,LL; refer to Electrical specification section + 1 + + + + + 0x8 0x4 @@ -35487,13 +35424,13 @@ POSSIBILITY OF SUCH DAMAGE. TASKS_STOP - Stops I2S transfer. Also stops MCK generator. Triggering this task will cause the event STOPPED to be generated. + Stops I2S transfer and MCK generator. Triggering this task will cause the event STOPPED to be generated. 0x004 write-only TASKS_STOP - Stops I2S transfer. Also stops MCK generator. Triggering this task will cause the event STOPPED to be generated. + Stops I2S transfer and MCK generator. Triggering this task will cause the event STOPPED to be generated. 0 0 @@ -39425,13 +39362,13 @@ POSSIBILITY OF SUCH DAMAGE. EVENTS_READY - QSPI peripheral is ready. This event will be generated as a response to any QSPI task. + QSPI peripheral is ready. This event will be generated as a response to all QSPI tasks except DEACTIVATE. 0x100 read-write EVENTS_READY - QSPI peripheral is ready. This event will be generated as a response to any QSPI task. + QSPI peripheral is ready. This event will be generated as a response to all QSPI tasks except DEACTIVATE. 0 0 @@ -40408,24 +40345,24 @@ POSSIBILITY OF SUCH DAMAGE. ENABLE - Enable stream cipher for XIP + Enable stream cipher for EasyDMA 0x01C read-write ENABLE - Enable or disable stream cipher for XIP + Enable or disable stream cipher for EasyDMA 0 0 Disabled - Disable stream cipher for QSPI XIP + Disable stream cipher for QSPI EasyDMA 0 Enabled - Enable stream cipher for QSPI XIP + Enable stream cipher for QSPI EasyDMA 1 @@ -40475,16 +40412,11 @@ POSSIBILITY OF SUCH DAMAGE. Mode 0: Data are captured on the clock rising edge and data is output on a falling edge. Base level of clock is 0 (CPOL=0, CPHA=0). 0 - - MODE3 - Mode 3: Data are captured on the clock falling edge and data is output on a rising edge. Base level of clock is 1 (CPOL=1, CPHA=1). - 1 - SCKFREQ - SCK frequency is given as 96 MHz / (SCKFREQ + 1). + SCK frequency is derived from PCLK192M with SCK frequency = PCLK192M / (2*(SCKFREQ + 1)). 28 31 @@ -40868,15 +40800,7 @@ POSSIBILITY OF SUCH DAMAGE. SPI interface timing. 0x640 read-write - 0x00000200 - - - RXDELAY - Timing related to sampling of the input serial data. The value of RXDELAY specifies the number of 192 MHz cycles (5.208 ns) delay from the the rising edge of the SPI Clock (SCK) until the input serial data is sampled. As en example, if set to 0 the input serial data is sampled on the rising edge of SCK. - 8 - 10 - - + 0x00000600 @@ -45313,53 +45237,53 @@ POSSIBILITY OF SUCH DAMAGE. REPORTPER - Specifies the number of samples to be accumulated in the ACC register before the REPORTRDY and DBLRDY events can be generated + Specifies the number of samples to be accumulated in the ACC register before the REPORTRDY and DBLRDY events can be generated. 0 3 10Smpl - 10 samples / report + 10 samples/report 0 40Smpl - 40 samples / report + 40 samples/report 1 80Smpl - 80 samples / report + 80 samples/report 2 120Smpl - 120 samples / report + 120 samples/report 3 160Smpl - 160 samples / report + 160 samples/report 4 200Smpl - 200 samples / report + 200 samples/report 5 240Smpl - 240 samples / report + 240 samples/report 6 280Smpl - 280 samples / report + 280 samples/report 7 1Smpl - 1 sample / report + 1 sample/report 8 @@ -45375,7 +45299,7 @@ POSSIBILITY OF SUCH DAMAGE. ACC - Register accumulating all valid samples (not double transition) read from the SAMPLE register + Register accumulating all valid samples (not double transition) read from the SAMPLE register. 0 31 @@ -51634,7 +51558,7 @@ POSSIBILITY OF SUCH DAMAGE. WEN - Program memory access mode. It is strongly recommended to only activate erase and write modes when they are actively used. Enabling write or erase will invalidate the cache and keep it invalidated. + Program memory access mode. It is strongly recommended to only activate erase and write modes when they are actively used. 0 2 @@ -51705,82 +51629,6 @@ POSSIBILITY OF SUCH DAMAGE. - - ICACHECNF - I-code cache configuration register - 0x540 - read-write - 0x00000000 - - - - CACHEEN - Cache enable - 0 - 0 - - - Disabled - Disable cache. Invalidates all cache entries. - 0 - - - Enabled - Enable cache - 1 - - - - - CACHEPROFEN - Cache profiling enable - 8 - 8 - - - Disabled - Disable cache profiling - 0 - - - Enabled - Enable cache profiling - 1 - - - - - - - IHIT - I-code cache hit counter - 0x548 - read-write - - - - HITS - Number of cache hits Write zero to clear - 0 - 31 - - - - - IMISS - I-code cache miss counter - 0x54C - read-write - - - - MISSES - Number of cache misses Write zero to clear - 0 - 31 - - - CONFIGNS Unspecified @@ -51789,7 +51637,7 @@ POSSIBILITY OF SUCH DAMAGE. WEN - Program memory access mode. It is strongly recommended to only activate erase and write modes when they are actively used. Enabling write or erase will invalidate the cache and keep it invalidated. + Program memory access mode. It is strongly recommended to only activate erase and write modes when they are actively used. 0 1 @@ -57876,31 +57724,11 @@ POSSIBILITY OF SUCH DAMAGE. High drive '0', disconnect '1' (normally used for wired-and connections) 7 - - E0S1 - Extra high drive '0', standard '1' - 9 - - - S0E1 - Standard '0', extra high drive '1' - 10 - E0E1 Extra high drive '0', extra high drive '1' 11 - - D0E1 - Disconnect '0', extra high drive '1' (normally used for wired-or connections) - 13 - - - E0D1 - Extra high drive '0', disconnect '1' (normally used for wired-and connections) - 15 - diff --git a/mdk/nrf5340_application_bitfields.h b/mdk/nrf5340_application_bitfields.h index 1c547b1983..094507730f 100644 --- a/mdk/nrf5340_application_bitfields.h +++ b/mdk/nrf5340_application_bitfields.h @@ -654,7 +654,7 @@ POSSIBILITY OF SUCH DAMAGE. #define CLOCK_HFCLKRUN_STATUS_Triggered (1UL) /*!< Task triggered */ /* Register: CLOCK_HFCLKSTAT */ -/* Description: Status indicating which HFCLK128M/HFCLK64M source is running Note: Value of this register in any CLOCK instance reflects status only due to configurations/actions in that CLOCK instance. */ +/* Description: Status indicating which HFCLK128M/HFCLK64M source is running This register value in any CLOCK instance reflects status only due to configurations/actions in that CLOCK instance. */ /* Bit 16 : HFCLK state */ #define CLOCK_HFCLKSTAT_STATE_Pos (16UL) /*!< Position of STATE field. */ @@ -684,7 +684,7 @@ POSSIBILITY OF SUCH DAMAGE. #define CLOCK_LFCLKRUN_STATUS_Triggered (1UL) /*!< Task triggered */ /* Register: CLOCK_LFCLKSTAT */ -/* Description: Status indicating which LFCLK source is running Note: Value of this register in any CLOCK instance reflects status only due to configurations/actions in that CLOCK instance. */ +/* Description: Status indicating which LFCLK source is running This register value in any CLOCK instance reflects status only due to configurations/actions in that CLOCK instance. */ /* Bit 16 : LFCLK state */ #define CLOCK_LFCLKSTAT_STATE_Pos (16UL) /*!< Position of STATE field. */ @@ -794,9 +794,9 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: CLOCK_HFCLKCTRL */ /* Description: HFCLK128M frequency configuration */ -/* Bit 0 : High frequency clock HCLK */ +/* Bits 1..0 : High frequency clock HCLK */ #define CLOCK_HFCLKCTRL_HCLK_Pos (0UL) /*!< Position of HCLK field. */ -#define CLOCK_HFCLKCTRL_HCLK_Msk (0x1UL << CLOCK_HFCLKCTRL_HCLK_Pos) /*!< Bit mask of HCLK field. */ +#define CLOCK_HFCLKCTRL_HCLK_Msk (0x3UL << CLOCK_HFCLKCTRL_HCLK_Pos) /*!< Bit mask of HCLK field. */ #define CLOCK_HFCLKCTRL_HCLK_Div1 (0UL) /*!< Divide HFCLK by 1 */ #define CLOCK_HFCLKCTRL_HCLK_Div2 (1UL) /*!< Divide HFCLK by 2 */ @@ -1266,7 +1266,7 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: CTI_CTICONTROL */ /* Description: CTI Control register */ -/* Bit 0 : Enables or disables the CTI */ +/* Bit 0 : Enables or disables the CTI. */ #define CTI_CTICONTROL_GLBEN_Pos (0UL) /*!< Position of GLBEN field. */ #define CTI_CTICONTROL_GLBEN_Msk (0x1UL << CTI_CTICONTROL_GLBEN_Pos) /*!< Bit mask of GLBEN field. */ #define CTI_CTICONTROL_GLBEN_Disabled (0UL) /*!< All cross-triggering mapping logic functionality is disabled. */ @@ -1278,68 +1278,68 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 7 : ETM Event Input 3 */ #define CTI_CTIINTACK_ETMEVTIN3_Pos (7UL) /*!< Position of ETMEVTIN3 field. */ #define CTI_CTIINTACK_ETMEVTIN3_Msk (0x1UL << CTI_CTIINTACK_ETMEVTIN3_Pos) /*!< Bit mask of ETMEVTIN3 field. */ -#define CTI_CTIINTACK_ETMEVTIN3_Acknowledge (1UL) /*!< Clears the ctitrigout */ +#define CTI_CTIINTACK_ETMEVTIN3_Acknowledge (1UL) /*!< Clears the ctitrigout. */ /* Bit 6 : ETM Event Input 2 */ #define CTI_CTIINTACK_ETMEVTIN2_Pos (6UL) /*!< Position of ETMEVTIN2 field. */ #define CTI_CTIINTACK_ETMEVTIN2_Msk (0x1UL << CTI_CTIINTACK_ETMEVTIN2_Pos) /*!< Bit mask of ETMEVTIN2 field. */ -#define CTI_CTIINTACK_ETMEVTIN2_Acknowledge (1UL) /*!< Clears the ctitrigout */ +#define CTI_CTIINTACK_ETMEVTIN2_Acknowledge (1UL) /*!< Clears the ctitrigout. */ /* Bit 5 : ETM Event Input 1 */ #define CTI_CTIINTACK_ETMEVTIN1_Pos (5UL) /*!< Position of ETMEVTIN1 field. */ #define CTI_CTIINTACK_ETMEVTIN1_Msk (0x1UL << CTI_CTIINTACK_ETMEVTIN1_Pos) /*!< Bit mask of ETMEVTIN1 field. */ -#define CTI_CTIINTACK_ETMEVTIN1_Acknowledge (1UL) /*!< Clears the ctitrigout */ +#define CTI_CTIINTACK_ETMEVTIN1_Acknowledge (1UL) /*!< Clears the ctitrigout. */ /* Bit 4 : ETM Event Input 0 */ #define CTI_CTIINTACK_ETMEVTIN0_Pos (4UL) /*!< Position of ETMEVTIN0 field. */ #define CTI_CTIINTACK_ETMEVTIN0_Msk (0x1UL << CTI_CTIINTACK_ETMEVTIN0_Pos) /*!< Bit mask of ETMEVTIN0 field. */ -#define CTI_CTIINTACK_ETMEVTIN0_Acknowledge (1UL) /*!< Clears the ctitrigout */ +#define CTI_CTIINTACK_ETMEVTIN0_Acknowledge (1UL) /*!< Clears the ctitrigout. */ /* Bit 3 : N/A */ #define CTI_CTIINTACK_UNUSED1_Pos (3UL) /*!< Position of UNUSED1 field. */ #define CTI_CTIINTACK_UNUSED1_Msk (0x1UL << CTI_CTIINTACK_UNUSED1_Pos) /*!< Bit mask of UNUSED1 field. */ -#define CTI_CTIINTACK_UNUSED1_Acknowledge (1UL) /*!< Clears the ctitrigout */ +#define CTI_CTIINTACK_UNUSED1_Acknowledge (1UL) /*!< Clears the ctitrigout. */ /* Bit 2 : N/A */ #define CTI_CTIINTACK_UNUSED0_Pos (2UL) /*!< Position of UNUSED0 field. */ #define CTI_CTIINTACK_UNUSED0_Msk (0x1UL << CTI_CTIINTACK_UNUSED0_Pos) /*!< Bit mask of UNUSED0 field. */ -#define CTI_CTIINTACK_UNUSED0_Acknowledge (1UL) /*!< Clears the ctitrigout */ +#define CTI_CTIINTACK_UNUSED0_Acknowledge (1UL) /*!< Clears the ctitrigout. */ /* Bit 1 : Processor Restart */ #define CTI_CTIINTACK_CPURESTART_Pos (1UL) /*!< Position of CPURESTART field. */ #define CTI_CTIINTACK_CPURESTART_Msk (0x1UL << CTI_CTIINTACK_CPURESTART_Pos) /*!< Bit mask of CPURESTART field. */ -#define CTI_CTIINTACK_CPURESTART_Acknowledge (1UL) /*!< Clears the ctitrigout */ +#define CTI_CTIINTACK_CPURESTART_Acknowledge (1UL) /*!< Clears the ctitrigout. */ /* Bit 0 : Processor debug request */ #define CTI_CTIINTACK_DEBUGREQ_Pos (0UL) /*!< Position of DEBUGREQ field. */ #define CTI_CTIINTACK_DEBUGREQ_Msk (0x1UL << CTI_CTIINTACK_DEBUGREQ_Pos) /*!< Bit mask of DEBUGREQ field. */ -#define CTI_CTIINTACK_DEBUGREQ_Acknowledge (1UL) /*!< Clears the ctitrigout */ +#define CTI_CTIINTACK_DEBUGREQ_Acknowledge (1UL) /*!< Clears the ctitrigout. */ /* Register: CTI_CTIAPPSET */ /* Description: CTI Application Trigger Set register */ -/* Bit 3 : Application trigger event for channel 3 */ +/* Bit 3 : Application trigger event for channel 3. */ #define CTI_CTIAPPSET_APPSET_3_Pos (3UL) /*!< Position of APPSET_3 field. */ #define CTI_CTIAPPSET_APPSET_3_Msk (0x1UL << CTI_CTIAPPSET_APPSET_3_Pos) /*!< Bit mask of APPSET_3 field. */ #define CTI_CTIAPPSET_APPSET_3_Inactive (0UL) /*!< Application trigger 3 is inactive. */ #define CTI_CTIAPPSET_APPSET_3_Active (1UL) /*!< Application trigger 3 is active. */ #define CTI_CTIAPPSET_APPSET_3_Activate (1UL) /*!< Generate channel event for channel 3. */ -/* Bit 2 : Application trigger event for channel 2 */ +/* Bit 2 : Application trigger event for channel 2. */ #define CTI_CTIAPPSET_APPSET_2_Pos (2UL) /*!< Position of APPSET_2 field. */ #define CTI_CTIAPPSET_APPSET_2_Msk (0x1UL << CTI_CTIAPPSET_APPSET_2_Pos) /*!< Bit mask of APPSET_2 field. */ #define CTI_CTIAPPSET_APPSET_2_Inactive (0UL) /*!< Application trigger 2 is inactive. */ #define CTI_CTIAPPSET_APPSET_2_Active (1UL) /*!< Application trigger 2 is active. */ #define CTI_CTIAPPSET_APPSET_2_Activate (1UL) /*!< Generate channel event for channel 2. */ -/* Bit 1 : Application trigger event for channel 1 */ +/* Bit 1 : Application trigger event for channel 1. */ #define CTI_CTIAPPSET_APPSET_1_Pos (1UL) /*!< Position of APPSET_1 field. */ #define CTI_CTIAPPSET_APPSET_1_Msk (0x1UL << CTI_CTIAPPSET_APPSET_1_Pos) /*!< Bit mask of APPSET_1 field. */ #define CTI_CTIAPPSET_APPSET_1_Inactive (0UL) /*!< Application trigger 1 is inactive. */ #define CTI_CTIAPPSET_APPSET_1_Active (1UL) /*!< Application trigger 1 is active. */ #define CTI_CTIAPPSET_APPSET_1_Activate (1UL) /*!< Generate channel event for channel 1. */ -/* Bit 0 : Application trigger event for channel 0 */ +/* Bit 0 : Application trigger event for channel 0. */ #define CTI_CTIAPPSET_APPSET_0_Pos (0UL) /*!< Position of APPSET_0 field. */ #define CTI_CTIAPPSET_APPSET_0_Msk (0x1UL << CTI_CTIAPPSET_APPSET_0_Pos) /*!< Bit mask of APPSET_0 field. */ #define CTI_CTIAPPSET_APPSET_0_Inactive (0UL) /*!< Application trigger 0 is inactive. */ @@ -1352,22 +1352,22 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 3 : Sets the corresponding bits in the CTIAPPSET to 0. There is one bit of the register for each channel. */ #define CTI_CTIAPPCLEAR_APPCLEAR_3_Pos (3UL) /*!< Position of APPCLEAR_3 field. */ #define CTI_CTIAPPCLEAR_APPCLEAR_3_Msk (0x1UL << CTI_CTIAPPCLEAR_APPCLEAR_3_Pos) /*!< Bit mask of APPCLEAR_3 field. */ -#define CTI_CTIAPPCLEAR_APPCLEAR_3_Clear (1UL) /*!< Clears the event for channel 3 */ +#define CTI_CTIAPPCLEAR_APPCLEAR_3_Clear (1UL) /*!< Clears the event for channel 3. */ /* Bit 2 : Sets the corresponding bits in the CTIAPPSET to 0. There is one bit of the register for each channel. */ #define CTI_CTIAPPCLEAR_APPCLEAR_2_Pos (2UL) /*!< Position of APPCLEAR_2 field. */ #define CTI_CTIAPPCLEAR_APPCLEAR_2_Msk (0x1UL << CTI_CTIAPPCLEAR_APPCLEAR_2_Pos) /*!< Bit mask of APPCLEAR_2 field. */ -#define CTI_CTIAPPCLEAR_APPCLEAR_2_Clear (1UL) /*!< Clears the event for channel 2 */ +#define CTI_CTIAPPCLEAR_APPCLEAR_2_Clear (1UL) /*!< Clears the event for channel 2. */ /* Bit 1 : Sets the corresponding bits in the CTIAPPSET to 0. There is one bit of the register for each channel. */ #define CTI_CTIAPPCLEAR_APPCLEAR_1_Pos (1UL) /*!< Position of APPCLEAR_1 field. */ #define CTI_CTIAPPCLEAR_APPCLEAR_1_Msk (0x1UL << CTI_CTIAPPCLEAR_APPCLEAR_1_Pos) /*!< Bit mask of APPCLEAR_1 field. */ -#define CTI_CTIAPPCLEAR_APPCLEAR_1_Clear (1UL) /*!< Clears the event for channel 1 */ +#define CTI_CTIAPPCLEAR_APPCLEAR_1_Clear (1UL) /*!< Clears the event for channel 1. */ /* Bit 0 : Sets the corresponding bits in the CTIAPPSET to 0. There is one bit of the register for each channel. */ #define CTI_CTIAPPCLEAR_APPCLEAR_0_Pos (0UL) /*!< Position of APPCLEAR_0 field. */ #define CTI_CTIAPPCLEAR_APPCLEAR_0_Msk (0x1UL << CTI_CTIAPPCLEAR_APPCLEAR_0_Pos) /*!< Bit mask of APPCLEAR_0 field. */ -#define CTI_CTIAPPCLEAR_APPCLEAR_0_Clear (1UL) /*!< Clears the event for channel 0 */ +#define CTI_CTIAPPCLEAR_APPCLEAR_0_Clear (1UL) /*!< Clears the event for channel 0. */ /* Register: CTI_CTIAPPPULSE */ /* Description: CTI Application Pulse register */ @@ -1375,76 +1375,76 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 3 : Setting a bit HIGH generates a channel event pulse for the selected channel. There is one bit of the register for each channel. */ #define CTI_CTIAPPPULSE_APPULSE_3_Pos (3UL) /*!< Position of APPULSE_3 field. */ #define CTI_CTIAPPPULSE_APPULSE_3_Msk (0x1UL << CTI_CTIAPPPULSE_APPULSE_3_Pos) /*!< Bit mask of APPULSE_3 field. */ -#define CTI_CTIAPPPULSE_APPULSE_3_Generate (1UL) /*!< Generates an event pulse on channel 3 */ +#define CTI_CTIAPPPULSE_APPULSE_3_Generate (1UL) /*!< Generates an event pulse on channel 3. */ /* Bit 2 : Setting a bit HIGH generates a channel event pulse for the selected channel. There is one bit of the register for each channel. */ #define CTI_CTIAPPPULSE_APPULSE_2_Pos (2UL) /*!< Position of APPULSE_2 field. */ #define CTI_CTIAPPPULSE_APPULSE_2_Msk (0x1UL << CTI_CTIAPPPULSE_APPULSE_2_Pos) /*!< Bit mask of APPULSE_2 field. */ -#define CTI_CTIAPPPULSE_APPULSE_2_Generate (1UL) /*!< Generates an event pulse on channel 2 */ +#define CTI_CTIAPPPULSE_APPULSE_2_Generate (1UL) /*!< Generates an event pulse on channel 2. */ /* Bit 1 : Setting a bit HIGH generates a channel event pulse for the selected channel. There is one bit of the register for each channel. */ #define CTI_CTIAPPPULSE_APPULSE_1_Pos (1UL) /*!< Position of APPULSE_1 field. */ #define CTI_CTIAPPPULSE_APPULSE_1_Msk (0x1UL << CTI_CTIAPPPULSE_APPULSE_1_Pos) /*!< Bit mask of APPULSE_1 field. */ -#define CTI_CTIAPPPULSE_APPULSE_1_Generate (1UL) /*!< Generates an event pulse on channel 1 */ +#define CTI_CTIAPPPULSE_APPULSE_1_Generate (1UL) /*!< Generates an event pulse on channel 1. */ /* Bit 0 : Setting a bit HIGH generates a channel event pulse for the selected channel. There is one bit of the register for each channel. */ #define CTI_CTIAPPPULSE_APPULSE_0_Pos (0UL) /*!< Position of APPULSE_0 field. */ #define CTI_CTIAPPPULSE_APPULSE_0_Msk (0x1UL << CTI_CTIAPPPULSE_APPULSE_0_Pos) /*!< Bit mask of APPULSE_0 field. */ -#define CTI_CTIAPPPULSE_APPULSE_0_Generate (1UL) /*!< Generates an event pulse on channel 0 */ +#define CTI_CTIAPPPULSE_APPULSE_0_Generate (1UL) /*!< Generates an event pulse on channel 0. */ /* Register: CTI_CTIINEN */ /* Description: Description collection: CTI Trigger input */ -/* Bit 3 : Enables a cross trigger event to channel 3 when a ctitrigin input is activated */ +/* Bit 3 : Enables a cross trigger event to channel 3 when a ctitrigin input is activated. */ #define CTI_CTIINEN_TRIGINEN_3_Pos (3UL) /*!< Position of TRIGINEN_3 field. */ #define CTI_CTIINEN_TRIGINEN_3_Msk (0x1UL << CTI_CTIINEN_TRIGINEN_3_Pos) /*!< Bit mask of TRIGINEN_3 field. */ -#define CTI_CTIINEN_TRIGINEN_3_Disabled (0UL) /*!< Input trigger n events are ignored by channel 3 */ -#define CTI_CTIINEN_TRIGINEN_3_Enabled (1UL) /*!< When an event is received on input trigger n (ctitrigin[n]) generate an event on channel 3 */ +#define CTI_CTIINEN_TRIGINEN_3_Disabled (0UL) /*!< Input trigger n events are ignored by channel 3. */ +#define CTI_CTIINEN_TRIGINEN_3_Enabled (1UL) /*!< When an event is received on input trigger n (ctitrigin[n]), generate an event on channel 3. */ -/* Bit 2 : Enables a cross trigger event to channel 2 when a ctitrigin input is activated */ +/* Bit 2 : Enables a cross trigger event to channel 2 when a ctitrigin input is activated. */ #define CTI_CTIINEN_TRIGINEN_2_Pos (2UL) /*!< Position of TRIGINEN_2 field. */ #define CTI_CTIINEN_TRIGINEN_2_Msk (0x1UL << CTI_CTIINEN_TRIGINEN_2_Pos) /*!< Bit mask of TRIGINEN_2 field. */ -#define CTI_CTIINEN_TRIGINEN_2_Disabled (0UL) /*!< Input trigger n events are ignored by channel 2 */ -#define CTI_CTIINEN_TRIGINEN_2_Enabled (1UL) /*!< When an event is received on input trigger n (ctitrigin[n]) generate an event on channel 2 */ +#define CTI_CTIINEN_TRIGINEN_2_Disabled (0UL) /*!< Input trigger n events are ignored by channel 2. */ +#define CTI_CTIINEN_TRIGINEN_2_Enabled (1UL) /*!< When an event is received on input trigger n (ctitrigin[n]), generate an event on channel 2. */ -/* Bit 1 : Enables a cross trigger event to channel 1 when a ctitrigin input is activated */ +/* Bit 1 : Enables a cross trigger event to channel 1 when a ctitrigin input is activated. */ #define CTI_CTIINEN_TRIGINEN_1_Pos (1UL) /*!< Position of TRIGINEN_1 field. */ #define CTI_CTIINEN_TRIGINEN_1_Msk (0x1UL << CTI_CTIINEN_TRIGINEN_1_Pos) /*!< Bit mask of TRIGINEN_1 field. */ -#define CTI_CTIINEN_TRIGINEN_1_Disabled (0UL) /*!< Input trigger n events are ignored by channel 1 */ -#define CTI_CTIINEN_TRIGINEN_1_Enabled (1UL) /*!< When an event is received on input trigger n (ctitrigin[n]) generate an event on channel 1 */ +#define CTI_CTIINEN_TRIGINEN_1_Disabled (0UL) /*!< Input trigger n events are ignored by channel 1. */ +#define CTI_CTIINEN_TRIGINEN_1_Enabled (1UL) /*!< When an event is received on input trigger n (ctitrigin[n]), generate an event on channel 1. */ -/* Bit 0 : Enables a cross trigger event to channel 0 when a ctitrigin input is activated */ +/* Bit 0 : Enables a cross trigger event to channel 0 when a ctitrigin input is activated. */ #define CTI_CTIINEN_TRIGINEN_0_Pos (0UL) /*!< Position of TRIGINEN_0 field. */ #define CTI_CTIINEN_TRIGINEN_0_Msk (0x1UL << CTI_CTIINEN_TRIGINEN_0_Pos) /*!< Bit mask of TRIGINEN_0 field. */ -#define CTI_CTIINEN_TRIGINEN_0_Disabled (0UL) /*!< Input trigger n events are ignored by channel 0 */ -#define CTI_CTIINEN_TRIGINEN_0_Enabled (1UL) /*!< When an event is received on input trigger n (ctitrigin[n]) generate an event on channel 0 */ +#define CTI_CTIINEN_TRIGINEN_0_Disabled (0UL) /*!< Input trigger n events are ignored by channel 0. */ +#define CTI_CTIINEN_TRIGINEN_0_Enabled (1UL) /*!< When an event is received on input trigger n (ctitrigin[n]), generate an event on channel 0. */ /* Register: CTI_CTIOUTEN */ /* Description: Description collection: CTI Trigger output */ -/* Bit 3 : Enables a cross trigger event to ctitrigout when channel 3 when is activated */ +/* Bit 3 : Enables a cross trigger event to ctitrigout when channel 3 is activated. */ #define CTI_CTIOUTEN_TRIGOUTEN_3_Pos (3UL) /*!< Position of TRIGOUTEN_3 field. */ #define CTI_CTIOUTEN_TRIGOUTEN_3_Msk (0x1UL << CTI_CTIOUTEN_TRIGOUTEN_3_Pos) /*!< Bit mask of TRIGOUTEN_3 field. */ -#define CTI_CTIOUTEN_TRIGOUTEN_3_Disabled (0UL) /*!< Channel 3 is ignored by output trigger n */ -#define CTI_CTIOUTEN_TRIGOUTEN_3_Enabled (1UL) /*!< When an event occur on channel 3, generate an event on output event n (ctitrigout[n]) */ +#define CTI_CTIOUTEN_TRIGOUTEN_3_Disabled (0UL) /*!< Channel 3 is ignored by output trigger n. */ +#define CTI_CTIOUTEN_TRIGOUTEN_3_Enabled (1UL) /*!< When an event occurs on channel 3, generate an event on output event n (ctitrigout[n]). */ -/* Bit 2 : Enables a cross trigger event to ctitrigout when channel 2 when is activated */ +/* Bit 2 : Enables a cross trigger event to ctitrigout when channel 2 is activated. */ #define CTI_CTIOUTEN_TRIGOUTEN_2_Pos (2UL) /*!< Position of TRIGOUTEN_2 field. */ #define CTI_CTIOUTEN_TRIGOUTEN_2_Msk (0x1UL << CTI_CTIOUTEN_TRIGOUTEN_2_Pos) /*!< Bit mask of TRIGOUTEN_2 field. */ -#define CTI_CTIOUTEN_TRIGOUTEN_2_Disabled (0UL) /*!< Channel 2 is ignored by output trigger n */ -#define CTI_CTIOUTEN_TRIGOUTEN_2_Enabled (1UL) /*!< When an event occur on channel 2, generate an event on output event n (ctitrigout[n]) */ +#define CTI_CTIOUTEN_TRIGOUTEN_2_Disabled (0UL) /*!< Channel 2 is ignored by output trigger n. */ +#define CTI_CTIOUTEN_TRIGOUTEN_2_Enabled (1UL) /*!< When an event occurs on channel 2, generate an event on output event n (ctitrigout[n]). */ -/* Bit 1 : Enables a cross trigger event to ctitrigout when channel 1 when is activated */ +/* Bit 1 : Enables a cross trigger event to ctitrigout when channel 1 is activated. */ #define CTI_CTIOUTEN_TRIGOUTEN_1_Pos (1UL) /*!< Position of TRIGOUTEN_1 field. */ #define CTI_CTIOUTEN_TRIGOUTEN_1_Msk (0x1UL << CTI_CTIOUTEN_TRIGOUTEN_1_Pos) /*!< Bit mask of TRIGOUTEN_1 field. */ -#define CTI_CTIOUTEN_TRIGOUTEN_1_Disabled (0UL) /*!< Channel 1 is ignored by output trigger n */ -#define CTI_CTIOUTEN_TRIGOUTEN_1_Enabled (1UL) /*!< When an event occur on channel 1, generate an event on output event n (ctitrigout[n]) */ +#define CTI_CTIOUTEN_TRIGOUTEN_1_Disabled (0UL) /*!< Channel 1 is ignored by output trigger n. */ +#define CTI_CTIOUTEN_TRIGOUTEN_1_Enabled (1UL) /*!< When an event occurs on channel 1, generate an event on output event n (ctitrigout[n]). */ -/* Bit 0 : Enables a cross trigger event to ctitrigout when channel 0 when is activated */ +/* Bit 0 : Enables a cross trigger event to ctitrigout when channel 0 is activated. */ #define CTI_CTIOUTEN_TRIGOUTEN_0_Pos (0UL) /*!< Position of TRIGOUTEN_0 field. */ #define CTI_CTIOUTEN_TRIGOUTEN_0_Msk (0x1UL << CTI_CTIOUTEN_TRIGOUTEN_0_Pos) /*!< Bit mask of TRIGOUTEN_0 field. */ -#define CTI_CTIOUTEN_TRIGOUTEN_0_Disabled (0UL) /*!< Channel 0 is ignored by output trigger n */ -#define CTI_CTIOUTEN_TRIGOUTEN_0_Enabled (1UL) /*!< When an event occur on channel 0, generate an event on output event n (ctitrigout[n]) */ +#define CTI_CTIOUTEN_TRIGOUTEN_0_Disabled (0UL) /*!< Channel 0 is ignored by output trigger n. */ +#define CTI_CTIOUTEN_TRIGOUTEN_0_Enabled (1UL) /*!< When an event occurs on channel 0, generate an event on output event n (ctitrigout[n]). */ /* Register: CTI_CTITRIGINSTATUS */ /* Description: CTI Trigger In Status register */ @@ -1452,50 +1452,50 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 7 : N/A */ #define CTI_CTITRIGINSTATUS_UNUSED1_Pos (7UL) /*!< Position of UNUSED1 field. */ #define CTI_CTITRIGINSTATUS_UNUSED1_Msk (0x1UL << CTI_CTITRIGINSTATUS_UNUSED1_Pos) /*!< Bit mask of UNUSED1 field. */ -#define CTI_CTITRIGINSTATUS_UNUSED1_Inactive (0UL) /*!< Ctitrigin 7 is inactive */ -#define CTI_CTITRIGINSTATUS_UNUSED1_Active (1UL) /*!< Ctitrigin 7 is active */ +#define CTI_CTITRIGINSTATUS_UNUSED1_Inactive (0UL) /*!< Ctitrigin 7 is inactive. */ +#define CTI_CTITRIGINSTATUS_UNUSED1_Active (1UL) /*!< Ctitrigin 7 is active. */ /* Bit 6 : N/A */ #define CTI_CTITRIGINSTATUS_UNUSED0_Pos (6UL) /*!< Position of UNUSED0 field. */ #define CTI_CTITRIGINSTATUS_UNUSED0_Msk (0x1UL << CTI_CTITRIGINSTATUS_UNUSED0_Pos) /*!< Bit mask of UNUSED0 field. */ -#define CTI_CTITRIGINSTATUS_UNUSED0_Inactive (0UL) /*!< Ctitrigin 6 is inactive */ -#define CTI_CTITRIGINSTATUS_UNUSED0_Active (1UL) /*!< Ctitrigin 6 is active */ +#define CTI_CTITRIGINSTATUS_UNUSED0_Inactive (0UL) /*!< Ctitrigin 6 is inactive. */ +#define CTI_CTITRIGINSTATUS_UNUSED0_Active (1UL) /*!< Ctitrigin 6 is active. */ /* Bit 5 : ETM Event Output 1 */ #define CTI_CTITRIGINSTATUS_ETMEVTOUT1_Pos (5UL) /*!< Position of ETMEVTOUT1 field. */ #define CTI_CTITRIGINSTATUS_ETMEVTOUT1_Msk (0x1UL << CTI_CTITRIGINSTATUS_ETMEVTOUT1_Pos) /*!< Bit mask of ETMEVTOUT1 field. */ -#define CTI_CTITRIGINSTATUS_ETMEVTOUT1_Inactive (0UL) /*!< Ctitrigin 5 is inactive */ -#define CTI_CTITRIGINSTATUS_ETMEVTOUT1_Active (1UL) /*!< Ctitrigin 5 is active */ +#define CTI_CTITRIGINSTATUS_ETMEVTOUT1_Inactive (0UL) /*!< Ctitrigin 5 is inactive. */ +#define CTI_CTITRIGINSTATUS_ETMEVTOUT1_Active (1UL) /*!< Ctitrigin 5 is active. */ /* Bit 4 : ETM Event Output 0 */ #define CTI_CTITRIGINSTATUS_ETMEVTOUT0_Pos (4UL) /*!< Position of ETMEVTOUT0 field. */ #define CTI_CTITRIGINSTATUS_ETMEVTOUT0_Msk (0x1UL << CTI_CTITRIGINSTATUS_ETMEVTOUT0_Pos) /*!< Bit mask of ETMEVTOUT0 field. */ -#define CTI_CTITRIGINSTATUS_ETMEVTOUT0_Inactive (0UL) /*!< Ctitrigin 4 is inactive */ -#define CTI_CTITRIGINSTATUS_ETMEVTOUT0_Active (1UL) /*!< Ctitrigin 4 is active */ +#define CTI_CTITRIGINSTATUS_ETMEVTOUT0_Inactive (0UL) /*!< Ctitrigin 4 is inactive. */ +#define CTI_CTITRIGINSTATUS_ETMEVTOUT0_Active (1UL) /*!< Ctitrigin 4 is active. */ /* Bit 3 : DWT Comparator Output 2 */ #define CTI_CTITRIGINSTATUS_DWTCOMPOUT2_Pos (3UL) /*!< Position of DWTCOMPOUT2 field. */ #define CTI_CTITRIGINSTATUS_DWTCOMPOUT2_Msk (0x1UL << CTI_CTITRIGINSTATUS_DWTCOMPOUT2_Pos) /*!< Bit mask of DWTCOMPOUT2 field. */ -#define CTI_CTITRIGINSTATUS_DWTCOMPOUT2_Inactive (0UL) /*!< Ctitrigin 3 is inactive */ -#define CTI_CTITRIGINSTATUS_DWTCOMPOUT2_Active (1UL) /*!< Ctitrigin 3 is active */ +#define CTI_CTITRIGINSTATUS_DWTCOMPOUT2_Inactive (0UL) /*!< Ctitrigin 3 is inactive. */ +#define CTI_CTITRIGINSTATUS_DWTCOMPOUT2_Active (1UL) /*!< Ctitrigin 3 is active. */ /* Bit 2 : DWT Comparator Output 1 */ #define CTI_CTITRIGINSTATUS_DWTCOMPOUT1_Pos (2UL) /*!< Position of DWTCOMPOUT1 field. */ #define CTI_CTITRIGINSTATUS_DWTCOMPOUT1_Msk (0x1UL << CTI_CTITRIGINSTATUS_DWTCOMPOUT1_Pos) /*!< Bit mask of DWTCOMPOUT1 field. */ -#define CTI_CTITRIGINSTATUS_DWTCOMPOUT1_Inactive (0UL) /*!< Ctitrigin 2 is inactive */ -#define CTI_CTITRIGINSTATUS_DWTCOMPOUT1_Active (1UL) /*!< Ctitrigin 2 is active */ +#define CTI_CTITRIGINSTATUS_DWTCOMPOUT1_Inactive (0UL) /*!< Ctitrigin 2 is inactive. */ +#define CTI_CTITRIGINSTATUS_DWTCOMPOUT1_Active (1UL) /*!< Ctitrigin 2 is active. */ /* Bit 1 : DWT Comparator Output 0 */ #define CTI_CTITRIGINSTATUS_DWTCOMPOUT0_Pos (1UL) /*!< Position of DWTCOMPOUT0 field. */ #define CTI_CTITRIGINSTATUS_DWTCOMPOUT0_Msk (0x1UL << CTI_CTITRIGINSTATUS_DWTCOMPOUT0_Pos) /*!< Bit mask of DWTCOMPOUT0 field. */ -#define CTI_CTITRIGINSTATUS_DWTCOMPOUT0_Inactive (0UL) /*!< Ctitrigin 1 is inactive */ -#define CTI_CTITRIGINSTATUS_DWTCOMPOUT0_Active (1UL) /*!< Ctitrigin 1 is active */ +#define CTI_CTITRIGINSTATUS_DWTCOMPOUT0_Inactive (0UL) /*!< Ctitrigin 1 is inactive. */ +#define CTI_CTITRIGINSTATUS_DWTCOMPOUT0_Active (1UL) /*!< Ctitrigin 1 is active. */ /* Bit 0 : Processor Halted */ #define CTI_CTITRIGINSTATUS_CPUHALTED_Pos (0UL) /*!< Position of CPUHALTED field. */ #define CTI_CTITRIGINSTATUS_CPUHALTED_Msk (0x1UL << CTI_CTITRIGINSTATUS_CPUHALTED_Pos) /*!< Bit mask of CPUHALTED field. */ -#define CTI_CTITRIGINSTATUS_CPUHALTED_Inactive (0UL) /*!< Ctitrigin 0 is inactive */ -#define CTI_CTITRIGINSTATUS_CPUHALTED_Active (1UL) /*!< Ctitrigin 0 is active */ +#define CTI_CTITRIGINSTATUS_CPUHALTED_Inactive (0UL) /*!< Ctitrigin 0 is inactive. */ +#define CTI_CTITRIGINSTATUS_CPUHALTED_Active (1UL) /*!< Ctitrigin 0 is active. */ /* Register: CTI_CTITRIGOUTSTATUS */ /* Description: CTI Trigger Out Status register */ @@ -1503,50 +1503,50 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 7 : ETM Event Input 3 */ #define CTI_CTITRIGOUTSTATUS_ETMEVTIN3_Pos (7UL) /*!< Position of ETMEVTIN3 field. */ #define CTI_CTITRIGOUTSTATUS_ETMEVTIN3_Msk (0x1UL << CTI_CTITRIGOUTSTATUS_ETMEVTIN3_Pos) /*!< Bit mask of ETMEVTIN3 field. */ -#define CTI_CTITRIGOUTSTATUS_ETMEVTIN3_Inactive (0UL) /*!< Ctitrigout 7 is inactive */ -#define CTI_CTITRIGOUTSTATUS_ETMEVTIN3_Active (1UL) /*!< Ctitrigout 7 is active */ +#define CTI_CTITRIGOUTSTATUS_ETMEVTIN3_Inactive (0UL) /*!< Ctitrigout 7 is inactive. */ +#define CTI_CTITRIGOUTSTATUS_ETMEVTIN3_Active (1UL) /*!< Ctitrigout 7 is active. */ /* Bit 6 : ETM Event Input 2 */ #define CTI_CTITRIGOUTSTATUS_ETMEVTIN2_Pos (6UL) /*!< Position of ETMEVTIN2 field. */ #define CTI_CTITRIGOUTSTATUS_ETMEVTIN2_Msk (0x1UL << CTI_CTITRIGOUTSTATUS_ETMEVTIN2_Pos) /*!< Bit mask of ETMEVTIN2 field. */ -#define CTI_CTITRIGOUTSTATUS_ETMEVTIN2_Inactive (0UL) /*!< Ctitrigout 6 is inactive */ -#define CTI_CTITRIGOUTSTATUS_ETMEVTIN2_Active (1UL) /*!< Ctitrigout 6 is active */ +#define CTI_CTITRIGOUTSTATUS_ETMEVTIN2_Inactive (0UL) /*!< Ctitrigout 6 is inactive. */ +#define CTI_CTITRIGOUTSTATUS_ETMEVTIN2_Active (1UL) /*!< Ctitrigout 6 is active. */ /* Bit 5 : ETM Event Input 1 */ #define CTI_CTITRIGOUTSTATUS_ETMEVTIN1_Pos (5UL) /*!< Position of ETMEVTIN1 field. */ #define CTI_CTITRIGOUTSTATUS_ETMEVTIN1_Msk (0x1UL << CTI_CTITRIGOUTSTATUS_ETMEVTIN1_Pos) /*!< Bit mask of ETMEVTIN1 field. */ -#define CTI_CTITRIGOUTSTATUS_ETMEVTIN1_Inactive (0UL) /*!< Ctitrigout 5 is inactive */ -#define CTI_CTITRIGOUTSTATUS_ETMEVTIN1_Active (1UL) /*!< Ctitrigout 5 is active */ +#define CTI_CTITRIGOUTSTATUS_ETMEVTIN1_Inactive (0UL) /*!< Ctitrigout 5 is inactive. */ +#define CTI_CTITRIGOUTSTATUS_ETMEVTIN1_Active (1UL) /*!< Ctitrigout 5 is active. */ /* Bit 4 : ETM Event Input 0 */ #define CTI_CTITRIGOUTSTATUS_ETMEVTIN0_Pos (4UL) /*!< Position of ETMEVTIN0 field. */ #define CTI_CTITRIGOUTSTATUS_ETMEVTIN0_Msk (0x1UL << CTI_CTITRIGOUTSTATUS_ETMEVTIN0_Pos) /*!< Bit mask of ETMEVTIN0 field. */ -#define CTI_CTITRIGOUTSTATUS_ETMEVTIN0_Inactive (0UL) /*!< Ctitrigout 4 is inactive */ -#define CTI_CTITRIGOUTSTATUS_ETMEVTIN0_Active (1UL) /*!< Ctitrigout 4 is active */ +#define CTI_CTITRIGOUTSTATUS_ETMEVTIN0_Inactive (0UL) /*!< Ctitrigout 4 is inactive. */ +#define CTI_CTITRIGOUTSTATUS_ETMEVTIN0_Active (1UL) /*!< Ctitrigout 4 is active. */ /* Bit 3 : N/A */ #define CTI_CTITRIGOUTSTATUS_UNUSED1_Pos (3UL) /*!< Position of UNUSED1 field. */ #define CTI_CTITRIGOUTSTATUS_UNUSED1_Msk (0x1UL << CTI_CTITRIGOUTSTATUS_UNUSED1_Pos) /*!< Bit mask of UNUSED1 field. */ -#define CTI_CTITRIGOUTSTATUS_UNUSED1_Inactive (0UL) /*!< Ctitrigout 3 is inactive */ -#define CTI_CTITRIGOUTSTATUS_UNUSED1_Active (1UL) /*!< Ctitrigout 3 is active */ +#define CTI_CTITRIGOUTSTATUS_UNUSED1_Inactive (0UL) /*!< Ctitrigout 3 is inactive. */ +#define CTI_CTITRIGOUTSTATUS_UNUSED1_Active (1UL) /*!< Ctitrigout 3 is active. */ /* Bit 2 : N/A */ #define CTI_CTITRIGOUTSTATUS_UNUSED0_Pos (2UL) /*!< Position of UNUSED0 field. */ #define CTI_CTITRIGOUTSTATUS_UNUSED0_Msk (0x1UL << CTI_CTITRIGOUTSTATUS_UNUSED0_Pos) /*!< Bit mask of UNUSED0 field. */ -#define CTI_CTITRIGOUTSTATUS_UNUSED0_Inactive (0UL) /*!< Ctitrigout 2 is inactive */ -#define CTI_CTITRIGOUTSTATUS_UNUSED0_Active (1UL) /*!< Ctitrigout 2 is active */ +#define CTI_CTITRIGOUTSTATUS_UNUSED0_Inactive (0UL) /*!< Ctitrigout 2 is inactive. */ +#define CTI_CTITRIGOUTSTATUS_UNUSED0_Active (1UL) /*!< Ctitrigout 2 is active. */ /* Bit 1 : Processor Restart */ #define CTI_CTITRIGOUTSTATUS_CPURESTART_Pos (1UL) /*!< Position of CPURESTART field. */ #define CTI_CTITRIGOUTSTATUS_CPURESTART_Msk (0x1UL << CTI_CTITRIGOUTSTATUS_CPURESTART_Pos) /*!< Bit mask of CPURESTART field. */ -#define CTI_CTITRIGOUTSTATUS_CPURESTART_Inactive (0UL) /*!< Ctitrigout 1 is inactive */ -#define CTI_CTITRIGOUTSTATUS_CPURESTART_Active (1UL) /*!< Ctitrigout 1 is active */ +#define CTI_CTITRIGOUTSTATUS_CPURESTART_Inactive (0UL) /*!< Ctitrigout 1 is inactive. */ +#define CTI_CTITRIGOUTSTATUS_CPURESTART_Active (1UL) /*!< Ctitrigout 1 is active. */ /* Bit 0 : Processor debug request */ #define CTI_CTITRIGOUTSTATUS_DEBUGREQ_Pos (0UL) /*!< Position of DEBUGREQ field. */ #define CTI_CTITRIGOUTSTATUS_DEBUGREQ_Msk (0x1UL << CTI_CTITRIGOUTSTATUS_DEBUGREQ_Pos) /*!< Bit mask of DEBUGREQ field. */ -#define CTI_CTITRIGOUTSTATUS_DEBUGREQ_Inactive (0UL) /*!< Ctitrigout 0 is inactive */ -#define CTI_CTITRIGOUTSTATUS_DEBUGREQ_Active (1UL) /*!< Ctitrigout 0 is active */ +#define CTI_CTITRIGOUTSTATUS_DEBUGREQ_Inactive (0UL) /*!< Ctitrigout 0 is inactive. */ +#define CTI_CTITRIGOUTSTATUS_DEBUGREQ_Active (1UL) /*!< Ctitrigout 0 is active. */ /* Register: CTI_CTICHINSTATUS */ /* Description: CTI Channel In Status register */ @@ -1554,69 +1554,69 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 3 : Shows the status of the ctitrigin 3 input. */ #define CTI_CTICHINSTATUS_CTICHINSTATUS_3_Pos (3UL) /*!< Position of CTICHINSTATUS_3 field. */ #define CTI_CTICHINSTATUS_CTICHINSTATUS_3_Msk (0x1UL << CTI_CTICHINSTATUS_CTICHINSTATUS_3_Pos) /*!< Bit mask of CTICHINSTATUS_3 field. */ -#define CTI_CTICHINSTATUS_CTICHINSTATUS_3_Inactive (0UL) /*!< Ctichin 3 is inactive */ -#define CTI_CTICHINSTATUS_CTICHINSTATUS_3_Active (1UL) /*!< Ctichin 3 is active */ +#define CTI_CTICHINSTATUS_CTICHINSTATUS_3_Inactive (0UL) /*!< Ctichin 3 is inactive. */ +#define CTI_CTICHINSTATUS_CTICHINSTATUS_3_Active (1UL) /*!< Ctichin 3 is active. */ /* Bit 2 : Shows the status of the ctitrigin 2 input. */ #define CTI_CTICHINSTATUS_CTICHINSTATUS_2_Pos (2UL) /*!< Position of CTICHINSTATUS_2 field. */ #define CTI_CTICHINSTATUS_CTICHINSTATUS_2_Msk (0x1UL << CTI_CTICHINSTATUS_CTICHINSTATUS_2_Pos) /*!< Bit mask of CTICHINSTATUS_2 field. */ -#define CTI_CTICHINSTATUS_CTICHINSTATUS_2_Inactive (0UL) /*!< Ctichin 2 is inactive */ -#define CTI_CTICHINSTATUS_CTICHINSTATUS_2_Active (1UL) /*!< Ctichin 2 is active */ +#define CTI_CTICHINSTATUS_CTICHINSTATUS_2_Inactive (0UL) /*!< Ctichin 2 is inactive. */ +#define CTI_CTICHINSTATUS_CTICHINSTATUS_2_Active (1UL) /*!< Ctichin 2 is active. */ /* Bit 1 : Shows the status of the ctitrigin 1 input. */ #define CTI_CTICHINSTATUS_CTICHINSTATUS_1_Pos (1UL) /*!< Position of CTICHINSTATUS_1 field. */ #define CTI_CTICHINSTATUS_CTICHINSTATUS_1_Msk (0x1UL << CTI_CTICHINSTATUS_CTICHINSTATUS_1_Pos) /*!< Bit mask of CTICHINSTATUS_1 field. */ -#define CTI_CTICHINSTATUS_CTICHINSTATUS_1_Inactive (0UL) /*!< Ctichin 1 is inactive */ -#define CTI_CTICHINSTATUS_CTICHINSTATUS_1_Active (1UL) /*!< Ctichin 1 is active */ +#define CTI_CTICHINSTATUS_CTICHINSTATUS_1_Inactive (0UL) /*!< Ctichin 1 is inactive. */ +#define CTI_CTICHINSTATUS_CTICHINSTATUS_1_Active (1UL) /*!< Ctichin 1 is active. */ /* Bit 0 : Shows the status of the ctitrigin 0 input. */ #define CTI_CTICHINSTATUS_CTICHINSTATUS_0_Pos (0UL) /*!< Position of CTICHINSTATUS_0 field. */ #define CTI_CTICHINSTATUS_CTICHINSTATUS_0_Msk (0x1UL << CTI_CTICHINSTATUS_CTICHINSTATUS_0_Pos) /*!< Bit mask of CTICHINSTATUS_0 field. */ -#define CTI_CTICHINSTATUS_CTICHINSTATUS_0_Inactive (0UL) /*!< Ctichin 0 is inactive */ -#define CTI_CTICHINSTATUS_CTICHINSTATUS_0_Active (1UL) /*!< Ctichin 0 is active */ +#define CTI_CTICHINSTATUS_CTICHINSTATUS_0_Inactive (0UL) /*!< Ctichin 0 is inactive. */ +#define CTI_CTICHINSTATUS_CTICHINSTATUS_0_Active (1UL) /*!< Ctichin 0 is active. */ /* Register: CTI_CTIGATE */ /* Description: Enable CTI Channel Gate register */ -/* Bit 3 : Enable ctichout3 */ +/* Bit 3 : Enable ctichout3. */ #define CTI_CTIGATE_CTIGATEEN_3_Pos (3UL) /*!< Position of CTIGATEEN_3 field. */ #define CTI_CTIGATE_CTIGATEEN_3_Msk (0x1UL << CTI_CTIGATE_CTIGATEEN_3_Pos) /*!< Bit mask of CTIGATEEN_3 field. */ -#define CTI_CTIGATE_CTIGATEEN_3_Disabled (0UL) /*!< Disable ctichout channel 3 propagation */ -#define CTI_CTIGATE_CTIGATEEN_3_Enabled (1UL) /*!< Enable ctichout channel 3 propagation */ +#define CTI_CTIGATE_CTIGATEEN_3_Disabled (0UL) /*!< Disable ctichout channel 3 propagation. */ +#define CTI_CTIGATE_CTIGATEEN_3_Enabled (1UL) /*!< Enable ctichout channel 3 propagation. */ -/* Bit 2 : Enable ctichout2 */ +/* Bit 2 : Enable ctichout2. */ #define CTI_CTIGATE_CTIGATEEN_2_Pos (2UL) /*!< Position of CTIGATEEN_2 field. */ #define CTI_CTIGATE_CTIGATEEN_2_Msk (0x1UL << CTI_CTIGATE_CTIGATEEN_2_Pos) /*!< Bit mask of CTIGATEEN_2 field. */ -#define CTI_CTIGATE_CTIGATEEN_2_Disabled (0UL) /*!< Disable ctichout channel 2 propagation */ -#define CTI_CTIGATE_CTIGATEEN_2_Enabled (1UL) /*!< Enable ctichout channel 2 propagation */ +#define CTI_CTIGATE_CTIGATEEN_2_Disabled (0UL) /*!< Disable ctichout channel 2 propagation. */ +#define CTI_CTIGATE_CTIGATEEN_2_Enabled (1UL) /*!< Enable ctichout channel 2 propagation. */ -/* Bit 1 : Enable ctichout1 */ +/* Bit 1 : Enable ctichout1. */ #define CTI_CTIGATE_CTIGATEEN_1_Pos (1UL) /*!< Position of CTIGATEEN_1 field. */ #define CTI_CTIGATE_CTIGATEEN_1_Msk (0x1UL << CTI_CTIGATE_CTIGATEEN_1_Pos) /*!< Bit mask of CTIGATEEN_1 field. */ -#define CTI_CTIGATE_CTIGATEEN_1_Disabled (0UL) /*!< Disable ctichout channel 1 propagation */ -#define CTI_CTIGATE_CTIGATEEN_1_Enabled (1UL) /*!< Enable ctichout channel 1 propagation */ +#define CTI_CTIGATE_CTIGATEEN_1_Disabled (0UL) /*!< Disable ctichout channel 1 propagation. */ +#define CTI_CTIGATE_CTIGATEEN_1_Enabled (1UL) /*!< Enable ctichout channel 1 propagation. */ -/* Bit 0 : Enable ctichout0 */ +/* Bit 0 : Enable ctichout0. */ #define CTI_CTIGATE_CTIGATEEN_0_Pos (0UL) /*!< Position of CTIGATEEN_0 field. */ #define CTI_CTIGATE_CTIGATEEN_0_Msk (0x1UL << CTI_CTIGATE_CTIGATEEN_0_Pos) /*!< Bit mask of CTIGATEEN_0 field. */ -#define CTI_CTIGATE_CTIGATEEN_0_Disabled (0UL) /*!< Disable ctichout channel 0 propagation */ -#define CTI_CTIGATE_CTIGATEEN_0_Enabled (1UL) /*!< Enable ctichout channel 0 propagation */ +#define CTI_CTIGATE_CTIGATEEN_0_Disabled (0UL) /*!< Disable ctichout channel 0 propagation. */ +#define CTI_CTIGATE_CTIGATEEN_0_Enabled (1UL) /*!< Enable ctichout channel 0 propagation. */ /* Register: CTI_DEVARCH */ /* Description: Device Architecture register */ -/* Bit 0 : Contains the CTI device architecture */ +/* Bit 0 : Contains the CTI device architecture. */ #define CTI_DEVARCH_Architecture_Pos (0UL) /*!< Position of Architecture field. */ #define CTI_DEVARCH_Architecture_Msk (0x1UL << CTI_DEVARCH_Architecture_Pos) /*!< Bit mask of Architecture field. */ /* Register: CTI_DEVID */ /* Description: Device Configuration register */ -/* Bits 19..16 : Number of ECT channels available */ +/* Bits 19..16 : Number of ECT channels available. */ #define CTI_DEVID_NUMCH_Pos (16UL) /*!< Position of NUMCH field. */ #define CTI_DEVID_NUMCH_Msk (0xFUL << CTI_DEVID_NUMCH_Pos) /*!< Bit mask of NUMCH field. */ -/* Bits 15..8 : Number of ECT triggers available */ +/* Bits 15..8 : Number of ECT triggers available. */ #define CTI_DEVID_NUMTRIG_Pos (8UL) /*!< Position of NUMTRIG field. */ #define CTI_DEVID_NUMTRIG_Msk (0xFFUL << CTI_DEVID_NUMTRIG_Pos) /*!< Bit mask of NUMTRIG field. */ @@ -1632,22 +1632,22 @@ POSSIBILITY OF SUCH DAMAGE. the major classification as specified in the MAJOR field. */ #define CTI_DEVTYPE_SUB_Pos (4UL) /*!< Position of SUB field. */ #define CTI_DEVTYPE_SUB_Msk (0xFUL << CTI_DEVTYPE_SUB_Pos) /*!< Bit mask of SUB field. */ -#define CTI_DEVTYPE_SUB_Crosstrigger (0b0001UL) /*!< Indicates that this component is a sub-triggering component */ +#define CTI_DEVTYPE_SUB_Crosstrigger (0b0001UL) /*!< Indicates that this component is a sub-triggering component. */ /* Bits 3..0 : Major classification of the type of the debug component as specified in the ARM Architecture Specification for this - debug and trace component */ + debug and trace component. */ #define CTI_DEVTYPE_MAJOR_Pos (0UL) /*!< Position of MAJOR field. */ #define CTI_DEVTYPE_MAJOR_Msk (0xFUL << CTI_DEVTYPE_MAJOR_Pos) /*!< Bit mask of MAJOR field. */ -#define CTI_DEVTYPE_MAJOR_Controller (0b0100UL) /*!< Indicates that this component allows a debugger to control other components in a CoreSight SoC-400 system */ +#define CTI_DEVTYPE_MAJOR_Controller (0b0100UL) /*!< Indicates that this component allows a debugger to control other components in a CoreSight SoC-400 system. */ /* Register: CTI_PIDR4 */ /* Description: Peripheral ID4 Register */ -/* Bits 7..4 : Always 0b0000. Indicates that the device only occupies 4KB of memory */ +/* Bits 7..4 : Always 0b0000. Indicates that the device only occupies 4KB of memory. */ #define CTI_PIDR4_SIZE_Pos (4UL) /*!< Position of SIZE field. */ #define CTI_PIDR4_SIZE_Msk (0xFUL << CTI_PIDR4_SIZE_Pos) /*!< Bit mask of SIZE field. */ -/* Bits 3..0 : Together, PIDR1.DES_0, PIDR2.DES_1, and PIDR4.DES_2 identify the designer of the component */ +/* Bits 3..0 : Together, PIDR1.DES_0, PIDR2.DES_1, and PIDR4.DES_2 identify the designer of the component. */ #define CTI_PIDR4_DES_2_Pos (0UL) /*!< Position of DES_2 field. */ #define CTI_PIDR4_DES_2_Msk (0xFUL << CTI_PIDR4_DES_2_Pos) /*!< Bit mask of DES_2 field. */ #define CTI_PIDR4_DES_2_Code (0b0100UL) /*!< JEDEC continuation code */ @@ -1655,23 +1655,23 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: CTI_PIDR0 */ /* Description: Peripheral ID0 Register */ -/* Bits 7..0 : Bits[7:0] of the 12-bit part number of the component. The designer of the component assigns this part number */ +/* Bits 7..0 : Bits[7:0] of the 12-bit part number of the component. The designer of the component assigns this part number. */ #define CTI_PIDR0_PART_0_Pos (0UL) /*!< Position of PART_0 field. */ #define CTI_PIDR0_PART_0_Msk (0xFFUL << CTI_PIDR0_PART_0_Pos) /*!< Bit mask of PART_0 field. */ -#define CTI_PIDR0_PART_0_PartnumberL (0x21UL) /*!< Indicates bits[7:0] of the part number of the component */ +#define CTI_PIDR0_PART_0_PartnumberL (0x21UL) /*!< Indicates bits[7:0] of the part number of the component. */ /* Register: CTI_PIDR1 */ /* Description: Peripheral ID1 Register */ -/* Bits 7..4 : Together, PIDR1.DES_0, PIDR2.DES_1, and PIDR4.DES_2 identify the designer of the component */ +/* Bits 7..4 : Together, PIDR1.DES_0, PIDR2.DES_1, and PIDR4.DES_2 identify the designer of the component. */ #define CTI_PIDR1_DES_0_Pos (4UL) /*!< Position of DES_0 field. */ #define CTI_PIDR1_DES_0_Msk (0xFUL << CTI_PIDR1_DES_0_Pos) /*!< Bit mask of DES_0 field. */ #define CTI_PIDR1_DES_0_Arm (0b1011UL) /*!< ARM. Bits[3:0] of the JEDEC JEP106 Identity Code */ -/* Bits 3..0 : Bits[11:8] of the 12-bit part number of the component. The designer of the component assigns this part number */ +/* Bits 3..0 : Bits[11:8] of the 12-bit part number of the component. The designer of the component assigns this part number. */ #define CTI_PIDR1_PART_1_Pos (0UL) /*!< Position of PART_1 field. */ #define CTI_PIDR1_PART_1_Msk (0xFUL << CTI_PIDR1_PART_1_Pos) /*!< Bit mask of PART_1 field. */ -#define CTI_PIDR1_PART_1_PartnumberH (0b1101UL) /*!< Indicates bits[11:8] of the part number of the component */ +#define CTI_PIDR1_PART_1_PartnumberH (0b1101UL) /*!< Indicates bits[11:8] of the part number of the component. */ /* Register: CTI_PIDR2 */ /* Description: Peripheral ID2 Register */ @@ -1681,11 +1681,11 @@ POSSIBILITY OF SUCH DAMAGE. #define CTI_PIDR2_REVISION_Msk (0xFUL << CTI_PIDR2_REVISION_Pos) /*!< Bit mask of REVISION field. */ #define CTI_PIDR2_REVISION_Rev0p0 (0b0000UL) /*!< This device is at r0p0 */ -/* Bit 3 : Always 1. Indicates that the JEDEC-assigned designer ID is used */ +/* Bit 3 : Always 1. Indicates that the JEDEC-assigned designer ID is used. */ #define CTI_PIDR2_JEDEC_Pos (3UL) /*!< Position of JEDEC field. */ #define CTI_PIDR2_JEDEC_Msk (0x1UL << CTI_PIDR2_JEDEC_Pos) /*!< Bit mask of JEDEC field. */ -/* Bits 2..0 : Together, PIDR1.DES_0, PIDR2.DES_1, and PIDR4.DES_2 identify the designer of the component */ +/* Bits 2..0 : Together, PIDR1.DES_0, PIDR2.DES_1, and PIDR4.DES_2 identify the designer of the component. */ #define CTI_PIDR2_DES_1_Pos (0UL) /*!< Position of DES_1 field. */ #define CTI_PIDR2_DES_1_Msk (0x7UL << CTI_PIDR2_DES_1_Pos) /*!< Bit mask of DES_1 field. */ #define CTI_PIDR2_DES_1_Arm (0b011UL) /*!< ARM. Bits[6:4] of the JEDEC JEP106 Identity Code */ @@ -1698,21 +1698,21 @@ POSSIBILITY OF SUCH DAMAGE. metal fix can change this field if required, for example, by driving it from registers that reset to 0b0000. */ #define CTI_PIDR3_REVAND_Pos (4UL) /*!< Position of REVAND field. */ #define CTI_PIDR3_REVAND_Msk (0xFUL << CTI_PIDR3_REVAND_Pos) /*!< Bit mask of REVAND field. */ -#define CTI_PIDR3_REVAND_NoErrata (0b000UL) /*!< Indicates that there are no errata fixes to this component */ +#define CTI_PIDR3_REVAND_NoErrata (0b000UL) /*!< Indicates that there are no errata fixes to this component. */ /* Bits 3..0 : Customer Modified. Indicates whether the customer has modified the behavior of the component. In most cases, this field is 0b0000. Customers change this value when they make authorized modifications to this component. */ #define CTI_PIDR3_CMOD_Pos (0UL) /*!< Position of CMOD field. */ #define CTI_PIDR3_CMOD_Msk (0xFUL << CTI_PIDR3_CMOD_Pos) /*!< Bit mask of CMOD field. */ -#define CTI_PIDR3_CMOD_Unmodified (0b000UL) /*!< Indicates that the customer has not modified this component */ +#define CTI_PIDR3_CMOD_Unmodified (0b000UL) /*!< Indicates that the customer has not modified this component. */ /* Register: CTI_CIDR0 */ /* Description: Component ID0 Register */ -/* Bits 7..0 : Preamble[0]. Contains bits[7:0] of the component identification code */ +/* Bits 7..0 : Preamble[0]. Contains bits[7:0] of the component identification code. */ #define CTI_CIDR0_PRMBL_0_Pos (0UL) /*!< Position of PRMBL_0 field. */ #define CTI_CIDR0_PRMBL_0_Msk (0xFFUL << CTI_CIDR0_PRMBL_0_Pos) /*!< Bit mask of PRMBL_0 field. */ -#define CTI_CIDR0_PRMBL_0_Value (0x0DUL) /*!< Bits[7:0] of the identification code */ +#define CTI_CIDR0_PRMBL_0_Value (0x0DUL) /*!< Bits[7:0] of the identification code. */ /* Register: CTI_CIDR1 */ /* Description: Component ID1 Register */ @@ -1721,42 +1721,42 @@ POSSIBILITY OF SUCH DAMAGE. Contains bits[15:12] of the component identification code */ #define CTI_CIDR1_CLASS_Pos (4UL) /*!< Position of CLASS field. */ #define CTI_CIDR1_CLASS_Msk (0xFUL << CTI_CIDR1_CLASS_Pos) /*!< Bit mask of CLASS field. */ -#define CTI_CIDR1_CLASS_Coresight (0b1001UL) /*!< Indicates that the component is a CoreSight component */ +#define CTI_CIDR1_CLASS_Coresight (0b1001UL) /*!< Indicates that the component is a CoreSight component. */ -/* Bits 3..0 : Preamble[1]. Contains bits[11:8] of the component identification code */ +/* Bits 3..0 : Preamble[1]. Contains bits[11:8] of the component identification code. */ #define CTI_CIDR1_PRMBL_1_Pos (0UL) /*!< Position of PRMBL_1 field. */ #define CTI_CIDR1_PRMBL_1_Msk (0xFUL << CTI_CIDR1_PRMBL_1_Pos) /*!< Bit mask of PRMBL_1 field. */ -#define CTI_CIDR1_PRMBL_1_Value (0b0000UL) /*!< Bits[11:8] of the identification code */ +#define CTI_CIDR1_PRMBL_1_Value (0b0000UL) /*!< Bits[11:8] of the identification code. */ /* Register: CTI_CIDR2 */ /* Description: Component ID2 Register */ -/* Bits 7..0 : Preamble[2]. Contains bits[23:16] of the component identification code */ +/* Bits 7..0 : Preamble[2]. Contains bits[23:16] of the component identification code. */ #define CTI_CIDR2_PRMBL_2_Pos (0UL) /*!< Position of PRMBL_2 field. */ #define CTI_CIDR2_PRMBL_2_Msk (0xFFUL << CTI_CIDR2_PRMBL_2_Pos) /*!< Bit mask of PRMBL_2 field. */ -#define CTI_CIDR2_PRMBL_2_Value (0x05UL) /*!< Bits[23:16] of the identification code */ +#define CTI_CIDR2_PRMBL_2_Value (0x05UL) /*!< Bits[23:16] of the identification code. */ /* Register: CTI_CIDR3 */ /* Description: Component ID3 Register */ -/* Bits 7..0 : Preamble[3]. Contains bits[31:24] of the component identification code */ +/* Bits 7..0 : Preamble[3]. Contains bits[31:24] of the component identification code. */ #define CTI_CIDR3_PRMBL_3_Pos (0UL) /*!< Position of PRMBL_3 field. */ #define CTI_CIDR3_PRMBL_3_Msk (0xFFUL << CTI_CIDR3_PRMBL_3_Pos) /*!< Bit mask of PRMBL_3 field. */ -#define CTI_CIDR3_PRMBL_3_Value (0xB1UL) /*!< Bits[31:24] of the identification code */ +#define CTI_CIDR3_PRMBL_3_Value (0xB1UL) /*!< Bits[31:24] of the identification code. */ /* Peripheral: CTRLAPPERI */ /* Description: Control access port 0 */ /* Register: CTRLAPPERI_MAILBOX_RXDATA */ -/* Description: Data sent from the debugger to the CPU */ +/* Description: Data sent from the debugger to the CPU. */ /* Bits 31..0 : Data received from debugger */ #define CTRLAPPERI_MAILBOX_RXDATA_RXDATA_Pos (0UL) /*!< Position of RXDATA field. */ #define CTRLAPPERI_MAILBOX_RXDATA_RXDATA_Msk (0xFFFFFFFFUL << CTRLAPPERI_MAILBOX_RXDATA_RXDATA_Pos) /*!< Bit mask of RXDATA field. */ /* Register: CTRLAPPERI_MAILBOX_RXSTATUS */ -/* Description: Status to indicate if data sent from the debugger to the CPU has been read */ +/* Description: This register shows a status that indicates if data sent from the debugger to the CPU has been read. */ /* Bit 0 : Status of data in register RXDATA */ #define CTRLAPPERI_MAILBOX_RXSTATUS_RXSTATUS_Pos (0UL) /*!< Position of RXSTATUS field. */ @@ -1765,14 +1765,14 @@ POSSIBILITY OF SUCH DAMAGE. #define CTRLAPPERI_MAILBOX_RXSTATUS_RXSTATUS_DataPending (1UL) /*!< Data pending in register RXDATA */ /* Register: CTRLAPPERI_MAILBOX_TXDATA */ -/* Description: Data sent from the CPU to the debugger */ +/* Description: Data sent from the CPU to the debugger. */ /* Bits 31..0 : Data sent to debugger */ #define CTRLAPPERI_MAILBOX_TXDATA_TXDATA_Pos (0UL) /*!< Position of TXDATA field. */ #define CTRLAPPERI_MAILBOX_TXDATA_TXDATA_Msk (0xFFFFFFFFUL << CTRLAPPERI_MAILBOX_TXDATA_TXDATA_Pos) /*!< Bit mask of TXDATA field. */ /* Register: CTRLAPPERI_MAILBOX_TXSTATUS */ -/* Description: Status to indicate if data sent from the CPU to the debugger has been read */ +/* Description: This register shows a status that indicates if the data sent from the CPU to the debugger has been read. */ /* Bit 0 : Status of data in register TXDATA */ #define CTRLAPPERI_MAILBOX_TXSTATUS_TXSTATUS_Pos (0UL) /*!< Position of TXSTATUS field. */ @@ -1781,39 +1781,39 @@ POSSIBILITY OF SUCH DAMAGE. #define CTRLAPPERI_MAILBOX_TXSTATUS_TXSTATUS_DataPending (1UL) /*!< Data pending in register TXDATA */ /* Register: CTRLAPPERI_ERASEPROTECT_LOCK */ -/* Description: Lock register ERASEPROTECT.DISABLE from being written until next reset */ +/* Description: This register locks the ERASEPROTECT.DISABLE register from being written until next reset. */ -/* Bit 0 : Lock register ERASEPROTECT.DISABLE from being written until next reset */ +/* Bit 0 : Lock ERASEPROTECT.DISABLE register from being written until next reset */ #define CTRLAPPERI_ERASEPROTECT_LOCK_LOCK_Pos (0UL) /*!< Position of LOCK field. */ #define CTRLAPPERI_ERASEPROTECT_LOCK_LOCK_Msk (0x1UL << CTRLAPPERI_ERASEPROTECT_LOCK_LOCK_Pos) /*!< Bit mask of LOCK field. */ #define CTRLAPPERI_ERASEPROTECT_LOCK_LOCK_Unlocked (0UL) /*!< Register ERASEPROTECT.DISABLE is writeable */ #define CTRLAPPERI_ERASEPROTECT_LOCK_LOCK_Locked (1UL) /*!< Register ERASEPROTECT.DISABLE is read-only */ /* Register: CTRLAPPERI_ERASEPROTECT_DISABLE */ -/* Description: Disable ERASEPROTECT and perform ERASEALL */ +/* Description: This register disables the ERASEPROTECT register and performs an ERASEALL operation. */ -/* Bits 31..0 : The ERASEALL sequence will be initiated if value of KEY fields are non-zero and KEY fields match on both CPU and debugger side */ +/* Bits 31..0 : The ERASEALL sequence is initiated if the value of the KEY fields are non-zero and the KEY fields match on both the CPU and debugger sides. */ #define CTRLAPPERI_ERASEPROTECT_DISABLE_KEY_Pos (0UL) /*!< Position of KEY field. */ #define CTRLAPPERI_ERASEPROTECT_DISABLE_KEY_Msk (0xFFFFFFFFUL << CTRLAPPERI_ERASEPROTECT_DISABLE_KEY_Pos) /*!< Bit mask of KEY field. */ /* Register: CTRLAPPERI_APPROTECT_LOCK */ -/* Description: Lock register APPROTECT.DISABLE from being written to until next reset */ +/* Description: This register locks the APPROTECT.DISABLE register from being written to until next reset. */ -/* Bit 0 : Lock register APPROTECT.DISABLE from being written to until next reset */ +/* Bit 0 : Lock the APPROTECT.DISABLE register from being written to until next reset */ #define CTRLAPPERI_APPROTECT_LOCK_LOCK_Pos (0UL) /*!< Position of LOCK field. */ #define CTRLAPPERI_APPROTECT_LOCK_LOCK_Msk (0x1UL << CTRLAPPERI_APPROTECT_LOCK_LOCK_Pos) /*!< Bit mask of LOCK field. */ #define CTRLAPPERI_APPROTECT_LOCK_LOCK_Unlocked (0UL) /*!< Register APPROTECT.DISABLE is writeable */ #define CTRLAPPERI_APPROTECT_LOCK_LOCK_Locked (1UL) /*!< Register APPROTECT.DISABLE is read-only */ /* Register: CTRLAPPERI_APPROTECT_DISABLE */ -/* Description: Disable APPROTECT and enable debug access to non-secure mode */ +/* Description: This register disables the APPROTECT register and enables debug access to non-secure mode. */ -/* Bits 31..0 : Disable APPROTECT and enable debug access to non-secure mode until next pin reset if KEY fields match The current APPROTECT value as configured from UICR is bypassed if value of KEY fields are non-zero and KEY fields match on both CPU and debugger side */ +/* Bits 31..0 : Disable APPROTECT and enable debug access to non-secure mode until the next pin reset if the KEY fields match. The current APPROTECT value as configured from UICR is bypassed if the value of the KEY fields are non-zero and the KEY fields match on both the CPU and debugger sides. */ #define CTRLAPPERI_APPROTECT_DISABLE_KEY_Pos (0UL) /*!< Position of KEY field. */ #define CTRLAPPERI_APPROTECT_DISABLE_KEY_Msk (0xFFFFFFFFUL << CTRLAPPERI_APPROTECT_DISABLE_KEY_Pos) /*!< Bit mask of KEY field. */ /* Register: CTRLAPPERI_SECUREAPPROTECT_LOCK */ -/* Description: Lock register SECUREAPPROTECT.DISABLE from being written until next reset */ +/* Description: This register locks the SECUREAPPROTECT.DISABLE register from being written until next reset. */ /* Bit 0 : Lock register SECUREAPPROTECT.DISABLE from being written until next reset */ #define CTRLAPPERI_SECUREAPPROTECT_LOCK_LOCK_Pos (0UL) /*!< Position of LOCK field. */ @@ -1822,33 +1822,33 @@ POSSIBILITY OF SUCH DAMAGE. #define CTRLAPPERI_SECUREAPPROTECT_LOCK_LOCK_Locked (1UL) /*!< Register SECUREAPPROTECT.DISABLE is read-only */ /* Register: CTRLAPPERI_SECUREAPPROTECT_DISABLE */ -/* Description: Disable SECUREAPPROTECT and enable debug access to secure mode */ +/* Description: This register disables the SECUREAPPROTECT register and enables debug access to secure mode. */ -/* Bits 31..0 : Disable SECUREAPPROTECT and enable debug of secure mode until next pin reset if KEY fields match The current SECUREAPPROTECT value as configured from UICR is bypassed if value of KEY fields are non-zero and KEY fields match on both CPU and debugger side */ +/* Bits 31..0 : Disable SECUREAPPROTECT and enable debug of secure mode until the next pin reset if the KEY fields match. The current SECUREAPPROTECT value as configured from UICR is bypassed if the value of the KEY fields are non-zero and the KEY fields match on both the CPU and debugger sides. */ #define CTRLAPPERI_SECUREAPPROTECT_DISABLE_KEY_Pos (0UL) /*!< Position of KEY field. */ #define CTRLAPPERI_SECUREAPPROTECT_DISABLE_KEY_Msk (0xFFFFFFFFUL << CTRLAPPERI_SECUREAPPROTECT_DISABLE_KEY_Pos) /*!< Bit mask of KEY field. */ /* Register: CTRLAPPERI_STATUS */ /* Description: Status bits for CTRL-AP peripheral */ -/* Bit 2 : Status bit for access port protection in secure mode */ -#define CTRLAPPERI_STATUS_SECUREAPPROTECT_Pos (2UL) /*!< Position of SECUREAPPROTECT field. */ +/* Bit 2 : Status bit for device debug interface mode */ +#define CTRLAPPERI_STATUS_DBGIFACEMODE_Pos (2UL) /*!< Position of DBGIFACEMODE field. */ +#define CTRLAPPERI_STATUS_DBGIFACEMODE_Msk (0x1UL << CTRLAPPERI_STATUS_DBGIFACEMODE_Pos) /*!< Bit mask of DBGIFACEMODE field. */ +#define CTRLAPPERI_STATUS_DBGIFACEMODE_Disabled (0UL) /*!< No debugger attached */ +#define CTRLAPPERI_STATUS_DBGIFACEMODE_Enabled (1UL) /*!< Debugger is attached and device is in debug interface mode */ + +/* Bit 1 : Status bit for access port protection in secure mode */ +#define CTRLAPPERI_STATUS_SECUREAPPROTECT_Pos (1UL) /*!< Position of SECUREAPPROTECT field. */ #define CTRLAPPERI_STATUS_SECUREAPPROTECT_Msk (0x1UL << CTRLAPPERI_STATUS_SECUREAPPROTECT_Pos) /*!< Bit mask of SECUREAPPROTECT field. */ #define CTRLAPPERI_STATUS_SECUREAPPROTECT_Disabled (0UL) /*!< Secure mode access port protection is currently disabled */ #define CTRLAPPERI_STATUS_SECUREAPPROTECT_Enabled (1UL) /*!< Secure mode access port protection is currently enabled */ -/* Bit 1 : Status bit for access port protection in non-secure mode */ -#define CTRLAPPERI_STATUS_APPROTECT_Pos (1UL) /*!< Position of APPROTECT field. */ +/* Bit 0 : Status bit for access port protection in non-secure mode */ +#define CTRLAPPERI_STATUS_APPROTECT_Pos (0UL) /*!< Position of APPROTECT field. */ #define CTRLAPPERI_STATUS_APPROTECT_Msk (0x1UL << CTRLAPPERI_STATUS_APPROTECT_Pos) /*!< Bit mask of APPROTECT field. */ #define CTRLAPPERI_STATUS_APPROTECT_Disabled (0UL) /*!< Non-secure mode access port protection is currently disabled */ #define CTRLAPPERI_STATUS_APPROTECT_Enabled (1UL) /*!< Non-secure mode access port protection is currently enabled */ -/* Bit 0 : Status bit for device debug interface mode */ -#define CTRLAPPERI_STATUS_DBGIFACEMODE_Pos (0UL) /*!< Position of DBGIFACEMODE field. */ -#define CTRLAPPERI_STATUS_DBGIFACEMODE_Msk (0x1UL << CTRLAPPERI_STATUS_DBGIFACEMODE_Pos) /*!< Bit mask of DBGIFACEMODE field. */ -#define CTRLAPPERI_STATUS_DBGIFACEMODE_Disabled (0UL) /*!< No debugger attached */ -#define CTRLAPPERI_STATUS_DBGIFACEMODE_Enabled (1UL) /*!< Debugger is attached and device is in debug interface mode */ - /* Peripheral: DCNF */ /* Description: Domain configuration management 0 */ @@ -3228,7 +3228,7 @@ POSSIBILITY OF SUCH DAMAGE. /* Bits 31..0 : Part Variant, Hardware version and Production configuration, encoded as ASCII */ #define FICR_INFO_VARIANT_VARIANT_Pos (0UL) /*!< Position of VARIANT field. */ #define FICR_INFO_VARIANT_VARIANT_Msk (0xFFFFFFFFUL << FICR_INFO_VARIANT_VARIANT_Pos) /*!< Bit mask of VARIANT field. */ -#define FICR_INFO_VARIANT_VARIANT_AAAA (0x41414141UL) /*!< AAAA */ +#define FICR_INFO_VARIANT_VARIANT_QKAA (0x514B4141UL) /*!< QKAA */ #define FICR_INFO_VARIANT_VARIANT_Unspecified (0xFFFFFFFFUL) /*!< Unspecified */ /* Register: FICR_INFO_PACKAGE */ @@ -3879,6 +3879,15 @@ POSSIBILITY OF SUCH DAMAGE. #define GPIOTE_INTENCLR_IN0_Enabled (1UL) /*!< Read: Enabled */ #define GPIOTE_INTENCLR_IN0_Clear (1UL) /*!< Disable */ +/* Register: GPIOTE_LATENCY */ +/* Description: Latency selection for Event mode (MODE=Event) with rising or falling edge detection on the pin. */ + +/* Bit 0 : Latency setting */ +#define GPIOTE_LATENCY_LATENCY_Pos (0UL) /*!< Position of LATENCY field. */ +#define GPIOTE_LATENCY_LATENCY_Msk (0x1UL << GPIOTE_LATENCY_LATENCY_Pos) /*!< Bit mask of LATENCY field. */ +#define GPIOTE_LATENCY_LATENCY_LowPower (0UL) /*!< Low power setting, for signals with minimum hold time tGPIOTE,HOLD,LP; refer to Electrical specification section */ +#define GPIOTE_LATENCY_LATENCY_LowLatency (1UL) /*!< Low latency setting, for signals with minimum hold time tGPIOTE,HOLD,LL; refer to Electrical specification section */ + /* Register: GPIOTE_CONFIG */ /* Description: Description collection: Configuration for OUT[n], SET[n], and CLR[n] tasks and IN[n] event */ @@ -3924,9 +3933,9 @@ POSSIBILITY OF SUCH DAMAGE. #define I2S_TASKS_START_TASKS_START_Trigger (1UL) /*!< Trigger task */ /* Register: I2S_TASKS_STOP */ -/* Description: Stops I2S transfer. Also stops MCK generator. Triggering this task will cause the event STOPPED to be generated. */ +/* Description: Stops I2S transfer and MCK generator. Triggering this task will cause the event STOPPED to be generated. */ -/* Bit 0 : Stops I2S transfer. Also stops MCK generator. Triggering this task will cause the event STOPPED to be generated. */ +/* Bit 0 : Stops I2S transfer and MCK generator. Triggering this task will cause the event STOPPED to be generated. */ #define I2S_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */ #define I2S_TASKS_STOP_TASKS_STOP_Msk (0x1UL << I2S_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */ #define I2S_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */ @@ -6719,7 +6728,7 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: NVMC_CONFIG */ /* Description: Configuration register */ -/* Bits 2..0 : Program memory access mode. It is strongly recommended to only activate erase and write modes when they are actively used. Enabling write or erase will invalidate the cache and keep it invalidated. */ +/* Bits 2..0 : Program memory access mode. It is strongly recommended to only activate erase and write modes when they are actively used. */ #define NVMC_CONFIG_WEN_Pos (0UL) /*!< Position of WEN field. */ #define NVMC_CONFIG_WEN_Msk (0x7UL << NVMC_CONFIG_WEN_Pos) /*!< Bit mask of WEN field. */ #define NVMC_CONFIG_WEN_Ren (0UL) /*!< Read only access */ @@ -6743,39 +6752,10 @@ POSSIBILITY OF SUCH DAMAGE. #define NVMC_ERASEPAGEPARTIALCFG_DURATION_Pos (0UL) /*!< Position of DURATION field. */ #define NVMC_ERASEPAGEPARTIALCFG_DURATION_Msk (0x7FUL << NVMC_ERASEPAGEPARTIALCFG_DURATION_Pos) /*!< Bit mask of DURATION field. */ -/* Register: NVMC_ICACHECNF */ -/* Description: I-code cache configuration register */ - -/* Bit 8 : Cache profiling enable */ -#define NVMC_ICACHECNF_CACHEPROFEN_Pos (8UL) /*!< Position of CACHEPROFEN field. */ -#define NVMC_ICACHECNF_CACHEPROFEN_Msk (0x1UL << NVMC_ICACHECNF_CACHEPROFEN_Pos) /*!< Bit mask of CACHEPROFEN field. */ -#define NVMC_ICACHECNF_CACHEPROFEN_Disabled (0UL) /*!< Disable cache profiling */ -#define NVMC_ICACHECNF_CACHEPROFEN_Enabled (1UL) /*!< Enable cache profiling */ - -/* Bit 0 : Cache enable */ -#define NVMC_ICACHECNF_CACHEEN_Pos (0UL) /*!< Position of CACHEEN field. */ -#define NVMC_ICACHECNF_CACHEEN_Msk (0x1UL << NVMC_ICACHECNF_CACHEEN_Pos) /*!< Bit mask of CACHEEN field. */ -#define NVMC_ICACHECNF_CACHEEN_Disabled (0UL) /*!< Disable cache. Invalidates all cache entries. */ -#define NVMC_ICACHECNF_CACHEEN_Enabled (1UL) /*!< Enable cache */ - -/* Register: NVMC_IHIT */ -/* Description: I-code cache hit counter */ - -/* Bits 31..0 : Number of cache hits Write zero to clear */ -#define NVMC_IHIT_HITS_Pos (0UL) /*!< Position of HITS field. */ -#define NVMC_IHIT_HITS_Msk (0xFFFFFFFFUL << NVMC_IHIT_HITS_Pos) /*!< Bit mask of HITS field. */ - -/* Register: NVMC_IMISS */ -/* Description: I-code cache miss counter */ - -/* Bits 31..0 : Number of cache misses Write zero to clear */ -#define NVMC_IMISS_MISSES_Pos (0UL) /*!< Position of MISSES field. */ -#define NVMC_IMISS_MISSES_Msk (0xFFFFFFFFUL << NVMC_IMISS_MISSES_Pos) /*!< Bit mask of MISSES field. */ - /* Register: NVMC_CONFIGNS */ /* Description: Unspecified */ -/* Bits 1..0 : Program memory access mode. It is strongly recommended to only activate erase and write modes when they are actively used. Enabling write or erase will invalidate the cache and keep it invalidated. */ +/* Bits 1..0 : Program memory access mode. It is strongly recommended to only activate erase and write modes when they are actively used. */ #define NVMC_CONFIGNS_WEN_Pos (0UL) /*!< Position of WEN field. */ #define NVMC_CONFIGNS_WEN_Msk (0x3UL << NVMC_CONFIGNS_WEN_Pos) /*!< Bit mask of WEN field. */ #define NVMC_CONFIGNS_WEN_Ren (0UL) /*!< Read only access */ @@ -6818,7 +6798,7 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 0 : Enable or disable bypass of LFCLK crystal oscillator with external clock source */ #define OSCILLATORS_XOSC32KI_BYPASS_BYPASS_Pos (0UL) /*!< Position of BYPASS field. */ #define OSCILLATORS_XOSC32KI_BYPASS_BYPASS_Msk (0x1UL << OSCILLATORS_XOSC32KI_BYPASS_BYPASS_Pos) /*!< Bit mask of BYPASS field. */ -#define OSCILLATORS_XOSC32KI_BYPASS_BYPASS_Disabled (0UL) /*!< Disable (use with xtal or low-swing external source) */ +#define OSCILLATORS_XOSC32KI_BYPASS_BYPASS_Disabled (0UL) /*!< Disable (use with crystal or low-swing external source) */ #define OSCILLATORS_XOSC32KI_BYPASS_BYPASS_Enabled (1UL) /*!< Enable (use with rail-to-rail external source) */ /* Register: OSCILLATORS_XOSC32KI_INTCAP */ @@ -8571,11 +8551,7 @@ POSSIBILITY OF SUCH DAMAGE. #define GPIO_PIN_CNF_DRIVE_D0H1 (5UL) /*!< Disconnect '0', high drive '1' (normally used for wired-or connections) */ #define GPIO_PIN_CNF_DRIVE_S0D1 (6UL) /*!< Standard '0', disconnect '1' (normally used for wired-and connections) */ #define GPIO_PIN_CNF_DRIVE_H0D1 (7UL) /*!< High drive '0', disconnect '1' (normally used for wired-and connections) */ -#define GPIO_PIN_CNF_DRIVE_E0S1 (9UL) /*!< Extra high drive '0', standard '1' */ -#define GPIO_PIN_CNF_DRIVE_S0E1 (10UL) /*!< Standard '0', extra high drive '1' */ #define GPIO_PIN_CNF_DRIVE_E0E1 (11UL) /*!< Extra high drive '0', extra high drive '1' */ -#define GPIO_PIN_CNF_DRIVE_D0E1 (13UL) /*!< Disconnect '0', extra high drive '1' (normally used for wired-or connections) */ -#define GPIO_PIN_CNF_DRIVE_E0D1 (15UL) /*!< Extra high drive '0', disconnect '1' (normally used for wired-and connections) */ /* Bits 3..2 : Pull configuration */ #define GPIO_PIN_CNF_PULL_Pos (2UL) /*!< Position of PULL field. */ @@ -8907,17 +8883,17 @@ POSSIBILITY OF SUCH DAMAGE. /* Description: Power control 0 */ /* Register: POWER_TASKS_CONSTLAT */ -/* Description: Enable constant latency mode */ +/* Description: Enable Constant Latency mode */ -/* Bit 0 : Enable constant latency mode */ +/* Bit 0 : Enable Constant Latency mode */ #define POWER_TASKS_CONSTLAT_TASKS_CONSTLAT_Pos (0UL) /*!< Position of TASKS_CONSTLAT field. */ #define POWER_TASKS_CONSTLAT_TASKS_CONSTLAT_Msk (0x1UL << POWER_TASKS_CONSTLAT_TASKS_CONSTLAT_Pos) /*!< Bit mask of TASKS_CONSTLAT field. */ #define POWER_TASKS_CONSTLAT_TASKS_CONSTLAT_Trigger (1UL) /*!< Trigger task */ /* Register: POWER_TASKS_LOWPWR */ -/* Description: Enable low power mode (variable latency) */ +/* Description: Enable Low-Power mode (variable latency) */ -/* Bit 0 : Enable low power mode (variable latency) */ +/* Bit 0 : Enable Low-Power mode (variable latency) */ #define POWER_TASKS_LOWPWR_TASKS_LOWPWR_Pos (0UL) /*!< Position of TASKS_LOWPWR field. */ #define POWER_TASKS_LOWPWR_TASKS_LOWPWR_Msk (0x1UL << POWER_TASKS_LOWPWR_TASKS_LOWPWR_Pos) /*!< Bit mask of TASKS_LOWPWR field. */ #define POWER_TASKS_LOWPWR_TASKS_LOWPWR_Trigger (1UL) /*!< Trigger task */ @@ -9947,23 +9923,23 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: QDEC_REPORTPER */ /* Description: Number of samples to be taken before REPORTRDY and DBLRDY events can be generated */ -/* Bits 3..0 : Specifies the number of samples to be accumulated in the ACC register before the REPORTRDY and DBLRDY events can be generated */ +/* Bits 3..0 : Specifies the number of samples to be accumulated in the ACC register before the REPORTRDY and DBLRDY events can be generated. */ #define QDEC_REPORTPER_REPORTPER_Pos (0UL) /*!< Position of REPORTPER field. */ #define QDEC_REPORTPER_REPORTPER_Msk (0xFUL << QDEC_REPORTPER_REPORTPER_Pos) /*!< Bit mask of REPORTPER field. */ -#define QDEC_REPORTPER_REPORTPER_10Smpl (0UL) /*!< 10 samples / report */ -#define QDEC_REPORTPER_REPORTPER_40Smpl (1UL) /*!< 40 samples / report */ -#define QDEC_REPORTPER_REPORTPER_80Smpl (2UL) /*!< 80 samples / report */ -#define QDEC_REPORTPER_REPORTPER_120Smpl (3UL) /*!< 120 samples / report */ -#define QDEC_REPORTPER_REPORTPER_160Smpl (4UL) /*!< 160 samples / report */ -#define QDEC_REPORTPER_REPORTPER_200Smpl (5UL) /*!< 200 samples / report */ -#define QDEC_REPORTPER_REPORTPER_240Smpl (6UL) /*!< 240 samples / report */ -#define QDEC_REPORTPER_REPORTPER_280Smpl (7UL) /*!< 280 samples / report */ -#define QDEC_REPORTPER_REPORTPER_1Smpl (8UL) /*!< 1 sample / report */ +#define QDEC_REPORTPER_REPORTPER_10Smpl (0UL) /*!< 10 samples/report */ +#define QDEC_REPORTPER_REPORTPER_40Smpl (1UL) /*!< 40 samples/report */ +#define QDEC_REPORTPER_REPORTPER_80Smpl (2UL) /*!< 80 samples/report */ +#define QDEC_REPORTPER_REPORTPER_120Smpl (3UL) /*!< 120 samples/report */ +#define QDEC_REPORTPER_REPORTPER_160Smpl (4UL) /*!< 160 samples/report */ +#define QDEC_REPORTPER_REPORTPER_200Smpl (5UL) /*!< 200 samples/report */ +#define QDEC_REPORTPER_REPORTPER_240Smpl (6UL) /*!< 240 samples/report */ +#define QDEC_REPORTPER_REPORTPER_280Smpl (7UL) /*!< 280 samples/report */ +#define QDEC_REPORTPER_REPORTPER_1Smpl (8UL) /*!< 1 sample/report */ /* Register: QDEC_ACC */ /* Description: Register accumulating the valid transitions */ -/* Bits 31..0 : Register accumulating all valid samples (not double transition) read from the SAMPLE register */ +/* Bits 31..0 : Register accumulating all valid samples (not double transition) read from the SAMPLE register. */ #define QDEC_ACC_ACC_Pos (0UL) /*!< Position of ACC field. */ #define QDEC_ACC_ACC_Msk (0xFFFFFFFFUL << QDEC_ACC_ACC_Pos) /*!< Bit mask of ACC field. */ @@ -10165,9 +10141,9 @@ POSSIBILITY OF SUCH DAMAGE. #define QSPI_SUBSCRIBE_DEACTIVATE_CHIDX_Msk (0xFFUL << QSPI_SUBSCRIBE_DEACTIVATE_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ /* Register: QSPI_EVENTS_READY */ -/* Description: QSPI peripheral is ready. This event will be generated as a response to any QSPI task. */ +/* Description: QSPI peripheral is ready. This event will be generated as a response to all QSPI tasks except DEACTIVATE. */ -/* Bit 0 : QSPI peripheral is ready. This event will be generated as a response to any QSPI task. */ +/* Bit 0 : QSPI peripheral is ready. This event will be generated as a response to all QSPI tasks except DEACTIVATE. */ #define QSPI_EVENTS_READY_EVENTS_READY_Pos (0UL) /*!< Position of EVENTS_READY field. */ #define QSPI_EVENTS_READY_EVENTS_READY_Msk (0x1UL << QSPI_EVENTS_READY_EVENTS_READY_Pos) /*!< Bit mask of EVENTS_READY field. */ #define QSPI_EVENTS_READY_EVENTS_READY_NotGenerated (0UL) /*!< Event not generated */ @@ -10547,18 +10523,18 @@ POSSIBILITY OF SUCH DAMAGE. #define QSPI_DMA_ENC_NONCE2_NONCE2_Msk (0xFFFFFFFFUL << QSPI_DMA_ENC_NONCE2_NONCE2_Pos) /*!< Bit mask of NONCE2 field. */ /* Register: QSPI_DMA_ENC_ENABLE */ -/* Description: Enable stream cipher for XIP */ +/* Description: Enable stream cipher for EasyDMA */ -/* Bit 0 : Enable or disable stream cipher for XIP */ +/* Bit 0 : Enable or disable stream cipher for EasyDMA */ #define QSPI_DMA_ENC_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ #define QSPI_DMA_ENC_ENABLE_ENABLE_Msk (0x1UL << QSPI_DMA_ENC_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ -#define QSPI_DMA_ENC_ENABLE_ENABLE_Disabled (0UL) /*!< Disable stream cipher for QSPI XIP */ -#define QSPI_DMA_ENC_ENABLE_ENABLE_Enabled (1UL) /*!< Enable stream cipher for QSPI XIP */ +#define QSPI_DMA_ENC_ENABLE_ENABLE_Disabled (0UL) /*!< Disable stream cipher for QSPI EasyDMA */ +#define QSPI_DMA_ENC_ENABLE_ENABLE_Enabled (1UL) /*!< Enable stream cipher for QSPI EasyDMA */ /* Register: QSPI_IFCONFIG1 */ /* Description: Interface configuration. */ -/* Bits 31..28 : SCK frequency is given as 96 MHz / (SCKFREQ + 1). */ +/* Bits 31..28 : SCK frequency is derived from PCLK192M with SCK frequency = PCLK192M / (2*(SCKFREQ + 1)). */ #define QSPI_IFCONFIG1_SCKFREQ_Pos (28UL) /*!< Position of SCKFREQ field. */ #define QSPI_IFCONFIG1_SCKFREQ_Msk (0xFUL << QSPI_IFCONFIG1_SCKFREQ_Pos) /*!< Bit mask of SCKFREQ field. */ @@ -10566,7 +10542,6 @@ POSSIBILITY OF SUCH DAMAGE. #define QSPI_IFCONFIG1_SPIMODE_Pos (25UL) /*!< Position of SPIMODE field. */ #define QSPI_IFCONFIG1_SPIMODE_Msk (0x1UL << QSPI_IFCONFIG1_SPIMODE_Pos) /*!< Bit mask of SPIMODE field. */ #define QSPI_IFCONFIG1_SPIMODE_MODE0 (0UL) /*!< Mode 0: Data are captured on the clock rising edge and data is output on a falling edge. Base level of clock is 0 (CPOL=0, CPHA=0). */ -#define QSPI_IFCONFIG1_SPIMODE_MODE3 (1UL) /*!< Mode 3: Data are captured on the clock falling edge and data is output on a rising edge. Base level of clock is 1 (CPOL=1, CPHA=1). */ /* Bit 24 : Enter/exit deep power-down mode (DPM) for external flash memory. */ #define QSPI_IFCONFIG1_DPMEN_Pos (24UL) /*!< Position of DPMEN field. */ @@ -10732,13 +10707,6 @@ POSSIBILITY OF SUCH DAMAGE. #define QSPI_CINSTRDAT1_BYTE4_Pos (0UL) /*!< Position of BYTE4 field. */ #define QSPI_CINSTRDAT1_BYTE4_Msk (0xFFUL << QSPI_CINSTRDAT1_BYTE4_Pos) /*!< Bit mask of BYTE4 field. */ -/* Register: QSPI_IFTIMING */ -/* Description: SPI interface timing. */ - -/* Bits 10..8 : Timing related to sampling of the input serial data. The value of RXDELAY specifies the number of 192 MHz cycles (5.208 ns) delay from the the rising edge of the SPI Clock (SCK) until the input serial data is sampled. As en example, if set to 0 the input serial data is sampled on the rising edge of SCK. */ -#define QSPI_IFTIMING_RXDELAY_Pos (8UL) /*!< Position of RXDELAY field. */ -#define QSPI_IFTIMING_RXDELAY_Msk (0x7UL << QSPI_IFTIMING_RXDELAY_Pos) /*!< Bit mask of RXDELAY field. */ - /* Peripheral: REGULATORS */ /* Description: Voltage regulators 0 */ @@ -10837,12 +10805,6 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: RESET_RESETREAS */ /* Description: Reset reason */ -/* Bit 27 : Reset from network CTRL-AP detected */ -#define RESET_RESETREAS_LCTRLAP_Pos (27UL) /*!< Position of LCTRLAP field. */ -#define RESET_RESETREAS_LCTRLAP_Msk (0x1UL << RESET_RESETREAS_LCTRLAP_Pos) /*!< Bit mask of LCTRLAP field. */ -#define RESET_RESETREAS_LCTRLAP_NotDetected (0UL) /*!< Not detected */ -#define RESET_RESETREAS_LCTRLAP_Detected (1UL) /*!< Detected */ - /* Bit 26 : Reset after wakeup from System OFF mode due to VBUS rising into valid range */ #define RESET_RESETREAS_VBUS_Pos (26UL) /*!< Position of VBUS field. */ #define RESET_RESETREAS_VBUS_Msk (0x1UL << RESET_RESETREAS_VBUS_Pos) /*!< Bit mask of VBUS field. */ @@ -10861,31 +10823,7 @@ POSSIBILITY OF SUCH DAMAGE. #define RESET_RESETREAS_NFC_NotDetected (0UL) /*!< Not detected */ #define RESET_RESETREAS_NFC_Detected (1UL) /*!< Detected */ -/* Bit 23 : Force off reset from application core detected */ -#define RESET_RESETREAS_MFORCEOFF_Pos (23UL) /*!< Position of MFORCEOFF field. */ -#define RESET_RESETREAS_MFORCEOFF_Msk (0x1UL << RESET_RESETREAS_MFORCEOFF_Pos) /*!< Bit mask of MFORCEOFF field. */ -#define RESET_RESETREAS_MFORCEOFF_NotDetected (0UL) /*!< Not detected */ -#define RESET_RESETREAS_MFORCEOFF_Detected (1UL) /*!< Detected */ - -/* Bit 18 : Reset from network watchdog timer detected */ -#define RESET_RESETREAS_LDOG_Pos (18UL) /*!< Position of LDOG field. */ -#define RESET_RESETREAS_LDOG_Msk (0x1UL << RESET_RESETREAS_LDOG_Pos) /*!< Bit mask of LDOG field. */ -#define RESET_RESETREAS_LDOG_NotDetected (0UL) /*!< Not detected */ -#define RESET_RESETREAS_LDOG_Detected (1UL) /*!< Detected */ - -/* Bit 17 : Reset from network CPU lockup detected */ -#define RESET_RESETREAS_LLOCKUP_Pos (17UL) /*!< Position of LLOCKUP field. */ -#define RESET_RESETREAS_LLOCKUP_Msk (0x1UL << RESET_RESETREAS_LLOCKUP_Pos) /*!< Bit mask of LLOCKUP field. */ -#define RESET_RESETREAS_LLOCKUP_NotDetected (0UL) /*!< Not detected */ -#define RESET_RESETREAS_LLOCKUP_Detected (1UL) /*!< Detected */ - -/* Bit 16 : Reset from network soft reset detected */ -#define RESET_RESETREAS_LSREQ_Pos (16UL) /*!< Position of LSREQ field. */ -#define RESET_RESETREAS_LSREQ_Msk (0x1UL << RESET_RESETREAS_LSREQ_Pos) /*!< Bit mask of LSREQ field. */ -#define RESET_RESETREAS_LSREQ_NotDetected (0UL) /*!< Not detected */ -#define RESET_RESETREAS_LSREQ_Detected (1UL) /*!< Detected */ - -/* Bit 7 : Reset due to wakeup from System OFF mode when wakeup is triggered by entering the debug interface mode */ +/* Bit 7 : Reset due to wakeup from System OFF mode when wakeup is triggered by entering the Debug Interface mode */ #define RESET_RESETREAS_DIF_Pos (7UL) /*!< Position of DIF field. */ #define RESET_RESETREAS_DIF_Msk (0x1UL << RESET_RESETREAS_DIF_Pos) /*!< Bit mask of DIF field. */ #define RESET_RESETREAS_DIF_NotDetected (0UL) /*!< Not detected */ @@ -10934,13 +10872,13 @@ POSSIBILITY OF SUCH DAMAGE. #define RESET_RESETREAS_RESETPIN_Detected (1UL) /*!< Detected */ /* Register: RESET_NETWORK_FORCEOFF */ -/* Description: Force off power and clock in network core */ +/* Description: Force network core off */ -/* Bit 0 : Force off power and clock in network core */ +/* Bit 0 : Force network core off */ #define RESET_NETWORK_FORCEOFF_FORCEOFF_Pos (0UL) /*!< Position of FORCEOFF field. */ #define RESET_NETWORK_FORCEOFF_FORCEOFF_Msk (0x1UL << RESET_NETWORK_FORCEOFF_FORCEOFF_Pos) /*!< Bit mask of FORCEOFF field. */ -#define RESET_NETWORK_FORCEOFF_FORCEOFF_Release (0UL) /*!< Release force off signal */ -#define RESET_NETWORK_FORCEOFF_FORCEOFF_Hold (1UL) /*!< Hold force off signal */ +#define RESET_NETWORK_FORCEOFF_FORCEOFF_Release (0UL) /*!< Release Force-OFF */ +#define RESET_NETWORK_FORCEOFF_FORCEOFF_Hold (1UL) /*!< Hold Force-OFF */ /* Peripheral: RTC */ @@ -14604,9 +14542,9 @@ POSSIBILITY OF SUCH DAMAGE. #define TWIM_EVENTS_ERROR_EVENTS_ERROR_Generated (1UL) /*!< Event generated */ /* Register: TWIM_EVENTS_SUSPENDED */ -/* Description: Last byte has been sent out after the SUSPEND task has been issued, TWI traffic is now suspended. */ +/* Description: SUSPEND task has been issued, TWI traffic is now suspended. */ -/* Bit 0 : Last byte has been sent out after the SUSPEND task has been issued, TWI traffic is now suspended. */ +/* Bit 0 : SUSPEND task has been issued, TWI traffic is now suspended. */ #define TWIM_EVENTS_SUSPENDED_EVENTS_SUSPENDED_Pos (0UL) /*!< Position of EVENTS_SUSPENDED field. */ #define TWIM_EVENTS_SUSPENDED_EVENTS_SUSPENDED_Msk (0x1UL << TWIM_EVENTS_SUSPENDED_EVENTS_SUSPENDED_Pos) /*!< Bit mask of EVENTS_SUSPENDED field. */ #define TWIM_EVENTS_SUSPENDED_EVENTS_SUSPENDED_NotGenerated (0UL) /*!< Event not generated */ @@ -16415,7 +16353,7 @@ POSSIBILITY OF SUCH DAMAGE. /* Description: Access port protection */ /* Bits 31..0 : Blocks debugger read/write access to all CPU registers and - memory mapped addresses Using any value not listed below will yield unexpected results. */ + memory mapped addresses Using any value except Unprotected will lead to the protection being enabled. */ #define UICR_APPROTECT_PALL_Pos (0UL) /*!< Position of PALL field. */ #define UICR_APPROTECT_PALL_Msk (0xFFFFFFFFUL << UICR_APPROTECT_PALL_Pos) /*!< Bit mask of PALL field. */ #define UICR_APPROTECT_PALL_Protected (0x00000000UL) /*!< Protected */ @@ -16458,7 +16396,7 @@ POSSIBILITY OF SUCH DAMAGE. /* Description: Secure access port protection */ /* Bits 31..0 : Blocks debugger read/write access to all secure CPU registers and secure memory - mapped addresses. Using any value not listed below will yield unexpected results. */ + mapped addresses. Using any value except Unprotected will lead to the protection being enabled. */ #define UICR_SECUREAPPROTECT_PALL_Pos (0UL) /*!< Position of PALL field. */ #define UICR_SECUREAPPROTECT_PALL_Msk (0xFFFFFFFFUL << UICR_SECUREAPPROTECT_PALL_Pos) /*!< Bit mask of PALL field. */ #define UICR_SECUREAPPROTECT_PALL_Protected (0x00000000UL) /*!< Protected */ @@ -16467,7 +16405,7 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: UICR_ERASEPROTECT */ /* Description: Erase protection */ -/* Bits 31..0 : Blocks NVMC ERASEALL and CTRLAP ERASEALL functionality. Using any value not listed below will yield unexpected results. */ +/* Bits 31..0 : Blocks NVMC ERASEALL and CTRLAP ERASEALL functionality. Using any value except Unprotected will lead to the protection being enabled. */ #define UICR_ERASEPROTECT_PALL_Pos (0UL) /*!< Position of PALL field. */ #define UICR_ERASEPROTECT_PALL_Msk (0xFFFFFFFFUL << UICR_ERASEPROTECT_PALL_Pos) /*!< Bit mask of PALL field. */ #define UICR_ERASEPROTECT_PALL_Protected (0x00000000UL) /*!< Protected */ diff --git a/mdk/nrf5340_network.h b/mdk/nrf5340_network.h index f8ec27b45f..54c1739393 100644 --- a/mdk/nrf5340_network.h +++ b/mdk/nrf5340_network.h @@ -18,10 +18,10 @@ * @file nrf5340_network.h * @brief CMSIS HeaderFile * @version 1 - * @date 04. March 2020 - * @note Generated by SVDConv V3.3.25 on Wednesday, 04.03.2020 14:56:53 + * @date 14. August 2020 + * @note Generated by SVDConv V3.3.35 on Friday, 14.08.2020 15:02:14 * from File 'nrf5340_network.svd', - * last modified on Wednesday, 04.03.2020 13:56:45 + * last modified on Friday, 14.08.2020 13:02:07 */ @@ -107,7 +107,7 @@ typedef enum { #define __MPU_PRESENT 1 /*!< MPU present */ #define __FPU_PRESENT 0 /*!< FPU present */ #define __FPU_DP 0 /*!< unused, Device has no FPU */ -#define __SAU_REGION_PRESENT 0 /*!< SAU present */ +#define __SAUREGION_PRESENT 0 /*!< SAU region present */ /** @} */ /* End of group Configuration_of_CMSIS */ @@ -175,35 +175,19 @@ typedef struct { } VREQCTRL_VREGRADIO_Type; /*!< Size = 12 (0xc) */ -/** - * @brief CLOCK_HFCLKAUDIO [HFCLKAUDIO] (Unspecified) - */ -typedef struct { - __IOM uint32_t FREQUENCY; /*!< (@ 0x00000000) Audio PLL frequency in 11.176 MHz - 11.402 MHz - or 12.165 MHz - 12.411 MHz frequency bands */ -} CLOCK_HFCLKAUDIO_Type; /*!< Size = 4 (0x4) */ - - -/** - * @brief RESET_NETWORK [NETWORK] (ULP network core control) - */ -typedef struct { - __IM uint32_t RESERVED; - __IOM uint32_t FORCEOFF; /*!< (@ 0x00000004) Force off power and clock in network core */ -} RESET_NETWORK_Type; /*!< Size = 8 (0x8) */ - - /** * @brief CTRLAPPERI_MAILBOX [MAILBOX] (Unspecified) */ typedef struct { - __IM uint32_t RXDATA; /*!< (@ 0x00000000) Data sent from the debugger to the CPU */ - __IM uint32_t RXSTATUS; /*!< (@ 0x00000004) Status to indicate if data sent from the debugger - to the CPU has been read */ + __IM uint32_t RXDATA; /*!< (@ 0x00000000) Data sent from the debugger to the CPU. */ + __IM uint32_t RXSTATUS; /*!< (@ 0x00000004) This register shows a status that indicates if + data sent from the debugger to the CPU has + been read. */ __IM uint32_t RESERVED[30]; - __IOM uint32_t TXDATA; /*!< (@ 0x00000080) Data sent from the CPU to the debugger */ - __IM uint32_t TXSTATUS; /*!< (@ 0x00000084) Status to indicate if data sent from the CPU - to the debugger has been read */ + __IOM uint32_t TXDATA; /*!< (@ 0x00000080) Data sent from the CPU to the debugger. */ + __IM uint32_t TXSTATUS; /*!< (@ 0x00000084) This register shows a status that indicates if + the data sent from the CPU to the debugger + has been read. */ } CTRLAPPERI_MAILBOX_Type; /*!< Size = 136 (0x88) */ @@ -211,9 +195,10 @@ typedef struct { * @brief CTRLAPPERI_ERASEPROTECT [ERASEPROTECT] (Unspecified) */ typedef struct { - __IOM uint32_t LOCK; /*!< (@ 0x00000000) Lock register ERASEPROTECT.DISABLE from being - written until next reset */ - __IOM uint32_t DISABLE; /*!< (@ 0x00000004) Disable ERASEPROTECT and perform ERASEALL */ + __IOM uint32_t LOCK; /*!< (@ 0x00000000) This register locks the ERASEPROTECT.DISABLE + register from being written until next reset. */ + __IOM uint32_t DISABLE; /*!< (@ 0x00000004) This register disables the ERASEPROTECT register + and performs an ERASEALL operation. */ } CTRLAPPERI_ERASEPROTECT_Type; /*!< Size = 8 (0x8) */ @@ -221,24 +206,13 @@ typedef struct { * @brief CTRLAPPERI_APPROTECT [APPROTECT] (Unspecified) */ typedef struct { - __IOM uint32_t LOCK; /*!< (@ 0x00000000) Lock register APPROTECT.DISABLE from being written - to until next reset */ - __IOM uint32_t DISABLE; /*!< (@ 0x00000004) Disable APPROTECT and enable debug access to - non-secure mode */ + __IOM uint32_t LOCK; /*!< (@ 0x00000000) This register locks the APPROTECT.DISABLE register + from being written to until next reset. */ + __IOM uint32_t DISABLE; /*!< (@ 0x00000004) This register disables the APPROTECT register + and enables debug access to non-secure mode. */ } CTRLAPPERI_APPROTECT_Type; /*!< Size = 8 (0x8) */ -/** - * @brief CTRLAPPERI_SECUREAPPROTECT [SECUREAPPROTECT] (Unspecified) - */ -typedef struct { - __IOM uint32_t LOCK; /*!< (@ 0x00000000) Lock register SECUREAPPROTECT.DISABLE from being - written until next reset */ - __IOM uint32_t DISABLE; /*!< (@ 0x00000004) Disable SECUREAPPROTECT and enable debug access - to secure mode */ -} CTRLAPPERI_SECUREAPPROTECT_Type; /*!< Size = 8 (0x8) */ - - /** * @brief RADIO_PSEL [PSEL] (Unspecified) */ @@ -630,82 +604,52 @@ typedef struct { /*!< (@ 0x41005000) CLOCK_NS Str __OM uint32_t TASKS_LFCLKSTART; /*!< (@ 0x00000008) Start LFCLK source as selected in LFCLKSRC */ __OM uint32_t TASKS_LFCLKSTOP; /*!< (@ 0x0000000C) Stop LFCLK source */ __OM uint32_t TASKS_CAL; /*!< (@ 0x00000010) Start calibration of LFRC oscillator */ - __IM uint32_t RESERVED; - __OM uint32_t TASKS_HFCLKAUDIOSTART; /*!< (@ 0x00000018) Start HFCLKAUDIO source */ - __OM uint32_t TASKS_HFCLKAUDIOSTOP; /*!< (@ 0x0000001C) Stop HFCLKAUDIO source */ - __OM uint32_t TASKS_HFCLK192MSTART; /*!< (@ 0x00000020) Start HFCLK192M source as selected in HFCLK192MSRC */ - __OM uint32_t TASKS_HFCLK192MSTOP; /*!< (@ 0x00000024) Stop HFCLK192M source */ - __IM uint32_t RESERVED1[22]; + __IM uint32_t RESERVED[27]; __IOM uint32_t SUBSCRIBE_HFCLKSTART; /*!< (@ 0x00000080) Subscribe configuration for task HFCLKSTART */ __IOM uint32_t SUBSCRIBE_HFCLKSTOP; /*!< (@ 0x00000084) Subscribe configuration for task HFCLKSTOP */ __IOM uint32_t SUBSCRIBE_LFCLKSTART; /*!< (@ 0x00000088) Subscribe configuration for task LFCLKSTART */ __IOM uint32_t SUBSCRIBE_LFCLKSTOP; /*!< (@ 0x0000008C) Subscribe configuration for task LFCLKSTOP */ __IOM uint32_t SUBSCRIBE_CAL; /*!< (@ 0x00000090) Subscribe configuration for task CAL */ - __IM uint32_t RESERVED2; - __IOM uint32_t SUBSCRIBE_HFCLKAUDIOSTART; /*!< (@ 0x00000098) Subscribe configuration for task HFCLKAUDIOSTART */ - __IOM uint32_t SUBSCRIBE_HFCLKAUDIOSTOP; /*!< (@ 0x0000009C) Subscribe configuration for task HFCLKAUDIOSTOP */ - __IOM uint32_t SUBSCRIBE_HFCLK192MSTART; /*!< (@ 0x000000A0) Subscribe configuration for task HFCLK192MSTART */ - __IOM uint32_t SUBSCRIBE_HFCLK192MSTOP; /*!< (@ 0x000000A4) Subscribe configuration for task HFCLK192MSTOP */ - __IM uint32_t RESERVED3[22]; + __IM uint32_t RESERVED1[27]; __IOM uint32_t EVENTS_HFCLKSTARTED; /*!< (@ 0x00000100) HFCLK128M/HFCLK64M source started */ __IOM uint32_t EVENTS_LFCLKSTARTED; /*!< (@ 0x00000104) LFCLK source started */ - __IM uint32_t RESERVED4[5]; + __IM uint32_t RESERVED2[5]; __IOM uint32_t EVENTS_DONE; /*!< (@ 0x0000011C) Calibration of LFRC oscillator complete event */ - __IOM uint32_t EVENTS_HFCLKAUDIOSTARTED; /*!< (@ 0x00000120) HFCLKAUDIO source started */ - __IOM uint32_t EVENTS_HFCLK192MSTARTED; /*!< (@ 0x00000124) HFCLK192M source started */ - __IM uint32_t RESERVED5[22]; + __IM uint32_t RESERVED3[24]; __IOM uint32_t PUBLISH_HFCLKSTARTED; /*!< (@ 0x00000180) Publish configuration for event HFCLKSTARTED */ __IOM uint32_t PUBLISH_LFCLKSTARTED; /*!< (@ 0x00000184) Publish configuration for event LFCLKSTARTED */ - __IM uint32_t RESERVED6[5]; + __IM uint32_t RESERVED4[5]; __IOM uint32_t PUBLISH_DONE; /*!< (@ 0x0000019C) Publish configuration for event DONE */ - __IOM uint32_t PUBLISH_HFCLKAUDIOSTARTED; /*!< (@ 0x000001A0) Publish configuration for event HFCLKAUDIOSTARTED */ - __IOM uint32_t PUBLISH_HFCLK192MSTARTED; /*!< (@ 0x000001A4) Publish configuration for event HFCLK192MSTARTED */ - __IM uint32_t RESERVED7[86]; + __IM uint32_t RESERVED5[88]; __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ __IM uint32_t INTPEND; /*!< (@ 0x0000030C) Pending interrupts */ - __IM uint32_t RESERVED8[62]; + __IM uint32_t RESERVED6[62]; __IM uint32_t HFCLKRUN; /*!< (@ 0x00000408) Status indicating that HFCLKSTART task has been triggered */ __IM uint32_t HFCLKSTAT; /*!< (@ 0x0000040C) Status indicating which HFCLK128M/HFCLK64M source - is running Note: Value of this register - in any CLOCK instance reflects status only - due to configurations/actions in that CLOCK - instance. */ - __IM uint32_t RESERVED9; + is running This register value in any CLOCK + instance reflects status only due to configurations/action + in that CLOCK instance. */ + __IM uint32_t RESERVED7; __IM uint32_t LFCLKRUN; /*!< (@ 0x00000414) Status indicating that LFCLKSTART task has been triggered */ __IM uint32_t LFCLKSTAT; /*!< (@ 0x00000418) Status indicating which LFCLK source is running - Note: Value of this register in any CLOCK - instance reflects status only due to configurations/action + This register value in any CLOCK instance + reflects status only due to configurations/actions in that CLOCK instance. */ __IM uint32_t LFCLKSRCCOPY; /*!< (@ 0x0000041C) Copy of LFCLKSRC register, set when LFCLKSTART task was triggered */ - __IM uint32_t RESERVED10[12]; - __IM uint32_t HFCLKAUDIORUN; /*!< (@ 0x00000450) Status indicating that HFCLKAUDIOSTART task has - been triggered */ - __IM uint32_t HFCLKAUDIOSTAT; /*!< (@ 0x00000454) Status indicating which HFCLKAUDIO source is - running */ - __IM uint32_t HFCLK192MRUN; /*!< (@ 0x00000458) Status indicating that HFCLK192MSTART task has - been triggered */ - __IM uint32_t HFCLK192MSTAT; /*!< (@ 0x0000045C) Status indicating which HFCLK192M source is running */ - __IM uint32_t RESERVED11[45]; + __IM uint32_t RESERVED8[61]; __IOM uint32_t HFCLKSRC; /*!< (@ 0x00000514) Clock source for HFCLK128M/HFCLK64M */ __IOM uint32_t LFCLKSRC; /*!< (@ 0x00000518) Clock source for LFCLK */ - __IM uint32_t RESERVED12[15]; + __IM uint32_t RESERVED9[15]; __IOM uint32_t HFCLKCTRL; /*!< (@ 0x00000558) HFCLK128M frequency configuration */ - __IOM CLOCK_HFCLKAUDIO_Type HFCLKAUDIO; /*!< (@ 0x0000055C) Unspecified */ - __IM uint32_t RESERVED13[4]; - __IM uint32_t HFCLKALWAYSRUN; /*!< (@ 0x00000570) Automatic or manual control of HFCLK128M/HFCLK64M */ - __IM uint32_t LFCLKALWAYSRUN; /*!< (@ 0x00000574) Automatic or manual control of LFCLK */ - __IM uint32_t RESERVED14; - __IM uint32_t HFCLKAUDIOALWAYSRUN; /*!< (@ 0x0000057C) Automatic or manual control of HFCLKAUDIO */ - __IOM uint32_t HFCLK192MSRC; /*!< (@ 0x00000580) Clock source for HFCLK192M */ - __IM uint32_t HFCLK192MALWAYSRUN; /*!< (@ 0x00000584) Automatic or manual control of HFCLK192M */ - __IM uint32_t RESERVED15[12]; - __IOM uint32_t HFCLK192MCTRL; /*!< (@ 0x000005B8) HFCLK192M frequency configuration */ -} NRF_CLOCK_Type; /*!< Size = 1468 (0x5bc) */ + __IM uint32_t RESERVED10[5]; + __IOM uint32_t HFCLKALWAYSRUN; /*!< (@ 0x00000570) Automatic or manual control of HFCLK128M/HFCLK64M */ + __IOM uint32_t LFCLKALWAYSRUN; /*!< (@ 0x00000574) Automatic or manual control of LFCLK */ +} NRF_CLOCK_Type; /*!< Size = 1400 (0x578) */ @@ -720,8 +664,8 @@ typedef struct { /*!< (@ 0x41005000) CLOCK_NS Str typedef struct { /*!< (@ 0x41005000) POWER_NS Structure */ __IM uint32_t RESERVED[30]; - __OM uint32_t TASKS_CONSTLAT; /*!< (@ 0x00000078) Enable constant latency mode */ - __OM uint32_t TASKS_LOWPWR; /*!< (@ 0x0000007C) Enable low power mode (variable latency) */ + __OM uint32_t TASKS_CONSTLAT; /*!< (@ 0x00000078) Enable Constant Latency mode */ + __OM uint32_t TASKS_LOWPWR; /*!< (@ 0x0000007C) Enable Low-Power mode (variable latency) */ __IM uint32_t RESERVED1[30]; __IOM uint32_t SUBSCRIBE_CONSTLAT; /*!< (@ 0x000000F8) Subscribe configuration for task CONSTLAT */ __IOM uint32_t SUBSCRIBE_LOWPWR; /*!< (@ 0x000000FC) Subscribe configuration for task LOWPWR */ @@ -758,9 +702,7 @@ typedef struct { /*!< (@ 0x41005000) POWER_NS Str typedef struct { /*!< (@ 0x41005000) RESET_NS Structure */ __IM uint32_t RESERVED[256]; __IOM uint32_t RESETREAS; /*!< (@ 0x00000400) Reset reason */ - __IM uint32_t RESERVED1[131]; - __IOM RESET_NETWORK_Type NETWORK; /*!< (@ 0x00000610) ULP network core control */ -} NRF_RESET_Type; /*!< Size = 1560 (0x618) */ +} NRF_RESET_Type; /*!< Size = 1028 (0x404) */ @@ -780,8 +722,7 @@ typedef struct { /*!< (@ 0x41006000) CTRLAP_NS St __IOM CTRLAPPERI_ERASEPROTECT_Type ERASEPROTECT;/*!< (@ 0x00000500) Unspecified */ __IM uint32_t RESERVED2[14]; __IOM CTRLAPPERI_APPROTECT_Type APPROTECT; /*!< (@ 0x00000540) Unspecified */ - __IOM CTRLAPPERI_SECUREAPPROTECT_Type SECUREAPPROTECT;/*!< (@ 0x00000548) Unspecified */ - __IM uint32_t RESERVED3[44]; + __IM uint32_t RESERVED3[46]; __IM uint32_t STATUS; /*!< (@ 0x00000600) Status bits for CTRL-AP peripheral */ } NRF_CTRLAPPERI_Type; /*!< Size = 1540 (0x604) */ @@ -858,8 +799,10 @@ typedef struct { /*!< (@ 0x41008000) RADIO_NS Str __IOM uint32_t EVENTS_RXREADY; /*!< (@ 0x00000158) RADIO has ramped up and is ready to be started RX path */ __IOM uint32_t EVENTS_MHRMATCH; /*!< (@ 0x0000015C) MAC header match found */ - __IM uint32_t RESERVED4[3]; - __IOM uint32_t EVENTS_PHYEND; /*!< (@ 0x0000016C) Generated when last bit is sent on air */ + __IM uint32_t RESERVED4[2]; + __IOM uint32_t EVENTS_SYNC; /*!< (@ 0x00000168) Preamble indicator */ + __IOM uint32_t EVENTS_PHYEND; /*!< (@ 0x0000016C) Generated when last bit is sent on air, or received + from air */ __IOM uint32_t EVENTS_CTEPRESENT; /*!< (@ 0x00000170) CTE is present (early warning right after receiving CTEInfo byte) */ __IM uint32_t RESERVED5[3]; @@ -886,7 +829,8 @@ typedef struct { /*!< (@ 0x41008000) RADIO_NS Str __IOM uint32_t PUBLISH_TXREADY; /*!< (@ 0x000001D4) Publish configuration for event TXREADY */ __IOM uint32_t PUBLISH_RXREADY; /*!< (@ 0x000001D8) Publish configuration for event RXREADY */ __IOM uint32_t PUBLISH_MHRMATCH; /*!< (@ 0x000001DC) Publish configuration for event MHRMATCH */ - __IM uint32_t RESERVED8[3]; + __IM uint32_t RESERVED8[2]; + __IOM uint32_t PUBLISH_SYNC; /*!< (@ 0x000001E8) Publish configuration for event SYNC */ __IOM uint32_t PUBLISH_PHYEND; /*!< (@ 0x000001EC) Publish configuration for event PHYEND */ __IOM uint32_t PUBLISH_CTEPRESENT; /*!< (@ 0x000001F0) Publish configuration for event CTEPRESENT */ __IM uint32_t RESERVED9[3]; @@ -1035,7 +979,11 @@ typedef struct { /*!< (@ 0x4100A000) GPIOTE_NS St __IM uint32_t RESERVED6[65]; __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ - __IM uint32_t RESERVED7[129]; + __IM uint32_t RESERVED7[126]; + __IOM uint32_t LATENCY; /*!< (@ 0x00000504) Latency selection for Event mode (MODE=Event) + with rising or falling edge detection on + the pin. */ + __IM uint32_t RESERVED8[2]; __IOM uint32_t CONFIG[8]; /*!< (@ 0x00000510) Description collection: Configuration for OUT[n], SET[n], and CLR[n] tasks and IN[n] event */ } NRF_GPIOTE_Type; /*!< Size = 1328 (0x530) */ @@ -1599,9 +1547,8 @@ typedef struct { /*!< (@ 0x41013000) TWIM0_NS Str __IM uint32_t RESERVED8[7]; __IOM uint32_t EVENTS_ERROR; /*!< (@ 0x00000124) TWI error */ __IM uint32_t RESERVED9[8]; - __IOM uint32_t EVENTS_SUSPENDED; /*!< (@ 0x00000148) Last byte has been sent out after the SUSPEND - task has been issued, TWI traffic is now - suspended. */ + __IOM uint32_t EVENTS_SUSPENDED; /*!< (@ 0x00000148) SUSPEND task has been issued, TWI traffic is + now suspended. */ __IOM uint32_t EVENTS_RXSTARTED; /*!< (@ 0x0000014C) Receive sequence started */ __IOM uint32_t EVENTS_TXSTARTED; /*!< (@ 0x00000150) Transmit sequence started */ __IM uint32_t RESERVED10[2]; @@ -1904,10 +1851,7 @@ typedef struct { /*!< (@ 0x41080000) NVMC_NS Stru __IM uint32_t RESERVED6; __IOM uint32_t IHIT; /*!< (@ 0x00000548) I-code cache hit counter */ __IOM uint32_t IMISS; /*!< (@ 0x0000054C) I-code cache miss counter */ - __IM uint32_t RESERVED7[13]; - __IOM uint32_t CONFIGNS; /*!< (@ 0x00000584) Unspecified */ - __OM uint32_t WRITEUICRNS; /*!< (@ 0x00000588) Non-secure APPROTECT enable register */ -} NRF_NVMC_Type; /*!< Size = 1420 (0x58c) */ +} NRF_NVMC_Type; /*!< Size = 1360 (0x550) */ diff --git a/mdk/nrf5340_network.svd b/mdk/nrf5340_network.svd index 4757733cd4..e03445183d 100644 --- a/mdk/nrf5340_network.svd +++ b/mdk/nrf5340_network.svd @@ -152,9 +152,9 @@ POSSIBILITY OF SUCH DAMAGE. 31 - AAAA - AAAA - 0x41414141 + QKAA + QKAA + 0x514B4141 Unspecified @@ -508,7 +508,7 @@ POSSIBILITY OF SUCH DAMAGE. PALL Blocks debugger read/write access to all CPU registers and memory mapped - addresses Any value except for the enumerations will yield unexpected results. + addresses Using any value except Unprotected will lead to the protection being enabled. 0 31 @@ -535,7 +535,7 @@ POSSIBILITY OF SUCH DAMAGE. PALL - Blocks NVMC ERASEALL and CTRLAP ERASEALL functionality. Any value except for the enumerations will yield unexpected results. + Blocks NVMC ERASEALL and CTRLAP ERASEALL functionality. Using any value except Unprotected will lead to the protection being enabled. 0 31 @@ -613,7 +613,7 @@ POSSIBILITY OF SUCH DAMAGE. GLBEN - Enables or disables the CTI + Enables or disables the CTI. 0 0 @@ -647,7 +647,7 @@ POSSIBILITY OF SUCH DAMAGE. write Acknowledge - Clears the ctitrigout + Clears the ctitrigout. 1 @@ -661,7 +661,7 @@ POSSIBILITY OF SUCH DAMAGE. write Acknowledge - Clears the ctitrigout + Clears the ctitrigout. 1 @@ -675,7 +675,7 @@ POSSIBILITY OF SUCH DAMAGE. write Acknowledge - Clears the ctitrigout + Clears the ctitrigout. 1 @@ -689,7 +689,7 @@ POSSIBILITY OF SUCH DAMAGE. write Acknowledge - Clears the ctitrigout + Clears the ctitrigout. 1 @@ -703,7 +703,7 @@ POSSIBILITY OF SUCH DAMAGE. write Acknowledge - Clears the ctitrigout + Clears the ctitrigout. 1 @@ -717,7 +717,7 @@ POSSIBILITY OF SUCH DAMAGE. write Acknowledge - Clears the ctitrigout + Clears the ctitrigout. 1 @@ -731,7 +731,7 @@ POSSIBILITY OF SUCH DAMAGE. write Acknowledge - Clears the ctitrigout + Clears the ctitrigout. 1 @@ -745,7 +745,7 @@ POSSIBILITY OF SUCH DAMAGE. write Acknowledge - Clears the ctitrigout + Clears the ctitrigout. 1 @@ -761,7 +761,7 @@ POSSIBILITY OF SUCH DAMAGE. APPSET_0 - Application trigger event for channel 0 + Application trigger event for channel 0. 0 0 @@ -788,7 +788,7 @@ POSSIBILITY OF SUCH DAMAGE. APPSET_1 - Application trigger event for channel 1 + Application trigger event for channel 1. 1 1 @@ -815,7 +815,7 @@ POSSIBILITY OF SUCH DAMAGE. APPSET_2 - Application trigger event for channel 2 + Application trigger event for channel 2. 2 2 @@ -842,7 +842,7 @@ POSSIBILITY OF SUCH DAMAGE. APPSET_3 - Application trigger event for channel 3 + Application trigger event for channel 3. 3 3 @@ -885,7 +885,7 @@ POSSIBILITY OF SUCH DAMAGE. write Clear - Clears the event for channel 0 + Clears the event for channel 0. 1 @@ -899,7 +899,7 @@ POSSIBILITY OF SUCH DAMAGE. write Clear - Clears the event for channel 1 + Clears the event for channel 1. 1 @@ -913,7 +913,7 @@ POSSIBILITY OF SUCH DAMAGE. write Clear - Clears the event for channel 2 + Clears the event for channel 2. 1 @@ -927,7 +927,7 @@ POSSIBILITY OF SUCH DAMAGE. write Clear - Clears the event for channel 3 + Clears the event for channel 3. 1 @@ -950,7 +950,7 @@ POSSIBILITY OF SUCH DAMAGE. write Generate - Generates an event pulse on channel 0 + Generates an event pulse on channel 0. 1 @@ -964,7 +964,7 @@ POSSIBILITY OF SUCH DAMAGE. write Generate - Generates an event pulse on channel 1 + Generates an event pulse on channel 1. 1 @@ -978,7 +978,7 @@ POSSIBILITY OF SUCH DAMAGE. write Generate - Generates an event pulse on channel 2 + Generates an event pulse on channel 2. 1 @@ -992,7 +992,7 @@ POSSIBILITY OF SUCH DAMAGE. write Generate - Generates an event pulse on channel 3 + Generates an event pulse on channel 3. 1 @@ -1010,72 +1010,72 @@ POSSIBILITY OF SUCH DAMAGE. TRIGINEN_0 - Enables a cross trigger event to channel 0 when a ctitrigin input is activated + Enables a cross trigger event to channel 0 when a ctitrigin input is activated. 0 0 Disabled - Input trigger n events are ignored by channel 0 + Input trigger n events are ignored by channel 0. 0 Enabled - When an event is received on input trigger n (ctitrigin[n]) generate an event on channel 0 + When an event is received on input trigger n (ctitrigin[n]), generate an event on channel 0. 1 TRIGINEN_1 - Enables a cross trigger event to channel 1 when a ctitrigin input is activated + Enables a cross trigger event to channel 1 when a ctitrigin input is activated. 1 1 Disabled - Input trigger n events are ignored by channel 1 + Input trigger n events are ignored by channel 1. 0 Enabled - When an event is received on input trigger n (ctitrigin[n]) generate an event on channel 1 + When an event is received on input trigger n (ctitrigin[n]), generate an event on channel 1. 1 TRIGINEN_2 - Enables a cross trigger event to channel 2 when a ctitrigin input is activated + Enables a cross trigger event to channel 2 when a ctitrigin input is activated. 2 2 Disabled - Input trigger n events are ignored by channel 2 + Input trigger n events are ignored by channel 2. 0 Enabled - When an event is received on input trigger n (ctitrigin[n]) generate an event on channel 2 + When an event is received on input trigger n (ctitrigin[n]), generate an event on channel 2. 1 TRIGINEN_3 - Enables a cross trigger event to channel 3 when a ctitrigin input is activated + Enables a cross trigger event to channel 3 when a ctitrigin input is activated. 3 3 Disabled - Input trigger n events are ignored by channel 3 + Input trigger n events are ignored by channel 3. 0 Enabled - When an event is received on input trigger n (ctitrigin[n]) generate an event on channel 3 + When an event is received on input trigger n (ctitrigin[n]), generate an event on channel 3. 1 @@ -1093,72 +1093,72 @@ POSSIBILITY OF SUCH DAMAGE. TRIGOUTEN_0 - Enables a cross trigger event to ctitrigout when channel 0 when is activated + Enables a cross trigger event to ctitrigout when channel 0 is activated. 0 0 Disabled - Channel 0 is ignored by output trigger n + Channel 0 is ignored by output trigger n. 0 Enabled - When an event occur on channel 0, generate an event on output event n (ctitrigout[n]) + When an event occurs on channel 0, generate an event on output event n (ctitrigout[n]). 1 TRIGOUTEN_1 - Enables a cross trigger event to ctitrigout when channel 1 when is activated + Enables a cross trigger event to ctitrigout when channel 1 is activated. 1 1 Disabled - Channel 1 is ignored by output trigger n + Channel 1 is ignored by output trigger n. 0 Enabled - When an event occur on channel 1, generate an event on output event n (ctitrigout[n]) + When an event occurs on channel 1, generate an event on output event n (ctitrigout[n]). 1 TRIGOUTEN_2 - Enables a cross trigger event to ctitrigout when channel 2 when is activated + Enables a cross trigger event to ctitrigout when channel 2 is activated. 2 2 Disabled - Channel 2 is ignored by output trigger n + Channel 2 is ignored by output trigger n. 0 Enabled - When an event occur on channel 2, generate an event on output event n (ctitrigout[n]) + When an event occurs on channel 2, generate an event on output event n (ctitrigout[n]). 1 TRIGOUTEN_3 - Enables a cross trigger event to ctitrigout when channel 3 when is activated + Enables a cross trigger event to ctitrigout when channel 3 is activated. 3 3 Disabled - Channel 3 is ignored by output trigger n + Channel 3 is ignored by output trigger n. 0 Enabled - When an event occur on channel 3, generate an event on output event n (ctitrigout[n]) + When an event occurs on channel 3, generate an event on output event n (ctitrigout[n]). 1 @@ -1180,12 +1180,12 @@ POSSIBILITY OF SUCH DAMAGE. Active - Ctitrigin 0 is active + Ctitrigin 0 is active. 1 Inactive - Ctitrigin 0 is inactive + Ctitrigin 0 is inactive. 0 @@ -1198,12 +1198,12 @@ POSSIBILITY OF SUCH DAMAGE. Active - Ctitrigin 1 is active + Ctitrigin 1 is active. 1 Inactive - Ctitrigin 1 is inactive + Ctitrigin 1 is inactive. 0 @@ -1216,12 +1216,12 @@ POSSIBILITY OF SUCH DAMAGE. Active - Ctitrigin 2 is active + Ctitrigin 2 is active. 1 Inactive - Ctitrigin 2 is inactive + Ctitrigin 2 is inactive. 0 @@ -1234,12 +1234,12 @@ POSSIBILITY OF SUCH DAMAGE. Active - Ctitrigin 3 is active + Ctitrigin 3 is active. 1 Inactive - Ctitrigin 3 is inactive + Ctitrigin 3 is inactive. 0 @@ -1252,12 +1252,12 @@ POSSIBILITY OF SUCH DAMAGE. Active - Ctitrigin 4 is active + Ctitrigin 4 is active. 1 Inactive - Ctitrigin 4 is inactive + Ctitrigin 4 is inactive. 0 @@ -1270,12 +1270,12 @@ POSSIBILITY OF SUCH DAMAGE. Active - Ctitrigin 5 is active + Ctitrigin 5 is active. 1 Inactive - Ctitrigin 5 is inactive + Ctitrigin 5 is inactive. 0 @@ -1288,12 +1288,12 @@ POSSIBILITY OF SUCH DAMAGE. Active - Ctitrigin 6 is active + Ctitrigin 6 is active. 1 Inactive - Ctitrigin 6 is inactive + Ctitrigin 6 is inactive. 0 @@ -1306,12 +1306,12 @@ POSSIBILITY OF SUCH DAMAGE. Active - Ctitrigin 7 is active + Ctitrigin 7 is active. 1 Inactive - Ctitrigin 7 is inactive + Ctitrigin 7 is inactive. 0 @@ -1333,12 +1333,12 @@ POSSIBILITY OF SUCH DAMAGE. Active - Ctitrigout 0 is active + Ctitrigout 0 is active. 1 Inactive - Ctitrigout 0 is inactive + Ctitrigout 0 is inactive. 0 @@ -1351,12 +1351,12 @@ POSSIBILITY OF SUCH DAMAGE. Active - Ctitrigout 1 is active + Ctitrigout 1 is active. 1 Inactive - Ctitrigout 1 is inactive + Ctitrigout 1 is inactive. 0 @@ -1369,12 +1369,12 @@ POSSIBILITY OF SUCH DAMAGE. Active - Ctitrigout 2 is active + Ctitrigout 2 is active. 1 Inactive - Ctitrigout 2 is inactive + Ctitrigout 2 is inactive. 0 @@ -1387,12 +1387,12 @@ POSSIBILITY OF SUCH DAMAGE. Active - Ctitrigout 3 is active + Ctitrigout 3 is active. 1 Inactive - Ctitrigout 3 is inactive + Ctitrigout 3 is inactive. 0 @@ -1405,12 +1405,12 @@ POSSIBILITY OF SUCH DAMAGE. Active - Ctitrigout 4 is active + Ctitrigout 4 is active. 1 Inactive - Ctitrigout 4 is inactive + Ctitrigout 4 is inactive. 0 @@ -1423,12 +1423,12 @@ POSSIBILITY OF SUCH DAMAGE. Active - Ctitrigout 5 is active + Ctitrigout 5 is active. 1 Inactive - Ctitrigout 5 is inactive + Ctitrigout 5 is inactive. 0 @@ -1441,12 +1441,12 @@ POSSIBILITY OF SUCH DAMAGE. Active - Ctitrigout 6 is active + Ctitrigout 6 is active. 1 Inactive - Ctitrigout 6 is inactive + Ctitrigout 6 is inactive. 0 @@ -1459,12 +1459,12 @@ POSSIBILITY OF SUCH DAMAGE. Active - Ctitrigout 7 is active + Ctitrigout 7 is active. 1 Inactive - Ctitrigout 7 is inactive + Ctitrigout 7 is inactive. 0 @@ -1486,12 +1486,12 @@ POSSIBILITY OF SUCH DAMAGE. Active - Ctichin 0 is active + Ctichin 0 is active. 1 Inactive - Ctichin 0 is inactive + Ctichin 0 is inactive. 0 @@ -1504,12 +1504,12 @@ POSSIBILITY OF SUCH DAMAGE. Active - Ctichin 1 is active + Ctichin 1 is active. 1 Inactive - Ctichin 1 is inactive + Ctichin 1 is inactive. 0 @@ -1522,12 +1522,12 @@ POSSIBILITY OF SUCH DAMAGE. Active - Ctichin 2 is active + Ctichin 2 is active. 1 Inactive - Ctichin 2 is inactive + Ctichin 2 is inactive. 0 @@ -1540,12 +1540,12 @@ POSSIBILITY OF SUCH DAMAGE. Active - Ctichin 3 is active + Ctichin 3 is active. 1 Inactive - Ctichin 3 is inactive + Ctichin 3 is inactive. 0 @@ -1561,72 +1561,72 @@ POSSIBILITY OF SUCH DAMAGE. CTIGATEEN_0 - Enable ctichout0 + Enable ctichout0. 0 0 Enabled - Enable ctichout channel 0 propagation + Enable ctichout channel 0 propagation. 1 Disabled - Disable ctichout channel 0 propagation + Disable ctichout channel 0 propagation. 0 CTIGATEEN_1 - Enable ctichout1 + Enable ctichout1. 1 1 Enabled - Enable ctichout channel 1 propagation + Enable ctichout channel 1 propagation. 1 Disabled - Disable ctichout channel 1 propagation + Disable ctichout channel 1 propagation. 0 CTIGATEEN_2 - Enable ctichout2 + Enable ctichout2. 2 2 Enabled - Enable ctichout channel 2 propagation + Enable ctichout channel 2 propagation. 1 Disabled - Disable ctichout channel 2 propagation + Disable ctichout channel 2 propagation. 0 CTIGATEEN_3 - Enable ctichout3 + Enable ctichout3. 3 3 Enabled - Enable ctichout channel 3 propagation + Enable ctichout channel 3 propagation. 1 Disabled - Disable ctichout channel 3 propagation + Disable ctichout channel 3 propagation. 0 @@ -1642,7 +1642,7 @@ POSSIBILITY OF SUCH DAMAGE. Architecture - Contains the CTI device architecture + Contains the CTI device architecture. 0 0 @@ -1664,13 +1664,13 @@ POSSIBILITY OF SUCH DAMAGE. NUMTRIG - Number of ECT triggers available + Number of ECT triggers available. 8 15 NUMCH - Number of ECT channels available + Number of ECT channels available. 16 19 @@ -1686,13 +1686,13 @@ POSSIBILITY OF SUCH DAMAGE. MAJOR Major classification of the type of the debug component as specified in the ARM Architecture Specification for this - debug and trace component + debug and trace component. 0 3 Controller - Indicates that this component allows a debugger to control other components in a CoreSight SoC-400 system + Indicates that this component allows a debugger to control other components in a CoreSight SoC-400 system. 0b0100 @@ -1706,7 +1706,7 @@ POSSIBILITY OF SUCH DAMAGE. Crosstrigger - Indicates that this component is a sub-triggering component + Indicates that this component is a sub-triggering component. 0b0001 @@ -1722,7 +1722,7 @@ POSSIBILITY OF SUCH DAMAGE. DES_2 - Together, PIDR1.DES_0, PIDR2.DES_1, and PIDR4.DES_2 identify the designer of the component + Together, PIDR1.DES_0, PIDR2.DES_1, and PIDR4.DES_2 identify the designer of the component. 0 3 @@ -1735,7 +1735,7 @@ POSSIBILITY OF SUCH DAMAGE. SIZE - Always 0b0000. Indicates that the device only occupies 4KB of memory + Always 0b0000. Indicates that the device only occupies 4KB of memory. 4 7 @@ -1768,13 +1768,13 @@ POSSIBILITY OF SUCH DAMAGE. PART_0 - Bits[7:0] of the 12-bit part number of the component. The designer of the component assigns this part number + Bits[7:0] of the 12-bit part number of the component. The designer of the component assigns this part number. 0 7 PartnumberL - Indicates bits[7:0] of the part number of the component + Indicates bits[7:0] of the part number of the component. 0x21 @@ -1790,20 +1790,20 @@ POSSIBILITY OF SUCH DAMAGE. PART_1 - Bits[11:8] of the 12-bit part number of the component. The designer of the component assigns this part number + Bits[11:8] of the 12-bit part number of the component. The designer of the component assigns this part number. 0 3 PartnumberH - Indicates bits[11:8] of the part number of the component + Indicates bits[11:8] of the part number of the component. 0b1101 DES_0 - Together, PIDR1.DES_0, PIDR2.DES_1, and PIDR4.DES_2 identify the designer of the component + Together, PIDR1.DES_0, PIDR2.DES_1, and PIDR4.DES_2 identify the designer of the component. 4 7 @@ -1825,7 +1825,7 @@ POSSIBILITY OF SUCH DAMAGE. DES_1 - Together, PIDR1.DES_0, PIDR2.DES_1, and PIDR4.DES_2 identify the designer of the component + Together, PIDR1.DES_0, PIDR2.DES_1, and PIDR4.DES_2 identify the designer of the component. 0 2 @@ -1838,7 +1838,7 @@ POSSIBILITY OF SUCH DAMAGE. JEDEC - Always 1. Indicates that the JEDEC-assigned designer ID is used + Always 1. Indicates that the JEDEC-assigned designer ID is used. 3 3 @@ -1873,7 +1873,7 @@ POSSIBILITY OF SUCH DAMAGE. Unmodified - Indicates that the customer has not modified this component + Indicates that the customer has not modified this component. 0b000 @@ -1888,7 +1888,7 @@ POSSIBILITY OF SUCH DAMAGE. NoErrata - Indicates that there are no errata fixes to this component + Indicates that there are no errata fixes to this component. 0b000 @@ -1904,13 +1904,13 @@ POSSIBILITY OF SUCH DAMAGE. PRMBL_0 - Preamble[0]. Contains bits[7:0] of the component identification code + Preamble[0]. Contains bits[7:0] of the component identification code. 0 7 Value - Bits[7:0] of the identification code + Bits[7:0] of the identification code. 0x0D @@ -1926,13 +1926,13 @@ POSSIBILITY OF SUCH DAMAGE. PRMBL_1 - Preamble[1]. Contains bits[11:8] of the component identification code + Preamble[1]. Contains bits[11:8] of the component identification code. 0 3 Value - Bits[11:8] of the identification code + Bits[11:8] of the identification code. 0b0000 @@ -1946,7 +1946,7 @@ POSSIBILITY OF SUCH DAMAGE. Coresight - Indicates that the component is a CoreSight component + Indicates that the component is a CoreSight component. 0b1001 @@ -1962,13 +1962,13 @@ POSSIBILITY OF SUCH DAMAGE. PRMBL_2 - Preamble[2]. Contains bits[23:16] of the component identification code + Preamble[2]. Contains bits[23:16] of the component identification code. 0 7 Value - Bits[23:16] of the identification code + Bits[23:16] of the identification code. 0x05 @@ -1984,13 +1984,13 @@ POSSIBILITY OF SUCH DAMAGE. PRMBL_3 - Preamble[3]. Contains bits[31:24] of the component identification code + Preamble[3]. Contains bits[31:24] of the component identification code. 0 7 Value - Bits[31:24] of the identification code + Bits[31:24] of the identification code. 0xB1 @@ -2231,90 +2231,6 @@ POSSIBILITY OF SUCH DAMAGE. - - TASKS_HFCLKAUDIOSTART - Start HFCLKAUDIO source - 0x018 - write-only - - - TASKS_HFCLKAUDIOSTART - Start HFCLKAUDIO source - 0 - 0 - - - Trigger - Trigger task - 1 - - - - - - - TASKS_HFCLKAUDIOSTOP - Stop HFCLKAUDIO source - 0x01C - write-only - - - TASKS_HFCLKAUDIOSTOP - Stop HFCLKAUDIO source - 0 - 0 - - - Trigger - Trigger task - 1 - - - - - - - TASKS_HFCLK192MSTART - Start HFCLK192M source as selected in HFCLK192MSRC - 0x020 - write-only - - - TASKS_HFCLK192MSTART - Start HFCLK192M source as selected in HFCLK192MSRC - 0 - 0 - - - Trigger - Trigger task - 1 - - - - - - - TASKS_HFCLK192MSTOP - Stop HFCLK192M source - 0x024 - write-only - - - TASKS_HFCLK192MSTOP - Stop HFCLK192M source - 0 - 0 - - - Trigger - Trigger task - 1 - - - - - SUBSCRIBE_HFCLKSTART Subscribe configuration for task HFCLKSTART @@ -2323,7 +2239,7 @@ POSSIBILITY OF SUCH DAMAGE. CHIDX - Channel that task HFCLKSTART will subscribe to + DPPI channel that task HFCLKSTART will subscribe to 0 7 @@ -2354,7 +2270,7 @@ POSSIBILITY OF SUCH DAMAGE. CHIDX - Channel that task HFCLKSTOP will subscribe to + DPPI channel that task HFCLKSTOP will subscribe to 0 7 @@ -2385,7 +2301,7 @@ POSSIBILITY OF SUCH DAMAGE. CHIDX - Channel that task LFCLKSTART will subscribe to + DPPI channel that task LFCLKSTART will subscribe to 0 7 @@ -2416,7 +2332,7 @@ POSSIBILITY OF SUCH DAMAGE. CHIDX - Channel that task LFCLKSTOP will subscribe to + DPPI channel that task LFCLKSTOP will subscribe to 0 7 @@ -2447,131 +2363,7 @@ POSSIBILITY OF SUCH DAMAGE. CHIDX - Channel that task CAL will subscribe to - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable subscription - 0 - - - Enabled - Enable subscription - 1 - - - - - - - SUBSCRIBE_HFCLKAUDIOSTART - Subscribe configuration for task HFCLKAUDIOSTART - 0x098 - read-write - - - CHIDX - Channel that task HFCLKAUDIOSTART will subscribe to - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable subscription - 0 - - - Enabled - Enable subscription - 1 - - - - - - - SUBSCRIBE_HFCLKAUDIOSTOP - Subscribe configuration for task HFCLKAUDIOSTOP - 0x09C - read-write - - - CHIDX - Channel that task HFCLKAUDIOSTOP will subscribe to - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable subscription - 0 - - - Enabled - Enable subscription - 1 - - - - - - - SUBSCRIBE_HFCLK192MSTART - Subscribe configuration for task HFCLK192MSTART - 0x0A0 - read-write - - - CHIDX - Channel that task HFCLK192MSTART will subscribe to - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable subscription - 0 - - - Enabled - Enable subscription - 1 - - - - - - - SUBSCRIBE_HFCLK192MSTOP - Subscribe configuration for task HFCLK192MSTOP - 0x0A4 - read-write - - - CHIDX - Channel that task HFCLK192MSTOP will subscribe to + DPPI channel that task CAL will subscribe to 0 7 @@ -2672,58 +2464,6 @@ POSSIBILITY OF SUCH DAMAGE. - - EVENTS_HFCLKAUDIOSTARTED - HFCLKAUDIO source started - 0x120 - read-write - - - EVENTS_HFCLKAUDIOSTARTED - HFCLKAUDIO source started - 0 - 0 - - - NotGenerated - Event not generated - 0 - - - Generated - Event generated - 1 - - - - - - - EVENTS_HFCLK192MSTARTED - HFCLK192M source started - 0x124 - read-write - - - EVENTS_HFCLK192MSTARTED - HFCLK192M source started - 0 - 0 - - - NotGenerated - Event not generated - 0 - - - Generated - Event generated - 1 - - - - - PUBLISH_HFCLKSTARTED Publish configuration for event HFCLKSTARTED @@ -2732,7 +2472,7 @@ POSSIBILITY OF SUCH DAMAGE. CHIDX - Channel that event HFCLKSTARTED will publish to. + DPPI channel that event HFCLKSTARTED will publish to. 0 7 @@ -2763,7 +2503,7 @@ POSSIBILITY OF SUCH DAMAGE. CHIDX - Channel that event LFCLKSTARTED will publish to. + DPPI channel that event LFCLKSTARTED will publish to. 0 7 @@ -2794,69 +2534,7 @@ POSSIBILITY OF SUCH DAMAGE. CHIDX - Channel that event DONE will publish to. - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable publishing - 0 - - - Enabled - Enable publishing - 1 - - - - - - - PUBLISH_HFCLKAUDIOSTARTED - Publish configuration for event HFCLKAUDIOSTARTED - 0x1A0 - read-write - - - CHIDX - Channel that event HFCLKAUDIOSTARTED will publish to. - 0 - 7 - - - EN - 31 - 31 - - - Disabled - Disable publishing - 0 - - - Enabled - Enable publishing - 1 - - - - - - - PUBLISH_HFCLK192MSTARTED - Publish configuration for event HFCLK192MSTARTED - 0x1A4 - read-write - - - CHIDX - Channel that event HFCLK192MSTARTED will publish to. + DPPI channel that event DONE will publish to. 0 7 @@ -2939,42 +2617,6 @@ POSSIBILITY OF SUCH DAMAGE. - - HFCLKAUDIOSTARTED - Enable or disable interrupt for event HFCLKAUDIOSTARTED - 8 - 8 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - - - HFCLK192MSTARTED - Enable or disable interrupt for event HFCLK192MSTARTED - 9 - 9 - - - Disabled - Disable - 0 - - - Enabled - Enable - 1 - - - @@ -3064,60 +2706,6 @@ POSSIBILITY OF SUCH DAMAGE. - - HFCLKAUDIOSTARTED - Write '1' to enable interrupt for event HFCLKAUDIOSTARTED - 8 - 8 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - - - HFCLK192MSTARTED - Write '1' to enable interrupt for event HFCLK192MSTARTED - 9 - 9 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Set - Enable - 1 - - - @@ -3207,60 +2795,6 @@ POSSIBILITY OF SUCH DAMAGE. - - HFCLKAUDIOSTARTED - Write '1' to disable interrupt for event HFCLKAUDIOSTARTED - 8 - 8 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - - - HFCLK192MSTARTED - Write '1' to disable interrupt for event HFCLK192MSTARTED - 9 - 9 - - read - - Disabled - Read: Disabled - 0 - - - Enabled - Read: Enabled - 1 - - - - write - - Clear - Disable - 1 - - - @@ -3326,44 +2860,6 @@ POSSIBILITY OF SUCH DAMAGE. - - HFCLKAUDIOSTARTED - Read pending status of interrupt for event HFCLKAUDIOSTARTED - 8 - 8 - - read - - NotPending - Read: Not pending - 0 - - - Pending - Read: Pending - 1 - - - - - HFCLK192MSTARTED - Read pending status of interrupt for event HFCLK192MSTARTED - 9 - 9 - - read - - NotPending - Read: Not pending - 0 - - - Pending - Read: Pending - 1 - - - @@ -3394,7 +2890,7 @@ POSSIBILITY OF SUCH DAMAGE. HFCLKSTAT - Status indicating which HFCLK128M/HFCLK64M source is running Note: Value of this register in any CLOCK instance reflects status only due to configurations/actions in that CLOCK instance. + Status indicating which HFCLK128M/HFCLK64M source is running This register value in any CLOCK instance reflects status only due to configurations/actions in that CLOCK instance. 0x40C read-only @@ -3482,7 +2978,7 @@ POSSIBILITY OF SUCH DAMAGE. LFCLKSTAT - Status indicating which LFCLK source is running Note: Value of this register in any CLOCK instance reflects status only due to configurations/actions in that CLOCK instance. + Status indicating which LFCLK source is running This register value in any CLOCK instance reflects status only due to configurations/actions in that CLOCK instance. 0x418 read-only @@ -3589,164 +3085,6 @@ POSSIBILITY OF SUCH DAMAGE. - - HFCLKAUDIORUN - Status indicating that HFCLKAUDIOSTART task has been triggered - 0x450 - read-only - - - STATUS - HFCLKAUDIOSTART task triggered or not - 0 - 0 - - - NotTriggered - Task not triggered - 0 - - - Triggered - Task triggered - 1 - - - - - - - HFCLKAUDIOSTAT - Status indicating which HFCLKAUDIO source is running - 0x454 - read-only - - - ALWAYSRUNNING - ALWAYSRUN activated - 4 - 4 - - - NotRunning - Automatic clock control enabled - 0 - - - Running - Oscillator is always running - 1 - - - - - STATE - HFCLKAUDIO state - 16 - 16 - - - NotRunning - HFCLKAUDIO not running - 0 - - - Running - HFCLKAUDIO running - 1 - - - - - - - HFCLK192MRUN - Status indicating that HFCLK192MSTART task has been triggered - 0x458 - read-only - - - STATUS - HFCLK192MSTART task triggered or not - 0 - 0 - - - NotTriggered - Task not triggered - 0 - - - Triggered - Task triggered - 1 - - - - - - - HFCLK192MSTAT - Status indicating which HFCLK192M source is running - 0x45C - read-only - - - SRC - Active clock source - 0 - 0 - - - HFINT - Clock source: HFINT - on-chip oscillator - 0 - - - HFXO - Clock source: HFXO - derived from external 32 MHz crystal oscillator - 1 - - - - - ALWAYSRUNNING - ALWAYSRUN activated - 4 - 4 - - - NotRunning - Automatic clock control enabled - 0 - - - Running - Oscillator is always running - 1 - - - - - STATE - HFCLK192M state - 16 - 16 - - - NotRunning - HFCLK192M not running - 0 - - - Running - HFCLK192M running - 1 - - - - - HFCLKSRC Clock source for HFCLK128M/HFCLK64M @@ -3822,7 +3160,7 @@ POSSIBILITY OF SUCH DAMAGE. HCLK High frequency clock HCLK 0 - 0 + 1 Div1 @@ -3838,33 +3176,11 @@ POSSIBILITY OF SUCH DAMAGE. - - HFCLKAUDIO - Unspecified - CLOCK_HFCLKAUDIO - read-write - 0x55C - - FREQUENCY - Audio PLL frequency in 11.176 MHz - 11.402 MHz or 12.165 MHz - 12.411 MHz frequency bands - 0x000 - read-write - 0x00009BAE - - - FREQUENCY - Frequency 0: 10.666 MHz 65535: 13.333 MHz - 0 - 15 - - - - HFCLKALWAYSRUN Automatic or manual control of HFCLK128M/HFCLK64M 0x570 - read-only + read-write ALWAYSRUN @@ -3890,86 +3206,7 @@ POSSIBILITY OF SUCH DAMAGE. LFCLKALWAYSRUN Automatic or manual control of LFCLK 0x574 - read-only - - - ALWAYSRUN - Ensure clock is always running - 0 - 0 - - - Automatic - Use automatic clock control - 0 - - - AlwaysRun - Ensure clock is always running - 1 - - - - - - - HFCLKAUDIOALWAYSRUN - Automatic or manual control of HFCLKAUDIO - 0x57C - read-only - - - ALWAYSRUN - Ensure clock is always running - 0 - 0 - - - Automatic - Use automatic clock control - 0 - - - AlwaysRun - Ensure clock is always running - 1 - - - - - - - HFCLK192MSRC - Clock source for HFCLK192M - 0x580 read-write - 0x00000001 - - - SRC - Select which HFCLK192M source is started by the HFCLK192MSTART task - 0 - 0 - - - HFINT - HFCLK192MSTART task starts HFINT oscillator - 0 - - - HFXO - HFCLK192MSTART task starts HFXO oscillator - 1 - - - - - - - HFCLK192MALWAYSRUN - Automatic or manual control of HFCLK192M - 0x584 - read-only ALWAYSRUN @@ -3991,38 +3228,6 @@ POSSIBILITY OF SUCH DAMAGE. - - HFCLK192MCTRL - HFCLK192M frequency configuration - 0x5B8 - read-write - 0x00000002 - - - HCLK192M - High frequency clock HCLK192M - 0 - 1 - - - Div1 - Divide HFCLK192M by 1 - 0 - - - Div2 - Divide HFCLK192M by 2 - 1 - - - Div4 - Divide HFCLK192M by 4 - 2 - - - - - @@ -4047,13 +3252,13 @@ POSSIBILITY OF SUCH DAMAGE. TASKS_CONSTLAT - Enable constant latency mode + Enable Constant Latency mode 0x78 write-only TASKS_CONSTLAT - Enable constant latency mode + Enable Constant Latency mode 0 0 @@ -4068,13 +3273,13 @@ POSSIBILITY OF SUCH DAMAGE. TASKS_LOWPWR - Enable low power mode (variable latency) + Enable Low-Power mode (variable latency) 0x7C write-only TASKS_LOWPWR - Enable low power mode (variable latency) + Enable Low-Power mode (variable latency) 0 0 @@ -4095,7 +3300,7 @@ POSSIBILITY OF SUCH DAMAGE. CHIDX - Channel that task CONSTLAT will subscribe to + DPPI channel that task CONSTLAT will subscribe to 0 7 @@ -4126,7 +3331,7 @@ POSSIBILITY OF SUCH DAMAGE. CHIDX - Channel that task LOWPWR will subscribe to + DPPI channel that task LOWPWR will subscribe to 0 7 @@ -4235,7 +3440,7 @@ POSSIBILITY OF SUCH DAMAGE. CHIDX - Channel that event POFWARN will publish to. + DPPI channel that event POFWARN will publish to. 0 7 @@ -4266,7 +3471,7 @@ POSSIBILITY OF SUCH DAMAGE. CHIDX - Channel that event SLEEPENTER will publish to. + DPPI channel that event SLEEPENTER will publish to. 0 7 @@ -4297,7 +3502,7 @@ POSSIBILITY OF SUCH DAMAGE. CHIDX - Channel that event SLEEPEXIT will publish to. + DPPI channel that event SLEEPEXIT will publish to. 0 7 @@ -4728,7 +3933,7 @@ POSSIBILITY OF SUCH DAMAGE. DIF - Reset due to wakeup from System OFF mode when wakeup is triggered by entering the debug interface mode + Reset due to wakeup from System OFF mode when wakeup is triggered by entering the Debug Interface mode 7 7 @@ -4800,7 +4005,7 @@ POSSIBILITY OF SUCH DAMAGE. MFORCEOFF - Force off reset from application core detected + Force-OFF reset from application core detected 23 23 @@ -4890,40 +4095,6 @@ POSSIBILITY OF SUCH DAMAGE. - - NETWORK - ULP network core control - RESET_NETWORK - read-write - 0x610 - - FORCEOFF - Force off power and clock in network core - 0x004 - read-write - 0x00000001 - - - FORCEOFF - Force off power and clock in network core - 0 - 0 - - - Release - Release force off signal - 0 - - - Hold - Hold force off signal - 1 - - - - - - @@ -4949,7 +4120,7 @@ POSSIBILITY OF SUCH DAMAGE. 0x400 RXDATA - Data sent from the debugger to the CPU + Data sent from the debugger to the CPU. 0x000 read-only 0x00000000 @@ -4964,7 +4135,7 @@ POSSIBILITY OF SUCH DAMAGE. RXSTATUS - Status to indicate if data sent from the debugger to the CPU has been read + This register shows a status that indicates if data sent from the debugger to the CPU has been read. 0x004 read-only 0x00000000 @@ -4991,7 +4162,7 @@ POSSIBILITY OF SUCH DAMAGE. TXDATA - Data sent from the CPU to the debugger + Data sent from the CPU to the debugger. 0x80 read-write 0x00000000 @@ -5006,7 +4177,7 @@ POSSIBILITY OF SUCH DAMAGE. TXSTATUS - Status to indicate if data sent from the CPU to the debugger has been read + This register shows a status that indicates if the data sent from the CPU to the debugger has been read. 0x84 read-only 0x00000000 @@ -5040,14 +4211,14 @@ POSSIBILITY OF SUCH DAMAGE. 0x500 LOCK - Lock register ERASEPROTECT.DISABLE from being written until next reset + This register locks the ERASEPROTECT.DISABLE register from being written until next reset. 0x000 read-writeonce 0x00000000 LOCK - Lock register ERASEPROTECT.DISABLE from being written until next reset + Lock ERASEPROTECT.DISABLE register from being written until next reset 0 0 @@ -5067,14 +4238,14 @@ POSSIBILITY OF SUCH DAMAGE. DISABLE - Disable ERASEPROTECT and perform ERASEALL + This register disables the ERASEPROTECT register and performs an ERASEALL operation. 0x004 read-write 0x00000000 KEY - The ERASEALL sequence will be initiated if value of KEY fields are non-zero and KEY fields match on both CPU and debugger side + The ERASEALL sequence is initiated if the value of the KEY fields are non-zero and the KEY fields match on both the CPU and debugger sides. 0 31 @@ -5089,14 +4260,14 @@ POSSIBILITY OF SUCH DAMAGE. 0x540 LOCK - Lock register APPROTECT.DISABLE from being written to until next reset + This register locks the APPROTECT.DISABLE register from being written to until next reset. 0x000 read-writeonce 0x00000000 LOCK - Lock register APPROTECT.DISABLE from being written to until next reset + Lock the APPROTECT.DISABLE register from being written to until next reset 0 0 @@ -5116,63 +4287,14 @@ POSSIBILITY OF SUCH DAMAGE. DISABLE - Disable APPROTECT and enable debug access to non-secure mode - 0x004 - read-write - 0x00000000 - - - KEY - Disable APPROTECT and enable debug access to non-secure mode until next pin reset if KEY fields match The current APPROTECT value as configured from UICR is bypassed if value of KEY fields are non-zero and KEY fields match on both CPU and debugger side - 0 - 31 - - - - - - SECUREAPPROTECT - Unspecified - CTRLAPPERI_SECUREAPPROTECT - read-write - 0x548 - - LOCK - Lock register SECUREAPPROTECT.DISABLE from being written until next reset - 0x000 - read-writeonce - 0x00000000 - - - LOCK - Lock register SECUREAPPROTECT.DISABLE from being written until next reset - 0 - 0 - - - Unlocked - Register SECUREAPPROTECT.DISABLE is writeable - 0 - - - Locked - Register SECUREAPPROTECT.DISABLE is read-only - 1 - - - - - - - DISABLE - Disable SECUREAPPROTECT and enable debug access to secure mode + This register disables the APPROTECT register and enables debug access to non-secure mode. 0x004 read-write 0x00000000 KEY - Disable SECUREAPPROTECT and enable debug of secure mode until next pin reset if KEY fields match The current SECUREAPPROTECT value as configured from UICR is bypassed if value of KEY fields are non-zero and KEY fields match on both CPU and debugger side + Disable APPROTECT and enable debug access to non-secure mode until the next pin reset if the KEY fields match. The current APPROTECT value as configured from UICR is bypassed if the value of the KEY fields are non-zero and the KEY fields match on both the CPU and debugger sides. 0 31 @@ -5186,29 +4308,11 @@ POSSIBILITY OF SUCH DAMAGE. read-only 0x00000000 - - DBGIFACEMODE - Status bit for device debug interface mode - 0 - 0 - - - Disabled - No debugger attached - 0 - - - Enabled - Debugger is attached and device is in debug interface mode - 1 - - - APPROTECT Status bit for access port protection in non-secure mode - 1 - 1 + 0 + 0 Disabled @@ -5223,19 +4327,19 @@ POSSIBILITY OF SUCH DAMAGE. - SECUREAPPROTECT - Status bit for access port protection in secure mode + DBGIFACEMODE + Status bit for device debug interface mode 2 2 Disabled - Secure mode access port protection is currently disabled + No debugger attached 0 Enabled - Secure mode access port protection is currently enabled + Debugger is attached and device is in debug interface mode 1 @@ -5544,7 +4648,7 @@ POSSIBILITY OF SUCH DAMAGE. CHIDX - Channel that task TXEN will subscribe to + DPPI channel that task TXEN will subscribe to 0 7 @@ -5575,7 +4679,7 @@ POSSIBILITY OF SUCH DAMAGE. CHIDX - Channel that task RXEN will subscribe to + DPPI channel that task RXEN will subscribe to 0 7 @@ -5606,7 +4710,7 @@ POSSIBILITY OF SUCH DAMAGE. CHIDX - Channel that task START will subscribe to + DPPI channel that task START will subscribe to 0 7 @@ -5637,7 +4741,7 @@ POSSIBILITY OF SUCH DAMAGE. CHIDX - Channel that task STOP will subscribe to + DPPI channel that task STOP will subscribe to 0 7 @@ -5668,7 +4772,7 @@ POSSIBILITY OF SUCH DAMAGE. CHIDX - Channel that task DISABLE will subscribe to + DPPI channel that task DISABLE will subscribe to 0 7 @@ -5699,7 +4803,7 @@ POSSIBILITY OF SUCH DAMAGE. CHIDX - Channel that task RSSISTART will subscribe to + DPPI channel that task RSSISTART will subscribe to 0 7 @@ -5730,7 +4834,7 @@ POSSIBILITY OF SUCH DAMAGE. CHIDX - Channel that task RSSISTOP will subscribe to + DPPI channel that task RSSISTOP will subscribe to 0 7 @@ -5761,7 +4865,7 @@ POSSIBILITY OF SUCH DAMAGE. CHIDX - Channel that task BCSTART will subscribe to + DPPI channel that task BCSTART will subscribe to 0 7 @@ -5792,7 +4896,7 @@ POSSIBILITY OF SUCH DAMAGE. CHIDX - Channel that task BCSTOP will subscribe to + DPPI channel that task BCSTOP will subscribe to 0 7 @@ -5823,7 +4927,7 @@ POSSIBILITY OF SUCH DAMAGE. CHIDX - Channel that task EDSTART will subscribe to + DPPI channel that task EDSTART will subscribe to 0 7 @@ -5854,7 +4958,7 @@ POSSIBILITY OF SUCH DAMAGE. CHIDX - Channel that task EDSTOP will subscribe to + DPPI channel that task EDSTOP will subscribe to 0 7 @@ -5885,7 +4989,7 @@ POSSIBILITY OF SUCH DAMAGE. CHIDX - Channel that task CCASTART will subscribe to + DPPI channel that task CCASTART will subscribe to 0 7 @@ -5916,7 +5020,7 @@ POSSIBILITY OF SUCH DAMAGE. CHIDX - Channel that task CCASTOP will subscribe to + DPPI channel that task CCASTOP will subscribe to 0 7 @@ -6485,15 +5589,41 @@ POSSIBILITY OF SUCH DAMAGE. + + EVENTS_SYNC + Preamble indicator + 0x168 + read-write + + + EVENTS_SYNC + Preamble indicator + 0 + 0 + + + NotGenerated + Event not generated + 0 + + + Generated + Event generated + 1 + + + + + EVENTS_PHYEND - Generated when last bit is sent on air + Generated when last bit is sent on air, or received from air 0x16C read-write EVENTS_PHYEND - Generated when last bit is sent on air + Generated when last bit is sent on air, or received from air 0 0 @@ -6545,7 +5675,7 @@ POSSIBILITY OF SUCH DAMAGE. CHIDX - Channel that event READY will publish to. + DPPI channel that event READY will publish to. 0 7 @@ -6576,7 +5706,7 @@ POSSIBILITY OF SUCH DAMAGE. CHIDX - Channel that event ADDRESS will publish to. + DPPI channel that event ADDRESS will publish to. 0 7 @@ -6607,7 +5737,7 @@ POSSIBILITY OF SUCH DAMAGE. CHIDX - Channel that event PAYLOAD will publish to. + DPPI channel that event PAYLOAD will publish to. 0 7 @@ -6638,7 +5768,7 @@ POSSIBILITY OF SUCH DAMAGE. CHIDX - Channel that event END will publish to. + DPPI channel that event END will publish to. 0 7 @@ -6669,7 +5799,7 @@ POSSIBILITY OF SUCH DAMAGE. CHIDX - Channel that event DISABLED will publish to. + DPPI channel that event DISABLED will publish to. 0 7 @@ -6700,7 +5830,7 @@ POSSIBILITY OF SUCH DAMAGE. CHIDX - Channel that event DEVMATCH will publish to. + DPPI channel that event DEVMATCH will publish to. 0 7 @@ -6731,7 +5861,7 @@ POSSIBILITY OF SUCH DAMAGE. CHIDX - Channel that event DEVMISS will publish to. + DPPI channel that event DEVMISS will publish to. 0 7 @@ -6762,7 +5892,7 @@ POSSIBILITY OF SUCH DAMAGE. CHIDX - Channel that event RSSIEND will publish to. + DPPI channel that event RSSIEND will publish to. 0 7 @@ -6793,7 +5923,7 @@ POSSIBILITY OF SUCH DAMAGE. CHIDX - Channel that event BCMATCH will publish to. + DPPI channel that event BCMATCH will publish to. 0 7 @@ -6824,7 +5954,7 @@ POSSIBILITY OF SUCH DAMAGE. CHIDX - Channel that event CRCOK will publish to. + DPPI channel that event CRCOK will publish to. 0 7 @@ -6855,7 +5985,7 @@ POSSIBILITY OF SUCH DAMAGE. CHIDX - Channel that event CRCERROR will publish to. + DPPI channel that event CRCERROR will publish to. 0 7 @@ -6886,7 +6016,7 @@ POSSIBILITY OF SUCH DAMAGE. CHIDX - Channel that event FRAMESTART will publish to. + DPPI channel that event FRAMESTART will publish to. 0 7 @@ -6917,7 +6047,7 @@ POSSIBILITY OF SUCH DAMAGE. CHIDX - Channel that event EDEND will publish to. + DPPI channel that event EDEND will publish to. 0 7 @@ -6948,7 +6078,7 @@ POSSIBILITY OF SUCH DAMAGE. CHIDX - Channel that event EDSTOPPED will publish to. + DPPI channel that event EDSTOPPED will publish to. 0 7 @@ -6979,7 +6109,7 @@ POSSIBILITY OF SUCH DAMAGE. CHIDX - Channel that event CCAIDLE will publish to. + DPPI channel that event CCAIDLE will publish to. 0 7 @@ -7010,7 +6140,7 @@ POSSIBILITY OF SUCH DAMAGE. CHIDX - Channel that event CCABUSY will publish to. + DPPI channel that event CCABUSY will publish to. 0 7 @@ -7041,7 +6171,7 @@ POSSIBILITY OF SUCH DAMAGE. CHIDX - Channel that event CCASTOPPED will publish to. + DPPI channel that event CCASTOPPED will publish to. 0 7 @@ -7072,7 +6202,7 @@ POSSIBILITY OF SUCH DAMAGE. CHIDX - Channel that event RATEBOOST will publish to. + DPPI channel that event RATEBOOST will publish to. 0 7 @@ -7103,7 +6233,7 @@ POSSIBILITY OF SUCH DAMAGE. CHIDX - Channel that event TXREADY will publish to. + DPPI channel that event TXREADY will publish to. 0 7 @@ -7134,7 +6264,7 @@ POSSIBILITY OF SUCH DAMAGE. CHIDX - Channel that event RXREADY will publish to. + DPPI channel that event RXREADY will publish to. 0 7 @@ -7165,7 +6295,38 @@ POSSIBILITY OF SUCH DAMAGE. CHIDX - Channel that event MHRMATCH will publish to. + DPPI channel that event MHRMATCH will publish to. + 0 + 7 + + + EN + 31 + 31 + + + Disabled + Disable publishing + 0 + + + Enabled + Enable publishing + 1 + + + + + + + PUBLISH_SYNC + Publish configuration for event SYNC + 0x1E8 + read-write + + + CHIDX + DPPI channel that event SYNC will publish to. 0 7 @@ -7196,7 +6357,7 @@ POSSIBILITY OF SUCH DAMAGE. CHIDX - Channel that event PHYEND will publish to. + DPPI channel that event PHYEND will publish to. 0 7 @@ -7227,7 +6388,7 @@ POSSIBILITY OF SUCH DAMAGE. CHIDX - Channel that event CTEPRESENT will publish to. + DPPI channel that event CTEPRESENT will publish to. 0 7 @@ -8173,6 +7334,33 @@ POSSIBILITY OF SUCH DAMAGE. + + SYNC + Write '1' to enable interrupt for event SYNC + 26 + 26 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Set + Enable + 1 + + + PHYEND Write '1' to enable interrupt for event PHYEND @@ -8802,6 +7990,33 @@ POSSIBILITY OF SUCH DAMAGE. + + SYNC + Write '1' to disable interrupt for event SYNC + 26 + 26 + + read + + Disabled + Read: Disabled + 0 + + + Enabled + Read: Enabled + 1 + + + + write + + Clear + Disable + 1 + + + PHYEND Write '1' to disable interrupt for event PHYEND @@ -10644,7 +9859,7 @@ POSSIBILITY OF SUCH DAMAGE. REPEATPATTERN - Repeat every antenna pattern N times. + Repeat each individual antenna pattern N times sequentially, i.e. P0, P0, P1, P1, P2, P2, P3, P3, etc. 20 23 @@ -10918,7 +10133,7 @@ POSSIBILITY OF SUCH DAMAGE. CHIDX - Channel that task START will subscribe to + DPPI channel that task START will subscribe to 0 7 @@ -10949,7 +10164,7 @@ POSSIBILITY OF SUCH DAMAGE. CHIDX - Channel that task STOP will subscribe to + DPPI channel that task STOP will subscribe to 0 7 @@ -11006,7 +10221,7 @@ POSSIBILITY OF SUCH DAMAGE. CHIDX - Channel that event VALRDY will publish to. + DPPI channel that event VALRDY will publish to. 0 7 @@ -11265,7 +10480,7 @@ POSSIBILITY OF SUCH DAMAGE. CHIDX - Channel that task OUT[n] will subscribe to + DPPI channel that task OUT[n] will subscribe to 0 7 @@ -11298,7 +10513,7 @@ POSSIBILITY OF SUCH DAMAGE. CHIDX - Channel that task SET[n] will subscribe to + DPPI channel that task SET[n] will subscribe to 0 7 @@ -11331,7 +10546,7 @@ POSSIBILITY OF SUCH DAMAGE. CHIDX - Channel that task CLR[n] will subscribe to + DPPI channel that task CLR[n] will subscribe to 0 7 @@ -11418,7 +10633,7 @@ POSSIBILITY OF SUCH DAMAGE. CHIDX - Channel that event IN[n] will publish to. + DPPI channel that event IN[n] will publish to. 0 7 @@ -11449,7 +10664,7 @@ POSSIBILITY OF SUCH DAMAGE. CHIDX - Channel that event PORT will publish to. + DPPI channel that event PORT will publish to. 0 7 @@ -11974,6 +11189,33 @@ POSSIBILITY OF SUCH DAMAGE. + + LATENCY + Latency selection for Event mode (MODE=Event) with rising or falling edge detection on the pin. + 0x504 + read-write + 0x00000001 + + + LATENCY + Latency setting + 0 + 0 + + + LowPower + Low power setting, for signals with minimum hold time tGPIOTE,HOLD,LP; refer to Electrical specification section + 0 + + + LowLatency + Low latency setting, for signals with minimum hold time tGPIOTE,HOLD,LL; refer to Electrical specification section + 1 + + + + + 0x8 0x4 @@ -12136,7 +11378,7 @@ POSSIBILITY OF SUCH DAMAGE. CHIDX - Channel that task START will subscribe to + DPPI channel that task START will subscribe to 0 7 @@ -12167,7 +11409,7 @@ POSSIBILITY OF SUCH DAMAGE. CHIDX - Channel that task STOP will subscribe to + DPPI channel that task STOP will subscribe to 0 7 @@ -12250,7 +11492,7 @@ POSSIBILITY OF SUCH DAMAGE. CHIDX - Channel that event TIMEOUT will publish to. + DPPI channel that event TIMEOUT will publish to. 0 7 @@ -12281,7 +11523,7 @@ POSSIBILITY OF SUCH DAMAGE. CHIDX - Channel that event STOPPED will publish to. + DPPI channel that event STOPPED will publish to. 0 7 @@ -13164,7 +12406,7 @@ POSSIBILITY OF SUCH DAMAGE. CHIDX - Channel that task START will subscribe to + DPPI channel that task START will subscribe to 0 7 @@ -13195,7 +12437,7 @@ POSSIBILITY OF SUCH DAMAGE. CHIDX - Channel that task STOP will subscribe to + DPPI channel that task STOP will subscribe to 0 7 @@ -13226,7 +12468,7 @@ POSSIBILITY OF SUCH DAMAGE. CHIDX - Channel that task COUNT will subscribe to + DPPI channel that task COUNT will subscribe to 0 7 @@ -13257,7 +12499,7 @@ POSSIBILITY OF SUCH DAMAGE. CHIDX - Channel that task CLEAR will subscribe to + DPPI channel that task CLEAR will subscribe to 0 7 @@ -13288,7 +12530,7 @@ POSSIBILITY OF SUCH DAMAGE. CHIDX - Channel that task SHUTDOWN will subscribe to + DPPI channel that task SHUTDOWN will subscribe to 0 7 @@ -13321,7 +12563,7 @@ POSSIBILITY OF SUCH DAMAGE. CHIDX - Channel that task CAPTURE[n] will subscribe to + DPPI channel that task CAPTURE[n] will subscribe to 0 7 @@ -13382,7 +12624,7 @@ POSSIBILITY OF SUCH DAMAGE. CHIDX - Channel that event COMPARE[n] will publish to. + DPPI channel that event COMPARE[n] will publish to. 0 7 @@ -14498,7 +13740,7 @@ POSSIBILITY OF SUCH DAMAGE. CHIDX - Channel that task STARTECB will subscribe to + DPPI channel that task STARTECB will subscribe to 0 7 @@ -14529,7 +13771,7 @@ POSSIBILITY OF SUCH DAMAGE. CHIDX - Channel that task STOPECB will subscribe to + DPPI channel that task STOPECB will subscribe to 0 7 @@ -14612,7 +13854,7 @@ POSSIBILITY OF SUCH DAMAGE. CHIDX - Channel that event ENDECB will publish to. + DPPI channel that event ENDECB will publish to. 0 7 @@ -14643,7 +13885,7 @@ POSSIBILITY OF SUCH DAMAGE. CHIDX - Channel that event ERRORECB will publish to. + DPPI channel that event ERRORECB will publish to. 0 7 @@ -14875,7 +14117,7 @@ POSSIBILITY OF SUCH DAMAGE. CHIDX - Channel that task START will subscribe to + DPPI channel that task START will subscribe to 0 7 @@ -14906,7 +14148,7 @@ POSSIBILITY OF SUCH DAMAGE. CHIDX - Channel that task STOP will subscribe to + DPPI channel that task STOP will subscribe to 0 7 @@ -15015,7 +14257,7 @@ POSSIBILITY OF SUCH DAMAGE. CHIDX - Channel that event END will publish to. + DPPI channel that event END will publish to. 0 7 @@ -15046,7 +14288,7 @@ POSSIBILITY OF SUCH DAMAGE. CHIDX - Channel that event RESOLVED will publish to. + DPPI channel that event RESOLVED will publish to. 0 7 @@ -15077,7 +14319,7 @@ POSSIBILITY OF SUCH DAMAGE. CHIDX - Channel that event NOTRESOLVED will publish to. + DPPI channel that event NOTRESOLVED will publish to. 0 7 @@ -15489,7 +14731,7 @@ POSSIBILITY OF SUCH DAMAGE. CHIDX - Channel that task KSGEN will subscribe to + DPPI channel that task KSGEN will subscribe to 0 7 @@ -15520,7 +14762,7 @@ POSSIBILITY OF SUCH DAMAGE. CHIDX - Channel that task CRYPT will subscribe to + DPPI channel that task CRYPT will subscribe to 0 7 @@ -15551,7 +14793,7 @@ POSSIBILITY OF SUCH DAMAGE. CHIDX - Channel that task STOP will subscribe to + DPPI channel that task STOP will subscribe to 0 7 @@ -15582,7 +14824,7 @@ POSSIBILITY OF SUCH DAMAGE. CHIDX - Channel that task RATEOVERRIDE will subscribe to + DPPI channel that task RATEOVERRIDE will subscribe to 0 7 @@ -15691,7 +14933,7 @@ POSSIBILITY OF SUCH DAMAGE. CHIDX - Channel that event ENDKSGEN will publish to. + DPPI channel that event ENDKSGEN will publish to. 0 7 @@ -15722,7 +14964,7 @@ POSSIBILITY OF SUCH DAMAGE. CHIDX - Channel that event ENDCRYPT will publish to. + DPPI channel that event ENDCRYPT will publish to. 0 7 @@ -15753,7 +14995,7 @@ POSSIBILITY OF SUCH DAMAGE. CHIDX - Channel that event ERROR will publish to. + DPPI channel that event ERROR will publish to. 0 7 @@ -16313,7 +15555,7 @@ POSSIBILITY OF SUCH DAMAGE. CHIDX - Channel that task CHG[n].EN will subscribe to + DPPI channel that task CHG[n].EN will subscribe to 0 7 @@ -16344,7 +15586,7 @@ POSSIBILITY OF SUCH DAMAGE. CHIDX - Channel that task CHG[n].DIS will subscribe to + DPPI channel that task CHG[n].DIS will subscribe to 0 7 @@ -17915,7 +17157,7 @@ POSSIBILITY OF SUCH DAMAGE. CHIDX - Channel that task START will subscribe to + DPPI channel that task START will subscribe to 0 7 @@ -17946,7 +17188,7 @@ POSSIBILITY OF SUCH DAMAGE. CHIDX - Channel that task STOP will subscribe to + DPPI channel that task STOP will subscribe to 0 7 @@ -18003,7 +17245,7 @@ POSSIBILITY OF SUCH DAMAGE. CHIDX - Channel that event DATARDY will publish to. + DPPI channel that event DATARDY will publish to. 0 7 @@ -18502,7 +17744,7 @@ POSSIBILITY OF SUCH DAMAGE. CHIDX - Channel that task START will subscribe to + DPPI channel that task START will subscribe to 0 7 @@ -18533,7 +17775,7 @@ POSSIBILITY OF SUCH DAMAGE. CHIDX - Channel that task STOP will subscribe to + DPPI channel that task STOP will subscribe to 0 7 @@ -18564,7 +17806,7 @@ POSSIBILITY OF SUCH DAMAGE. CHIDX - Channel that task CLEAR will subscribe to + DPPI channel that task CLEAR will subscribe to 0 7 @@ -18595,7 +17837,7 @@ POSSIBILITY OF SUCH DAMAGE. CHIDX - Channel that task TRIGOVRFLW will subscribe to + DPPI channel that task TRIGOVRFLW will subscribe to 0 7 @@ -18628,7 +17870,7 @@ POSSIBILITY OF SUCH DAMAGE. CHIDX - Channel that task CAPTURE[n] will subscribe to + DPPI channel that task CAPTURE[n] will subscribe to 0 7 @@ -18739,7 +17981,7 @@ POSSIBILITY OF SUCH DAMAGE. CHIDX - Channel that event TICK will publish to. + DPPI channel that event TICK will publish to. 0 7 @@ -18770,7 +18012,7 @@ POSSIBILITY OF SUCH DAMAGE. CHIDX - Channel that event OVRFLW will publish to. + DPPI channel that event OVRFLW will publish to. 0 7 @@ -18803,7 +18045,7 @@ POSSIBILITY OF SUCH DAMAGE. CHIDX - Channel that event COMPARE[n] will publish to. + DPPI channel that event COMPARE[n] will publish to. 0 7 @@ -19800,7 +19042,7 @@ POSSIBILITY OF SUCH DAMAGE. CHIDX - Channel that task SEND[n] will subscribe to + DPPI channel that task SEND[n] will subscribe to 0 7 @@ -19861,7 +19103,7 @@ POSSIBILITY OF SUCH DAMAGE. CHIDX - Channel that event RECEIVE[n] will publish to. + DPPI channel that event RECEIVE[n] will publish to. 0 7 @@ -22100,7 +21342,7 @@ POSSIBILITY OF SUCH DAMAGE. CHIDX - Channel that task START will subscribe to + DPPI channel that task START will subscribe to 0 7 @@ -22131,7 +21373,7 @@ POSSIBILITY OF SUCH DAMAGE. CHIDX - Channel that task STOP will subscribe to + DPPI channel that task STOP will subscribe to 0 7 @@ -22162,7 +21404,7 @@ POSSIBILITY OF SUCH DAMAGE. CHIDX - Channel that task SUSPEND will subscribe to + DPPI channel that task SUSPEND will subscribe to 0 7 @@ -22193,7 +21435,7 @@ POSSIBILITY OF SUCH DAMAGE. CHIDX - Channel that task RESUME will subscribe to + DPPI channel that task RESUME will subscribe to 0 7 @@ -22354,7 +21596,7 @@ POSSIBILITY OF SUCH DAMAGE. CHIDX - Channel that event STOPPED will publish to. + DPPI channel that event STOPPED will publish to. 0 7 @@ -22385,7 +21627,7 @@ POSSIBILITY OF SUCH DAMAGE. CHIDX - Channel that event ENDRX will publish to. + DPPI channel that event ENDRX will publish to. 0 7 @@ -22416,7 +21658,7 @@ POSSIBILITY OF SUCH DAMAGE. CHIDX - Channel that event END will publish to. + DPPI channel that event END will publish to. 0 7 @@ -22447,7 +21689,7 @@ POSSIBILITY OF SUCH DAMAGE. CHIDX - Channel that event ENDTX will publish to. + DPPI channel that event ENDTX will publish to. 0 7 @@ -22478,7 +21720,7 @@ POSSIBILITY OF SUCH DAMAGE. CHIDX - Channel that event STARTED will publish to. + DPPI channel that event STARTED will publish to. 0 7 @@ -23524,7 +22766,7 @@ POSSIBILITY OF SUCH DAMAGE. CHIDX - Channel that task ACQUIRE will subscribe to + DPPI channel that task ACQUIRE will subscribe to 0 7 @@ -23555,7 +22797,7 @@ POSSIBILITY OF SUCH DAMAGE. CHIDX - Channel that task RELEASE will subscribe to + DPPI channel that task RELEASE will subscribe to 0 7 @@ -23664,7 +22906,7 @@ POSSIBILITY OF SUCH DAMAGE. CHIDX - Channel that event END will publish to. + DPPI channel that event END will publish to. 0 7 @@ -23695,7 +22937,7 @@ POSSIBILITY OF SUCH DAMAGE. CHIDX - Channel that event ENDRX will publish to. + DPPI channel that event ENDRX will publish to. 0 7 @@ -23726,7 +22968,7 @@ POSSIBILITY OF SUCH DAMAGE. CHIDX - Channel that event ACQUIRED will publish to. + DPPI channel that event ACQUIRED will publish to. 0 7 @@ -24616,7 +23858,7 @@ POSSIBILITY OF SUCH DAMAGE. CHIDX - Channel that task STARTRX will subscribe to + DPPI channel that task STARTRX will subscribe to 0 7 @@ -24647,7 +23889,7 @@ POSSIBILITY OF SUCH DAMAGE. CHIDX - Channel that task STARTTX will subscribe to + DPPI channel that task STARTTX will subscribe to 0 7 @@ -24678,7 +23920,7 @@ POSSIBILITY OF SUCH DAMAGE. CHIDX - Channel that task STOP will subscribe to + DPPI channel that task STOP will subscribe to 0 7 @@ -24709,7 +23951,7 @@ POSSIBILITY OF SUCH DAMAGE. CHIDX - Channel that task SUSPEND will subscribe to + DPPI channel that task SUSPEND will subscribe to 0 7 @@ -24740,7 +23982,7 @@ POSSIBILITY OF SUCH DAMAGE. CHIDX - Channel that task RESUME will subscribe to + DPPI channel that task RESUME will subscribe to 0 7 @@ -24817,13 +24059,13 @@ POSSIBILITY OF SUCH DAMAGE. EVENTS_SUSPENDED - Last byte has been sent out after the SUSPEND task has been issued, TWI traffic is now suspended. + SUSPEND task has been issued, TWI traffic is now suspended. 0x148 read-write EVENTS_SUSPENDED - Last byte has been sent out after the SUSPEND task has been issued, TWI traffic is now suspended. + SUSPEND task has been issued, TWI traffic is now suspended. 0 0 @@ -24953,7 +24195,7 @@ POSSIBILITY OF SUCH DAMAGE. CHIDX - Channel that event STOPPED will publish to. + DPPI channel that event STOPPED will publish to. 0 7 @@ -24984,7 +24226,7 @@ POSSIBILITY OF SUCH DAMAGE. CHIDX - Channel that event ERROR will publish to. + DPPI channel that event ERROR will publish to. 0 7 @@ -25015,7 +24257,7 @@ POSSIBILITY OF SUCH DAMAGE. CHIDX - Channel that event SUSPENDED will publish to. + DPPI channel that event SUSPENDED will publish to. 0 7 @@ -25046,7 +24288,7 @@ POSSIBILITY OF SUCH DAMAGE. CHIDX - Channel that event RXSTARTED will publish to. + DPPI channel that event RXSTARTED will publish to. 0 7 @@ -25077,7 +24319,7 @@ POSSIBILITY OF SUCH DAMAGE. CHIDX - Channel that event TXSTARTED will publish to. + DPPI channel that event TXSTARTED will publish to. 0 7 @@ -25108,7 +24350,7 @@ POSSIBILITY OF SUCH DAMAGE. CHIDX - Channel that event LASTRX will publish to. + DPPI channel that event LASTRX will publish to. 0 7 @@ -25139,7 +24381,7 @@ POSSIBILITY OF SUCH DAMAGE. CHIDX - Channel that event LASTTX will publish to. + DPPI channel that event LASTTX will publish to. 0 7 @@ -26316,7 +25558,7 @@ POSSIBILITY OF SUCH DAMAGE. CHIDX - Channel that task STOP will subscribe to + DPPI channel that task STOP will subscribe to 0 7 @@ -26347,7 +25589,7 @@ POSSIBILITY OF SUCH DAMAGE. CHIDX - Channel that task SUSPEND will subscribe to + DPPI channel that task SUSPEND will subscribe to 0 7 @@ -26378,7 +25620,7 @@ POSSIBILITY OF SUCH DAMAGE. CHIDX - Channel that task RESUME will subscribe to + DPPI channel that task RESUME will subscribe to 0 7 @@ -26409,7 +25651,7 @@ POSSIBILITY OF SUCH DAMAGE. CHIDX - Channel that task PREPARERX will subscribe to + DPPI channel that task PREPARERX will subscribe to 0 7 @@ -26440,7 +25682,7 @@ POSSIBILITY OF SUCH DAMAGE. CHIDX - Channel that task PREPARETX will subscribe to + DPPI channel that task PREPARETX will subscribe to 0 7 @@ -26627,7 +25869,7 @@ POSSIBILITY OF SUCH DAMAGE. CHIDX - Channel that event STOPPED will publish to. + DPPI channel that event STOPPED will publish to. 0 7 @@ -26658,7 +25900,7 @@ POSSIBILITY OF SUCH DAMAGE. CHIDX - Channel that event ERROR will publish to. + DPPI channel that event ERROR will publish to. 0 7 @@ -26689,7 +25931,7 @@ POSSIBILITY OF SUCH DAMAGE. CHIDX - Channel that event RXSTARTED will publish to. + DPPI channel that event RXSTARTED will publish to. 0 7 @@ -26720,7 +25962,7 @@ POSSIBILITY OF SUCH DAMAGE. CHIDX - Channel that event TXSTARTED will publish to. + DPPI channel that event TXSTARTED will publish to. 0 7 @@ -26751,7 +25993,7 @@ POSSIBILITY OF SUCH DAMAGE. CHIDX - Channel that event WRITE will publish to. + DPPI channel that event WRITE will publish to. 0 7 @@ -26782,7 +26024,7 @@ POSSIBILITY OF SUCH DAMAGE. CHIDX - Channel that event READ will publish to. + DPPI channel that event READ will publish to. 0 7 @@ -27853,7 +27095,7 @@ POSSIBILITY OF SUCH DAMAGE. CHIDX - Channel that task STARTRX will subscribe to + DPPI channel that task STARTRX will subscribe to 0 7 @@ -27884,7 +27126,7 @@ POSSIBILITY OF SUCH DAMAGE. CHIDX - Channel that task STOPRX will subscribe to + DPPI channel that task STOPRX will subscribe to 0 7 @@ -27915,7 +27157,7 @@ POSSIBILITY OF SUCH DAMAGE. CHIDX - Channel that task STARTTX will subscribe to + DPPI channel that task STARTTX will subscribe to 0 7 @@ -27946,7 +27188,7 @@ POSSIBILITY OF SUCH DAMAGE. CHIDX - Channel that task STOPTX will subscribe to + DPPI channel that task STOPTX will subscribe to 0 7 @@ -27977,7 +27219,7 @@ POSSIBILITY OF SUCH DAMAGE. CHIDX - Channel that task FLUSHRX will subscribe to + DPPI channel that task FLUSHRX will subscribe to 0 7 @@ -28294,7 +27536,7 @@ POSSIBILITY OF SUCH DAMAGE. CHIDX - Channel that event CTS will publish to. + DPPI channel that event CTS will publish to. 0 7 @@ -28325,7 +27567,7 @@ POSSIBILITY OF SUCH DAMAGE. CHIDX - Channel that event NCTS will publish to. + DPPI channel that event NCTS will publish to. 0 7 @@ -28356,7 +27598,7 @@ POSSIBILITY OF SUCH DAMAGE. CHIDX - Channel that event RXDRDY will publish to. + DPPI channel that event RXDRDY will publish to. 0 7 @@ -28387,7 +27629,7 @@ POSSIBILITY OF SUCH DAMAGE. CHIDX - Channel that event ENDRX will publish to. + DPPI channel that event ENDRX will publish to. 0 7 @@ -28418,7 +27660,7 @@ POSSIBILITY OF SUCH DAMAGE. CHIDX - Channel that event TXDRDY will publish to. + DPPI channel that event TXDRDY will publish to. 0 7 @@ -28449,7 +27691,7 @@ POSSIBILITY OF SUCH DAMAGE. CHIDX - Channel that event ENDTX will publish to. + DPPI channel that event ENDTX will publish to. 0 7 @@ -28480,7 +27722,7 @@ POSSIBILITY OF SUCH DAMAGE. CHIDX - Channel that event ERROR will publish to. + DPPI channel that event ERROR will publish to. 0 7 @@ -28511,7 +27753,7 @@ POSSIBILITY OF SUCH DAMAGE. CHIDX - Channel that event RXTO will publish to. + DPPI channel that event RXTO will publish to. 0 7 @@ -28542,7 +27784,7 @@ POSSIBILITY OF SUCH DAMAGE. CHIDX - Channel that event RXSTARTED will publish to. + DPPI channel that event RXSTARTED will publish to. 0 7 @@ -28573,7 +27815,7 @@ POSSIBILITY OF SUCH DAMAGE. CHIDX - Channel that event TXSTARTED will publish to. + DPPI channel that event TXSTARTED will publish to. 0 7 @@ -28604,7 +27846,7 @@ POSSIBILITY OF SUCH DAMAGE. CHIDX - Channel that event TXSTOPPED will publish to. + DPPI channel that event TXSTOPPED will publish to. 0 7 @@ -30100,7 +29342,7 @@ POSSIBILITY OF SUCH DAMAGE. CHIDX - Channel that task TRIGGER[n] will subscribe to + DPPI channel that task TRIGGER[n] will subscribe to 0 7 @@ -30161,7 +29403,7 @@ POSSIBILITY OF SUCH DAMAGE. CHIDX - Channel that event TRIGGERED[n] will publish to. + DPPI channel that event TRIGGERED[n] will publish to. 0 7 @@ -31835,71 +31077,6 @@ POSSIBILITY OF SUCH DAMAGE. - - CONFIGNS - Unspecified - 0x584 - read-write - - - WEN - Program memory access mode. It is strongly recommended to only activate erase and write modes when they are actively used. Enabling write or erase will invalidate the cache and keep it invalidated. - 0 - 1 - - - Ren - Read only access - 0 - - - Wen - Write enabled - 1 - - - Een - Erase enabled - 2 - - - - - - - WRITEUICRNS - Non-secure APPROTECT enable register - 0x588 - write-only - - - SET - Allow non-secure code to set APPROTECT - 0 - 0 - - - Set - Set value - 1 - - - - - KEY - Key to write in order to validate the write operation - 4 - 31 - - - Keyvalid - Key value - 0xAFBE5A7 - - - - - @@ -38316,31 +37493,11 @@ POSSIBILITY OF SUCH DAMAGE. High drive '0', disconnect '1' (normally used for wired-and connections) 7 - - E0S1 - Extra high drive '0', standard '1' - 9 - - - S0E1 - Standard '0', extra high drive '1' - 10 - E0E1 Extra high drive '0', extra high drive '1' 11 - - D0E1 - Disconnect '0', extra high drive '1' (normally used for wired-or connections) - 13 - - - E0D1 - Extra high drive '0', disconnect '1' (normally used for wired-and connections) - 15 - diff --git a/mdk/nrf5340_network_bitfields.h b/mdk/nrf5340_network_bitfields.h index 59958f6605..212bf59509 100644 --- a/mdk/nrf5340_network_bitfields.h +++ b/mdk/nrf5340_network_bitfields.h @@ -63,7 +63,7 @@ POSSIBILITY OF SUCH DAMAGE. #define AAR_SUBSCRIBE_START_EN_Disabled (0UL) /*!< Disable subscription */ #define AAR_SUBSCRIBE_START_EN_Enabled (1UL) /*!< Enable subscription */ -/* Bits 7..0 : Channel that task START will subscribe to */ +/* Bits 7..0 : DPPI channel that task START will subscribe to */ #define AAR_SUBSCRIBE_START_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ #define AAR_SUBSCRIBE_START_CHIDX_Msk (0xFFUL << AAR_SUBSCRIBE_START_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ @@ -76,7 +76,7 @@ POSSIBILITY OF SUCH DAMAGE. #define AAR_SUBSCRIBE_STOP_EN_Disabled (0UL) /*!< Disable subscription */ #define AAR_SUBSCRIBE_STOP_EN_Enabled (1UL) /*!< Enable subscription */ -/* Bits 7..0 : Channel that task STOP will subscribe to */ +/* Bits 7..0 : DPPI channel that task STOP will subscribe to */ #define AAR_SUBSCRIBE_STOP_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ #define AAR_SUBSCRIBE_STOP_CHIDX_Msk (0xFFUL << AAR_SUBSCRIBE_STOP_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ @@ -116,7 +116,7 @@ POSSIBILITY OF SUCH DAMAGE. #define AAR_PUBLISH_END_EN_Disabled (0UL) /*!< Disable publishing */ #define AAR_PUBLISH_END_EN_Enabled (1UL) /*!< Enable publishing */ -/* Bits 7..0 : Channel that event END will publish to. */ +/* Bits 7..0 : DPPI channel that event END will publish to. */ #define AAR_PUBLISH_END_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ #define AAR_PUBLISH_END_CHIDX_Msk (0xFFUL << AAR_PUBLISH_END_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ @@ -129,7 +129,7 @@ POSSIBILITY OF SUCH DAMAGE. #define AAR_PUBLISH_RESOLVED_EN_Disabled (0UL) /*!< Disable publishing */ #define AAR_PUBLISH_RESOLVED_EN_Enabled (1UL) /*!< Enable publishing */ -/* Bits 7..0 : Channel that event RESOLVED will publish to. */ +/* Bits 7..0 : DPPI channel that event RESOLVED will publish to. */ #define AAR_PUBLISH_RESOLVED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ #define AAR_PUBLISH_RESOLVED_CHIDX_Msk (0xFFUL << AAR_PUBLISH_RESOLVED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ @@ -142,7 +142,7 @@ POSSIBILITY OF SUCH DAMAGE. #define AAR_PUBLISH_NOTRESOLVED_EN_Disabled (0UL) /*!< Disable publishing */ #define AAR_PUBLISH_NOTRESOLVED_EN_Enabled (1UL) /*!< Enable publishing */ -/* Bits 7..0 : Channel that event NOTRESOLVED will publish to. */ +/* Bits 7..0 : DPPI channel that event NOTRESOLVED will publish to. */ #define AAR_PUBLISH_NOTRESOLVED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ #define AAR_PUBLISH_NOTRESOLVED_CHIDX_Msk (0xFFUL << AAR_PUBLISH_NOTRESOLVED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ @@ -329,7 +329,7 @@ POSSIBILITY OF SUCH DAMAGE. #define CCM_SUBSCRIBE_KSGEN_EN_Disabled (0UL) /*!< Disable subscription */ #define CCM_SUBSCRIBE_KSGEN_EN_Enabled (1UL) /*!< Enable subscription */ -/* Bits 7..0 : Channel that task KSGEN will subscribe to */ +/* Bits 7..0 : DPPI channel that task KSGEN will subscribe to */ #define CCM_SUBSCRIBE_KSGEN_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ #define CCM_SUBSCRIBE_KSGEN_CHIDX_Msk (0xFFUL << CCM_SUBSCRIBE_KSGEN_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ @@ -342,7 +342,7 @@ POSSIBILITY OF SUCH DAMAGE. #define CCM_SUBSCRIBE_CRYPT_EN_Disabled (0UL) /*!< Disable subscription */ #define CCM_SUBSCRIBE_CRYPT_EN_Enabled (1UL) /*!< Enable subscription */ -/* Bits 7..0 : Channel that task CRYPT will subscribe to */ +/* Bits 7..0 : DPPI channel that task CRYPT will subscribe to */ #define CCM_SUBSCRIBE_CRYPT_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ #define CCM_SUBSCRIBE_CRYPT_CHIDX_Msk (0xFFUL << CCM_SUBSCRIBE_CRYPT_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ @@ -355,7 +355,7 @@ POSSIBILITY OF SUCH DAMAGE. #define CCM_SUBSCRIBE_STOP_EN_Disabled (0UL) /*!< Disable subscription */ #define CCM_SUBSCRIBE_STOP_EN_Enabled (1UL) /*!< Enable subscription */ -/* Bits 7..0 : Channel that task STOP will subscribe to */ +/* Bits 7..0 : DPPI channel that task STOP will subscribe to */ #define CCM_SUBSCRIBE_STOP_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ #define CCM_SUBSCRIBE_STOP_CHIDX_Msk (0xFFUL << CCM_SUBSCRIBE_STOP_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ @@ -368,7 +368,7 @@ POSSIBILITY OF SUCH DAMAGE. #define CCM_SUBSCRIBE_RATEOVERRIDE_EN_Disabled (0UL) /*!< Disable subscription */ #define CCM_SUBSCRIBE_RATEOVERRIDE_EN_Enabled (1UL) /*!< Enable subscription */ -/* Bits 7..0 : Channel that task RATEOVERRIDE will subscribe to */ +/* Bits 7..0 : DPPI channel that task RATEOVERRIDE will subscribe to */ #define CCM_SUBSCRIBE_RATEOVERRIDE_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ #define CCM_SUBSCRIBE_RATEOVERRIDE_CHIDX_Msk (0xFFUL << CCM_SUBSCRIBE_RATEOVERRIDE_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ @@ -408,7 +408,7 @@ POSSIBILITY OF SUCH DAMAGE. #define CCM_PUBLISH_ENDKSGEN_EN_Disabled (0UL) /*!< Disable publishing */ #define CCM_PUBLISH_ENDKSGEN_EN_Enabled (1UL) /*!< Enable publishing */ -/* Bits 7..0 : Channel that event ENDKSGEN will publish to. */ +/* Bits 7..0 : DPPI channel that event ENDKSGEN will publish to. */ #define CCM_PUBLISH_ENDKSGEN_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ #define CCM_PUBLISH_ENDKSGEN_CHIDX_Msk (0xFFUL << CCM_PUBLISH_ENDKSGEN_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ @@ -421,7 +421,7 @@ POSSIBILITY OF SUCH DAMAGE. #define CCM_PUBLISH_ENDCRYPT_EN_Disabled (0UL) /*!< Disable publishing */ #define CCM_PUBLISH_ENDCRYPT_EN_Enabled (1UL) /*!< Enable publishing */ -/* Bits 7..0 : Channel that event ENDCRYPT will publish to. */ +/* Bits 7..0 : DPPI channel that event ENDCRYPT will publish to. */ #define CCM_PUBLISH_ENDCRYPT_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ #define CCM_PUBLISH_ENDCRYPT_CHIDX_Msk (0xFFUL << CCM_PUBLISH_ENDCRYPT_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ @@ -434,7 +434,7 @@ POSSIBILITY OF SUCH DAMAGE. #define CCM_PUBLISH_ERROR_EN_Disabled (0UL) /*!< Disable publishing */ #define CCM_PUBLISH_ERROR_EN_Enabled (1UL) /*!< Enable publishing */ -/* Bits 7..0 : Channel that event ERROR will publish to. */ +/* Bits 7..0 : DPPI channel that event ERROR will publish to. */ #define CCM_PUBLISH_ERROR_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ #define CCM_PUBLISH_ERROR_CHIDX_Msk (0xFFUL << CCM_PUBLISH_ERROR_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ @@ -634,38 +634,6 @@ POSSIBILITY OF SUCH DAMAGE. #define CLOCK_TASKS_CAL_TASKS_CAL_Msk (0x1UL << CLOCK_TASKS_CAL_TASKS_CAL_Pos) /*!< Bit mask of TASKS_CAL field. */ #define CLOCK_TASKS_CAL_TASKS_CAL_Trigger (1UL) /*!< Trigger task */ -/* Register: CLOCK_TASKS_HFCLKAUDIOSTART */ -/* Description: Start HFCLKAUDIO source */ - -/* Bit 0 : Start HFCLKAUDIO source */ -#define CLOCK_TASKS_HFCLKAUDIOSTART_TASKS_HFCLKAUDIOSTART_Pos (0UL) /*!< Position of TASKS_HFCLKAUDIOSTART field. */ -#define CLOCK_TASKS_HFCLKAUDIOSTART_TASKS_HFCLKAUDIOSTART_Msk (0x1UL << CLOCK_TASKS_HFCLKAUDIOSTART_TASKS_HFCLKAUDIOSTART_Pos) /*!< Bit mask of TASKS_HFCLKAUDIOSTART field. */ -#define CLOCK_TASKS_HFCLKAUDIOSTART_TASKS_HFCLKAUDIOSTART_Trigger (1UL) /*!< Trigger task */ - -/* Register: CLOCK_TASKS_HFCLKAUDIOSTOP */ -/* Description: Stop HFCLKAUDIO source */ - -/* Bit 0 : Stop HFCLKAUDIO source */ -#define CLOCK_TASKS_HFCLKAUDIOSTOP_TASKS_HFCLKAUDIOSTOP_Pos (0UL) /*!< Position of TASKS_HFCLKAUDIOSTOP field. */ -#define CLOCK_TASKS_HFCLKAUDIOSTOP_TASKS_HFCLKAUDIOSTOP_Msk (0x1UL << CLOCK_TASKS_HFCLKAUDIOSTOP_TASKS_HFCLKAUDIOSTOP_Pos) /*!< Bit mask of TASKS_HFCLKAUDIOSTOP field. */ -#define CLOCK_TASKS_HFCLKAUDIOSTOP_TASKS_HFCLKAUDIOSTOP_Trigger (1UL) /*!< Trigger task */ - -/* Register: CLOCK_TASKS_HFCLK192MSTART */ -/* Description: Start HFCLK192M source as selected in HFCLK192MSRC */ - -/* Bit 0 : Start HFCLK192M source as selected in HFCLK192MSRC */ -#define CLOCK_TASKS_HFCLK192MSTART_TASKS_HFCLK192MSTART_Pos (0UL) /*!< Position of TASKS_HFCLK192MSTART field. */ -#define CLOCK_TASKS_HFCLK192MSTART_TASKS_HFCLK192MSTART_Msk (0x1UL << CLOCK_TASKS_HFCLK192MSTART_TASKS_HFCLK192MSTART_Pos) /*!< Bit mask of TASKS_HFCLK192MSTART field. */ -#define CLOCK_TASKS_HFCLK192MSTART_TASKS_HFCLK192MSTART_Trigger (1UL) /*!< Trigger task */ - -/* Register: CLOCK_TASKS_HFCLK192MSTOP */ -/* Description: Stop HFCLK192M source */ - -/* Bit 0 : Stop HFCLK192M source */ -#define CLOCK_TASKS_HFCLK192MSTOP_TASKS_HFCLK192MSTOP_Pos (0UL) /*!< Position of TASKS_HFCLK192MSTOP field. */ -#define CLOCK_TASKS_HFCLK192MSTOP_TASKS_HFCLK192MSTOP_Msk (0x1UL << CLOCK_TASKS_HFCLK192MSTOP_TASKS_HFCLK192MSTOP_Pos) /*!< Bit mask of TASKS_HFCLK192MSTOP field. */ -#define CLOCK_TASKS_HFCLK192MSTOP_TASKS_HFCLK192MSTOP_Trigger (1UL) /*!< Trigger task */ - /* Register: CLOCK_SUBSCRIBE_HFCLKSTART */ /* Description: Subscribe configuration for task HFCLKSTART */ @@ -675,7 +643,7 @@ POSSIBILITY OF SUCH DAMAGE. #define CLOCK_SUBSCRIBE_HFCLKSTART_EN_Disabled (0UL) /*!< Disable subscription */ #define CLOCK_SUBSCRIBE_HFCLKSTART_EN_Enabled (1UL) /*!< Enable subscription */ -/* Bits 7..0 : Channel that task HFCLKSTART will subscribe to */ +/* Bits 7..0 : DPPI channel that task HFCLKSTART will subscribe to */ #define CLOCK_SUBSCRIBE_HFCLKSTART_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ #define CLOCK_SUBSCRIBE_HFCLKSTART_CHIDX_Msk (0xFFUL << CLOCK_SUBSCRIBE_HFCLKSTART_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ @@ -688,7 +656,7 @@ POSSIBILITY OF SUCH DAMAGE. #define CLOCK_SUBSCRIBE_HFCLKSTOP_EN_Disabled (0UL) /*!< Disable subscription */ #define CLOCK_SUBSCRIBE_HFCLKSTOP_EN_Enabled (1UL) /*!< Enable subscription */ -/* Bits 7..0 : Channel that task HFCLKSTOP will subscribe to */ +/* Bits 7..0 : DPPI channel that task HFCLKSTOP will subscribe to */ #define CLOCK_SUBSCRIBE_HFCLKSTOP_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ #define CLOCK_SUBSCRIBE_HFCLKSTOP_CHIDX_Msk (0xFFUL << CLOCK_SUBSCRIBE_HFCLKSTOP_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ @@ -701,7 +669,7 @@ POSSIBILITY OF SUCH DAMAGE. #define CLOCK_SUBSCRIBE_LFCLKSTART_EN_Disabled (0UL) /*!< Disable subscription */ #define CLOCK_SUBSCRIBE_LFCLKSTART_EN_Enabled (1UL) /*!< Enable subscription */ -/* Bits 7..0 : Channel that task LFCLKSTART will subscribe to */ +/* Bits 7..0 : DPPI channel that task LFCLKSTART will subscribe to */ #define CLOCK_SUBSCRIBE_LFCLKSTART_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ #define CLOCK_SUBSCRIBE_LFCLKSTART_CHIDX_Msk (0xFFUL << CLOCK_SUBSCRIBE_LFCLKSTART_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ @@ -714,7 +682,7 @@ POSSIBILITY OF SUCH DAMAGE. #define CLOCK_SUBSCRIBE_LFCLKSTOP_EN_Disabled (0UL) /*!< Disable subscription */ #define CLOCK_SUBSCRIBE_LFCLKSTOP_EN_Enabled (1UL) /*!< Enable subscription */ -/* Bits 7..0 : Channel that task LFCLKSTOP will subscribe to */ +/* Bits 7..0 : DPPI channel that task LFCLKSTOP will subscribe to */ #define CLOCK_SUBSCRIBE_LFCLKSTOP_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ #define CLOCK_SUBSCRIBE_LFCLKSTOP_CHIDX_Msk (0xFFUL << CLOCK_SUBSCRIBE_LFCLKSTOP_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ @@ -727,62 +695,10 @@ POSSIBILITY OF SUCH DAMAGE. #define CLOCK_SUBSCRIBE_CAL_EN_Disabled (0UL) /*!< Disable subscription */ #define CLOCK_SUBSCRIBE_CAL_EN_Enabled (1UL) /*!< Enable subscription */ -/* Bits 7..0 : Channel that task CAL will subscribe to */ +/* Bits 7..0 : DPPI channel that task CAL will subscribe to */ #define CLOCK_SUBSCRIBE_CAL_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ #define CLOCK_SUBSCRIBE_CAL_CHIDX_Msk (0xFFUL << CLOCK_SUBSCRIBE_CAL_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ -/* Register: CLOCK_SUBSCRIBE_HFCLKAUDIOSTART */ -/* Description: Subscribe configuration for task HFCLKAUDIOSTART */ - -/* Bit 31 : */ -#define CLOCK_SUBSCRIBE_HFCLKAUDIOSTART_EN_Pos (31UL) /*!< Position of EN field. */ -#define CLOCK_SUBSCRIBE_HFCLKAUDIOSTART_EN_Msk (0x1UL << CLOCK_SUBSCRIBE_HFCLKAUDIOSTART_EN_Pos) /*!< Bit mask of EN field. */ -#define CLOCK_SUBSCRIBE_HFCLKAUDIOSTART_EN_Disabled (0UL) /*!< Disable subscription */ -#define CLOCK_SUBSCRIBE_HFCLKAUDIOSTART_EN_Enabled (1UL) /*!< Enable subscription */ - -/* Bits 7..0 : Channel that task HFCLKAUDIOSTART will subscribe to */ -#define CLOCK_SUBSCRIBE_HFCLKAUDIOSTART_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ -#define CLOCK_SUBSCRIBE_HFCLKAUDIOSTART_CHIDX_Msk (0xFFUL << CLOCK_SUBSCRIBE_HFCLKAUDIOSTART_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ - -/* Register: CLOCK_SUBSCRIBE_HFCLKAUDIOSTOP */ -/* Description: Subscribe configuration for task HFCLKAUDIOSTOP */ - -/* Bit 31 : */ -#define CLOCK_SUBSCRIBE_HFCLKAUDIOSTOP_EN_Pos (31UL) /*!< Position of EN field. */ -#define CLOCK_SUBSCRIBE_HFCLKAUDIOSTOP_EN_Msk (0x1UL << CLOCK_SUBSCRIBE_HFCLKAUDIOSTOP_EN_Pos) /*!< Bit mask of EN field. */ -#define CLOCK_SUBSCRIBE_HFCLKAUDIOSTOP_EN_Disabled (0UL) /*!< Disable subscription */ -#define CLOCK_SUBSCRIBE_HFCLKAUDIOSTOP_EN_Enabled (1UL) /*!< Enable subscription */ - -/* Bits 7..0 : Channel that task HFCLKAUDIOSTOP will subscribe to */ -#define CLOCK_SUBSCRIBE_HFCLKAUDIOSTOP_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ -#define CLOCK_SUBSCRIBE_HFCLKAUDIOSTOP_CHIDX_Msk (0xFFUL << CLOCK_SUBSCRIBE_HFCLKAUDIOSTOP_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ - -/* Register: CLOCK_SUBSCRIBE_HFCLK192MSTART */ -/* Description: Subscribe configuration for task HFCLK192MSTART */ - -/* Bit 31 : */ -#define CLOCK_SUBSCRIBE_HFCLK192MSTART_EN_Pos (31UL) /*!< Position of EN field. */ -#define CLOCK_SUBSCRIBE_HFCLK192MSTART_EN_Msk (0x1UL << CLOCK_SUBSCRIBE_HFCLK192MSTART_EN_Pos) /*!< Bit mask of EN field. */ -#define CLOCK_SUBSCRIBE_HFCLK192MSTART_EN_Disabled (0UL) /*!< Disable subscription */ -#define CLOCK_SUBSCRIBE_HFCLK192MSTART_EN_Enabled (1UL) /*!< Enable subscription */ - -/* Bits 7..0 : Channel that task HFCLK192MSTART will subscribe to */ -#define CLOCK_SUBSCRIBE_HFCLK192MSTART_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ -#define CLOCK_SUBSCRIBE_HFCLK192MSTART_CHIDX_Msk (0xFFUL << CLOCK_SUBSCRIBE_HFCLK192MSTART_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ - -/* Register: CLOCK_SUBSCRIBE_HFCLK192MSTOP */ -/* Description: Subscribe configuration for task HFCLK192MSTOP */ - -/* Bit 31 : */ -#define CLOCK_SUBSCRIBE_HFCLK192MSTOP_EN_Pos (31UL) /*!< Position of EN field. */ -#define CLOCK_SUBSCRIBE_HFCLK192MSTOP_EN_Msk (0x1UL << CLOCK_SUBSCRIBE_HFCLK192MSTOP_EN_Pos) /*!< Bit mask of EN field. */ -#define CLOCK_SUBSCRIBE_HFCLK192MSTOP_EN_Disabled (0UL) /*!< Disable subscription */ -#define CLOCK_SUBSCRIBE_HFCLK192MSTOP_EN_Enabled (1UL) /*!< Enable subscription */ - -/* Bits 7..0 : Channel that task HFCLK192MSTOP will subscribe to */ -#define CLOCK_SUBSCRIBE_HFCLK192MSTOP_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ -#define CLOCK_SUBSCRIBE_HFCLK192MSTOP_CHIDX_Msk (0xFFUL << CLOCK_SUBSCRIBE_HFCLK192MSTOP_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ - /* Register: CLOCK_EVENTS_HFCLKSTARTED */ /* Description: HFCLK128M/HFCLK64M source started */ @@ -810,24 +726,6 @@ POSSIBILITY OF SUCH DAMAGE. #define CLOCK_EVENTS_DONE_EVENTS_DONE_NotGenerated (0UL) /*!< Event not generated */ #define CLOCK_EVENTS_DONE_EVENTS_DONE_Generated (1UL) /*!< Event generated */ -/* Register: CLOCK_EVENTS_HFCLKAUDIOSTARTED */ -/* Description: HFCLKAUDIO source started */ - -/* Bit 0 : HFCLKAUDIO source started */ -#define CLOCK_EVENTS_HFCLKAUDIOSTARTED_EVENTS_HFCLKAUDIOSTARTED_Pos (0UL) /*!< Position of EVENTS_HFCLKAUDIOSTARTED field. */ -#define CLOCK_EVENTS_HFCLKAUDIOSTARTED_EVENTS_HFCLKAUDIOSTARTED_Msk (0x1UL << CLOCK_EVENTS_HFCLKAUDIOSTARTED_EVENTS_HFCLKAUDIOSTARTED_Pos) /*!< Bit mask of EVENTS_HFCLKAUDIOSTARTED field. */ -#define CLOCK_EVENTS_HFCLKAUDIOSTARTED_EVENTS_HFCLKAUDIOSTARTED_NotGenerated (0UL) /*!< Event not generated */ -#define CLOCK_EVENTS_HFCLKAUDIOSTARTED_EVENTS_HFCLKAUDIOSTARTED_Generated (1UL) /*!< Event generated */ - -/* Register: CLOCK_EVENTS_HFCLK192MSTARTED */ -/* Description: HFCLK192M source started */ - -/* Bit 0 : HFCLK192M source started */ -#define CLOCK_EVENTS_HFCLK192MSTARTED_EVENTS_HFCLK192MSTARTED_Pos (0UL) /*!< Position of EVENTS_HFCLK192MSTARTED field. */ -#define CLOCK_EVENTS_HFCLK192MSTARTED_EVENTS_HFCLK192MSTARTED_Msk (0x1UL << CLOCK_EVENTS_HFCLK192MSTARTED_EVENTS_HFCLK192MSTARTED_Pos) /*!< Bit mask of EVENTS_HFCLK192MSTARTED field. */ -#define CLOCK_EVENTS_HFCLK192MSTARTED_EVENTS_HFCLK192MSTARTED_NotGenerated (0UL) /*!< Event not generated */ -#define CLOCK_EVENTS_HFCLK192MSTARTED_EVENTS_HFCLK192MSTARTED_Generated (1UL) /*!< Event generated */ - /* Register: CLOCK_PUBLISH_HFCLKSTARTED */ /* Description: Publish configuration for event HFCLKSTARTED */ @@ -837,7 +735,7 @@ POSSIBILITY OF SUCH DAMAGE. #define CLOCK_PUBLISH_HFCLKSTARTED_EN_Disabled (0UL) /*!< Disable publishing */ #define CLOCK_PUBLISH_HFCLKSTARTED_EN_Enabled (1UL) /*!< Enable publishing */ -/* Bits 7..0 : Channel that event HFCLKSTARTED will publish to. */ +/* Bits 7..0 : DPPI channel that event HFCLKSTARTED will publish to. */ #define CLOCK_PUBLISH_HFCLKSTARTED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ #define CLOCK_PUBLISH_HFCLKSTARTED_CHIDX_Msk (0xFFUL << CLOCK_PUBLISH_HFCLKSTARTED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ @@ -850,7 +748,7 @@ POSSIBILITY OF SUCH DAMAGE. #define CLOCK_PUBLISH_LFCLKSTARTED_EN_Disabled (0UL) /*!< Disable publishing */ #define CLOCK_PUBLISH_LFCLKSTARTED_EN_Enabled (1UL) /*!< Enable publishing */ -/* Bits 7..0 : Channel that event LFCLKSTARTED will publish to. */ +/* Bits 7..0 : DPPI channel that event LFCLKSTARTED will publish to. */ #define CLOCK_PUBLISH_LFCLKSTARTED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ #define CLOCK_PUBLISH_LFCLKSTARTED_CHIDX_Msk (0xFFUL << CLOCK_PUBLISH_LFCLKSTARTED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ @@ -863,51 +761,13 @@ POSSIBILITY OF SUCH DAMAGE. #define CLOCK_PUBLISH_DONE_EN_Disabled (0UL) /*!< Disable publishing */ #define CLOCK_PUBLISH_DONE_EN_Enabled (1UL) /*!< Enable publishing */ -/* Bits 7..0 : Channel that event DONE will publish to. */ +/* Bits 7..0 : DPPI channel that event DONE will publish to. */ #define CLOCK_PUBLISH_DONE_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ #define CLOCK_PUBLISH_DONE_CHIDX_Msk (0xFFUL << CLOCK_PUBLISH_DONE_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ -/* Register: CLOCK_PUBLISH_HFCLKAUDIOSTARTED */ -/* Description: Publish configuration for event HFCLKAUDIOSTARTED */ - -/* Bit 31 : */ -#define CLOCK_PUBLISH_HFCLKAUDIOSTARTED_EN_Pos (31UL) /*!< Position of EN field. */ -#define CLOCK_PUBLISH_HFCLKAUDIOSTARTED_EN_Msk (0x1UL << CLOCK_PUBLISH_HFCLKAUDIOSTARTED_EN_Pos) /*!< Bit mask of EN field. */ -#define CLOCK_PUBLISH_HFCLKAUDIOSTARTED_EN_Disabled (0UL) /*!< Disable publishing */ -#define CLOCK_PUBLISH_HFCLKAUDIOSTARTED_EN_Enabled (1UL) /*!< Enable publishing */ - -/* Bits 7..0 : Channel that event HFCLKAUDIOSTARTED will publish to. */ -#define CLOCK_PUBLISH_HFCLKAUDIOSTARTED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ -#define CLOCK_PUBLISH_HFCLKAUDIOSTARTED_CHIDX_Msk (0xFFUL << CLOCK_PUBLISH_HFCLKAUDIOSTARTED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ - -/* Register: CLOCK_PUBLISH_HFCLK192MSTARTED */ -/* Description: Publish configuration for event HFCLK192MSTARTED */ - -/* Bit 31 : */ -#define CLOCK_PUBLISH_HFCLK192MSTARTED_EN_Pos (31UL) /*!< Position of EN field. */ -#define CLOCK_PUBLISH_HFCLK192MSTARTED_EN_Msk (0x1UL << CLOCK_PUBLISH_HFCLK192MSTARTED_EN_Pos) /*!< Bit mask of EN field. */ -#define CLOCK_PUBLISH_HFCLK192MSTARTED_EN_Disabled (0UL) /*!< Disable publishing */ -#define CLOCK_PUBLISH_HFCLK192MSTARTED_EN_Enabled (1UL) /*!< Enable publishing */ - -/* Bits 7..0 : Channel that event HFCLK192MSTARTED will publish to. */ -#define CLOCK_PUBLISH_HFCLK192MSTARTED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ -#define CLOCK_PUBLISH_HFCLK192MSTARTED_CHIDX_Msk (0xFFUL << CLOCK_PUBLISH_HFCLK192MSTARTED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ - /* Register: CLOCK_INTEN */ /* Description: Enable or disable interrupt */ -/* Bit 9 : Enable or disable interrupt for event HFCLK192MSTARTED */ -#define CLOCK_INTEN_HFCLK192MSTARTED_Pos (9UL) /*!< Position of HFCLK192MSTARTED field. */ -#define CLOCK_INTEN_HFCLK192MSTARTED_Msk (0x1UL << CLOCK_INTEN_HFCLK192MSTARTED_Pos) /*!< Bit mask of HFCLK192MSTARTED field. */ -#define CLOCK_INTEN_HFCLK192MSTARTED_Disabled (0UL) /*!< Disable */ -#define CLOCK_INTEN_HFCLK192MSTARTED_Enabled (1UL) /*!< Enable */ - -/* Bit 8 : Enable or disable interrupt for event HFCLKAUDIOSTARTED */ -#define CLOCK_INTEN_HFCLKAUDIOSTARTED_Pos (8UL) /*!< Position of HFCLKAUDIOSTARTED field. */ -#define CLOCK_INTEN_HFCLKAUDIOSTARTED_Msk (0x1UL << CLOCK_INTEN_HFCLKAUDIOSTARTED_Pos) /*!< Bit mask of HFCLKAUDIOSTARTED field. */ -#define CLOCK_INTEN_HFCLKAUDIOSTARTED_Disabled (0UL) /*!< Disable */ -#define CLOCK_INTEN_HFCLKAUDIOSTARTED_Enabled (1UL) /*!< Enable */ - /* Bit 7 : Enable or disable interrupt for event DONE */ #define CLOCK_INTEN_DONE_Pos (7UL) /*!< Position of DONE field. */ #define CLOCK_INTEN_DONE_Msk (0x1UL << CLOCK_INTEN_DONE_Pos) /*!< Bit mask of DONE field. */ @@ -929,20 +789,6 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: CLOCK_INTENSET */ /* Description: Enable interrupt */ -/* Bit 9 : Write '1' to enable interrupt for event HFCLK192MSTARTED */ -#define CLOCK_INTENSET_HFCLK192MSTARTED_Pos (9UL) /*!< Position of HFCLK192MSTARTED field. */ -#define CLOCK_INTENSET_HFCLK192MSTARTED_Msk (0x1UL << CLOCK_INTENSET_HFCLK192MSTARTED_Pos) /*!< Bit mask of HFCLK192MSTARTED field. */ -#define CLOCK_INTENSET_HFCLK192MSTARTED_Disabled (0UL) /*!< Read: Disabled */ -#define CLOCK_INTENSET_HFCLK192MSTARTED_Enabled (1UL) /*!< Read: Enabled */ -#define CLOCK_INTENSET_HFCLK192MSTARTED_Set (1UL) /*!< Enable */ - -/* Bit 8 : Write '1' to enable interrupt for event HFCLKAUDIOSTARTED */ -#define CLOCK_INTENSET_HFCLKAUDIOSTARTED_Pos (8UL) /*!< Position of HFCLKAUDIOSTARTED field. */ -#define CLOCK_INTENSET_HFCLKAUDIOSTARTED_Msk (0x1UL << CLOCK_INTENSET_HFCLKAUDIOSTARTED_Pos) /*!< Bit mask of HFCLKAUDIOSTARTED field. */ -#define CLOCK_INTENSET_HFCLKAUDIOSTARTED_Disabled (0UL) /*!< Read: Disabled */ -#define CLOCK_INTENSET_HFCLKAUDIOSTARTED_Enabled (1UL) /*!< Read: Enabled */ -#define CLOCK_INTENSET_HFCLKAUDIOSTARTED_Set (1UL) /*!< Enable */ - /* Bit 7 : Write '1' to enable interrupt for event DONE */ #define CLOCK_INTENSET_DONE_Pos (7UL) /*!< Position of DONE field. */ #define CLOCK_INTENSET_DONE_Msk (0x1UL << CLOCK_INTENSET_DONE_Pos) /*!< Bit mask of DONE field. */ @@ -967,20 +813,6 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: CLOCK_INTENCLR */ /* Description: Disable interrupt */ -/* Bit 9 : Write '1' to disable interrupt for event HFCLK192MSTARTED */ -#define CLOCK_INTENCLR_HFCLK192MSTARTED_Pos (9UL) /*!< Position of HFCLK192MSTARTED field. */ -#define CLOCK_INTENCLR_HFCLK192MSTARTED_Msk (0x1UL << CLOCK_INTENCLR_HFCLK192MSTARTED_Pos) /*!< Bit mask of HFCLK192MSTARTED field. */ -#define CLOCK_INTENCLR_HFCLK192MSTARTED_Disabled (0UL) /*!< Read: Disabled */ -#define CLOCK_INTENCLR_HFCLK192MSTARTED_Enabled (1UL) /*!< Read: Enabled */ -#define CLOCK_INTENCLR_HFCLK192MSTARTED_Clear (1UL) /*!< Disable */ - -/* Bit 8 : Write '1' to disable interrupt for event HFCLKAUDIOSTARTED */ -#define CLOCK_INTENCLR_HFCLKAUDIOSTARTED_Pos (8UL) /*!< Position of HFCLKAUDIOSTARTED field. */ -#define CLOCK_INTENCLR_HFCLKAUDIOSTARTED_Msk (0x1UL << CLOCK_INTENCLR_HFCLKAUDIOSTARTED_Pos) /*!< Bit mask of HFCLKAUDIOSTARTED field. */ -#define CLOCK_INTENCLR_HFCLKAUDIOSTARTED_Disabled (0UL) /*!< Read: Disabled */ -#define CLOCK_INTENCLR_HFCLKAUDIOSTARTED_Enabled (1UL) /*!< Read: Enabled */ -#define CLOCK_INTENCLR_HFCLKAUDIOSTARTED_Clear (1UL) /*!< Disable */ - /* Bit 7 : Write '1' to disable interrupt for event DONE */ #define CLOCK_INTENCLR_DONE_Pos (7UL) /*!< Position of DONE field. */ #define CLOCK_INTENCLR_DONE_Msk (0x1UL << CLOCK_INTENCLR_DONE_Pos) /*!< Bit mask of DONE field. */ @@ -1005,18 +837,6 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: CLOCK_INTPEND */ /* Description: Pending interrupts */ -/* Bit 9 : Read pending status of interrupt for event HFCLK192MSTARTED */ -#define CLOCK_INTPEND_HFCLK192MSTARTED_Pos (9UL) /*!< Position of HFCLK192MSTARTED field. */ -#define CLOCK_INTPEND_HFCLK192MSTARTED_Msk (0x1UL << CLOCK_INTPEND_HFCLK192MSTARTED_Pos) /*!< Bit mask of HFCLK192MSTARTED field. */ -#define CLOCK_INTPEND_HFCLK192MSTARTED_NotPending (0UL) /*!< Read: Not pending */ -#define CLOCK_INTPEND_HFCLK192MSTARTED_Pending (1UL) /*!< Read: Pending */ - -/* Bit 8 : Read pending status of interrupt for event HFCLKAUDIOSTARTED */ -#define CLOCK_INTPEND_HFCLKAUDIOSTARTED_Pos (8UL) /*!< Position of HFCLKAUDIOSTARTED field. */ -#define CLOCK_INTPEND_HFCLKAUDIOSTARTED_Msk (0x1UL << CLOCK_INTPEND_HFCLKAUDIOSTARTED_Pos) /*!< Bit mask of HFCLKAUDIOSTARTED field. */ -#define CLOCK_INTPEND_HFCLKAUDIOSTARTED_NotPending (0UL) /*!< Read: Not pending */ -#define CLOCK_INTPEND_HFCLKAUDIOSTARTED_Pending (1UL) /*!< Read: Pending */ - /* Bit 7 : Read pending status of interrupt for event DONE */ #define CLOCK_INTPEND_DONE_Pos (7UL) /*!< Position of DONE field. */ #define CLOCK_INTPEND_DONE_Msk (0x1UL << CLOCK_INTPEND_DONE_Pos) /*!< Bit mask of DONE field. */ @@ -1045,7 +865,7 @@ POSSIBILITY OF SUCH DAMAGE. #define CLOCK_HFCLKRUN_STATUS_Triggered (1UL) /*!< Task triggered */ /* Register: CLOCK_HFCLKSTAT */ -/* Description: Status indicating which HFCLK128M/HFCLK64M source is running Note: Value of this register in any CLOCK instance reflects status only due to configurations/actions in that CLOCK instance. */ +/* Description: Status indicating which HFCLK128M/HFCLK64M source is running This register value in any CLOCK instance reflects status only due to configurations/actions in that CLOCK instance. */ /* Bit 16 : HFCLK state */ #define CLOCK_HFCLKSTAT_STATE_Pos (16UL) /*!< Position of STATE field. */ @@ -1075,7 +895,7 @@ POSSIBILITY OF SUCH DAMAGE. #define CLOCK_LFCLKRUN_STATUS_Triggered (1UL) /*!< Task triggered */ /* Register: CLOCK_LFCLKSTAT */ -/* Description: Status indicating which LFCLK source is running Note: Value of this register in any CLOCK instance reflects status only due to configurations/actions in that CLOCK instance. */ +/* Description: Status indicating which LFCLK source is running This register value in any CLOCK instance reflects status only due to configurations/actions in that CLOCK instance. */ /* Bit 16 : LFCLK state */ #define CLOCK_LFCLKSTAT_STATE_Pos (16UL) /*!< Position of STATE field. */ @@ -1108,60 +928,6 @@ POSSIBILITY OF SUCH DAMAGE. #define CLOCK_LFCLKSRCCOPY_SRC_LFXO (2UL) /*!< 32.768 kHz crystal oscillator */ #define CLOCK_LFCLKSRCCOPY_SRC_LFSYNT (3UL) /*!< 32.768 kHz synthesized from HFCLK */ -/* Register: CLOCK_HFCLKAUDIORUN */ -/* Description: Status indicating that HFCLKAUDIOSTART task has been triggered */ - -/* Bit 0 : HFCLKAUDIOSTART task triggered or not */ -#define CLOCK_HFCLKAUDIORUN_STATUS_Pos (0UL) /*!< Position of STATUS field. */ -#define CLOCK_HFCLKAUDIORUN_STATUS_Msk (0x1UL << CLOCK_HFCLKAUDIORUN_STATUS_Pos) /*!< Bit mask of STATUS field. */ -#define CLOCK_HFCLKAUDIORUN_STATUS_NotTriggered (0UL) /*!< Task not triggered */ -#define CLOCK_HFCLKAUDIORUN_STATUS_Triggered (1UL) /*!< Task triggered */ - -/* Register: CLOCK_HFCLKAUDIOSTAT */ -/* Description: Status indicating which HFCLKAUDIO source is running */ - -/* Bit 16 : HFCLKAUDIO state */ -#define CLOCK_HFCLKAUDIOSTAT_STATE_Pos (16UL) /*!< Position of STATE field. */ -#define CLOCK_HFCLKAUDIOSTAT_STATE_Msk (0x1UL << CLOCK_HFCLKAUDIOSTAT_STATE_Pos) /*!< Bit mask of STATE field. */ -#define CLOCK_HFCLKAUDIOSTAT_STATE_NotRunning (0UL) /*!< HFCLKAUDIO not running */ -#define CLOCK_HFCLKAUDIOSTAT_STATE_Running (1UL) /*!< HFCLKAUDIO running */ - -/* Bit 4 : ALWAYSRUN activated */ -#define CLOCK_HFCLKAUDIOSTAT_ALWAYSRUNNING_Pos (4UL) /*!< Position of ALWAYSRUNNING field. */ -#define CLOCK_HFCLKAUDIOSTAT_ALWAYSRUNNING_Msk (0x1UL << CLOCK_HFCLKAUDIOSTAT_ALWAYSRUNNING_Pos) /*!< Bit mask of ALWAYSRUNNING field. */ -#define CLOCK_HFCLKAUDIOSTAT_ALWAYSRUNNING_NotRunning (0UL) /*!< Automatic clock control enabled */ -#define CLOCK_HFCLKAUDIOSTAT_ALWAYSRUNNING_Running (1UL) /*!< Oscillator is always running */ - -/* Register: CLOCK_HFCLK192MRUN */ -/* Description: Status indicating that HFCLK192MSTART task has been triggered */ - -/* Bit 0 : HFCLK192MSTART task triggered or not */ -#define CLOCK_HFCLK192MRUN_STATUS_Pos (0UL) /*!< Position of STATUS field. */ -#define CLOCK_HFCLK192MRUN_STATUS_Msk (0x1UL << CLOCK_HFCLK192MRUN_STATUS_Pos) /*!< Bit mask of STATUS field. */ -#define CLOCK_HFCLK192MRUN_STATUS_NotTriggered (0UL) /*!< Task not triggered */ -#define CLOCK_HFCLK192MRUN_STATUS_Triggered (1UL) /*!< Task triggered */ - -/* Register: CLOCK_HFCLK192MSTAT */ -/* Description: Status indicating which HFCLK192M source is running */ - -/* Bit 16 : HFCLK192M state */ -#define CLOCK_HFCLK192MSTAT_STATE_Pos (16UL) /*!< Position of STATE field. */ -#define CLOCK_HFCLK192MSTAT_STATE_Msk (0x1UL << CLOCK_HFCLK192MSTAT_STATE_Pos) /*!< Bit mask of STATE field. */ -#define CLOCK_HFCLK192MSTAT_STATE_NotRunning (0UL) /*!< HFCLK192M not running */ -#define CLOCK_HFCLK192MSTAT_STATE_Running (1UL) /*!< HFCLK192M running */ - -/* Bit 4 : ALWAYSRUN activated */ -#define CLOCK_HFCLK192MSTAT_ALWAYSRUNNING_Pos (4UL) /*!< Position of ALWAYSRUNNING field. */ -#define CLOCK_HFCLK192MSTAT_ALWAYSRUNNING_Msk (0x1UL << CLOCK_HFCLK192MSTAT_ALWAYSRUNNING_Pos) /*!< Bit mask of ALWAYSRUNNING field. */ -#define CLOCK_HFCLK192MSTAT_ALWAYSRUNNING_NotRunning (0UL) /*!< Automatic clock control enabled */ -#define CLOCK_HFCLK192MSTAT_ALWAYSRUNNING_Running (1UL) /*!< Oscillator is always running */ - -/* Bit 0 : Active clock source */ -#define CLOCK_HFCLK192MSTAT_SRC_Pos (0UL) /*!< Position of SRC field. */ -#define CLOCK_HFCLK192MSTAT_SRC_Msk (0x1UL << CLOCK_HFCLK192MSTAT_SRC_Pos) /*!< Bit mask of SRC field. */ -#define CLOCK_HFCLK192MSTAT_SRC_HFINT (0UL) /*!< Clock source: HFINT - on-chip oscillator */ -#define CLOCK_HFCLK192MSTAT_SRC_HFXO (1UL) /*!< Clock source: HFXO - derived from external 32 MHz crystal oscillator */ - /* Register: CLOCK_HFCLKSRC */ /* Description: Clock source for HFCLK128M/HFCLK64M */ @@ -1185,19 +951,12 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: CLOCK_HFCLKCTRL */ /* Description: HFCLK128M frequency configuration */ -/* Bit 0 : High frequency clock HCLK */ +/* Bits 1..0 : High frequency clock HCLK */ #define CLOCK_HFCLKCTRL_HCLK_Pos (0UL) /*!< Position of HCLK field. */ -#define CLOCK_HFCLKCTRL_HCLK_Msk (0x1UL << CLOCK_HFCLKCTRL_HCLK_Pos) /*!< Bit mask of HCLK field. */ +#define CLOCK_HFCLKCTRL_HCLK_Msk (0x3UL << CLOCK_HFCLKCTRL_HCLK_Pos) /*!< Bit mask of HCLK field. */ #define CLOCK_HFCLKCTRL_HCLK_Div1 (0UL) /*!< Divide HFCLK by 1 */ #define CLOCK_HFCLKCTRL_HCLK_Div2 (1UL) /*!< Divide HFCLK by 2 */ -/* Register: CLOCK_HFCLKAUDIO_FREQUENCY */ -/* Description: Audio PLL frequency in 11.176 MHz - 11.402 MHz or 12.165 MHz - 12.411 MHz frequency bands */ - -/* Bits 15..0 : Frequency 0: 10.666 MHz 65535: 13.333 MHz */ -#define CLOCK_HFCLKAUDIO_FREQUENCY_FREQUENCY_Pos (0UL) /*!< Position of FREQUENCY field. */ -#define CLOCK_HFCLKAUDIO_FREQUENCY_FREQUENCY_Msk (0xFFFFUL << CLOCK_HFCLKAUDIO_FREQUENCY_FREQUENCY_Pos) /*!< Bit mask of FREQUENCY field. */ - /* Register: CLOCK_HFCLKALWAYSRUN */ /* Description: Automatic or manual control of HFCLK128M/HFCLK64M */ @@ -1216,43 +975,6 @@ POSSIBILITY OF SUCH DAMAGE. #define CLOCK_LFCLKALWAYSRUN_ALWAYSRUN_Automatic (0UL) /*!< Use automatic clock control */ #define CLOCK_LFCLKALWAYSRUN_ALWAYSRUN_AlwaysRun (1UL) /*!< Ensure clock is always running */ -/* Register: CLOCK_HFCLKAUDIOALWAYSRUN */ -/* Description: Automatic or manual control of HFCLKAUDIO */ - -/* Bit 0 : Ensure clock is always running */ -#define CLOCK_HFCLKAUDIOALWAYSRUN_ALWAYSRUN_Pos (0UL) /*!< Position of ALWAYSRUN field. */ -#define CLOCK_HFCLKAUDIOALWAYSRUN_ALWAYSRUN_Msk (0x1UL << CLOCK_HFCLKAUDIOALWAYSRUN_ALWAYSRUN_Pos) /*!< Bit mask of ALWAYSRUN field. */ -#define CLOCK_HFCLKAUDIOALWAYSRUN_ALWAYSRUN_Automatic (0UL) /*!< Use automatic clock control */ -#define CLOCK_HFCLKAUDIOALWAYSRUN_ALWAYSRUN_AlwaysRun (1UL) /*!< Ensure clock is always running */ - -/* Register: CLOCK_HFCLK192MSRC */ -/* Description: Clock source for HFCLK192M */ - -/* Bit 0 : Select which HFCLK192M source is started by the HFCLK192MSTART task */ -#define CLOCK_HFCLK192MSRC_SRC_Pos (0UL) /*!< Position of SRC field. */ -#define CLOCK_HFCLK192MSRC_SRC_Msk (0x1UL << CLOCK_HFCLK192MSRC_SRC_Pos) /*!< Bit mask of SRC field. */ -#define CLOCK_HFCLK192MSRC_SRC_HFINT (0UL) /*!< HFCLK192MSTART task starts HFINT oscillator */ -#define CLOCK_HFCLK192MSRC_SRC_HFXO (1UL) /*!< HFCLK192MSTART task starts HFXO oscillator */ - -/* Register: CLOCK_HFCLK192MALWAYSRUN */ -/* Description: Automatic or manual control of HFCLK192M */ - -/* Bit 0 : Ensure clock is always running */ -#define CLOCK_HFCLK192MALWAYSRUN_ALWAYSRUN_Pos (0UL) /*!< Position of ALWAYSRUN field. */ -#define CLOCK_HFCLK192MALWAYSRUN_ALWAYSRUN_Msk (0x1UL << CLOCK_HFCLK192MALWAYSRUN_ALWAYSRUN_Pos) /*!< Bit mask of ALWAYSRUN field. */ -#define CLOCK_HFCLK192MALWAYSRUN_ALWAYSRUN_Automatic (0UL) /*!< Use automatic clock control */ -#define CLOCK_HFCLK192MALWAYSRUN_ALWAYSRUN_AlwaysRun (1UL) /*!< Ensure clock is always running */ - -/* Register: CLOCK_HFCLK192MCTRL */ -/* Description: HFCLK192M frequency configuration */ - -/* Bits 1..0 : High frequency clock HCLK192M */ -#define CLOCK_HFCLK192MCTRL_HCLK192M_Pos (0UL) /*!< Position of HCLK192M field. */ -#define CLOCK_HFCLK192MCTRL_HCLK192M_Msk (0x3UL << CLOCK_HFCLK192MCTRL_HCLK192M_Pos) /*!< Bit mask of HCLK192M field. */ -#define CLOCK_HFCLK192MCTRL_HCLK192M_Div1 (0UL) /*!< Divide HFCLK192M by 1 */ -#define CLOCK_HFCLK192MCTRL_HCLK192M_Div2 (1UL) /*!< Divide HFCLK192M by 2 */ -#define CLOCK_HFCLK192MCTRL_HCLK192M_Div4 (2UL) /*!< Divide HFCLK192M by 4 */ - /* Peripheral: CTI */ /* Description: Cross-Trigger Interface control. NOTE: this is not a separate peripheral, but describes CM33 functionality. */ @@ -1260,7 +982,7 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: CTI_CTICONTROL */ /* Description: CTI Control register */ -/* Bit 0 : Enables or disables the CTI */ +/* Bit 0 : Enables or disables the CTI. */ #define CTI_CTICONTROL_GLBEN_Pos (0UL) /*!< Position of GLBEN field. */ #define CTI_CTICONTROL_GLBEN_Msk (0x1UL << CTI_CTICONTROL_GLBEN_Pos) /*!< Bit mask of GLBEN field. */ #define CTI_CTICONTROL_GLBEN_Disabled (0UL) /*!< All cross-triggering mapping logic functionality is disabled. */ @@ -1272,68 +994,68 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 7 : N/A */ #define CTI_CTIINTACK_UNUSED5_Pos (7UL) /*!< Position of UNUSED5 field. */ #define CTI_CTIINTACK_UNUSED5_Msk (0x1UL << CTI_CTIINTACK_UNUSED5_Pos) /*!< Bit mask of UNUSED5 field. */ -#define CTI_CTIINTACK_UNUSED5_Acknowledge (1UL) /*!< Clears the ctitrigout */ +#define CTI_CTIINTACK_UNUSED5_Acknowledge (1UL) /*!< Clears the ctitrigout. */ /* Bit 6 : N/A */ #define CTI_CTIINTACK_UNUSED4_Pos (6UL) /*!< Position of UNUSED4 field. */ #define CTI_CTIINTACK_UNUSED4_Msk (0x1UL << CTI_CTIINTACK_UNUSED4_Pos) /*!< Bit mask of UNUSED4 field. */ -#define CTI_CTIINTACK_UNUSED4_Acknowledge (1UL) /*!< Clears the ctitrigout */ +#define CTI_CTIINTACK_UNUSED4_Acknowledge (1UL) /*!< Clears the ctitrigout. */ /* Bit 5 : N/A */ #define CTI_CTIINTACK_UNUSED3_Pos (5UL) /*!< Position of UNUSED3 field. */ #define CTI_CTIINTACK_UNUSED3_Msk (0x1UL << CTI_CTIINTACK_UNUSED3_Pos) /*!< Bit mask of UNUSED3 field. */ -#define CTI_CTIINTACK_UNUSED3_Acknowledge (1UL) /*!< Clears the ctitrigout */ +#define CTI_CTIINTACK_UNUSED3_Acknowledge (1UL) /*!< Clears the ctitrigout. */ /* Bit 4 : N/A */ #define CTI_CTIINTACK_UNUSED2_Pos (4UL) /*!< Position of UNUSED2 field. */ #define CTI_CTIINTACK_UNUSED2_Msk (0x1UL << CTI_CTIINTACK_UNUSED2_Pos) /*!< Bit mask of UNUSED2 field. */ -#define CTI_CTIINTACK_UNUSED2_Acknowledge (1UL) /*!< Clears the ctitrigout */ +#define CTI_CTIINTACK_UNUSED2_Acknowledge (1UL) /*!< Clears the ctitrigout. */ /* Bit 3 : N/A */ #define CTI_CTIINTACK_UNUSED1_Pos (3UL) /*!< Position of UNUSED1 field. */ #define CTI_CTIINTACK_UNUSED1_Msk (0x1UL << CTI_CTIINTACK_UNUSED1_Pos) /*!< Bit mask of UNUSED1 field. */ -#define CTI_CTIINTACK_UNUSED1_Acknowledge (1UL) /*!< Clears the ctitrigout */ +#define CTI_CTIINTACK_UNUSED1_Acknowledge (1UL) /*!< Clears the ctitrigout. */ /* Bit 2 : N/A */ #define CTI_CTIINTACK_UNUSED0_Pos (2UL) /*!< Position of UNUSED0 field. */ #define CTI_CTIINTACK_UNUSED0_Msk (0x1UL << CTI_CTIINTACK_UNUSED0_Pos) /*!< Bit mask of UNUSED0 field. */ -#define CTI_CTIINTACK_UNUSED0_Acknowledge (1UL) /*!< Clears the ctitrigout */ +#define CTI_CTIINTACK_UNUSED0_Acknowledge (1UL) /*!< Clears the ctitrigout. */ /* Bit 1 : Processor Restart */ #define CTI_CTIINTACK_CPURESTART_Pos (1UL) /*!< Position of CPURESTART field. */ #define CTI_CTIINTACK_CPURESTART_Msk (0x1UL << CTI_CTIINTACK_CPURESTART_Pos) /*!< Bit mask of CPURESTART field. */ -#define CTI_CTIINTACK_CPURESTART_Acknowledge (1UL) /*!< Clears the ctitrigout */ +#define CTI_CTIINTACK_CPURESTART_Acknowledge (1UL) /*!< Clears the ctitrigout. */ /* Bit 0 : Processor debug request */ #define CTI_CTIINTACK_DEBUGREQ_Pos (0UL) /*!< Position of DEBUGREQ field. */ #define CTI_CTIINTACK_DEBUGREQ_Msk (0x1UL << CTI_CTIINTACK_DEBUGREQ_Pos) /*!< Bit mask of DEBUGREQ field. */ -#define CTI_CTIINTACK_DEBUGREQ_Acknowledge (1UL) /*!< Clears the ctitrigout */ +#define CTI_CTIINTACK_DEBUGREQ_Acknowledge (1UL) /*!< Clears the ctitrigout. */ /* Register: CTI_CTIAPPSET */ /* Description: CTI Application Trigger Set register */ -/* Bit 3 : Application trigger event for channel 3 */ +/* Bit 3 : Application trigger event for channel 3. */ #define CTI_CTIAPPSET_APPSET_3_Pos (3UL) /*!< Position of APPSET_3 field. */ #define CTI_CTIAPPSET_APPSET_3_Msk (0x1UL << CTI_CTIAPPSET_APPSET_3_Pos) /*!< Bit mask of APPSET_3 field. */ #define CTI_CTIAPPSET_APPSET_3_Inactive (0UL) /*!< Application trigger 3 is inactive. */ #define CTI_CTIAPPSET_APPSET_3_Active (1UL) /*!< Application trigger 3 is active. */ #define CTI_CTIAPPSET_APPSET_3_Activate (1UL) /*!< Generate channel event for channel 3. */ -/* Bit 2 : Application trigger event for channel 2 */ +/* Bit 2 : Application trigger event for channel 2. */ #define CTI_CTIAPPSET_APPSET_2_Pos (2UL) /*!< Position of APPSET_2 field. */ #define CTI_CTIAPPSET_APPSET_2_Msk (0x1UL << CTI_CTIAPPSET_APPSET_2_Pos) /*!< Bit mask of APPSET_2 field. */ #define CTI_CTIAPPSET_APPSET_2_Inactive (0UL) /*!< Application trigger 2 is inactive. */ #define CTI_CTIAPPSET_APPSET_2_Active (1UL) /*!< Application trigger 2 is active. */ #define CTI_CTIAPPSET_APPSET_2_Activate (1UL) /*!< Generate channel event for channel 2. */ -/* Bit 1 : Application trigger event for channel 1 */ +/* Bit 1 : Application trigger event for channel 1. */ #define CTI_CTIAPPSET_APPSET_1_Pos (1UL) /*!< Position of APPSET_1 field. */ #define CTI_CTIAPPSET_APPSET_1_Msk (0x1UL << CTI_CTIAPPSET_APPSET_1_Pos) /*!< Bit mask of APPSET_1 field. */ #define CTI_CTIAPPSET_APPSET_1_Inactive (0UL) /*!< Application trigger 1 is inactive. */ #define CTI_CTIAPPSET_APPSET_1_Active (1UL) /*!< Application trigger 1 is active. */ #define CTI_CTIAPPSET_APPSET_1_Activate (1UL) /*!< Generate channel event for channel 1. */ -/* Bit 0 : Application trigger event for channel 0 */ +/* Bit 0 : Application trigger event for channel 0. */ #define CTI_CTIAPPSET_APPSET_0_Pos (0UL) /*!< Position of APPSET_0 field. */ #define CTI_CTIAPPSET_APPSET_0_Msk (0x1UL << CTI_CTIAPPSET_APPSET_0_Pos) /*!< Bit mask of APPSET_0 field. */ #define CTI_CTIAPPSET_APPSET_0_Inactive (0UL) /*!< Application trigger 0 is inactive. */ @@ -1346,22 +1068,22 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 3 : Sets the corresponding bits in the CTIAPPSET to 0. There is one bit of the register for each channel. */ #define CTI_CTIAPPCLEAR_APPCLEAR_3_Pos (3UL) /*!< Position of APPCLEAR_3 field. */ #define CTI_CTIAPPCLEAR_APPCLEAR_3_Msk (0x1UL << CTI_CTIAPPCLEAR_APPCLEAR_3_Pos) /*!< Bit mask of APPCLEAR_3 field. */ -#define CTI_CTIAPPCLEAR_APPCLEAR_3_Clear (1UL) /*!< Clears the event for channel 3 */ +#define CTI_CTIAPPCLEAR_APPCLEAR_3_Clear (1UL) /*!< Clears the event for channel 3. */ /* Bit 2 : Sets the corresponding bits in the CTIAPPSET to 0. There is one bit of the register for each channel. */ #define CTI_CTIAPPCLEAR_APPCLEAR_2_Pos (2UL) /*!< Position of APPCLEAR_2 field. */ #define CTI_CTIAPPCLEAR_APPCLEAR_2_Msk (0x1UL << CTI_CTIAPPCLEAR_APPCLEAR_2_Pos) /*!< Bit mask of APPCLEAR_2 field. */ -#define CTI_CTIAPPCLEAR_APPCLEAR_2_Clear (1UL) /*!< Clears the event for channel 2 */ +#define CTI_CTIAPPCLEAR_APPCLEAR_2_Clear (1UL) /*!< Clears the event for channel 2. */ /* Bit 1 : Sets the corresponding bits in the CTIAPPSET to 0. There is one bit of the register for each channel. */ #define CTI_CTIAPPCLEAR_APPCLEAR_1_Pos (1UL) /*!< Position of APPCLEAR_1 field. */ #define CTI_CTIAPPCLEAR_APPCLEAR_1_Msk (0x1UL << CTI_CTIAPPCLEAR_APPCLEAR_1_Pos) /*!< Bit mask of APPCLEAR_1 field. */ -#define CTI_CTIAPPCLEAR_APPCLEAR_1_Clear (1UL) /*!< Clears the event for channel 1 */ +#define CTI_CTIAPPCLEAR_APPCLEAR_1_Clear (1UL) /*!< Clears the event for channel 1. */ /* Bit 0 : Sets the corresponding bits in the CTIAPPSET to 0. There is one bit of the register for each channel. */ #define CTI_CTIAPPCLEAR_APPCLEAR_0_Pos (0UL) /*!< Position of APPCLEAR_0 field. */ #define CTI_CTIAPPCLEAR_APPCLEAR_0_Msk (0x1UL << CTI_CTIAPPCLEAR_APPCLEAR_0_Pos) /*!< Bit mask of APPCLEAR_0 field. */ -#define CTI_CTIAPPCLEAR_APPCLEAR_0_Clear (1UL) /*!< Clears the event for channel 0 */ +#define CTI_CTIAPPCLEAR_APPCLEAR_0_Clear (1UL) /*!< Clears the event for channel 0. */ /* Register: CTI_CTIAPPPULSE */ /* Description: CTI Application Pulse register */ @@ -1369,76 +1091,76 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 3 : Setting a bit HIGH generates a channel event pulse for the selected channel. There is one bit of the register for each channel. */ #define CTI_CTIAPPPULSE_APPULSE_3_Pos (3UL) /*!< Position of APPULSE_3 field. */ #define CTI_CTIAPPPULSE_APPULSE_3_Msk (0x1UL << CTI_CTIAPPPULSE_APPULSE_3_Pos) /*!< Bit mask of APPULSE_3 field. */ -#define CTI_CTIAPPPULSE_APPULSE_3_Generate (1UL) /*!< Generates an event pulse on channel 3 */ +#define CTI_CTIAPPPULSE_APPULSE_3_Generate (1UL) /*!< Generates an event pulse on channel 3. */ /* Bit 2 : Setting a bit HIGH generates a channel event pulse for the selected channel. There is one bit of the register for each channel. */ #define CTI_CTIAPPPULSE_APPULSE_2_Pos (2UL) /*!< Position of APPULSE_2 field. */ #define CTI_CTIAPPPULSE_APPULSE_2_Msk (0x1UL << CTI_CTIAPPPULSE_APPULSE_2_Pos) /*!< Bit mask of APPULSE_2 field. */ -#define CTI_CTIAPPPULSE_APPULSE_2_Generate (1UL) /*!< Generates an event pulse on channel 2 */ +#define CTI_CTIAPPPULSE_APPULSE_2_Generate (1UL) /*!< Generates an event pulse on channel 2. */ /* Bit 1 : Setting a bit HIGH generates a channel event pulse for the selected channel. There is one bit of the register for each channel. */ #define CTI_CTIAPPPULSE_APPULSE_1_Pos (1UL) /*!< Position of APPULSE_1 field. */ #define CTI_CTIAPPPULSE_APPULSE_1_Msk (0x1UL << CTI_CTIAPPPULSE_APPULSE_1_Pos) /*!< Bit mask of APPULSE_1 field. */ -#define CTI_CTIAPPPULSE_APPULSE_1_Generate (1UL) /*!< Generates an event pulse on channel 1 */ +#define CTI_CTIAPPPULSE_APPULSE_1_Generate (1UL) /*!< Generates an event pulse on channel 1. */ /* Bit 0 : Setting a bit HIGH generates a channel event pulse for the selected channel. There is one bit of the register for each channel. */ #define CTI_CTIAPPPULSE_APPULSE_0_Pos (0UL) /*!< Position of APPULSE_0 field. */ #define CTI_CTIAPPPULSE_APPULSE_0_Msk (0x1UL << CTI_CTIAPPPULSE_APPULSE_0_Pos) /*!< Bit mask of APPULSE_0 field. */ -#define CTI_CTIAPPPULSE_APPULSE_0_Generate (1UL) /*!< Generates an event pulse on channel 0 */ +#define CTI_CTIAPPPULSE_APPULSE_0_Generate (1UL) /*!< Generates an event pulse on channel 0. */ /* Register: CTI_CTIINEN */ /* Description: Description collection: CTI Trigger input */ -/* Bit 3 : Enables a cross trigger event to channel 3 when a ctitrigin input is activated */ +/* Bit 3 : Enables a cross trigger event to channel 3 when a ctitrigin input is activated. */ #define CTI_CTIINEN_TRIGINEN_3_Pos (3UL) /*!< Position of TRIGINEN_3 field. */ #define CTI_CTIINEN_TRIGINEN_3_Msk (0x1UL << CTI_CTIINEN_TRIGINEN_3_Pos) /*!< Bit mask of TRIGINEN_3 field. */ -#define CTI_CTIINEN_TRIGINEN_3_Disabled (0UL) /*!< Input trigger n events are ignored by channel 3 */ -#define CTI_CTIINEN_TRIGINEN_3_Enabled (1UL) /*!< When an event is received on input trigger n (ctitrigin[n]) generate an event on channel 3 */ +#define CTI_CTIINEN_TRIGINEN_3_Disabled (0UL) /*!< Input trigger n events are ignored by channel 3. */ +#define CTI_CTIINEN_TRIGINEN_3_Enabled (1UL) /*!< When an event is received on input trigger n (ctitrigin[n]), generate an event on channel 3. */ -/* Bit 2 : Enables a cross trigger event to channel 2 when a ctitrigin input is activated */ +/* Bit 2 : Enables a cross trigger event to channel 2 when a ctitrigin input is activated. */ #define CTI_CTIINEN_TRIGINEN_2_Pos (2UL) /*!< Position of TRIGINEN_2 field. */ #define CTI_CTIINEN_TRIGINEN_2_Msk (0x1UL << CTI_CTIINEN_TRIGINEN_2_Pos) /*!< Bit mask of TRIGINEN_2 field. */ -#define CTI_CTIINEN_TRIGINEN_2_Disabled (0UL) /*!< Input trigger n events are ignored by channel 2 */ -#define CTI_CTIINEN_TRIGINEN_2_Enabled (1UL) /*!< When an event is received on input trigger n (ctitrigin[n]) generate an event on channel 2 */ +#define CTI_CTIINEN_TRIGINEN_2_Disabled (0UL) /*!< Input trigger n events are ignored by channel 2. */ +#define CTI_CTIINEN_TRIGINEN_2_Enabled (1UL) /*!< When an event is received on input trigger n (ctitrigin[n]), generate an event on channel 2. */ -/* Bit 1 : Enables a cross trigger event to channel 1 when a ctitrigin input is activated */ +/* Bit 1 : Enables a cross trigger event to channel 1 when a ctitrigin input is activated. */ #define CTI_CTIINEN_TRIGINEN_1_Pos (1UL) /*!< Position of TRIGINEN_1 field. */ #define CTI_CTIINEN_TRIGINEN_1_Msk (0x1UL << CTI_CTIINEN_TRIGINEN_1_Pos) /*!< Bit mask of TRIGINEN_1 field. */ -#define CTI_CTIINEN_TRIGINEN_1_Disabled (0UL) /*!< Input trigger n events are ignored by channel 1 */ -#define CTI_CTIINEN_TRIGINEN_1_Enabled (1UL) /*!< When an event is received on input trigger n (ctitrigin[n]) generate an event on channel 1 */ +#define CTI_CTIINEN_TRIGINEN_1_Disabled (0UL) /*!< Input trigger n events are ignored by channel 1. */ +#define CTI_CTIINEN_TRIGINEN_1_Enabled (1UL) /*!< When an event is received on input trigger n (ctitrigin[n]), generate an event on channel 1. */ -/* Bit 0 : Enables a cross trigger event to channel 0 when a ctitrigin input is activated */ +/* Bit 0 : Enables a cross trigger event to channel 0 when a ctitrigin input is activated. */ #define CTI_CTIINEN_TRIGINEN_0_Pos (0UL) /*!< Position of TRIGINEN_0 field. */ #define CTI_CTIINEN_TRIGINEN_0_Msk (0x1UL << CTI_CTIINEN_TRIGINEN_0_Pos) /*!< Bit mask of TRIGINEN_0 field. */ -#define CTI_CTIINEN_TRIGINEN_0_Disabled (0UL) /*!< Input trigger n events are ignored by channel 0 */ -#define CTI_CTIINEN_TRIGINEN_0_Enabled (1UL) /*!< When an event is received on input trigger n (ctitrigin[n]) generate an event on channel 0 */ +#define CTI_CTIINEN_TRIGINEN_0_Disabled (0UL) /*!< Input trigger n events are ignored by channel 0. */ +#define CTI_CTIINEN_TRIGINEN_0_Enabled (1UL) /*!< When an event is received on input trigger n (ctitrigin[n]), generate an event on channel 0. */ /* Register: CTI_CTIOUTEN */ /* Description: Description collection: CTI Trigger output */ -/* Bit 3 : Enables a cross trigger event to ctitrigout when channel 3 when is activated */ +/* Bit 3 : Enables a cross trigger event to ctitrigout when channel 3 is activated. */ #define CTI_CTIOUTEN_TRIGOUTEN_3_Pos (3UL) /*!< Position of TRIGOUTEN_3 field. */ #define CTI_CTIOUTEN_TRIGOUTEN_3_Msk (0x1UL << CTI_CTIOUTEN_TRIGOUTEN_3_Pos) /*!< Bit mask of TRIGOUTEN_3 field. */ -#define CTI_CTIOUTEN_TRIGOUTEN_3_Disabled (0UL) /*!< Channel 3 is ignored by output trigger n */ -#define CTI_CTIOUTEN_TRIGOUTEN_3_Enabled (1UL) /*!< When an event occur on channel 3, generate an event on output event n (ctitrigout[n]) */ +#define CTI_CTIOUTEN_TRIGOUTEN_3_Disabled (0UL) /*!< Channel 3 is ignored by output trigger n. */ +#define CTI_CTIOUTEN_TRIGOUTEN_3_Enabled (1UL) /*!< When an event occurs on channel 3, generate an event on output event n (ctitrigout[n]). */ -/* Bit 2 : Enables a cross trigger event to ctitrigout when channel 2 when is activated */ +/* Bit 2 : Enables a cross trigger event to ctitrigout when channel 2 is activated. */ #define CTI_CTIOUTEN_TRIGOUTEN_2_Pos (2UL) /*!< Position of TRIGOUTEN_2 field. */ #define CTI_CTIOUTEN_TRIGOUTEN_2_Msk (0x1UL << CTI_CTIOUTEN_TRIGOUTEN_2_Pos) /*!< Bit mask of TRIGOUTEN_2 field. */ -#define CTI_CTIOUTEN_TRIGOUTEN_2_Disabled (0UL) /*!< Channel 2 is ignored by output trigger n */ -#define CTI_CTIOUTEN_TRIGOUTEN_2_Enabled (1UL) /*!< When an event occur on channel 2, generate an event on output event n (ctitrigout[n]) */ +#define CTI_CTIOUTEN_TRIGOUTEN_2_Disabled (0UL) /*!< Channel 2 is ignored by output trigger n. */ +#define CTI_CTIOUTEN_TRIGOUTEN_2_Enabled (1UL) /*!< When an event occurs on channel 2, generate an event on output event n (ctitrigout[n]). */ -/* Bit 1 : Enables a cross trigger event to ctitrigout when channel 1 when is activated */ +/* Bit 1 : Enables a cross trigger event to ctitrigout when channel 1 is activated. */ #define CTI_CTIOUTEN_TRIGOUTEN_1_Pos (1UL) /*!< Position of TRIGOUTEN_1 field. */ #define CTI_CTIOUTEN_TRIGOUTEN_1_Msk (0x1UL << CTI_CTIOUTEN_TRIGOUTEN_1_Pos) /*!< Bit mask of TRIGOUTEN_1 field. */ -#define CTI_CTIOUTEN_TRIGOUTEN_1_Disabled (0UL) /*!< Channel 1 is ignored by output trigger n */ -#define CTI_CTIOUTEN_TRIGOUTEN_1_Enabled (1UL) /*!< When an event occur on channel 1, generate an event on output event n (ctitrigout[n]) */ +#define CTI_CTIOUTEN_TRIGOUTEN_1_Disabled (0UL) /*!< Channel 1 is ignored by output trigger n. */ +#define CTI_CTIOUTEN_TRIGOUTEN_1_Enabled (1UL) /*!< When an event occurs on channel 1, generate an event on output event n (ctitrigout[n]). */ -/* Bit 0 : Enables a cross trigger event to ctitrigout when channel 0 when is activated */ +/* Bit 0 : Enables a cross trigger event to ctitrigout when channel 0 is activated. */ #define CTI_CTIOUTEN_TRIGOUTEN_0_Pos (0UL) /*!< Position of TRIGOUTEN_0 field. */ #define CTI_CTIOUTEN_TRIGOUTEN_0_Msk (0x1UL << CTI_CTIOUTEN_TRIGOUTEN_0_Pos) /*!< Bit mask of TRIGOUTEN_0 field. */ -#define CTI_CTIOUTEN_TRIGOUTEN_0_Disabled (0UL) /*!< Channel 0 is ignored by output trigger n */ -#define CTI_CTIOUTEN_TRIGOUTEN_0_Enabled (1UL) /*!< When an event occur on channel 0, generate an event on output event n (ctitrigout[n]) */ +#define CTI_CTIOUTEN_TRIGOUTEN_0_Disabled (0UL) /*!< Channel 0 is ignored by output trigger n. */ +#define CTI_CTIOUTEN_TRIGOUTEN_0_Enabled (1UL) /*!< When an event occurs on channel 0, generate an event on output event n (ctitrigout[n]). */ /* Register: CTI_CTITRIGINSTATUS */ /* Description: CTI Trigger In Status register */ @@ -1446,50 +1168,50 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 7 : N/A */ #define CTI_CTITRIGINSTATUS_UNUSED3_Pos (7UL) /*!< Position of UNUSED3 field. */ #define CTI_CTITRIGINSTATUS_UNUSED3_Msk (0x1UL << CTI_CTITRIGINSTATUS_UNUSED3_Pos) /*!< Bit mask of UNUSED3 field. */ -#define CTI_CTITRIGINSTATUS_UNUSED3_Inactive (0UL) /*!< Ctitrigin 7 is inactive */ -#define CTI_CTITRIGINSTATUS_UNUSED3_Active (1UL) /*!< Ctitrigin 7 is active */ +#define CTI_CTITRIGINSTATUS_UNUSED3_Inactive (0UL) /*!< Ctitrigin 7 is inactive. */ +#define CTI_CTITRIGINSTATUS_UNUSED3_Active (1UL) /*!< Ctitrigin 7 is active. */ /* Bit 6 : N/A */ #define CTI_CTITRIGINSTATUS_UNUSED2_Pos (6UL) /*!< Position of UNUSED2 field. */ #define CTI_CTITRIGINSTATUS_UNUSED2_Msk (0x1UL << CTI_CTITRIGINSTATUS_UNUSED2_Pos) /*!< Bit mask of UNUSED2 field. */ -#define CTI_CTITRIGINSTATUS_UNUSED2_Inactive (0UL) /*!< Ctitrigin 6 is inactive */ -#define CTI_CTITRIGINSTATUS_UNUSED2_Active (1UL) /*!< Ctitrigin 6 is active */ +#define CTI_CTITRIGINSTATUS_UNUSED2_Inactive (0UL) /*!< Ctitrigin 6 is inactive. */ +#define CTI_CTITRIGINSTATUS_UNUSED2_Active (1UL) /*!< Ctitrigin 6 is active. */ /* Bit 5 : N/A */ #define CTI_CTITRIGINSTATUS_UNUSED1_Pos (5UL) /*!< Position of UNUSED1 field. */ #define CTI_CTITRIGINSTATUS_UNUSED1_Msk (0x1UL << CTI_CTITRIGINSTATUS_UNUSED1_Pos) /*!< Bit mask of UNUSED1 field. */ -#define CTI_CTITRIGINSTATUS_UNUSED1_Inactive (0UL) /*!< Ctitrigin 5 is inactive */ -#define CTI_CTITRIGINSTATUS_UNUSED1_Active (1UL) /*!< Ctitrigin 5 is active */ +#define CTI_CTITRIGINSTATUS_UNUSED1_Inactive (0UL) /*!< Ctitrigin 5 is inactive. */ +#define CTI_CTITRIGINSTATUS_UNUSED1_Active (1UL) /*!< Ctitrigin 5 is active. */ /* Bit 4 : N/A */ #define CTI_CTITRIGINSTATUS_UNUSED0_Pos (4UL) /*!< Position of UNUSED0 field. */ #define CTI_CTITRIGINSTATUS_UNUSED0_Msk (0x1UL << CTI_CTITRIGINSTATUS_UNUSED0_Pos) /*!< Bit mask of UNUSED0 field. */ -#define CTI_CTITRIGINSTATUS_UNUSED0_Inactive (0UL) /*!< Ctitrigin 4 is inactive */ -#define CTI_CTITRIGINSTATUS_UNUSED0_Active (1UL) /*!< Ctitrigin 4 is active */ +#define CTI_CTITRIGINSTATUS_UNUSED0_Inactive (0UL) /*!< Ctitrigin 4 is inactive. */ +#define CTI_CTITRIGINSTATUS_UNUSED0_Active (1UL) /*!< Ctitrigin 4 is active. */ /* Bit 3 : DWT Comparator Output 2 */ #define CTI_CTITRIGINSTATUS_DWTCOMPOUT2_Pos (3UL) /*!< Position of DWTCOMPOUT2 field. */ #define CTI_CTITRIGINSTATUS_DWTCOMPOUT2_Msk (0x1UL << CTI_CTITRIGINSTATUS_DWTCOMPOUT2_Pos) /*!< Bit mask of DWTCOMPOUT2 field. */ -#define CTI_CTITRIGINSTATUS_DWTCOMPOUT2_Inactive (0UL) /*!< Ctitrigin 3 is inactive */ -#define CTI_CTITRIGINSTATUS_DWTCOMPOUT2_Active (1UL) /*!< Ctitrigin 3 is active */ +#define CTI_CTITRIGINSTATUS_DWTCOMPOUT2_Inactive (0UL) /*!< Ctitrigin 3 is inactive. */ +#define CTI_CTITRIGINSTATUS_DWTCOMPOUT2_Active (1UL) /*!< Ctitrigin 3 is active. */ /* Bit 2 : DWT Comparator Output 1 */ #define CTI_CTITRIGINSTATUS_DWTCOMPOUT1_Pos (2UL) /*!< Position of DWTCOMPOUT1 field. */ #define CTI_CTITRIGINSTATUS_DWTCOMPOUT1_Msk (0x1UL << CTI_CTITRIGINSTATUS_DWTCOMPOUT1_Pos) /*!< Bit mask of DWTCOMPOUT1 field. */ -#define CTI_CTITRIGINSTATUS_DWTCOMPOUT1_Inactive (0UL) /*!< Ctitrigin 2 is inactive */ -#define CTI_CTITRIGINSTATUS_DWTCOMPOUT1_Active (1UL) /*!< Ctitrigin 2 is active */ +#define CTI_CTITRIGINSTATUS_DWTCOMPOUT1_Inactive (0UL) /*!< Ctitrigin 2 is inactive. */ +#define CTI_CTITRIGINSTATUS_DWTCOMPOUT1_Active (1UL) /*!< Ctitrigin 2 is active. */ /* Bit 1 : DWT Comparator Output 0 */ #define CTI_CTITRIGINSTATUS_DWTCOMPOUT0_Pos (1UL) /*!< Position of DWTCOMPOUT0 field. */ #define CTI_CTITRIGINSTATUS_DWTCOMPOUT0_Msk (0x1UL << CTI_CTITRIGINSTATUS_DWTCOMPOUT0_Pos) /*!< Bit mask of DWTCOMPOUT0 field. */ -#define CTI_CTITRIGINSTATUS_DWTCOMPOUT0_Inactive (0UL) /*!< Ctitrigin 1 is inactive */ -#define CTI_CTITRIGINSTATUS_DWTCOMPOUT0_Active (1UL) /*!< Ctitrigin 1 is active */ +#define CTI_CTITRIGINSTATUS_DWTCOMPOUT0_Inactive (0UL) /*!< Ctitrigin 1 is inactive. */ +#define CTI_CTITRIGINSTATUS_DWTCOMPOUT0_Active (1UL) /*!< Ctitrigin 1 is active. */ /* Bit 0 : Processor Halted */ #define CTI_CTITRIGINSTATUS_CPUHALTED_Pos (0UL) /*!< Position of CPUHALTED field. */ #define CTI_CTITRIGINSTATUS_CPUHALTED_Msk (0x1UL << CTI_CTITRIGINSTATUS_CPUHALTED_Pos) /*!< Bit mask of CPUHALTED field. */ -#define CTI_CTITRIGINSTATUS_CPUHALTED_Inactive (0UL) /*!< Ctitrigin 0 is inactive */ -#define CTI_CTITRIGINSTATUS_CPUHALTED_Active (1UL) /*!< Ctitrigin 0 is active */ +#define CTI_CTITRIGINSTATUS_CPUHALTED_Inactive (0UL) /*!< Ctitrigin 0 is inactive. */ +#define CTI_CTITRIGINSTATUS_CPUHALTED_Active (1UL) /*!< Ctitrigin 0 is active. */ /* Register: CTI_CTITRIGOUTSTATUS */ /* Description: CTI Trigger Out Status register */ @@ -1497,50 +1219,50 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 7 : N/A */ #define CTI_CTITRIGOUTSTATUS_UNUSED5_Pos (7UL) /*!< Position of UNUSED5 field. */ #define CTI_CTITRIGOUTSTATUS_UNUSED5_Msk (0x1UL << CTI_CTITRIGOUTSTATUS_UNUSED5_Pos) /*!< Bit mask of UNUSED5 field. */ -#define CTI_CTITRIGOUTSTATUS_UNUSED5_Inactive (0UL) /*!< Ctitrigout 7 is inactive */ -#define CTI_CTITRIGOUTSTATUS_UNUSED5_Active (1UL) /*!< Ctitrigout 7 is active */ +#define CTI_CTITRIGOUTSTATUS_UNUSED5_Inactive (0UL) /*!< Ctitrigout 7 is inactive. */ +#define CTI_CTITRIGOUTSTATUS_UNUSED5_Active (1UL) /*!< Ctitrigout 7 is active. */ /* Bit 6 : N/A */ #define CTI_CTITRIGOUTSTATUS_UNUSED4_Pos (6UL) /*!< Position of UNUSED4 field. */ #define CTI_CTITRIGOUTSTATUS_UNUSED4_Msk (0x1UL << CTI_CTITRIGOUTSTATUS_UNUSED4_Pos) /*!< Bit mask of UNUSED4 field. */ -#define CTI_CTITRIGOUTSTATUS_UNUSED4_Inactive (0UL) /*!< Ctitrigout 6 is inactive */ -#define CTI_CTITRIGOUTSTATUS_UNUSED4_Active (1UL) /*!< Ctitrigout 6 is active */ +#define CTI_CTITRIGOUTSTATUS_UNUSED4_Inactive (0UL) /*!< Ctitrigout 6 is inactive. */ +#define CTI_CTITRIGOUTSTATUS_UNUSED4_Active (1UL) /*!< Ctitrigout 6 is active. */ /* Bit 5 : N/A */ #define CTI_CTITRIGOUTSTATUS_UNUSED3_Pos (5UL) /*!< Position of UNUSED3 field. */ #define CTI_CTITRIGOUTSTATUS_UNUSED3_Msk (0x1UL << CTI_CTITRIGOUTSTATUS_UNUSED3_Pos) /*!< Bit mask of UNUSED3 field. */ -#define CTI_CTITRIGOUTSTATUS_UNUSED3_Inactive (0UL) /*!< Ctitrigout 5 is inactive */ -#define CTI_CTITRIGOUTSTATUS_UNUSED3_Active (1UL) /*!< Ctitrigout 5 is active */ +#define CTI_CTITRIGOUTSTATUS_UNUSED3_Inactive (0UL) /*!< Ctitrigout 5 is inactive. */ +#define CTI_CTITRIGOUTSTATUS_UNUSED3_Active (1UL) /*!< Ctitrigout 5 is active. */ /* Bit 4 : N/A */ #define CTI_CTITRIGOUTSTATUS_UNUSED2_Pos (4UL) /*!< Position of UNUSED2 field. */ #define CTI_CTITRIGOUTSTATUS_UNUSED2_Msk (0x1UL << CTI_CTITRIGOUTSTATUS_UNUSED2_Pos) /*!< Bit mask of UNUSED2 field. */ -#define CTI_CTITRIGOUTSTATUS_UNUSED2_Inactive (0UL) /*!< Ctitrigout 4 is inactive */ -#define CTI_CTITRIGOUTSTATUS_UNUSED2_Active (1UL) /*!< Ctitrigout 4 is active */ +#define CTI_CTITRIGOUTSTATUS_UNUSED2_Inactive (0UL) /*!< Ctitrigout 4 is inactive. */ +#define CTI_CTITRIGOUTSTATUS_UNUSED2_Active (1UL) /*!< Ctitrigout 4 is active. */ /* Bit 3 : N/A */ #define CTI_CTITRIGOUTSTATUS_UNUSED1_Pos (3UL) /*!< Position of UNUSED1 field. */ #define CTI_CTITRIGOUTSTATUS_UNUSED1_Msk (0x1UL << CTI_CTITRIGOUTSTATUS_UNUSED1_Pos) /*!< Bit mask of UNUSED1 field. */ -#define CTI_CTITRIGOUTSTATUS_UNUSED1_Inactive (0UL) /*!< Ctitrigout 3 is inactive */ -#define CTI_CTITRIGOUTSTATUS_UNUSED1_Active (1UL) /*!< Ctitrigout 3 is active */ +#define CTI_CTITRIGOUTSTATUS_UNUSED1_Inactive (0UL) /*!< Ctitrigout 3 is inactive. */ +#define CTI_CTITRIGOUTSTATUS_UNUSED1_Active (1UL) /*!< Ctitrigout 3 is active. */ /* Bit 2 : N/A */ #define CTI_CTITRIGOUTSTATUS_UNUSED0_Pos (2UL) /*!< Position of UNUSED0 field. */ #define CTI_CTITRIGOUTSTATUS_UNUSED0_Msk (0x1UL << CTI_CTITRIGOUTSTATUS_UNUSED0_Pos) /*!< Bit mask of UNUSED0 field. */ -#define CTI_CTITRIGOUTSTATUS_UNUSED0_Inactive (0UL) /*!< Ctitrigout 2 is inactive */ -#define CTI_CTITRIGOUTSTATUS_UNUSED0_Active (1UL) /*!< Ctitrigout 2 is active */ +#define CTI_CTITRIGOUTSTATUS_UNUSED0_Inactive (0UL) /*!< Ctitrigout 2 is inactive. */ +#define CTI_CTITRIGOUTSTATUS_UNUSED0_Active (1UL) /*!< Ctitrigout 2 is active. */ /* Bit 1 : Processor Restart */ #define CTI_CTITRIGOUTSTATUS_CPURESTART_Pos (1UL) /*!< Position of CPURESTART field. */ #define CTI_CTITRIGOUTSTATUS_CPURESTART_Msk (0x1UL << CTI_CTITRIGOUTSTATUS_CPURESTART_Pos) /*!< Bit mask of CPURESTART field. */ -#define CTI_CTITRIGOUTSTATUS_CPURESTART_Inactive (0UL) /*!< Ctitrigout 1 is inactive */ -#define CTI_CTITRIGOUTSTATUS_CPURESTART_Active (1UL) /*!< Ctitrigout 1 is active */ +#define CTI_CTITRIGOUTSTATUS_CPURESTART_Inactive (0UL) /*!< Ctitrigout 1 is inactive. */ +#define CTI_CTITRIGOUTSTATUS_CPURESTART_Active (1UL) /*!< Ctitrigout 1 is active. */ /* Bit 0 : Processor debug request */ #define CTI_CTITRIGOUTSTATUS_DEBUGREQ_Pos (0UL) /*!< Position of DEBUGREQ field. */ #define CTI_CTITRIGOUTSTATUS_DEBUGREQ_Msk (0x1UL << CTI_CTITRIGOUTSTATUS_DEBUGREQ_Pos) /*!< Bit mask of DEBUGREQ field. */ -#define CTI_CTITRIGOUTSTATUS_DEBUGREQ_Inactive (0UL) /*!< Ctitrigout 0 is inactive */ -#define CTI_CTITRIGOUTSTATUS_DEBUGREQ_Active (1UL) /*!< Ctitrigout 0 is active */ +#define CTI_CTITRIGOUTSTATUS_DEBUGREQ_Inactive (0UL) /*!< Ctitrigout 0 is inactive. */ +#define CTI_CTITRIGOUTSTATUS_DEBUGREQ_Active (1UL) /*!< Ctitrigout 0 is active. */ /* Register: CTI_CTICHINSTATUS */ /* Description: CTI Channel In Status register */ @@ -1548,69 +1270,69 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 3 : Shows the status of the ctitrigin 3 input. */ #define CTI_CTICHINSTATUS_CTICHINSTATUS_3_Pos (3UL) /*!< Position of CTICHINSTATUS_3 field. */ #define CTI_CTICHINSTATUS_CTICHINSTATUS_3_Msk (0x1UL << CTI_CTICHINSTATUS_CTICHINSTATUS_3_Pos) /*!< Bit mask of CTICHINSTATUS_3 field. */ -#define CTI_CTICHINSTATUS_CTICHINSTATUS_3_Inactive (0UL) /*!< Ctichin 3 is inactive */ -#define CTI_CTICHINSTATUS_CTICHINSTATUS_3_Active (1UL) /*!< Ctichin 3 is active */ +#define CTI_CTICHINSTATUS_CTICHINSTATUS_3_Inactive (0UL) /*!< Ctichin 3 is inactive. */ +#define CTI_CTICHINSTATUS_CTICHINSTATUS_3_Active (1UL) /*!< Ctichin 3 is active. */ /* Bit 2 : Shows the status of the ctitrigin 2 input. */ #define CTI_CTICHINSTATUS_CTICHINSTATUS_2_Pos (2UL) /*!< Position of CTICHINSTATUS_2 field. */ #define CTI_CTICHINSTATUS_CTICHINSTATUS_2_Msk (0x1UL << CTI_CTICHINSTATUS_CTICHINSTATUS_2_Pos) /*!< Bit mask of CTICHINSTATUS_2 field. */ -#define CTI_CTICHINSTATUS_CTICHINSTATUS_2_Inactive (0UL) /*!< Ctichin 2 is inactive */ -#define CTI_CTICHINSTATUS_CTICHINSTATUS_2_Active (1UL) /*!< Ctichin 2 is active */ +#define CTI_CTICHINSTATUS_CTICHINSTATUS_2_Inactive (0UL) /*!< Ctichin 2 is inactive. */ +#define CTI_CTICHINSTATUS_CTICHINSTATUS_2_Active (1UL) /*!< Ctichin 2 is active. */ /* Bit 1 : Shows the status of the ctitrigin 1 input. */ #define CTI_CTICHINSTATUS_CTICHINSTATUS_1_Pos (1UL) /*!< Position of CTICHINSTATUS_1 field. */ #define CTI_CTICHINSTATUS_CTICHINSTATUS_1_Msk (0x1UL << CTI_CTICHINSTATUS_CTICHINSTATUS_1_Pos) /*!< Bit mask of CTICHINSTATUS_1 field. */ -#define CTI_CTICHINSTATUS_CTICHINSTATUS_1_Inactive (0UL) /*!< Ctichin 1 is inactive */ -#define CTI_CTICHINSTATUS_CTICHINSTATUS_1_Active (1UL) /*!< Ctichin 1 is active */ +#define CTI_CTICHINSTATUS_CTICHINSTATUS_1_Inactive (0UL) /*!< Ctichin 1 is inactive. */ +#define CTI_CTICHINSTATUS_CTICHINSTATUS_1_Active (1UL) /*!< Ctichin 1 is active. */ /* Bit 0 : Shows the status of the ctitrigin 0 input. */ #define CTI_CTICHINSTATUS_CTICHINSTATUS_0_Pos (0UL) /*!< Position of CTICHINSTATUS_0 field. */ #define CTI_CTICHINSTATUS_CTICHINSTATUS_0_Msk (0x1UL << CTI_CTICHINSTATUS_CTICHINSTATUS_0_Pos) /*!< Bit mask of CTICHINSTATUS_0 field. */ -#define CTI_CTICHINSTATUS_CTICHINSTATUS_0_Inactive (0UL) /*!< Ctichin 0 is inactive */ -#define CTI_CTICHINSTATUS_CTICHINSTATUS_0_Active (1UL) /*!< Ctichin 0 is active */ +#define CTI_CTICHINSTATUS_CTICHINSTATUS_0_Inactive (0UL) /*!< Ctichin 0 is inactive. */ +#define CTI_CTICHINSTATUS_CTICHINSTATUS_0_Active (1UL) /*!< Ctichin 0 is active. */ /* Register: CTI_CTIGATE */ /* Description: Enable CTI Channel Gate register */ -/* Bit 3 : Enable ctichout3 */ +/* Bit 3 : Enable ctichout3. */ #define CTI_CTIGATE_CTIGATEEN_3_Pos (3UL) /*!< Position of CTIGATEEN_3 field. */ #define CTI_CTIGATE_CTIGATEEN_3_Msk (0x1UL << CTI_CTIGATE_CTIGATEEN_3_Pos) /*!< Bit mask of CTIGATEEN_3 field. */ -#define CTI_CTIGATE_CTIGATEEN_3_Disabled (0UL) /*!< Disable ctichout channel 3 propagation */ -#define CTI_CTIGATE_CTIGATEEN_3_Enabled (1UL) /*!< Enable ctichout channel 3 propagation */ +#define CTI_CTIGATE_CTIGATEEN_3_Disabled (0UL) /*!< Disable ctichout channel 3 propagation. */ +#define CTI_CTIGATE_CTIGATEEN_3_Enabled (1UL) /*!< Enable ctichout channel 3 propagation. */ -/* Bit 2 : Enable ctichout2 */ +/* Bit 2 : Enable ctichout2. */ #define CTI_CTIGATE_CTIGATEEN_2_Pos (2UL) /*!< Position of CTIGATEEN_2 field. */ #define CTI_CTIGATE_CTIGATEEN_2_Msk (0x1UL << CTI_CTIGATE_CTIGATEEN_2_Pos) /*!< Bit mask of CTIGATEEN_2 field. */ -#define CTI_CTIGATE_CTIGATEEN_2_Disabled (0UL) /*!< Disable ctichout channel 2 propagation */ -#define CTI_CTIGATE_CTIGATEEN_2_Enabled (1UL) /*!< Enable ctichout channel 2 propagation */ +#define CTI_CTIGATE_CTIGATEEN_2_Disabled (0UL) /*!< Disable ctichout channel 2 propagation. */ +#define CTI_CTIGATE_CTIGATEEN_2_Enabled (1UL) /*!< Enable ctichout channel 2 propagation. */ -/* Bit 1 : Enable ctichout1 */ +/* Bit 1 : Enable ctichout1. */ #define CTI_CTIGATE_CTIGATEEN_1_Pos (1UL) /*!< Position of CTIGATEEN_1 field. */ #define CTI_CTIGATE_CTIGATEEN_1_Msk (0x1UL << CTI_CTIGATE_CTIGATEEN_1_Pos) /*!< Bit mask of CTIGATEEN_1 field. */ -#define CTI_CTIGATE_CTIGATEEN_1_Disabled (0UL) /*!< Disable ctichout channel 1 propagation */ -#define CTI_CTIGATE_CTIGATEEN_1_Enabled (1UL) /*!< Enable ctichout channel 1 propagation */ +#define CTI_CTIGATE_CTIGATEEN_1_Disabled (0UL) /*!< Disable ctichout channel 1 propagation. */ +#define CTI_CTIGATE_CTIGATEEN_1_Enabled (1UL) /*!< Enable ctichout channel 1 propagation. */ -/* Bit 0 : Enable ctichout0 */ +/* Bit 0 : Enable ctichout0. */ #define CTI_CTIGATE_CTIGATEEN_0_Pos (0UL) /*!< Position of CTIGATEEN_0 field. */ #define CTI_CTIGATE_CTIGATEEN_0_Msk (0x1UL << CTI_CTIGATE_CTIGATEEN_0_Pos) /*!< Bit mask of CTIGATEEN_0 field. */ -#define CTI_CTIGATE_CTIGATEEN_0_Disabled (0UL) /*!< Disable ctichout channel 0 propagation */ -#define CTI_CTIGATE_CTIGATEEN_0_Enabled (1UL) /*!< Enable ctichout channel 0 propagation */ +#define CTI_CTIGATE_CTIGATEEN_0_Disabled (0UL) /*!< Disable ctichout channel 0 propagation. */ +#define CTI_CTIGATE_CTIGATEEN_0_Enabled (1UL) /*!< Enable ctichout channel 0 propagation. */ /* Register: CTI_DEVARCH */ /* Description: Device Architecture register */ -/* Bit 0 : Contains the CTI device architecture */ +/* Bit 0 : Contains the CTI device architecture. */ #define CTI_DEVARCH_Architecture_Pos (0UL) /*!< Position of Architecture field. */ #define CTI_DEVARCH_Architecture_Msk (0x1UL << CTI_DEVARCH_Architecture_Pos) /*!< Bit mask of Architecture field. */ /* Register: CTI_DEVID */ /* Description: Device Configuration register */ -/* Bits 19..16 : Number of ECT channels available */ +/* Bits 19..16 : Number of ECT channels available. */ #define CTI_DEVID_NUMCH_Pos (16UL) /*!< Position of NUMCH field. */ #define CTI_DEVID_NUMCH_Msk (0xFUL << CTI_DEVID_NUMCH_Pos) /*!< Bit mask of NUMCH field. */ -/* Bits 15..8 : Number of ECT triggers available */ +/* Bits 15..8 : Number of ECT triggers available. */ #define CTI_DEVID_NUMTRIG_Pos (8UL) /*!< Position of NUMTRIG field. */ #define CTI_DEVID_NUMTRIG_Msk (0xFFUL << CTI_DEVID_NUMTRIG_Pos) /*!< Bit mask of NUMTRIG field. */ @@ -1626,22 +1348,22 @@ POSSIBILITY OF SUCH DAMAGE. the major classification as specified in the MAJOR field. */ #define CTI_DEVTYPE_SUB_Pos (4UL) /*!< Position of SUB field. */ #define CTI_DEVTYPE_SUB_Msk (0xFUL << CTI_DEVTYPE_SUB_Pos) /*!< Bit mask of SUB field. */ -#define CTI_DEVTYPE_SUB_Crosstrigger (0b0001UL) /*!< Indicates that this component is a sub-triggering component */ +#define CTI_DEVTYPE_SUB_Crosstrigger (0b0001UL) /*!< Indicates that this component is a sub-triggering component. */ /* Bits 3..0 : Major classification of the type of the debug component as specified in the ARM Architecture Specification for this - debug and trace component */ + debug and trace component. */ #define CTI_DEVTYPE_MAJOR_Pos (0UL) /*!< Position of MAJOR field. */ #define CTI_DEVTYPE_MAJOR_Msk (0xFUL << CTI_DEVTYPE_MAJOR_Pos) /*!< Bit mask of MAJOR field. */ -#define CTI_DEVTYPE_MAJOR_Controller (0b0100UL) /*!< Indicates that this component allows a debugger to control other components in a CoreSight SoC-400 system */ +#define CTI_DEVTYPE_MAJOR_Controller (0b0100UL) /*!< Indicates that this component allows a debugger to control other components in a CoreSight SoC-400 system. */ /* Register: CTI_PIDR4 */ /* Description: Peripheral ID4 Register */ -/* Bits 7..4 : Always 0b0000. Indicates that the device only occupies 4KB of memory */ +/* Bits 7..4 : Always 0b0000. Indicates that the device only occupies 4KB of memory. */ #define CTI_PIDR4_SIZE_Pos (4UL) /*!< Position of SIZE field. */ #define CTI_PIDR4_SIZE_Msk (0xFUL << CTI_PIDR4_SIZE_Pos) /*!< Bit mask of SIZE field. */ -/* Bits 3..0 : Together, PIDR1.DES_0, PIDR2.DES_1, and PIDR4.DES_2 identify the designer of the component */ +/* Bits 3..0 : Together, PIDR1.DES_0, PIDR2.DES_1, and PIDR4.DES_2 identify the designer of the component. */ #define CTI_PIDR4_DES_2_Pos (0UL) /*!< Position of DES_2 field. */ #define CTI_PIDR4_DES_2_Msk (0xFUL << CTI_PIDR4_DES_2_Pos) /*!< Bit mask of DES_2 field. */ #define CTI_PIDR4_DES_2_Code (0b0100UL) /*!< JEDEC continuation code */ @@ -1649,23 +1371,23 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: CTI_PIDR0 */ /* Description: Peripheral ID0 Register */ -/* Bits 7..0 : Bits[7:0] of the 12-bit part number of the component. The designer of the component assigns this part number */ +/* Bits 7..0 : Bits[7:0] of the 12-bit part number of the component. The designer of the component assigns this part number. */ #define CTI_PIDR0_PART_0_Pos (0UL) /*!< Position of PART_0 field. */ #define CTI_PIDR0_PART_0_Msk (0xFFUL << CTI_PIDR0_PART_0_Pos) /*!< Bit mask of PART_0 field. */ -#define CTI_PIDR0_PART_0_PartnumberL (0x21UL) /*!< Indicates bits[7:0] of the part number of the component */ +#define CTI_PIDR0_PART_0_PartnumberL (0x21UL) /*!< Indicates bits[7:0] of the part number of the component. */ /* Register: CTI_PIDR1 */ /* Description: Peripheral ID1 Register */ -/* Bits 7..4 : Together, PIDR1.DES_0, PIDR2.DES_1, and PIDR4.DES_2 identify the designer of the component */ +/* Bits 7..4 : Together, PIDR1.DES_0, PIDR2.DES_1, and PIDR4.DES_2 identify the designer of the component. */ #define CTI_PIDR1_DES_0_Pos (4UL) /*!< Position of DES_0 field. */ #define CTI_PIDR1_DES_0_Msk (0xFUL << CTI_PIDR1_DES_0_Pos) /*!< Bit mask of DES_0 field. */ #define CTI_PIDR1_DES_0_Arm (0b1011UL) /*!< ARM. Bits[3:0] of the JEDEC JEP106 Identity Code */ -/* Bits 3..0 : Bits[11:8] of the 12-bit part number of the component. The designer of the component assigns this part number */ +/* Bits 3..0 : Bits[11:8] of the 12-bit part number of the component. The designer of the component assigns this part number. */ #define CTI_PIDR1_PART_1_Pos (0UL) /*!< Position of PART_1 field. */ #define CTI_PIDR1_PART_1_Msk (0xFUL << CTI_PIDR1_PART_1_Pos) /*!< Bit mask of PART_1 field. */ -#define CTI_PIDR1_PART_1_PartnumberH (0b1101UL) /*!< Indicates bits[11:8] of the part number of the component */ +#define CTI_PIDR1_PART_1_PartnumberH (0b1101UL) /*!< Indicates bits[11:8] of the part number of the component. */ /* Register: CTI_PIDR2 */ /* Description: Peripheral ID2 Register */ @@ -1675,11 +1397,11 @@ POSSIBILITY OF SUCH DAMAGE. #define CTI_PIDR2_REVISION_Msk (0xFUL << CTI_PIDR2_REVISION_Pos) /*!< Bit mask of REVISION field. */ #define CTI_PIDR2_REVISION_Rev0p0 (0b0000UL) /*!< This device is at r0p0 */ -/* Bit 3 : Always 1. Indicates that the JEDEC-assigned designer ID is used */ +/* Bit 3 : Always 1. Indicates that the JEDEC-assigned designer ID is used. */ #define CTI_PIDR2_JEDEC_Pos (3UL) /*!< Position of JEDEC field. */ #define CTI_PIDR2_JEDEC_Msk (0x1UL << CTI_PIDR2_JEDEC_Pos) /*!< Bit mask of JEDEC field. */ -/* Bits 2..0 : Together, PIDR1.DES_0, PIDR2.DES_1, and PIDR4.DES_2 identify the designer of the component */ +/* Bits 2..0 : Together, PIDR1.DES_0, PIDR2.DES_1, and PIDR4.DES_2 identify the designer of the component. */ #define CTI_PIDR2_DES_1_Pos (0UL) /*!< Position of DES_1 field. */ #define CTI_PIDR2_DES_1_Msk (0x7UL << CTI_PIDR2_DES_1_Pos) /*!< Bit mask of DES_1 field. */ #define CTI_PIDR2_DES_1_Arm (0b011UL) /*!< ARM. Bits[6:4] of the JEDEC JEP106 Identity Code */ @@ -1692,21 +1414,21 @@ POSSIBILITY OF SUCH DAMAGE. metal fix can change this field if required, for example, by driving it from registers that reset to 0b0000. */ #define CTI_PIDR3_REVAND_Pos (4UL) /*!< Position of REVAND field. */ #define CTI_PIDR3_REVAND_Msk (0xFUL << CTI_PIDR3_REVAND_Pos) /*!< Bit mask of REVAND field. */ -#define CTI_PIDR3_REVAND_NoErrata (0b000UL) /*!< Indicates that there are no errata fixes to this component */ +#define CTI_PIDR3_REVAND_NoErrata (0b000UL) /*!< Indicates that there are no errata fixes to this component. */ /* Bits 3..0 : Customer Modified. Indicates whether the customer has modified the behavior of the component. In most cases, this field is 0b0000. Customers change this value when they make authorized modifications to this component. */ #define CTI_PIDR3_CMOD_Pos (0UL) /*!< Position of CMOD field. */ #define CTI_PIDR3_CMOD_Msk (0xFUL << CTI_PIDR3_CMOD_Pos) /*!< Bit mask of CMOD field. */ -#define CTI_PIDR3_CMOD_Unmodified (0b000UL) /*!< Indicates that the customer has not modified this component */ +#define CTI_PIDR3_CMOD_Unmodified (0b000UL) /*!< Indicates that the customer has not modified this component. */ /* Register: CTI_CIDR0 */ /* Description: Component ID0 Register */ -/* Bits 7..0 : Preamble[0]. Contains bits[7:0] of the component identification code */ +/* Bits 7..0 : Preamble[0]. Contains bits[7:0] of the component identification code. */ #define CTI_CIDR0_PRMBL_0_Pos (0UL) /*!< Position of PRMBL_0 field. */ #define CTI_CIDR0_PRMBL_0_Msk (0xFFUL << CTI_CIDR0_PRMBL_0_Pos) /*!< Bit mask of PRMBL_0 field. */ -#define CTI_CIDR0_PRMBL_0_Value (0x0DUL) /*!< Bits[7:0] of the identification code */ +#define CTI_CIDR0_PRMBL_0_Value (0x0DUL) /*!< Bits[7:0] of the identification code. */ /* Register: CTI_CIDR1 */ /* Description: Component ID1 Register */ @@ -1715,42 +1437,42 @@ POSSIBILITY OF SUCH DAMAGE. Contains bits[15:12] of the component identification code */ #define CTI_CIDR1_CLASS_Pos (4UL) /*!< Position of CLASS field. */ #define CTI_CIDR1_CLASS_Msk (0xFUL << CTI_CIDR1_CLASS_Pos) /*!< Bit mask of CLASS field. */ -#define CTI_CIDR1_CLASS_Coresight (0b1001UL) /*!< Indicates that the component is a CoreSight component */ +#define CTI_CIDR1_CLASS_Coresight (0b1001UL) /*!< Indicates that the component is a CoreSight component. */ -/* Bits 3..0 : Preamble[1]. Contains bits[11:8] of the component identification code */ +/* Bits 3..0 : Preamble[1]. Contains bits[11:8] of the component identification code. */ #define CTI_CIDR1_PRMBL_1_Pos (0UL) /*!< Position of PRMBL_1 field. */ #define CTI_CIDR1_PRMBL_1_Msk (0xFUL << CTI_CIDR1_PRMBL_1_Pos) /*!< Bit mask of PRMBL_1 field. */ -#define CTI_CIDR1_PRMBL_1_Value (0b0000UL) /*!< Bits[11:8] of the identification code */ +#define CTI_CIDR1_PRMBL_1_Value (0b0000UL) /*!< Bits[11:8] of the identification code. */ /* Register: CTI_CIDR2 */ /* Description: Component ID2 Register */ -/* Bits 7..0 : Preamble[2]. Contains bits[23:16] of the component identification code */ +/* Bits 7..0 : Preamble[2]. Contains bits[23:16] of the component identification code. */ #define CTI_CIDR2_PRMBL_2_Pos (0UL) /*!< Position of PRMBL_2 field. */ #define CTI_CIDR2_PRMBL_2_Msk (0xFFUL << CTI_CIDR2_PRMBL_2_Pos) /*!< Bit mask of PRMBL_2 field. */ -#define CTI_CIDR2_PRMBL_2_Value (0x05UL) /*!< Bits[23:16] of the identification code */ +#define CTI_CIDR2_PRMBL_2_Value (0x05UL) /*!< Bits[23:16] of the identification code. */ /* Register: CTI_CIDR3 */ /* Description: Component ID3 Register */ -/* Bits 7..0 : Preamble[3]. Contains bits[31:24] of the component identification code */ +/* Bits 7..0 : Preamble[3]. Contains bits[31:24] of the component identification code. */ #define CTI_CIDR3_PRMBL_3_Pos (0UL) /*!< Position of PRMBL_3 field. */ #define CTI_CIDR3_PRMBL_3_Msk (0xFFUL << CTI_CIDR3_PRMBL_3_Pos) /*!< Bit mask of PRMBL_3 field. */ -#define CTI_CIDR3_PRMBL_3_Value (0xB1UL) /*!< Bits[31:24] of the identification code */ +#define CTI_CIDR3_PRMBL_3_Value (0xB1UL) /*!< Bits[31:24] of the identification code. */ /* Peripheral: CTRLAPPERI */ /* Description: Control access port */ /* Register: CTRLAPPERI_MAILBOX_RXDATA */ -/* Description: Data sent from the debugger to the CPU */ +/* Description: Data sent from the debugger to the CPU. */ /* Bits 31..0 : Data received from debugger */ #define CTRLAPPERI_MAILBOX_RXDATA_RXDATA_Pos (0UL) /*!< Position of RXDATA field. */ #define CTRLAPPERI_MAILBOX_RXDATA_RXDATA_Msk (0xFFFFFFFFUL << CTRLAPPERI_MAILBOX_RXDATA_RXDATA_Pos) /*!< Bit mask of RXDATA field. */ /* Register: CTRLAPPERI_MAILBOX_RXSTATUS */ -/* Description: Status to indicate if data sent from the debugger to the CPU has been read */ +/* Description: This register shows a status that indicates if data sent from the debugger to the CPU has been read. */ /* Bit 0 : Status of data in register RXDATA */ #define CTRLAPPERI_MAILBOX_RXSTATUS_RXSTATUS_Pos (0UL) /*!< Position of RXSTATUS field. */ @@ -1759,14 +1481,14 @@ POSSIBILITY OF SUCH DAMAGE. #define CTRLAPPERI_MAILBOX_RXSTATUS_RXSTATUS_DataPending (1UL) /*!< Data pending in register RXDATA */ /* Register: CTRLAPPERI_MAILBOX_TXDATA */ -/* Description: Data sent from the CPU to the debugger */ +/* Description: Data sent from the CPU to the debugger. */ /* Bits 31..0 : Data sent to debugger */ #define CTRLAPPERI_MAILBOX_TXDATA_TXDATA_Pos (0UL) /*!< Position of TXDATA field. */ #define CTRLAPPERI_MAILBOX_TXDATA_TXDATA_Msk (0xFFFFFFFFUL << CTRLAPPERI_MAILBOX_TXDATA_TXDATA_Pos) /*!< Bit mask of TXDATA field. */ /* Register: CTRLAPPERI_MAILBOX_TXSTATUS */ -/* Description: Status to indicate if data sent from the CPU to the debugger has been read */ +/* Description: This register shows a status that indicates if the data sent from the CPU to the debugger has been read. */ /* Bit 0 : Status of data in register TXDATA */ #define CTRLAPPERI_MAILBOX_TXSTATUS_TXSTATUS_Pos (0UL) /*!< Position of TXSTATUS field. */ @@ -1775,74 +1497,52 @@ POSSIBILITY OF SUCH DAMAGE. #define CTRLAPPERI_MAILBOX_TXSTATUS_TXSTATUS_DataPending (1UL) /*!< Data pending in register TXDATA */ /* Register: CTRLAPPERI_ERASEPROTECT_LOCK */ -/* Description: Lock register ERASEPROTECT.DISABLE from being written until next reset */ +/* Description: This register locks the ERASEPROTECT.DISABLE register from being written until next reset. */ -/* Bit 0 : Lock register ERASEPROTECT.DISABLE from being written until next reset */ +/* Bit 0 : Lock ERASEPROTECT.DISABLE register from being written until next reset */ #define CTRLAPPERI_ERASEPROTECT_LOCK_LOCK_Pos (0UL) /*!< Position of LOCK field. */ #define CTRLAPPERI_ERASEPROTECT_LOCK_LOCK_Msk (0x1UL << CTRLAPPERI_ERASEPROTECT_LOCK_LOCK_Pos) /*!< Bit mask of LOCK field. */ #define CTRLAPPERI_ERASEPROTECT_LOCK_LOCK_Unlocked (0UL) /*!< Register ERASEPROTECT.DISABLE is writeable */ #define CTRLAPPERI_ERASEPROTECT_LOCK_LOCK_Locked (1UL) /*!< Register ERASEPROTECT.DISABLE is read-only */ /* Register: CTRLAPPERI_ERASEPROTECT_DISABLE */ -/* Description: Disable ERASEPROTECT and perform ERASEALL */ +/* Description: This register disables the ERASEPROTECT register and performs an ERASEALL operation. */ -/* Bits 31..0 : The ERASEALL sequence will be initiated if value of KEY fields are non-zero and KEY fields match on both CPU and debugger side */ +/* Bits 31..0 : The ERASEALL sequence is initiated if the value of the KEY fields are non-zero and the KEY fields match on both the CPU and debugger sides. */ #define CTRLAPPERI_ERASEPROTECT_DISABLE_KEY_Pos (0UL) /*!< Position of KEY field. */ #define CTRLAPPERI_ERASEPROTECT_DISABLE_KEY_Msk (0xFFFFFFFFUL << CTRLAPPERI_ERASEPROTECT_DISABLE_KEY_Pos) /*!< Bit mask of KEY field. */ /* Register: CTRLAPPERI_APPROTECT_LOCK */ -/* Description: Lock register APPROTECT.DISABLE from being written to until next reset */ +/* Description: This register locks the APPROTECT.DISABLE register from being written to until next reset. */ -/* Bit 0 : Lock register APPROTECT.DISABLE from being written to until next reset */ +/* Bit 0 : Lock the APPROTECT.DISABLE register from being written to until next reset */ #define CTRLAPPERI_APPROTECT_LOCK_LOCK_Pos (0UL) /*!< Position of LOCK field. */ #define CTRLAPPERI_APPROTECT_LOCK_LOCK_Msk (0x1UL << CTRLAPPERI_APPROTECT_LOCK_LOCK_Pos) /*!< Bit mask of LOCK field. */ #define CTRLAPPERI_APPROTECT_LOCK_LOCK_Unlocked (0UL) /*!< Register APPROTECT.DISABLE is writeable */ #define CTRLAPPERI_APPROTECT_LOCK_LOCK_Locked (1UL) /*!< Register APPROTECT.DISABLE is read-only */ /* Register: CTRLAPPERI_APPROTECT_DISABLE */ -/* Description: Disable APPROTECT and enable debug access to non-secure mode */ +/* Description: This register disables the APPROTECT register and enables debug access to non-secure mode. */ -/* Bits 31..0 : Disable APPROTECT and enable debug access to non-secure mode until next pin reset if KEY fields match The current APPROTECT value as configured from UICR is bypassed if value of KEY fields are non-zero and KEY fields match on both CPU and debugger side */ +/* Bits 31..0 : Disable APPROTECT and enable debug access to non-secure mode until the next pin reset if the KEY fields match. The current APPROTECT value as configured from UICR is bypassed if the value of the KEY fields are non-zero and the KEY fields match on both the CPU and debugger sides. */ #define CTRLAPPERI_APPROTECT_DISABLE_KEY_Pos (0UL) /*!< Position of KEY field. */ #define CTRLAPPERI_APPROTECT_DISABLE_KEY_Msk (0xFFFFFFFFUL << CTRLAPPERI_APPROTECT_DISABLE_KEY_Pos) /*!< Bit mask of KEY field. */ -/* Register: CTRLAPPERI_SECUREAPPROTECT_LOCK */ -/* Description: Lock register SECUREAPPROTECT.DISABLE from being written until next reset */ - -/* Bit 0 : Lock register SECUREAPPROTECT.DISABLE from being written until next reset */ -#define CTRLAPPERI_SECUREAPPROTECT_LOCK_LOCK_Pos (0UL) /*!< Position of LOCK field. */ -#define CTRLAPPERI_SECUREAPPROTECT_LOCK_LOCK_Msk (0x1UL << CTRLAPPERI_SECUREAPPROTECT_LOCK_LOCK_Pos) /*!< Bit mask of LOCK field. */ -#define CTRLAPPERI_SECUREAPPROTECT_LOCK_LOCK_Unlocked (0UL) /*!< Register SECUREAPPROTECT.DISABLE is writeable */ -#define CTRLAPPERI_SECUREAPPROTECT_LOCK_LOCK_Locked (1UL) /*!< Register SECUREAPPROTECT.DISABLE is read-only */ - -/* Register: CTRLAPPERI_SECUREAPPROTECT_DISABLE */ -/* Description: Disable SECUREAPPROTECT and enable debug access to secure mode */ - -/* Bits 31..0 : Disable SECUREAPPROTECT and enable debug of secure mode until next pin reset if KEY fields match The current SECUREAPPROTECT value as configured from UICR is bypassed if value of KEY fields are non-zero and KEY fields match on both CPU and debugger side */ -#define CTRLAPPERI_SECUREAPPROTECT_DISABLE_KEY_Pos (0UL) /*!< Position of KEY field. */ -#define CTRLAPPERI_SECUREAPPROTECT_DISABLE_KEY_Msk (0xFFFFFFFFUL << CTRLAPPERI_SECUREAPPROTECT_DISABLE_KEY_Pos) /*!< Bit mask of KEY field. */ - /* Register: CTRLAPPERI_STATUS */ /* Description: Status bits for CTRL-AP peripheral */ -/* Bit 2 : Status bit for access port protection in secure mode */ -#define CTRLAPPERI_STATUS_SECUREAPPROTECT_Pos (2UL) /*!< Position of SECUREAPPROTECT field. */ -#define CTRLAPPERI_STATUS_SECUREAPPROTECT_Msk (0x1UL << CTRLAPPERI_STATUS_SECUREAPPROTECT_Pos) /*!< Bit mask of SECUREAPPROTECT field. */ -#define CTRLAPPERI_STATUS_SECUREAPPROTECT_Disabled (0UL) /*!< Secure mode access port protection is currently disabled */ -#define CTRLAPPERI_STATUS_SECUREAPPROTECT_Enabled (1UL) /*!< Secure mode access port protection is currently enabled */ +/* Bit 2 : Status bit for device debug interface mode */ +#define CTRLAPPERI_STATUS_DBGIFACEMODE_Pos (2UL) /*!< Position of DBGIFACEMODE field. */ +#define CTRLAPPERI_STATUS_DBGIFACEMODE_Msk (0x1UL << CTRLAPPERI_STATUS_DBGIFACEMODE_Pos) /*!< Bit mask of DBGIFACEMODE field. */ +#define CTRLAPPERI_STATUS_DBGIFACEMODE_Disabled (0UL) /*!< No debugger attached */ +#define CTRLAPPERI_STATUS_DBGIFACEMODE_Enabled (1UL) /*!< Debugger is attached and device is in debug interface mode */ -/* Bit 1 : Status bit for access port protection in non-secure mode */ -#define CTRLAPPERI_STATUS_APPROTECT_Pos (1UL) /*!< Position of APPROTECT field. */ +/* Bit 0 : Status bit for access port protection in non-secure mode */ +#define CTRLAPPERI_STATUS_APPROTECT_Pos (0UL) /*!< Position of APPROTECT field. */ #define CTRLAPPERI_STATUS_APPROTECT_Msk (0x1UL << CTRLAPPERI_STATUS_APPROTECT_Pos) /*!< Bit mask of APPROTECT field. */ #define CTRLAPPERI_STATUS_APPROTECT_Disabled (0UL) /*!< Non-secure mode access port protection is currently disabled */ #define CTRLAPPERI_STATUS_APPROTECT_Enabled (1UL) /*!< Non-secure mode access port protection is currently enabled */ -/* Bit 0 : Status bit for device debug interface mode */ -#define CTRLAPPERI_STATUS_DBGIFACEMODE_Pos (0UL) /*!< Position of DBGIFACEMODE field. */ -#define CTRLAPPERI_STATUS_DBGIFACEMODE_Msk (0x1UL << CTRLAPPERI_STATUS_DBGIFACEMODE_Pos) /*!< Bit mask of DBGIFACEMODE field. */ -#define CTRLAPPERI_STATUS_DBGIFACEMODE_Disabled (0UL) /*!< No debugger attached */ -#define CTRLAPPERI_STATUS_DBGIFACEMODE_Enabled (1UL) /*!< Debugger is attached and device is in debug interface mode */ - /* Peripheral: DCNF */ /* Description: Domain configuration management */ @@ -1883,7 +1583,7 @@ POSSIBILITY OF SUCH DAMAGE. #define DPPIC_SUBSCRIBE_CHG_EN_EN_Disabled (0UL) /*!< Disable subscription */ #define DPPIC_SUBSCRIBE_CHG_EN_EN_Enabled (1UL) /*!< Enable subscription */ -/* Bits 7..0 : Channel that task CHG[n].EN will subscribe to */ +/* Bits 7..0 : DPPI channel that task CHG[n].EN will subscribe to */ #define DPPIC_SUBSCRIBE_CHG_EN_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ #define DPPIC_SUBSCRIBE_CHG_EN_CHIDX_Msk (0xFFUL << DPPIC_SUBSCRIBE_CHG_EN_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ @@ -1896,7 +1596,7 @@ POSSIBILITY OF SUCH DAMAGE. #define DPPIC_SUBSCRIBE_CHG_DIS_EN_Disabled (0UL) /*!< Disable subscription */ #define DPPIC_SUBSCRIBE_CHG_DIS_EN_Enabled (1UL) /*!< Enable subscription */ -/* Bits 7..0 : Channel that task CHG[n].DIS will subscribe to */ +/* Bits 7..0 : DPPI channel that task CHG[n].DIS will subscribe to */ #define DPPIC_SUBSCRIBE_CHG_DIS_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ #define DPPIC_SUBSCRIBE_CHG_DIS_CHIDX_Msk (0xFFUL << DPPIC_SUBSCRIBE_CHG_DIS_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ @@ -2357,7 +2057,7 @@ POSSIBILITY OF SUCH DAMAGE. #define ECB_SUBSCRIBE_STARTECB_EN_Disabled (0UL) /*!< Disable subscription */ #define ECB_SUBSCRIBE_STARTECB_EN_Enabled (1UL) /*!< Enable subscription */ -/* Bits 7..0 : Channel that task STARTECB will subscribe to */ +/* Bits 7..0 : DPPI channel that task STARTECB will subscribe to */ #define ECB_SUBSCRIBE_STARTECB_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ #define ECB_SUBSCRIBE_STARTECB_CHIDX_Msk (0xFFUL << ECB_SUBSCRIBE_STARTECB_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ @@ -2370,7 +2070,7 @@ POSSIBILITY OF SUCH DAMAGE. #define ECB_SUBSCRIBE_STOPECB_EN_Disabled (0UL) /*!< Disable subscription */ #define ECB_SUBSCRIBE_STOPECB_EN_Enabled (1UL) /*!< Enable subscription */ -/* Bits 7..0 : Channel that task STOPECB will subscribe to */ +/* Bits 7..0 : DPPI channel that task STOPECB will subscribe to */ #define ECB_SUBSCRIBE_STOPECB_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ #define ECB_SUBSCRIBE_STOPECB_CHIDX_Msk (0xFFUL << ECB_SUBSCRIBE_STOPECB_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ @@ -2401,7 +2101,7 @@ POSSIBILITY OF SUCH DAMAGE. #define ECB_PUBLISH_ENDECB_EN_Disabled (0UL) /*!< Disable publishing */ #define ECB_PUBLISH_ENDECB_EN_Enabled (1UL) /*!< Enable publishing */ -/* Bits 7..0 : Channel that event ENDECB will publish to. */ +/* Bits 7..0 : DPPI channel that event ENDECB will publish to. */ #define ECB_PUBLISH_ENDECB_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ #define ECB_PUBLISH_ENDECB_CHIDX_Msk (0xFFUL << ECB_PUBLISH_ENDECB_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ @@ -2414,7 +2114,7 @@ POSSIBILITY OF SUCH DAMAGE. #define ECB_PUBLISH_ERRORECB_EN_Disabled (0UL) /*!< Disable publishing */ #define ECB_PUBLISH_ERRORECB_EN_Enabled (1UL) /*!< Enable publishing */ -/* Bits 7..0 : Channel that event ERRORECB will publish to. */ +/* Bits 7..0 : DPPI channel that event ERRORECB will publish to. */ #define ECB_PUBLISH_ERRORECB_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ #define ECB_PUBLISH_ERRORECB_CHIDX_Msk (0xFFUL << ECB_PUBLISH_ERRORECB_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ @@ -2480,7 +2180,7 @@ POSSIBILITY OF SUCH DAMAGE. #define EGU_SUBSCRIBE_TRIGGER_EN_Disabled (0UL) /*!< Disable subscription */ #define EGU_SUBSCRIBE_TRIGGER_EN_Enabled (1UL) /*!< Enable subscription */ -/* Bits 7..0 : Channel that task TRIGGER[n] will subscribe to */ +/* Bits 7..0 : DPPI channel that task TRIGGER[n] will subscribe to */ #define EGU_SUBSCRIBE_TRIGGER_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ #define EGU_SUBSCRIBE_TRIGGER_CHIDX_Msk (0xFFUL << EGU_SUBSCRIBE_TRIGGER_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ @@ -2502,7 +2202,7 @@ POSSIBILITY OF SUCH DAMAGE. #define EGU_PUBLISH_TRIGGERED_EN_Disabled (0UL) /*!< Disable publishing */ #define EGU_PUBLISH_TRIGGERED_EN_Enabled (1UL) /*!< Enable publishing */ -/* Bits 7..0 : Channel that event TRIGGERED[n] will publish to. */ +/* Bits 7..0 : DPPI channel that event TRIGGERED[n] will publish to. */ #define EGU_PUBLISH_TRIGGERED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ #define EGU_PUBLISH_TRIGGERED_CHIDX_Msk (0xFFUL << EGU_PUBLISH_TRIGGERED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ @@ -2868,7 +2568,7 @@ POSSIBILITY OF SUCH DAMAGE. /* Bits 31..0 : Part Variant, Hardware version and Production configuration, encoded as ASCII */ #define FICR_INFO_VARIANT_VARIANT_Pos (0UL) /*!< Position of VARIANT field. */ #define FICR_INFO_VARIANT_VARIANT_Msk (0xFFFFFFFFUL << FICR_INFO_VARIANT_VARIANT_Pos) /*!< Bit mask of VARIANT field. */ -#define FICR_INFO_VARIANT_VARIANT_AAAA (0x41414141UL) /*!< AAAA */ +#define FICR_INFO_VARIANT_VARIANT_QKAA (0x514B4141UL) /*!< QKAA */ #define FICR_INFO_VARIANT_VARIANT_Unspecified (0xFFFFFFFFUL) /*!< Unspecified */ /* Register: FICR_INFO_PACKAGE */ @@ -3013,7 +2713,7 @@ POSSIBILITY OF SUCH DAMAGE. #define GPIOTE_SUBSCRIBE_OUT_EN_Disabled (0UL) /*!< Disable subscription */ #define GPIOTE_SUBSCRIBE_OUT_EN_Enabled (1UL) /*!< Enable subscription */ -/* Bits 7..0 : Channel that task OUT[n] will subscribe to */ +/* Bits 7..0 : DPPI channel that task OUT[n] will subscribe to */ #define GPIOTE_SUBSCRIBE_OUT_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ #define GPIOTE_SUBSCRIBE_OUT_CHIDX_Msk (0xFFUL << GPIOTE_SUBSCRIBE_OUT_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ @@ -3026,7 +2726,7 @@ POSSIBILITY OF SUCH DAMAGE. #define GPIOTE_SUBSCRIBE_SET_EN_Disabled (0UL) /*!< Disable subscription */ #define GPIOTE_SUBSCRIBE_SET_EN_Enabled (1UL) /*!< Enable subscription */ -/* Bits 7..0 : Channel that task SET[n] will subscribe to */ +/* Bits 7..0 : DPPI channel that task SET[n] will subscribe to */ #define GPIOTE_SUBSCRIBE_SET_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ #define GPIOTE_SUBSCRIBE_SET_CHIDX_Msk (0xFFUL << GPIOTE_SUBSCRIBE_SET_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ @@ -3039,7 +2739,7 @@ POSSIBILITY OF SUCH DAMAGE. #define GPIOTE_SUBSCRIBE_CLR_EN_Disabled (0UL) /*!< Disable subscription */ #define GPIOTE_SUBSCRIBE_CLR_EN_Enabled (1UL) /*!< Enable subscription */ -/* Bits 7..0 : Channel that task CLR[n] will subscribe to */ +/* Bits 7..0 : DPPI channel that task CLR[n] will subscribe to */ #define GPIOTE_SUBSCRIBE_CLR_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ #define GPIOTE_SUBSCRIBE_CLR_CHIDX_Msk (0xFFUL << GPIOTE_SUBSCRIBE_CLR_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ @@ -3070,7 +2770,7 @@ POSSIBILITY OF SUCH DAMAGE. #define GPIOTE_PUBLISH_IN_EN_Disabled (0UL) /*!< Disable publishing */ #define GPIOTE_PUBLISH_IN_EN_Enabled (1UL) /*!< Enable publishing */ -/* Bits 7..0 : Channel that event IN[n] will publish to. */ +/* Bits 7..0 : DPPI channel that event IN[n] will publish to. */ #define GPIOTE_PUBLISH_IN_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ #define GPIOTE_PUBLISH_IN_CHIDX_Msk (0xFFUL << GPIOTE_PUBLISH_IN_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ @@ -3083,7 +2783,7 @@ POSSIBILITY OF SUCH DAMAGE. #define GPIOTE_PUBLISH_PORT_EN_Disabled (0UL) /*!< Disable publishing */ #define GPIOTE_PUBLISH_PORT_EN_Enabled (1UL) /*!< Enable publishing */ -/* Bits 7..0 : Channel that event PORT will publish to. */ +/* Bits 7..0 : DPPI channel that event PORT will publish to. */ #define GPIOTE_PUBLISH_PORT_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ #define GPIOTE_PUBLISH_PORT_CHIDX_Msk (0xFFUL << GPIOTE_PUBLISH_PORT_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ @@ -3219,6 +2919,15 @@ POSSIBILITY OF SUCH DAMAGE. #define GPIOTE_INTENCLR_IN0_Enabled (1UL) /*!< Read: Enabled */ #define GPIOTE_INTENCLR_IN0_Clear (1UL) /*!< Disable */ +/* Register: GPIOTE_LATENCY */ +/* Description: Latency selection for Event mode (MODE=Event) with rising or falling edge detection on the pin. */ + +/* Bit 0 : Latency setting */ +#define GPIOTE_LATENCY_LATENCY_Pos (0UL) /*!< Position of LATENCY field. */ +#define GPIOTE_LATENCY_LATENCY_Msk (0x1UL << GPIOTE_LATENCY_LATENCY_Pos) /*!< Bit mask of LATENCY field. */ +#define GPIOTE_LATENCY_LATENCY_LowPower (0UL) /*!< Low power setting, for signals with minimum hold time tGPIOTE,HOLD,LP; refer to Electrical specification section */ +#define GPIOTE_LATENCY_LATENCY_LowLatency (1UL) /*!< Low latency setting, for signals with minimum hold time tGPIOTE,HOLD,LL; refer to Electrical specification section */ + /* Register: GPIOTE_CONFIG */ /* Description: Description collection: Configuration for OUT[n], SET[n], and CLR[n] tasks and IN[n] event */ @@ -3272,7 +2981,7 @@ POSSIBILITY OF SUCH DAMAGE. #define IPC_SUBSCRIBE_SEND_EN_Disabled (0UL) /*!< Disable subscription */ #define IPC_SUBSCRIBE_SEND_EN_Enabled (1UL) /*!< Enable subscription */ -/* Bits 7..0 : Channel that task SEND[n] will subscribe to */ +/* Bits 7..0 : DPPI channel that task SEND[n] will subscribe to */ #define IPC_SUBSCRIBE_SEND_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ #define IPC_SUBSCRIBE_SEND_CHIDX_Msk (0xFFUL << IPC_SUBSCRIBE_SEND_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ @@ -3294,7 +3003,7 @@ POSSIBILITY OF SUCH DAMAGE. #define IPC_PUBLISH_RECEIVE_EN_Disabled (0UL) /*!< Disable publishing */ #define IPC_PUBLISH_RECEIVE_EN_Enabled (1UL) /*!< Enable publishing */ -/* Bits 7..0 : Channel that event RECEIVE[n] will publish to. */ +/* Bits 7..0 : DPPI channel that event RECEIVE[n] will publish to. */ #define IPC_PUBLISH_RECEIVE_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ #define IPC_PUBLISH_RECEIVE_CHIDX_Msk (0xFFUL << IPC_PUBLISH_RECEIVE_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ @@ -4009,29 +3718,6 @@ POSSIBILITY OF SUCH DAMAGE. #define NVMC_IMISS_MISSES_Pos (0UL) /*!< Position of MISSES field. */ #define NVMC_IMISS_MISSES_Msk (0xFFFFFFFFUL << NVMC_IMISS_MISSES_Pos) /*!< Bit mask of MISSES field. */ -/* Register: NVMC_CONFIGNS */ -/* Description: Unspecified */ - -/* Bits 1..0 : Program memory access mode. It is strongly recommended to only activate erase and write modes when they are actively used. Enabling write or erase will invalidate the cache and keep it invalidated. */ -#define NVMC_CONFIGNS_WEN_Pos (0UL) /*!< Position of WEN field. */ -#define NVMC_CONFIGNS_WEN_Msk (0x3UL << NVMC_CONFIGNS_WEN_Pos) /*!< Bit mask of WEN field. */ -#define NVMC_CONFIGNS_WEN_Ren (0UL) /*!< Read only access */ -#define NVMC_CONFIGNS_WEN_Wen (1UL) /*!< Write enabled */ -#define NVMC_CONFIGNS_WEN_Een (2UL) /*!< Erase enabled */ - -/* Register: NVMC_WRITEUICRNS */ -/* Description: Non-secure APPROTECT enable register */ - -/* Bits 31..4 : Key to write in order to validate the write operation */ -#define NVMC_WRITEUICRNS_KEY_Pos (4UL) /*!< Position of KEY field. */ -#define NVMC_WRITEUICRNS_KEY_Msk (0xFFFFFFFUL << NVMC_WRITEUICRNS_KEY_Pos) /*!< Bit mask of KEY field. */ -#define NVMC_WRITEUICRNS_KEY_Keyvalid (0xAFBE5A7UL) /*!< Key value */ - -/* Bit 0 : Allow non-secure code to set APPROTECT */ -#define NVMC_WRITEUICRNS_SET_Pos (0UL) /*!< Position of SET field. */ -#define NVMC_WRITEUICRNS_SET_Msk (0x1UL << NVMC_WRITEUICRNS_SET_Pos) /*!< Bit mask of SET field. */ -#define NVMC_WRITEUICRNS_SET_Set (1UL) /*!< Set value */ - /* Peripheral: GPIO */ /* Description: GPIO Port 0 */ @@ -5771,11 +5457,7 @@ POSSIBILITY OF SUCH DAMAGE. #define GPIO_PIN_CNF_DRIVE_D0H1 (5UL) /*!< Disconnect '0', high drive '1' (normally used for wired-or connections) */ #define GPIO_PIN_CNF_DRIVE_S0D1 (6UL) /*!< Standard '0', disconnect '1' (normally used for wired-and connections) */ #define GPIO_PIN_CNF_DRIVE_H0D1 (7UL) /*!< High drive '0', disconnect '1' (normally used for wired-and connections) */ -#define GPIO_PIN_CNF_DRIVE_E0S1 (9UL) /*!< Extra high drive '0', standard '1' */ -#define GPIO_PIN_CNF_DRIVE_S0E1 (10UL) /*!< Standard '0', extra high drive '1' */ #define GPIO_PIN_CNF_DRIVE_E0E1 (11UL) /*!< Extra high drive '0', extra high drive '1' */ -#define GPIO_PIN_CNF_DRIVE_D0E1 (13UL) /*!< Disconnect '0', extra high drive '1' (normally used for wired-or connections) */ -#define GPIO_PIN_CNF_DRIVE_E0D1 (15UL) /*!< Extra high drive '0', disconnect '1' (normally used for wired-and connections) */ /* Bits 3..2 : Pull configuration */ #define GPIO_PIN_CNF_PULL_Pos (2UL) /*!< Position of PULL field. */ @@ -5801,17 +5483,17 @@ POSSIBILITY OF SUCH DAMAGE. /* Description: Power control */ /* Register: POWER_TASKS_CONSTLAT */ -/* Description: Enable constant latency mode */ +/* Description: Enable Constant Latency mode */ -/* Bit 0 : Enable constant latency mode */ +/* Bit 0 : Enable Constant Latency mode */ #define POWER_TASKS_CONSTLAT_TASKS_CONSTLAT_Pos (0UL) /*!< Position of TASKS_CONSTLAT field. */ #define POWER_TASKS_CONSTLAT_TASKS_CONSTLAT_Msk (0x1UL << POWER_TASKS_CONSTLAT_TASKS_CONSTLAT_Pos) /*!< Bit mask of TASKS_CONSTLAT field. */ #define POWER_TASKS_CONSTLAT_TASKS_CONSTLAT_Trigger (1UL) /*!< Trigger task */ /* Register: POWER_TASKS_LOWPWR */ -/* Description: Enable low power mode (variable latency) */ +/* Description: Enable Low-Power mode (variable latency) */ -/* Bit 0 : Enable low power mode (variable latency) */ +/* Bit 0 : Enable Low-Power mode (variable latency) */ #define POWER_TASKS_LOWPWR_TASKS_LOWPWR_Pos (0UL) /*!< Position of TASKS_LOWPWR field. */ #define POWER_TASKS_LOWPWR_TASKS_LOWPWR_Msk (0x1UL << POWER_TASKS_LOWPWR_TASKS_LOWPWR_Pos) /*!< Bit mask of TASKS_LOWPWR field. */ #define POWER_TASKS_LOWPWR_TASKS_LOWPWR_Trigger (1UL) /*!< Trigger task */ @@ -5825,7 +5507,7 @@ POSSIBILITY OF SUCH DAMAGE. #define POWER_SUBSCRIBE_CONSTLAT_EN_Disabled (0UL) /*!< Disable subscription */ #define POWER_SUBSCRIBE_CONSTLAT_EN_Enabled (1UL) /*!< Enable subscription */ -/* Bits 7..0 : Channel that task CONSTLAT will subscribe to */ +/* Bits 7..0 : DPPI channel that task CONSTLAT will subscribe to */ #define POWER_SUBSCRIBE_CONSTLAT_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ #define POWER_SUBSCRIBE_CONSTLAT_CHIDX_Msk (0xFFUL << POWER_SUBSCRIBE_CONSTLAT_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ @@ -5838,7 +5520,7 @@ POSSIBILITY OF SUCH DAMAGE. #define POWER_SUBSCRIBE_LOWPWR_EN_Disabled (0UL) /*!< Disable subscription */ #define POWER_SUBSCRIBE_LOWPWR_EN_Enabled (1UL) /*!< Enable subscription */ -/* Bits 7..0 : Channel that task LOWPWR will subscribe to */ +/* Bits 7..0 : DPPI channel that task LOWPWR will subscribe to */ #define POWER_SUBSCRIBE_LOWPWR_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ #define POWER_SUBSCRIBE_LOWPWR_CHIDX_Msk (0xFFUL << POWER_SUBSCRIBE_LOWPWR_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ @@ -5878,7 +5560,7 @@ POSSIBILITY OF SUCH DAMAGE. #define POWER_PUBLISH_POFWARN_EN_Disabled (0UL) /*!< Disable publishing */ #define POWER_PUBLISH_POFWARN_EN_Enabled (1UL) /*!< Enable publishing */ -/* Bits 7..0 : Channel that event POFWARN will publish to. */ +/* Bits 7..0 : DPPI channel that event POFWARN will publish to. */ #define POWER_PUBLISH_POFWARN_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ #define POWER_PUBLISH_POFWARN_CHIDX_Msk (0xFFUL << POWER_PUBLISH_POFWARN_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ @@ -5891,7 +5573,7 @@ POSSIBILITY OF SUCH DAMAGE. #define POWER_PUBLISH_SLEEPENTER_EN_Disabled (0UL) /*!< Disable publishing */ #define POWER_PUBLISH_SLEEPENTER_EN_Enabled (1UL) /*!< Enable publishing */ -/* Bits 7..0 : Channel that event SLEEPENTER will publish to. */ +/* Bits 7..0 : DPPI channel that event SLEEPENTER will publish to. */ #define POWER_PUBLISH_SLEEPENTER_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ #define POWER_PUBLISH_SLEEPENTER_CHIDX_Msk (0xFFUL << POWER_PUBLISH_SLEEPENTER_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ @@ -5904,7 +5586,7 @@ POSSIBILITY OF SUCH DAMAGE. #define POWER_PUBLISH_SLEEPEXIT_EN_Disabled (0UL) /*!< Disable publishing */ #define POWER_PUBLISH_SLEEPEXIT_EN_Enabled (1UL) /*!< Enable publishing */ -/* Bits 7..0 : Channel that event SLEEPEXIT will publish to. */ +/* Bits 7..0 : DPPI channel that event SLEEPEXIT will publish to. */ #define POWER_PUBLISH_SLEEPEXIT_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ #define POWER_PUBLISH_SLEEPEXIT_CHIDX_Msk (0xFFUL << POWER_PUBLISH_SLEEPEXIT_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ @@ -6101,7 +5783,7 @@ POSSIBILITY OF SUCH DAMAGE. #define RADIO_SUBSCRIBE_TXEN_EN_Disabled (0UL) /*!< Disable subscription */ #define RADIO_SUBSCRIBE_TXEN_EN_Enabled (1UL) /*!< Enable subscription */ -/* Bits 7..0 : Channel that task TXEN will subscribe to */ +/* Bits 7..0 : DPPI channel that task TXEN will subscribe to */ #define RADIO_SUBSCRIBE_TXEN_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ #define RADIO_SUBSCRIBE_TXEN_CHIDX_Msk (0xFFUL << RADIO_SUBSCRIBE_TXEN_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ @@ -6114,7 +5796,7 @@ POSSIBILITY OF SUCH DAMAGE. #define RADIO_SUBSCRIBE_RXEN_EN_Disabled (0UL) /*!< Disable subscription */ #define RADIO_SUBSCRIBE_RXEN_EN_Enabled (1UL) /*!< Enable subscription */ -/* Bits 7..0 : Channel that task RXEN will subscribe to */ +/* Bits 7..0 : DPPI channel that task RXEN will subscribe to */ #define RADIO_SUBSCRIBE_RXEN_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ #define RADIO_SUBSCRIBE_RXEN_CHIDX_Msk (0xFFUL << RADIO_SUBSCRIBE_RXEN_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ @@ -6127,7 +5809,7 @@ POSSIBILITY OF SUCH DAMAGE. #define RADIO_SUBSCRIBE_START_EN_Disabled (0UL) /*!< Disable subscription */ #define RADIO_SUBSCRIBE_START_EN_Enabled (1UL) /*!< Enable subscription */ -/* Bits 7..0 : Channel that task START will subscribe to */ +/* Bits 7..0 : DPPI channel that task START will subscribe to */ #define RADIO_SUBSCRIBE_START_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ #define RADIO_SUBSCRIBE_START_CHIDX_Msk (0xFFUL << RADIO_SUBSCRIBE_START_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ @@ -6140,7 +5822,7 @@ POSSIBILITY OF SUCH DAMAGE. #define RADIO_SUBSCRIBE_STOP_EN_Disabled (0UL) /*!< Disable subscription */ #define RADIO_SUBSCRIBE_STOP_EN_Enabled (1UL) /*!< Enable subscription */ -/* Bits 7..0 : Channel that task STOP will subscribe to */ +/* Bits 7..0 : DPPI channel that task STOP will subscribe to */ #define RADIO_SUBSCRIBE_STOP_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ #define RADIO_SUBSCRIBE_STOP_CHIDX_Msk (0xFFUL << RADIO_SUBSCRIBE_STOP_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ @@ -6153,7 +5835,7 @@ POSSIBILITY OF SUCH DAMAGE. #define RADIO_SUBSCRIBE_DISABLE_EN_Disabled (0UL) /*!< Disable subscription */ #define RADIO_SUBSCRIBE_DISABLE_EN_Enabled (1UL) /*!< Enable subscription */ -/* Bits 7..0 : Channel that task DISABLE will subscribe to */ +/* Bits 7..0 : DPPI channel that task DISABLE will subscribe to */ #define RADIO_SUBSCRIBE_DISABLE_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ #define RADIO_SUBSCRIBE_DISABLE_CHIDX_Msk (0xFFUL << RADIO_SUBSCRIBE_DISABLE_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ @@ -6166,7 +5848,7 @@ POSSIBILITY OF SUCH DAMAGE. #define RADIO_SUBSCRIBE_RSSISTART_EN_Disabled (0UL) /*!< Disable subscription */ #define RADIO_SUBSCRIBE_RSSISTART_EN_Enabled (1UL) /*!< Enable subscription */ -/* Bits 7..0 : Channel that task RSSISTART will subscribe to */ +/* Bits 7..0 : DPPI channel that task RSSISTART will subscribe to */ #define RADIO_SUBSCRIBE_RSSISTART_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ #define RADIO_SUBSCRIBE_RSSISTART_CHIDX_Msk (0xFFUL << RADIO_SUBSCRIBE_RSSISTART_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ @@ -6179,7 +5861,7 @@ POSSIBILITY OF SUCH DAMAGE. #define RADIO_SUBSCRIBE_RSSISTOP_EN_Disabled (0UL) /*!< Disable subscription */ #define RADIO_SUBSCRIBE_RSSISTOP_EN_Enabled (1UL) /*!< Enable subscription */ -/* Bits 7..0 : Channel that task RSSISTOP will subscribe to */ +/* Bits 7..0 : DPPI channel that task RSSISTOP will subscribe to */ #define RADIO_SUBSCRIBE_RSSISTOP_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ #define RADIO_SUBSCRIBE_RSSISTOP_CHIDX_Msk (0xFFUL << RADIO_SUBSCRIBE_RSSISTOP_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ @@ -6192,7 +5874,7 @@ POSSIBILITY OF SUCH DAMAGE. #define RADIO_SUBSCRIBE_BCSTART_EN_Disabled (0UL) /*!< Disable subscription */ #define RADIO_SUBSCRIBE_BCSTART_EN_Enabled (1UL) /*!< Enable subscription */ -/* Bits 7..0 : Channel that task BCSTART will subscribe to */ +/* Bits 7..0 : DPPI channel that task BCSTART will subscribe to */ #define RADIO_SUBSCRIBE_BCSTART_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ #define RADIO_SUBSCRIBE_BCSTART_CHIDX_Msk (0xFFUL << RADIO_SUBSCRIBE_BCSTART_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ @@ -6205,7 +5887,7 @@ POSSIBILITY OF SUCH DAMAGE. #define RADIO_SUBSCRIBE_BCSTOP_EN_Disabled (0UL) /*!< Disable subscription */ #define RADIO_SUBSCRIBE_BCSTOP_EN_Enabled (1UL) /*!< Enable subscription */ -/* Bits 7..0 : Channel that task BCSTOP will subscribe to */ +/* Bits 7..0 : DPPI channel that task BCSTOP will subscribe to */ #define RADIO_SUBSCRIBE_BCSTOP_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ #define RADIO_SUBSCRIBE_BCSTOP_CHIDX_Msk (0xFFUL << RADIO_SUBSCRIBE_BCSTOP_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ @@ -6218,7 +5900,7 @@ POSSIBILITY OF SUCH DAMAGE. #define RADIO_SUBSCRIBE_EDSTART_EN_Disabled (0UL) /*!< Disable subscription */ #define RADIO_SUBSCRIBE_EDSTART_EN_Enabled (1UL) /*!< Enable subscription */ -/* Bits 7..0 : Channel that task EDSTART will subscribe to */ +/* Bits 7..0 : DPPI channel that task EDSTART will subscribe to */ #define RADIO_SUBSCRIBE_EDSTART_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ #define RADIO_SUBSCRIBE_EDSTART_CHIDX_Msk (0xFFUL << RADIO_SUBSCRIBE_EDSTART_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ @@ -6231,7 +5913,7 @@ POSSIBILITY OF SUCH DAMAGE. #define RADIO_SUBSCRIBE_EDSTOP_EN_Disabled (0UL) /*!< Disable subscription */ #define RADIO_SUBSCRIBE_EDSTOP_EN_Enabled (1UL) /*!< Enable subscription */ -/* Bits 7..0 : Channel that task EDSTOP will subscribe to */ +/* Bits 7..0 : DPPI channel that task EDSTOP will subscribe to */ #define RADIO_SUBSCRIBE_EDSTOP_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ #define RADIO_SUBSCRIBE_EDSTOP_CHIDX_Msk (0xFFUL << RADIO_SUBSCRIBE_EDSTOP_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ @@ -6244,7 +5926,7 @@ POSSIBILITY OF SUCH DAMAGE. #define RADIO_SUBSCRIBE_CCASTART_EN_Disabled (0UL) /*!< Disable subscription */ #define RADIO_SUBSCRIBE_CCASTART_EN_Enabled (1UL) /*!< Enable subscription */ -/* Bits 7..0 : Channel that task CCASTART will subscribe to */ +/* Bits 7..0 : DPPI channel that task CCASTART will subscribe to */ #define RADIO_SUBSCRIBE_CCASTART_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ #define RADIO_SUBSCRIBE_CCASTART_CHIDX_Msk (0xFFUL << RADIO_SUBSCRIBE_CCASTART_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ @@ -6257,7 +5939,7 @@ POSSIBILITY OF SUCH DAMAGE. #define RADIO_SUBSCRIBE_CCASTOP_EN_Disabled (0UL) /*!< Disable subscription */ #define RADIO_SUBSCRIBE_CCASTOP_EN_Enabled (1UL) /*!< Enable subscription */ -/* Bits 7..0 : Channel that task CCASTOP will subscribe to */ +/* Bits 7..0 : DPPI channel that task CCASTOP will subscribe to */ #define RADIO_SUBSCRIBE_CCASTOP_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ #define RADIO_SUBSCRIBE_CCASTOP_CHIDX_Msk (0xFFUL << RADIO_SUBSCRIBE_CCASTOP_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ @@ -6450,10 +6132,19 @@ POSSIBILITY OF SUCH DAMAGE. #define RADIO_EVENTS_MHRMATCH_EVENTS_MHRMATCH_NotGenerated (0UL) /*!< Event not generated */ #define RADIO_EVENTS_MHRMATCH_EVENTS_MHRMATCH_Generated (1UL) /*!< Event generated */ +/* Register: RADIO_EVENTS_SYNC */ +/* Description: Preamble indicator */ + +/* Bit 0 : Preamble indicator */ +#define RADIO_EVENTS_SYNC_EVENTS_SYNC_Pos (0UL) /*!< Position of EVENTS_SYNC field. */ +#define RADIO_EVENTS_SYNC_EVENTS_SYNC_Msk (0x1UL << RADIO_EVENTS_SYNC_EVENTS_SYNC_Pos) /*!< Bit mask of EVENTS_SYNC field. */ +#define RADIO_EVENTS_SYNC_EVENTS_SYNC_NotGenerated (0UL) /*!< Event not generated */ +#define RADIO_EVENTS_SYNC_EVENTS_SYNC_Generated (1UL) /*!< Event generated */ + /* Register: RADIO_EVENTS_PHYEND */ -/* Description: Generated when last bit is sent on air */ +/* Description: Generated when last bit is sent on air, or received from air */ -/* Bit 0 : Generated when last bit is sent on air */ +/* Bit 0 : Generated when last bit is sent on air, or received from air */ #define RADIO_EVENTS_PHYEND_EVENTS_PHYEND_Pos (0UL) /*!< Position of EVENTS_PHYEND field. */ #define RADIO_EVENTS_PHYEND_EVENTS_PHYEND_Msk (0x1UL << RADIO_EVENTS_PHYEND_EVENTS_PHYEND_Pos) /*!< Bit mask of EVENTS_PHYEND field. */ #define RADIO_EVENTS_PHYEND_EVENTS_PHYEND_NotGenerated (0UL) /*!< Event not generated */ @@ -6477,7 +6168,7 @@ POSSIBILITY OF SUCH DAMAGE. #define RADIO_PUBLISH_READY_EN_Disabled (0UL) /*!< Disable publishing */ #define RADIO_PUBLISH_READY_EN_Enabled (1UL) /*!< Enable publishing */ -/* Bits 7..0 : Channel that event READY will publish to. */ +/* Bits 7..0 : DPPI channel that event READY will publish to. */ #define RADIO_PUBLISH_READY_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ #define RADIO_PUBLISH_READY_CHIDX_Msk (0xFFUL << RADIO_PUBLISH_READY_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ @@ -6490,7 +6181,7 @@ POSSIBILITY OF SUCH DAMAGE. #define RADIO_PUBLISH_ADDRESS_EN_Disabled (0UL) /*!< Disable publishing */ #define RADIO_PUBLISH_ADDRESS_EN_Enabled (1UL) /*!< Enable publishing */ -/* Bits 7..0 : Channel that event ADDRESS will publish to. */ +/* Bits 7..0 : DPPI channel that event ADDRESS will publish to. */ #define RADIO_PUBLISH_ADDRESS_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ #define RADIO_PUBLISH_ADDRESS_CHIDX_Msk (0xFFUL << RADIO_PUBLISH_ADDRESS_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ @@ -6503,7 +6194,7 @@ POSSIBILITY OF SUCH DAMAGE. #define RADIO_PUBLISH_PAYLOAD_EN_Disabled (0UL) /*!< Disable publishing */ #define RADIO_PUBLISH_PAYLOAD_EN_Enabled (1UL) /*!< Enable publishing */ -/* Bits 7..0 : Channel that event PAYLOAD will publish to. */ +/* Bits 7..0 : DPPI channel that event PAYLOAD will publish to. */ #define RADIO_PUBLISH_PAYLOAD_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ #define RADIO_PUBLISH_PAYLOAD_CHIDX_Msk (0xFFUL << RADIO_PUBLISH_PAYLOAD_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ @@ -6516,7 +6207,7 @@ POSSIBILITY OF SUCH DAMAGE. #define RADIO_PUBLISH_END_EN_Disabled (0UL) /*!< Disable publishing */ #define RADIO_PUBLISH_END_EN_Enabled (1UL) /*!< Enable publishing */ -/* Bits 7..0 : Channel that event END will publish to. */ +/* Bits 7..0 : DPPI channel that event END will publish to. */ #define RADIO_PUBLISH_END_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ #define RADIO_PUBLISH_END_CHIDX_Msk (0xFFUL << RADIO_PUBLISH_END_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ @@ -6529,7 +6220,7 @@ POSSIBILITY OF SUCH DAMAGE. #define RADIO_PUBLISH_DISABLED_EN_Disabled (0UL) /*!< Disable publishing */ #define RADIO_PUBLISH_DISABLED_EN_Enabled (1UL) /*!< Enable publishing */ -/* Bits 7..0 : Channel that event DISABLED will publish to. */ +/* Bits 7..0 : DPPI channel that event DISABLED will publish to. */ #define RADIO_PUBLISH_DISABLED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ #define RADIO_PUBLISH_DISABLED_CHIDX_Msk (0xFFUL << RADIO_PUBLISH_DISABLED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ @@ -6542,7 +6233,7 @@ POSSIBILITY OF SUCH DAMAGE. #define RADIO_PUBLISH_DEVMATCH_EN_Disabled (0UL) /*!< Disable publishing */ #define RADIO_PUBLISH_DEVMATCH_EN_Enabled (1UL) /*!< Enable publishing */ -/* Bits 7..0 : Channel that event DEVMATCH will publish to. */ +/* Bits 7..0 : DPPI channel that event DEVMATCH will publish to. */ #define RADIO_PUBLISH_DEVMATCH_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ #define RADIO_PUBLISH_DEVMATCH_CHIDX_Msk (0xFFUL << RADIO_PUBLISH_DEVMATCH_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ @@ -6555,7 +6246,7 @@ POSSIBILITY OF SUCH DAMAGE. #define RADIO_PUBLISH_DEVMISS_EN_Disabled (0UL) /*!< Disable publishing */ #define RADIO_PUBLISH_DEVMISS_EN_Enabled (1UL) /*!< Enable publishing */ -/* Bits 7..0 : Channel that event DEVMISS will publish to. */ +/* Bits 7..0 : DPPI channel that event DEVMISS will publish to. */ #define RADIO_PUBLISH_DEVMISS_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ #define RADIO_PUBLISH_DEVMISS_CHIDX_Msk (0xFFUL << RADIO_PUBLISH_DEVMISS_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ @@ -6568,7 +6259,7 @@ POSSIBILITY OF SUCH DAMAGE. #define RADIO_PUBLISH_RSSIEND_EN_Disabled (0UL) /*!< Disable publishing */ #define RADIO_PUBLISH_RSSIEND_EN_Enabled (1UL) /*!< Enable publishing */ -/* Bits 7..0 : Channel that event RSSIEND will publish to. */ +/* Bits 7..0 : DPPI channel that event RSSIEND will publish to. */ #define RADIO_PUBLISH_RSSIEND_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ #define RADIO_PUBLISH_RSSIEND_CHIDX_Msk (0xFFUL << RADIO_PUBLISH_RSSIEND_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ @@ -6581,7 +6272,7 @@ POSSIBILITY OF SUCH DAMAGE. #define RADIO_PUBLISH_BCMATCH_EN_Disabled (0UL) /*!< Disable publishing */ #define RADIO_PUBLISH_BCMATCH_EN_Enabled (1UL) /*!< Enable publishing */ -/* Bits 7..0 : Channel that event BCMATCH will publish to. */ +/* Bits 7..0 : DPPI channel that event BCMATCH will publish to. */ #define RADIO_PUBLISH_BCMATCH_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ #define RADIO_PUBLISH_BCMATCH_CHIDX_Msk (0xFFUL << RADIO_PUBLISH_BCMATCH_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ @@ -6594,7 +6285,7 @@ POSSIBILITY OF SUCH DAMAGE. #define RADIO_PUBLISH_CRCOK_EN_Disabled (0UL) /*!< Disable publishing */ #define RADIO_PUBLISH_CRCOK_EN_Enabled (1UL) /*!< Enable publishing */ -/* Bits 7..0 : Channel that event CRCOK will publish to. */ +/* Bits 7..0 : DPPI channel that event CRCOK will publish to. */ #define RADIO_PUBLISH_CRCOK_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ #define RADIO_PUBLISH_CRCOK_CHIDX_Msk (0xFFUL << RADIO_PUBLISH_CRCOK_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ @@ -6607,7 +6298,7 @@ POSSIBILITY OF SUCH DAMAGE. #define RADIO_PUBLISH_CRCERROR_EN_Disabled (0UL) /*!< Disable publishing */ #define RADIO_PUBLISH_CRCERROR_EN_Enabled (1UL) /*!< Enable publishing */ -/* Bits 7..0 : Channel that event CRCERROR will publish to. */ +/* Bits 7..0 : DPPI channel that event CRCERROR will publish to. */ #define RADIO_PUBLISH_CRCERROR_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ #define RADIO_PUBLISH_CRCERROR_CHIDX_Msk (0xFFUL << RADIO_PUBLISH_CRCERROR_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ @@ -6620,7 +6311,7 @@ POSSIBILITY OF SUCH DAMAGE. #define RADIO_PUBLISH_FRAMESTART_EN_Disabled (0UL) /*!< Disable publishing */ #define RADIO_PUBLISH_FRAMESTART_EN_Enabled (1UL) /*!< Enable publishing */ -/* Bits 7..0 : Channel that event FRAMESTART will publish to. */ +/* Bits 7..0 : DPPI channel that event FRAMESTART will publish to. */ #define RADIO_PUBLISH_FRAMESTART_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ #define RADIO_PUBLISH_FRAMESTART_CHIDX_Msk (0xFFUL << RADIO_PUBLISH_FRAMESTART_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ @@ -6633,7 +6324,7 @@ POSSIBILITY OF SUCH DAMAGE. #define RADIO_PUBLISH_EDEND_EN_Disabled (0UL) /*!< Disable publishing */ #define RADIO_PUBLISH_EDEND_EN_Enabled (1UL) /*!< Enable publishing */ -/* Bits 7..0 : Channel that event EDEND will publish to. */ +/* Bits 7..0 : DPPI channel that event EDEND will publish to. */ #define RADIO_PUBLISH_EDEND_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ #define RADIO_PUBLISH_EDEND_CHIDX_Msk (0xFFUL << RADIO_PUBLISH_EDEND_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ @@ -6646,7 +6337,7 @@ POSSIBILITY OF SUCH DAMAGE. #define RADIO_PUBLISH_EDSTOPPED_EN_Disabled (0UL) /*!< Disable publishing */ #define RADIO_PUBLISH_EDSTOPPED_EN_Enabled (1UL) /*!< Enable publishing */ -/* Bits 7..0 : Channel that event EDSTOPPED will publish to. */ +/* Bits 7..0 : DPPI channel that event EDSTOPPED will publish to. */ #define RADIO_PUBLISH_EDSTOPPED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ #define RADIO_PUBLISH_EDSTOPPED_CHIDX_Msk (0xFFUL << RADIO_PUBLISH_EDSTOPPED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ @@ -6659,7 +6350,7 @@ POSSIBILITY OF SUCH DAMAGE. #define RADIO_PUBLISH_CCAIDLE_EN_Disabled (0UL) /*!< Disable publishing */ #define RADIO_PUBLISH_CCAIDLE_EN_Enabled (1UL) /*!< Enable publishing */ -/* Bits 7..0 : Channel that event CCAIDLE will publish to. */ +/* Bits 7..0 : DPPI channel that event CCAIDLE will publish to. */ #define RADIO_PUBLISH_CCAIDLE_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ #define RADIO_PUBLISH_CCAIDLE_CHIDX_Msk (0xFFUL << RADIO_PUBLISH_CCAIDLE_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ @@ -6672,7 +6363,7 @@ POSSIBILITY OF SUCH DAMAGE. #define RADIO_PUBLISH_CCABUSY_EN_Disabled (0UL) /*!< Disable publishing */ #define RADIO_PUBLISH_CCABUSY_EN_Enabled (1UL) /*!< Enable publishing */ -/* Bits 7..0 : Channel that event CCABUSY will publish to. */ +/* Bits 7..0 : DPPI channel that event CCABUSY will publish to. */ #define RADIO_PUBLISH_CCABUSY_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ #define RADIO_PUBLISH_CCABUSY_CHIDX_Msk (0xFFUL << RADIO_PUBLISH_CCABUSY_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ @@ -6685,7 +6376,7 @@ POSSIBILITY OF SUCH DAMAGE. #define RADIO_PUBLISH_CCASTOPPED_EN_Disabled (0UL) /*!< Disable publishing */ #define RADIO_PUBLISH_CCASTOPPED_EN_Enabled (1UL) /*!< Enable publishing */ -/* Bits 7..0 : Channel that event CCASTOPPED will publish to. */ +/* Bits 7..0 : DPPI channel that event CCASTOPPED will publish to. */ #define RADIO_PUBLISH_CCASTOPPED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ #define RADIO_PUBLISH_CCASTOPPED_CHIDX_Msk (0xFFUL << RADIO_PUBLISH_CCASTOPPED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ @@ -6698,7 +6389,7 @@ POSSIBILITY OF SUCH DAMAGE. #define RADIO_PUBLISH_RATEBOOST_EN_Disabled (0UL) /*!< Disable publishing */ #define RADIO_PUBLISH_RATEBOOST_EN_Enabled (1UL) /*!< Enable publishing */ -/* Bits 7..0 : Channel that event RATEBOOST will publish to. */ +/* Bits 7..0 : DPPI channel that event RATEBOOST will publish to. */ #define RADIO_PUBLISH_RATEBOOST_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ #define RADIO_PUBLISH_RATEBOOST_CHIDX_Msk (0xFFUL << RADIO_PUBLISH_RATEBOOST_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ @@ -6711,7 +6402,7 @@ POSSIBILITY OF SUCH DAMAGE. #define RADIO_PUBLISH_TXREADY_EN_Disabled (0UL) /*!< Disable publishing */ #define RADIO_PUBLISH_TXREADY_EN_Enabled (1UL) /*!< Enable publishing */ -/* Bits 7..0 : Channel that event TXREADY will publish to. */ +/* Bits 7..0 : DPPI channel that event TXREADY will publish to. */ #define RADIO_PUBLISH_TXREADY_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ #define RADIO_PUBLISH_TXREADY_CHIDX_Msk (0xFFUL << RADIO_PUBLISH_TXREADY_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ @@ -6724,7 +6415,7 @@ POSSIBILITY OF SUCH DAMAGE. #define RADIO_PUBLISH_RXREADY_EN_Disabled (0UL) /*!< Disable publishing */ #define RADIO_PUBLISH_RXREADY_EN_Enabled (1UL) /*!< Enable publishing */ -/* Bits 7..0 : Channel that event RXREADY will publish to. */ +/* Bits 7..0 : DPPI channel that event RXREADY will publish to. */ #define RADIO_PUBLISH_RXREADY_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ #define RADIO_PUBLISH_RXREADY_CHIDX_Msk (0xFFUL << RADIO_PUBLISH_RXREADY_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ @@ -6737,10 +6428,23 @@ POSSIBILITY OF SUCH DAMAGE. #define RADIO_PUBLISH_MHRMATCH_EN_Disabled (0UL) /*!< Disable publishing */ #define RADIO_PUBLISH_MHRMATCH_EN_Enabled (1UL) /*!< Enable publishing */ -/* Bits 7..0 : Channel that event MHRMATCH will publish to. */ +/* Bits 7..0 : DPPI channel that event MHRMATCH will publish to. */ #define RADIO_PUBLISH_MHRMATCH_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ #define RADIO_PUBLISH_MHRMATCH_CHIDX_Msk (0xFFUL << RADIO_PUBLISH_MHRMATCH_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ +/* Register: RADIO_PUBLISH_SYNC */ +/* Description: Publish configuration for event SYNC */ + +/* Bit 31 : */ +#define RADIO_PUBLISH_SYNC_EN_Pos (31UL) /*!< Position of EN field. */ +#define RADIO_PUBLISH_SYNC_EN_Msk (0x1UL << RADIO_PUBLISH_SYNC_EN_Pos) /*!< Bit mask of EN field. */ +#define RADIO_PUBLISH_SYNC_EN_Disabled (0UL) /*!< Disable publishing */ +#define RADIO_PUBLISH_SYNC_EN_Enabled (1UL) /*!< Enable publishing */ + +/* Bits 7..0 : DPPI channel that event SYNC will publish to. */ +#define RADIO_PUBLISH_SYNC_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ +#define RADIO_PUBLISH_SYNC_CHIDX_Msk (0xFFUL << RADIO_PUBLISH_SYNC_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + /* Register: RADIO_PUBLISH_PHYEND */ /* Description: Publish configuration for event PHYEND */ @@ -6750,7 +6454,7 @@ POSSIBILITY OF SUCH DAMAGE. #define RADIO_PUBLISH_PHYEND_EN_Disabled (0UL) /*!< Disable publishing */ #define RADIO_PUBLISH_PHYEND_EN_Enabled (1UL) /*!< Enable publishing */ -/* Bits 7..0 : Channel that event PHYEND will publish to. */ +/* Bits 7..0 : DPPI channel that event PHYEND will publish to. */ #define RADIO_PUBLISH_PHYEND_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ #define RADIO_PUBLISH_PHYEND_CHIDX_Msk (0xFFUL << RADIO_PUBLISH_PHYEND_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ @@ -6763,7 +6467,7 @@ POSSIBILITY OF SUCH DAMAGE. #define RADIO_PUBLISH_CTEPRESENT_EN_Disabled (0UL) /*!< Disable publishing */ #define RADIO_PUBLISH_CTEPRESENT_EN_Enabled (1UL) /*!< Enable publishing */ -/* Bits 7..0 : Channel that event CTEPRESENT will publish to. */ +/* Bits 7..0 : DPPI channel that event CTEPRESENT will publish to. */ #define RADIO_PUBLISH_CTEPRESENT_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ #define RADIO_PUBLISH_CTEPRESENT_CHIDX_Msk (0xFFUL << RADIO_PUBLISH_CTEPRESENT_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ @@ -6901,6 +6605,13 @@ POSSIBILITY OF SUCH DAMAGE. #define RADIO_INTENSET_PHYEND_Enabled (1UL) /*!< Read: Enabled */ #define RADIO_INTENSET_PHYEND_Set (1UL) /*!< Enable */ +/* Bit 26 : Write '1' to enable interrupt for event SYNC */ +#define RADIO_INTENSET_SYNC_Pos (26UL) /*!< Position of SYNC field. */ +#define RADIO_INTENSET_SYNC_Msk (0x1UL << RADIO_INTENSET_SYNC_Pos) /*!< Bit mask of SYNC field. */ +#define RADIO_INTENSET_SYNC_Disabled (0UL) /*!< Read: Disabled */ +#define RADIO_INTENSET_SYNC_Enabled (1UL) /*!< Read: Enabled */ +#define RADIO_INTENSET_SYNC_Set (1UL) /*!< Enable */ + /* Bit 23 : Write '1' to enable interrupt for event MHRMATCH */ #define RADIO_INTENSET_MHRMATCH_Pos (23UL) /*!< Position of MHRMATCH field. */ #define RADIO_INTENSET_MHRMATCH_Msk (0x1UL << RADIO_INTENSET_MHRMATCH_Pos) /*!< Bit mask of MHRMATCH field. */ @@ -7065,6 +6776,13 @@ POSSIBILITY OF SUCH DAMAGE. #define RADIO_INTENCLR_PHYEND_Enabled (1UL) /*!< Read: Enabled */ #define RADIO_INTENCLR_PHYEND_Clear (1UL) /*!< Disable */ +/* Bit 26 : Write '1' to disable interrupt for event SYNC */ +#define RADIO_INTENCLR_SYNC_Pos (26UL) /*!< Position of SYNC field. */ +#define RADIO_INTENCLR_SYNC_Msk (0x1UL << RADIO_INTENCLR_SYNC_Pos) /*!< Bit mask of SYNC field. */ +#define RADIO_INTENCLR_SYNC_Disabled (0UL) /*!< Read: Disabled */ +#define RADIO_INTENCLR_SYNC_Enabled (1UL) /*!< Read: Enabled */ +#define RADIO_INTENCLR_SYNC_Clear (1UL) /*!< Disable */ + /* Bit 23 : Write '1' to disable interrupt for event MHRMATCH */ #define RADIO_INTENCLR_MHRMATCH_Pos (23UL) /*!< Position of MHRMATCH field. */ #define RADIO_INTENCLR_MHRMATCH_Msk (0x1UL << RADIO_INTENCLR_MHRMATCH_Pos) /*!< Bit mask of MHRMATCH field. */ @@ -7847,7 +7565,7 @@ POSSIBILITY OF SUCH DAMAGE. #define RADIO_DFECTRL1_AGCBACKOFFGAIN_Pos (24UL) /*!< Position of AGCBACKOFFGAIN field. */ #define RADIO_DFECTRL1_AGCBACKOFFGAIN_Msk (0xFUL << RADIO_DFECTRL1_AGCBACKOFFGAIN_Pos) /*!< Bit mask of AGCBACKOFFGAIN field. */ -/* Bits 23..20 : Repeat every antenna pattern N times. */ +/* Bits 23..20 : Repeat each individual antenna pattern N times sequentially, i.e. P0, P0, P1, P1, P2, P2, P3, P3, etc. */ #define RADIO_DFECTRL1_REPEATPATTERN_Pos (20UL) /*!< Position of REPEATPATTERN field. */ #define RADIO_DFECTRL1_REPEATPATTERN_Msk (0xFUL << RADIO_DFECTRL1_REPEATPATTERN_Pos) /*!< Bit mask of REPEATPATTERN field. */ #define RADIO_DFECTRL1_REPEATPATTERN_NoRepeat (0UL) /*!< Do not repeat (1 time in total) */ @@ -7999,7 +7717,7 @@ POSSIBILITY OF SUCH DAMAGE. #define RESET_RESETREAS_NFC_NotDetected (0UL) /*!< Not detected */ #define RESET_RESETREAS_NFC_Detected (1UL) /*!< Detected */ -/* Bit 23 : Force off reset from application core detected */ +/* Bit 23 : Force-OFF reset from application core detected */ #define RESET_RESETREAS_MFORCEOFF_Pos (23UL) /*!< Position of MFORCEOFF field. */ #define RESET_RESETREAS_MFORCEOFF_Msk (0x1UL << RESET_RESETREAS_MFORCEOFF_Pos) /*!< Bit mask of MFORCEOFF field. */ #define RESET_RESETREAS_MFORCEOFF_NotDetected (0UL) /*!< Not detected */ @@ -8023,7 +7741,7 @@ POSSIBILITY OF SUCH DAMAGE. #define RESET_RESETREAS_LSREQ_NotDetected (0UL) /*!< Not detected */ #define RESET_RESETREAS_LSREQ_Detected (1UL) /*!< Detected */ -/* Bit 7 : Reset due to wakeup from System OFF mode when wakeup is triggered by entering the debug interface mode */ +/* Bit 7 : Reset due to wakeup from System OFF mode when wakeup is triggered by entering the Debug Interface mode */ #define RESET_RESETREAS_DIF_Pos (7UL) /*!< Position of DIF field. */ #define RESET_RESETREAS_DIF_Msk (0x1UL << RESET_RESETREAS_DIF_Pos) /*!< Bit mask of DIF field. */ #define RESET_RESETREAS_DIF_NotDetected (0UL) /*!< Not detected */ @@ -8071,15 +7789,6 @@ POSSIBILITY OF SUCH DAMAGE. #define RESET_RESETREAS_RESETPIN_NotDetected (0UL) /*!< Not detected */ #define RESET_RESETREAS_RESETPIN_Detected (1UL) /*!< Detected */ -/* Register: RESET_NETWORK_FORCEOFF */ -/* Description: Force off power and clock in network core */ - -/* Bit 0 : Force off power and clock in network core */ -#define RESET_NETWORK_FORCEOFF_FORCEOFF_Pos (0UL) /*!< Position of FORCEOFF field. */ -#define RESET_NETWORK_FORCEOFF_FORCEOFF_Msk (0x1UL << RESET_NETWORK_FORCEOFF_FORCEOFF_Pos) /*!< Bit mask of FORCEOFF field. */ -#define RESET_NETWORK_FORCEOFF_FORCEOFF_Release (0UL) /*!< Release force off signal */ -#define RESET_NETWORK_FORCEOFF_FORCEOFF_Hold (1UL) /*!< Hold force off signal */ - /* Peripheral: RNG */ /* Description: Random Number Generator */ @@ -8109,7 +7818,7 @@ POSSIBILITY OF SUCH DAMAGE. #define RNG_SUBSCRIBE_START_EN_Disabled (0UL) /*!< Disable subscription */ #define RNG_SUBSCRIBE_START_EN_Enabled (1UL) /*!< Enable subscription */ -/* Bits 7..0 : Channel that task START will subscribe to */ +/* Bits 7..0 : DPPI channel that task START will subscribe to */ #define RNG_SUBSCRIBE_START_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ #define RNG_SUBSCRIBE_START_CHIDX_Msk (0xFFUL << RNG_SUBSCRIBE_START_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ @@ -8122,7 +7831,7 @@ POSSIBILITY OF SUCH DAMAGE. #define RNG_SUBSCRIBE_STOP_EN_Disabled (0UL) /*!< Disable subscription */ #define RNG_SUBSCRIBE_STOP_EN_Enabled (1UL) /*!< Enable subscription */ -/* Bits 7..0 : Channel that task STOP will subscribe to */ +/* Bits 7..0 : DPPI channel that task STOP will subscribe to */ #define RNG_SUBSCRIBE_STOP_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ #define RNG_SUBSCRIBE_STOP_CHIDX_Msk (0xFFUL << RNG_SUBSCRIBE_STOP_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ @@ -8144,7 +7853,7 @@ POSSIBILITY OF SUCH DAMAGE. #define RNG_PUBLISH_VALRDY_EN_Disabled (0UL) /*!< Disable publishing */ #define RNG_PUBLISH_VALRDY_EN_Enabled (1UL) /*!< Enable publishing */ -/* Bits 7..0 : Channel that event VALRDY will publish to. */ +/* Bits 7..0 : DPPI channel that event VALRDY will publish to. */ #define RNG_PUBLISH_VALRDY_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ #define RNG_PUBLISH_VALRDY_CHIDX_Msk (0xFFUL << RNG_PUBLISH_VALRDY_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ @@ -8246,7 +7955,7 @@ POSSIBILITY OF SUCH DAMAGE. #define RTC_SUBSCRIBE_START_EN_Disabled (0UL) /*!< Disable subscription */ #define RTC_SUBSCRIBE_START_EN_Enabled (1UL) /*!< Enable subscription */ -/* Bits 7..0 : Channel that task START will subscribe to */ +/* Bits 7..0 : DPPI channel that task START will subscribe to */ #define RTC_SUBSCRIBE_START_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ #define RTC_SUBSCRIBE_START_CHIDX_Msk (0xFFUL << RTC_SUBSCRIBE_START_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ @@ -8259,7 +7968,7 @@ POSSIBILITY OF SUCH DAMAGE. #define RTC_SUBSCRIBE_STOP_EN_Disabled (0UL) /*!< Disable subscription */ #define RTC_SUBSCRIBE_STOP_EN_Enabled (1UL) /*!< Enable subscription */ -/* Bits 7..0 : Channel that task STOP will subscribe to */ +/* Bits 7..0 : DPPI channel that task STOP will subscribe to */ #define RTC_SUBSCRIBE_STOP_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ #define RTC_SUBSCRIBE_STOP_CHIDX_Msk (0xFFUL << RTC_SUBSCRIBE_STOP_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ @@ -8272,7 +7981,7 @@ POSSIBILITY OF SUCH DAMAGE. #define RTC_SUBSCRIBE_CLEAR_EN_Disabled (0UL) /*!< Disable subscription */ #define RTC_SUBSCRIBE_CLEAR_EN_Enabled (1UL) /*!< Enable subscription */ -/* Bits 7..0 : Channel that task CLEAR will subscribe to */ +/* Bits 7..0 : DPPI channel that task CLEAR will subscribe to */ #define RTC_SUBSCRIBE_CLEAR_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ #define RTC_SUBSCRIBE_CLEAR_CHIDX_Msk (0xFFUL << RTC_SUBSCRIBE_CLEAR_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ @@ -8285,7 +7994,7 @@ POSSIBILITY OF SUCH DAMAGE. #define RTC_SUBSCRIBE_TRIGOVRFLW_EN_Disabled (0UL) /*!< Disable subscription */ #define RTC_SUBSCRIBE_TRIGOVRFLW_EN_Enabled (1UL) /*!< Enable subscription */ -/* Bits 7..0 : Channel that task TRIGOVRFLW will subscribe to */ +/* Bits 7..0 : DPPI channel that task TRIGOVRFLW will subscribe to */ #define RTC_SUBSCRIBE_TRIGOVRFLW_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ #define RTC_SUBSCRIBE_TRIGOVRFLW_CHIDX_Msk (0xFFUL << RTC_SUBSCRIBE_TRIGOVRFLW_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ @@ -8298,7 +8007,7 @@ POSSIBILITY OF SUCH DAMAGE. #define RTC_SUBSCRIBE_CAPTURE_EN_Disabled (0UL) /*!< Disable subscription */ #define RTC_SUBSCRIBE_CAPTURE_EN_Enabled (1UL) /*!< Enable subscription */ -/* Bits 7..0 : Channel that task CAPTURE[n] will subscribe to */ +/* Bits 7..0 : DPPI channel that task CAPTURE[n] will subscribe to */ #define RTC_SUBSCRIBE_CAPTURE_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ #define RTC_SUBSCRIBE_CAPTURE_CHIDX_Msk (0xFFUL << RTC_SUBSCRIBE_CAPTURE_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ @@ -8338,7 +8047,7 @@ POSSIBILITY OF SUCH DAMAGE. #define RTC_PUBLISH_TICK_EN_Disabled (0UL) /*!< Disable publishing */ #define RTC_PUBLISH_TICK_EN_Enabled (1UL) /*!< Enable publishing */ -/* Bits 7..0 : Channel that event TICK will publish to. */ +/* Bits 7..0 : DPPI channel that event TICK will publish to. */ #define RTC_PUBLISH_TICK_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ #define RTC_PUBLISH_TICK_CHIDX_Msk (0xFFUL << RTC_PUBLISH_TICK_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ @@ -8351,7 +8060,7 @@ POSSIBILITY OF SUCH DAMAGE. #define RTC_PUBLISH_OVRFLW_EN_Disabled (0UL) /*!< Disable publishing */ #define RTC_PUBLISH_OVRFLW_EN_Enabled (1UL) /*!< Enable publishing */ -/* Bits 7..0 : Channel that event OVRFLW will publish to. */ +/* Bits 7..0 : DPPI channel that event OVRFLW will publish to. */ #define RTC_PUBLISH_OVRFLW_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ #define RTC_PUBLISH_OVRFLW_CHIDX_Msk (0xFFUL << RTC_PUBLISH_OVRFLW_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ @@ -8364,7 +8073,7 @@ POSSIBILITY OF SUCH DAMAGE. #define RTC_PUBLISH_COMPARE_EN_Disabled (0UL) /*!< Disable publishing */ #define RTC_PUBLISH_COMPARE_EN_Enabled (1UL) /*!< Enable publishing */ -/* Bits 7..0 : Channel that event COMPARE[n] will publish to. */ +/* Bits 7..0 : DPPI channel that event COMPARE[n] will publish to. */ #define RTC_PUBLISH_COMPARE_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ #define RTC_PUBLISH_COMPARE_CHIDX_Msk (0xFFUL << RTC_PUBLISH_COMPARE_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ @@ -8680,7 +8389,7 @@ POSSIBILITY OF SUCH DAMAGE. #define SPIM_SUBSCRIBE_START_EN_Disabled (0UL) /*!< Disable subscription */ #define SPIM_SUBSCRIBE_START_EN_Enabled (1UL) /*!< Enable subscription */ -/* Bits 7..0 : Channel that task START will subscribe to */ +/* Bits 7..0 : DPPI channel that task START will subscribe to */ #define SPIM_SUBSCRIBE_START_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ #define SPIM_SUBSCRIBE_START_CHIDX_Msk (0xFFUL << SPIM_SUBSCRIBE_START_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ @@ -8693,7 +8402,7 @@ POSSIBILITY OF SUCH DAMAGE. #define SPIM_SUBSCRIBE_STOP_EN_Disabled (0UL) /*!< Disable subscription */ #define SPIM_SUBSCRIBE_STOP_EN_Enabled (1UL) /*!< Enable subscription */ -/* Bits 7..0 : Channel that task STOP will subscribe to */ +/* Bits 7..0 : DPPI channel that task STOP will subscribe to */ #define SPIM_SUBSCRIBE_STOP_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ #define SPIM_SUBSCRIBE_STOP_CHIDX_Msk (0xFFUL << SPIM_SUBSCRIBE_STOP_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ @@ -8706,7 +8415,7 @@ POSSIBILITY OF SUCH DAMAGE. #define SPIM_SUBSCRIBE_SUSPEND_EN_Disabled (0UL) /*!< Disable subscription */ #define SPIM_SUBSCRIBE_SUSPEND_EN_Enabled (1UL) /*!< Enable subscription */ -/* Bits 7..0 : Channel that task SUSPEND will subscribe to */ +/* Bits 7..0 : DPPI channel that task SUSPEND will subscribe to */ #define SPIM_SUBSCRIBE_SUSPEND_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ #define SPIM_SUBSCRIBE_SUSPEND_CHIDX_Msk (0xFFUL << SPIM_SUBSCRIBE_SUSPEND_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ @@ -8719,7 +8428,7 @@ POSSIBILITY OF SUCH DAMAGE. #define SPIM_SUBSCRIBE_RESUME_EN_Disabled (0UL) /*!< Disable subscription */ #define SPIM_SUBSCRIBE_RESUME_EN_Enabled (1UL) /*!< Enable subscription */ -/* Bits 7..0 : Channel that task RESUME will subscribe to */ +/* Bits 7..0 : DPPI channel that task RESUME will subscribe to */ #define SPIM_SUBSCRIBE_RESUME_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ #define SPIM_SUBSCRIBE_RESUME_CHIDX_Msk (0xFFUL << SPIM_SUBSCRIBE_RESUME_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ @@ -8777,7 +8486,7 @@ POSSIBILITY OF SUCH DAMAGE. #define SPIM_PUBLISH_STOPPED_EN_Disabled (0UL) /*!< Disable publishing */ #define SPIM_PUBLISH_STOPPED_EN_Enabled (1UL) /*!< Enable publishing */ -/* Bits 7..0 : Channel that event STOPPED will publish to. */ +/* Bits 7..0 : DPPI channel that event STOPPED will publish to. */ #define SPIM_PUBLISH_STOPPED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ #define SPIM_PUBLISH_STOPPED_CHIDX_Msk (0xFFUL << SPIM_PUBLISH_STOPPED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ @@ -8790,7 +8499,7 @@ POSSIBILITY OF SUCH DAMAGE. #define SPIM_PUBLISH_ENDRX_EN_Disabled (0UL) /*!< Disable publishing */ #define SPIM_PUBLISH_ENDRX_EN_Enabled (1UL) /*!< Enable publishing */ -/* Bits 7..0 : Channel that event ENDRX will publish to. */ +/* Bits 7..0 : DPPI channel that event ENDRX will publish to. */ #define SPIM_PUBLISH_ENDRX_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ #define SPIM_PUBLISH_ENDRX_CHIDX_Msk (0xFFUL << SPIM_PUBLISH_ENDRX_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ @@ -8803,7 +8512,7 @@ POSSIBILITY OF SUCH DAMAGE. #define SPIM_PUBLISH_END_EN_Disabled (0UL) /*!< Disable publishing */ #define SPIM_PUBLISH_END_EN_Enabled (1UL) /*!< Enable publishing */ -/* Bits 7..0 : Channel that event END will publish to. */ +/* Bits 7..0 : DPPI channel that event END will publish to. */ #define SPIM_PUBLISH_END_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ #define SPIM_PUBLISH_END_CHIDX_Msk (0xFFUL << SPIM_PUBLISH_END_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ @@ -8816,7 +8525,7 @@ POSSIBILITY OF SUCH DAMAGE. #define SPIM_PUBLISH_ENDTX_EN_Disabled (0UL) /*!< Disable publishing */ #define SPIM_PUBLISH_ENDTX_EN_Enabled (1UL) /*!< Enable publishing */ -/* Bits 7..0 : Channel that event ENDTX will publish to. */ +/* Bits 7..0 : DPPI channel that event ENDTX will publish to. */ #define SPIM_PUBLISH_ENDTX_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ #define SPIM_PUBLISH_ENDTX_CHIDX_Msk (0xFFUL << SPIM_PUBLISH_ENDTX_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ @@ -8829,7 +8538,7 @@ POSSIBILITY OF SUCH DAMAGE. #define SPIM_PUBLISH_STARTED_EN_Disabled (0UL) /*!< Disable publishing */ #define SPIM_PUBLISH_STARTED_EN_Enabled (1UL) /*!< Enable publishing */ -/* Bits 7..0 : Channel that event STARTED will publish to. */ +/* Bits 7..0 : DPPI channel that event STARTED will publish to. */ #define SPIM_PUBLISH_STARTED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ #define SPIM_PUBLISH_STARTED_CHIDX_Msk (0xFFUL << SPIM_PUBLISH_STARTED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ @@ -9190,7 +8899,7 @@ POSSIBILITY OF SUCH DAMAGE. #define SPIS_SUBSCRIBE_ACQUIRE_EN_Disabled (0UL) /*!< Disable subscription */ #define SPIS_SUBSCRIBE_ACQUIRE_EN_Enabled (1UL) /*!< Enable subscription */ -/* Bits 7..0 : Channel that task ACQUIRE will subscribe to */ +/* Bits 7..0 : DPPI channel that task ACQUIRE will subscribe to */ #define SPIS_SUBSCRIBE_ACQUIRE_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ #define SPIS_SUBSCRIBE_ACQUIRE_CHIDX_Msk (0xFFUL << SPIS_SUBSCRIBE_ACQUIRE_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ @@ -9203,7 +8912,7 @@ POSSIBILITY OF SUCH DAMAGE. #define SPIS_SUBSCRIBE_RELEASE_EN_Disabled (0UL) /*!< Disable subscription */ #define SPIS_SUBSCRIBE_RELEASE_EN_Enabled (1UL) /*!< Enable subscription */ -/* Bits 7..0 : Channel that task RELEASE will subscribe to */ +/* Bits 7..0 : DPPI channel that task RELEASE will subscribe to */ #define SPIS_SUBSCRIBE_RELEASE_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ #define SPIS_SUBSCRIBE_RELEASE_CHIDX_Msk (0xFFUL << SPIS_SUBSCRIBE_RELEASE_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ @@ -9243,7 +8952,7 @@ POSSIBILITY OF SUCH DAMAGE. #define SPIS_PUBLISH_END_EN_Disabled (0UL) /*!< Disable publishing */ #define SPIS_PUBLISH_END_EN_Enabled (1UL) /*!< Enable publishing */ -/* Bits 7..0 : Channel that event END will publish to. */ +/* Bits 7..0 : DPPI channel that event END will publish to. */ #define SPIS_PUBLISH_END_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ #define SPIS_PUBLISH_END_CHIDX_Msk (0xFFUL << SPIS_PUBLISH_END_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ @@ -9256,7 +8965,7 @@ POSSIBILITY OF SUCH DAMAGE. #define SPIS_PUBLISH_ENDRX_EN_Disabled (0UL) /*!< Disable publishing */ #define SPIS_PUBLISH_ENDRX_EN_Enabled (1UL) /*!< Enable publishing */ -/* Bits 7..0 : Channel that event ENDRX will publish to. */ +/* Bits 7..0 : DPPI channel that event ENDRX will publish to. */ #define SPIS_PUBLISH_ENDRX_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ #define SPIS_PUBLISH_ENDRX_CHIDX_Msk (0xFFUL << SPIS_PUBLISH_ENDRX_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ @@ -9269,7 +8978,7 @@ POSSIBILITY OF SUCH DAMAGE. #define SPIS_PUBLISH_ACQUIRED_EN_Disabled (0UL) /*!< Disable publishing */ #define SPIS_PUBLISH_ACQUIRED_EN_Enabled (1UL) /*!< Enable publishing */ -/* Bits 7..0 : Channel that event ACQUIRED will publish to. */ +/* Bits 7..0 : DPPI channel that event ACQUIRED will publish to. */ #define SPIS_PUBLISH_ACQUIRED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ #define SPIS_PUBLISH_ACQUIRED_CHIDX_Msk (0xFFUL << SPIS_PUBLISH_ACQUIRED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ @@ -9559,7 +9268,7 @@ POSSIBILITY OF SUCH DAMAGE. #define TEMP_SUBSCRIBE_START_EN_Disabled (0UL) /*!< Disable subscription */ #define TEMP_SUBSCRIBE_START_EN_Enabled (1UL) /*!< Enable subscription */ -/* Bits 7..0 : Channel that task START will subscribe to */ +/* Bits 7..0 : DPPI channel that task START will subscribe to */ #define TEMP_SUBSCRIBE_START_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ #define TEMP_SUBSCRIBE_START_CHIDX_Msk (0xFFUL << TEMP_SUBSCRIBE_START_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ @@ -9572,7 +9281,7 @@ POSSIBILITY OF SUCH DAMAGE. #define TEMP_SUBSCRIBE_STOP_EN_Disabled (0UL) /*!< Disable subscription */ #define TEMP_SUBSCRIBE_STOP_EN_Enabled (1UL) /*!< Enable subscription */ -/* Bits 7..0 : Channel that task STOP will subscribe to */ +/* Bits 7..0 : DPPI channel that task STOP will subscribe to */ #define TEMP_SUBSCRIBE_STOP_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ #define TEMP_SUBSCRIBE_STOP_CHIDX_Msk (0xFFUL << TEMP_SUBSCRIBE_STOP_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ @@ -9594,7 +9303,7 @@ POSSIBILITY OF SUCH DAMAGE. #define TEMP_PUBLISH_DATARDY_EN_Disabled (0UL) /*!< Disable publishing */ #define TEMP_PUBLISH_DATARDY_EN_Enabled (1UL) /*!< Enable publishing */ -/* Bits 7..0 : Channel that event DATARDY will publish to. */ +/* Bits 7..0 : DPPI channel that event DATARDY will publish to. */ #define TEMP_PUBLISH_DATARDY_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ #define TEMP_PUBLISH_DATARDY_CHIDX_Msk (0xFFUL << TEMP_PUBLISH_DATARDY_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ @@ -9805,7 +9514,7 @@ POSSIBILITY OF SUCH DAMAGE. #define TIMER_SUBSCRIBE_START_EN_Disabled (0UL) /*!< Disable subscription */ #define TIMER_SUBSCRIBE_START_EN_Enabled (1UL) /*!< Enable subscription */ -/* Bits 7..0 : Channel that task START will subscribe to */ +/* Bits 7..0 : DPPI channel that task START will subscribe to */ #define TIMER_SUBSCRIBE_START_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ #define TIMER_SUBSCRIBE_START_CHIDX_Msk (0xFFUL << TIMER_SUBSCRIBE_START_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ @@ -9818,7 +9527,7 @@ POSSIBILITY OF SUCH DAMAGE. #define TIMER_SUBSCRIBE_STOP_EN_Disabled (0UL) /*!< Disable subscription */ #define TIMER_SUBSCRIBE_STOP_EN_Enabled (1UL) /*!< Enable subscription */ -/* Bits 7..0 : Channel that task STOP will subscribe to */ +/* Bits 7..0 : DPPI channel that task STOP will subscribe to */ #define TIMER_SUBSCRIBE_STOP_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ #define TIMER_SUBSCRIBE_STOP_CHIDX_Msk (0xFFUL << TIMER_SUBSCRIBE_STOP_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ @@ -9831,7 +9540,7 @@ POSSIBILITY OF SUCH DAMAGE. #define TIMER_SUBSCRIBE_COUNT_EN_Disabled (0UL) /*!< Disable subscription */ #define TIMER_SUBSCRIBE_COUNT_EN_Enabled (1UL) /*!< Enable subscription */ -/* Bits 7..0 : Channel that task COUNT will subscribe to */ +/* Bits 7..0 : DPPI channel that task COUNT will subscribe to */ #define TIMER_SUBSCRIBE_COUNT_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ #define TIMER_SUBSCRIBE_COUNT_CHIDX_Msk (0xFFUL << TIMER_SUBSCRIBE_COUNT_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ @@ -9844,7 +9553,7 @@ POSSIBILITY OF SUCH DAMAGE. #define TIMER_SUBSCRIBE_CLEAR_EN_Disabled (0UL) /*!< Disable subscription */ #define TIMER_SUBSCRIBE_CLEAR_EN_Enabled (1UL) /*!< Enable subscription */ -/* Bits 7..0 : Channel that task CLEAR will subscribe to */ +/* Bits 7..0 : DPPI channel that task CLEAR will subscribe to */ #define TIMER_SUBSCRIBE_CLEAR_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ #define TIMER_SUBSCRIBE_CLEAR_CHIDX_Msk (0xFFUL << TIMER_SUBSCRIBE_CLEAR_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ @@ -9857,7 +9566,7 @@ POSSIBILITY OF SUCH DAMAGE. #define TIMER_SUBSCRIBE_SHUTDOWN_EN_Disabled (0UL) /*!< Disable subscription */ #define TIMER_SUBSCRIBE_SHUTDOWN_EN_Enabled (1UL) /*!< Enable subscription */ -/* Bits 7..0 : Channel that task SHUTDOWN will subscribe to */ +/* Bits 7..0 : DPPI channel that task SHUTDOWN will subscribe to */ #define TIMER_SUBSCRIBE_SHUTDOWN_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ #define TIMER_SUBSCRIBE_SHUTDOWN_CHIDX_Msk (0xFFUL << TIMER_SUBSCRIBE_SHUTDOWN_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ @@ -9870,7 +9579,7 @@ POSSIBILITY OF SUCH DAMAGE. #define TIMER_SUBSCRIBE_CAPTURE_EN_Disabled (0UL) /*!< Disable subscription */ #define TIMER_SUBSCRIBE_CAPTURE_EN_Enabled (1UL) /*!< Enable subscription */ -/* Bits 7..0 : Channel that task CAPTURE[n] will subscribe to */ +/* Bits 7..0 : DPPI channel that task CAPTURE[n] will subscribe to */ #define TIMER_SUBSCRIBE_CAPTURE_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ #define TIMER_SUBSCRIBE_CAPTURE_CHIDX_Msk (0xFFUL << TIMER_SUBSCRIBE_CAPTURE_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ @@ -9892,7 +9601,7 @@ POSSIBILITY OF SUCH DAMAGE. #define TIMER_PUBLISH_COMPARE_EN_Disabled (0UL) /*!< Disable publishing */ #define TIMER_PUBLISH_COMPARE_EN_Enabled (1UL) /*!< Enable publishing */ -/* Bits 7..0 : Channel that event COMPARE[n] will publish to. */ +/* Bits 7..0 : DPPI channel that event COMPARE[n] will publish to. */ #define TIMER_PUBLISH_COMPARE_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ #define TIMER_PUBLISH_COMPARE_CHIDX_Msk (0xFFUL << TIMER_PUBLISH_COMPARE_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ @@ -10261,7 +9970,7 @@ POSSIBILITY OF SUCH DAMAGE. #define TWIM_SUBSCRIBE_STARTRX_EN_Disabled (0UL) /*!< Disable subscription */ #define TWIM_SUBSCRIBE_STARTRX_EN_Enabled (1UL) /*!< Enable subscription */ -/* Bits 7..0 : Channel that task STARTRX will subscribe to */ +/* Bits 7..0 : DPPI channel that task STARTRX will subscribe to */ #define TWIM_SUBSCRIBE_STARTRX_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ #define TWIM_SUBSCRIBE_STARTRX_CHIDX_Msk (0xFFUL << TWIM_SUBSCRIBE_STARTRX_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ @@ -10274,7 +9983,7 @@ POSSIBILITY OF SUCH DAMAGE. #define TWIM_SUBSCRIBE_STARTTX_EN_Disabled (0UL) /*!< Disable subscription */ #define TWIM_SUBSCRIBE_STARTTX_EN_Enabled (1UL) /*!< Enable subscription */ -/* Bits 7..0 : Channel that task STARTTX will subscribe to */ +/* Bits 7..0 : DPPI channel that task STARTTX will subscribe to */ #define TWIM_SUBSCRIBE_STARTTX_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ #define TWIM_SUBSCRIBE_STARTTX_CHIDX_Msk (0xFFUL << TWIM_SUBSCRIBE_STARTTX_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ @@ -10287,7 +9996,7 @@ POSSIBILITY OF SUCH DAMAGE. #define TWIM_SUBSCRIBE_STOP_EN_Disabled (0UL) /*!< Disable subscription */ #define TWIM_SUBSCRIBE_STOP_EN_Enabled (1UL) /*!< Enable subscription */ -/* Bits 7..0 : Channel that task STOP will subscribe to */ +/* Bits 7..0 : DPPI channel that task STOP will subscribe to */ #define TWIM_SUBSCRIBE_STOP_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ #define TWIM_SUBSCRIBE_STOP_CHIDX_Msk (0xFFUL << TWIM_SUBSCRIBE_STOP_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ @@ -10300,7 +10009,7 @@ POSSIBILITY OF SUCH DAMAGE. #define TWIM_SUBSCRIBE_SUSPEND_EN_Disabled (0UL) /*!< Disable subscription */ #define TWIM_SUBSCRIBE_SUSPEND_EN_Enabled (1UL) /*!< Enable subscription */ -/* Bits 7..0 : Channel that task SUSPEND will subscribe to */ +/* Bits 7..0 : DPPI channel that task SUSPEND will subscribe to */ #define TWIM_SUBSCRIBE_SUSPEND_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ #define TWIM_SUBSCRIBE_SUSPEND_CHIDX_Msk (0xFFUL << TWIM_SUBSCRIBE_SUSPEND_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ @@ -10313,7 +10022,7 @@ POSSIBILITY OF SUCH DAMAGE. #define TWIM_SUBSCRIBE_RESUME_EN_Disabled (0UL) /*!< Disable subscription */ #define TWIM_SUBSCRIBE_RESUME_EN_Enabled (1UL) /*!< Enable subscription */ -/* Bits 7..0 : Channel that task RESUME will subscribe to */ +/* Bits 7..0 : DPPI channel that task RESUME will subscribe to */ #define TWIM_SUBSCRIBE_RESUME_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ #define TWIM_SUBSCRIBE_RESUME_CHIDX_Msk (0xFFUL << TWIM_SUBSCRIBE_RESUME_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ @@ -10336,9 +10045,9 @@ POSSIBILITY OF SUCH DAMAGE. #define TWIM_EVENTS_ERROR_EVENTS_ERROR_Generated (1UL) /*!< Event generated */ /* Register: TWIM_EVENTS_SUSPENDED */ -/* Description: Last byte has been sent out after the SUSPEND task has been issued, TWI traffic is now suspended. */ +/* Description: SUSPEND task has been issued, TWI traffic is now suspended. */ -/* Bit 0 : Last byte has been sent out after the SUSPEND task has been issued, TWI traffic is now suspended. */ +/* Bit 0 : SUSPEND task has been issued, TWI traffic is now suspended. */ #define TWIM_EVENTS_SUSPENDED_EVENTS_SUSPENDED_Pos (0UL) /*!< Position of EVENTS_SUSPENDED field. */ #define TWIM_EVENTS_SUSPENDED_EVENTS_SUSPENDED_Msk (0x1UL << TWIM_EVENTS_SUSPENDED_EVENTS_SUSPENDED_Pos) /*!< Bit mask of EVENTS_SUSPENDED field. */ #define TWIM_EVENTS_SUSPENDED_EVENTS_SUSPENDED_NotGenerated (0UL) /*!< Event not generated */ @@ -10389,7 +10098,7 @@ POSSIBILITY OF SUCH DAMAGE. #define TWIM_PUBLISH_STOPPED_EN_Disabled (0UL) /*!< Disable publishing */ #define TWIM_PUBLISH_STOPPED_EN_Enabled (1UL) /*!< Enable publishing */ -/* Bits 7..0 : Channel that event STOPPED will publish to. */ +/* Bits 7..0 : DPPI channel that event STOPPED will publish to. */ #define TWIM_PUBLISH_STOPPED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ #define TWIM_PUBLISH_STOPPED_CHIDX_Msk (0xFFUL << TWIM_PUBLISH_STOPPED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ @@ -10402,7 +10111,7 @@ POSSIBILITY OF SUCH DAMAGE. #define TWIM_PUBLISH_ERROR_EN_Disabled (0UL) /*!< Disable publishing */ #define TWIM_PUBLISH_ERROR_EN_Enabled (1UL) /*!< Enable publishing */ -/* Bits 7..0 : Channel that event ERROR will publish to. */ +/* Bits 7..0 : DPPI channel that event ERROR will publish to. */ #define TWIM_PUBLISH_ERROR_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ #define TWIM_PUBLISH_ERROR_CHIDX_Msk (0xFFUL << TWIM_PUBLISH_ERROR_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ @@ -10415,7 +10124,7 @@ POSSIBILITY OF SUCH DAMAGE. #define TWIM_PUBLISH_SUSPENDED_EN_Disabled (0UL) /*!< Disable publishing */ #define TWIM_PUBLISH_SUSPENDED_EN_Enabled (1UL) /*!< Enable publishing */ -/* Bits 7..0 : Channel that event SUSPENDED will publish to. */ +/* Bits 7..0 : DPPI channel that event SUSPENDED will publish to. */ #define TWIM_PUBLISH_SUSPENDED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ #define TWIM_PUBLISH_SUSPENDED_CHIDX_Msk (0xFFUL << TWIM_PUBLISH_SUSPENDED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ @@ -10428,7 +10137,7 @@ POSSIBILITY OF SUCH DAMAGE. #define TWIM_PUBLISH_RXSTARTED_EN_Disabled (0UL) /*!< Disable publishing */ #define TWIM_PUBLISH_RXSTARTED_EN_Enabled (1UL) /*!< Enable publishing */ -/* Bits 7..0 : Channel that event RXSTARTED will publish to. */ +/* Bits 7..0 : DPPI channel that event RXSTARTED will publish to. */ #define TWIM_PUBLISH_RXSTARTED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ #define TWIM_PUBLISH_RXSTARTED_CHIDX_Msk (0xFFUL << TWIM_PUBLISH_RXSTARTED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ @@ -10441,7 +10150,7 @@ POSSIBILITY OF SUCH DAMAGE. #define TWIM_PUBLISH_TXSTARTED_EN_Disabled (0UL) /*!< Disable publishing */ #define TWIM_PUBLISH_TXSTARTED_EN_Enabled (1UL) /*!< Enable publishing */ -/* Bits 7..0 : Channel that event TXSTARTED will publish to. */ +/* Bits 7..0 : DPPI channel that event TXSTARTED will publish to. */ #define TWIM_PUBLISH_TXSTARTED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ #define TWIM_PUBLISH_TXSTARTED_CHIDX_Msk (0xFFUL << TWIM_PUBLISH_TXSTARTED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ @@ -10454,7 +10163,7 @@ POSSIBILITY OF SUCH DAMAGE. #define TWIM_PUBLISH_LASTRX_EN_Disabled (0UL) /*!< Disable publishing */ #define TWIM_PUBLISH_LASTRX_EN_Enabled (1UL) /*!< Enable publishing */ -/* Bits 7..0 : Channel that event LASTRX will publish to. */ +/* Bits 7..0 : DPPI channel that event LASTRX will publish to. */ #define TWIM_PUBLISH_LASTRX_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ #define TWIM_PUBLISH_LASTRX_CHIDX_Msk (0xFFUL << TWIM_PUBLISH_LASTRX_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ @@ -10467,7 +10176,7 @@ POSSIBILITY OF SUCH DAMAGE. #define TWIM_PUBLISH_LASTTX_EN_Disabled (0UL) /*!< Disable publishing */ #define TWIM_PUBLISH_LASTTX_EN_Enabled (1UL) /*!< Enable publishing */ -/* Bits 7..0 : Channel that event LASTTX will publish to. */ +/* Bits 7..0 : DPPI channel that event LASTTX will publish to. */ #define TWIM_PUBLISH_LASTTX_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ #define TWIM_PUBLISH_LASTTX_CHIDX_Msk (0xFFUL << TWIM_PUBLISH_LASTTX_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ @@ -10854,7 +10563,7 @@ POSSIBILITY OF SUCH DAMAGE. #define TWIS_SUBSCRIBE_STOP_EN_Disabled (0UL) /*!< Disable subscription */ #define TWIS_SUBSCRIBE_STOP_EN_Enabled (1UL) /*!< Enable subscription */ -/* Bits 7..0 : Channel that task STOP will subscribe to */ +/* Bits 7..0 : DPPI channel that task STOP will subscribe to */ #define TWIS_SUBSCRIBE_STOP_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ #define TWIS_SUBSCRIBE_STOP_CHIDX_Msk (0xFFUL << TWIS_SUBSCRIBE_STOP_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ @@ -10867,7 +10576,7 @@ POSSIBILITY OF SUCH DAMAGE. #define TWIS_SUBSCRIBE_SUSPEND_EN_Disabled (0UL) /*!< Disable subscription */ #define TWIS_SUBSCRIBE_SUSPEND_EN_Enabled (1UL) /*!< Enable subscription */ -/* Bits 7..0 : Channel that task SUSPEND will subscribe to */ +/* Bits 7..0 : DPPI channel that task SUSPEND will subscribe to */ #define TWIS_SUBSCRIBE_SUSPEND_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ #define TWIS_SUBSCRIBE_SUSPEND_CHIDX_Msk (0xFFUL << TWIS_SUBSCRIBE_SUSPEND_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ @@ -10880,7 +10589,7 @@ POSSIBILITY OF SUCH DAMAGE. #define TWIS_SUBSCRIBE_RESUME_EN_Disabled (0UL) /*!< Disable subscription */ #define TWIS_SUBSCRIBE_RESUME_EN_Enabled (1UL) /*!< Enable subscription */ -/* Bits 7..0 : Channel that task RESUME will subscribe to */ +/* Bits 7..0 : DPPI channel that task RESUME will subscribe to */ #define TWIS_SUBSCRIBE_RESUME_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ #define TWIS_SUBSCRIBE_RESUME_CHIDX_Msk (0xFFUL << TWIS_SUBSCRIBE_RESUME_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ @@ -10893,7 +10602,7 @@ POSSIBILITY OF SUCH DAMAGE. #define TWIS_SUBSCRIBE_PREPARERX_EN_Disabled (0UL) /*!< Disable subscription */ #define TWIS_SUBSCRIBE_PREPARERX_EN_Enabled (1UL) /*!< Enable subscription */ -/* Bits 7..0 : Channel that task PREPARERX will subscribe to */ +/* Bits 7..0 : DPPI channel that task PREPARERX will subscribe to */ #define TWIS_SUBSCRIBE_PREPARERX_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ #define TWIS_SUBSCRIBE_PREPARERX_CHIDX_Msk (0xFFUL << TWIS_SUBSCRIBE_PREPARERX_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ @@ -10906,7 +10615,7 @@ POSSIBILITY OF SUCH DAMAGE. #define TWIS_SUBSCRIBE_PREPARETX_EN_Disabled (0UL) /*!< Disable subscription */ #define TWIS_SUBSCRIBE_PREPARETX_EN_Enabled (1UL) /*!< Enable subscription */ -/* Bits 7..0 : Channel that task PREPARETX will subscribe to */ +/* Bits 7..0 : DPPI channel that task PREPARETX will subscribe to */ #define TWIS_SUBSCRIBE_PREPARETX_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ #define TWIS_SUBSCRIBE_PREPARETX_CHIDX_Msk (0xFFUL << TWIS_SUBSCRIBE_PREPARETX_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ @@ -10973,7 +10682,7 @@ POSSIBILITY OF SUCH DAMAGE. #define TWIS_PUBLISH_STOPPED_EN_Disabled (0UL) /*!< Disable publishing */ #define TWIS_PUBLISH_STOPPED_EN_Enabled (1UL) /*!< Enable publishing */ -/* Bits 7..0 : Channel that event STOPPED will publish to. */ +/* Bits 7..0 : DPPI channel that event STOPPED will publish to. */ #define TWIS_PUBLISH_STOPPED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ #define TWIS_PUBLISH_STOPPED_CHIDX_Msk (0xFFUL << TWIS_PUBLISH_STOPPED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ @@ -10986,7 +10695,7 @@ POSSIBILITY OF SUCH DAMAGE. #define TWIS_PUBLISH_ERROR_EN_Disabled (0UL) /*!< Disable publishing */ #define TWIS_PUBLISH_ERROR_EN_Enabled (1UL) /*!< Enable publishing */ -/* Bits 7..0 : Channel that event ERROR will publish to. */ +/* Bits 7..0 : DPPI channel that event ERROR will publish to. */ #define TWIS_PUBLISH_ERROR_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ #define TWIS_PUBLISH_ERROR_CHIDX_Msk (0xFFUL << TWIS_PUBLISH_ERROR_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ @@ -10999,7 +10708,7 @@ POSSIBILITY OF SUCH DAMAGE. #define TWIS_PUBLISH_RXSTARTED_EN_Disabled (0UL) /*!< Disable publishing */ #define TWIS_PUBLISH_RXSTARTED_EN_Enabled (1UL) /*!< Enable publishing */ -/* Bits 7..0 : Channel that event RXSTARTED will publish to. */ +/* Bits 7..0 : DPPI channel that event RXSTARTED will publish to. */ #define TWIS_PUBLISH_RXSTARTED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ #define TWIS_PUBLISH_RXSTARTED_CHIDX_Msk (0xFFUL << TWIS_PUBLISH_RXSTARTED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ @@ -11012,7 +10721,7 @@ POSSIBILITY OF SUCH DAMAGE. #define TWIS_PUBLISH_TXSTARTED_EN_Disabled (0UL) /*!< Disable publishing */ #define TWIS_PUBLISH_TXSTARTED_EN_Enabled (1UL) /*!< Enable publishing */ -/* Bits 7..0 : Channel that event TXSTARTED will publish to. */ +/* Bits 7..0 : DPPI channel that event TXSTARTED will publish to. */ #define TWIS_PUBLISH_TXSTARTED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ #define TWIS_PUBLISH_TXSTARTED_CHIDX_Msk (0xFFUL << TWIS_PUBLISH_TXSTARTED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ @@ -11025,7 +10734,7 @@ POSSIBILITY OF SUCH DAMAGE. #define TWIS_PUBLISH_WRITE_EN_Disabled (0UL) /*!< Disable publishing */ #define TWIS_PUBLISH_WRITE_EN_Enabled (1UL) /*!< Enable publishing */ -/* Bits 7..0 : Channel that event WRITE will publish to. */ +/* Bits 7..0 : DPPI channel that event WRITE will publish to. */ #define TWIS_PUBLISH_WRITE_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ #define TWIS_PUBLISH_WRITE_CHIDX_Msk (0xFFUL << TWIS_PUBLISH_WRITE_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ @@ -11038,7 +10747,7 @@ POSSIBILITY OF SUCH DAMAGE. #define TWIS_PUBLISH_READ_EN_Disabled (0UL) /*!< Disable publishing */ #define TWIS_PUBLISH_READ_EN_Enabled (1UL) /*!< Enable publishing */ -/* Bits 7..0 : Channel that event READ will publish to. */ +/* Bits 7..0 : DPPI channel that event READ will publish to. */ #define TWIS_PUBLISH_READ_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ #define TWIS_PUBLISH_READ_CHIDX_Msk (0xFFUL << TWIS_PUBLISH_READ_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ @@ -11399,7 +11108,7 @@ POSSIBILITY OF SUCH DAMAGE. #define UARTE_SUBSCRIBE_STARTRX_EN_Disabled (0UL) /*!< Disable subscription */ #define UARTE_SUBSCRIBE_STARTRX_EN_Enabled (1UL) /*!< Enable subscription */ -/* Bits 7..0 : Channel that task STARTRX will subscribe to */ +/* Bits 7..0 : DPPI channel that task STARTRX will subscribe to */ #define UARTE_SUBSCRIBE_STARTRX_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ #define UARTE_SUBSCRIBE_STARTRX_CHIDX_Msk (0xFFUL << UARTE_SUBSCRIBE_STARTRX_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ @@ -11412,7 +11121,7 @@ POSSIBILITY OF SUCH DAMAGE. #define UARTE_SUBSCRIBE_STOPRX_EN_Disabled (0UL) /*!< Disable subscription */ #define UARTE_SUBSCRIBE_STOPRX_EN_Enabled (1UL) /*!< Enable subscription */ -/* Bits 7..0 : Channel that task STOPRX will subscribe to */ +/* Bits 7..0 : DPPI channel that task STOPRX will subscribe to */ #define UARTE_SUBSCRIBE_STOPRX_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ #define UARTE_SUBSCRIBE_STOPRX_CHIDX_Msk (0xFFUL << UARTE_SUBSCRIBE_STOPRX_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ @@ -11425,7 +11134,7 @@ POSSIBILITY OF SUCH DAMAGE. #define UARTE_SUBSCRIBE_STARTTX_EN_Disabled (0UL) /*!< Disable subscription */ #define UARTE_SUBSCRIBE_STARTTX_EN_Enabled (1UL) /*!< Enable subscription */ -/* Bits 7..0 : Channel that task STARTTX will subscribe to */ +/* Bits 7..0 : DPPI channel that task STARTTX will subscribe to */ #define UARTE_SUBSCRIBE_STARTTX_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ #define UARTE_SUBSCRIBE_STARTTX_CHIDX_Msk (0xFFUL << UARTE_SUBSCRIBE_STARTTX_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ @@ -11438,7 +11147,7 @@ POSSIBILITY OF SUCH DAMAGE. #define UARTE_SUBSCRIBE_STOPTX_EN_Disabled (0UL) /*!< Disable subscription */ #define UARTE_SUBSCRIBE_STOPTX_EN_Enabled (1UL) /*!< Enable subscription */ -/* Bits 7..0 : Channel that task STOPTX will subscribe to */ +/* Bits 7..0 : DPPI channel that task STOPTX will subscribe to */ #define UARTE_SUBSCRIBE_STOPTX_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ #define UARTE_SUBSCRIBE_STOPTX_CHIDX_Msk (0xFFUL << UARTE_SUBSCRIBE_STOPTX_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ @@ -11451,7 +11160,7 @@ POSSIBILITY OF SUCH DAMAGE. #define UARTE_SUBSCRIBE_FLUSHRX_EN_Disabled (0UL) /*!< Disable subscription */ #define UARTE_SUBSCRIBE_FLUSHRX_EN_Enabled (1UL) /*!< Enable subscription */ -/* Bits 7..0 : Channel that task FLUSHRX will subscribe to */ +/* Bits 7..0 : DPPI channel that task FLUSHRX will subscribe to */ #define UARTE_SUBSCRIBE_FLUSHRX_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ #define UARTE_SUBSCRIBE_FLUSHRX_CHIDX_Msk (0xFFUL << UARTE_SUBSCRIBE_FLUSHRX_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ @@ -11563,7 +11272,7 @@ POSSIBILITY OF SUCH DAMAGE. #define UARTE_PUBLISH_CTS_EN_Disabled (0UL) /*!< Disable publishing */ #define UARTE_PUBLISH_CTS_EN_Enabled (1UL) /*!< Enable publishing */ -/* Bits 7..0 : Channel that event CTS will publish to. */ +/* Bits 7..0 : DPPI channel that event CTS will publish to. */ #define UARTE_PUBLISH_CTS_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ #define UARTE_PUBLISH_CTS_CHIDX_Msk (0xFFUL << UARTE_PUBLISH_CTS_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ @@ -11576,7 +11285,7 @@ POSSIBILITY OF SUCH DAMAGE. #define UARTE_PUBLISH_NCTS_EN_Disabled (0UL) /*!< Disable publishing */ #define UARTE_PUBLISH_NCTS_EN_Enabled (1UL) /*!< Enable publishing */ -/* Bits 7..0 : Channel that event NCTS will publish to. */ +/* Bits 7..0 : DPPI channel that event NCTS will publish to. */ #define UARTE_PUBLISH_NCTS_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ #define UARTE_PUBLISH_NCTS_CHIDX_Msk (0xFFUL << UARTE_PUBLISH_NCTS_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ @@ -11589,7 +11298,7 @@ POSSIBILITY OF SUCH DAMAGE. #define UARTE_PUBLISH_RXDRDY_EN_Disabled (0UL) /*!< Disable publishing */ #define UARTE_PUBLISH_RXDRDY_EN_Enabled (1UL) /*!< Enable publishing */ -/* Bits 7..0 : Channel that event RXDRDY will publish to. */ +/* Bits 7..0 : DPPI channel that event RXDRDY will publish to. */ #define UARTE_PUBLISH_RXDRDY_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ #define UARTE_PUBLISH_RXDRDY_CHIDX_Msk (0xFFUL << UARTE_PUBLISH_RXDRDY_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ @@ -11602,7 +11311,7 @@ POSSIBILITY OF SUCH DAMAGE. #define UARTE_PUBLISH_ENDRX_EN_Disabled (0UL) /*!< Disable publishing */ #define UARTE_PUBLISH_ENDRX_EN_Enabled (1UL) /*!< Enable publishing */ -/* Bits 7..0 : Channel that event ENDRX will publish to. */ +/* Bits 7..0 : DPPI channel that event ENDRX will publish to. */ #define UARTE_PUBLISH_ENDRX_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ #define UARTE_PUBLISH_ENDRX_CHIDX_Msk (0xFFUL << UARTE_PUBLISH_ENDRX_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ @@ -11615,7 +11324,7 @@ POSSIBILITY OF SUCH DAMAGE. #define UARTE_PUBLISH_TXDRDY_EN_Disabled (0UL) /*!< Disable publishing */ #define UARTE_PUBLISH_TXDRDY_EN_Enabled (1UL) /*!< Enable publishing */ -/* Bits 7..0 : Channel that event TXDRDY will publish to. */ +/* Bits 7..0 : DPPI channel that event TXDRDY will publish to. */ #define UARTE_PUBLISH_TXDRDY_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ #define UARTE_PUBLISH_TXDRDY_CHIDX_Msk (0xFFUL << UARTE_PUBLISH_TXDRDY_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ @@ -11628,7 +11337,7 @@ POSSIBILITY OF SUCH DAMAGE. #define UARTE_PUBLISH_ENDTX_EN_Disabled (0UL) /*!< Disable publishing */ #define UARTE_PUBLISH_ENDTX_EN_Enabled (1UL) /*!< Enable publishing */ -/* Bits 7..0 : Channel that event ENDTX will publish to. */ +/* Bits 7..0 : DPPI channel that event ENDTX will publish to. */ #define UARTE_PUBLISH_ENDTX_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ #define UARTE_PUBLISH_ENDTX_CHIDX_Msk (0xFFUL << UARTE_PUBLISH_ENDTX_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ @@ -11641,7 +11350,7 @@ POSSIBILITY OF SUCH DAMAGE. #define UARTE_PUBLISH_ERROR_EN_Disabled (0UL) /*!< Disable publishing */ #define UARTE_PUBLISH_ERROR_EN_Enabled (1UL) /*!< Enable publishing */ -/* Bits 7..0 : Channel that event ERROR will publish to. */ +/* Bits 7..0 : DPPI channel that event ERROR will publish to. */ #define UARTE_PUBLISH_ERROR_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ #define UARTE_PUBLISH_ERROR_CHIDX_Msk (0xFFUL << UARTE_PUBLISH_ERROR_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ @@ -11654,7 +11363,7 @@ POSSIBILITY OF SUCH DAMAGE. #define UARTE_PUBLISH_RXTO_EN_Disabled (0UL) /*!< Disable publishing */ #define UARTE_PUBLISH_RXTO_EN_Enabled (1UL) /*!< Enable publishing */ -/* Bits 7..0 : Channel that event RXTO will publish to. */ +/* Bits 7..0 : DPPI channel that event RXTO will publish to. */ #define UARTE_PUBLISH_RXTO_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ #define UARTE_PUBLISH_RXTO_CHIDX_Msk (0xFFUL << UARTE_PUBLISH_RXTO_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ @@ -11667,7 +11376,7 @@ POSSIBILITY OF SUCH DAMAGE. #define UARTE_PUBLISH_RXSTARTED_EN_Disabled (0UL) /*!< Disable publishing */ #define UARTE_PUBLISH_RXSTARTED_EN_Enabled (1UL) /*!< Enable publishing */ -/* Bits 7..0 : Channel that event RXSTARTED will publish to. */ +/* Bits 7..0 : DPPI channel that event RXSTARTED will publish to. */ #define UARTE_PUBLISH_RXSTARTED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ #define UARTE_PUBLISH_RXSTARTED_CHIDX_Msk (0xFFUL << UARTE_PUBLISH_RXSTARTED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ @@ -11680,7 +11389,7 @@ POSSIBILITY OF SUCH DAMAGE. #define UARTE_PUBLISH_TXSTARTED_EN_Disabled (0UL) /*!< Disable publishing */ #define UARTE_PUBLISH_TXSTARTED_EN_Enabled (1UL) /*!< Enable publishing */ -/* Bits 7..0 : Channel that event TXSTARTED will publish to. */ +/* Bits 7..0 : DPPI channel that event TXSTARTED will publish to. */ #define UARTE_PUBLISH_TXSTARTED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ #define UARTE_PUBLISH_TXSTARTED_CHIDX_Msk (0xFFUL << UARTE_PUBLISH_TXSTARTED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ @@ -11693,7 +11402,7 @@ POSSIBILITY OF SUCH DAMAGE. #define UARTE_PUBLISH_TXSTOPPED_EN_Disabled (0UL) /*!< Disable publishing */ #define UARTE_PUBLISH_TXSTOPPED_EN_Enabled (1UL) /*!< Enable publishing */ -/* Bits 7..0 : Channel that event TXSTOPPED will publish to. */ +/* Bits 7..0 : DPPI channel that event TXSTOPPED will publish to. */ #define UARTE_PUBLISH_TXSTOPPED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ #define UARTE_PUBLISH_TXSTOPPED_CHIDX_Msk (0xFFUL << UARTE_PUBLISH_TXSTOPPED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ @@ -12147,7 +11856,7 @@ POSSIBILITY OF SUCH DAMAGE. /* Description: Access port protection */ /* Bits 31..0 : Blocks debugger read/write access to all CPU registers and memory mapped - addresses Any value except for the enumerations will yield unexpected results. */ + addresses Using any value except Unprotected will lead to the protection being enabled. */ #define UICR_APPROTECT_PALL_Pos (0UL) /*!< Position of PALL field. */ #define UICR_APPROTECT_PALL_Msk (0xFFFFFFFFUL << UICR_APPROTECT_PALL_Pos) /*!< Bit mask of PALL field. */ #define UICR_APPROTECT_PALL_Protected (0x00000000UL) /*!< Protected */ @@ -12156,7 +11865,7 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: UICR_ERASEPROTECT */ /* Description: Erase protection */ -/* Bits 31..0 : Blocks NVMC ERASEALL and CTRLAP ERASEALL functionality. Any value except for the enumerations will yield unexpected results. */ +/* Bits 31..0 : Blocks NVMC ERASEALL and CTRLAP ERASEALL functionality. Using any value except Unprotected will lead to the protection being enabled. */ #define UICR_ERASEPROTECT_PALL_Pos (0UL) /*!< Position of PALL field. */ #define UICR_ERASEPROTECT_PALL_Msk (0xFFFFFFFFUL << UICR_ERASEPROTECT_PALL_Pos) /*!< Bit mask of PALL field. */ #define UICR_ERASEPROTECT_PALL_Protected (0x00000000UL) /*!< Protected */ @@ -12368,7 +12077,7 @@ POSSIBILITY OF SUCH DAMAGE. #define WDT_SUBSCRIBE_START_EN_Disabled (0UL) /*!< Disable subscription */ #define WDT_SUBSCRIBE_START_EN_Enabled (1UL) /*!< Enable subscription */ -/* Bits 7..0 : Channel that task START will subscribe to */ +/* Bits 7..0 : DPPI channel that task START will subscribe to */ #define WDT_SUBSCRIBE_START_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ #define WDT_SUBSCRIBE_START_CHIDX_Msk (0xFFUL << WDT_SUBSCRIBE_START_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ @@ -12381,7 +12090,7 @@ POSSIBILITY OF SUCH DAMAGE. #define WDT_SUBSCRIBE_STOP_EN_Disabled (0UL) /*!< Disable subscription */ #define WDT_SUBSCRIBE_STOP_EN_Enabled (1UL) /*!< Enable subscription */ -/* Bits 7..0 : Channel that task STOP will subscribe to */ +/* Bits 7..0 : DPPI channel that task STOP will subscribe to */ #define WDT_SUBSCRIBE_STOP_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ #define WDT_SUBSCRIBE_STOP_CHIDX_Msk (0xFFUL << WDT_SUBSCRIBE_STOP_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ @@ -12412,7 +12121,7 @@ POSSIBILITY OF SUCH DAMAGE. #define WDT_PUBLISH_TIMEOUT_EN_Disabled (0UL) /*!< Disable publishing */ #define WDT_PUBLISH_TIMEOUT_EN_Enabled (1UL) /*!< Enable publishing */ -/* Bits 7..0 : Channel that event TIMEOUT will publish to. */ +/* Bits 7..0 : DPPI channel that event TIMEOUT will publish to. */ #define WDT_PUBLISH_TIMEOUT_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ #define WDT_PUBLISH_TIMEOUT_CHIDX_Msk (0xFFUL << WDT_PUBLISH_TIMEOUT_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ @@ -12425,7 +12134,7 @@ POSSIBILITY OF SUCH DAMAGE. #define WDT_PUBLISH_STOPPED_EN_Disabled (0UL) /*!< Disable publishing */ #define WDT_PUBLISH_STOPPED_EN_Enabled (1UL) /*!< Enable publishing */ -/* Bits 7..0 : Channel that event STOPPED will publish to. */ +/* Bits 7..0 : DPPI channel that event STOPPED will publish to. */ #define WDT_PUBLISH_STOPPED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ #define WDT_PUBLISH_STOPPED_CHIDX_Msk (0xFFUL << WDT_PUBLISH_STOPPED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ diff --git a/mdk/nrf5340_network_peripherals.h b/mdk/nrf5340_network_peripherals.h index 2986e7cf6e..2081d49a2e 100644 --- a/mdk/nrf5340_network_peripherals.h +++ b/mdk/nrf5340_network_peripherals.h @@ -93,6 +93,8 @@ POSSIBILITY OF SUCH DAMAGE. #define RADIO_EASYDMA_MAXCNT_SIZE 9 #define RADIO_FEATURE_IEEE_802_15_4_PRESENT +#define RADIO_TXPOWER_TXPOWER_Max RADIO_TXPOWER_TXPOWER_0dBm + /* Accelerated Address Resolver */ #define AAR_PRESENT #define AAR_COUNT 1 diff --git a/mdk/nrf5340_xxaa_application.ld b/mdk/nrf5340_xxaa_application.ld index 45333396b2..f649da6fb9 100644 --- a/mdk/nrf5340_xxaa_application.ld +++ b/mdk/nrf5340_xxaa_application.ld @@ -6,6 +6,7 @@ GROUP(-lgcc -lc -lnosys) MEMORY { FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 0x100000 + EXTFLASH (rx) : ORIGIN = 0x10000000, LENGTH = 0x8000000 RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x40000 RAM1 (rwx) : ORIGIN = 0x20040000, LENGTH = 0x40000 } diff --git a/mdk/nrf5340_xxaa_network.ld b/mdk/nrf5340_xxaa_network.ld index afcc7b67a9..1c4b584f80 100644 --- a/mdk/nrf5340_xxaa_network.ld +++ b/mdk/nrf5340_xxaa_network.ld @@ -6,7 +6,10 @@ GROUP(-lgcc -lc -lnosys) MEMORY { FLASH (rx) : ORIGIN = 0x1000000, LENGTH = 0x40000 + EXTFLASH (rx) : ORIGIN = 0x10000000, LENGTH = 0x8000000 RAM (rwx) : ORIGIN = 0x21000000, LENGTH = 0x10000 + RAM1 (rwx) : ORIGIN = 0x20000000, LENGTH = 0x40000 /* Application core RAM */ + RAM2 (rwx) : ORIGIN = 0x20040000, LENGTH = 0x40000 /* Application core RAM */ } diff --git a/mdk/nrf53_erratas.h b/mdk/nrf53_erratas.h index 588f4c57b5..701048fd01 100644 --- a/mdk/nrf53_erratas.h +++ b/mdk/nrf53_erratas.h @@ -64,8 +64,11 @@ static bool nrf53_errata_27(void) __UNUSED; static bool nrf53_errata_28(void) __UNUSED; static bool nrf53_errata_29(void) __UNUSED; static bool nrf53_errata_30(void) __UNUSED; +static bool nrf53_errata_31(void) __UNUSED; static bool nrf53_errata_32(void) __UNUSED; static bool nrf53_errata_33(void) __UNUSED; +static bool nrf53_errata_34(void) __UNUSED; +static bool nrf53_errata_36(void) __UNUSED; static bool nrf53_errata_37(void) __UNUSED; static bool nrf53_errata_42(void) __UNUSED; static bool nrf53_errata_43(void) __UNUSED; @@ -76,6 +79,7 @@ static bool nrf53_errata_47(void) __UNUSED; static bool nrf53_errata_49(void) __UNUSED; static bool nrf53_errata_50(void) __UNUSED; static bool nrf53_errata_51(void) __UNUSED; +static bool nrf53_errata_52(void) __UNUSED; static bool nrf53_errata_53(void) __UNUSED; static bool nrf53_errata_54(void) __UNUSED; static bool nrf53_errata_55(void) __UNUSED; @@ -94,35 +98,59 @@ static bool nrf53_errata_72(void) __UNUSED; static bool nrf53_errata_73(void) __UNUSED; static bool nrf53_errata_74(void) __UNUSED; static bool nrf53_errata_75(void) __UNUSED; +static bool nrf53_errata_76(void) __UNUSED; +static bool nrf53_errata_77(void) __UNUSED; static bool nrf53_errata_79(void) __UNUSED; static bool nrf53_errata_80(void) __UNUSED; static bool nrf53_errata_81(void) __UNUSED; static bool nrf53_errata_82(void) __UNUSED; static bool nrf53_errata_83(void) __UNUSED; static bool nrf53_errata_84(void) __UNUSED; +static bool nrf53_errata_85(void) __UNUSED; +static bool nrf53_errata_86(void) __UNUSED; +static bool nrf53_errata_87(void) __UNUSED; static bool nrf53_errata_90(void) __UNUSED; +static bool nrf53_errata_91(void) __UNUSED; +static bool nrf53_errata_93(void) __UNUSED; +static bool nrf53_errata_95(void) __UNUSED; static bool nrf53_errata_97(void) __UNUSED; +static bool nrf53_errata_103(void) __UNUSED; +static bool nrf53_errata_105(void) __UNUSED; +static bool nrf53_errata_106(void) __UNUSED; +static bool nrf53_errata_109(void) __UNUSED; +static bool nrf53_errata_110(void) __UNUSED; +static bool nrf53_errata_113(void) __UNUSED; +static bool nrf53_errata_114(void) __UNUSED; +static bool nrf53_errata_115(void) __UNUSED; +static bool nrf53_errata_116(void) __UNUSED; +static bool nrf53_errata_119(void) __UNUSED; static bool nrf53_errata_1(void) { #ifndef NRF53_SERIES return false; #else - #if defined (NRF5340_XXAA_APPLICATION) || defined (DEVELOP_IN_NRF5340_APPLICATION) - uint32_t var1 = *(uint32_t *)0x00FF0130ul; - uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) + uint32_t var1 = *(uint32_t *)0x00FF0130ul; + uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #endif #endif - #if defined (NRF5340_XXAA_APPLICATION) || defined (DEVELOP_IN_NRF5340_APPLICATION) - if (var1 == 0x07) - { - switch(var2) + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined (NRF_APPLICATION) + if (var1 == 0x07) { - case 0x02ul: - return true; - case 0x03ul: - return false; + switch(var2) + { + case 0x02ul: + return true; + case 0x03ul: + return false; + default: + return false; + } } - } + #endif #endif return false; #endif @@ -133,21 +161,27 @@ static bool nrf53_errata_2(void) #ifndef NRF53_SERIES return false; #else - #if defined (NRF5340_XXAA_APPLICATION) || defined (DEVELOP_IN_NRF5340_APPLICATION) - uint32_t var1 = *(uint32_t *)0x00FF0130ul; - uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) + uint32_t var1 = *(uint32_t *)0x00FF0130ul; + uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #endif #endif - #if defined (NRF5340_XXAA_APPLICATION) || defined (DEVELOP_IN_NRF5340_APPLICATION) - if (var1 == 0x07) - { - switch(var2) + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined (NRF_APPLICATION) + if (var1 == 0x07) { - case 0x02ul: - return true; - case 0x03ul: - return false; + switch(var2) + { + case 0x02ul: + return true; + case 0x03ul: + return false; + default: + return false; + } } - } + #endif #endif return false; #endif @@ -158,21 +192,27 @@ static bool nrf53_errata_3(void) #ifndef NRF53_SERIES return false; #else - #if defined (NRF5340_XXAA_APPLICATION) || defined (DEVELOP_IN_NRF5340_APPLICATION) - uint32_t var1 = *(uint32_t *)0x00FF0130ul; - uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) + uint32_t var1 = *(uint32_t *)0x00FF0130ul; + uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #endif #endif - #if defined (NRF5340_XXAA_APPLICATION) || defined (DEVELOP_IN_NRF5340_APPLICATION) - if (var1 == 0x07) - { - switch(var2) + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined (NRF_APPLICATION) + if (var1 == 0x07) { - case 0x02ul: - return true; - case 0x03ul: - return true; + switch(var2) + { + case 0x02ul: + return true; + case 0x03ul: + return false; + default: + return false; + } } - } + #endif #endif return false; #endif @@ -183,21 +223,27 @@ static bool nrf53_errata_4(void) #ifndef NRF53_SERIES return false; #else - #if defined (NRF5340_XXAA_APPLICATION) || defined (DEVELOP_IN_NRF5340_APPLICATION) - uint32_t var1 = *(uint32_t *)0x00FF0130ul; - uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) + uint32_t var1 = *(uint32_t *)0x00FF0130ul; + uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #endif #endif - #if defined (NRF5340_XXAA_APPLICATION) || defined (DEVELOP_IN_NRF5340_APPLICATION) - if (var1 == 0x07) - { - switch(var2) + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined (NRF_APPLICATION) + if (var1 == 0x07) { - case 0x02ul: - return true; - case 0x03ul: - return false; + switch(var2) + { + case 0x02ul: + return true; + case 0x03ul: + return false; + default: + return false; + } } - } + #endif #endif return false; #endif @@ -208,21 +254,27 @@ static bool nrf53_errata_5(void) #ifndef NRF53_SERIES return false; #else - #if defined (NRF5340_XXAA_APPLICATION) || defined (DEVELOP_IN_NRF5340_APPLICATION) - uint32_t var1 = *(uint32_t *)0x00FF0130ul; - uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) + uint32_t var1 = *(uint32_t *)0x00FF0130ul; + uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #endif #endif - #if defined (NRF5340_XXAA_APPLICATION) || defined (DEVELOP_IN_NRF5340_APPLICATION) - if (var1 == 0x07) - { - switch(var2) + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined (NRF_APPLICATION) + if (var1 == 0x07) { - case 0x02ul: - return true; - case 0x03ul: - return false; + switch(var2) + { + case 0x02ul: + return true; + case 0x03ul: + return false; + default: + return false; + } } - } + #endif #endif return false; #endif @@ -233,21 +285,27 @@ static bool nrf53_errata_6(void) #ifndef NRF53_SERIES return false; #else - #if defined (NRF5340_XXAA_NETWORK) || defined (DEVELOP_IN_NRF5340_NETWORK) - uint32_t var1 = *(uint32_t *)0x01FF0130ul; - uint32_t var2 = *(uint32_t *)0x01FF0134ul; + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_NETWORK) + uint32_t var1 = *(uint32_t *)0x01FF0130ul; + uint32_t var2 = *(uint32_t *)0x01FF0134ul; + #endif #endif - #if defined (NRF5340_XXAA_NETWORK) || defined (DEVELOP_IN_NRF5340_NETWORK) - if (var1 == 0x07) - { - switch(var2) + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined (NRF_NETWORK) + if (var1 == 0x07) { - case 0x02ul: - return true; - case 0x03ul: - return false; + switch(var2) + { + case 0x02ul: + return true; + case 0x03ul: + return false; + default: + return false; + } } - } + #endif #endif return false; #endif @@ -258,21 +316,27 @@ static bool nrf53_errata_7(void) #ifndef NRF53_SERIES return false; #else - #if defined (NRF5340_XXAA_APPLICATION) || defined (DEVELOP_IN_NRF5340_APPLICATION) - uint32_t var1 = *(uint32_t *)0x00FF0130ul; - uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) + uint32_t var1 = *(uint32_t *)0x00FF0130ul; + uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #endif #endif - #if defined (NRF5340_XXAA_APPLICATION) || defined (DEVELOP_IN_NRF5340_APPLICATION) - if (var1 == 0x07) - { - switch(var2) + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined (NRF_APPLICATION) + if (var1 == 0x07) { - case 0x02ul: - return true; - case 0x03ul: - return false; + switch(var2) + { + case 0x02ul: + return true; + case 0x03ul: + return false; + default: + return false; + } } - } + #endif #endif return false; #endif @@ -283,21 +347,27 @@ static bool nrf53_errata_8(void) #ifndef NRF53_SERIES return false; #else - #if defined (NRF5340_XXAA_APPLICATION) || defined (DEVELOP_IN_NRF5340_APPLICATION) - uint32_t var1 = *(uint32_t *)0x00FF0130ul; - uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) + uint32_t var1 = *(uint32_t *)0x00FF0130ul; + uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #endif #endif - #if defined (NRF5340_XXAA_APPLICATION) || defined (DEVELOP_IN_NRF5340_APPLICATION) - if (var1 == 0x07) - { - switch(var2) + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined (NRF_APPLICATION) + if (var1 == 0x07) { - case 0x02ul: - return true; - case 0x03ul: - return false; + switch(var2) + { + case 0x02ul: + return true; + case 0x03ul: + return false; + default: + return false; + } } - } + #endif #endif return false; #endif @@ -308,21 +378,27 @@ static bool nrf53_errata_9(void) #ifndef NRF53_SERIES return false; #else - #if defined (NRF5340_XXAA_APPLICATION) || defined (DEVELOP_IN_NRF5340_APPLICATION) - uint32_t var1 = *(uint32_t *)0x00FF0130ul; - uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) + uint32_t var1 = *(uint32_t *)0x00FF0130ul; + uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #endif #endif - #if defined (NRF5340_XXAA_APPLICATION) || defined (DEVELOP_IN_NRF5340_APPLICATION) - if (var1 == 0x07) - { - switch(var2) + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined (NRF_APPLICATION) + if (var1 == 0x07) { - case 0x02ul: - return true; - case 0x03ul: - return false; + switch(var2) + { + case 0x02ul: + return true; + case 0x03ul: + return false; + default: + return false; + } } - } + #endif #endif return false; #endif @@ -333,21 +409,27 @@ static bool nrf53_errata_10(void) #ifndef NRF53_SERIES return false; #else - #if defined (NRF5340_XXAA_NETWORK) || defined (DEVELOP_IN_NRF5340_NETWORK) - uint32_t var1 = *(uint32_t *)0x01FF0130ul; - uint32_t var2 = *(uint32_t *)0x01FF0134ul; + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_NETWORK) + uint32_t var1 = *(uint32_t *)0x01FF0130ul; + uint32_t var2 = *(uint32_t *)0x01FF0134ul; + #endif #endif - #if defined (NRF5340_XXAA_NETWORK) || defined (DEVELOP_IN_NRF5340_NETWORK) - if (var1 == 0x07) - { - switch(var2) + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined (NRF_NETWORK) + if (var1 == 0x07) { - case 0x02ul: - return true; - case 0x03ul: - return false; + switch(var2) + { + case 0x02ul: + return true; + case 0x03ul: + return false; + default: + return false; + } } - } + #endif #endif return false; #endif @@ -358,21 +440,27 @@ static bool nrf53_errata_11(void) #ifndef NRF53_SERIES return false; #else - #if defined (NRF5340_XXAA_NETWORK) || defined (DEVELOP_IN_NRF5340_NETWORK) - uint32_t var1 = *(uint32_t *)0x01FF0130ul; - uint32_t var2 = *(uint32_t *)0x01FF0134ul; + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_NETWORK) + uint32_t var1 = *(uint32_t *)0x01FF0130ul; + uint32_t var2 = *(uint32_t *)0x01FF0134ul; + #endif #endif - #if defined (NRF5340_XXAA_NETWORK) || defined (DEVELOP_IN_NRF5340_NETWORK) - if (var1 == 0x07) - { - switch(var2) + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined (NRF_NETWORK) + if (var1 == 0x07) { - case 0x02ul: - return true; - case 0x03ul: - return false; + switch(var2) + { + case 0x02ul: + return true; + case 0x03ul: + return false; + default: + return false; + } } - } + #endif #endif return false; #endif @@ -383,21 +471,27 @@ static bool nrf53_errata_12(void) #ifndef NRF53_SERIES return false; #else - #if defined (NRF5340_XXAA_APPLICATION) || defined (DEVELOP_IN_NRF5340_APPLICATION) - uint32_t var1 = *(uint32_t *)0x00FF0130ul; - uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) + uint32_t var1 = *(uint32_t *)0x00FF0130ul; + uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #endif #endif - #if defined (NRF5340_XXAA_APPLICATION) || defined (DEVELOP_IN_NRF5340_APPLICATION) - if (var1 == 0x07) - { - switch(var2) + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined (NRF_APPLICATION) + if (var1 == 0x07) { - case 0x02ul: - return true; - case 0x03ul: - return true; + switch(var2) + { + case 0x02ul: + return true; + case 0x03ul: + return false; + default: + return false; + } } - } + #endif #endif return false; #endif @@ -408,8 +502,7 @@ static bool nrf53_errata_13(void) #ifndef NRF53_SERIES return false; #else - #if defined (NRF5340_XXAA_APPLICATION) || defined (DEVELOP_IN_NRF5340_APPLICATION)\ - || defined (NRF5340_XXAA_NETWORK) || defined (DEVELOP_IN_NRF5340_NETWORK) + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) #if defined(NRF_APPLICATION) uint32_t var1 = *(uint32_t *)0x00FF0130ul; uint32_t var2 = *(uint32_t *)0x00FF0134ul; @@ -418,18 +511,22 @@ static bool nrf53_errata_13(void) uint32_t var2 = *(uint32_t *)0x01FF0134ul; #endif #endif - #if defined (NRF5340_XXAA_APPLICATION) || defined (DEVELOP_IN_NRF5340_APPLICATION)\ - || defined (NRF5340_XXAA_NETWORK) || defined (DEVELOP_IN_NRF5340_NETWORK) - if (var1 == 0x07) - { - switch(var2) - { - case 0x02ul: - return true; - case 0x03ul: - return false; + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined (NRF_APPLICATION)\ + || defined (NRF_NETWORK) + if (var1 == 0x07) + { + switch(var2) + { + case 0x02ul: + return true; + case 0x03ul: + return false; + default: + return false; + } } - } + #endif #endif return false; #endif @@ -440,21 +537,27 @@ static bool nrf53_errata_14(void) #ifndef NRF53_SERIES return false; #else - #if defined (NRF5340_XXAA_NETWORK) || defined (DEVELOP_IN_NRF5340_NETWORK) - uint32_t var1 = *(uint32_t *)0x01FF0130ul; - uint32_t var2 = *(uint32_t *)0x01FF0134ul; + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_NETWORK) + uint32_t var1 = *(uint32_t *)0x01FF0130ul; + uint32_t var2 = *(uint32_t *)0x01FF0134ul; + #endif #endif - #if defined (NRF5340_XXAA_NETWORK) || defined (DEVELOP_IN_NRF5340_NETWORK) - if (var1 == 0x07) - { - switch(var2) + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined (NRF_NETWORK) + if (var1 == 0x07) { - case 0x02ul: - return true; - case 0x03ul: - return false; + switch(var2) + { + case 0x02ul: + return true; + case 0x03ul: + return false; + default: + return false; + } } - } + #endif #endif return false; #endif @@ -465,8 +568,7 @@ static bool nrf53_errata_15(void) #ifndef NRF53_SERIES return false; #else - #if defined (NRF5340_XXAA_APPLICATION) || defined (DEVELOP_IN_NRF5340_APPLICATION)\ - || defined (NRF5340_XXAA_NETWORK) || defined (DEVELOP_IN_NRF5340_NETWORK) + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) #if defined(NRF_APPLICATION) uint32_t var1 = *(uint32_t *)0x00FF0130ul; uint32_t var2 = *(uint32_t *)0x00FF0134ul; @@ -475,18 +577,22 @@ static bool nrf53_errata_15(void) uint32_t var2 = *(uint32_t *)0x01FF0134ul; #endif #endif - #if defined (NRF5340_XXAA_APPLICATION) || defined (DEVELOP_IN_NRF5340_APPLICATION)\ - || defined (NRF5340_XXAA_NETWORK) || defined (DEVELOP_IN_NRF5340_NETWORK) - if (var1 == 0x07) - { - switch(var2) - { - case 0x02ul: - return true; - case 0x03ul: - return false; + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined (NRF_APPLICATION)\ + || defined (NRF_NETWORK) + if (var1 == 0x07) + { + switch(var2) + { + case 0x02ul: + return true; + case 0x03ul: + return false; + default: + return false; + } } - } + #endif #endif return false; #endif @@ -497,21 +603,27 @@ static bool nrf53_errata_16(void) #ifndef NRF53_SERIES return false; #else - #if defined (NRF5340_XXAA_NETWORK) || defined (DEVELOP_IN_NRF5340_NETWORK) - uint32_t var1 = *(uint32_t *)0x01FF0130ul; - uint32_t var2 = *(uint32_t *)0x01FF0134ul; + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_NETWORK) + uint32_t var1 = *(uint32_t *)0x01FF0130ul; + uint32_t var2 = *(uint32_t *)0x01FF0134ul; + #endif #endif - #if defined (NRF5340_XXAA_NETWORK) || defined (DEVELOP_IN_NRF5340_NETWORK) - if (var1 == 0x07) - { - switch(var2) + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined (NRF_NETWORK) + if (var1 == 0x07) { - case 0x02ul: - return true; - case 0x03ul: - return false; + switch(var2) + { + case 0x02ul: + return true; + case 0x03ul: + return false; + default: + return false; + } } - } + #endif #endif return false; #endif @@ -522,21 +634,27 @@ static bool nrf53_errata_18(void) #ifndef NRF53_SERIES return false; #else - #if defined (NRF5340_XXAA_APPLICATION) || defined (DEVELOP_IN_NRF5340_APPLICATION) - uint32_t var1 = *(uint32_t *)0x00FF0130ul; - uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) + uint32_t var1 = *(uint32_t *)0x00FF0130ul; + uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #endif #endif - #if defined (NRF5340_XXAA_APPLICATION) || defined (DEVELOP_IN_NRF5340_APPLICATION) - if (var1 == 0x07) - { - switch(var2) + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined (NRF_APPLICATION) + if (var1 == 0x07) { - case 0x02ul: - return true; - case 0x03ul: - return false; + switch(var2) + { + case 0x02ul: + return true; + case 0x03ul: + return false; + default: + return false; + } } - } + #endif #endif return false; #endif @@ -547,21 +665,27 @@ static bool nrf53_errata_19(void) #ifndef NRF53_SERIES return false; #else - #if defined (NRF5340_XXAA_APPLICATION) || defined (DEVELOP_IN_NRF5340_APPLICATION) - uint32_t var1 = *(uint32_t *)0x00FF0130ul; - uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) + uint32_t var1 = *(uint32_t *)0x00FF0130ul; + uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #endif #endif - #if defined (NRF5340_XXAA_APPLICATION) || defined (DEVELOP_IN_NRF5340_APPLICATION) - if (var1 == 0x07) - { - switch(var2) + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined (NRF_APPLICATION) + if (var1 == 0x07) { - case 0x02ul: - return true; - case 0x03ul: - return false; + switch(var2) + { + case 0x02ul: + return true; + case 0x03ul: + return false; + default: + return false; + } } - } + #endif #endif return false; #endif @@ -572,8 +696,7 @@ static bool nrf53_errata_20(void) #ifndef NRF53_SERIES return false; #else - #if defined (NRF5340_XXAA_APPLICATION) || defined (DEVELOP_IN_NRF5340_APPLICATION)\ - || defined (NRF5340_XXAA_NETWORK) || defined (DEVELOP_IN_NRF5340_NETWORK) + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) #if defined(NRF_APPLICATION) uint32_t var1 = *(uint32_t *)0x00FF0130ul; uint32_t var2 = *(uint32_t *)0x00FF0134ul; @@ -582,18 +705,22 @@ static bool nrf53_errata_20(void) uint32_t var2 = *(uint32_t *)0x01FF0134ul; #endif #endif - #if defined (NRF5340_XXAA_APPLICATION) || defined (DEVELOP_IN_NRF5340_APPLICATION)\ - || defined (NRF5340_XXAA_NETWORK) || defined (DEVELOP_IN_NRF5340_NETWORK) - if (var1 == 0x07) - { - switch(var2) - { - case 0x02ul: - return true; - case 0x03ul: - return false; + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined (NRF_APPLICATION)\ + || defined (NRF_NETWORK) + if (var1 == 0x07) + { + switch(var2) + { + case 0x02ul: + return true; + case 0x03ul: + return false; + default: + return false; + } } - } + #endif #endif return false; #endif @@ -604,8 +731,7 @@ static bool nrf53_errata_21(void) #ifndef NRF53_SERIES return false; #else - #if defined (NRF5340_XXAA_APPLICATION) || defined (DEVELOP_IN_NRF5340_APPLICATION)\ - || defined (NRF5340_XXAA_NETWORK) || defined (DEVELOP_IN_NRF5340_NETWORK) + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) #if defined(NRF_APPLICATION) uint32_t var1 = *(uint32_t *)0x00FF0130ul; uint32_t var2 = *(uint32_t *)0x00FF0134ul; @@ -614,18 +740,22 @@ static bool nrf53_errata_21(void) uint32_t var2 = *(uint32_t *)0x01FF0134ul; #endif #endif - #if defined (NRF5340_XXAA_APPLICATION) || defined (DEVELOP_IN_NRF5340_APPLICATION)\ - || defined (NRF5340_XXAA_NETWORK) || defined (DEVELOP_IN_NRF5340_NETWORK) - if (var1 == 0x07) - { - switch(var2) - { - case 0x02ul: - return true; - case 0x03ul: - return true; + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined (NRF_APPLICATION)\ + || defined (NRF_NETWORK) + if (var1 == 0x07) + { + switch(var2) + { + case 0x02ul: + return true; + case 0x03ul: + return false; + default: + return false; + } } - } + #endif #endif return false; #endif @@ -636,21 +766,27 @@ static bool nrf53_errata_22(void) #ifndef NRF53_SERIES return false; #else - #if defined (NRF5340_XXAA_APPLICATION) || defined (DEVELOP_IN_NRF5340_APPLICATION) - uint32_t var1 = *(uint32_t *)0x00FF0130ul; - uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) + uint32_t var1 = *(uint32_t *)0x00FF0130ul; + uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #endif #endif - #if defined (NRF5340_XXAA_APPLICATION) || defined (DEVELOP_IN_NRF5340_APPLICATION) - if (var1 == 0x07) - { - switch(var2) + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined (NRF_APPLICATION) + if (var1 == 0x07) { - case 0x02ul: - return true; - case 0x03ul: - return false; + switch(var2) + { + case 0x02ul: + return true; + case 0x03ul: + return false; + default: + return false; + } } - } + #endif #endif return false; #endif @@ -661,21 +797,27 @@ static bool nrf53_errata_23(void) #ifndef NRF53_SERIES return false; #else - #if defined (NRF5340_XXAA_APPLICATION) || defined (DEVELOP_IN_NRF5340_APPLICATION) - uint32_t var1 = *(uint32_t *)0x00FF0130ul; - uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) + uint32_t var1 = *(uint32_t *)0x00FF0130ul; + uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #endif #endif - #if defined (NRF5340_XXAA_APPLICATION) || defined (DEVELOP_IN_NRF5340_APPLICATION) - if (var1 == 0x07) - { - switch(var2) + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined (NRF_APPLICATION) + if (var1 == 0x07) { - case 0x02ul: - return true; - case 0x03ul: - return false; + switch(var2) + { + case 0x02ul: + return true; + case 0x03ul: + return false; + default: + return false; + } } - } + #endif #endif return false; #endif @@ -686,8 +828,7 @@ static bool nrf53_errata_26(void) #ifndef NRF53_SERIES return false; #else - #if defined (NRF5340_XXAA_APPLICATION) || defined (DEVELOP_IN_NRF5340_APPLICATION)\ - || defined (NRF5340_XXAA_NETWORK) || defined (DEVELOP_IN_NRF5340_NETWORK) + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) #if defined(NRF_APPLICATION) uint32_t var1 = *(uint32_t *)0x00FF0130ul; uint32_t var2 = *(uint32_t *)0x00FF0134ul; @@ -696,18 +837,22 @@ static bool nrf53_errata_26(void) uint32_t var2 = *(uint32_t *)0x01FF0134ul; #endif #endif - #if defined (NRF5340_XXAA_APPLICATION) || defined (DEVELOP_IN_NRF5340_APPLICATION)\ - || defined (NRF5340_XXAA_NETWORK) || defined (DEVELOP_IN_NRF5340_NETWORK) - if (var1 == 0x07) - { - switch(var2) - { - case 0x02ul: - return true; - case 0x03ul: - return false; + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined (NRF_APPLICATION)\ + || defined (NRF_NETWORK) + if (var1 == 0x07) + { + switch(var2) + { + case 0x02ul: + return true; + case 0x03ul: + return false; + default: + return false; + } } - } + #endif #endif return false; #endif @@ -718,8 +863,7 @@ static bool nrf53_errata_27(void) #ifndef NRF53_SERIES return false; #else - #if defined (NRF5340_XXAA_APPLICATION) || defined (DEVELOP_IN_NRF5340_APPLICATION)\ - || defined (NRF5340_XXAA_NETWORK) || defined (DEVELOP_IN_NRF5340_NETWORK) + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) #if defined(NRF_APPLICATION) uint32_t var1 = *(uint32_t *)0x00FF0130ul; uint32_t var2 = *(uint32_t *)0x00FF0134ul; @@ -728,18 +872,22 @@ static bool nrf53_errata_27(void) uint32_t var2 = *(uint32_t *)0x01FF0134ul; #endif #endif - #if defined (NRF5340_XXAA_APPLICATION) || defined (DEVELOP_IN_NRF5340_APPLICATION)\ - || defined (NRF5340_XXAA_NETWORK) || defined (DEVELOP_IN_NRF5340_NETWORK) - if (var1 == 0x07) - { - switch(var2) - { - case 0x02ul: - return true; - case 0x03ul: - return false; + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined (NRF_APPLICATION)\ + || defined (NRF_NETWORK) + if (var1 == 0x07) + { + switch(var2) + { + case 0x02ul: + return true; + case 0x03ul: + return false; + default: + return false; + } } - } + #endif #endif return false; #endif @@ -750,8 +898,7 @@ static bool nrf53_errata_28(void) #ifndef NRF53_SERIES return false; #else - #if defined (NRF5340_XXAA_APPLICATION) || defined (DEVELOP_IN_NRF5340_APPLICATION)\ - || defined (NRF5340_XXAA_NETWORK) || defined (DEVELOP_IN_NRF5340_NETWORK) + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) #if defined(NRF_APPLICATION) uint32_t var1 = *(uint32_t *)0x00FF0130ul; uint32_t var2 = *(uint32_t *)0x00FF0134ul; @@ -760,18 +907,22 @@ static bool nrf53_errata_28(void) uint32_t var2 = *(uint32_t *)0x01FF0134ul; #endif #endif - #if defined (NRF5340_XXAA_APPLICATION) || defined (DEVELOP_IN_NRF5340_APPLICATION)\ - || defined (NRF5340_XXAA_NETWORK) || defined (DEVELOP_IN_NRF5340_NETWORK) - if (var1 == 0x07) - { - switch(var2) - { - case 0x02ul: - return true; - case 0x03ul: - return false; + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined (NRF_APPLICATION)\ + || defined (NRF_NETWORK) + if (var1 == 0x07) + { + switch(var2) + { + case 0x02ul: + return true; + case 0x03ul: + return false; + default: + return false; + } } - } + #endif #endif return false; #endif @@ -782,21 +933,27 @@ static bool nrf53_errata_29(void) #ifndef NRF53_SERIES return false; #else - #if defined (NRF5340_XXAA_NETWORK) || defined (DEVELOP_IN_NRF5340_NETWORK) - uint32_t var1 = *(uint32_t *)0x01FF0130ul; - uint32_t var2 = *(uint32_t *)0x01FF0134ul; + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_NETWORK) + uint32_t var1 = *(uint32_t *)0x01FF0130ul; + uint32_t var2 = *(uint32_t *)0x01FF0134ul; + #endif #endif - #if defined (NRF5340_XXAA_NETWORK) || defined (DEVELOP_IN_NRF5340_NETWORK) - if (var1 == 0x07) - { - switch(var2) + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined (NRF_NETWORK) + if (var1 == 0x07) { - case 0x02ul: - return true; - case 0x03ul: - return false; + switch(var2) + { + case 0x02ul: + return true; + case 0x03ul: + return false; + default: + return false; + } } - } + #endif #endif return false; #endif @@ -807,21 +964,62 @@ static bool nrf53_errata_30(void) #ifndef NRF53_SERIES return false; #else - #if defined (NRF5340_XXAA_NETWORK) || defined (DEVELOP_IN_NRF5340_NETWORK) - uint32_t var1 = *(uint32_t *)0x01FF0130ul; - uint32_t var2 = *(uint32_t *)0x01FF0134ul; + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_NETWORK) + uint32_t var1 = *(uint32_t *)0x01FF0130ul; + uint32_t var2 = *(uint32_t *)0x01FF0134ul; + #endif #endif - #if defined (NRF5340_XXAA_NETWORK) || defined (DEVELOP_IN_NRF5340_NETWORK) - if (var1 == 0x07) - { - switch(var2) + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined (NRF_NETWORK) + if (var1 == 0x07) { - case 0x02ul: - return true; - case 0x03ul: - return false; + switch(var2) + { + case 0x02ul: + return true; + case 0x03ul: + return false; + default: + return false; + } + } + #endif + #endif + return false; + #endif +} + +static bool nrf53_errata_31(void) +{ + #ifndef NRF53_SERIES + return false; + #else + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) + uint32_t var1 = *(uint32_t *)0x00FF0130ul; + uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #elif defined(NRF_NETWORK) + uint32_t var1 = *(uint32_t *)0x01FF0130ul; + uint32_t var2 = *(uint32_t *)0x01FF0134ul; + #endif + #endif + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined (NRF_APPLICATION)\ + || defined (NRF_NETWORK) + if (var1 == 0x07) + { + switch(var2) + { + case 0x02ul: + return true; + case 0x03ul: + return false; + default: + return false; + } } - } + #endif #endif return false; #endif @@ -832,21 +1030,27 @@ static bool nrf53_errata_32(void) #ifndef NRF53_SERIES return false; #else - #if defined (NRF5340_XXAA_NETWORK) || defined (DEVELOP_IN_NRF5340_NETWORK) - uint32_t var1 = *(uint32_t *)0x01FF0130ul; - uint32_t var2 = *(uint32_t *)0x01FF0134ul; + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_NETWORK) + uint32_t var1 = *(uint32_t *)0x01FF0130ul; + uint32_t var2 = *(uint32_t *)0x01FF0134ul; + #endif #endif - #if defined (NRF5340_XXAA_NETWORK) || defined (DEVELOP_IN_NRF5340_NETWORK) - if (var1 == 0x07) - { - switch(var2) + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined (NRF_NETWORK) + if (var1 == 0x07) { - case 0x02ul: - return true; - case 0x03ul: - return false; + switch(var2) + { + case 0x02ul: + return true; + case 0x03ul: + return false; + default: + return false; + } } - } + #endif #endif return false; #endif @@ -857,21 +1061,89 @@ static bool nrf53_errata_33(void) #ifndef NRF53_SERIES return false; #else - #if defined (NRF5340_XXAA_APPLICATION) || defined (DEVELOP_IN_NRF5340_APPLICATION) - uint32_t var1 = *(uint32_t *)0x00FF0130ul; - uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) + uint32_t var1 = *(uint32_t *)0x00FF0130ul; + uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #endif + #endif + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined (NRF_APPLICATION) + if (var1 == 0x07) + { + switch(var2) + { + case 0x02ul: + return true; + case 0x03ul: + return false; + default: + return false; + } + } + #endif + #endif + return false; + #endif +} + +static bool nrf53_errata_34(void) +{ + #ifndef NRF53_SERIES + return false; + #else + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_NETWORK) + uint32_t var1 = *(uint32_t *)0x01FF0130ul; + uint32_t var2 = *(uint32_t *)0x01FF0134ul; + #endif + #endif + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined (NRF_NETWORK) + if (var1 == 0x07) + { + switch(var2) + { + case 0x02ul: + return true; + case 0x03ul: + return false; + default: + return false; + } + } + #endif + #endif + return false; + #endif +} + +static bool nrf53_errata_36(void) +{ + #ifndef NRF53_SERIES + return false; + #else + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) + uint32_t var1 = *(uint32_t *)0x00FF0130ul; + uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #endif #endif - #if defined (NRF5340_XXAA_APPLICATION) || defined (DEVELOP_IN_NRF5340_APPLICATION) - if (var1 == 0x07) - { - switch(var2) + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined (NRF_APPLICATION) + if (var1 == 0x07) { - case 0x02ul: - return true; - case 0x03ul: - return false; + switch(var2) + { + case 0x02ul: + return true; + case 0x03ul: + return false; + default: + return false; + } } - } + #endif #endif return false; #endif @@ -882,8 +1154,7 @@ static bool nrf53_errata_37(void) #ifndef NRF53_SERIES return false; #else - #if defined (NRF5340_XXAA_APPLICATION) || defined (DEVELOP_IN_NRF5340_APPLICATION)\ - || defined (NRF5340_XXAA_NETWORK) || defined (DEVELOP_IN_NRF5340_NETWORK) + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) #if defined(NRF_APPLICATION) uint32_t var1 = *(uint32_t *)0x00FF0130ul; uint32_t var2 = *(uint32_t *)0x00FF0134ul; @@ -892,18 +1163,22 @@ static bool nrf53_errata_37(void) uint32_t var2 = *(uint32_t *)0x01FF0134ul; #endif #endif - #if defined (NRF5340_XXAA_APPLICATION) || defined (DEVELOP_IN_NRF5340_APPLICATION)\ - || defined (NRF5340_XXAA_NETWORK) || defined (DEVELOP_IN_NRF5340_NETWORK) - if (var1 == 0x07) - { - switch(var2) - { - case 0x02ul: - return true; - case 0x03ul: - return false; + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined (NRF_APPLICATION)\ + || defined (NRF_NETWORK) + if (var1 == 0x07) + { + switch(var2) + { + case 0x02ul: + return true; + case 0x03ul: + return false; + default: + return false; + } } - } + #endif #endif return false; #endif @@ -914,21 +1189,27 @@ static bool nrf53_errata_42(void) #ifndef NRF53_SERIES return false; #else - #if defined (NRF5340_XXAA_APPLICATION) || defined (DEVELOP_IN_NRF5340_APPLICATION) - uint32_t var1 = *(uint32_t *)0x00FF0130ul; - uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) + uint32_t var1 = *(uint32_t *)0x00FF0130ul; + uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #endif #endif - #if defined (NRF5340_XXAA_APPLICATION) || defined (DEVELOP_IN_NRF5340_APPLICATION) - if (var1 == 0x07) - { - switch(var2) + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined (NRF_APPLICATION) + if (var1 == 0x07) { - case 0x02ul: - return true; - case 0x03ul: - return false; + switch(var2) + { + case 0x02ul: + return true; + case 0x03ul: + return false; + default: + return false; + } } - } + #endif #endif return false; #endif @@ -939,21 +1220,27 @@ static bool nrf53_errata_43(void) #ifndef NRF53_SERIES return false; #else - #if defined (NRF5340_XXAA_APPLICATION) || defined (DEVELOP_IN_NRF5340_APPLICATION) - uint32_t var1 = *(uint32_t *)0x00FF0130ul; - uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) + uint32_t var1 = *(uint32_t *)0x00FF0130ul; + uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #endif #endif - #if defined (NRF5340_XXAA_APPLICATION) || defined (DEVELOP_IN_NRF5340_APPLICATION) - if (var1 == 0x07) - { - switch(var2) + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined (NRF_APPLICATION) + if (var1 == 0x07) { - case 0x02ul: - return true; - case 0x03ul: - return true; + switch(var2) + { + case 0x02ul: + return true; + case 0x03ul: + return false; + default: + return false; + } } - } + #endif #endif return false; #endif @@ -964,8 +1251,7 @@ static bool nrf53_errata_44(void) #ifndef NRF53_SERIES return false; #else - #if defined (NRF5340_XXAA_APPLICATION) || defined (DEVELOP_IN_NRF5340_APPLICATION)\ - || defined (NRF5340_XXAA_NETWORK) || defined (DEVELOP_IN_NRF5340_NETWORK) + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) #if defined(NRF_APPLICATION) uint32_t var1 = *(uint32_t *)0x00FF0130ul; uint32_t var2 = *(uint32_t *)0x00FF0134ul; @@ -974,18 +1260,22 @@ static bool nrf53_errata_44(void) uint32_t var2 = *(uint32_t *)0x01FF0134ul; #endif #endif - #if defined (NRF5340_XXAA_APPLICATION) || defined (DEVELOP_IN_NRF5340_APPLICATION)\ - || defined (NRF5340_XXAA_NETWORK) || defined (DEVELOP_IN_NRF5340_NETWORK) - if (var1 == 0x07) - { - switch(var2) - { - case 0x02ul: - return true; - case 0x03ul: - return false; + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined (NRF_APPLICATION)\ + || defined (NRF_NETWORK) + if (var1 == 0x07) + { + switch(var2) + { + case 0x02ul: + return true; + case 0x03ul: + return false; + default: + return false; + } } - } + #endif #endif return false; #endif @@ -996,21 +1286,27 @@ static bool nrf53_errata_45(void) #ifndef NRF53_SERIES return false; #else - #if defined (NRF5340_XXAA_APPLICATION) || defined (DEVELOP_IN_NRF5340_APPLICATION) - uint32_t var1 = *(uint32_t *)0x00FF0130ul; - uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) + uint32_t var1 = *(uint32_t *)0x00FF0130ul; + uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #endif #endif - #if defined (NRF5340_XXAA_APPLICATION) || defined (DEVELOP_IN_NRF5340_APPLICATION) - if (var1 == 0x07) - { - switch(var2) + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined (NRF_APPLICATION) + if (var1 == 0x07) { - case 0x02ul: - return true; - case 0x03ul: - return true; + switch(var2) + { + case 0x02ul: + return true; + case 0x03ul: + return false; + default: + return false; + } } - } + #endif #endif return false; #endif @@ -1021,21 +1317,27 @@ static bool nrf53_errata_46(void) #ifndef NRF53_SERIES return false; #else - #if defined (NRF5340_XXAA_APPLICATION) || defined (DEVELOP_IN_NRF5340_APPLICATION) - uint32_t var1 = *(uint32_t *)0x00FF0130ul; - uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) + uint32_t var1 = *(uint32_t *)0x00FF0130ul; + uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #endif #endif - #if defined (NRF5340_XXAA_APPLICATION) || defined (DEVELOP_IN_NRF5340_APPLICATION) - if (var1 == 0x07) - { - switch(var2) + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined (NRF_APPLICATION) + if (var1 == 0x07) { - case 0x02ul: - return true; - case 0x03ul: - return false; + switch(var2) + { + case 0x02ul: + return true; + case 0x03ul: + return false; + default: + return false; + } } - } + #endif #endif return false; #endif @@ -1046,8 +1348,7 @@ static bool nrf53_errata_47(void) #ifndef NRF53_SERIES return false; #else - #if defined (NRF5340_XXAA_APPLICATION) || defined (DEVELOP_IN_NRF5340_APPLICATION)\ - || defined (NRF5340_XXAA_NETWORK) || defined (DEVELOP_IN_NRF5340_NETWORK) + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) #if defined(NRF_APPLICATION) uint32_t var1 = *(uint32_t *)0x00FF0130ul; uint32_t var2 = *(uint32_t *)0x00FF0134ul; @@ -1056,18 +1357,22 @@ static bool nrf53_errata_47(void) uint32_t var2 = *(uint32_t *)0x01FF0134ul; #endif #endif - #if defined (NRF5340_XXAA_APPLICATION) || defined (DEVELOP_IN_NRF5340_APPLICATION)\ - || defined (NRF5340_XXAA_NETWORK) || defined (DEVELOP_IN_NRF5340_NETWORK) - if (var1 == 0x07) - { - switch(var2) - { - case 0x02ul: - return true; - case 0x03ul: - return true; + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined (NRF_APPLICATION)\ + || defined (NRF_NETWORK) + if (var1 == 0x07) + { + switch(var2) + { + case 0x02ul: + return true; + case 0x03ul: + return false; + default: + return false; + } } - } + #endif #endif return false; #endif @@ -1078,8 +1383,7 @@ static bool nrf53_errata_49(void) #ifndef NRF53_SERIES return false; #else - #if defined (NRF5340_XXAA_APPLICATION) || defined (DEVELOP_IN_NRF5340_APPLICATION)\ - || defined (NRF5340_XXAA_NETWORK) || defined (DEVELOP_IN_NRF5340_NETWORK) + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) #if defined(NRF_APPLICATION) uint32_t var1 = *(uint32_t *)0x00FF0130ul; uint32_t var2 = *(uint32_t *)0x00FF0134ul; @@ -1088,18 +1392,22 @@ static bool nrf53_errata_49(void) uint32_t var2 = *(uint32_t *)0x01FF0134ul; #endif #endif - #if defined (NRF5340_XXAA_APPLICATION) || defined (DEVELOP_IN_NRF5340_APPLICATION)\ - || defined (NRF5340_XXAA_NETWORK) || defined (DEVELOP_IN_NRF5340_NETWORK) - if (var1 == 0x07) - { - switch(var2) - { - case 0x02ul: - return true; - case 0x03ul: - return false; + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined (NRF_APPLICATION)\ + || defined (NRF_NETWORK) + if (var1 == 0x07) + { + switch(var2) + { + case 0x02ul: + return true; + case 0x03ul: + return false; + default: + return false; + } } - } + #endif #endif return false; #endif @@ -1110,21 +1418,27 @@ static bool nrf53_errata_50(void) #ifndef NRF53_SERIES return false; #else - #if defined (NRF5340_XXAA_APPLICATION) || defined (DEVELOP_IN_NRF5340_APPLICATION) - uint32_t var1 = *(uint32_t *)0x00FF0130ul; - uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) + uint32_t var1 = *(uint32_t *)0x00FF0130ul; + uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #endif #endif - #if defined (NRF5340_XXAA_APPLICATION) || defined (DEVELOP_IN_NRF5340_APPLICATION) - if (var1 == 0x07) - { - switch(var2) + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined (NRF_APPLICATION) + if (var1 == 0x07) { - case 0x02ul: - return true; - case 0x03ul: - return false; + switch(var2) + { + case 0x02ul: + return true; + case 0x03ul: + return false; + default: + return false; + } } - } + #endif #endif return false; #endif @@ -1135,21 +1449,62 @@ static bool nrf53_errata_51(void) #ifndef NRF53_SERIES return false; #else - #if defined (NRF5340_XXAA_APPLICATION) || defined (DEVELOP_IN_NRF5340_APPLICATION) - uint32_t var1 = *(uint32_t *)0x00FF0130ul; - uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) + uint32_t var1 = *(uint32_t *)0x00FF0130ul; + uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #endif #endif - #if defined (NRF5340_XXAA_APPLICATION) || defined (DEVELOP_IN_NRF5340_APPLICATION) - if (var1 == 0x07) - { - switch(var2) + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined (NRF_APPLICATION) + if (var1 == 0x07) { - case 0x02ul: - return true; - case 0x03ul: - return false; + switch(var2) + { + case 0x02ul: + return true; + case 0x03ul: + return false; + default: + return false; + } + } + #endif + #endif + return false; + #endif +} + +static bool nrf53_errata_52(void) +{ + #ifndef NRF53_SERIES + return false; + #else + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) + uint32_t var1 = *(uint32_t *)0x00FF0130ul; + uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #elif defined(NRF_NETWORK) + uint32_t var1 = *(uint32_t *)0x01FF0130ul; + uint32_t var2 = *(uint32_t *)0x01FF0134ul; + #endif + #endif + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined (NRF_APPLICATION)\ + || defined (NRF_NETWORK) + if (var1 == 0x07) + { + switch(var2) + { + case 0x02ul: + return true; + case 0x03ul: + return false; + default: + return false; + } } - } + #endif #endif return false; #endif @@ -1160,21 +1515,27 @@ static bool nrf53_errata_53(void) #ifndef NRF53_SERIES return false; #else - #if defined (NRF5340_XXAA_APPLICATION) || defined (DEVELOP_IN_NRF5340_APPLICATION) - uint32_t var1 = *(uint32_t *)0x00FF0130ul; - uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) + uint32_t var1 = *(uint32_t *)0x00FF0130ul; + uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #endif #endif - #if defined (NRF5340_XXAA_APPLICATION) || defined (DEVELOP_IN_NRF5340_APPLICATION) - if (var1 == 0x07) - { - switch(var2) + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined (NRF_APPLICATION) + if (var1 == 0x07) { - case 0x02ul: - return true; - case 0x03ul: - return false; + switch(var2) + { + case 0x02ul: + return true; + case 0x03ul: + return false; + default: + return false; + } } - } + #endif #endif return false; #endif @@ -1185,21 +1546,27 @@ static bool nrf53_errata_54(void) #ifndef NRF53_SERIES return false; #else - #if defined (NRF5340_XXAA_NETWORK) || defined (DEVELOP_IN_NRF5340_NETWORK) - uint32_t var1 = *(uint32_t *)0x01FF0130ul; - uint32_t var2 = *(uint32_t *)0x01FF0134ul; + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_NETWORK) + uint32_t var1 = *(uint32_t *)0x01FF0130ul; + uint32_t var2 = *(uint32_t *)0x01FF0134ul; + #endif #endif - #if defined (NRF5340_XXAA_NETWORK) || defined (DEVELOP_IN_NRF5340_NETWORK) - if (var1 == 0x07) - { - switch(var2) + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined (NRF_NETWORK) + if (var1 == 0x07) { - case 0x02ul: - return true; - case 0x03ul: - return false; + switch(var2) + { + case 0x02ul: + return true; + case 0x03ul: + return false; + default: + return false; + } } - } + #endif #endif return false; #endif @@ -1210,8 +1577,7 @@ static bool nrf53_errata_55(void) #ifndef NRF53_SERIES return false; #else - #if defined (NRF5340_XXAA_APPLICATION) || defined (DEVELOP_IN_NRF5340_APPLICATION)\ - || defined (NRF5340_XXAA_NETWORK) || defined (DEVELOP_IN_NRF5340_NETWORK) + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) #if defined(NRF_APPLICATION) uint32_t var1 = *(uint32_t *)0x00FF0130ul; uint32_t var2 = *(uint32_t *)0x00FF0134ul; @@ -1220,18 +1586,22 @@ static bool nrf53_errata_55(void) uint32_t var2 = *(uint32_t *)0x01FF0134ul; #endif #endif - #if defined (NRF5340_XXAA_APPLICATION) || defined (DEVELOP_IN_NRF5340_APPLICATION)\ - || defined (NRF5340_XXAA_NETWORK) || defined (DEVELOP_IN_NRF5340_NETWORK) - if (var1 == 0x07) - { - switch(var2) - { - case 0x02ul: - return true; - case 0x03ul: - return true; + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined (NRF_APPLICATION)\ + || defined (NRF_NETWORK) + if (var1 == 0x07) + { + switch(var2) + { + case 0x02ul: + return true; + case 0x03ul: + return false; + default: + return false; + } } - } + #endif #endif return false; #endif @@ -1242,21 +1612,27 @@ static bool nrf53_errata_57(void) #ifndef NRF53_SERIES return false; #else - #if defined (NRF5340_XXAA_APPLICATION) || defined (DEVELOP_IN_NRF5340_APPLICATION) - uint32_t var1 = *(uint32_t *)0x00FF0130ul; - uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) + uint32_t var1 = *(uint32_t *)0x00FF0130ul; + uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #endif #endif - #if defined (NRF5340_XXAA_APPLICATION) || defined (DEVELOP_IN_NRF5340_APPLICATION) - if (var1 == 0x07) - { - switch(var2) + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined (NRF_APPLICATION) + if (var1 == 0x07) { - case 0x02ul: - return true; - case 0x03ul: - return false; + switch(var2) + { + case 0x02ul: + return true; + case 0x03ul: + return false; + default: + return false; + } } - } + #endif #endif return false; #endif @@ -1267,21 +1643,27 @@ static bool nrf53_errata_58(void) #ifndef NRF53_SERIES return false; #else - #if defined (NRF5340_XXAA_APPLICATION) || defined (DEVELOP_IN_NRF5340_APPLICATION) - uint32_t var1 = *(uint32_t *)0x00FF0130ul; - uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) + uint32_t var1 = *(uint32_t *)0x00FF0130ul; + uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #endif #endif - #if defined (NRF5340_XXAA_APPLICATION) || defined (DEVELOP_IN_NRF5340_APPLICATION) - if (var1 == 0x07) - { - switch(var2) + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined (NRF_APPLICATION) + if (var1 == 0x07) { - case 0x02ul: - return true; - case 0x03ul: - return false; + switch(var2) + { + case 0x02ul: + return true; + case 0x03ul: + return false; + default: + return false; + } } - } + #endif #endif return false; #endif @@ -1292,21 +1674,27 @@ static bool nrf53_errata_59(void) #ifndef NRF53_SERIES return false; #else - #if defined (NRF5340_XXAA_APPLICATION) || defined (DEVELOP_IN_NRF5340_APPLICATION) - uint32_t var1 = *(uint32_t *)0x00FF0130ul; - uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) + uint32_t var1 = *(uint32_t *)0x00FF0130ul; + uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #endif #endif - #if defined (NRF5340_XXAA_APPLICATION) || defined (DEVELOP_IN_NRF5340_APPLICATION) - if (var1 == 0x07) - { - switch(var2) + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined (NRF_APPLICATION) + if (var1 == 0x07) { - case 0x02ul: - return true; - case 0x03ul: - return false; + switch(var2) + { + case 0x02ul: + return true; + case 0x03ul: + return false; + default: + return false; + } } - } + #endif #endif return false; #endif @@ -1317,8 +1705,7 @@ static bool nrf53_errata_62(void) #ifndef NRF53_SERIES return false; #else - #if defined (NRF5340_XXAA_APPLICATION) || defined (DEVELOP_IN_NRF5340_APPLICATION)\ - || defined (NRF5340_XXAA_NETWORK) || defined (DEVELOP_IN_NRF5340_NETWORK) + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) #if defined(NRF_APPLICATION) uint32_t var1 = *(uint32_t *)0x00FF0130ul; uint32_t var2 = *(uint32_t *)0x00FF0134ul; @@ -1327,18 +1714,22 @@ static bool nrf53_errata_62(void) uint32_t var2 = *(uint32_t *)0x01FF0134ul; #endif #endif - #if defined (NRF5340_XXAA_APPLICATION) || defined (DEVELOP_IN_NRF5340_APPLICATION)\ - || defined (NRF5340_XXAA_NETWORK) || defined (DEVELOP_IN_NRF5340_NETWORK) - if (var1 == 0x07) - { - switch(var2) - { - case 0x02ul: - return true; - case 0x03ul: - return false; + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined (NRF_APPLICATION)\ + || defined (NRF_NETWORK) + if (var1 == 0x07) + { + switch(var2) + { + case 0x02ul: + return true; + case 0x03ul: + return false; + default: + return false; + } } - } + #endif #endif return false; #endif @@ -1349,8 +1740,7 @@ static bool nrf53_errata_64(void) #ifndef NRF53_SERIES return false; #else - #if defined (NRF5340_XXAA_APPLICATION) || defined (DEVELOP_IN_NRF5340_APPLICATION)\ - || defined (NRF5340_XXAA_NETWORK) || defined (DEVELOP_IN_NRF5340_NETWORK) + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) #if defined(NRF_APPLICATION) uint32_t var1 = *(uint32_t *)0x00FF0130ul; uint32_t var2 = *(uint32_t *)0x00FF0134ul; @@ -1359,18 +1749,22 @@ static bool nrf53_errata_64(void) uint32_t var2 = *(uint32_t *)0x01FF0134ul; #endif #endif - #if defined (NRF5340_XXAA_APPLICATION) || defined (DEVELOP_IN_NRF5340_APPLICATION)\ - || defined (NRF5340_XXAA_NETWORK) || defined (DEVELOP_IN_NRF5340_NETWORK) - if (var1 == 0x07) - { - switch(var2) - { - case 0x02ul: - return true; - case 0x03ul: - return false; + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined (NRF_APPLICATION)\ + || defined (NRF_NETWORK) + if (var1 == 0x07) + { + switch(var2) + { + case 0x02ul: + return true; + case 0x03ul: + return false; + default: + return false; + } } - } + #endif #endif return false; #endif @@ -1381,21 +1775,27 @@ static bool nrf53_errata_65(void) #ifndef NRF53_SERIES return false; #else - #if defined (NRF5340_XXAA_APPLICATION) || defined (DEVELOP_IN_NRF5340_APPLICATION) - uint32_t var1 = *(uint32_t *)0x00FF0130ul; - uint32_t var2 = *(uint32_t *)0x00FF0134ul; - #endif - #if defined (NRF5340_XXAA_APPLICATION) || defined (DEVELOP_IN_NRF5340_APPLICATION) - if (var1 == 0x07) - { - switch(var2) + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) + uint32_t var1 = *(uint32_t *)0x00FF0130ul; + uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #endif + #endif + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined (NRF_APPLICATION) + if (var1 == 0x07) { - case 0x02ul: - return true; - case 0x03ul: - return true; + switch(var2) + { + case 0x02ul: + return true; + case 0x03ul: + return false; + default: + return false; + } } - } + #endif #endif return false; #endif @@ -1406,21 +1806,27 @@ static bool nrf53_errata_66(void) #ifndef NRF53_SERIES return false; #else - #if defined (NRF5340_XXAA_APPLICATION) || defined (DEVELOP_IN_NRF5340_APPLICATION) - uint32_t var1 = *(uint32_t *)0x00FF0130ul; - uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) + uint32_t var1 = *(uint32_t *)0x00FF0130ul; + uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #endif #endif - #if defined (NRF5340_XXAA_APPLICATION) || defined (DEVELOP_IN_NRF5340_APPLICATION) - if (var1 == 0x07) - { - switch(var2) + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined (NRF_APPLICATION) + if (var1 == 0x07) { - case 0x02ul: - return true; - case 0x03ul: - return false; + switch(var2) + { + case 0x02ul: + return true; + case 0x03ul: + return false; + default: + return false; + } } - } + #endif #endif return false; #endif @@ -1431,8 +1837,7 @@ static bool nrf53_errata_67(void) #ifndef NRF53_SERIES return false; #else - #if defined (NRF5340_XXAA_APPLICATION) || defined (DEVELOP_IN_NRF5340_APPLICATION)\ - || defined (NRF5340_XXAA_NETWORK) || defined (DEVELOP_IN_NRF5340_NETWORK) + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) #if defined(NRF_APPLICATION) uint32_t var1 = *(uint32_t *)0x00FF0130ul; uint32_t var2 = *(uint32_t *)0x00FF0134ul; @@ -1441,18 +1846,22 @@ static bool nrf53_errata_67(void) uint32_t var2 = *(uint32_t *)0x01FF0134ul; #endif #endif - #if defined (NRF5340_XXAA_APPLICATION) || defined (DEVELOP_IN_NRF5340_APPLICATION)\ - || defined (NRF5340_XXAA_NETWORK) || defined (DEVELOP_IN_NRF5340_NETWORK) - if (var1 == 0x07) - { - switch(var2) - { - case 0x02ul: - return true; - case 0x03ul: - return false; + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined (NRF_APPLICATION)\ + || defined (NRF_NETWORK) + if (var1 == 0x07) + { + switch(var2) + { + case 0x02ul: + return true; + case 0x03ul: + return false; + default: + return false; + } } - } + #endif #endif return false; #endif @@ -1463,21 +1872,27 @@ static bool nrf53_errata_69(void) #ifndef NRF53_SERIES return false; #else - #if defined (NRF5340_XXAA_APPLICATION) || defined (DEVELOP_IN_NRF5340_APPLICATION) - uint32_t var1 = *(uint32_t *)0x00FF0130ul; - uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) + uint32_t var1 = *(uint32_t *)0x00FF0130ul; + uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #endif #endif - #if defined (NRF5340_XXAA_APPLICATION) || defined (DEVELOP_IN_NRF5340_APPLICATION) - if (var1 == 0x07) - { - switch(var2) + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined (NRF_APPLICATION) + if (var1 == 0x07) { - case 0x02ul: - return true; - case 0x03ul: - return false; + switch(var2) + { + case 0x02ul: + return true; + case 0x03ul: + return false; + default: + return false; + } } - } + #endif #endif return false; #endif @@ -1488,21 +1903,27 @@ static bool nrf53_errata_70(void) #ifndef NRF53_SERIES return false; #else - #if defined (NRF5340_XXAA_APPLICATION) || defined (DEVELOP_IN_NRF5340_APPLICATION) - uint32_t var1 = *(uint32_t *)0x00FF0130ul; - uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) + uint32_t var1 = *(uint32_t *)0x00FF0130ul; + uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #endif #endif - #if defined (NRF5340_XXAA_APPLICATION) || defined (DEVELOP_IN_NRF5340_APPLICATION) - if (var1 == 0x07) - { - switch(var2) + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined (NRF_APPLICATION) + if (var1 == 0x07) { - case 0x02ul: - return true; - case 0x03ul: - return false; + switch(var2) + { + case 0x02ul: + return true; + case 0x03ul: + return false; + default: + return false; + } } - } + #endif #endif return false; #endif @@ -1513,21 +1934,27 @@ static bool nrf53_errata_71(void) #ifndef NRF53_SERIES return false; #else - #if defined (NRF5340_XXAA_APPLICATION) || defined (DEVELOP_IN_NRF5340_APPLICATION) - uint32_t var1 = *(uint32_t *)0x00FF0130ul; - uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) + uint32_t var1 = *(uint32_t *)0x00FF0130ul; + uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #endif #endif - #if defined (NRF5340_XXAA_APPLICATION) || defined (DEVELOP_IN_NRF5340_APPLICATION) - if (var1 == 0x07) - { - switch(var2) + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined (NRF_APPLICATION) + if (var1 == 0x07) { - case 0x02ul: - return true; - case 0x03ul: - return false; + switch(var2) + { + case 0x02ul: + return true; + case 0x03ul: + return false; + default: + return false; + } } - } + #endif #endif return false; #endif @@ -1538,21 +1965,27 @@ static bool nrf53_errata_72(void) #ifndef NRF53_SERIES return false; #else - #if defined (NRF5340_XXAA_APPLICATION) || defined (DEVELOP_IN_NRF5340_APPLICATION) - uint32_t var1 = *(uint32_t *)0x00FF0130ul; - uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) + uint32_t var1 = *(uint32_t *)0x00FF0130ul; + uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #endif #endif - #if defined (NRF5340_XXAA_APPLICATION) || defined (DEVELOP_IN_NRF5340_APPLICATION) - if (var1 == 0x07) - { - switch(var2) + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined (NRF_APPLICATION) + if (var1 == 0x07) { - case 0x02ul: - return true; - case 0x03ul: - return false; + switch(var2) + { + case 0x02ul: + return true; + case 0x03ul: + return false; + default: + return false; + } } - } + #endif #endif return false; #endif @@ -1563,8 +1996,7 @@ static bool nrf53_errata_73(void) #ifndef NRF53_SERIES return false; #else - #if defined (NRF5340_XXAA_APPLICATION) || defined (DEVELOP_IN_NRF5340_APPLICATION)\ - || defined (NRF5340_XXAA_NETWORK) || defined (DEVELOP_IN_NRF5340_NETWORK) + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) #if defined(NRF_APPLICATION) uint32_t var1 = *(uint32_t *)0x00FF0130ul; uint32_t var2 = *(uint32_t *)0x00FF0134ul; @@ -1573,18 +2005,22 @@ static bool nrf53_errata_73(void) uint32_t var2 = *(uint32_t *)0x01FF0134ul; #endif #endif - #if defined (NRF5340_XXAA_APPLICATION) || defined (DEVELOP_IN_NRF5340_APPLICATION)\ - || defined (NRF5340_XXAA_NETWORK) || defined (DEVELOP_IN_NRF5340_NETWORK) - if (var1 == 0x07) - { - switch(var2) - { - case 0x02ul: - return true; - case 0x03ul: - return false; + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined (NRF_APPLICATION)\ + || defined (NRF_NETWORK) + if (var1 == 0x07) + { + switch(var2) + { + case 0x02ul: + return true; + case 0x03ul: + return false; + default: + return false; + } } - } + #endif #endif return false; #endif @@ -1595,8 +2031,7 @@ static bool nrf53_errata_74(void) #ifndef NRF53_SERIES return false; #else - #if defined (NRF5340_XXAA_APPLICATION) || defined (DEVELOP_IN_NRF5340_APPLICATION)\ - || defined (NRF5340_XXAA_NETWORK) || defined (DEVELOP_IN_NRF5340_NETWORK) + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) #if defined(NRF_APPLICATION) uint32_t var1 = *(uint32_t *)0x00FF0130ul; uint32_t var2 = *(uint32_t *)0x00FF0134ul; @@ -1605,18 +2040,22 @@ static bool nrf53_errata_74(void) uint32_t var2 = *(uint32_t *)0x01FF0134ul; #endif #endif - #if defined (NRF5340_XXAA_APPLICATION) || defined (DEVELOP_IN_NRF5340_APPLICATION)\ - || defined (NRF5340_XXAA_NETWORK) || defined (DEVELOP_IN_NRF5340_NETWORK) - if (var1 == 0x07) - { - switch(var2) - { - case 0x02ul: - return true; - case 0x03ul: - return false; + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined (NRF_APPLICATION)\ + || defined (NRF_NETWORK) + if (var1 == 0x07) + { + switch(var2) + { + case 0x02ul: + return true; + case 0x03ul: + return false; + default: + return false; + } } - } + #endif #endif return false; #endif @@ -1627,21 +2066,93 @@ static bool nrf53_errata_75(void) #ifndef NRF53_SERIES return false; #else - #if defined (NRF5340_XXAA_APPLICATION) || defined (DEVELOP_IN_NRF5340_APPLICATION) - uint32_t var1 = *(uint32_t *)0x00FF0130ul; - uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) + uint32_t var1 = *(uint32_t *)0x00FF0130ul; + uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #endif #endif - #if defined (NRF5340_XXAA_APPLICATION) || defined (DEVELOP_IN_NRF5340_APPLICATION) - if (var1 == 0x07) - { - switch(var2) + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined (NRF_APPLICATION) + if (var1 == 0x07) { - case 0x02ul: - return true; - case 0x03ul: - return true; + switch(var2) + { + case 0x02ul: + return true; + case 0x03ul: + return false; + default: + return false; + } } - } + #endif + #endif + return false; + #endif +} + +static bool nrf53_errata_76(void) +{ + #ifndef NRF53_SERIES + return false; + #else + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) + uint32_t var1 = *(uint32_t *)0x00FF0130ul; + uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #endif + #endif + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined (NRF_APPLICATION) + if (var1 == 0x07) + { + switch(var2) + { + case 0x02ul: + return true; + case 0x03ul: + return false; + default: + return false; + } + } + #endif + #endif + return false; + #endif +} + +static bool nrf53_errata_77(void) +{ + #ifndef NRF53_SERIES + return false; + #else + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) + uint32_t var1 = *(uint32_t *)0x00FF0130ul; + uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #elif defined(NRF_NETWORK) + uint32_t var1 = *(uint32_t *)0x01FF0130ul; + uint32_t var2 = *(uint32_t *)0x01FF0134ul; + #endif + #endif + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined (NRF_APPLICATION)\ + || defined (NRF_NETWORK) + if (var1 == 0x07) + { + switch(var2) + { + case 0x02ul: + return true; + case 0x03ul: + return false; + default: + return false; + } + } + #endif #endif return false; #endif @@ -1652,21 +2163,27 @@ static bool nrf53_errata_79(void) #ifndef NRF53_SERIES return false; #else - #if defined (NRF5340_XXAA_APPLICATION) || defined (DEVELOP_IN_NRF5340_APPLICATION) - uint32_t var1 = *(uint32_t *)0x00FF0130ul; - uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) + uint32_t var1 = *(uint32_t *)0x00FF0130ul; + uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #endif #endif - #if defined (NRF5340_XXAA_APPLICATION) || defined (DEVELOP_IN_NRF5340_APPLICATION) - if (var1 == 0x07) - { - switch(var2) + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined (NRF_APPLICATION) + if (var1 == 0x07) { - case 0x02ul: - return true; - case 0x03ul: - return false; + switch(var2) + { + case 0x02ul: + return true; + case 0x03ul: + return false; + default: + return false; + } } - } + #endif #endif return false; #endif @@ -1677,21 +2194,27 @@ static bool nrf53_errata_80(void) #ifndef NRF53_SERIES return false; #else - #if defined (NRF5340_XXAA_APPLICATION) || defined (DEVELOP_IN_NRF5340_APPLICATION) - uint32_t var1 = *(uint32_t *)0x00FF0130ul; - uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) + uint32_t var1 = *(uint32_t *)0x00FF0130ul; + uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #endif #endif - #if defined (NRF5340_XXAA_APPLICATION) || defined (DEVELOP_IN_NRF5340_APPLICATION) - if (var1 == 0x07) - { - switch(var2) + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined (NRF_APPLICATION) + if (var1 == 0x07) { - case 0x02ul: - return true; - case 0x03ul: - return false; + switch(var2) + { + case 0x02ul: + return true; + case 0x03ul: + return false; + default: + return false; + } } - } + #endif #endif return false; #endif @@ -1702,21 +2225,27 @@ static bool nrf53_errata_81(void) #ifndef NRF53_SERIES return false; #else - #if defined (NRF5340_XXAA_APPLICATION) || defined (DEVELOP_IN_NRF5340_APPLICATION) - uint32_t var1 = *(uint32_t *)0x00FF0130ul; - uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) + uint32_t var1 = *(uint32_t *)0x00FF0130ul; + uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #endif #endif - #if defined (NRF5340_XXAA_APPLICATION) || defined (DEVELOP_IN_NRF5340_APPLICATION) - if (var1 == 0x07) - { - switch(var2) + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined (NRF_APPLICATION) + if (var1 == 0x07) { - case 0x02ul: - return true; - case 0x03ul: - return false; + switch(var2) + { + case 0x02ul: + return true; + case 0x03ul: + return false; + default: + return false; + } } - } + #endif #endif return false; #endif @@ -1727,21 +2256,27 @@ static bool nrf53_errata_82(void) #ifndef NRF53_SERIES return false; #else - #if defined (NRF5340_XXAA_APPLICATION) || defined (DEVELOP_IN_NRF5340_APPLICATION) - uint32_t var1 = *(uint32_t *)0x00FF0130ul; - uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) + uint32_t var1 = *(uint32_t *)0x00FF0130ul; + uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #endif #endif - #if defined (NRF5340_XXAA_APPLICATION) || defined (DEVELOP_IN_NRF5340_APPLICATION) - if (var1 == 0x07) - { - switch(var2) + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined (NRF_APPLICATION) + if (var1 == 0x07) { - case 0x02ul: - return true; - case 0x03ul: - return false; + switch(var2) + { + case 0x02ul: + return true; + case 0x03ul: + return false; + default: + return false; + } } - } + #endif #endif return false; #endif @@ -1752,21 +2287,27 @@ static bool nrf53_errata_83(void) #ifndef NRF53_SERIES return false; #else - #if defined (NRF5340_XXAA_APPLICATION) || defined (DEVELOP_IN_NRF5340_APPLICATION) - uint32_t var1 = *(uint32_t *)0x00FF0130ul; - uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) + uint32_t var1 = *(uint32_t *)0x00FF0130ul; + uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #endif #endif - #if defined (NRF5340_XXAA_APPLICATION) || defined (DEVELOP_IN_NRF5340_APPLICATION) - if (var1 == 0x07) - { - switch(var2) + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined (NRF_APPLICATION) + if (var1 == 0x07) { - case 0x02ul: - return true; - case 0x03ul: - return false; + switch(var2) + { + case 0x02ul: + return true; + case 0x03ul: + return false; + default: + return false; + } } - } + #endif #endif return false; #endif @@ -1777,21 +2318,124 @@ static bool nrf53_errata_84(void) #ifndef NRF53_SERIES return false; #else - #if defined (NRF5340_XXAA_APPLICATION) || defined (DEVELOP_IN_NRF5340_APPLICATION) - uint32_t var1 = *(uint32_t *)0x00FF0130ul; - uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) + uint32_t var1 = *(uint32_t *)0x00FF0130ul; + uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #endif + #endif + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined (NRF_APPLICATION) + if (var1 == 0x07) + { + switch(var2) + { + case 0x02ul: + return true; + case 0x03ul: + return false; + default: + return false; + } + } + #endif + #endif + return false; + #endif +} + +static bool nrf53_errata_85(void) +{ + #ifndef NRF53_SERIES + return false; + #else + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) + uint32_t var1 = *(uint32_t *)0x00FF0130ul; + uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #endif + #endif + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined (NRF_APPLICATION) + if (var1 == 0x07) + { + switch(var2) + { + case 0x02ul: + return true; + case 0x03ul: + return false; + default: + return false; + } + } + #endif + #endif + return false; + #endif +} + +static bool nrf53_errata_86(void) +{ + #ifndef NRF53_SERIES + return false; + #else + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) + uint32_t var1 = *(uint32_t *)0x00FF0130ul; + uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #elif defined(NRF_NETWORK) + uint32_t var1 = *(uint32_t *)0x01FF0130ul; + uint32_t var2 = *(uint32_t *)0x01FF0134ul; + #endif + #endif + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined (NRF_APPLICATION)\ + || defined (NRF_NETWORK) + if (var1 == 0x07) + { + switch(var2) + { + case 0x02ul: + return true; + case 0x03ul: + return false; + default: + return false; + } + } + #endif + #endif + return false; + #endif +} + +static bool nrf53_errata_87(void) +{ + #ifndef NRF53_SERIES + return false; + #else + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_NETWORK) + uint32_t var1 = *(uint32_t *)0x01FF0130ul; + uint32_t var2 = *(uint32_t *)0x01FF0134ul; + #endif #endif - #if defined (NRF5340_XXAA_APPLICATION) || defined (DEVELOP_IN_NRF5340_APPLICATION) - if (var1 == 0x07) - { - switch(var2) + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined (NRF_NETWORK) + if (var1 == 0x07) { - case 0x02ul: - return true; - case 0x03ul: - return false; + switch(var2) + { + case 0x02ul: + return true; + case 0x03ul: + return false; + default: + return false; + } } - } + #endif #endif return false; #endif @@ -1802,21 +2446,120 @@ static bool nrf53_errata_90(void) #ifndef NRF53_SERIES return false; #else - #if defined (NRF5340_XXAA_APPLICATION) || defined (DEVELOP_IN_NRF5340_APPLICATION) - uint32_t var1 = *(uint32_t *)0x00FF0130ul; - uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) + uint32_t var1 = *(uint32_t *)0x00FF0130ul; + uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #endif + #endif + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined (NRF_APPLICATION) + if (var1 == 0x07) + { + switch(var2) + { + case 0x02ul: + return true; + case 0x03ul: + return false; + default: + return false; + } + } + #endif + #endif + return false; + #endif +} + +static bool nrf53_errata_91(void) +{ + #ifndef NRF53_SERIES + return false; + #else + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_NETWORK) + uint32_t var1 = *(uint32_t *)0x01FF0130ul; + uint32_t var2 = *(uint32_t *)0x01FF0134ul; + #endif + #endif + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined (NRF_NETWORK) + if (var1 == 0x07) + { + switch(var2) + { + case 0x02ul: + return true; + case 0x03ul: + return false; + default: + return false; + } + } + #endif + #endif + return false; + #endif +} + +static bool nrf53_errata_93(void) +{ + #ifndef NRF53_SERIES + return false; + #else + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_NETWORK) + uint32_t var1 = *(uint32_t *)0x01FF0130ul; + uint32_t var2 = *(uint32_t *)0x01FF0134ul; + #endif + #endif + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined (NRF_NETWORK) + if (var1 == 0x07) + { + switch(var2) + { + case 0x02ul: + return true; + case 0x03ul: + return false; + default: + return false; + } + } + #endif + #endif + return false; + #endif +} + +static bool nrf53_errata_95(void) +{ + #ifndef NRF53_SERIES + return false; + #else + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_NETWORK) + uint32_t var1 = *(uint32_t *)0x01FF0130ul; + uint32_t var2 = *(uint32_t *)0x01FF0134ul; + #endif #endif - #if defined (NRF5340_XXAA_APPLICATION) || defined (DEVELOP_IN_NRF5340_APPLICATION) - if (var1 == 0x07) - { - switch(var2) + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined (NRF_NETWORK) + if (var1 == 0x07) { - case 0x02ul: - return true; - case 0x03ul: - return false; + switch(var2) + { + case 0x02ul: + return true; + case 0x03ul: + return false; + default: + return false; + } } - } + #endif #endif return false; #endif @@ -1827,8 +2570,7 @@ static bool nrf53_errata_97(void) #ifndef NRF53_SERIES return false; #else - #if defined (NRF5340_XXAA_APPLICATION) || defined (DEVELOP_IN_NRF5340_APPLICATION)\ - || defined (NRF5340_XXAA_NETWORK) || defined (DEVELOP_IN_NRF5340_NETWORK) + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) #if defined(NRF_APPLICATION) uint32_t var1 = *(uint32_t *)0x00FF0130ul; uint32_t var2 = *(uint32_t *)0x00FF0134ul; @@ -1837,18 +2579,332 @@ static bool nrf53_errata_97(void) uint32_t var2 = *(uint32_t *)0x01FF0134ul; #endif #endif - #if defined (NRF5340_XXAA_APPLICATION) || defined (DEVELOP_IN_NRF5340_APPLICATION)\ - || defined (NRF5340_XXAA_NETWORK) || defined (DEVELOP_IN_NRF5340_NETWORK) - if (var1 == 0x07) - { - switch(var2) + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined (NRF_APPLICATION)\ + || defined (NRF_NETWORK) + if (var1 == 0x07) + { + switch(var2) + { + case 0x02ul: + return true; + case 0x03ul: + return false; + default: + return false; + } + } + #endif + #endif + return false; + #endif +} + +static bool nrf53_errata_103(void) +{ + #ifndef NRF53_SERIES + return false; + #else + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_NETWORK) + uint32_t var1 = *(uint32_t *)0x01FF0130ul; + uint32_t var2 = *(uint32_t *)0x01FF0134ul; + #endif + #endif + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined (NRF_NETWORK) + if (var1 == 0x07) { - case 0x02ul: - return true; - case 0x03ul: - return false; + switch(var2) + { + case 0x02ul: + return true; + case 0x03ul: + return false; + default: + return false; + } } - } + #endif + #endif + return false; + #endif +} + +static bool nrf53_errata_105(void) +{ + #ifndef NRF53_SERIES + return false; + #else + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) + uint32_t var1 = *(uint32_t *)0x00FF0130ul; + uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #endif + #endif + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined (NRF_APPLICATION) + if (var1 == 0x07) + { + switch(var2) + { + case 0x02ul: + return true; + case 0x03ul: + return false; + default: + return false; + } + } + #endif + #endif + return false; + #endif +} + +static bool nrf53_errata_106(void) +{ + #ifndef NRF53_SERIES + return false; + #else + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) + uint32_t var1 = *(uint32_t *)0x00FF0130ul; + uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #endif + #endif + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined (NRF_APPLICATION) + if (var1 == 0x07) + { + switch(var2) + { + case 0x02ul: + return true; + case 0x03ul: + return false; + default: + return false; + } + } + #endif + #endif + return false; + #endif +} + +static bool nrf53_errata_109(void) +{ + #ifndef NRF53_SERIES + return false; + #else + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) + uint32_t var1 = *(uint32_t *)0x00FF0130ul; + uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #endif + #endif + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined (NRF_APPLICATION) + if (var1 == 0x07) + { + switch(var2) + { + case 0x02ul: + return true; + case 0x03ul: + return false; + default: + return false; + } + } + #endif + #endif + return false; + #endif +} + +static bool nrf53_errata_110(void) +{ + #ifndef NRF53_SERIES + return false; + #else + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) + uint32_t var1 = *(uint32_t *)0x00FF0130ul; + uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #endif + #endif + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined (NRF_APPLICATION) + if (var1 == 0x07) + { + switch(var2) + { + case 0x02ul: + return true; + case 0x03ul: + return false; + default: + return false; + } + } + #endif + #endif + return false; + #endif +} + +static bool nrf53_errata_113(void) +{ + #ifndef NRF53_SERIES + return false; + #else + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_NETWORK) + uint32_t var1 = *(uint32_t *)0x01FF0130ul; + uint32_t var2 = *(uint32_t *)0x01FF0134ul; + #endif + #endif + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined (NRF_NETWORK) + if (var1 == 0x07) + { + switch(var2) + { + case 0x02ul: + return true; + case 0x03ul: + return false; + default: + return false; + } + } + #endif + #endif + return false; + #endif +} + +static bool nrf53_errata_114(void) +{ + #ifndef NRF53_SERIES + return false; + #else + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_NETWORK) + uint32_t var1 = *(uint32_t *)0x01FF0130ul; + uint32_t var2 = *(uint32_t *)0x01FF0134ul; + #endif + #endif + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined (NRF_NETWORK) + if (var1 == 0x07) + { + switch(var2) + { + case 0x02ul: + return true; + case 0x03ul: + return false; + default: + return false; + } + } + #endif + #endif + return false; + #endif +} + +static bool nrf53_errata_115(void) +{ + #ifndef NRF53_SERIES + return false; + #else + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) + uint32_t var1 = *(uint32_t *)0x00FF0130ul; + uint32_t var2 = *(uint32_t *)0x00FF0134ul; + #endif + #endif + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined (NRF_APPLICATION) + if (var1 == 0x07) + { + switch(var2) + { + case 0x02ul: + return true; + case 0x03ul: + return false; + default: + return false; + } + } + #endif + #endif + return false; + #endif +} + +static bool nrf53_errata_116(void) +{ + #ifndef NRF53_SERIES + return false; + #else + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_NETWORK) + uint32_t var1 = *(uint32_t *)0x01FF0130ul; + uint32_t var2 = *(uint32_t *)0x01FF0134ul; + #endif + #endif + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined (NRF_NETWORK) + if (var1 == 0x07) + { + switch(var2) + { + case 0x02ul: + return true; + case 0x03ul: + return false; + default: + return false; + } + } + #endif + #endif + return false; + #endif +} + +static bool nrf53_errata_119(void) +{ + #ifndef NRF53_SERIES + return false; + #else + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_NETWORK) + uint32_t var1 = *(uint32_t *)0x01FF0130ul; + uint32_t var2 = *(uint32_t *)0x01FF0134ul; + #endif + #endif + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined (NRF_NETWORK) + if (var1 == 0x07) + { + switch(var2) + { + case 0x02ul: + return true; + case 0x03ul: + return false; + default: + return false; + } + } + #endif #endif return false; #endif diff --git a/mdk/nrf9160.h b/mdk/nrf9160.h index 94bcb70c01..5b32d0abd9 100644 --- a/mdk/nrf9160.h +++ b/mdk/nrf9160.h @@ -30,10 +30,10 @@ * @file nrf9160.h * @brief CMSIS HeaderFile * @version 1 - * @date 04. March 2020 - * @note Generated by SVDConv V3.3.25 on Wednesday, 04.03.2020 14:56:53 + * @date 14. August 2020 + * @note Generated by SVDConv V3.3.35 on Friday, 14.08.2020 15:02:15 * from File 'nrf9160.svd', - * last modified on Wednesday, 04.03.2020 13:56:45 + * last modified on Friday, 14.08.2020 13:02:08 */ @@ -130,7 +130,7 @@ typedef enum { #define __MPU_PRESENT 1 /*!< MPU present */ #define __FPU_PRESENT 1 /*!< FPU present */ #define __FPU_DP 0 /*!< Double Precision FPU */ -#define __SAU_REGION_PRESENT 0 /*!< SAU present */ +#define __SAUREGION_PRESENT 0 /*!< SAU region present */ /** @} */ /* End of group Configuration_of_CMSIS */ diff --git a/mdk/nrf91_erratas.h b/mdk/nrf91_erratas.h index 26b6eb06ac..20ee7cfcc3 100644 --- a/mdk/nrf91_erratas.h +++ b/mdk/nrf91_erratas.h @@ -81,6 +81,8 @@ static bool nrf91_errata_1(void) return true; case 0x02ul: return true; + default: + return true; } } #endif @@ -106,6 +108,8 @@ static bool nrf91_errata_2(void) return true; case 0x02ul: return true; + default: + return true; } } #endif @@ -131,6 +135,8 @@ static bool nrf91_errata_4(void) return true; case 0x02ul: return true; + default: + return true; } } #endif @@ -156,6 +162,8 @@ static bool nrf91_errata_6(void) return true; case 0x02ul: return true; + default: + return true; } } #endif @@ -181,6 +189,8 @@ static bool nrf91_errata_7(void) return true; case 0x02ul: return true; + default: + return true; } } #endif @@ -206,6 +216,8 @@ static bool nrf91_errata_8(void) return true; case 0x02ul: return false; + default: + return false; } } #endif @@ -231,6 +243,8 @@ static bool nrf91_errata_9(void) return false; case 0x02ul: return true; + default: + return true; } } #endif @@ -256,6 +270,8 @@ static bool nrf91_errata_10(void) return true; case 0x02ul: return false; + default: + return false; } } #endif @@ -281,6 +297,8 @@ static bool nrf91_errata_12(void) return true; case 0x02ul: return false; + default: + return false; } } #endif @@ -306,6 +324,8 @@ static bool nrf91_errata_14(void) return true; case 0x02ul: return false; + default: + return false; } } #endif @@ -331,6 +351,8 @@ static bool nrf91_errata_15(void) return false; case 0x02ul: return true; + default: + return true; } } #endif @@ -356,6 +378,8 @@ static bool nrf91_errata_16(void) return true; case 0x02ul: return false; + default: + return false; } } #endif @@ -381,6 +405,8 @@ static bool nrf91_errata_17(void) return true; case 0x02ul: return false; + default: + return false; } } #endif @@ -406,6 +432,8 @@ static bool nrf91_errata_20(void) return true; case 0x02ul: return false; + default: + return false; } } #endif @@ -431,6 +459,8 @@ static bool nrf91_errata_21(void) return true; case 0x02ul: return true; + default: + return true; } } #endif @@ -456,6 +486,8 @@ static bool nrf91_errata_23(void) return true; case 0x02ul: return true; + default: + return true; } } #endif @@ -481,6 +513,8 @@ static bool nrf91_errata_24(void) return true; case 0x02ul: return true; + default: + return true; } } #endif @@ -506,6 +540,8 @@ static bool nrf91_errata_26(void) return true; case 0x02ul: return true; + default: + return true; } } #endif @@ -531,6 +567,8 @@ static bool nrf91_errata_27(void) return false; case 0x02ul: return true; + default: + return true; } } #endif @@ -556,6 +594,8 @@ static bool nrf91_errata_28(void) return true; case 0x02ul: return true; + default: + return true; } } #endif @@ -581,6 +621,8 @@ static bool nrf91_errata_29(void) return true; case 0x02ul: return true; + default: + return true; } } #endif @@ -606,6 +648,8 @@ static bool nrf91_errata_30(void) return true; case 0x02ul: return true; + default: + return true; } } #endif @@ -631,6 +675,8 @@ static bool nrf91_errata_31(void) return true; case 0x02ul: return true; + default: + return true; } } #endif @@ -656,6 +702,8 @@ static bool nrf91_errata_32(void) return true; case 0x02ul: return true; + default: + return true; } } #endif @@ -681,6 +729,8 @@ static bool nrf91_errata_33(void) return true; case 0x02ul: return true; + default: + return true; } } #endif diff --git a/mdk/nrf_common.ld b/mdk/nrf_common.ld index 1aba217366..fa7858349a 100644 --- a/mdk/nrf_common.ld +++ b/mdk/nrf_common.ld @@ -87,6 +87,7 @@ SECTIONS } > FLASH __exidx_end = .; + . = ALIGN(4); __etext = .; .data : AT (__etext) diff --git a/mdk/nrf_erratas.h b/mdk/nrf_erratas.h index bccc320668..73a87d7d03 100644 --- a/mdk/nrf_erratas.h +++ b/mdk/nrf_erratas.h @@ -35,6 +35,9 @@ POSSIBILITY OF SUCH DAMAGE. #include "nrf.h" +/* Check MDK version to make sure we have the required macros */ +NRF_MDK_VERSION_ASSERT_AT_LEAST(8,34,0); + /*lint ++flb "Enter library region */ #include "nrf51_erratas.h" diff --git a/mdk/nrf_peripherals.h b/mdk/nrf_peripherals.h index c927c7a350..b99f089502 100644 --- a/mdk/nrf_peripherals.h +++ b/mdk/nrf_peripherals.h @@ -35,43 +35,34 @@ POSSIBILITY OF SUCH DAMAGE. /*lint ++flb "Enter library region */ -#if defined(_WIN32) - /* Do not include nrf specific files when building for PC host */ -#elif defined(__unix) - /* Do not include nrf specific files when building for PC host */ -#elif defined(__APPLE__) - /* Do not include nrf specific files when building for PC host */ -#else +#if defined(NRF51) + #include "nrf51_peripherals.h" + +#elif defined (NRF52805_XXAA) + #include "nrf52805_peripherals.h" +#elif defined(NRF52810_XXAA) + #include "nrf52810_peripherals.h" +#elif defined(NRF52811_XXAA) + #include "nrf52811_peripherals.h" +#elif defined(NRF52820_XXAA) + #include "nrf52820_peripherals.h" +#elif defined(NRF52832_XXAA) || defined(NRF52832_XXAB) + #include "nrf52832_peripherals.h" +#elif defined (NRF52833_XXAA) + #include "nrf52833_peripherals.h" +#elif defined(NRF52840_XXAA) + #include "nrf52840_peripherals.h" + +#elif defined (NRF5340_XXAA_APPLICATION) + #include "nrf5340_application_peripherals.h" +#elif defined (NRF5340_XXAA_NETWORK) + #include "nrf5340_network_peripherals.h" - #if defined(NRF51) - #include "nrf51_peripherals.h" - - #elif defined (NRF52805_XXAA) - #include "nrf52805_peripherals.h" - #elif defined(NRF52810_XXAA) - #include "nrf52810_peripherals.h" - #elif defined(NRF52811_XXAA) - #include "nrf52811_peripherals.h" - #elif defined(NRF52820_XXAA) - #include "nrf52820_peripherals.h" - #elif defined(NRF52832_XXAA) || defined(NRF52832_XXAB) - #include "nrf52832_peripherals.h" - #elif defined (NRF52833_XXAA) - #include "nrf52833_peripherals.h" - #elif defined(NRF52840_XXAA) - #include "nrf52840_peripherals.h" - - #elif defined (NRF5340_XXAA_APPLICATION) - #include "nrf5340_application_peripherals.h" - #elif defined (NRF5340_XXAA_NETWORK) - #include "nrf5340_network_peripherals.h" - - #elif defined(NRF9160_XXAA) - #include "nrf9160_peripherals.h" - - #else - #error "Device must be defined. See nrf.h." - #endif +#elif defined(NRF9160_XXAA) + #include "nrf9160_peripherals.h" + +#else + #error "Device must be defined. See nrf.h." #endif /*lint --flb "Leave library region" */ diff --git a/mdk/ses_startup_nrf52805.s b/mdk/ses_startup_nrf52805.s index 0303941c0d..87d7b1cad3 100644 --- a/mdk/ses_startup_nrf52805.s +++ b/mdk/ses_startup_nrf52805.s @@ -166,6 +166,9 @@ Dummy_Handler: .weak RTC1_IRQHandler .thumb_set RTC1_IRQHandler, Dummy_Handler +.weak QDEC_IRQHandler +.thumb_set QDEC_IRQHandler, Dummy_Handler + .weak SWI0_EGU0_IRQHandler .thumb_set SWI0_EGU0_IRQHandler, Dummy_Handler @@ -243,7 +246,7 @@ _vectors: .word CCM_AAR_IRQHandler .word WDT_IRQHandler .word RTC1_IRQHandler - .word 0 /*Reserved */ + .word QDEC_IRQHandler .word 0 /*Reserved */ .word SWI0_EGU0_IRQHandler .word SWI1_EGU1_IRQHandler diff --git a/mdk/ses_startup_nrf_common.s b/mdk/ses_startup_nrf_common.s index 4be4828f9e..f7ede0a0cb 100644 --- a/mdk/ses_startup_nrf_common.s +++ b/mdk/ses_startup_nrf_common.s @@ -38,6 +38,11 @@ * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH * * DAMAGE. * * * + *********************************************************************************** + * * + * This file has been modified by Nordic Semiconductor: * + * To separate out device-specific data * + * * ***********************************************************************************/ /************************************************************************************ @@ -96,13 +101,15 @@ .equ FPU_CPACR_REG, 0xE000ED88 #ifndef STACK_INIT_VAL -#define STACK_INIT_VAL __RAM_segment_end__ +#define STACK_INIT_VAL __RAM1_segment_end__ #endif Reset_Handler: /* Perform prestart tasks. */ b nRFInitialize + +.thumb_func afterInitialize: #ifndef NO_STACK_INIT diff --git a/nrfx.h b/nrfx.h index ac261665ac..ed74bc57b1 100644 --- a/nrfx.h +++ b/nrfx.h @@ -34,6 +34,7 @@ #include #include +#include #include #include diff --git a/soc/nrfx_coredep.h b/soc/nrfx_coredep.h index 23354516bb..15bb9f3b66 100644 --- a/soc/nrfx_coredep.h +++ b/soc/nrfx_coredep.h @@ -56,7 +56,8 @@ #elif defined(NRF51) #define NRFX_DELAY_CPU_FREQ_MHZ 16 #define NRFX_DELAY_DWT_PRESENT 0 -#elif defined(NRF52810_XXAA) || defined(NRF52811_XXAA) || defined(NRF52820_XXAA) +#elif defined(NRF52805_XXAA) || defined(NRF52810_XXAA) || \ + defined(NRF52811_XXAA) || defined(NRF52820_XXAA) #define NRFX_DELAY_CPU_FREQ_MHZ 64 #define NRFX_DELAY_DWT_PRESENT 0 #elif defined(NRF52832_XXAA) || defined(NRF52832_XXAB) || \ @@ -142,7 +143,8 @@ NRF_STATIC_INLINE void nrfx_coredep_delay_us(uint32_t time_us) #if defined(NRF51) // The loop takes 4 cycles: 1 for SUBS, 3 for BHI. #define NRFX_COREDEP_DELAY_US_LOOP_CYCLES 4 - #elif defined(NRF52810_XXAA) || defined(NRF52811_XXAA) || defined(NRF52820_XXAA) + #elif defined(NRF52805_XXAA) || defined(NRF52810_XXAA) || \ + defined(NRF52811_XXAA) || defined(NRF52820_XXAA) // The loop takes 7 cycles: 1 for SUBS, 2 for BHI, 2 wait states // for each instruction. #define NRFX_COREDEP_DELAY_US_LOOP_CYCLES 7 diff --git a/soc/nrfx_irqs.h b/soc/nrfx_irqs.h index a2056bfafc..b3d833351d 100644 --- a/soc/nrfx_irqs.h +++ b/soc/nrfx_irqs.h @@ -34,6 +34,8 @@ #if defined(NRF51) #include +#elif defined(NRF52805_XXAA) + #include #elif defined(NRF52810_XXAA) #include #elif defined(NRF52811_XXAA) diff --git a/soc/nrfx_irqs_nrf52805.h b/soc/nrfx_irqs_nrf52805.h new file mode 100644 index 0000000000..fbbd0a9011 --- /dev/null +++ b/soc/nrfx_irqs_nrf52805.h @@ -0,0 +1,127 @@ +/* + * Copyright (c) 2020, Nordic Semiconductor ASA + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef NRFX_IRQS_NRF52805_H__ +#define NRFX_IRQS_NRF52805_H__ + +#ifdef __cplusplus +extern "C" { +#endif + + +// POWER_CLOCK_IRQn +#define nrfx_power_clock_irq_handler POWER_CLOCK_IRQHandler + +// RADIO_IRQn + +// UARTE0_UART0_IRQn +#if NRFX_CHECK(NRFX_PRS_BOX_2_ENABLED) +#define nrfx_prs_box_2_irq_handler UARTE0_UART0_IRQHandler +#else +#define nrfx_uarte_0_irq_handler UARTE0_UART0_IRQHandler +#define nrfx_uart_0_irq_handler UARTE0_UART0_IRQHandler +#endif + +// TWIM0_TWIS0_TWI0_IRQn +#if NRFX_CHECK(NRFX_PRS_BOX_0_ENABLED) +#define nrfx_prs_box_0_irq_handler TWIM0_TWIS0_TWI0_IRQHandler +#else +#define nrfx_twim_0_irq_handler TWIM0_TWIS0_TWI0_IRQHandler +#define nrfx_twis_0_irq_handler TWIM0_TWIS0_TWI0_IRQHandler +#define nrfx_twi_0_irq_handler TWIM0_TWIS0_TWI0_IRQHandler +#endif + +// SPIM0_SPIS0_SPI0_IRQn +#if NRFX_CHECK(NRFX_PRS_BOX_1_ENABLED) +#define nrfx_prs_box_1_irq_handler SPIM0_SPIS0_SPI0_IRQHandler +#else +#define nrfx_spim_0_irq_handler SPIM0_SPIS0_SPI0_IRQHandler +#define nrfx_spis_0_irq_handler SPIM0_SPIS0_SPI0_IRQHandler +#define nrfx_spi_0_irq_handler SPIM0_SPIS0_SPI0_IRQHandler +#endif + +// GPIOTE_IRQn +#define nrfx_gpiote_irq_handler GPIOTE_IRQHandler + +// SAADC_IRQn +#define nrfx_saadc_irq_handler SAADC_IRQHandler + +// TIMER0_IRQn +#define nrfx_timer_0_irq_handler TIMER0_IRQHandler + +// TIMER1_IRQn +#define nrfx_timer_1_irq_handler TIMER1_IRQHandler + +// TIMER2_IRQn +#define nrfx_timer_2_irq_handler TIMER2_IRQHandler + +// RTC0_IRQn +#define nrfx_rtc_0_irq_handler RTC0_IRQHandler + +// TEMP_IRQn +#define nrfx_temp_irq_handler TEMP_IRQHandler + +// RNG_IRQn +#define nrfx_rng_irq_handler RNG_IRQHandler + +// ECB_IRQn + +// CCM_AAR_IRQn + +// WDT_IRQn +#define nrfx_wdt_0_irq_handler WDT_IRQHandler + +// RTC1_IRQn +#define nrfx_rtc_1_irq_handler RTC1_IRQHandler + +// QDEC_IRQn +#define nrfx_qdec_irq_handler QDEC_IRQHandler + +// SWI0_EGU0_IRQn +#define nrfx_egu_0_irq_handler SWI0_EGU0_IRQHandler + +// SWI1_EGU1_IRQn +#define nrfx_egu_1_irq_handler SWI1_EGU1_IRQHandler + +// SWI2_IRQn + +// SWI3_IRQn + +// SWI4_IRQn + +// SWI5_IRQn + + +#ifdef __cplusplus +} +#endif + +#endif // NRFX_IRQS_NRF52805_H__ diff --git a/soc/nrfx_irqs_nrf52810.h b/soc/nrfx_irqs_nrf52810.h index a38e9f203e..4f5990a512 100644 --- a/soc/nrfx_irqs_nrf52810.h +++ b/soc/nrfx_irqs_nrf52810.h @@ -29,8 +29,8 @@ * POSSIBILITY OF SUCH DAMAGE. */ -#ifndef NRFX_IRQS_NRF52832_H__ -#define NRFX_IRQS_NRF52832_H__ +#ifndef NRFX_IRQS_NRF52810_H__ +#define NRFX_IRQS_NRF52810_H__ #ifdef __cplusplus extern "C" { @@ -133,4 +133,4 @@ extern "C" { } #endif -#endif // NRFX_IRQS_NRF52832_H__ +#endif // NRFX_IRQS_NRF52810_H__ diff --git a/templates/nrfx_config.h b/templates/nrfx_config.h index 7e8ca2dbb0..520bbb0c59 100644 --- a/templates/nrfx_config.h +++ b/templates/nrfx_config.h @@ -34,6 +34,8 @@ #if defined(NRF51) #include +#elif defined(NRF52805_XXAA) + #include #elif defined(NRF52810_XXAA) #include #elif defined(NRF52811_XXAA) diff --git a/templates/nrfx_config_nrf51.h b/templates/nrfx_config_nrf51.h index ae63473a54..5f0e45cf5d 100644 --- a/templates/nrfx_config_nrf51.h +++ b/templates/nrfx_config_nrf51.h @@ -130,6 +130,17 @@ #define NRFX_CLOCK_CONFIG_LF_CAL_ENABLED 0 #endif +// NRFX_CLOCK_CONFIG_LFXO_TWO_STAGE_ENABLED - Enables two-stage LFXO start procedure + +// If set to a non-zero value, LFRC will be started before LFXO and corresponding +// event will be generated. It means that CPU will be woken up when LFRC +// oscillator starts, but user callback will be invoked only after LFXO +// finally starts. + +#ifndef NRFX_CLOCK_CONFIG_LFXO_TWO_STAGE_ENABLED +#define NRFX_CLOCK_CONFIG_LFXO_TWO_STAGE_ENABLED 0 +#endif + // NRFX_CLOCK_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority // <0=> 0 (highest) diff --git a/templates/nrfx_config_nrf52805.h b/templates/nrfx_config_nrf52805.h new file mode 100644 index 0000000000..290e468ac8 --- /dev/null +++ b/templates/nrfx_config_nrf52805.h @@ -0,0 +1,1603 @@ +/* + * Copyright (c) 2020, Nordic Semiconductor ASA + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef NRFX_CONFIG_NRF52805_H__ +#define NRFX_CONFIG_NRF52805_H__ + +#ifndef NRFX_CONFIG_H__ +#error "This file should not be included directly. Include nrfx_config.h instead." +#endif + +// <<< Use Configuration Wizard in Context Menu >>>\n + +// nRF_Drivers + +// NRFX_CLOCK_ENABLED - nrfx_clock - CLOCK peripheral driver +//========================================================== +#ifndef NRFX_CLOCK_ENABLED +#define NRFX_CLOCK_ENABLED 0 +#endif +// NRFX_CLOCK_CONFIG_LF_SRC - LF Clock Source + +// <0=> RC +// <1=> XTAL +// <2=> Synth +// <131073=> External Low Swing +// <196609=> External Full Swing + +#ifndef NRFX_CLOCK_CONFIG_LF_SRC +#define NRFX_CLOCK_CONFIG_LF_SRC 1 +#endif + +// NRFX_CLOCK_CONFIG_LF_CAL_ENABLED - Enables LF Clock Calibration Support + +#ifndef NRFX_CLOCK_CONFIG_LF_CAL_ENABLED +#define NRFX_CLOCK_CONFIG_LF_CAL_ENABLED 0 +#endif + +// NRFX_CLOCK_CONFIG_LFXO_TWO_STAGE_ENABLED - Enables two-stage LFXO start procedure + +// If set to a non-zero value, LFRC will be started before LFXO and corresponding +// event will be generated. It means that CPU will be woken up when LFRC +// oscillator starts, but user callback will be invoked only after LFXO +// finally starts. + +#ifndef NRFX_CLOCK_CONFIG_LFXO_TWO_STAGE_ENABLED +#define NRFX_CLOCK_CONFIG_LFXO_TWO_STAGE_ENABLED 0 +#endif + +// NRFX_CLOCK_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority + +// <0=> 0 (highest) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 + +#ifndef NRFX_CLOCK_DEFAULT_CONFIG_IRQ_PRIORITY +#define NRFX_CLOCK_DEFAULT_CONFIG_IRQ_PRIORITY 7 +#endif + +// NRFX_CLOCK_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef NRFX_CLOCK_CONFIG_LOG_ENABLED +#define NRFX_CLOCK_CONFIG_LOG_ENABLED 0 +#endif +// NRFX_CLOCK_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef NRFX_CLOCK_CONFIG_LOG_LEVEL +#define NRFX_CLOCK_CONFIG_LOG_LEVEL 3 +#endif + +// NRFX_CLOCK_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_CLOCK_CONFIG_INFO_COLOR +#define NRFX_CLOCK_CONFIG_INFO_COLOR 0 +#endif + +// NRFX_CLOCK_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_CLOCK_CONFIG_DEBUG_COLOR +#define NRFX_CLOCK_CONFIG_DEBUG_COLOR 0 +#endif + +// + +// + +// NRFX_EGU_ENABLED - nrfx_egu - EGU peripheral driver. +//========================================================== +#ifndef NRFX_EGU_ENABLED +#define NRFX_EGU_ENABLED 0 +#endif + +// NRFX_EGU0_ENABLED - Enable EGU0 instance. + +#ifndef NRFX_EGU0_ENABLED +#define NRFX_EGU0_ENABLED 0 +#endif + +// NRFX_EGU1_ENABLED - Enable EGU1 instance. + +#ifndef NRFX_EGU1_ENABLED +#define NRFX_EGU1_ENABLED 0 +#endif + +// NRFX_EGU_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority. + +// <0=> 0 (highest) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 + +#ifndef NRFX_EGU_DEFAULT_CONFIG_IRQ_PRIORITY +#define NRFX_EGU_DEFAULT_CONFIG_IRQ_PRIORITY 7 +#endif + +// + +// NRFX_GPIOTE_ENABLED - nrfx_gpiote - GPIOTE peripheral driver +//========================================================== +#ifndef NRFX_GPIOTE_ENABLED +#define NRFX_GPIOTE_ENABLED 0 +#endif +// NRFX_GPIOTE_CONFIG_NUM_OF_LOW_POWER_EVENTS - Number of lower power input pins +#ifndef NRFX_GPIOTE_CONFIG_NUM_OF_LOW_POWER_EVENTS +#define NRFX_GPIOTE_CONFIG_NUM_OF_LOW_POWER_EVENTS 1 +#endif + +// NRFX_GPIOTE_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority + +// <0=> 0 (highest) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 + +#ifndef NRFX_GPIOTE_DEFAULT_CONFIG_IRQ_PRIORITY +#define NRFX_GPIOTE_DEFAULT_CONFIG_IRQ_PRIORITY 7 +#endif + +// NRFX_GPIOTE_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef NRFX_GPIOTE_CONFIG_LOG_ENABLED +#define NRFX_GPIOTE_CONFIG_LOG_ENABLED 0 +#endif +// NRFX_GPIOTE_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef NRFX_GPIOTE_CONFIG_LOG_LEVEL +#define NRFX_GPIOTE_CONFIG_LOG_LEVEL 3 +#endif + +// NRFX_GPIOTE_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_GPIOTE_CONFIG_INFO_COLOR +#define NRFX_GPIOTE_CONFIG_INFO_COLOR 0 +#endif + +// NRFX_GPIOTE_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_GPIOTE_CONFIG_DEBUG_COLOR +#define NRFX_GPIOTE_CONFIG_DEBUG_COLOR 0 +#endif + +// + +// + +// NRFX_NVMC_ENABLED - nrfx_nvmc - NVMC peripheral driver +//========================================================== +#ifndef NRFX_NVMC_ENABLED +#define NRFX_NVMC_ENABLED 0 +#endif + +// + +// NRFX_POWER_ENABLED - nrfx_power - POWER peripheral driver +//========================================================== +#ifndef NRFX_POWER_ENABLED +#define NRFX_POWER_ENABLED 0 +#endif +// NRFX_POWER_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority + +// <0=> 0 (highest) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 + +#ifndef NRFX_POWER_DEFAULT_CONFIG_IRQ_PRIORITY +#define NRFX_POWER_DEFAULT_CONFIG_IRQ_PRIORITY 7 +#endif + +// + +// NRFX_PPI_ENABLED - nrfx_ppi - PPI peripheral allocator +//========================================================== +#ifndef NRFX_PPI_ENABLED +#define NRFX_PPI_ENABLED 0 +#endif +// NRFX_PPI_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef NRFX_PPI_CONFIG_LOG_ENABLED +#define NRFX_PPI_CONFIG_LOG_ENABLED 0 +#endif +// NRFX_PPI_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef NRFX_PPI_CONFIG_LOG_LEVEL +#define NRFX_PPI_CONFIG_LOG_LEVEL 3 +#endif + +// NRFX_PPI_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_PPI_CONFIG_INFO_COLOR +#define NRFX_PPI_CONFIG_INFO_COLOR 0 +#endif + +// NRFX_PPI_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_PPI_CONFIG_DEBUG_COLOR +#define NRFX_PPI_CONFIG_DEBUG_COLOR 0 +#endif + +// + +// + +// NRFX_PRS_ENABLED - nrfx_prs - Peripheral Resource Sharing module +//========================================================== +#ifndef NRFX_PRS_ENABLED +#define NRFX_PRS_ENABLED 0 +#endif +// NRFX_PRS_BOX_0_ENABLED - Enables box 0 in the module. + + +#ifndef NRFX_PRS_BOX_0_ENABLED +#define NRFX_PRS_BOX_0_ENABLED 0 +#endif + +// NRFX_PRS_BOX_1_ENABLED - Enables box 1 in the module. + + +#ifndef NRFX_PRS_BOX_1_ENABLED +#define NRFX_PRS_BOX_1_ENABLED 0 +#endif + +// NRFX_PRS_BOX_2_ENABLED - Enables box 2 in the module. + + +#ifndef NRFX_PRS_BOX_2_ENABLED +#define NRFX_PRS_BOX_2_ENABLED 0 +#endif + + +// NRFX_PRS_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef NRFX_PRS_CONFIG_LOG_ENABLED +#define NRFX_PRS_CONFIG_LOG_ENABLED 0 +#endif +// NRFX_PRS_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef NRFX_PRS_CONFIG_LOG_LEVEL +#define NRFX_PRS_CONFIG_LOG_LEVEL 3 +#endif + +// NRFX_PRS_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_PRS_CONFIG_INFO_COLOR +#define NRFX_PRS_CONFIG_INFO_COLOR 0 +#endif + +// NRFX_PRS_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_PRS_CONFIG_DEBUG_COLOR +#define NRFX_PRS_CONFIG_DEBUG_COLOR 0 +#endif + +// + +// + +// NRFX_QDEC_ENABLED - nrfx_qdec - QDEC peripheral driver +//========================================================== +#ifndef NRFX_QDEC_ENABLED +#define NRFX_QDEC_ENABLED 0 +#endif + +// NRFX_QDEC_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority + +// <0=> 0 (highest) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 + +#ifndef NRFX_QDEC_DEFAULT_CONFIG_IRQ_PRIORITY +#define NRFX_QDEC_DEFAULT_CONFIG_IRQ_PRIORITY 7 +#endif + +// NRFX_QDEC_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef NRFX_QDEC_CONFIG_LOG_ENABLED +#define NRFX_QDEC_CONFIG_LOG_ENABLED 0 +#endif +// NRFX_QDEC_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef NRFX_QDEC_CONFIG_LOG_LEVEL +#define NRFX_QDEC_CONFIG_LOG_LEVEL 3 +#endif + +// NRFX_QDEC_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_QDEC_CONFIG_INFO_COLOR +#define NRFX_QDEC_CONFIG_INFO_COLOR 0 +#endif + +// NRFX_QDEC_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_QDEC_CONFIG_DEBUG_COLOR +#define NRFX_QDEC_CONFIG_DEBUG_COLOR 0 +#endif + +// + +// + +// NRFX_RNG_ENABLED - nrfx_rng - RNG peripheral driver +//========================================================== +#ifndef NRFX_RNG_ENABLED +#define NRFX_RNG_ENABLED 0 +#endif + +// NRFX_RNG_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority + +// <0=> 0 (highest) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 + +#ifndef NRFX_RNG_DEFAULT_CONFIG_IRQ_PRIORITY +#define NRFX_RNG_DEFAULT_CONFIG_IRQ_PRIORITY 7 +#endif + +// NRFX_RNG_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef NRFX_RNG_CONFIG_LOG_ENABLED +#define NRFX_RNG_CONFIG_LOG_ENABLED 0 +#endif +// NRFX_RNG_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef NRFX_RNG_CONFIG_LOG_LEVEL +#define NRFX_RNG_CONFIG_LOG_LEVEL 3 +#endif + +// NRFX_RNG_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_RNG_CONFIG_INFO_COLOR +#define NRFX_RNG_CONFIG_INFO_COLOR 0 +#endif + +// NRFX_RNG_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_RNG_CONFIG_DEBUG_COLOR +#define NRFX_RNG_CONFIG_DEBUG_COLOR 0 +#endif + +// + +// + +// NRFX_RTC_ENABLED - nrfx_rtc - RTC peripheral driver +//========================================================== +#ifndef NRFX_RTC_ENABLED +#define NRFX_RTC_ENABLED 0 +#endif +// NRFX_RTC0_ENABLED - Enable RTC0 instance + +#ifndef NRFX_RTC0_ENABLED +#define NRFX_RTC0_ENABLED 0 +#endif + +// NRFX_RTC1_ENABLED - Enable RTC1 instance + +#ifndef NRFX_RTC1_ENABLED +#define NRFX_RTC1_ENABLED 0 +#endif + +// NRFX_RTC_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority + +// <0=> 0 (highest) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 + +#ifndef NRFX_RTC_DEFAULT_CONFIG_IRQ_PRIORITY +#define NRFX_RTC_DEFAULT_CONFIG_IRQ_PRIORITY 7 +#endif + +// NRFX_RTC_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef NRFX_RTC_CONFIG_LOG_ENABLED +#define NRFX_RTC_CONFIG_LOG_ENABLED 0 +#endif +// NRFX_RTC_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef NRFX_RTC_CONFIG_LOG_LEVEL +#define NRFX_RTC_CONFIG_LOG_LEVEL 3 +#endif + +// NRFX_RTC_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_RTC_CONFIG_INFO_COLOR +#define NRFX_RTC_CONFIG_INFO_COLOR 0 +#endif + +// NRFX_RTC_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_RTC_CONFIG_DEBUG_COLOR +#define NRFX_RTC_CONFIG_DEBUG_COLOR 0 +#endif + +// + +// + +// NRFX_SAADC_ENABLED - nrfx_saadc - SAADC peripheral driver +//========================================================== +#ifndef NRFX_SAADC_ENABLED +#define NRFX_SAADC_ENABLED 0 +#endif + +// NRFX_SAADC_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority + +// <0=> 0 (highest) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 + +#ifndef NRFX_SAADC_DEFAULT_CONFIG_IRQ_PRIORITY +#define NRFX_SAADC_DEFAULT_CONFIG_IRQ_PRIORITY 7 +#endif + +// NRFX_SAADC_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef NRFX_SAADC_CONFIG_LOG_ENABLED +#define NRFX_SAADC_CONFIG_LOG_ENABLED 0 +#endif + +// NRFX_SAADC_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef NRFX_SAADC_CONFIG_LOG_LEVEL +#define NRFX_SAADC_CONFIG_LOG_LEVEL 3 +#endif + +// NRFX_SAADC_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_SAADC_CONFIG_INFO_COLOR +#define NRFX_SAADC_CONFIG_INFO_COLOR 0 +#endif + +// NRFX_SAADC_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_SAADC_CONFIG_DEBUG_COLOR +#define NRFX_SAADC_CONFIG_DEBUG_COLOR 0 +#endif + +// + +// + +// NRFX_SPIM_ENABLED - nrfx_spim - SPIM peripheral driver +//========================================================== +#ifndef NRFX_SPIM_ENABLED +#define NRFX_SPIM_ENABLED 0 +#endif + +// NRFX_SPIM0_ENABLED - Enable SPIM0 instance + +#ifndef NRFX_SPIM0_ENABLED +#define NRFX_SPIM0_ENABLED 0 +#endif + +// NRFX_SPIM_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority + +// <0=> 0 (highest) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 + +#ifndef NRFX_SPIM_DEFAULT_CONFIG_IRQ_PRIORITY +#define NRFX_SPIM_DEFAULT_CONFIG_IRQ_PRIORITY 7 +#endif + +// NRFX_SPIM_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef NRFX_SPIM_CONFIG_LOG_ENABLED +#define NRFX_SPIM_CONFIG_LOG_ENABLED 0 +#endif +// NRFX_SPIM_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef NRFX_SPIM_CONFIG_LOG_LEVEL +#define NRFX_SPIM_CONFIG_LOG_LEVEL 3 +#endif + +// NRFX_SPIM_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_SPIM_CONFIG_INFO_COLOR +#define NRFX_SPIM_CONFIG_INFO_COLOR 0 +#endif + +// NRFX_SPIM_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_SPIM_CONFIG_DEBUG_COLOR +#define NRFX_SPIM_CONFIG_DEBUG_COLOR 0 +#endif + +// + +// + +// NRFX_SPIS_ENABLED - nrfx_spis - SPIS peripheral driver +//========================================================== +#ifndef NRFX_SPIS_ENABLED +#define NRFX_SPIS_ENABLED 0 +#endif +// NRFX_SPIS0_ENABLED - Enable SPIS0 instance + + +#ifndef NRFX_SPIS0_ENABLED +#define NRFX_SPIS0_ENABLED 0 +#endif + +// NRFX_SPIS_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority + +// <0=> 0 (highest) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 + +#ifndef NRFX_SPIS_DEFAULT_CONFIG_IRQ_PRIORITY +#define NRFX_SPIS_DEFAULT_CONFIG_IRQ_PRIORITY 7 +#endif + +// NRFX_SPIS_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef NRFX_SPIS_CONFIG_LOG_ENABLED +#define NRFX_SPIS_CONFIG_LOG_ENABLED 0 +#endif +// NRFX_SPIS_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef NRFX_SPIS_CONFIG_LOG_LEVEL +#define NRFX_SPIS_CONFIG_LOG_LEVEL 3 +#endif + +// NRFX_SPIS_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_SPIS_CONFIG_INFO_COLOR +#define NRFX_SPIS_CONFIG_INFO_COLOR 0 +#endif + +// NRFX_SPIS_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_SPIS_CONFIG_DEBUG_COLOR +#define NRFX_SPIS_CONFIG_DEBUG_COLOR 0 +#endif + +// + +// + +// NRFX_SPI_ENABLED - nrfx_spi - SPI peripheral driver +//========================================================== +#ifndef NRFX_SPI_ENABLED +#define NRFX_SPI_ENABLED 0 +#endif +// NRFX_SPI0_ENABLED - Enable SPI0 instance + + +#ifndef NRFX_SPI0_ENABLED +#define NRFX_SPI0_ENABLED 0 +#endif + +// NRFX_SPI_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority + +// <0=> 0 (highest) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 + +#ifndef NRFX_SPI_DEFAULT_CONFIG_IRQ_PRIORITY +#define NRFX_SPI_DEFAULT_CONFIG_IRQ_PRIORITY 7 +#endif + +// NRFX_SPI_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef NRFX_SPI_CONFIG_LOG_ENABLED +#define NRFX_SPI_CONFIG_LOG_ENABLED 0 +#endif +// NRFX_SPI_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef NRFX_SPI_CONFIG_LOG_LEVEL +#define NRFX_SPI_CONFIG_LOG_LEVEL 3 +#endif + +// NRFX_SPI_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_SPI_CONFIG_INFO_COLOR +#define NRFX_SPI_CONFIG_INFO_COLOR 0 +#endif + +// NRFX_SPI_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_SPI_CONFIG_DEBUG_COLOR +#define NRFX_SPI_CONFIG_DEBUG_COLOR 0 +#endif + +// + +// + +// NRFX_SYSTICK_ENABLED - nrfx_systick - ARM(R) SysTick driver + + +#ifndef NRFX_SYSTICK_ENABLED +#define NRFX_SYSTICK_ENABLED 0 +#endif + +// NRFX_TEMP_ENABLED - nrfx_temp - TEMP peripheral driver +//========================================================== +#ifndef NRFX_TEMP_ENABLED +#define NRFX_TEMP_ENABLED 0 +#endif + +// NRFX_TEMP_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority + +// <0=> 0 (highest) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 + +#ifndef NRFX_TEMP_DEFAULT_CONFIG_IRQ_PRIORITY +#define NRFX_TEMP_DEFAULT_CONFIG_IRQ_PRIORITY 7 +#endif + +// + +// NRFX_TIMER_ENABLED - nrfx_timer - TIMER periperal driver +//========================================================== +#ifndef NRFX_TIMER_ENABLED +#define NRFX_TIMER_ENABLED 0 +#endif + +// NRFX_TIMER0_ENABLED - Enable TIMER0 instance + +#ifndef NRFX_TIMER0_ENABLED +#define NRFX_TIMER0_ENABLED 0 +#endif + +// NRFX_TIMER1_ENABLED - Enable TIMER1 instance + +#ifndef NRFX_TIMER1_ENABLED +#define NRFX_TIMER1_ENABLED 0 +#endif + +// NRFX_TIMER2_ENABLED - Enable TIMER2 instance + +#ifndef NRFX_TIMER2_ENABLED +#define NRFX_TIMER2_ENABLED 0 +#endif + +// NRFX_TIMER_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority + +// <0=> 0 (highest) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 + +#ifndef NRFX_TIMER_DEFAULT_CONFIG_IRQ_PRIORITY +#define NRFX_TIMER_DEFAULT_CONFIG_IRQ_PRIORITY 7 +#endif + +// NRFX_TIMER_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef NRFX_TIMER_CONFIG_LOG_ENABLED +#define NRFX_TIMER_CONFIG_LOG_ENABLED 0 +#endif +// NRFX_TIMER_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef NRFX_TIMER_CONFIG_LOG_LEVEL +#define NRFX_TIMER_CONFIG_LOG_LEVEL 3 +#endif + +// NRFX_TIMER_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_TIMER_CONFIG_INFO_COLOR +#define NRFX_TIMER_CONFIG_INFO_COLOR 0 +#endif + +// NRFX_TIMER_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_TIMER_CONFIG_DEBUG_COLOR +#define NRFX_TIMER_CONFIG_DEBUG_COLOR 0 +#endif + +// + +// + +// NRFX_TWIM_ENABLED - nrfx_twim - TWIM peripheral driver +//========================================================== +#ifndef NRFX_TWIM_ENABLED +#define NRFX_TWIM_ENABLED 0 +#endif + +// NRFX_TWIM0_ENABLED - Enable TWIM0 instance + +#ifndef NRFX_TWIM0_ENABLED +#define NRFX_TWIM0_ENABLED 0 +#endif + +// NRFX_TWIM_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority + +// <0=> 0 (highest) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 + +#ifndef NRFX_TWIM_DEFAULT_CONFIG_IRQ_PRIORITY +#define NRFX_TWIM_DEFAULT_CONFIG_IRQ_PRIORITY 7 +#endif + +// NRFX_TWIM_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef NRFX_TWIM_CONFIG_LOG_ENABLED +#define NRFX_TWIM_CONFIG_LOG_ENABLED 0 +#endif +// NRFX_TWIM_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef NRFX_TWIM_CONFIG_LOG_LEVEL +#define NRFX_TWIM_CONFIG_LOG_LEVEL 3 +#endif + +// NRFX_TWIM_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_TWIM_CONFIG_INFO_COLOR +#define NRFX_TWIM_CONFIG_INFO_COLOR 0 +#endif + +// NRFX_TWIM_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_TWIM_CONFIG_DEBUG_COLOR +#define NRFX_TWIM_CONFIG_DEBUG_COLOR 0 +#endif + +// + +// + +// NRFX_TWIS_ENABLED - nrfx_twis - TWIS peripheral driver +//========================================================== +#ifndef NRFX_TWIS_ENABLED +#define NRFX_TWIS_ENABLED 0 +#endif + +// NRFX_TWIS0_ENABLED - Enable TWIS0 instance + +#ifndef NRFX_TWIS0_ENABLED +#define NRFX_TWIS0_ENABLED 0 +#endif + +// NRFX_TWIS_ASSUME_INIT_AFTER_RESET_ONLY - Assume that any instance would be initialized only once + +// Optimization flag. Registers used by TWIS are shared by other peripherals. Normally, during initialization driver tries to clear all registers to known state before doing the initialization itself. This gives initialization safe procedure, no matter when it would be called. If you activate TWIS only once and do never uninitialize it - set this flag to 1 what gives more optimal code. + +#ifndef NRFX_TWIS_ASSUME_INIT_AFTER_RESET_ONLY +#define NRFX_TWIS_ASSUME_INIT_AFTER_RESET_ONLY 0 +#endif + +// NRFX_TWIS_NO_SYNC_MODE - Remove support for synchronous mode + +// Synchronous mode would be used in specific situations. And it uses some additional code and data memory to safely process state machine by polling it in status functions. If this functionality is not required it may be disabled to free some resources. + +#ifndef NRFX_TWIS_NO_SYNC_MODE +#define NRFX_TWIS_NO_SYNC_MODE 0 +#endif + +// NRFX_TWIS_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority + +// <0=> 0 (highest) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 + +#ifndef NRFX_TWIS_DEFAULT_CONFIG_IRQ_PRIORITY +#define NRFX_TWIS_DEFAULT_CONFIG_IRQ_PRIORITY 7 +#endif + +// NRFX_TWIS_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef NRFX_TWIS_CONFIG_LOG_ENABLED +#define NRFX_TWIS_CONFIG_LOG_ENABLED 0 +#endif +// NRFX_TWIS_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef NRFX_TWIS_CONFIG_LOG_LEVEL +#define NRFX_TWIS_CONFIG_LOG_LEVEL 3 +#endif + +// NRFX_TWIS_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_TWIS_CONFIG_INFO_COLOR +#define NRFX_TWIS_CONFIG_INFO_COLOR 0 +#endif + +// NRFX_TWIS_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_TWIS_CONFIG_DEBUG_COLOR +#define NRFX_TWIS_CONFIG_DEBUG_COLOR 0 +#endif + +// + +// + +// NRFX_TWI_ENABLED - nrfx_twi - TWI peripheral driver +//========================================================== +#ifndef NRFX_TWI_ENABLED +#define NRFX_TWI_ENABLED 0 +#endif + +// NRFX_TWI0_ENABLED - Enable TWI0 instance + +#ifndef NRFX_TWI0_ENABLED +#define NRFX_TWI0_ENABLED 0 +#endif + +// NRFX_TWI_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority + +// <0=> 0 (highest) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 + +#ifndef NRFX_TWI_DEFAULT_CONFIG_IRQ_PRIORITY +#define NRFX_TWI_DEFAULT_CONFIG_IRQ_PRIORITY 7 +#endif + +// NRFX_TWI_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef NRFX_TWI_CONFIG_LOG_ENABLED +#define NRFX_TWI_CONFIG_LOG_ENABLED 0 +#endif +// NRFX_TWI_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef NRFX_TWI_CONFIG_LOG_LEVEL +#define NRFX_TWI_CONFIG_LOG_LEVEL 3 +#endif + +// NRFX_TWI_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_TWI_CONFIG_INFO_COLOR +#define NRFX_TWI_CONFIG_INFO_COLOR 0 +#endif + +// NRFX_TWI_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_TWI_CONFIG_DEBUG_COLOR +#define NRFX_TWI_CONFIG_DEBUG_COLOR 0 +#endif + +// + +// + +// NRFX_UARTE_ENABLED - nrfx_uarte - UARTE peripheral driver +//========================================================== +#ifndef NRFX_UARTE_ENABLED +#define NRFX_UARTE_ENABLED 0 +#endif + +// NRFX_UARTE0_ENABLED - Enable UARTE0 instance + +#ifndef NRFX_UARTE0_ENABLED +#define NRFX_UARTE0_ENABLED 0 +#endif + +// NRFX_UARTE_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority + +// <0=> 0 (highest) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 + +#ifndef NRFX_UARTE_DEFAULT_CONFIG_IRQ_PRIORITY +#define NRFX_UARTE_DEFAULT_CONFIG_IRQ_PRIORITY 7 +#endif + +// NRFX_UARTE_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef NRFX_UARTE_CONFIG_LOG_ENABLED +#define NRFX_UARTE_CONFIG_LOG_ENABLED 0 +#endif +// NRFX_UARTE_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef NRFX_UARTE_CONFIG_LOG_LEVEL +#define NRFX_UARTE_CONFIG_LOG_LEVEL 3 +#endif + +// NRFX_UARTE_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_UARTE_CONFIG_INFO_COLOR +#define NRFX_UARTE_CONFIG_INFO_COLOR 0 +#endif + +// NRFX_UARTE_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_UARTE_CONFIG_DEBUG_COLOR +#define NRFX_UARTE_CONFIG_DEBUG_COLOR 0 +#endif + +// + +// + +// NRFX_UART_ENABLED - nrfx_uart - UART peripheral driver +//========================================================== +#ifndef NRFX_UART_ENABLED +#define NRFX_UART_ENABLED 0 +#endif + +// NRFX_UART0_ENABLED - Enable UART0 instance + +#ifndef NRFX_UART0_ENABLED +#define NRFX_UART0_ENABLED 0 +#endif + +// NRFX_UART_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority + +// <0=> 0 (highest) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 + +#ifndef NRFX_UART_DEFAULT_CONFIG_IRQ_PRIORITY +#define NRFX_UART_DEFAULT_CONFIG_IRQ_PRIORITY 7 +#endif + +// NRFX_UART_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef NRFX_UART_CONFIG_LOG_ENABLED +#define NRFX_UART_CONFIG_LOG_ENABLED 0 +#endif +// NRFX_UART_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef NRFX_UART_CONFIG_LOG_LEVEL +#define NRFX_UART_CONFIG_LOG_LEVEL 3 +#endif + +// NRFX_UART_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_UART_CONFIG_INFO_COLOR +#define NRFX_UART_CONFIG_INFO_COLOR 0 +#endif + +// NRFX_UART_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_UART_CONFIG_DEBUG_COLOR +#define NRFX_UART_CONFIG_DEBUG_COLOR 0 +#endif + +// + +// + +// NRFX_WDT_ENABLED - nrfx_wdt - WDT peripheral driver +//========================================================== +#ifndef NRFX_WDT_ENABLED +#define NRFX_WDT_ENABLED 0 +#endif + +// NRFX_WDT0_ENABLED - Enable WDT0 instance + +#ifndef NRFX_WDT0_ENABLED +#define NRFX_WDT0_ENABLED 0 +#endif + +// NRFX_WDT_CONFIG_NO_IRQ - Remove WDT IRQ handling from WDT driver + +// <0=> Include WDT IRQ handling +// <1=> Remove WDT IRQ handling + +#ifndef NRFX_WDT_CONFIG_NO_IRQ +#define NRFX_WDT_CONFIG_NO_IRQ 0 +#endif + +// NRFX_WDT_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority + +// <0=> 0 (highest) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 + +#ifndef NRFX_WDT_DEFAULT_CONFIG_IRQ_PRIORITY +#define NRFX_WDT_DEFAULT_CONFIG_IRQ_PRIORITY 7 +#endif + +// NRFX_WDT_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef NRFX_WDT_CONFIG_LOG_ENABLED +#define NRFX_WDT_CONFIG_LOG_ENABLED 0 +#endif +// NRFX_WDT_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef NRFX_WDT_CONFIG_LOG_LEVEL +#define NRFX_WDT_CONFIG_LOG_LEVEL 3 +#endif + +// NRFX_WDT_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_WDT_CONFIG_INFO_COLOR +#define NRFX_WDT_CONFIG_INFO_COLOR 0 +#endif + +// NRFX_WDT_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_WDT_CONFIG_DEBUG_COLOR +#define NRFX_WDT_CONFIG_DEBUG_COLOR 0 +#endif + +// + +// + +// + +#endif // NRFX_CONFIG_NRF52805_H__ diff --git a/templates/nrfx_config_nrf52810.h b/templates/nrfx_config_nrf52810.h index 6f56361ead..cd7015115c 100644 --- a/templates/nrfx_config_nrf52810.h +++ b/templates/nrfx_config_nrf52810.h @@ -63,6 +63,17 @@ #define NRFX_CLOCK_CONFIG_LF_CAL_ENABLED 0 #endif +// NRFX_CLOCK_CONFIG_LFXO_TWO_STAGE_ENABLED - Enables two-stage LFXO start procedure + +// If set to a non-zero value, LFRC will be started before LFXO and corresponding +// event will be generated. It means that CPU will be woken up when LFRC +// oscillator starts, but user callback will be invoked only after LFXO +// finally starts. + +#ifndef NRFX_CLOCK_CONFIG_LFXO_TWO_STAGE_ENABLED +#define NRFX_CLOCK_CONFIG_LFXO_TWO_STAGE_ENABLED 0 +#endif + // NRFX_CLOCK_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority // <0=> 0 (highest) diff --git a/templates/nrfx_config_nrf52811.h b/templates/nrfx_config_nrf52811.h index cd68d7ff9f..43e1bbd3a4 100644 --- a/templates/nrfx_config_nrf52811.h +++ b/templates/nrfx_config_nrf52811.h @@ -63,6 +63,17 @@ #define NRFX_CLOCK_CONFIG_LF_CAL_ENABLED 0 #endif +// NRFX_CLOCK_CONFIG_LFXO_TWO_STAGE_ENABLED - Enables two-stage LFXO start procedure + +// If set to a non-zero value, LFRC will be started before LFXO and corresponding +// event will be generated. It means that CPU will be woken up when LFRC +// oscillator starts, but user callback will be invoked only after LFXO +// finally starts. + +#ifndef NRFX_CLOCK_CONFIG_LFXO_TWO_STAGE_ENABLED +#define NRFX_CLOCK_CONFIG_LFXO_TWO_STAGE_ENABLED 0 +#endif + // NRFX_CLOCK_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority // <0=> 0 (highest) diff --git a/templates/nrfx_config_nrf52820.h b/templates/nrfx_config_nrf52820.h index 9004fce609..f22a2145b1 100644 --- a/templates/nrfx_config_nrf52820.h +++ b/templates/nrfx_config_nrf52820.h @@ -63,6 +63,17 @@ #define NRFX_CLOCK_CONFIG_LF_CAL_ENABLED 0 #endif +// NRFX_CLOCK_CONFIG_LFXO_TWO_STAGE_ENABLED - Enables two-stage LFXO start procedure + +// If set to a non-zero value, LFRC will be started before LFXO and corresponding +// event will be generated. It means that CPU will be woken up when LFRC +// oscillator starts, but user callback will be invoked only after LFXO +// finally starts. + +#ifndef NRFX_CLOCK_CONFIG_LFXO_TWO_STAGE_ENABLED +#define NRFX_CLOCK_CONFIG_LFXO_TWO_STAGE_ENABLED 0 +#endif + // NRFX_CLOCK_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority // <0=> 0 (highest) diff --git a/templates/nrfx_config_nrf52832.h b/templates/nrfx_config_nrf52832.h index fb2e6d0370..e266d12454 100644 --- a/templates/nrfx_config_nrf52832.h +++ b/templates/nrfx_config_nrf52832.h @@ -63,6 +63,17 @@ #define NRFX_CLOCK_CONFIG_LF_CAL_ENABLED 0 #endif +// NRFX_CLOCK_CONFIG_LFXO_TWO_STAGE_ENABLED - Enables two-stage LFXO start procedure + +// If set to a non-zero value, LFRC will be started before LFXO and corresponding +// event will be generated. It means that CPU will be woken up when LFRC +// oscillator starts, but user callback will be invoked only after LFXO +// finally starts. + +#ifndef NRFX_CLOCK_CONFIG_LFXO_TWO_STAGE_ENABLED +#define NRFX_CLOCK_CONFIG_LFXO_TWO_STAGE_ENABLED 0 +#endif + // NRFX_CLOCK_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority // <0=> 0 (highest) diff --git a/templates/nrfx_config_nrf52833.h b/templates/nrfx_config_nrf52833.h index 94c79b57a0..da93dcf2cf 100644 --- a/templates/nrfx_config_nrf52833.h +++ b/templates/nrfx_config_nrf52833.h @@ -63,6 +63,17 @@ #define NRFX_CLOCK_CONFIG_LF_CAL_ENABLED 0 #endif +// NRFX_CLOCK_CONFIG_LFXO_TWO_STAGE_ENABLED - Enables two-stage LFXO start procedure + +// If set to a non-zero value, LFRC will be started before LFXO and corresponding +// event will be generated. It means that CPU will be woken up when LFRC +// oscillator starts, but user callback will be invoked only after LFXO +// finally starts. + +#ifndef NRFX_CLOCK_CONFIG_LFXO_TWO_STAGE_ENABLED +#define NRFX_CLOCK_CONFIG_LFXO_TWO_STAGE_ENABLED 0 +#endif + // NRFX_CLOCK_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority // <0=> 0 (highest) diff --git a/templates/nrfx_config_nrf52840.h b/templates/nrfx_config_nrf52840.h index bf24f04dcd..75a2648518 100644 --- a/templates/nrfx_config_nrf52840.h +++ b/templates/nrfx_config_nrf52840.h @@ -63,6 +63,17 @@ #define NRFX_CLOCK_CONFIG_LF_CAL_ENABLED 0 #endif +// NRFX_CLOCK_CONFIG_LFXO_TWO_STAGE_ENABLED - Enables two-stage LFXO start procedure + +// If set to a non-zero value, LFRC will be started before LFXO and corresponding +// event will be generated. It means that CPU will be woken up when LFRC +// oscillator starts, but user callback will be invoked only after LFXO +// finally starts. + +#ifndef NRFX_CLOCK_CONFIG_LFXO_TWO_STAGE_ENABLED +#define NRFX_CLOCK_CONFIG_LFXO_TWO_STAGE_ENABLED 0 +#endif + // NRFX_CLOCK_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority // <0=> 0 (highest) diff --git a/templates/nrfx_config_nrf5340_application.h b/templates/nrfx_config_nrf5340_application.h index ec64a91e19..a93d1d25cd 100644 --- a/templates/nrfx_config_nrf5340_application.h +++ b/templates/nrfx_config_nrf5340_application.h @@ -168,6 +168,17 @@ #define NRFX_CLOCK_CONFIG_LF_CAL_ENABLED 0 #endif +// NRFX_CLOCK_CONFIG_LFXO_TWO_STAGE_ENABLED - Enables two-stage LFXO start procedure + +// If set to a non-zero value, LFRC will be started before LFXO and corresponding +// event will be generated. It means that CPU will be woken up when LFRC +// oscillator starts, but user callback will be invoked only after LFXO +// finally starts. + +#ifndef NRFX_CLOCK_CONFIG_LFXO_TWO_STAGE_ENABLED +#define NRFX_CLOCK_CONFIG_LFXO_TWO_STAGE_ENABLED 0 +#endif + // NRFX_CLOCK_CONFIG_HFCLK192M_SRC - HFCLK192M source. // <0=> HFINT diff --git a/templates/nrfx_config_nrf5340_network.h b/templates/nrfx_config_nrf5340_network.h index a4a6806ab1..1a6489c5a2 100644 --- a/templates/nrfx_config_nrf5340_network.h +++ b/templates/nrfx_config_nrf5340_network.h @@ -109,6 +109,17 @@ #define NRFX_CLOCK_CONFIG_LF_CAL_ENABLED 0 #endif +// NRFX_CLOCK_CONFIG_LFXO_TWO_STAGE_ENABLED - Enables two-stage LFXO start procedure + +// If set to a non-zero value, LFRC will be started before LFXO and corresponding +// event will be generated. It means that CPU will be woken up when LFRC +// oscillator starts, but user callback will be invoked only after LFXO +// finally starts. + +#ifndef NRFX_CLOCK_CONFIG_LFXO_TWO_STAGE_ENABLED +#define NRFX_CLOCK_CONFIG_LFXO_TWO_STAGE_ENABLED 0 +#endif + // NRFX_CLOCK_CONFIG_HFCLK192M_SRC - HFCLK192M source. // <0=> HFINT diff --git a/templates/nrfx_config_nrf9160.h b/templates/nrfx_config_nrf9160.h index c06e3ca8de..4ab38dedc9 100644 --- a/templates/nrfx_config_nrf9160.h +++ b/templates/nrfx_config_nrf9160.h @@ -139,6 +139,17 @@ #define NRFX_CLOCK_CONFIG_LF_SRC 2 #endif +// NRFX_CLOCK_CONFIG_LFXO_TWO_STAGE_ENABLED - Enables two-stage LFXO start procedure + +// If set to a non-zero value, LFRC will be started before LFXO and corresponding +// event will be generated. It means that CPU will be woken up when LFRC +// oscillator starts, but user callback will be invoked only after LFXO +// finally starts. + +#ifndef NRFX_CLOCK_CONFIG_LFXO_TWO_STAGE_ENABLED +#define NRFX_CLOCK_CONFIG_LFXO_TWO_STAGE_ENABLED 0 +#endif + // NRFX_CLOCK_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority. // <0=> 0 (highest) diff --git a/templates/nrfx_glue.h b/templates/nrfx_glue.h index 316a408563..59d8b75b22 100644 --- a/templates/nrfx_glue.h +++ b/templates/nrfx_glue.h @@ -231,6 +231,15 @@ extern "C" { //------------------------------------------------------------------------------ +/** + * @brief When set to a non-zero value, this macro specifies that inside HALs + * the event registers are read back after clearing, on devices that + * otherwise could defer the actual register modification. + */ +#define NRFX_EVENT_READBACK_ENABLED 1 + +//------------------------------------------------------------------------------ + /** @brief Bitmask that defines DPPI channels that are reserved for use outside of the nrfx library. */ #define NRFX_DPPI_CHANNELS_USED 0