From 3521c97df0b9549daecf867fb588f62819c317b4 Mon Sep 17 00:00:00 2001 From: Nikodem Kastelik Date: Wed, 15 Dec 2021 18:48:39 +0100 Subject: [PATCH] nrfx 2.7.0 release --- CHANGELOG.md | 10 + doc/nrfx.doxyfile | 2 +- drivers/include/nrfx_i2s.h | 14 ++ drivers/include/nrfx_pdm.h | 14 ++ drivers/include/nrfx_pwm.h | 30 ++- drivers/include/nrfx_qdec.h | 34 +++- drivers/include/nrfx_qspi.h | 24 ++- drivers/include/nrfx_spi.h | 62 ++++--- drivers/include/nrfx_spim.h | 84 +++++---- drivers/include/nrfx_spis.h | 36 ++-- drivers/include/nrfx_twi.h | 14 ++ drivers/include/nrfx_twim.h | 14 ++ drivers/include/nrfx_twis.h | 26 ++- drivers/include/nrfx_uart.h | 14 ++ drivers/include/nrfx_uarte.h | 14 ++ drivers/src/nrfx_i2s.c | 127 +++++++------ drivers/src/nrfx_pdm.c | 23 ++- drivers/src/nrfx_pwm.c | 29 +-- drivers/src/nrfx_qdec.c | 39 ++-- drivers/src/nrfx_qspi.c | 71 ++++--- drivers/src/nrfx_saadc.c | 7 +- drivers/src/nrfx_spi.c | 159 ++++++++-------- drivers/src/nrfx_spim.c | 351 +++++++++++++++++------------------ drivers/src/nrfx_spis.c | 133 +++++++------ drivers/src/nrfx_twi.c | 20 +- drivers/src/nrfx_twim.c | 27 ++- drivers/src/nrfx_twis.c | 30 +-- drivers/src/nrfx_uart.c | 85 ++++++--- drivers/src/nrfx_uarte.c | 87 ++++++--- mdk/nrf.h | 2 +- mdk/nrf51.h | 6 +- mdk/nrf52.h | 6 +- mdk/nrf52805.h | 6 +- mdk/nrf52810.h | 6 +- mdk/nrf52811.h | 6 +- mdk/nrf52820.h | 6 +- mdk/nrf52833.h | 6 +- mdk/nrf52840.h | 6 +- mdk/nrf52_erratas.h | 278 ++++++++++++++++++++------- mdk/nrf5340_application.h | 6 +- mdk/nrf5340_network.h | 6 +- mdk/nrf53_erratas.h | 112 +++++++++++ mdk/nrf9160.h | 6 +- 43 files changed, 1334 insertions(+), 704 deletions(-) diff --git a/CHANGELOG.md b/CHANGELOG.md index 9dc10105d..c81c9c041 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -1,6 +1,16 @@ # Changelog All notable changes to this project are documented in this file. +## [2.7.0] - 2021-12-16 +### Added +- Added new fields in the driver configuration structures to allow skipping GPIO and/or PSEL register configuration. Affected drivers: I2S, PDM, PWM, QDEC, QSPI, SPI, SPIM, SPIS, TWI, TWIM, TWIS, UART, UARTE. + +### Changed +- Updated MDK to version 8.44.2. + +### Fixed +- Fixed the inability to start subsequent simple mode conversion from the user callback context in the SAADC driver. + ## [2.6.0] - 2021-11-22 ### Added - Added new functions for the GPIOTE peripheral management in the GPIOTE driver. Legacy API is now deprecated. diff --git a/doc/nrfx.doxyfile b/doc/nrfx.doxyfile index b0211543a..95b9c82a4 100644 --- a/doc/nrfx.doxyfile +++ b/doc/nrfx.doxyfile @@ -40,7 +40,7 @@ PROJECT_NAME = "nrfx" ### EDIT THIS ### -PROJECT_NUMBER = "2.6" +PROJECT_NUMBER = "2.7" # Using the PROJECT_BRIEF tag one can provide an optional one line description # for a project that appears at the top of each page and should give viewer a diff --git a/drivers/include/nrfx_i2s.h b/drivers/include/nrfx_i2s.h index ef6a916a4..93a556520 100644 --- a/drivers/include/nrfx_i2s.h +++ b/drivers/include/nrfx_i2s.h @@ -82,6 +82,20 @@ typedef struct nrf_i2s_clksrc_t clksrc; ///< Clock source selection. bool enable_bypass; ///< Bypass clock generator. MCK will be equal to source input. #endif + bool skip_gpio_cfg; ///< Skip GPIO configuration of pins. + /**< When set to true, the driver does not modify + * any GPIO parameters of the used pins. Those + * parameters are supposed to be configured + * externally before the driver is initialized. */ + bool skip_psel_cfg; ///< Skip pin selection configuration. + /**< When set to true, the driver does not modify + * pin select registers in the peripheral. + * Those registers are supposed to be set up + * externally before the driver is initialized. + * @note When both GPIO configuration and pin + * selection are to be skipped, the structure + * fields that specify pins can be omitted, + * as they are ignored anyway. */ } nrfx_i2s_config_t; /** @brief I2S driver buffers structure. */ diff --git a/drivers/include/nrfx_pdm.h b/drivers/include/nrfx_pdm.h index 12d60a920..46420894f 100644 --- a/drivers/include/nrfx_pdm.h +++ b/drivers/include/nrfx_pdm.h @@ -83,6 +83,20 @@ typedef struct #if NRF_PDM_HAS_MCLKCONFIG nrf_pdm_mclksrc_t mclksrc; ///< Master clock source selection. #endif + bool skip_gpio_cfg; ///< Skip GPIO configuration of pins. + /**< When set to true, the driver does not modify + * any GPIO parameters of the used pins. Those + * parameters are supposed to be configured + * externally before the driver is initialized. */ + bool skip_psel_cfg; ///< Skip pin selection configuration. + /**< When set to true, the driver does not modify + * pin select registers in the peripheral. + * Those registers are supposed to be set up + * externally before the driver is initialized. + * @note When both GPIO configuration and pin + * selection are to be skipped, the structure + * fields that specify pins can be omitted, + * as they are ignored anyway. */ } nrfx_pdm_config_t; diff --git a/drivers/include/nrfx_pwm.h b/drivers/include/nrfx_pwm.h index 0b3d43b72..2e2ff62dd 100644 --- a/drivers/include/nrfx_pwm.h +++ b/drivers/include/nrfx_pwm.h @@ -96,16 +96,26 @@ typedef struct uint8_t output_pins[NRF_PWM_CHANNEL_COUNT]; ///< Pin numbers for individual output channels (optional). /**< Use @ref NRFX_PWM_PIN_NOT_USED * if a given output channel is not needed. */ - uint8_t irq_priority; ///< Interrupt priority. - nrf_pwm_clk_t base_clock; ///< Base clock frequency. - nrf_pwm_mode_t count_mode; ///< Operating mode of the pulse generator counter. - uint16_t top_value; ///< Value up to which the pulse generator counter counts. - nrf_pwm_dec_load_t load_mode; ///< Mode of loading sequence data from RAM. - nrf_pwm_dec_step_t step_mode; ///< Mode of advancing the active sequence. - bool skip_gpio_cfg; ///< Skip the GPIO configuration - /**< When this flag is set, the user is responsible for - * providing the proper configuration of the output pins, - * as the driver does not touch it at all. */ + uint8_t irq_priority; ///< Interrupt priority. + nrf_pwm_clk_t base_clock; ///< Base clock frequency. + nrf_pwm_mode_t count_mode; ///< Operating mode of the pulse generator counter. + uint16_t top_value; ///< Value up to which the pulse generator counter counts. + nrf_pwm_dec_load_t load_mode; ///< Mode of loading sequence data from RAM. + nrf_pwm_dec_step_t step_mode; ///< Mode of advancing the active sequence. + bool skip_gpio_cfg; ///< Skip GPIO configuration of pins. + /**< When set to true, the driver does not modify + * any GPIO parameters of the used pins. Those + * parameters are supposed to be configured + * externally before the driver is initialized. */ + bool skip_psel_cfg; ///< Skip pin selection configuration. + /**< When set to true, the driver does not modify + * pin select registers in the peripheral. + * Those registers are supposed to be set up + * externally before the driver is initialized. + * @note When both GPIO configuration and pin + * selection are to be skipped, the structure + * fields that specify pins can be omitted, + * as they are ignored anyway. */ } nrfx_pwm_config_t; /** diff --git a/drivers/include/nrfx_qdec.h b/drivers/include/nrfx_qdec.h index d1c61a4ee..d35fd7529 100644 --- a/drivers/include/nrfx_qdec.h +++ b/drivers/include/nrfx_qdec.h @@ -51,16 +51,30 @@ extern "C" { /** @brief QDEC configuration structure. */ typedef struct { - nrf_qdec_reportper_t reportper; /**< Report period in samples. */ - nrf_qdec_sampleper_t sampleper; /**< Sampling period in microseconds. */ - uint32_t psela; /**< Pin number for A input. */ - uint32_t pselb; /**< Pin number for B input. */ - uint32_t pselled; /**< Pin number for LED output. */ - uint32_t ledpre; /**< Time (in microseconds) how long LED is switched on before sampling. */ - nrf_qdec_ledpol_t ledpol; /**< Active LED polarity. */ - bool dbfen; /**< State of debouncing filter. */ - bool sample_inten; /**< Enabling sample ready interrupt. */ - uint8_t interrupt_priority; /**< QDEC interrupt priority. */ + nrf_qdec_reportper_t reportper; ///< Report period in samples. + nrf_qdec_sampleper_t sampleper; ///< Sampling period in microseconds. + uint32_t psela; ///< Pin number for A input. + uint32_t pselb; ///< Pin number for B input. + uint32_t pselled; ///< Pin number for LED output. + uint32_t ledpre; ///< Time (in microseconds) how long LED is switched on before sampling. + nrf_qdec_ledpol_t ledpol; ///< Active LED polarity. + bool dbfen; ///< State of debouncing filter. + bool sample_inten; ///< Enabling sample ready interrupt. + uint8_t interrupt_priority; ///< QDEC interrupt priority. + bool skip_gpio_cfg; ///< Skip GPIO configuration of pins. + /**< When set to true, the driver does not modify + * any GPIO parameters of the used pins. Those + * parameters are supposed to be configured + * externally before the driver is initialized. */ + bool skip_psel_cfg; ///< Skip pin selection configuration. + /**< When set to true, the driver does not modify + * pin select registers in the peripheral. + * Those registers are supposed to be set up + * externally before the driver is initialized. + * @note When both GPIO configuration and pin + * selection are to be skipped, the structure + * fields that specify pins can be omitted, + * as they are ignored anyway. */ } nrfx_qdec_config_t; /** diff --git a/drivers/include/nrfx_qspi.h b/drivers/include/nrfx_qspi.h index f82e36b06..f7e6134ac 100644 --- a/drivers/include/nrfx_qspi.h +++ b/drivers/include/nrfx_qspi.h @@ -51,11 +51,25 @@ extern "C" { /** @brief QSPI driver instance configuration structure. */ typedef struct { - uint32_t xip_offset; /**< Address offset into the external memory for Execute in Place operation. */ - nrf_qspi_pins_t pins; /**< Pin configuration structure. */ - nrf_qspi_prot_conf_t prot_if; /**< Protocol layer interface configuration structure. */ - nrf_qspi_phy_conf_t phy_if; /**< Physical layer interface configuration structure. */ - uint8_t irq_priority; /**< Interrupt priority. */ + uint32_t xip_offset; ///< Address offset into the external memory for Execute in Place operation. + nrf_qspi_pins_t pins; ///< Pin configuration structure. + nrf_qspi_prot_conf_t prot_if; ///< Protocol layer interface configuration structure. + nrf_qspi_phy_conf_t phy_if; ///< Physical layer interface configuration structure. + uint8_t irq_priority; ///< Interrupt priority. + bool skip_gpio_cfg; ///< Skip GPIO configuration of pins. + /**< When set to true, the driver does not modify + * any GPIO parameters of the used pins. Those + * parameters are supposed to be configured + * externally before the driver is initialized. */ + bool skip_psel_cfg; ///< Skip pin selection configuration. + /**< When set to true, the driver does not modify + * pin select registers in the peripheral. + * Those registers are supposed to be set up + * externally before the driver is initialized. + * @note When both GPIO configuration and pin + * selection are to be skipped, the structure + * fields that specify pins can be omitted, + * as they are ignored anyway. */ } nrfx_qspi_config_t; /** diff --git a/drivers/include/nrfx_spi.h b/drivers/include/nrfx_spi.h index 155c99fed..d582fa736 100644 --- a/drivers/include/nrfx_spi.h +++ b/drivers/include/nrfx_spi.h @@ -88,27 +88,47 @@ enum { /** @brief Configuration structure of the SPI master driver instance. */ typedef struct { - uint8_t sck_pin; ///< SCK pin number. - uint8_t mosi_pin; ///< MOSI pin number (optional). - /**< Set to @ref NRFX_SPI_PIN_NOT_USED - * if this signal is not needed. */ - uint8_t miso_pin; ///< MISO pin number (optional). - /**< Set to @ref NRFX_SPI_PIN_NOT_USED - * if this signal is not needed. */ - uint8_t ss_pin; ///< Slave Select pin number (optional). - /**< Set to @ref NRFX_SPI_PIN_NOT_USED - * if this signal is not needed. The driver - * supports only active low for this signal. - * If the signal must be active high, - * it must be controlled externally. */ - uint8_t irq_priority; ///< Interrupt priority. - uint8_t orc; ///< Overrun character. - /**< This character is used when all bytes from the TX buffer are sent, - but the transfer continues due to RX. */ - nrf_spi_frequency_t frequency; ///< SPI frequency. - nrf_spi_mode_t mode; ///< SPI mode. - nrf_spi_bit_order_t bit_order; ///< SPI bit order. - nrf_gpio_pin_pull_t miso_pull; ///< MISO pull up configuration. + uint8_t sck_pin; ///< SCK pin number. + uint8_t mosi_pin; ///< MOSI pin number (optional). + /**< Set to @ref NRFX_SPI_PIN_NOT_USED + * if this signal is not needed. */ + uint8_t miso_pin; ///< MISO pin number (optional). + /**< Set to @ref NRFX_SPI_PIN_NOT_USED + * if this signal is not needed. */ + uint8_t ss_pin; ///< Slave Select pin number (optional). + /**< Set to @ref NRFX_SPI_PIN_NOT_USED + * if this signal is not needed. The driver + * supports only active low for this signal. + * If the signal must be active high, + * it must be controlled externally. + * @note Unlike the other fields that specify + * pin numbers, this one cannot be omitted + * when both GPIO configuration and pin + * selection are to be skipped, as the driver + * must control the signal as a regular GPIO. */ + uint8_t irq_priority; ///< Interrupt priority. + uint8_t orc; ///< Overrun character. + /**< This character is used when all bytes from the TX buffer are sent, + * but the transfer continues due to RX. */ + nrf_spi_frequency_t frequency; ///< SPI frequency. + nrf_spi_mode_t mode; ///< SPI mode. + nrf_spi_bit_order_t bit_order; ///< SPI bit order. + nrf_gpio_pin_pull_t miso_pull; ///< MISO pull up configuration. + bool skip_gpio_cfg; ///< Skip GPIO configuration of pins. + /**< When set to true, the driver does not modify + * any GPIO parameters of the used pins. Those + * parameters are supposed to be configured + * externally before the driver is initialized. */ + bool skip_psel_cfg; ///< Skip pin selection configuration. + /**< When set to true, the driver does not modify + * pin select registers in the peripheral. + * Those registers are supposed to be set up + * externally before the driver is initialized. + * @note When both GPIO configuration and pin + * selection are to be skipped, the structure + * fields that specify pins can be omitted, + * as they are ignored anyway. This does not + * apply to the @p ss_pin field. */ } nrfx_spi_config_t; /** diff --git a/drivers/include/nrfx_spim.h b/drivers/include/nrfx_spim.h index 51cf5a880..a79a83b57 100644 --- a/drivers/include/nrfx_spim.h +++ b/drivers/include/nrfx_spim.h @@ -94,39 +94,61 @@ enum { /** @brief Configuration structure of the SPIM driver instance. */ typedef struct { - uint8_t sck_pin; ///< SCK pin number. - uint8_t mosi_pin; ///< MOSI pin number (optional). - /**< Set to @ref NRFX_SPIM_PIN_NOT_USED - * if this signal is not needed. */ - uint8_t miso_pin; ///< MISO pin number (optional). - /**< Set to @ref NRFX_SPIM_PIN_NOT_USED - * if this signal is not needed. */ - uint8_t ss_pin; ///< Slave Select pin number (optional). - /**< Set to @ref NRFX_SPIM_PIN_NOT_USED - * if this signal is not needed. */ - bool ss_active_high; ///< Polarity of the Slave Select pin during transmission. - uint8_t irq_priority; ///< Interrupt priority. - uint8_t orc; ///< Overrun character. - /**< This character is used when all bytes from the TX buffer are sent, - but the transfer continues due to RX. */ - nrf_spim_frequency_t frequency; ///< SPIM frequency. - nrf_spim_mode_t mode; ///< SPIM mode. - nrf_spim_bit_order_t bit_order; ///< SPIM bit order. - nrf_gpio_pin_pull_t miso_pull; ///< MISO pull up configuration. + uint8_t sck_pin; ///< SCK pin number. + uint8_t mosi_pin; ///< MOSI pin number (optional). + /**< Set to @ref NRFX_SPIM_PIN_NOT_USED + * if this signal is not needed. */ + uint8_t miso_pin; ///< MISO pin number (optional). + /**< Set to @ref NRFX_SPIM_PIN_NOT_USED + * if this signal is not needed. */ + uint8_t ss_pin; ///< Slave Select pin number (optional). + /**< Set to @ref NRFX_SPIM_PIN_NOT_USED + * if this signal is not needed. + * @note Unlike the other fields that specify + * pin numbers, this one cannot be omitted + * when both GPIO configuration and pin + * selection are to be skipped but the signal + * is not controlled by hardware (the driver + * must then control it as a regular GPIO). */ + bool ss_active_high; ///< Polarity of the Slave Select pin during transmission. + uint8_t irq_priority; ///< Interrupt priority. + uint8_t orc; ///< Overrun character. + /**< This character is used when all bytes from the TX buffer are sent, + * but the transfer continues due to RX. */ + nrf_spim_frequency_t frequency; ///< SPIM frequency. + nrf_spim_mode_t mode; ///< SPIM mode. + nrf_spim_bit_order_t bit_order; ///< SPIM bit order. + nrf_gpio_pin_pull_t miso_pull; ///< MISO pull up configuration. #if NRFX_CHECK(NRFX_SPIM_EXTENDED_ENABLED) || defined(__NRFX_DOXYGEN__) - uint8_t dcx_pin; ///< D/CX pin number (optional). - uint8_t rx_delay; ///< Sample delay for input serial data on MISO. - /**< The value specifies the delay, in number of 64 MHz clock cycles - * (15.625 ns), from the the sampling edge of SCK (leading edge for - * CONFIG.CPHA = 0, trailing edge for CONFIG.CPHA = 1) until - * the input serial data is sampled. */ - bool use_hw_ss; ///< Indication to use software or hardware controlled Slave Select pin. - uint8_t ss_duration; ///< Slave Select duration before and after transmission. - /**< Minimum duration between the edge of CSN and the edge of SCK. - * Also, minimum duration of CSN inactivity between transactions. - * The value is specified in number of 64 MHz clock cycles (15.625 ns). - * Supported only for hardware-controlled Slave Select. */ + uint8_t dcx_pin; ///< D/CX pin number (optional). + uint8_t rx_delay; ///< Sample delay for input serial data on MISO. + /**< The value specifies the delay, in number of 64 MHz clock cycles + * (15.625 ns), from the the sampling edge of SCK (leading edge for + * CONFIG.CPHA = 0, trailing edge for CONFIG.CPHA = 1) until + * the input serial data is sampled. */ + bool use_hw_ss; ///< Indication to use software or hardware controlled Slave Select pin. + uint8_t ss_duration; ///< Slave Select duration before and after transmission. + /**< Minimum duration between the edge of CSN and the edge of SCK. + * Also, minimum duration of CSN inactivity between transactions. + * The value is specified in number of 64 MHz clock cycles (15.625 ns). + * Supported only for hardware-controlled Slave Select. */ #endif + bool skip_gpio_cfg; ///< Skip GPIO configuration of pins. + /**< When set to true, the driver does not modify + * any GPIO parameters of the used pins. Those + * parameters are supposed to be configured + * externally before the driver is initialized. */ + bool skip_psel_cfg; ///< Skip pin selection configuration. + /**< When set to true, the driver does not modify + * pin select registers in the peripheral. + * Those registers are supposed to be set up + * externally before the driver is initialized. + * @note When both GPIO configuration and pin + * selection are to be skipped, the structure + * fields that specify pins can be omitted, + * as they are ignored anyway. This does not + * apply to the @p ss_pin field, unless it is + * to be controlled by hardware.*/ } nrfx_spim_config_t; #if NRFX_CHECK(NRFX_SPIM_EXTENDED_ENABLED) || defined(__NRFX_DOXYGEN__) diff --git a/drivers/include/nrfx_spis.h b/drivers/include/nrfx_spis.h index 3bd618382..ddc9487c5 100644 --- a/drivers/include/nrfx_spis.h +++ b/drivers/include/nrfx_spis.h @@ -138,21 +138,35 @@ typedef struct /** @brief SPI peripheral device configuration data. */ typedef struct { - uint32_t miso_pin; //!< SPI MISO pin (optional). + uint32_t miso_pin; ///< SPI MISO pin (optional). /**< Set @ref NRFX_SPIS_PIN_NOT_USED * if this signal is not needed. */ - uint32_t mosi_pin; //!< SPI MOSI pin (optional). + uint32_t mosi_pin; ///< SPI MOSI pin (optional). /**< Set @ref NRFX_SPIS_PIN_NOT_USED * if this signal is not needed. */ - uint32_t sck_pin; //!< SPI SCK pin. - uint32_t csn_pin; //!< SPI CSN pin. - nrf_spis_mode_t mode; //!< SPI mode. - nrf_spis_bit_order_t bit_order; //!< SPI transaction bit order. - nrf_gpio_pin_pull_t csn_pullup; //!< CSN pin pull-up configuration. - nrf_gpio_pin_drive_t miso_drive; //!< MISO pin drive configuration. - uint8_t def; //!< Character clocked out in case of an ignored transaction. - uint8_t orc; //!< Character clocked out after an over-read of the transmit buffer. - uint8_t irq_priority; //!< Interrupt priority. + uint32_t sck_pin; ///< SPI SCK pin. + uint32_t csn_pin; ///< SPI CSN pin. + nrf_spis_mode_t mode; ///< SPI mode. + nrf_spis_bit_order_t bit_order; ///< SPI transaction bit order. + nrf_gpio_pin_pull_t csn_pullup; ///< CSN pin pull-up configuration. + nrf_gpio_pin_drive_t miso_drive; ///< MISO pin drive configuration. + uint8_t def; ///< Character clocked out in case of an ignored transaction. + uint8_t orc; ///< Character clocked out after an over-read of the transmit buffer. + uint8_t irq_priority; ///< Interrupt priority. + bool skip_gpio_cfg; ///< Skip GPIO configuration of pins. + /**< When set to true, the driver does not modify + * any GPIO parameters of the used pins. Those + * parameters are supposed to be configured + * externally before the driver is initialized. */ + bool skip_psel_cfg; ///< Skip pin selection configuration. + /**< When set to true, the driver does not modify + * pin select registers in the peripheral. + * Those registers are supposed to be set up + * externally before the driver is initialized. + * @note When both GPIO configuration and pin + * selection are to be skipped, the structure + * fields that specify pins can be omitted, + * as they are ignored anyway. */ } nrfx_spis_config_t; diff --git a/drivers/include/nrfx_twi.h b/drivers/include/nrfx_twi.h index b754cac6d..a93bc55d9 100644 --- a/drivers/include/nrfx_twi.h +++ b/drivers/include/nrfx_twi.h @@ -85,6 +85,20 @@ typedef struct nrf_twi_frequency_t frequency; ///< TWI frequency. uint8_t interrupt_priority; ///< Interrupt priority. bool hold_bus_uninit; ///< Hold pull up state on GPIO pins after uninit. + bool skip_gpio_cfg; ///< Skip GPIO configuration of pins. + /**< When set to true, the driver does not modify + * any GPIO parameters of the used pins. Those + * parameters are supposed to be configured + * externally before the driver is initialized. */ + bool skip_psel_cfg; ///< Skip pin selection configuration. + /**< When set to true, the driver does not modify + * pin select registers in the peripheral. + * Those registers are supposed to be set up + * externally before the driver is initialized. + * @note When both GPIO configuration and pin + * selection are to be skipped, the structure + * fields that specify pins can be omitted, + * as they are ignored anyway. */ } nrfx_twi_config_t; /** diff --git a/drivers/include/nrfx_twim.h b/drivers/include/nrfx_twim.h index 2976fab86..14e45410f 100644 --- a/drivers/include/nrfx_twim.h +++ b/drivers/include/nrfx_twim.h @@ -89,6 +89,20 @@ typedef struct nrf_twim_frequency_t frequency; ///< TWIM frequency. uint8_t interrupt_priority; ///< Interrupt priority. bool hold_bus_uninit; ///< Hold pull up state on GPIO pins after uninit. + bool skip_gpio_cfg; ///< Skip GPIO configuration of pins. + /**< When set to true, the driver does not modify + * any GPIO parameters of the used pins. Those + * parameters are supposed to be configured + * externally before the driver is initialized. */ + bool skip_psel_cfg; ///< Skip pin selection configuration. + /**< When set to true, the driver does not modify + * pin select registers in the peripheral. + * Those registers are supposed to be set up + * externally before the driver is initialized. + * @note When both GPIO configuration and pin + * selection are to be skipped, the structure + * fields that specify pins can be omitted, + * as they are ignored anyway. */ } nrfx_twim_config_t; /** diff --git a/drivers/include/nrfx_twis.h b/drivers/include/nrfx_twis.h index 69782dc68..8034161aa 100644 --- a/drivers/include/nrfx_twis.h +++ b/drivers/include/nrfx_twis.h @@ -139,12 +139,26 @@ typedef void (*nrfx_twis_event_handler_t)(nrfx_twis_evt_t const * p_event); /** @brief Structure for TWIS configuration. */ typedef struct { - uint32_t addr[2]; //!< Set addresses that this slave should respond. Set 0 to disable. - uint32_t scl; //!< SCL pin number. - uint32_t sda; //!< SDA pin number. - nrf_gpio_pin_pull_t scl_pull; //!< SCL pin pull. - nrf_gpio_pin_pull_t sda_pull; //!< SDA pin pull. - uint8_t interrupt_priority; //!< The priority of interrupt for the module to be set. + uint32_t addr[2]; ///< Set addresses that this slave should respond. Set 0 to disable. + uint32_t scl; ///< SCL pin number. + uint32_t sda; ///< SDA pin number. + nrf_gpio_pin_pull_t scl_pull; ///< SCL pin pull. + nrf_gpio_pin_pull_t sda_pull; ///< SDA pin pull. + uint8_t interrupt_priority; ///< The priority of interrupt for the module to be set. + bool skip_gpio_cfg; ///< Skip GPIO configuration of pins. + /**< When set to true, the driver does not modify + * any GPIO parameters of the used pins. Those + * parameters are supposed to be configured + * externally before the driver is initialized. */ + bool skip_psel_cfg; ///< Skip pin selection configuration. + /**< When set to true, the driver does not modify + * pin select registers in the peripheral. + * Those registers are supposed to be set up + * externally before the driver is initialized. + * @note When both GPIO configuration and pin + * selection are to be skipped, the structure + * fields that specify pins can be omitted, + * as they are ignored anyway. */ } nrfx_twis_config_t; /** diff --git a/drivers/include/nrfx_uart.h b/drivers/include/nrfx_uart.h index 3bd673b3b..8edcbe0d0 100644 --- a/drivers/include/nrfx_uart.h +++ b/drivers/include/nrfx_uart.h @@ -90,6 +90,20 @@ typedef struct nrf_uart_baudrate_t baudrate; ///< Baud rate. uint8_t interrupt_priority; ///< Interrupt priority. nrf_uart_config_t hal_cfg; ///< Parity, flow control and stop bits settings. + bool skip_gpio_cfg; ///< Skip GPIO configuration of pins. + /**< When set to true, the driver does not modify + * any GPIO parameters of the used pins. Those + * parameters are supposed to be configured + * externally before the driver is initialized. */ + bool skip_psel_cfg; ///< Skip pin selection configuration. + /**< When set to true, the driver does not modify + * pin select registers in the peripheral. + * Those registers are supposed to be set up + * externally before the driver is initialized. + * @note When both GPIO configuration and pin + * selection are to be skipped, the structure + * fields that specify pins can be omitted, + * as they are ignored anyway. */ } nrfx_uart_config_t; #if defined(UART_CONFIG_STOP_Msk) || defined(__NRFX_DOXYGEN__) diff --git a/drivers/include/nrfx_uarte.h b/drivers/include/nrfx_uarte.h index fe6238866..7b2760ab7 100644 --- a/drivers/include/nrfx_uarte.h +++ b/drivers/include/nrfx_uarte.h @@ -99,6 +99,20 @@ typedef struct nrf_uarte_baudrate_t baudrate; ///< Baud rate. uint8_t interrupt_priority; ///< Interrupt priority. nrf_uarte_config_t hal_cfg; ///< Parity, flow control and stop bits settings. + bool skip_gpio_cfg; ///< Skip GPIO configuration of pins. + /**< When set to true, the driver does not modify + * any GPIO parameters of the used pins. Those + * parameters are supposed to be configured + * externally before the driver is initialized. */ + bool skip_psel_cfg; ///< Skip pin selection configuration. + /**< When set to true, the driver does not modify + * pin select registers in the peripheral. + * Those registers are supposed to be set up + * externally before the driver is initialized. + * @note When both GPIO configuration and pin + * selection are to be skipped, the structure + * fields that specify pins can be omitted, + * as they are ignored anyway. */ } nrfx_uarte_config_t; #if defined(UARTE_CONFIG_STOP_Msk) || defined(__NRFX_DOXYGEN__) diff --git a/drivers/src/nrfx_i2s.c b/drivers/src/nrfx_i2s.c index 24108251e..2d633aeb4 100644 --- a/drivers/src/nrfx_i2s.c +++ b/drivers/src/nrfx_i2s.c @@ -79,6 +79,8 @@ typedef struct bool tx_ready : 1; bool buffers_needed : 1; bool buffers_reused : 1; + bool skip_gpio_cfg : 1; + bool skip_psel_cfg : 1; uint16_t buffer_size; nrfx_i2s_buffers_t next_buffers; @@ -89,63 +91,59 @@ static i2s_control_block_t m_cb; static void configure_pins(nrfx_i2s_config_t const * p_config) { - uint32_t mck_pin, sdout_pin, sdin_pin; - - // Configure pins used by the peripheral: - - // - SCK and LRCK (required) - depending on the mode of operation these - // pins are configured as outputs (in Master mode) or inputs (in Slave - // mode). - if (p_config->mode == NRF_I2S_MODE_MASTER) - { - nrf_gpio_cfg_output(p_config->sck_pin); - nrf_gpio_cfg_output(p_config->lrck_pin); - } - else - { - nrf_gpio_cfg_input(p_config->sck_pin, NRF_GPIO_PIN_NOPULL); - nrf_gpio_cfg_input(p_config->lrck_pin, NRF_GPIO_PIN_NOPULL); - } - - // - MCK (optional) - always output, - if (p_config->mck_pin != NRFX_I2S_PIN_NOT_USED) - { - mck_pin = p_config->mck_pin; - nrf_gpio_cfg_output(mck_pin); - } - else + if (!p_config->skip_gpio_cfg) { - mck_pin = NRF_I2S_PIN_NOT_CONNECTED; - } + // Configure pins used by the peripheral: - // - SDOUT (optional) - always output, - if (p_config->sdout_pin != NRFX_I2S_PIN_NOT_USED) - { - sdout_pin = p_config->sdout_pin; - nrf_gpio_cfg_output(sdout_pin); - } - else - { - sdout_pin = NRF_I2S_PIN_NOT_CONNECTED; + // - SCK and LRCK (required) - depending on the mode of operation these + // pins are configured as outputs (in Master mode) or inputs (in Slave + // mode). + if (p_config->mode == NRF_I2S_MODE_MASTER) + { + nrf_gpio_cfg_output(p_config->sck_pin); + nrf_gpio_cfg_output(p_config->lrck_pin); + } + else + { + nrf_gpio_cfg_input(p_config->sck_pin, NRF_GPIO_PIN_NOPULL); + nrf_gpio_cfg_input(p_config->lrck_pin, NRF_GPIO_PIN_NOPULL); + } + // - MCK (optional) - always output, + if (p_config->mck_pin != NRFX_I2S_PIN_NOT_USED) + { + nrf_gpio_cfg_output(p_config->mck_pin); + } + // - SDOUT (optional) - always output, + if (p_config->sdout_pin != NRFX_I2S_PIN_NOT_USED) + { + nrf_gpio_cfg_output(p_config->sdout_pin); + } + // - SDIN (optional) - always input. + if (p_config->sdin_pin != NRFX_I2S_PIN_NOT_USED) + { + nrf_gpio_cfg_input(p_config->sdin_pin, NRF_GPIO_PIN_NOPULL); + } } - // - SDIN (optional) - always input. - if (p_config->sdin_pin != NRFX_I2S_PIN_NOT_USED) + if (!p_config->skip_psel_cfg) { - sdin_pin = p_config->sdin_pin; - nrf_gpio_cfg_input(sdin_pin, NRF_GPIO_PIN_NOPULL); + uint32_t mck_pin = (p_config->mck_pin != NRFX_I2S_PIN_NOT_USED) + ? p_config->mck_pin + : NRF_I2S_PIN_NOT_CONNECTED; + uint32_t sdout_pin = (p_config->sdout_pin != NRFX_I2S_PIN_NOT_USED) + ? p_config->sdout_pin + : NRF_I2S_PIN_NOT_CONNECTED; + uint32_t sdin_pin = (p_config->sdin_pin != NRFX_I2S_PIN_NOT_USED) + ? p_config->sdin_pin + : NRF_I2S_PIN_NOT_CONNECTED; + + nrf_i2s_pins_set(NRF_I2S0, + p_config->sck_pin, + p_config->lrck_pin, + mck_pin, + sdout_pin, + sdin_pin); } - else - { - sdin_pin = NRF_I2S_PIN_NOT_CONNECTED; - } - - nrf_i2s_pins_set(NRF_I2S0, - p_config->sck_pin, - p_config->lrck_pin, - mck_pin, - sdout_pin, - sdin_pin); } static void deconfigure_pins(void) @@ -222,8 +220,11 @@ nrfx_err_t nrfx_i2s_init(nrfx_i2s_config_t const * p_config, #if NRF_I2S_HAS_CLKCONFIG nrf_i2s_clk_configure(NRF_I2S0, p_config->clksrc, p_config->enable_bypass); #endif + configure_pins(p_config); + m_cb.skip_gpio_cfg = p_config->skip_gpio_cfg; + m_cb.skip_psel_cfg = p_config->skip_psel_cfg; m_cb.handler = handler; NRFX_IRQ_PRIORITY_SET(nrfx_get_irq_number(NRF_I2S0), p_config->irq_priority); @@ -246,17 +247,23 @@ void nrfx_i2s_uninit(void) nrf_i2s_disable(NRF_I2S0); - deconfigure_pins(); + if (!m_cb.skip_gpio_cfg) + { + deconfigure_pins(); + } #if USE_WORKAROUND_FOR_ANOMALY_196 - // Disabling I2S is insufficient to release pins acquired by the peripheral. - // Explicit disconnect is needed. - nrf_i2s_pins_set(NRF_I2S0, - NRF_I2S_PIN_NOT_CONNECTED, - NRF_I2S_PIN_NOT_CONNECTED, - NRF_I2S_PIN_NOT_CONNECTED, - NRF_I2S_PIN_NOT_CONNECTED, - NRF_I2S_PIN_NOT_CONNECTED); + if (!m_cb.skip_psel_cfg) + { + // Disabling I2S is insufficient to release pins acquired + // by the peripheral. Explicit disconnect is needed. + nrf_i2s_pins_set(NRF_I2S0, + NRF_I2S_PIN_NOT_CONNECTED, + NRF_I2S_PIN_NOT_CONNECTED, + NRF_I2S_PIN_NOT_CONNECTED, + NRF_I2S_PIN_NOT_CONNECTED, + NRF_I2S_PIN_NOT_CONNECTED); + } #endif m_cb.state = NRFX_DRV_STATE_UNINITIALIZED; diff --git a/drivers/src/nrfx_pdm.c b/drivers/src/nrfx_pdm.c index d76d45a6f..b2d349146 100644 --- a/drivers/src/nrfx_pdm.c +++ b/drivers/src/nrfx_pdm.c @@ -68,6 +68,7 @@ typedef struct uint8_t active_buffer; ///< Number of currently active buffer. uint8_t error; ///< Driver error flag. volatile uint8_t irq_buff_request; ///< Request the next buffer in the ISR. + bool skip_gpio_cfg; ///< Do not touch GPIO configuration of used pins. } nrfx_pdm_cb_t; static nrfx_pdm_cb_t m_cb; @@ -201,6 +202,7 @@ nrfx_err_t nrfx_pdm_init(nrfx_pdm_config_t const * p_config, m_cb.error = 0; m_cb.event_handler = event_handler; m_cb.op_state = NRFX_PDM_STATE_IDLE; + m_cb.skip_gpio_cfg = p_config->skip_gpio_cfg; #if NRF_PDM_HAS_RATIO_CONFIG nrf_pdm_ratio_set(NRF_PDM0, p_config->ratio); @@ -213,10 +215,16 @@ nrfx_err_t nrfx_pdm_init(nrfx_pdm_config_t const * p_config, nrf_pdm_mode_set(NRF_PDM0, p_config->mode, p_config->edge); nrf_pdm_gain_set(NRF_PDM0, p_config->gain_l, p_config->gain_r); - nrf_gpio_cfg_output(p_config->pin_clk); - nrf_gpio_pin_clear(p_config->pin_clk); - nrf_gpio_cfg_input(p_config->pin_din, NRF_GPIO_PIN_NOPULL); - nrf_pdm_psel_connect(NRF_PDM0, p_config->pin_clk, p_config->pin_din); + if (!p_config->skip_gpio_cfg) + { + nrf_gpio_pin_clear(p_config->pin_clk); + nrf_gpio_cfg_output(p_config->pin_clk); + nrf_gpio_cfg_input(p_config->pin_din, NRF_GPIO_PIN_NOPULL); + } + if (!p_config->skip_psel_cfg) + { + nrf_pdm_psel_connect(NRF_PDM0, p_config->pin_clk, p_config->pin_din); + } nrf_pdm_event_clear(NRF_PDM0, NRF_PDM_EVENT_STARTED); nrf_pdm_event_clear(NRF_PDM0, NRF_PDM_EVENT_END); @@ -237,8 +245,11 @@ void nrfx_pdm_uninit(void) { nrf_pdm_disable(NRF_PDM0); - nrf_gpio_cfg_default(nrf_pdm_clk_pin_get(NRF_PDM0)); - nrf_gpio_cfg_default(nrf_pdm_din_pin_get(NRF_PDM0)); + if (!m_cb.skip_gpio_cfg) + { + nrf_gpio_cfg_default(nrf_pdm_clk_pin_get(NRF_PDM0)); + nrf_gpio_cfg_default(nrf_pdm_din_pin_get(NRF_PDM0)); + } m_cb.drv_state = NRFX_DRV_STATE_UNINITIALIZED; NRFX_LOG_INFO("Uninitialized."); diff --git a/drivers/src/nrfx_pwm.c b/drivers/src/nrfx_pwm.c index c47e3b060..21a2d992b 100644 --- a/drivers/src/nrfx_pwm.c +++ b/drivers/src/nrfx_pwm.c @@ -77,12 +77,20 @@ typedef struct void * p_context; nrfx_drv_state_t volatile state; uint8_t flags; + bool skip_gpio_cfg; } pwm_control_block_t; static pwm_control_block_t m_cb[NRFX_PWM_ENABLED_COUNT]; static void configure_pins(nrfx_pwm_t const * p_instance, nrfx_pwm_config_t const * p_config) { + // Nothing to do here if both GPIO configuration and pin selection are + // to be skipped (the pin numbers may be then even not specified). + if (!(p_config->skip_gpio_cfg && p_config->skip_psel_cfg)) + { + return; + } + uint32_t out_pins[NRF_PWM_CHANNEL_COUNT]; uint8_t i; @@ -96,15 +104,7 @@ static void configure_pins(nrfx_pwm_t const * p_instance, if (!p_config->skip_gpio_cfg) { - if (inverted) - { - nrf_gpio_pin_set(out_pins[i]); - } - else - { - nrf_gpio_pin_clear(out_pins[i]); - } - + nrf_gpio_pin_write(out_pins[i], inverted ? 1 : 0); nrf_gpio_cfg_output(out_pins[i]); } } @@ -114,7 +114,10 @@ static void configure_pins(nrfx_pwm_t const * p_instance, } } - nrf_pwm_pins_set(p_instance->p_registers, out_pins); + if (!p_config->skip_psel_cfg) + { + nrf_pwm_pins_set(p_instance->p_registers, out_pins); + } } static void deconfigure_pins(nrfx_pwm_t const * p_instance) @@ -151,6 +154,7 @@ nrfx_err_t nrfx_pwm_init(nrfx_pwm_t const * p_instance, p_cb->handler = handler; p_cb->p_context = p_context; + p_cb->skip_gpio_cfg = p_config->skip_gpio_cfg; configure_pins(p_instance, p_config); @@ -204,7 +208,10 @@ void nrfx_pwm_uninit(nrfx_pwm_t const * p_instance) nrf_pwm_disable(p_instance->p_registers); - deconfigure_pins(p_instance); + if (!p_cb->skip_gpio_cfg) + { + deconfigure_pins(p_instance); + } p_cb->state = NRFX_DRV_STATE_UNINITIALIZED; } diff --git a/drivers/src/nrfx_qdec.c b/drivers/src/nrfx_qdec.c index 19789eece..4be8073e7 100644 --- a/drivers/src/nrfx_qdec.c +++ b/drivers/src/nrfx_qdec.c @@ -50,6 +50,7 @@ static nrfx_qdec_event_handler_t m_qdec_event_handler = NULL; static nrfx_drv_state_t m_state = NRFX_DRV_STATE_UNINITIALIZED; +static bool m_skip_gpio_cfg; void nrfx_qdec_irq_handler(void) { @@ -107,17 +108,30 @@ nrfx_err_t nrfx_qdec_init(nrfx_qdec_config_t const * p_config, } m_qdec_event_handler = event_handler; + m_skip_gpio_cfg = p_config->skip_gpio_cfg; + + if (!p_config->skip_gpio_cfg) + { + nrf_gpio_cfg_input(p_config->psela, NRF_GPIO_PIN_NOPULL); + nrf_gpio_cfg_input(p_config->pselb, NRF_GPIO_PIN_NOPULL); + if (p_config->pselled != NRF_QDEC_LED_NOT_CONNECTED) + { + nrf_gpio_cfg_input(p_config->pselled, NRF_GPIO_PIN_NOPULL); + } + } + if (!p_config->skip_psel_cfg) + { + nrf_qdec_pins_set(NRF_QDEC, p_config->psela, p_config->pselb, p_config->pselled); + } nrf_qdec_sampleper_set(NRF_QDEC, p_config->sampleper); - nrf_gpio_cfg_input(p_config->psela, NRF_GPIO_PIN_NOPULL); - nrf_gpio_cfg_input(p_config->pselb, NRF_GPIO_PIN_NOPULL); - if (p_config->pselled != NRF_QDEC_LED_NOT_CONNECTED) + // Change the period and polarity of the LED only when it is used, + // otherwise the ledpre field might have an invalid value. + if (nrf_qdec_led_pin_get(NRF_QDEC) != NRF_QDEC_LED_NOT_CONNECTED) { - nrf_gpio_cfg_input(p_config->pselled, NRF_GPIO_PIN_NOPULL); nrf_qdec_ledpre_set(NRF_QDEC, p_config->ledpre); nrf_qdec_ledpol_set(NRF_QDEC, p_config->ledpol); } - nrf_qdec_pins_set(NRF_QDEC, p_config->psela, p_config->pselb, p_config->pselled); if (p_config->dbfen) { @@ -161,13 +175,16 @@ void nrfx_qdec_uninit(void) nrf_qdec_shorts_disable(NRF_QDEC, NRF_QDEC_SHORT_REPORTRDY_READCLRACC_MASK); - nrf_gpio_cfg_default(nrf_qdec_phase_a_pin_get(NRF_QDEC)); - nrf_gpio_cfg_default(nrf_qdec_phase_b_pin_get(NRF_QDEC)); - - uint32_t led_pin = nrf_qdec_led_pin_get(NRF_QDEC); - if (led_pin != NRF_QDEC_LED_NOT_CONNECTED) + if (!m_skip_gpio_cfg) { - nrf_gpio_cfg_default(led_pin); + nrf_gpio_cfg_default(nrf_qdec_phase_a_pin_get(NRF_QDEC)); + nrf_gpio_cfg_default(nrf_qdec_phase_b_pin_get(NRF_QDEC)); + + uint32_t led_pin = nrf_qdec_led_pin_get(NRF_QDEC); + if (led_pin != NRF_QDEC_LED_NOT_CONNECTED) + { + nrf_gpio_cfg_default(led_pin); + } } m_state = NRFX_DRV_STATE_UNINITIALIZED; diff --git a/drivers/src/nrfx_qspi.c b/drivers/src/nrfx_qspi.c index 23877acc0..7b6688a70 100644 --- a/drivers/src/nrfx_qspi.c +++ b/drivers/src/nrfx_qspi.c @@ -91,6 +91,7 @@ typedef struct uint32_t addr_secondary; /**< Address for the secondary buffer. */ nrfx_qspi_evt_ext_t evt_ext; /**< Extended event. */ nrfx_qspi_state_t state; /**< Driver state. */ + bool skip_gpio_cfg; /**< Do not touch GPIO configuration of used pins. */ } qspi_control_block_t; static qspi_control_block_t m_cb; @@ -163,13 +164,21 @@ static nrfx_err_t qspi_xfer(void * p_buffer, return NRFX_SUCCESS; } -static bool qspi_pins_configure(nrf_qspi_pins_t const * p_config) +static bool qspi_pins_configure(nrfx_qspi_config_t const * p_config) { + // If both GPIO configuration and pin selection are to be skipped, + // the pin numbers may be not specified at all, so even validation + // of those numbers cannot be performed. + if (p_config->skip_gpio_cfg && p_config->skip_psel_cfg) + { + return true; + } + // Check if the user set meaningful values to struct fields. If not, return false. - if ((p_config->sck_pin == NRF_QSPI_PIN_NOT_CONNECTED) || - (p_config->csn_pin == NRF_QSPI_PIN_NOT_CONNECTED) || - (p_config->io0_pin == NRF_QSPI_PIN_NOT_CONNECTED) || - (p_config->io1_pin == NRF_QSPI_PIN_NOT_CONNECTED)) + if ((p_config->pins.sck_pin == NRF_QSPI_PIN_NOT_CONNECTED) || + (p_config->pins.csn_pin == NRF_QSPI_PIN_NOT_CONNECTED) || + (p_config->pins.io0_pin == NRF_QSPI_PIN_NOT_CONNECTED) || + (p_config->pins.io1_pin == NRF_QSPI_PIN_NOT_CONNECTED)) { return false; } @@ -185,34 +194,40 @@ static bool qspi_pins_configure(nrf_qspi_pins_t const * p_config) QSPI_CSN_DEDICATED = NRF_GPIO_PIN_MAP(0, 18) }; - if ((p_config->sck_pin != QSPI_SCK_DEDICATED) || - (p_config->csn_pin != QSPI_CSN_DEDICATED) || - (p_config->io0_pin != QSPI_IO0_DEDICATED) || - (p_config->io1_pin != QSPI_IO1_DEDICATED) || - (p_config->io2_pin != NRF_QSPI_PIN_NOT_CONNECTED && - p_config->io2_pin != QSPI_IO2_DEDICATED) || - (p_config->io3_pin != NRF_QSPI_PIN_NOT_CONNECTED && - p_config->io3_pin != QSPI_IO3_DEDICATED)) + if ((p_config->pins.sck_pin != QSPI_SCK_DEDICATED) || + (p_config->pins.csn_pin != QSPI_CSN_DEDICATED) || + (p_config->pins.io0_pin != QSPI_IO0_DEDICATED) || + (p_config->pins.io1_pin != QSPI_IO1_DEDICATED) || + (p_config->pins.io2_pin != NRF_QSPI_PIN_NOT_CONNECTED && + p_config->pins.io2_pin != QSPI_IO2_DEDICATED) || + (p_config->pins.io3_pin != NRF_QSPI_PIN_NOT_CONNECTED && + p_config->pins.io3_pin != QSPI_IO3_DEDICATED)) { return false; } #endif - QSPI_PIN_INIT(p_config->sck_pin); - QSPI_PIN_INIT(p_config->csn_pin); - QSPI_PIN_INIT(p_config->io0_pin); - QSPI_PIN_INIT(p_config->io1_pin); - if (p_config->io2_pin != NRF_QSPI_PIN_NOT_CONNECTED) + if (!p_config->skip_gpio_cfg) { - QSPI_PIN_INIT(p_config->io2_pin); + QSPI_PIN_INIT(p_config->pins.sck_pin); + QSPI_PIN_INIT(p_config->pins.csn_pin); + QSPI_PIN_INIT(p_config->pins.io0_pin); + QSPI_PIN_INIT(p_config->pins.io1_pin); + if (p_config->pins.io2_pin != NRF_QSPI_PIN_NOT_CONNECTED) + { + QSPI_PIN_INIT(p_config->pins.io2_pin); + } + if (p_config->pins.io3_pin != NRF_QSPI_PIN_NOT_CONNECTED) + { + QSPI_PIN_INIT(p_config->pins.io3_pin); + } } - if (p_config->io3_pin != NRF_QSPI_PIN_NOT_CONNECTED) + + if (!p_config->skip_psel_cfg) { - QSPI_PIN_INIT(p_config->io3_pin); + nrf_qspi_pins_set(NRF_QSPI, &p_config->pins); } - nrf_qspi_pins_set(NRF_QSPI, p_config); - return true; } @@ -260,7 +275,7 @@ nrfx_err_t nrfx_qspi_init(nrfx_qspi_config_t const * p_config, return NRFX_ERROR_INVALID_STATE; } - if (!qspi_pins_configure(&p_config->pins)) + if (!qspi_pins_configure(p_config)) { return NRFX_ERROR_INVALID_PARAM; } @@ -286,6 +301,7 @@ nrfx_err_t nrfx_qspi_init(nrfx_qspi_config_t const * p_config, m_cb.handler = handler; m_cb.p_context = p_context; + m_cb.skip_gpio_cfg = p_config->skip_gpio_cfg; /* QSPI interrupt is disabled because the device should be enabled in polling mode (wait for activate task event ready) */ @@ -331,7 +347,7 @@ nrfx_err_t nrfx_qspi_cinstr_xfer(nrf_qspi_cinstr_conf_t const * p_config, nrf_qspi_cinstrdata_set(NRF_QSPI, p_config->length, p_tx_buffer); } - /* For custom instruction transfer driver has to switch to blocking mode. + /* For custom instruction transfer driver has to switch to blocking mode. * If driver was previously configured to non-blocking mode, interrupts * will get reenabled before next standard transfer. */ @@ -501,7 +517,10 @@ void nrfx_qspi_uninit(void) nrf_qspi_event_clear(NRF_QSPI, NRF_QSPI_EVENT_READY); - qspi_pins_deconfigure(); + if (!m_cb.skip_gpio_cfg) + { + qspi_pins_deconfigure(); + } m_cb.state = NRFX_QSPI_STATE_UNINITIALIZED; } diff --git a/drivers/src/nrfx_saadc.c b/drivers/src/nrfx_saadc.c index 45090bb9d..3947cc8ae 100644 --- a/drivers/src/nrfx_saadc.c +++ b/drivers/src/nrfx_saadc.c @@ -799,16 +799,21 @@ static void saadc_event_end_handle(void) evt_data.type = NRFX_SAADC_EVT_DONE; evt_data.data.done.p_buffer = m_cb.p_buffer_primary; evt_data.data.done.size = m_cb.size_primary; - m_cb.event_handler(&evt_data); switch (m_cb.saadc_state) { case NRF_SAADC_STATE_SIMPLE_MODE_SAMPLE: nrf_saadc_disable(NRF_SAADC); m_cb.saadc_state = NRF_SAADC_STATE_SIMPLE_MODE; + /* In the simple, non-blocking mode the event handler must be + * called after the internal driver state is updated. This will + * allow starting a new conversion from the event handler context. + */ + m_cb.event_handler(&evt_data); break; case NRF_SAADC_STATE_ADV_MODE_SAMPLE_STARTED: + m_cb.event_handler(&evt_data); m_cb.p_buffer_primary = m_cb.p_buffer_secondary; m_cb.size_primary = m_cb.size_secondary; m_cb.p_buffer_secondary = NULL; diff --git a/drivers/src/nrfx_spi.c b/drivers/src/nrfx_spi.c index 1951a4cc7..6a05a2802 100644 --- a/drivers/src/nrfx_spi.c +++ b/drivers/src/nrfx_spi.c @@ -56,17 +56,66 @@ typedef struct nrfx_drv_state_t state; volatile bool transfer_in_progress; - // [no need for 'volatile' attribute for the following members, as they - // are not concurrently used in IRQ handlers and main line code] - uint8_t ss_pin; - uint8_t orc; - size_t bytes_transferred; - - bool abort; + uint8_t ss_pin; + uint8_t orc; + size_t bytes_transferred; + bool abort; + bool skip_gpio_cfg; } spi_control_block_t; static spi_control_block_t m_cb[NRFX_SPI_ENABLED_COUNT]; +static void configure_pins(NRF_SPI_Type * p_spi, + nrfx_spi_config_t const * p_config) +{ + if (!p_config->skip_gpio_cfg) + { + // Configure pins used by the peripheral: + // - SCK - output with initial value corresponding with the SPI mode + // used: 0 - for modes 0 and 1 (CPOL = 0), 1 - for modes 2 and 3 + // (CPOL = 1); + // according to the reference manual guidelines, this pin and its + // input buffer must always be connected for the SPI to work + nrf_gpio_pin_write(p_config->sck_pin, + p_config->mode <= NRF_SPI_MODE_1 ? 0 : 1); + nrf_gpio_cfg(p_config->sck_pin, + NRF_GPIO_PIN_DIR_OUTPUT, + NRF_GPIO_PIN_INPUT_CONNECT, + NRF_GPIO_PIN_NOPULL, + NRF_GPIO_PIN_S0S1, + NRF_GPIO_PIN_NOSENSE); + // - MOSI (optional) - output with initial value 0 + if (p_config->mosi_pin != NRFX_SPI_PIN_NOT_USED) + { + nrf_gpio_pin_write(p_config->mosi_pin, 0); + nrf_gpio_cfg_output(p_config->mosi_pin); + } + // - MISO (optional) - input + if (p_config->miso_pin != NRFX_SPI_PIN_NOT_USED) + { + nrf_gpio_cfg_input(p_config->miso_pin, p_config->miso_pull); + } + // - Slave Select (optional) - output with initial value 1 (inactive) + if (p_config->ss_pin != NRFX_SPI_PIN_NOT_USED) + { + nrf_gpio_pin_write(p_config->ss_pin, 1); + nrf_gpio_cfg_output(p_config->ss_pin); + } + } + + if (!p_config->skip_psel_cfg) + { + uint32_t mosi_pin = (p_config->mosi_pin != NRFX_SPI_PIN_NOT_USED) + ? p_config->mosi_pin + : NRF_SPI_PIN_NOT_CONNECTED; + uint32_t miso_pin = (p_config->miso_pin != NRFX_SPI_PIN_NOT_USED) + ? p_config->miso_pin + : NRF_SPI_PIN_NOT_CONNECTED; + + nrf_spi_pins_set(p_spi, p_config->sck_pin, mosi_pin, miso_pin); + } +} + nrfx_err_t nrfx_spi_init(nrfx_spi_t const * p_instance, nrfx_spi_config_t const * p_config, nrfx_spi_evt_handler_t handler, @@ -74,6 +123,7 @@ nrfx_err_t nrfx_spi_init(nrfx_spi_t const * p_instance, { NRFX_ASSERT(p_config); spi_control_block_t * p_cb = &m_cb[p_instance->drv_inst_idx]; + NRF_SPI_Type * p_spi = p_instance->p_reg; nrfx_err_t err_code; if (p_cb->state != NRFX_DRV_STATE_UNINITIALIZED) @@ -111,63 +161,15 @@ nrfx_err_t nrfx_spi_init(nrfx_spi_t const * p_instance, p_cb->handler = handler; p_cb->p_context = p_context; - uint32_t mosi_pin; - uint32_t miso_pin; - // Configure pins used by the peripheral: - // - SCK - output with initial value corresponding with the SPI mode used: - // 0 - for modes 0 and 1 (CPOL = 0), 1 - for modes 2 and 3 (CPOL = 1); - // according to the reference manual guidelines this pin and its input - // buffer must always be connected for the SPI to work. - if (p_config->mode <= NRF_SPI_MODE_1) - { - nrf_gpio_pin_clear(p_config->sck_pin); - } - else - { - nrf_gpio_pin_set(p_config->sck_pin); - } - nrf_gpio_cfg(p_config->sck_pin, - NRF_GPIO_PIN_DIR_OUTPUT, - NRF_GPIO_PIN_INPUT_CONNECT, - NRF_GPIO_PIN_NOPULL, - NRF_GPIO_PIN_S0S1, - NRF_GPIO_PIN_NOSENSE); - // - MOSI (optional) - output with initial value 0, - if (p_config->mosi_pin != NRFX_SPI_PIN_NOT_USED) - { - mosi_pin = p_config->mosi_pin; - nrf_gpio_pin_clear(mosi_pin); - nrf_gpio_cfg_output(mosi_pin); - } - else - { - mosi_pin = NRF_SPI_PIN_NOT_CONNECTED; - } - // - MISO (optional) - input, - if (p_config->miso_pin != NRFX_SPI_PIN_NOT_USED) - { - miso_pin = p_config->miso_pin; - nrf_gpio_cfg_input(miso_pin, p_config->miso_pull); - } - else - { - miso_pin = NRF_SPI_PIN_NOT_CONNECTED; - } - // - Slave Select (optional) - output with initial value 1 (inactive). - if (p_config->ss_pin != NRFX_SPI_PIN_NOT_USED) - { - nrf_gpio_pin_set(p_config->ss_pin); - nrf_gpio_cfg_output(p_config->ss_pin); - } - m_cb[p_instance->drv_inst_idx].ss_pin = p_config->ss_pin; + p_cb->skip_gpio_cfg = p_config->skip_gpio_cfg; + p_cb->ss_pin = p_config->ss_pin; + p_cb->orc = p_config->orc; + + configure_pins(p_spi, p_config); - NRF_SPI_Type * p_spi = p_instance->p_reg; - nrf_spi_pins_set(p_spi, p_config->sck_pin, mosi_pin, miso_pin); nrf_spi_frequency_set(p_spi, p_config->frequency); nrf_spi_configure(p_spi, p_config->mode, p_config->bit_order); - m_cb[p_instance->drv_inst_idx].orc = p_config->orc; - nrf_spi_enable(p_spi); if (p_cb->handler) @@ -199,23 +201,26 @@ void nrfx_spi_uninit(nrfx_spi_t const * p_instance) nrf_spi_disable(p_spi); - nrf_gpio_cfg_default(nrf_spi_sck_pin_get(p_spi)); - - uint32_t miso_pin = nrf_spi_miso_pin_get(p_spi); - if (miso_pin != NRF_SPI_PIN_NOT_CONNECTED) + if (!p_cb->skip_gpio_cfg) { - nrf_gpio_cfg_default(miso_pin); - } + nrf_gpio_cfg_default(nrf_spi_sck_pin_get(p_spi)); - uint32_t mosi_pin = nrf_spi_mosi_pin_get(p_spi); - if (mosi_pin != NRF_SPI_PIN_NOT_CONNECTED) - { - nrf_gpio_cfg_default(mosi_pin); - } + uint32_t miso_pin = nrf_spi_miso_pin_get(p_spi); + if (miso_pin != NRF_SPI_PIN_NOT_CONNECTED) + { + nrf_gpio_cfg_default(miso_pin); + } - if (p_cb->ss_pin != NRFX_SPI_PIN_NOT_USED) - { - nrf_gpio_cfg_default(p_cb->ss_pin); + uint32_t mosi_pin = nrf_spi_mosi_pin_get(p_spi); + if (mosi_pin != NRF_SPI_PIN_NOT_CONNECTED) + { + nrf_gpio_cfg_default(mosi_pin); + } + + if (p_cb->ss_pin != NRFX_SPI_PIN_NOT_USED) + { + nrf_gpio_cfg_default(p_cb->ss_pin); + } } #if NRFX_CHECK(NRFX_PRS_ENABLED) @@ -230,7 +235,7 @@ static void finish_transfer(spi_control_block_t * p_cb) // If Slave Select signal is used, this is the time to deactivate it. if (p_cb->ss_pin != NRFX_SPI_PIN_NOT_USED) { - nrf_gpio_pin_set(p_cb->ss_pin); + nrf_gpio_pin_write(p_cb->ss_pin, 1); } // By clearing this flag before calling the handler we allow subsequent @@ -340,7 +345,7 @@ static void spi_xfer(NRF_SPI_Type * p_spi, } while (transfer_byte(p_spi, p_cb)); if (p_cb->ss_pin != NRFX_SPI_PIN_NOT_USED) { - nrf_gpio_pin_set(p_cb->ss_pin); + nrf_gpio_pin_write(p_cb->ss_pin, 1); } } } @@ -377,7 +382,7 @@ nrfx_err_t nrfx_spi_xfer(nrfx_spi_t const * p_instance, if (p_cb->ss_pin != NRFX_SPI_PIN_NOT_USED) { - nrf_gpio_pin_clear(p_cb->ss_pin); + nrf_gpio_pin_write(p_cb->ss_pin, 0); } if (flags) { diff --git a/drivers/src/nrfx_spim.c b/drivers/src/nrfx_spim.c index 28d0749e6..f05002517 100644 --- a/drivers/src/nrfx_spim.c +++ b/drivers/src/nrfx_spim.c @@ -184,19 +184,16 @@ typedef struct nrfx_drv_state_t state; volatile bool transfer_in_progress; + bool skip_gpio_cfg : 1; + bool ss_active_high : 1; #if NRFX_CHECK(NRFX_SPIM_EXTENDED_ENABLED) - bool use_hw_ss; + bool use_hw_ss : 1; #endif - - // [no need for 'volatile' attribute for the following members, as they - // are not concurrently used in IRQ handlers and main line code] - bool ss_active_high; - uint8_t ss_pin; - uint8_t orc; + uint8_t ss_pin; #if NRFX_CHECK(NRFX_SPIM_NRF52_ANOMALY_109_WORKAROUND_ENABLED) - size_t tx_length; - size_t rx_length; + size_t tx_length; + size_t rx_length; #endif } spim_control_block_t; static spim_control_block_t m_cb[NRFX_SPIM_ENABLED_COUNT]; @@ -254,6 +251,129 @@ static void spim_abort(NRF_SPIM_Type * p_spim, spim_control_block_t * p_cb) p_cb->transfer_in_progress = false; } +static void configure_pins(nrfx_spim_t const * p_instance, + nrfx_spim_config_t const * p_config) +{ + NRF_SPIM_Type * p_spim = (NRF_SPIM_Type *)p_instance->p_reg; + + if (!p_config->skip_gpio_cfg) + { + // Configure pin drive - high drive for 32 MHz clock frequency. + nrf_gpio_pin_drive_t pin_drive; +#if NRF_SPIM_HAS_32_MHZ_FREQ + pin_drive = (p_config->frequency == NRF_SPIM_FREQ_32M) + ? NRF_GPIO_PIN_H0H1 + : NRF_GPIO_PIN_S0S1; +#else + pin_drive = NRF_GPIO_PIN_S0S1; +#endif + + // Configure pins used by the peripheral: + // - SCK - output with initial value corresponding with the SPI mode + // used: 0 - for modes 0 and 1 (CPOL = 0), 1 - for modes 2 and 3 + // (CPOL = 1); + // according to the reference manual guidelines, this pin and its + // input buffer must always be connected for the SPI to work + nrf_gpio_pin_write(p_config->sck_pin, + p_config->mode <= NRF_SPIM_MODE_1 ? 0 : 1); + nrf_gpio_cfg(p_config->sck_pin, + NRF_GPIO_PIN_DIR_OUTPUT, + NRF_GPIO_PIN_INPUT_CONNECT, + NRF_GPIO_PIN_NOPULL, + pin_drive, + NRF_GPIO_PIN_NOSENSE); + // - MOSI (optional) - output with initial value 0 + if (p_config->mosi_pin != NRFX_SPIM_PIN_NOT_USED) + { + nrf_gpio_pin_write(p_config->mosi_pin, 0); + nrf_gpio_cfg(p_config->mosi_pin, + NRF_GPIO_PIN_DIR_OUTPUT, + NRF_GPIO_PIN_INPUT_DISCONNECT, + NRF_GPIO_PIN_NOPULL, + pin_drive, + NRF_GPIO_PIN_NOSENSE); + } + // - MISO (optional) - input + if (p_config->miso_pin != NRFX_SPIM_PIN_NOT_USED) + { + nrf_gpio_cfg(p_config->miso_pin, + NRF_GPIO_PIN_DIR_INPUT, + NRF_GPIO_PIN_INPUT_CONNECT, + p_config->miso_pull, + pin_drive, + NRF_GPIO_PIN_NOSENSE); + } + // - Slave Select (optional) - output, initially inactive + if (p_config->ss_pin != NRFX_SPIM_PIN_NOT_USED) + { + nrf_gpio_pin_write(p_config->ss_pin, + p_config->ss_active_high ? 0 : 1); + nrf_gpio_cfg(p_config->ss_pin, + NRF_GPIO_PIN_DIR_OUTPUT, + NRF_GPIO_PIN_INPUT_DISCONNECT, + NRF_GPIO_PIN_NOPULL, + pin_drive, + NRF_GPIO_PIN_NOSENSE); + } +#if NRFX_CHECK(NRFX_SPIM_EXTENDED_ENABLED) + // - DCX (optional) - output. + if (p_config->dcx_pin != NRFX_SPIM_PIN_NOT_USED) + { + nrf_gpio_pin_write(p_config->dcx_pin, 1); + nrf_gpio_cfg(p_config->dcx_pin, + NRF_GPIO_PIN_DIR_OUTPUT, + NRF_GPIO_PIN_INPUT_DISCONNECT, + NRF_GPIO_PIN_NOPULL, + pin_drive, + NRF_GPIO_PIN_NOSENSE); + } +#endif + } + + if (!p_config->skip_psel_cfg) + { + uint32_t mosi_pin = (p_config->mosi_pin != NRFX_SPIM_PIN_NOT_USED) + ? p_config->mosi_pin + : NRF_SPIM_PIN_NOT_CONNECTED; + uint32_t miso_pin = (p_config->miso_pin != NRFX_SPIM_PIN_NOT_USED) + ? p_config->miso_pin + : NRF_SPIM_PIN_NOT_CONNECTED; + + nrf_spim_pins_set(p_spim, p_config->sck_pin, mosi_pin, miso_pin); + +#if NRFX_CHECK(NRFX_SPIM_EXTENDED_ENABLED) + if (SPIM_HW_CSN_PRESENT_VALIDATE(p_instance->drv_inst_idx)) + { + if (p_config->ss_pin != NRFX_SPIM_PIN_NOT_USED && + p_config->use_hw_ss) + { + nrf_spim_csn_configure(p_spim, + p_config->ss_pin, + (p_config->ss_active_high == true + ? NRF_SPIM_CSN_POL_HIGH + : NRF_SPIM_CSN_POL_LOW), + p_config->ss_duration); + } + else + { + nrf_spim_csn_configure(p_spim, + NRF_SPIM_PIN_NOT_CONNECTED, + NRF_SPIM_CSN_POL_LOW, + 0); + } + } + + if (SPIM_DCX_PRESENT_VALIDATE(p_instance->drv_inst_idx)) + { + uint32_t dcx_pin = (p_config->dcx_pin != NRFX_SPIM_PIN_NOT_USED) + ? p_config->dcx_pin + : NRF_SPIM_PIN_NOT_CONNECTED; + nrf_spim_dcx_pin_set(p_spim, dcx_pin); + } +#endif + } +} + nrfx_err_t nrfx_spim_init(nrfx_spim_t const * p_instance, nrfx_spim_config_t const * p_config, nrfx_spim_evt_handler_t handler, @@ -261,6 +381,7 @@ nrfx_err_t nrfx_spim_init(nrfx_spim_t const * p_instance, { NRFX_ASSERT(p_config); spim_control_block_t * p_cb = &m_cb[p_instance->drv_inst_idx]; + NRF_SPIM_Type * p_spim = (NRF_SPIM_Type *)p_instance->p_reg; nrfx_err_t err_code; if (p_cb->state != NRFX_DRV_STATE_UNINITIALIZED) @@ -290,11 +411,12 @@ nrfx_err_t nrfx_spim_init(nrfx_spim_t const * p_instance, } #endif - NRF_SPIM_Type * p_spim = (NRF_SPIM_Type *)p_instance->p_reg; - #if NRF_SPIM_HAS_32_MHZ_FREQ && defined(NRF5340_XXAA_APPLICATION) - // Check if dedicated SPIM pins are used. - if ((p_spim == NRF_SPIM4) && (p_config->frequency == NRF_SPIM_FREQ_32M)) + // Check if dedicated SPIM pins are used, unless both GPIO configuration + // and pin selection are to be skipped (pin numbers may be not specified + // in such case). + if (!(p_config->skip_gpio_cfg && p_config->skip_psel_cfg) && + (p_spim == NRF_SPIM4) && (p_config->frequency == NRF_SPIM_FREQ_32M)) { enum { SPIM_SCK_DEDICATED = NRF_GPIO_PIN_MAP(0, 8), @@ -353,122 +475,20 @@ nrfx_err_t nrfx_spim_init(nrfx_spim_t const * p_instance, p_cb->handler = handler; p_cb->p_context = p_context; - uint32_t mosi_pin; - uint32_t miso_pin; - // Configure pins used by the peripheral: - // - SCK - output with initial value corresponding with the SPI mode used: - // 0 - for modes 0 and 1 (CPOL = 0), 1 - for modes 2 and 3 (CPOL = 1); - // according to the reference manual guidelines this pin and its input - // buffer must always be connected for the SPI to work. - if (p_config->mode <= NRF_SPIM_MODE_1) - { - nrf_gpio_pin_clear(p_config->sck_pin); - } - else - { - nrf_gpio_pin_set(p_config->sck_pin); - } - - nrf_gpio_pin_drive_t pin_drive; - // Configure pin drive - high drive for 32 MHz clock frequency. -#if NRF_SPIM_HAS_32_MHZ_FREQ - pin_drive = (p_config->frequency == NRF_SPIM_FREQ_32M) ? NRF_GPIO_PIN_H0H1 : NRF_GPIO_PIN_S0S1; -#else - pin_drive = NRF_GPIO_PIN_S0S1; + p_cb->skip_gpio_cfg = p_config->skip_gpio_cfg; + p_cb->ss_active_high = p_config->ss_active_high; +#if NRFX_CHECK(NRFX_SPIM_EXTENDED_ENABLED) + p_cb->use_hw_ss = p_config->use_hw_ss; #endif - - nrf_gpio_cfg(p_config->sck_pin, - NRF_GPIO_PIN_DIR_OUTPUT, - NRF_GPIO_PIN_INPUT_CONNECT, - NRF_GPIO_PIN_NOPULL, - pin_drive, - NRF_GPIO_PIN_NOSENSE); - // - MOSI (optional) - output with initial value 0, - if (p_config->mosi_pin != NRFX_SPIM_PIN_NOT_USED) - { - mosi_pin = p_config->mosi_pin; - nrf_gpio_pin_clear(mosi_pin); - nrf_gpio_cfg(mosi_pin, - NRF_GPIO_PIN_DIR_OUTPUT, - NRF_GPIO_PIN_INPUT_DISCONNECT, - NRF_GPIO_PIN_NOPULL, - pin_drive, - NRF_GPIO_PIN_NOSENSE); - } - else - { - mosi_pin = NRF_SPIM_PIN_NOT_CONNECTED; - } - // - MISO (optional) - input, - if (p_config->miso_pin != NRFX_SPIM_PIN_NOT_USED) - { - miso_pin = p_config->miso_pin; - nrf_gpio_cfg(miso_pin, - NRF_GPIO_PIN_DIR_INPUT, - NRF_GPIO_PIN_INPUT_CONNECT, - p_config->miso_pull, - pin_drive, - NRF_GPIO_PIN_NOSENSE); - } - else - { - miso_pin = NRF_SPIM_PIN_NOT_CONNECTED; - } - // - Slave Select (optional) - output with initial value 1 (inactive). - - // 'p_cb->ss_pin' variable is used during transfers to check if SS pin should be toggled, - // so this field needs to be initialized even if the pin is not used. p_cb->ss_pin = p_config->ss_pin; - if (p_config->ss_pin != NRFX_SPIM_PIN_NOT_USED) - { - if (p_config->ss_active_high) - { - nrf_gpio_pin_clear(p_config->ss_pin); - } - else - { - nrf_gpio_pin_set(p_config->ss_pin); - } - nrf_gpio_cfg(p_config->ss_pin, - NRF_GPIO_PIN_DIR_OUTPUT, - NRF_GPIO_PIN_INPUT_DISCONNECT, - NRF_GPIO_PIN_NOPULL, - pin_drive, - NRF_GPIO_PIN_NOSENSE); -#if NRFX_CHECK(NRFX_SPIM_EXTENDED_ENABLED) - if (p_config->use_hw_ss) - { - p_cb->use_hw_ss = p_config->use_hw_ss; - nrf_spim_csn_configure(p_spim, - p_config->ss_pin, - (p_config->ss_active_high == true ? - NRF_SPIM_CSN_POL_HIGH : NRF_SPIM_CSN_POL_LOW), - p_config->ss_duration); - } -#endif - p_cb->ss_active_high = p_config->ss_active_high; - } + configure_pins(p_instance, p_config); #if NRFX_CHECK(NRFX_SPIM_EXTENDED_ENABLED) - // - DCX (optional) - output. - if (p_config->dcx_pin != NRFX_SPIM_PIN_NOT_USED) - { - nrf_gpio_pin_set(p_config->dcx_pin); - nrf_gpio_cfg(p_config->dcx_pin, - NRF_GPIO_PIN_DIR_OUTPUT, - NRF_GPIO_PIN_INPUT_DISCONNECT, - NRF_GPIO_PIN_NOPULL, - pin_drive, - NRF_GPIO_PIN_NOSENSE); - nrf_spim_dcx_pin_set(p_spim, p_config->dcx_pin); - } - // Change rx delay nrf_spim_iftiming_set(p_spim, p_config->rx_delay); #endif - nrf_spim_pins_set(p_spim, p_config->sck_pin, mosi_pin, miso_pin); nrf_spim_frequency_set(p_spim, p_config->frequency); nrf_spim_configure(p_spim, p_config->mode, p_config->bit_order); @@ -520,18 +540,21 @@ void nrfx_spim_uninit(nrfx_spim_t const * p_instance) nrf_spim_disable(p_spim); - spim_pin_uninit(nrf_spim_sck_pin_get(p_spim)); - spim_pin_uninit(nrf_spim_miso_pin_get(p_spim)); - spim_pin_uninit(nrf_spim_mosi_pin_get(p_spim)); -#if NRFX_CHECK(NRFX_SPIM_EXTENDED_ENABLED) - if (SPIM_DCX_PRESENT_VALIDATE(p_instance->drv_inst_idx)) + if (!p_cb->skip_gpio_cfg) { - spim_pin_uninit(nrf_spim_dcx_pin_get(p_spim)); - } + spim_pin_uninit(nrf_spim_sck_pin_get(p_spim)); + spim_pin_uninit(nrf_spim_miso_pin_get(p_spim)); + spim_pin_uninit(nrf_spim_mosi_pin_get(p_spim)); +#if NRFX_CHECK(NRFX_SPIM_EXTENDED_ENABLED) + if (SPIM_DCX_PRESENT_VALIDATE(p_instance->drv_inst_idx)) + { + spim_pin_uninit(nrf_spim_dcx_pin_get(p_spim)); + } #endif - if (p_cb->ss_pin != NRFX_SPIM_PIN_NOT_USED) - { - nrf_gpio_cfg_default(p_cb->ss_pin); + if (p_cb->ss_pin != NRFX_SPIM_PIN_NOT_USED) + { + nrf_gpio_cfg_default(p_cb->ss_pin); + } } #if NRFX_CHECK(USE_WORKAROUND_FOR_ANOMALY_195) @@ -562,25 +585,26 @@ nrfx_err_t nrfx_spim_xfer_dcx(nrfx_spim_t const * p_instance, } #endif -static void finish_transfer(spim_control_block_t * p_cb) +static void set_ss_pin_state(spim_control_block_t * p_cb, bool active) { - // If Slave Select signal is used, this is the time to deactivate it. - if (p_cb->ss_pin != NRFX_SPIM_PIN_NOT_USED) - { #if NRFX_CHECK(NRFX_SPIM_EXTENDED_ENABLED) - if (!p_cb->use_hw_ss) + if (p_cb->use_hw_ss) + { + return; + } #endif - { - if (p_cb->ss_active_high) - { - nrf_gpio_pin_clear(p_cb->ss_pin); - } - else - { - nrf_gpio_pin_set(p_cb->ss_pin); - } - } + + if (p_cb->ss_pin != NRFX_SPIM_PIN_NOT_USED) + { + nrf_gpio_pin_write(p_cb->ss_pin, + p_cb->ss_active_high ? active : !active); } +} + +static void finish_transfer(spim_control_block_t * p_cb) +{ + // If Slave Select signal is used, this is the time to deactivate it. + set_ss_pin_state(p_cb, false); // By clearing this flag before calling the handler we allow subsequent // transfers to be started directly from the handler function. @@ -691,22 +715,7 @@ static nrfx_err_t spim_xfer(NRF_SPIM_Type * p_spim, anomaly_198_disable(); } #endif - if (p_cb->ss_pin != NRFX_SPIM_PIN_NOT_USED) - { -#if NRFX_CHECK(NRFX_SPIM_EXTENDED_ENABLED) - if (!p_cb->use_hw_ss) -#endif - { - if (p_cb->ss_active_high) - { - nrf_gpio_pin_clear(p_cb->ss_pin); - } - else - { - nrf_gpio_pin_set(p_cb->ss_pin); - } - } - } + set_ss_pin_state(p_cb, false); } else { @@ -729,6 +738,9 @@ nrfx_err_t nrfx_spim_xfer(nrfx_spim_t const * p_instance, p_xfer_desc->rx_length, p_xfer_desc->tx_length)); NRFX_ASSERT(!(flags & NRFX_SPIM_FLAG_HOLD_XFER) || +#if NRFX_CHECK(NRFX_SPIM_EXTENDED_ENABLED) + p_cb->use_hw_ss || +#endif (p_cb->ss_pin == NRFX_SPIM_PIN_NOT_USED)); nrfx_err_t err_code = NRFX_SUCCESS; @@ -752,22 +764,7 @@ nrfx_err_t nrfx_spim_xfer(nrfx_spim_t const * p_instance, p_cb->evt.xfer_desc = *p_xfer_desc; - if (p_cb->ss_pin != NRFX_SPIM_PIN_NOT_USED) - { -#if NRFX_CHECK(NRFX_SPIM_EXTENDED_ENABLED) - if (!p_cb->use_hw_ss) -#endif - { - if (p_cb->ss_active_high) - { - nrf_gpio_pin_set(p_cb->ss_pin); - } - else - { - nrf_gpio_pin_clear(p_cb->ss_pin); - } - } - } + set_ss_pin_state(p_cb, true); return spim_xfer(p_instance->p_reg, p_cb, p_xfer_desc, flags); } diff --git a/drivers/src/nrfx_spis.c b/drivers/src/nrfx_spis.c index 88654a016..44c545b79 100644 --- a/drivers/src/nrfx_spis.c +++ b/drivers/src/nrfx_spis.c @@ -121,10 +121,68 @@ typedef struct nrfx_drv_state_t state; //!< driver initialization state. volatile nrfx_spis_state_t spi_state; //!< SPI slave state. void * p_context; //!< Context set on initialization. + bool skip_gpio_cfg; } spis_cb_t; static spis_cb_t m_cb[NRFX_SPIS_ENABLED_COUNT]; +static void configure_pins(NRF_SPIS_Type * p_spis, + nrfx_spis_config_t const * p_config) +{ + if (!p_config->skip_gpio_cfg) + { + nrf_gpio_cfg(p_config->sck_pin, + NRF_GPIO_PIN_DIR_INPUT, + NRF_GPIO_PIN_INPUT_CONNECT, + NRF_GPIO_PIN_NOPULL, + NRF_GPIO_PIN_S0S1, + NRF_GPIO_PIN_NOSENSE); + + if (p_config->mosi_pin != NRFX_SPIS_PIN_NOT_USED) + { + nrf_gpio_cfg(p_config->mosi_pin, + NRF_GPIO_PIN_DIR_INPUT, + NRF_GPIO_PIN_INPUT_CONNECT, + NRF_GPIO_PIN_NOPULL, + NRF_GPIO_PIN_S0S1, + NRF_GPIO_PIN_NOSENSE); + } + + if (p_config->miso_pin != NRFX_SPIS_PIN_NOT_USED) + { + nrf_gpio_cfg(p_config->miso_pin, + NRF_GPIO_PIN_DIR_INPUT, + NRF_GPIO_PIN_INPUT_CONNECT, + NRF_GPIO_PIN_NOPULL, + p_config->miso_drive, + NRF_GPIO_PIN_NOSENSE); + } + + nrf_gpio_cfg(p_config->csn_pin, + NRF_GPIO_PIN_DIR_INPUT, + NRF_GPIO_PIN_INPUT_CONNECT, + p_config->csn_pullup, + NRF_GPIO_PIN_S0S1, + NRF_GPIO_PIN_NOSENSE); + } + + if (!p_config->skip_psel_cfg) + { + uint32_t mosi_pin = (p_config->mosi_pin != NRFX_SPIS_PIN_NOT_USED) + ? p_config->mosi_pin + : NRF_SPIS_PIN_NOT_CONNECTED; + uint32_t miso_pin = (p_config->miso_pin != NRFX_SPIS_PIN_NOT_USED) + ? p_config->miso_pin + : NRF_SPIS_PIN_NOT_CONNECTED; + + nrf_spis_pins_set(p_spis, + p_config->sck_pin, + mosi_pin, + miso_pin, + p_config->csn_pin); + } +} + nrfx_err_t nrfx_spis_init(nrfx_spis_t const * p_instance, nrfx_spis_config_t const * p_config, nrfx_spis_event_handler_t event_handler, @@ -180,55 +238,9 @@ nrfx_err_t nrfx_spis_init(nrfx_spis_t const * p_instance, } #endif // NRFX_CHECK(NRFX_PRS_ENABLED) - // Configure the SPI pins for input. - uint32_t mosi_pin; - uint32_t miso_pin; + p_cb->skip_gpio_cfg = p_config->skip_gpio_cfg; - if (p_config->miso_pin != NRFX_SPIS_PIN_NOT_USED) - { - nrf_gpio_cfg(p_config->miso_pin, - NRF_GPIO_PIN_DIR_INPUT, - NRF_GPIO_PIN_INPUT_CONNECT, - NRF_GPIO_PIN_NOPULL, - p_config->miso_drive, - NRF_GPIO_PIN_NOSENSE); - miso_pin = p_config->miso_pin; - } - else - { - miso_pin = NRF_SPIS_PIN_NOT_CONNECTED; - } - - if (p_config->mosi_pin != NRFX_SPIS_PIN_NOT_USED) - { - nrf_gpio_cfg(p_config->mosi_pin, - NRF_GPIO_PIN_DIR_INPUT, - NRF_GPIO_PIN_INPUT_CONNECT, - NRF_GPIO_PIN_NOPULL, - NRF_GPIO_PIN_S0S1, - NRF_GPIO_PIN_NOSENSE); - mosi_pin = p_config->mosi_pin; - } - else - { - mosi_pin = NRF_SPIS_PIN_NOT_CONNECTED; - } - - nrf_gpio_cfg(p_config->csn_pin, - NRF_GPIO_PIN_DIR_INPUT, - NRF_GPIO_PIN_INPUT_CONNECT, - p_config->csn_pullup, - NRF_GPIO_PIN_S0S1, - NRF_GPIO_PIN_NOSENSE); - - nrf_gpio_cfg(p_config->sck_pin, - NRF_GPIO_PIN_DIR_INPUT, - NRF_GPIO_PIN_INPUT_CONNECT, - NRF_GPIO_PIN_NOPULL, - NRF_GPIO_PIN_S0S1, - NRF_GPIO_PIN_NOSENSE); - - nrf_spis_pins_set(p_spis, p_config->sck_pin, mosi_pin, miso_pin, p_config->csn_pin); + configure_pins(p_spis, p_config); nrf_spis_rx_buffer_set(p_spis, NULL, 0); nrf_spis_tx_buffer_set(p_spis, NULL, 0); @@ -305,19 +317,22 @@ void nrfx_spis_uninit(nrfx_spis_t const * p_instance) nrf_spis_int_disable(p_spis, DISABLE_ALL); #undef DISABLE_ALL - nrf_gpio_cfg_default(nrf_spis_sck_pin_get(p_spis)); - nrf_gpio_cfg_default(nrf_spis_csn_pin_get(p_spis)); - - uint32_t miso_pin = nrf_spis_miso_pin_get(p_spis); - if (miso_pin != NRF_SPIS_PIN_NOT_CONNECTED) + if (!p_cb->skip_gpio_cfg) { - nrf_gpio_cfg_default(miso_pin); - } + nrf_gpio_cfg_default(nrf_spis_sck_pin_get(p_spis)); + nrf_gpio_cfg_default(nrf_spis_csn_pin_get(p_spis)); - uint32_t mosi_pin = nrf_spis_mosi_pin_get(p_spis); - if (mosi_pin != NRF_SPIS_PIN_NOT_CONNECTED) - { - nrf_gpio_cfg_default(mosi_pin); + uint32_t miso_pin = nrf_spis_miso_pin_get(p_spis); + if (miso_pin != NRF_SPIS_PIN_NOT_CONNECTED) + { + nrf_gpio_cfg_default(miso_pin); + } + + uint32_t mosi_pin = nrf_spis_mosi_pin_get(p_spis); + if (mosi_pin != NRF_SPIS_PIN_NOT_CONNECTED) + { + nrf_gpio_cfg_default(mosi_pin); + } } #if NRFX_CHECK(NRFX_PRS_ENABLED) diff --git a/drivers/src/nrfx_twi.c b/drivers/src/nrfx_twi.c index de16c2527..0e74f6edc 100644 --- a/drivers/src/nrfx_twi.c +++ b/drivers/src/nrfx_twi.c @@ -109,6 +109,7 @@ typedef struct bool repeated; size_t bytes_transferred; bool hold_bus_uninit; + bool skip_gpio_cfg; } twi_control_block_t; static twi_control_block_t m_cb[NRFX_TWI_ENABLED_COUNT]; @@ -161,8 +162,8 @@ nrfx_err_t nrfx_twi_init(nrfx_twi_t const * p_instance, void * p_context) { NRFX_ASSERT(p_config); - NRFX_ASSERT(p_config->scl != p_config->sda); twi_control_block_t * p_cb = &m_cb[p_instance->drv_inst_idx]; + NRF_TWI_Type * p_twi = p_instance->p_twi; nrfx_err_t err_code; if (p_cb->state != NRFX_DRV_STATE_UNINITIALIZED) @@ -201,16 +202,23 @@ nrfx_err_t nrfx_twi_init(nrfx_twi_t const * p_instance, p_cb->repeated = false; p_cb->busy = false; p_cb->hold_bus_uninit = p_config->hold_bus_uninit; + p_cb->skip_gpio_cfg = p_config->skip_gpio_cfg; /* To secure correct signal levels on the pins used by the TWI master when the system is in OFF mode, and when the TWI master is disabled, these pins must be configured in the GPIO peripheral. */ - TWI_PIN_INIT(p_config->scl); - TWI_PIN_INIT(p_config->sda); + if (!p_config->skip_gpio_cfg) + { + TWI_PIN_INIT(p_config->scl); + TWI_PIN_INIT(p_config->sda); + } + + if (!p_config->skip_psel_cfg) + { + nrf_twi_pins_set(p_twi, p_config->scl, p_config->sda); + } - NRF_TWI_Type * p_twi = p_instance->p_twi; - nrf_twi_pins_set(p_twi, p_config->scl, p_config->sda); nrf_twi_frequency_set(p_twi, (nrf_twi_frequency_t)p_config->frequency); @@ -243,7 +251,7 @@ void nrfx_twi_uninit(nrfx_twi_t const * p_instance) nrfx_prs_release(p_instance->p_twi); #endif - if (!p_cb->hold_bus_uninit) + if (!p_cb->skip_gpio_cfg && !p_cb->hold_bus_uninit) { nrf_gpio_cfg_default(nrf_twi_scl_pin_get(p_instance->p_twi)); nrf_gpio_cfg_default(nrf_twi_sda_pin_get(p_instance->p_twi)); diff --git a/drivers/src/nrfx_twim.c b/drivers/src/nrfx_twim.c index 17927daa3..ec9097970 100644 --- a/drivers/src/nrfx_twim.c +++ b/drivers/src/nrfx_twim.c @@ -132,6 +132,7 @@ typedef struct bool repeated; uint8_t bytes_transferred; bool hold_bus_uninit; + bool skip_gpio_cfg; #if NRFX_CHECK(NRFX_TWIM_NRF52_ANOMALY_109_WORKAROUND_ENABLED) nrf_twim_frequency_t bus_frequency; #endif @@ -218,6 +219,14 @@ static bool xfer_completeness_check(NRF_TWIM_Type * p_twim, twim_control_block_t static bool twim_pins_configure(NRF_TWIM_Type * p_twim, nrfx_twim_config_t const * p_config) { + // If both GPIO configuration and pin selection are to be skipped, + // the pin numbers may be not specified at all, so even validation + // of those numbers cannot be performed. + if (p_config->skip_gpio_cfg && p_config->skip_psel_cfg) + { + return true; + } + nrf_gpio_pin_drive_t drive; #if NRF_TWIM_HAS_1000_KHZ_FREQ && defined(NRF5340_XXAA) @@ -246,10 +255,16 @@ static bool twim_pins_configure(NRF_TWIM_Type * p_twim, nrfx_twim_config_t const master when the system is in OFF mode, and when the TWI master is disabled, these pins must be configured in the GPIO peripheral. */ - TWIM_PIN_INIT(p_config->scl, drive); - TWIM_PIN_INIT(p_config->sda, drive); + if (!p_config->skip_gpio_cfg) + { + TWIM_PIN_INIT(p_config->scl, drive); + TWIM_PIN_INIT(p_config->sda, drive); + } - nrf_twim_pins_set(p_twim, p_config->scl, p_config->sda); + if (!p_config->skip_psel_cfg) + { + nrf_twim_pins_set(p_twim, p_config->scl, p_config->sda); + } return true; } @@ -260,8 +275,8 @@ nrfx_err_t nrfx_twim_init(nrfx_twim_t const * p_instance, void * p_context) { NRFX_ASSERT(p_config); - NRFX_ASSERT(p_config->scl != p_config->sda); twim_control_block_t * p_cb = &m_cb[p_instance->drv_inst_idx]; + NRF_TWIM_Type * p_twim = p_instance->p_twim; nrfx_err_t err_code; if (p_cb->state != NRFX_DRV_STATE_UNINITIALIZED) @@ -305,11 +320,11 @@ nrfx_err_t nrfx_twim_init(nrfx_twim_t const * p_instance, p_cb->repeated = false; p_cb->busy = false; p_cb->hold_bus_uninit = p_config->hold_bus_uninit; + p_cb->skip_gpio_cfg = p_config->skip_gpio_cfg; #if NRFX_CHECK(NRFX_TWIM_NRF52_ANOMALY_109_WORKAROUND_ENABLED) p_cb->bus_frequency = (nrf_twim_frequency_t)p_config->frequency; #endif - NRF_TWIM_Type * p_twim = p_instance->p_twim; if (!twim_pins_configure(p_twim, p_config)) { return NRFX_ERROR_INVALID_PARAM; @@ -346,7 +361,7 @@ void nrfx_twim_uninit(nrfx_twim_t const * p_instance) nrfx_prs_release(p_instance->p_twim); #endif - if (!p_cb->hold_bus_uninit) + if (!p_cb->skip_gpio_cfg && !p_cb->hold_bus_uninit) { nrf_gpio_cfg_default(nrf_twim_scl_pin_get(p_instance->p_twim)); nrf_gpio_cfg_default(nrf_twim_sda_pin_get(p_instance->p_twim)); diff --git a/drivers/src/nrfx_twis.c b/drivers/src/nrfx_twis.c index b4f865066..71d9b9611 100644 --- a/drivers/src/nrfx_twis.c +++ b/drivers/src/nrfx_twis.c @@ -85,6 +85,7 @@ typedef struct volatile nrfx_twis_substate_t substate; volatile bool semaphore; + bool skip_gpio_cfg; } twis_control_block_t; static twis_control_block_t m_cb[NRFX_TWIS_ENABLED_COUNT]; @@ -129,9 +130,6 @@ static inline void nrfx_twis_swreset(NRF_TWIS_Type * p_reg) /* Disable TWIS */ nrf_twis_disable(p_reg); - /* Disconnect pins */ - nrf_twis_pins_set(p_reg, ~0U, ~0U); - /* Disable interrupt global for the instance */ NRFX_IRQ_DISABLE(nrfx_get_irq_number(p_reg)); @@ -459,7 +457,6 @@ nrfx_err_t nrfx_twis_init(nrfx_twis_t const * p_instance, nrfx_twis_event_handler_t event_handler) { NRFX_ASSERT(p_config); - NRFX_ASSERT(p_config->scl != p_config->sda); nrfx_err_t err_code; NRF_TWIS_Type * p_reg = p_instance->p_reg; @@ -505,8 +502,18 @@ nrfx_err_t nrfx_twis_init(nrfx_twis_t const * p_instance, nrfx_twis_swreset(p_reg); } - nrfx_twis_config_pin(p_config->scl, p_config->scl_pull); - nrfx_twis_config_pin(p_config->sda, p_config->sda_pull); + p_cb->skip_gpio_cfg = p_config->skip_gpio_cfg; + + if (!p_config->skip_gpio_cfg) + { + nrfx_twis_config_pin(p_config->scl, p_config->scl_pull); + nrfx_twis_config_pin(p_config->sda, p_config->sda_pull); + } + + if (!p_config->skip_psel_cfg) + { + nrf_twis_pins_set(p_reg, p_config->scl, p_config->sda); + } uint32_t addr_mask = 0; if (0 == (p_config->addr[0] | p_config->addr[1])) @@ -533,7 +540,6 @@ nrfx_err_t nrfx_twis_init(nrfx_twis_t const * p_instance, NRFX_IRQ_ENABLE(nrfx_get_irq_number(p_reg)); /* Configure */ - nrf_twis_pins_set (p_reg, p_config->scl, p_config->sda); nrf_twis_address_set (p_reg, 0, p_config->addr[0]); nrf_twis_address_set (p_reg, 1, p_config->addr[1]); nrf_twis_config_address_set(p_reg, (nrf_twis_config_addr_mask_t)addr_mask); @@ -559,13 +565,13 @@ void nrfx_twis_uninit(nrfx_twis_t const * p_instance) twis_control_block_t * p_cb = &m_cb[p_instance->drv_inst_idx]; NRFX_ASSERT(p_cb->state != NRFX_DRV_STATE_UNINITIALIZED); - uint32_t scl_pin = nrf_twis_scl_pin_get(p_reg); - uint32_t sda_pin = nrf_twis_sda_pin_get(p_reg); - nrfx_twis_swreset(p_reg); - nrf_gpio_cfg_default(scl_pin); - nrf_gpio_cfg_default(sda_pin); + if (!p_cb->skip_gpio_cfg) + { + nrf_gpio_cfg_default(nrf_twis_scl_pin_get(p_reg)); + nrf_gpio_cfg_default(nrf_twis_sda_pin_get(p_reg)); + } #if NRFX_CHECK(NRFX_PRS_ENABLED) nrfx_prs_release(p_reg); diff --git a/drivers/src/nrfx_uart.c b/drivers/src/nrfx_uart.c index 4b671774f..bb8067dfc 100644 --- a/drivers/src/nrfx_uart.c +++ b/drivers/src/nrfx_uart.c @@ -68,37 +68,54 @@ typedef struct volatile bool tx_abort; bool rx_enabled; nrfx_drv_state_t state; + bool skip_gpio_cfg : 1; + bool skip_psel_cfg : 1; } uart_control_block_t; static uart_control_block_t m_cb[NRFX_UART_ENABLED_COUNT]; static void apply_config(nrfx_uart_t const * p_instance, nrfx_uart_config_t const * p_config) { - if (p_config->pseltxd != NRF_UART_PSEL_DISCONNECTED) + nrf_uart_baudrate_set(p_instance->p_reg, p_config->baudrate); + nrf_uart_configure(p_instance->p_reg, &p_config->hal_cfg); + + if (!p_config->skip_gpio_cfg) { - nrf_gpio_pin_set(p_config->pseltxd); - nrf_gpio_cfg_output(p_config->pseltxd); + if (p_config->pseltxd != NRF_UART_PSEL_DISCONNECTED) + { + nrf_gpio_pin_set(p_config->pseltxd); + nrf_gpio_cfg_output(p_config->pseltxd); + } + if (p_config->pselrxd != NRF_UART_PSEL_DISCONNECTED) + { + nrf_gpio_cfg_input(p_config->pselrxd, NRF_GPIO_PIN_NOPULL); + } } - if (p_config->pselrxd != NRF_UART_PSEL_DISCONNECTED) + if (!p_config->skip_psel_cfg) { - nrf_gpio_cfg_input(p_config->pselrxd, NRF_GPIO_PIN_NOPULL); + nrf_uart_txrx_pins_set(p_instance->p_reg, + p_config->pseltxd, p_config->pselrxd); } - nrf_uart_baudrate_set(p_instance->p_reg, p_config->baudrate); - nrf_uart_configure(p_instance->p_reg, &p_config->hal_cfg); - nrf_uart_txrx_pins_set(p_instance->p_reg, p_config->pseltxd, p_config->pselrxd); if (p_config->hal_cfg.hwfc == NRF_UART_HWFC_ENABLED) { - if (p_config->pselcts != NRF_UART_PSEL_DISCONNECTED) + if (!p_config->skip_gpio_cfg) { - nrf_gpio_cfg_input(p_config->pselcts, NRF_GPIO_PIN_NOPULL); + if (p_config->pselrts != NRF_UART_PSEL_DISCONNECTED) + { + nrf_gpio_pin_set(p_config->pselrts); + nrf_gpio_cfg_output(p_config->pselrts); + } + if (p_config->pselcts != NRF_UART_PSEL_DISCONNECTED) + { + nrf_gpio_cfg_input(p_config->pselcts, NRF_GPIO_PIN_NOPULL); + } } - if (p_config->pselrts != NRF_UART_PSEL_DISCONNECTED) + if (!p_config->skip_psel_cfg) { - nrf_gpio_pin_set(p_config->pselrts); - nrf_gpio_cfg_output(p_config->pselrts); + nrf_uart_hwfc_pins_set(p_instance->p_reg, + p_config->pselrts, p_config->pselcts); } - nrf_uart_hwfc_pins_set(p_instance->p_reg, p_config->pselrts, p_config->pselcts); } } @@ -125,6 +142,8 @@ static void interrupts_disable(nrfx_uart_t const * p_instance) static void pins_to_default(nrfx_uart_t const * p_instance) { + uart_control_block_t const * p_cb = &m_cb[p_instance->drv_inst_idx]; + /* Reset pins to default states */ uint32_t txd; uint32_t rxd; @@ -135,24 +154,31 @@ static void pins_to_default(nrfx_uart_t const * p_instance) rxd = nrf_uart_rx_pin_get(p_instance->p_reg); rts = nrf_uart_rts_pin_get(p_instance->p_reg); cts = nrf_uart_cts_pin_get(p_instance->p_reg); - nrf_uart_txrx_pins_disconnect(p_instance->p_reg); - nrf_uart_hwfc_pins_disconnect(p_instance->p_reg); - if (txd != NRF_UART_PSEL_DISCONNECTED) + if (!p_cb->skip_psel_cfg) { - nrf_gpio_cfg_default(txd); + nrf_uart_txrx_pins_disconnect(p_instance->p_reg); + nrf_uart_hwfc_pins_disconnect(p_instance->p_reg); } - if (rxd != NRF_UART_PSEL_DISCONNECTED) - { - nrf_gpio_cfg_default(rxd); - } - if (cts != NRF_UART_PSEL_DISCONNECTED) - { - nrf_gpio_cfg_default(cts); - } - if (rts != NRF_UART_PSEL_DISCONNECTED) + + if (!p_cb->skip_gpio_cfg) { - nrf_gpio_cfg_default(rts); + if (txd != NRF_UART_PSEL_DISCONNECTED) + { + nrf_gpio_cfg_default(txd); + } + if (rxd != NRF_UART_PSEL_DISCONNECTED) + { + nrf_gpio_cfg_default(rxd); + } + if (cts != NRF_UART_PSEL_DISCONNECTED) + { + nrf_gpio_cfg_default(cts); + } + if (rts != NRF_UART_PSEL_DISCONNECTED) + { + nrf_gpio_cfg_default(rts); + } } } @@ -190,6 +216,9 @@ nrfx_err_t nrfx_uart_init(nrfx_uart_t const * p_instance, } #endif // NRFX_CHECK(NRFX_PRS_ENABLED) + p_cb->skip_gpio_cfg = p_config->skip_gpio_cfg; + p_cb->skip_psel_cfg = p_config->skip_psel_cfg; + apply_config(p_instance, p_config); p_cb->handler = event_handler; diff --git a/drivers/src/nrfx_uarte.c b/drivers/src/nrfx_uarte.c index b6a6c20b6..f1ffa083d 100644 --- a/drivers/src/nrfx_uarte.c +++ b/drivers/src/nrfx_uarte.c @@ -99,37 +99,54 @@ typedef struct size_t rx_secondary_buffer_length; nrfx_drv_state_t state; bool rx_aborted; + bool skip_gpio_cfg : 1; + bool skip_psel_cfg : 1; } uarte_control_block_t; static uarte_control_block_t m_cb[NRFX_UARTE_ENABLED_COUNT]; static void apply_config(nrfx_uarte_t const * p_instance, nrfx_uarte_config_t const * p_config) { - if (p_config->pseltxd != NRF_UARTE_PSEL_DISCONNECTED) + nrf_uarte_baudrate_set(p_instance->p_reg, p_config->baudrate); + nrf_uarte_configure(p_instance->p_reg, &p_config->hal_cfg); + + if (!p_config->skip_gpio_cfg) { - nrf_gpio_pin_set(p_config->pseltxd); - nrf_gpio_cfg_output(p_config->pseltxd); + if (p_config->pseltxd != NRF_UARTE_PSEL_DISCONNECTED) + { + nrf_gpio_pin_set(p_config->pseltxd); + nrf_gpio_cfg_output(p_config->pseltxd); + } + if (p_config->pselrxd != NRF_UARTE_PSEL_DISCONNECTED) + { + nrf_gpio_cfg_input(p_config->pselrxd, NRF_GPIO_PIN_NOPULL); + } } - if (p_config->pselrxd != NRF_UARTE_PSEL_DISCONNECTED) + if (!p_config->skip_psel_cfg) { - nrf_gpio_cfg_input(p_config->pselrxd, NRF_GPIO_PIN_NOPULL); + nrf_uarte_txrx_pins_set(p_instance->p_reg, + p_config->pseltxd, p_config->pselrxd); } - nrf_uarte_baudrate_set(p_instance->p_reg, p_config->baudrate); - nrf_uarte_configure(p_instance->p_reg, &p_config->hal_cfg); - nrf_uarte_txrx_pins_set(p_instance->p_reg, p_config->pseltxd, p_config->pselrxd); if (p_config->hal_cfg.hwfc == NRF_UARTE_HWFC_ENABLED) { - if (p_config->pselcts != NRF_UARTE_PSEL_DISCONNECTED) + if (!p_config->skip_gpio_cfg) { - nrf_gpio_cfg_input(p_config->pselcts, NRF_GPIO_PIN_NOPULL); + if (p_config->pselrts != NRF_UARTE_PSEL_DISCONNECTED) + { + nrf_gpio_pin_set(p_config->pselrts); + nrf_gpio_cfg_output(p_config->pselrts); + } + if (p_config->pselcts != NRF_UARTE_PSEL_DISCONNECTED) + { + nrf_gpio_cfg_input(p_config->pselcts, NRF_GPIO_PIN_NOPULL); + } } - if (p_config->pselrts != NRF_UARTE_PSEL_DISCONNECTED) + if (!p_config->skip_psel_cfg) { - nrf_gpio_pin_set(p_config->pselrts); - nrf_gpio_cfg_output(p_config->pselrts); + nrf_uarte_hwfc_pins_set(p_instance->p_reg, + p_config->pselrts, p_config->pselcts); } - nrf_uarte_hwfc_pins_set(p_instance->p_reg, p_config->pselrts, p_config->pselcts); } } @@ -163,6 +180,8 @@ static void interrupts_disable(nrfx_uarte_t const * p_instance) static void pins_to_default(nrfx_uarte_t const * p_instance) { + uarte_control_block_t const * p_cb = &m_cb[p_instance->drv_inst_idx]; + /* Reset pins to default states */ uint32_t txd; uint32_t rxd; @@ -173,24 +192,30 @@ static void pins_to_default(nrfx_uarte_t const * p_instance) rxd = nrf_uarte_rx_pin_get(p_instance->p_reg); rts = nrf_uarte_rts_pin_get(p_instance->p_reg); cts = nrf_uarte_cts_pin_get(p_instance->p_reg); - nrf_uarte_txrx_pins_disconnect(p_instance->p_reg); - nrf_uarte_hwfc_pins_disconnect(p_instance->p_reg); - - if (txd != NRF_UARTE_PSEL_DISCONNECTED) + if (!p_cb->skip_psel_cfg) { - nrf_gpio_cfg_default(txd); + nrf_uarte_txrx_pins_disconnect(p_instance->p_reg); + nrf_uarte_hwfc_pins_disconnect(p_instance->p_reg); } - if (rxd != NRF_UARTE_PSEL_DISCONNECTED) - { - nrf_gpio_cfg_default(rxd); - } - if (cts != NRF_UARTE_PSEL_DISCONNECTED) - { - nrf_gpio_cfg_default(cts); - } - if (rts != NRF_UARTE_PSEL_DISCONNECTED) + + if (!p_cb->skip_gpio_cfg) { - nrf_gpio_cfg_default(rts); + if (txd != NRF_UARTE_PSEL_DISCONNECTED) + { + nrf_gpio_cfg_default(txd); + } + if (rxd != NRF_UARTE_PSEL_DISCONNECTED) + { + nrf_gpio_cfg_default(rxd); + } + if (cts != NRF_UARTE_PSEL_DISCONNECTED) + { + nrf_gpio_cfg_default(cts); + } + if (rts != NRF_UARTE_PSEL_DISCONNECTED) + { + nrf_gpio_cfg_default(rts); + } } } @@ -277,6 +302,9 @@ nrfx_err_t nrfx_uarte_init(nrfx_uarte_t const * p_instance, } #endif // NRFX_CHECK(NRFX_PRS_ENABLED) + p_cb->skip_gpio_cfg = p_config->skip_gpio_cfg; + p_cb->skip_psel_cfg = p_config->skip_psel_cfg; + apply_config(p_instance, p_config); apply_workaround_for_enable_anomaly(p_instance); @@ -338,6 +366,7 @@ void nrfx_uarte_uninit(nrfx_uarte_t const * p_instance) } nrf_uarte_disable(p_reg); + pins_to_default(p_instance); #if NRFX_CHECK(NRFX_PRS_ENABLED) diff --git a/mdk/nrf.h b/mdk/nrf.h index 63906a44b..bd5c15ac6 100644 --- a/mdk/nrf.h +++ b/mdk/nrf.h @@ -38,7 +38,7 @@ POSSIBILITY OF SUCH DAMAGE. /* MDK version */ #define MDK_MAJOR_VERSION 8 #define MDK_MINOR_VERSION 44 -#define MDK_MICRO_VERSION 1 +#define MDK_MICRO_VERSION 2 /* Define coprocessor domains */ diff --git a/mdk/nrf51.h b/mdk/nrf51.h index fff9d076c..3efaa81b8 100644 --- a/mdk/nrf51.h +++ b/mdk/nrf51.h @@ -32,10 +32,10 @@ * @file nrf51.h * @brief CMSIS HeaderFile * @version 522 - * @date 19. November 2021 - * @note Generated by SVDConv V3.3.35 on Friday, 19.11.2021 12:44:56 + * @date 01. December 2021 + * @note Generated by SVDConv V3.3.35 on Wednesday, 01.12.2021 11:35:41 * from File 'nrf51.svd', - * last modified on Friday, 19.11.2021 11:44:55 + * last modified on Wednesday, 01.12.2021 10:35:40 */ diff --git a/mdk/nrf52.h b/mdk/nrf52.h index 53ac88713..7de143487 100644 --- a/mdk/nrf52.h +++ b/mdk/nrf52.h @@ -32,10 +32,10 @@ * @file nrf52.h * @brief CMSIS HeaderFile * @version 1 - * @date 19. November 2021 - * @note Generated by SVDConv V3.3.35 on Friday, 19.11.2021 12:45:00 + * @date 01. December 2021 + * @note Generated by SVDConv V3.3.35 on Wednesday, 01.12.2021 11:35:45 * from File 'nrf52.svd', - * last modified on Friday, 19.11.2021 11:44:55 + * last modified on Wednesday, 01.12.2021 10:35:40 */ diff --git a/mdk/nrf52805.h b/mdk/nrf52805.h index 0903e79f2..5ff901488 100644 --- a/mdk/nrf52805.h +++ b/mdk/nrf52805.h @@ -32,10 +32,10 @@ * @file nrf52805.h * @brief CMSIS HeaderFile * @version 1 - * @date 19. November 2021 - * @note Generated by SVDConv V3.3.35 on Friday, 19.11.2021 12:44:56 + * @date 01. December 2021 + * @note Generated by SVDConv V3.3.35 on Wednesday, 01.12.2021 11:35:42 * from File 'nrf52805.svd', - * last modified on Friday, 19.11.2021 11:44:55 + * last modified on Wednesday, 01.12.2021 10:35:40 */ diff --git a/mdk/nrf52810.h b/mdk/nrf52810.h index a30bfcab7..3f855a716 100644 --- a/mdk/nrf52810.h +++ b/mdk/nrf52810.h @@ -32,10 +32,10 @@ * @file nrf52810.h * @brief CMSIS HeaderFile * @version 1 - * @date 19. November 2021 - * @note Generated by SVDConv V3.3.35 on Friday, 19.11.2021 12:44:57 + * @date 01. December 2021 + * @note Generated by SVDConv V3.3.35 on Wednesday, 01.12.2021 11:35:42 * from File 'nrf52810.svd', - * last modified on Friday, 19.11.2021 11:44:55 + * last modified on Wednesday, 01.12.2021 10:35:40 */ diff --git a/mdk/nrf52811.h b/mdk/nrf52811.h index 88088cfc4..a1b4b8f43 100644 --- a/mdk/nrf52811.h +++ b/mdk/nrf52811.h @@ -32,10 +32,10 @@ * @file nrf52811.h * @brief CMSIS HeaderFile * @version 1 - * @date 19. November 2021 - * @note Generated by SVDConv V3.3.35 on Friday, 19.11.2021 12:44:58 + * @date 01. December 2021 + * @note Generated by SVDConv V3.3.35 on Wednesday, 01.12.2021 11:35:43 * from File 'nrf52811.svd', - * last modified on Friday, 19.11.2021 11:44:55 + * last modified on Wednesday, 01.12.2021 10:35:40 */ diff --git a/mdk/nrf52820.h b/mdk/nrf52820.h index dfa23f167..4e198aaa4 100644 --- a/mdk/nrf52820.h +++ b/mdk/nrf52820.h @@ -32,10 +32,10 @@ * @file nrf52820.h * @brief CMSIS HeaderFile * @version 1 - * @date 19. November 2021 - * @note Generated by SVDConv V3.3.35 on Friday, 19.11.2021 12:44:59 + * @date 01. December 2021 + * @note Generated by SVDConv V3.3.35 on Wednesday, 01.12.2021 11:35:44 * from File 'nrf52820.svd', - * last modified on Friday, 19.11.2021 11:44:55 + * last modified on Wednesday, 01.12.2021 10:35:40 */ diff --git a/mdk/nrf52833.h b/mdk/nrf52833.h index 6c34273a0..464f5ab2c 100644 --- a/mdk/nrf52833.h +++ b/mdk/nrf52833.h @@ -32,10 +32,10 @@ * @file nrf52833.h * @brief CMSIS HeaderFile * @version 1 - * @date 19. November 2021 - * @note Generated by SVDConv V3.3.35 on Friday, 19.11.2021 12:45:01 + * @date 01. December 2021 + * @note Generated by SVDConv V3.3.35 on Wednesday, 01.12.2021 11:35:46 * from File 'nrf52833.svd', - * last modified on Friday, 19.11.2021 11:44:55 + * last modified on Wednesday, 01.12.2021 10:35:40 */ diff --git a/mdk/nrf52840.h b/mdk/nrf52840.h index 25b6be8d1..1b3971591 100644 --- a/mdk/nrf52840.h +++ b/mdk/nrf52840.h @@ -32,10 +32,10 @@ * @file nrf52840.h * @brief CMSIS HeaderFile * @version 1 - * @date 19. November 2021 - * @note Generated by SVDConv V3.3.35 on Friday, 19.11.2021 12:45:03 + * @date 01. December 2021 + * @note Generated by SVDConv V3.3.35 on Wednesday, 01.12.2021 11:35:48 * from File 'nrf52840.svd', - * last modified on Friday, 19.11.2021 11:44:55 + * last modified on Wednesday, 01.12.2021 10:35:40 */ diff --git a/mdk/nrf52_erratas.h b/mdk/nrf52_erratas.h index 1f9531242..b78f480fa 100644 --- a/mdk/nrf52_erratas.h +++ b/mdk/nrf52_erratas.h @@ -223,6 +223,8 @@ static bool nrf52_errata_246(void) __UNUSED; static bool nrf52_errata_248(void) __UNUSED; static bool nrf52_configuration_249(void) __UNUSED; static bool nrf52_errata_250(void) __UNUSED; +static bool nrf52_errata_251(void) __UNUSED; +static bool nrf52_errata_252(void) __UNUSED; static bool nrf52_configuration_254(void) __UNUSED; static bool nrf52_configuration_255(void) __UNUSED; static bool nrf52_configuration_256(void) __UNUSED; @@ -1052,8 +1054,6 @@ static bool nrf52_errata_20(void) return true; case 0x01ul: return true; - case 0x02ul: - return true; default: return true; } @@ -1898,8 +1898,6 @@ static bool nrf52_errata_36(void) return true; case 0x01ul: return true; - case 0x02ul: - return true; default: return true; } @@ -2754,8 +2752,6 @@ static bool nrf52_errata_55(void) return true; case 0x01ul: return true; - case 0x02ul: - return true; default: return true; } @@ -3228,8 +3224,6 @@ static bool nrf52_errata_66(void) return true; case 0x01ul: return true; - case 0x02ul: - return true; default: return true; } @@ -4075,8 +4069,6 @@ static bool nrf52_errata_78(void) return true; case 0x01ul: return true; - case 0x02ul: - return true; default: return true; } @@ -4667,8 +4659,6 @@ static bool nrf52_errata_87(void) return true; case 0x01ul: return true; - case 0x02ul: - return true; default: return true; } @@ -6649,8 +6639,6 @@ static bool nrf52_errata_136(void) return true; case 0x01ul: return true; - case 0x02ul: - return true; default: return true; } @@ -8137,8 +8125,6 @@ static bool nrf52_errata_170(void) return true; case 0x01ul: return true; - case 0x02ul: - return true; default: return true; } @@ -8373,8 +8359,6 @@ static bool nrf52_errata_173(void) return true; case 0x01ul: return true; - case 0x02ul: - return true; default: return true; } @@ -8591,8 +8575,6 @@ static bool nrf52_errata_176(void) return true; case 0x01ul: return true; - case 0x02ul: - return true; default: return true; } @@ -9130,8 +9112,6 @@ static bool nrf52_errata_183(void) return true; case 0x01ul: return true; - case 0x02ul: - return true; default: return true; } @@ -9250,8 +9230,6 @@ static bool nrf52_errata_184(void) return true; case 0x01ul: return true; - case 0x02ul: - return true; default: return true; } @@ -9408,8 +9386,6 @@ static bool nrf52_errata_187(void) return true; case 0x01ul: return true; - case 0x02ul: - return true; default: return true; } @@ -9538,8 +9514,6 @@ static bool nrf52_errata_190(void) return true; case 0x01ul: return true; - case 0x02ul: - return true; default: return true; } @@ -9854,8 +9828,6 @@ static bool nrf52_errata_194(void) return true; case 0x01ul: return true; - case 0x02ul: - return true; default: return true; } @@ -10022,8 +9994,6 @@ static bool nrf52_errata_196(void) return true; case 0x01ul: return true; - case 0x02ul: - return true; default: return true; } @@ -10692,8 +10662,6 @@ static bool nrf52_errata_210(void) return true; case 0x01ul: return true; - case 0x02ul: - return true; default: return true; } @@ -10804,8 +10772,6 @@ static bool nrf52_errata_211(void) return true; case 0x01ul: return true; - case 0x02ul: - return true; default: return true; } @@ -10948,8 +10914,6 @@ static bool nrf52_errata_212(void) return true; case 0x01ul: return true; - case 0x02ul: - return true; default: return true; } @@ -11426,8 +11390,6 @@ static bool nrf52_errata_218(void) return true; case 0x01ul: return true; - case 0x02ul: - return true; default: return true; } @@ -11570,8 +11532,6 @@ static bool nrf52_errata_219(void) return true; case 0x01ul: return true; - case 0x02ul: - return true; default: return true; } @@ -11716,8 +11676,6 @@ static bool nrf52_errata_223(void) return true; case 0x01ul: return true; - case 0x02ul: - return true; default: return true; } @@ -11776,8 +11734,6 @@ static bool nrf52_errata_225(void) return true; case 0x01ul: return true; - case 0x02ul: - return true; default: return true; } @@ -11880,8 +11836,6 @@ static bool nrf52_errata_228(void) return true; case 0x01ul: return true; - case 0x02ul: - return true; default: return true; } @@ -12118,8 +12072,6 @@ static bool nrf52_errata_233(void) return true; case 0x01ul: return true; - case 0x02ul: - return true; default: return true; } @@ -12221,8 +12173,6 @@ static bool nrf52_errata_236(void) case 0x00ul: return true; case 0x01ul: - return true; - case 0x02ul: return false; default: return false; @@ -12340,8 +12290,6 @@ static bool nrf52_errata_237(void) return true; case 0x01ul: return true; - case 0x02ul: - return true; default: return true; } @@ -12534,8 +12482,6 @@ static bool nrf52_errata_243(void) return true; case 0x01ul: return true; - case 0x02ul: - return true; default: return true; } @@ -12724,8 +12670,6 @@ static bool nrf52_errata_245(void) return true; case 0x01ul: return true; - case 0x02ul: - return true; default: return true; } @@ -12858,8 +12802,6 @@ static bool nrf52_errata_246(void) return true; case 0x01ul: return true; - case 0x02ul: - return true; default: return true; } @@ -12990,8 +12932,6 @@ static bool nrf52_errata_248(void) return true; case 0x01ul: return true; - case 0x02ul: - return true; default: return true; } @@ -13134,8 +13074,6 @@ static bool nrf52_configuration_249(void) case 0x00ul: return false; case 0x01ul: - return false; - case 0x02ul: return true; default: return true; @@ -13216,6 +13154,20 @@ static bool nrf52_errata_250(void) #endif #if defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833) if (var1 == 0x0D) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52820_XXAA) || defined (DEVELOP_IN_NRF52820) + if (var1 == 0x10) { switch(var2) { @@ -13225,6 +13177,48 @@ static bool nrf52_errata_250(void) return true; case 0x02ul: return true; + case 0x03ul: + return true; + default: + return true; + } + } + #endif + return false; + #endif +} + +/* ========= Errata 251 ========= */ +#if defined (NRF52820_XXAA) || defined (DEVELOP_IN_NRF52820) \ + || defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833) + #define NRF52_ERRATA_251_PRESENT 1 +#else + #define NRF52_ERRATA_251_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_251_ENABLE_WORKAROUND + #define NRF52_ERRATA_251_ENABLE_WORKAROUND NRF52_ERRATA_251_PRESENT +#endif + +static bool nrf52_errata_251(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52820_XXAA) || defined (DEVELOP_IN_NRF52820)\ + || defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833) + uint32_t var1 = *(uint32_t *)0x10000130ul; + uint32_t var2 = *(uint32_t *)0x10000134ul; + #endif + #if defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833) + if (var1 == 0x0D) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; default: return true; } @@ -13252,6 +13246,160 @@ static bool nrf52_errata_250(void) #endif } +/* ========= Errata 252 ========= */ +#if defined (NRF52810_XXAA) || defined (DEVELOP_IN_NRF52810) \ + || defined (NRF52811_XXAA) || defined (DEVELOP_IN_NRF52811) \ + || defined (NRF52820_XXAA) || defined (DEVELOP_IN_NRF52820) \ + || defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832) \ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) \ + || defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833) \ + || defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + #define NRF52_ERRATA_252_PRESENT 1 +#else + #define NRF52_ERRATA_252_PRESENT 0 +#endif + +#ifndef NRF52_ERRATA_252_ENABLE_WORKAROUND + #define NRF52_ERRATA_252_ENABLE_WORKAROUND NRF52_ERRATA_252_PRESENT +#endif + +static bool nrf52_errata_252(void) +{ + #ifndef NRF52_SERIES + return false; + #else + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + uint32_t var1; + uint32_t var2; + + if (*(uint32_t *)0x10000130ul == 0xFFFFFFFF) + { + var1 = ((*(uint32_t *)0xF0000FE0ul) & 0x000000FFul); + var2 = ((*(uint32_t *)0xF0000FE8ul) & 0x000000F0ul) >> 4; + } + else + { + var1 = *(uint32_t *)0x10000130ul; + var2 = *(uint32_t *)0x10000134ul; + } + #elif defined (NRF52810_XXAA) || defined (DEVELOP_IN_NRF52810)\ + || defined (NRF52811_XXAA) || defined (DEVELOP_IN_NRF52811)\ + || defined (NRF52820_XXAA) || defined (DEVELOP_IN_NRF52820)\ + || defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833)\ + || defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + uint32_t var1 = *(uint32_t *)0x10000130ul; + uint32_t var2 = *(uint32_t *)0x10000134ul; + #endif + #if defined (NRF52832_XXAA) || defined (DEVELOP_IN_NRF52832)\ + || defined (NRF52832_XXAB) || defined (DEVELOP_IN_NRF52832) + if (var1 == 0x06) + { + switch(var2) + { + case 0x03ul: + return true; + case 0x04ul: + return true; + case 0x05ul: + return true; + case 0x06ul: + return true; + case 0x07ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) + if (var1 == 0x08) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + case 0x02ul: + return true; + case 0x03ul: + return true; + case 0x04ul: + return true; + case 0x05ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52810_XXAA) || defined (DEVELOP_IN_NRF52810) + if (var1 == 0x0A) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + case 0x02ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52833_XXAA) || defined (DEVELOP_IN_NRF52833) + if (var1 == 0x0D) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52811_XXAA) || defined (DEVELOP_IN_NRF52811) + if (var1 == 0x0E) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + default: + return true; + } + } + #endif + #if defined (NRF52820_XXAA) || defined (DEVELOP_IN_NRF52820) + if (var1 == 0x10) + { + switch(var2) + { + case 0x00ul: + return true; + case 0x01ul: + return true; + case 0x02ul: + return false; + case 0x03ul: + return false; + default: + return false; + } + } + #endif + return false; + #endif +} + /* ========= Errata 254 ========= */ #if defined (NRF52840_XXAA) || defined (DEVELOP_IN_NRF52840) #define NRF52_CONFIGURATION_254_PRESENT 1 @@ -13326,8 +13474,6 @@ static bool nrf52_configuration_255(void) case 0x00ul: return false; case 0x01ul: - return false; - case 0x02ul: return true; default: return true; diff --git a/mdk/nrf5340_application.h b/mdk/nrf5340_application.h index 5eb14481a..f4cf51a13 100644 --- a/mdk/nrf5340_application.h +++ b/mdk/nrf5340_application.h @@ -19,10 +19,10 @@ * @file nrf5340_application.h * @brief CMSIS HeaderFile * @version 1 - * @date 19. November 2021 - * @note Generated by SVDConv V3.3.35 on Friday, 19.11.2021 12:45:05 + * @date 01. December 2021 + * @note Generated by SVDConv V3.3.35 on Wednesday, 01.12.2021 11:35:50 * from File 'nrf5340_application.svd', - * last modified on Friday, 19.11.2021 11:44:55 + * last modified on Wednesday, 01.12.2021 10:35:40 */ diff --git a/mdk/nrf5340_network.h b/mdk/nrf5340_network.h index e13c809d2..fdd1ebcfc 100644 --- a/mdk/nrf5340_network.h +++ b/mdk/nrf5340_network.h @@ -19,10 +19,10 @@ * @file nrf5340_network.h * @brief CMSIS HeaderFile * @version 1 - * @date 19. November 2021 - * @note Generated by SVDConv V3.3.35 on Friday, 19.11.2021 12:45:14 + * @date 01. December 2021 + * @note Generated by SVDConv V3.3.35 on Wednesday, 01.12.2021 11:35:59 * from File 'nrf5340_network.svd', - * last modified on Friday, 19.11.2021 11:44:55 + * last modified on Wednesday, 01.12.2021 10:35:40 */ diff --git a/mdk/nrf53_erratas.h b/mdk/nrf53_erratas.h index 27c32e471..b699d03c5 100644 --- a/mdk/nrf53_erratas.h +++ b/mdk/nrf53_erratas.h @@ -132,7 +132,11 @@ static bool nrf53_errata_117(void) __UNUSED; static bool nrf53_errata_119(void) __UNUSED; static bool nrf53_errata_121(void) __UNUSED; static bool nrf53_errata_122(void) __UNUSED; +static bool nrf53_errata_133(void) __UNUSED; static bool nrf53_errata_134(void) __UNUSED; +static bool nrf53_errata_135(void) __UNUSED; +static bool nrf53_errata_136(void) __UNUSED; +static bool nrf53_errata_137(void) __UNUSED; static bool nrf53_errata_138(void) __UNUSED; /* ========= Errata 1 ========= */ @@ -5172,6 +5176,22 @@ static bool nrf53_errata_122(void) #endif } +/* ========= Errata 133 ========= */ +#define NRF53_ERRATA_133_PRESENT 0 + +#ifndef NRF53_ERRATA_133_ENABLE_WORKAROUND + #define NRF53_ERRATA_133_ENABLE_WORKAROUND NRF53_ERRATA_133_PRESENT +#endif + +static bool nrf53_errata_133(void) +{ + #ifndef NRF53_SERIES + return false; + #else + return false; + #endif +} + /* ========= Errata 134 ========= */ #define NRF53_ERRATA_134_PRESENT 0 @@ -5188,6 +5208,98 @@ static bool nrf53_errata_134(void) #endif } +/* ========= Errata 135 ========= */ +#define NRF53_ERRATA_135_PRESENT 0 + +#ifndef NRF53_ERRATA_135_ENABLE_WORKAROUND + #define NRF53_ERRATA_135_ENABLE_WORKAROUND NRF53_ERRATA_135_PRESENT +#endif + +static bool nrf53_errata_135(void) +{ + #ifndef NRF53_SERIES + return false; + #else + return false; + #endif +} + +/* ========= Errata 136 ========= */ +#if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) || \ + defined(NRF_NETWORK) + #define NRF53_ERRATA_136_PRESENT 1 + #else + #define NRF53_ERRATA_136_PRESENT 0 + #endif +#else + #define NRF53_ERRATA_136_PRESENT 0 +#endif + +#ifndef NRF53_ERRATA_136_ENABLE_WORKAROUND + #define NRF53_ERRATA_136_ENABLE_WORKAROUND NRF53_ERRATA_136_PRESENT +#endif + +static bool nrf53_errata_136(void) +{ + #ifndef NRF53_SERIES + return false; + #else + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined(NRF_APPLICATION) + #if defined(NRF_TRUSTZONE_NONSECURE) + uint32_t var1 = *((volatile uint32_t *)((uint32_t)NRF_FICR_NS + 0x00000130ul)); + uint32_t var2 = *((volatile uint32_t *)((uint32_t)NRF_FICR_NS + 0x00000134ul)); + #else + uint32_t var1 = *((volatile uint32_t *)((uint32_t)NRF_FICR_S + 0x00000130ul)); + uint32_t var2 = *((volatile uint32_t *)((uint32_t)NRF_FICR_S + 0x00000134ul)); + #endif + #elif defined(NRF_NETWORK) + uint32_t var1 = *(uint32_t *)0x01FF0130ul; + uint32_t var2 = *(uint32_t *)0x01FF0134ul; + #endif + #endif + #if defined (NRF5340_XXAA) || defined (DEVELOP_IN_NRF5340) + #if defined (NRF_APPLICATION)\ + || defined (NRF_NETWORK) + if (var1 == 0x07) + { + switch(var2) + { + case 0x02ul: + return false; + case 0x03ul: + return false; + case 0x04ul: + return true; + case 0x05ul: + return true; + default: + return true; + } + } + #endif + #endif + return false; + #endif +} + +/* ========= Errata 137 ========= */ +#define NRF53_ERRATA_137_PRESENT 0 + +#ifndef NRF53_ERRATA_137_ENABLE_WORKAROUND + #define NRF53_ERRATA_137_ENABLE_WORKAROUND NRF53_ERRATA_137_PRESENT +#endif + +static bool nrf53_errata_137(void) +{ + #ifndef NRF53_SERIES + return false; + #else + return false; + #endif +} + /* ========= Errata 138 ========= */ #define NRF53_ERRATA_138_PRESENT 0 diff --git a/mdk/nrf9160.h b/mdk/nrf9160.h index 28061efdf..0b55b09c2 100644 --- a/mdk/nrf9160.h +++ b/mdk/nrf9160.h @@ -32,10 +32,10 @@ * @file nrf9160.h * @brief CMSIS HeaderFile * @version 1 - * @date 19. November 2021 - * @note Generated by SVDConv V3.3.35 on Friday, 19.11.2021 12:45:15 + * @date 01. December 2021 + * @note Generated by SVDConv V3.3.35 on Wednesday, 01.12.2021 11:36:00 * from File 'nrf9160.svd', - * last modified on Friday, 19.11.2021 11:44:55 + * last modified on Wednesday, 01.12.2021 10:35:40 */