-
Notifications
You must be signed in to change notification settings - Fork 0
/
mimxrt_sdram.c
288 lines (262 loc) · 13.3 KB
/
mimxrt_sdram.c
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
/*
* This file is part of the MicroPython project, http://micropython.org/
*
* The MIT License (MIT)
*
* Copyright (c) 2021 Philipp Ebensberger
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
#if MICROPY_HW_SDRAM_AVAIL
#include "modmachine.h"
#include "fsl_semc.h"
#include "fsl_iomuxc.h"
#include "fsl_clock.h"
// Linker symbols
extern uint8_t __sdram_start;
#if defined(MIMXRT117x_SERIES)
// Pull Up, High drive strength
#define SDRAM_PIN_CONFIG (0x07UL)
#else
// Pull up 22K, high slew rate
#define SDRAM_PIN_CONFIG (0xE1UL)
#endif
#ifndef MICROPY_HW_SDRAM_TIMING_TRC
#if defined(MIMXRT117x_SERIES)
#define MICROPY_HW_SDRAM_TIMING_TRC (60)
#define MICROPY_HW_SDRAM_TIMING_TRP (15)
#define MICROPY_HW_SDRAM_TIMING_TRCD (15)
#define MICROPY_HW_SDRAM_TIMING_TWR (2)
#define MICROPY_HW_SDRAM_TIMING_TRRD (2)
#define MICROPY_HW_SDRAM_TIMING_TXSR (70)
#define MICROPY_HW_SDRAM_TIMING_TRAS (42)
#define MICROPY_HW_SDRAM_TIMING_TREF (64 * 1000000 / 8192) // 64ms/8192
#define MICROPY_HW_SDRAM_CAS_LATENCY (kSEMC_LatencyThree)
#define MICROPY_HW_SDRAM_MEM_BUS_WIDTH (kSEMC_PortSize32Bit)
#define MICROPY_HW_SDRAM_COLUMN_BITS_NUM (kSEMC_SdramColunm_9bit)
#define MICROPY_HW_SDRAM_BURST_LENGTH (kSEMC_Sdram_BurstLen8)
#define MICROPY_HW_SDRAM_RBURST_LENGTH (1)
#define MICROPY_HW_SDRAM_DELAY_CHAIN (2)
#else
#define MICROPY_HW_SDRAM_TIMING_TRC (60)
#define MICROPY_HW_SDRAM_TIMING_TRP (18)
#define MICROPY_HW_SDRAM_TIMING_TRCD (18)
#define MICROPY_HW_SDRAM_TIMING_TWR (12)
#define MICROPY_HW_SDRAM_TIMING_TRRD (60)
#define MICROPY_HW_SDRAM_TIMING_TXSR (67)
#define MICROPY_HW_SDRAM_TIMING_TRAS (42)
#define MICROPY_HW_SDRAM_TIMING_TREF (64 * 1000000 / 8192) // 64ms/8192
#define MICROPY_HW_SDRAM_CAS_LATENCY (kSEMC_LatencyThree)
#define MICROPY_HW_SDRAM_MEM_BUS_WIDTH (kSEMC_PortSize16Bit)
#define MICROPY_HW_SDRAM_COLUMN_BITS_NUM (kSEMC_SdramColunm_9bit)
#define MICROPY_HW_SDRAM_BURST_LENGTH (kSEMC_Sdram_BurstLen1)
#define MICROPY_HW_SDRAM_RBURST_LENGTH (1)
#endif
#endif
void mimxrt_sdram_init(void) {
// Set Clocks
#if defined(MIMXRT117x_SERIES)
CLOCK_InitPfd(kCLOCK_PllSys2, kCLOCK_Pfd1, 29);
clock_root_config_t rootCfg = { 0 };
rootCfg.mux = kCLOCK_SEMC_ClockRoot_MuxSysPll2Pfd1;
rootCfg.div = 2;
CLOCK_SetRootClock(kCLOCK_Root_Semc, &rootCfg);
#else
CLOCK_InitSysPfd(kCLOCK_Pfd2, 29); // '29' PLL2 PFD2 frequency = 528MHz * 18 / 29 = 327.72MHz (with 528MHz = PLL2 frequency)
CLOCK_SetMux(kCLOCK_SemcAltMux, 0); // '0' PLL2 PFD2 will be selected as alternative clock for SEMC root clock
CLOCK_SetMux(kCLOCK_SemcMux, 1); // '1' SEMC alternative clock will be used as SEMC clock root
CLOCK_SetDiv(kCLOCK_SemcDiv, 1); // '1' divide by 2 -> SEMC clock = 163.86 MHz
#endif
// Set Pins
// Data Pins 0..15
IOMUXC_SetPinMux(MIMXRT_IOMUXC_SEMC_DATA00, 0UL);
IOMUXC_SetPinConfig(MIMXRT_IOMUXC_SEMC_DATA00, SDRAM_PIN_CONFIG);
IOMUXC_SetPinMux(MIMXRT_IOMUXC_SEMC_DATA01, 0UL);
IOMUXC_SetPinConfig(MIMXRT_IOMUXC_SEMC_DATA01, SDRAM_PIN_CONFIG);
IOMUXC_SetPinMux(MIMXRT_IOMUXC_SEMC_DATA02, 0UL);
IOMUXC_SetPinConfig(MIMXRT_IOMUXC_SEMC_DATA02, SDRAM_PIN_CONFIG);
IOMUXC_SetPinMux(MIMXRT_IOMUXC_SEMC_DATA03, 0UL);
IOMUXC_SetPinConfig(MIMXRT_IOMUXC_SEMC_DATA03, SDRAM_PIN_CONFIG);
IOMUXC_SetPinMux(MIMXRT_IOMUXC_SEMC_DATA04, 0UL);
IOMUXC_SetPinConfig(MIMXRT_IOMUXC_SEMC_DATA04, SDRAM_PIN_CONFIG);
IOMUXC_SetPinMux(MIMXRT_IOMUXC_SEMC_DATA05, 0UL);
IOMUXC_SetPinConfig(MIMXRT_IOMUXC_SEMC_DATA05, SDRAM_PIN_CONFIG);
IOMUXC_SetPinMux(MIMXRT_IOMUXC_SEMC_DATA06, 0UL);
IOMUXC_SetPinConfig(MIMXRT_IOMUXC_SEMC_DATA06, SDRAM_PIN_CONFIG);
IOMUXC_SetPinMux(MIMXRT_IOMUXC_SEMC_DATA07, 0UL);
IOMUXC_SetPinConfig(MIMXRT_IOMUXC_SEMC_DATA07, SDRAM_PIN_CONFIG);
IOMUXC_SetPinMux(MIMXRT_IOMUXC_SEMC_DATA08, 0UL);
IOMUXC_SetPinConfig(MIMXRT_IOMUXC_SEMC_DATA08, SDRAM_PIN_CONFIG);
IOMUXC_SetPinMux(MIMXRT_IOMUXC_SEMC_DATA09, 0UL);
IOMUXC_SetPinConfig(MIMXRT_IOMUXC_SEMC_DATA09, SDRAM_PIN_CONFIG);
IOMUXC_SetPinMux(MIMXRT_IOMUXC_SEMC_DATA10, 0UL);
IOMUXC_SetPinConfig(MIMXRT_IOMUXC_SEMC_DATA10, SDRAM_PIN_CONFIG);
IOMUXC_SetPinMux(MIMXRT_IOMUXC_SEMC_DATA11, 0UL);
IOMUXC_SetPinConfig(MIMXRT_IOMUXC_SEMC_DATA11, SDRAM_PIN_CONFIG);
IOMUXC_SetPinMux(MIMXRT_IOMUXC_SEMC_DATA12, 0UL);
IOMUXC_SetPinConfig(MIMXRT_IOMUXC_SEMC_DATA12, SDRAM_PIN_CONFIG);
IOMUXC_SetPinMux(MIMXRT_IOMUXC_SEMC_DATA13, 0UL);
IOMUXC_SetPinConfig(MIMXRT_IOMUXC_SEMC_DATA13, SDRAM_PIN_CONFIG);
IOMUXC_SetPinMux(MIMXRT_IOMUXC_SEMC_DATA14, 0UL);
IOMUXC_SetPinConfig(MIMXRT_IOMUXC_SEMC_DATA14, SDRAM_PIN_CONFIG);
IOMUXC_SetPinMux(MIMXRT_IOMUXC_SEMC_DATA15, 0UL);
IOMUXC_SetPinConfig(MIMXRT_IOMUXC_SEMC_DATA15, SDRAM_PIN_CONFIG);
// Address Pins
IOMUXC_SetPinMux(MIMXRT_IOMUXC_SEMC_ADDR00, 0UL);
IOMUXC_SetPinConfig(MIMXRT_IOMUXC_SEMC_ADDR00, SDRAM_PIN_CONFIG);
IOMUXC_SetPinMux(MIMXRT_IOMUXC_SEMC_ADDR01, 0UL);
IOMUXC_SetPinConfig(MIMXRT_IOMUXC_SEMC_ADDR01, SDRAM_PIN_CONFIG);
IOMUXC_SetPinMux(MIMXRT_IOMUXC_SEMC_ADDR02, 0UL);
IOMUXC_SetPinConfig(MIMXRT_IOMUXC_SEMC_ADDR02, SDRAM_PIN_CONFIG);
IOMUXC_SetPinMux(MIMXRT_IOMUXC_SEMC_ADDR03, 0UL);
IOMUXC_SetPinConfig(MIMXRT_IOMUXC_SEMC_ADDR03, SDRAM_PIN_CONFIG);
IOMUXC_SetPinMux(MIMXRT_IOMUXC_SEMC_ADDR04, 0UL);
IOMUXC_SetPinConfig(MIMXRT_IOMUXC_SEMC_ADDR04, SDRAM_PIN_CONFIG);
IOMUXC_SetPinMux(MIMXRT_IOMUXC_SEMC_ADDR05, 0UL);
IOMUXC_SetPinConfig(MIMXRT_IOMUXC_SEMC_ADDR05, SDRAM_PIN_CONFIG);
IOMUXC_SetPinMux(MIMXRT_IOMUXC_SEMC_ADDR06, 0UL);
IOMUXC_SetPinConfig(MIMXRT_IOMUXC_SEMC_ADDR06, SDRAM_PIN_CONFIG);
IOMUXC_SetPinMux(MIMXRT_IOMUXC_SEMC_ADDR07, 0UL);
IOMUXC_SetPinConfig(MIMXRT_IOMUXC_SEMC_ADDR07, SDRAM_PIN_CONFIG);
IOMUXC_SetPinMux(MIMXRT_IOMUXC_SEMC_ADDR08, 0UL);
IOMUXC_SetPinConfig(MIMXRT_IOMUXC_SEMC_ADDR08, SDRAM_PIN_CONFIG);
IOMUXC_SetPinMux(MIMXRT_IOMUXC_SEMC_ADDR09, 0UL);
IOMUXC_SetPinConfig(MIMXRT_IOMUXC_SEMC_ADDR09, SDRAM_PIN_CONFIG);
IOMUXC_SetPinMux(MIMXRT_IOMUXC_SEMC_ADDR10, 0UL);
IOMUXC_SetPinConfig(MIMXRT_IOMUXC_SEMC_ADDR10, SDRAM_PIN_CONFIG);
IOMUXC_SetPinMux(MIMXRT_IOMUXC_SEMC_ADDR11, 0UL);
IOMUXC_SetPinConfig(MIMXRT_IOMUXC_SEMC_ADDR11, SDRAM_PIN_CONFIG);
IOMUXC_SetPinMux(MIMXRT_IOMUXC_SEMC_ADDR12, 0UL);
IOMUXC_SetPinConfig(MIMXRT_IOMUXC_SEMC_ADDR12, SDRAM_PIN_CONFIG);
IOMUXC_SetPinMux(MIMXRT_IOMUXC_SEMC_DM00, 0UL);
IOMUXC_SetPinConfig(MIMXRT_IOMUXC_SEMC_DM00, SDRAM_PIN_CONFIG);
IOMUXC_SetPinMux(MIMXRT_IOMUXC_SEMC_BA0, 0UL);
IOMUXC_SetPinConfig(MIMXRT_IOMUXC_SEMC_BA0, SDRAM_PIN_CONFIG);
IOMUXC_SetPinMux(MIMXRT_IOMUXC_SEMC_BA1, 0UL);
IOMUXC_SetPinConfig(MIMXRT_IOMUXC_SEMC_BA1, SDRAM_PIN_CONFIG);
IOMUXC_SetPinMux(MIMXRT_IOMUXC_SEMC_CAS, 0UL);
IOMUXC_SetPinConfig(MIMXRT_IOMUXC_SEMC_CAS, SDRAM_PIN_CONFIG);
IOMUXC_SetPinMux(MIMXRT_IOMUXC_SEMC_RAS, 0UL);
IOMUXC_SetPinConfig(MIMXRT_IOMUXC_SEMC_RAS, SDRAM_PIN_CONFIG);
IOMUXC_SetPinMux(MIMXRT_IOMUXC_SEMC_CLK, 0UL);
IOMUXC_SetPinConfig(MIMXRT_IOMUXC_SEMC_CLK, SDRAM_PIN_CONFIG);
IOMUXC_SetPinMux(MIMXRT_IOMUXC_SEMC_CKE, 0UL);
IOMUXC_SetPinConfig(MIMXRT_IOMUXC_SEMC_CKE, SDRAM_PIN_CONFIG);
IOMUXC_SetPinMux(MIMXRT_IOMUXC_SEMC_WE, 0UL);
IOMUXC_SetPinConfig(MIMXRT_IOMUXC_SEMC_WE, SDRAM_PIN_CONFIG);
IOMUXC_SetPinMux(MIMXRT_IOMUXC_SEMC_DM01, 0UL);
IOMUXC_SetPinConfig(MIMXRT_IOMUXC_SEMC_DM01, SDRAM_PIN_CONFIG);
IOMUXC_SetPinMux(MIMXRT_IOMUXC_SEMC_DQS, 1UL);
IOMUXC_SetPinConfig(MIMXRT_IOMUXC_SEMC_DQS, SDRAM_PIN_CONFIG);
#if defined(MIMXRT_IOMUXC_SEMC_DATA16)
// Data Pins 16..31
IOMUXC_SetPinMux(MIMXRT_IOMUXC_SEMC_DATA16, 0UL);
IOMUXC_SetPinConfig(MIMXRT_IOMUXC_SEMC_DATA16, SDRAM_PIN_CONFIG);
IOMUXC_SetPinMux(MIMXRT_IOMUXC_SEMC_DATA17, 0UL);
IOMUXC_SetPinConfig(MIMXRT_IOMUXC_SEMC_DATA17, SDRAM_PIN_CONFIG);
IOMUXC_SetPinMux(MIMXRT_IOMUXC_SEMC_DATA18, 0UL);
IOMUXC_SetPinConfig(MIMXRT_IOMUXC_SEMC_DATA18, SDRAM_PIN_CONFIG);
IOMUXC_SetPinMux(MIMXRT_IOMUXC_SEMC_DATA19, 0UL);
IOMUXC_SetPinConfig(MIMXRT_IOMUXC_SEMC_DATA19, SDRAM_PIN_CONFIG);
IOMUXC_SetPinMux(MIMXRT_IOMUXC_SEMC_DATA20, 0UL);
IOMUXC_SetPinConfig(MIMXRT_IOMUXC_SEMC_DATA20, SDRAM_PIN_CONFIG);
IOMUXC_SetPinMux(MIMXRT_IOMUXC_SEMC_DATA21, 0UL);
IOMUXC_SetPinConfig(MIMXRT_IOMUXC_SEMC_DATA21, SDRAM_PIN_CONFIG);
IOMUXC_SetPinMux(MIMXRT_IOMUXC_SEMC_DATA22, 0UL);
IOMUXC_SetPinConfig(MIMXRT_IOMUXC_SEMC_DATA22, SDRAM_PIN_CONFIG);
IOMUXC_SetPinMux(MIMXRT_IOMUXC_SEMC_DATA23, 0UL);
IOMUXC_SetPinConfig(MIMXRT_IOMUXC_SEMC_DATA23, SDRAM_PIN_CONFIG);
IOMUXC_SetPinMux(MIMXRT_IOMUXC_SEMC_DATA24, 0UL);
IOMUXC_SetPinConfig(MIMXRT_IOMUXC_SEMC_DATA24, SDRAM_PIN_CONFIG);
IOMUXC_SetPinMux(MIMXRT_IOMUXC_SEMC_DATA25, 0UL);
IOMUXC_SetPinConfig(MIMXRT_IOMUXC_SEMC_DATA25, SDRAM_PIN_CONFIG);
IOMUXC_SetPinMux(MIMXRT_IOMUXC_SEMC_DATA26, 0UL);
IOMUXC_SetPinConfig(MIMXRT_IOMUXC_SEMC_DATA26, SDRAM_PIN_CONFIG);
IOMUXC_SetPinMux(MIMXRT_IOMUXC_SEMC_DATA27, 0UL);
IOMUXC_SetPinConfig(MIMXRT_IOMUXC_SEMC_DATA27, SDRAM_PIN_CONFIG);
IOMUXC_SetPinMux(MIMXRT_IOMUXC_SEMC_DATA28, 0UL);
IOMUXC_SetPinConfig(MIMXRT_IOMUXC_SEMC_DATA28, SDRAM_PIN_CONFIG);
IOMUXC_SetPinMux(MIMXRT_IOMUXC_SEMC_DATA29, 0UL);
IOMUXC_SetPinConfig(MIMXRT_IOMUXC_SEMC_DATA29, SDRAM_PIN_CONFIG);
IOMUXC_SetPinMux(MIMXRT_IOMUXC_SEMC_DATA30, 0UL);
IOMUXC_SetPinConfig(MIMXRT_IOMUXC_SEMC_DATA30, SDRAM_PIN_CONFIG);
IOMUXC_SetPinMux(MIMXRT_IOMUXC_SEMC_DATA31, 0UL);
IOMUXC_SetPinConfig(MIMXRT_IOMUXC_SEMC_DATA31, SDRAM_PIN_CONFIG);
IOMUXC_SetPinMux(MIMXRT_IOMUXC_SEMC_DM02, 0UL);
IOMUXC_SetPinConfig(MIMXRT_IOMUXC_SEMC_DM02, SDRAM_PIN_CONFIG);
IOMUXC_SetPinMux(MIMXRT_IOMUXC_SEMC_DM03, 0UL);
IOMUXC_SetPinConfig(MIMXRT_IOMUXC_SEMC_DM03, SDRAM_PIN_CONFIG);
#endif
// Chip Select Pins
#ifndef MIMXRT_IOMUXC_SEMC_CS0
#error No SEMC CS0 defined!
#endif
IOMUXC_SetPinMux(MIMXRT_IOMUXC_SEMC_CS0, 0UL);
IOMUXC_SetPinConfig(MIMXRT_IOMUXC_SEMC_CS0, SDRAM_PIN_CONFIG);
#ifdef MIMXRT_IOMUXC_SEMC_CS1
IOMUXC_SetPinMux(MIMXRT_IOMUXC_SEMC_CS1, 0UL);
IOMUXC_SetPinConfig(MIMXRT_IOMUXC_SEMC_CS1, SDRAM_PIN_CONFIG);
#endif
#ifdef MIMXRT_IOMUXC_SEMC_CS2
IOMUXC_SetPinMux(MIMXRT_IOMUXC_SEMC_CS2, 0UL);
IOMUXC_SetPinConfig(MIMXRT_IOMUXC_SEMC_CS2, SDRAM_PIN_CONFIG);
#endif
#ifdef MIMXRT_IOMUXC_SEMC_CS3
IOMUXC_SetPinMux(MIMXRT_IOMUXC_SEMC_CS3, 0UL);
IOMUXC_SetPinConfig(MIMXRT_IOMUXC_SEMC_CS3, SDRAM_PIN_CONFIG);
#endif
// Configure SEMC
semc_config_t semc_cfg;
SEMC_GetDefaultConfig(&semc_cfg);
semc_cfg.dqsMode = kSEMC_Loopbackdqspad; // For more accurate timing.
SEMC_Init(SEMC, &semc_cfg);
#if defined(MIMXRT117x_SERIES)
uint32_t clock_freq = CLOCK_GetRootClockFreq(kCLOCK_Root_Semc);
#else
uint32_t clock_freq = CLOCK_GetFreq(kCLOCK_SemcClk);
#endif
semc_sdram_config_t sdram_cfg = {
.csxPinMux = kSEMC_MUXCSX0,
.address = ((uint32_t)&__sdram_start),
.memsize_kbytes = (MICROPY_HW_SDRAM_SIZE >> 10), // Right shift by 10 == division by 1024
.portSize = MICROPY_HW_SDRAM_MEM_BUS_WIDTH,
.burstLen = MICROPY_HW_SDRAM_BURST_LENGTH,
.columnAddrBitNum = MICROPY_HW_SDRAM_COLUMN_BITS_NUM,
.casLatency = MICROPY_HW_SDRAM_CAS_LATENCY,
.tPrecharge2Act_Ns = MICROPY_HW_SDRAM_TIMING_TRP,
.tAct2ReadWrite_Ns = MICROPY_HW_SDRAM_TIMING_TRCD,
.tRefreshRecovery_Ns = MICROPY_HW_SDRAM_TIMING_TXSR,
.tSelfRefRecovery_Ns = MICROPY_HW_SDRAM_TIMING_TXSR,
.tWriteRecovery_Ns = MICROPY_HW_SDRAM_TIMING_TWR,
.tCkeOff_Ns = MICROPY_HW_SDRAM_TIMING_TRAS,
.tAct2Prechage_Ns = MICROPY_HW_SDRAM_TIMING_TRAS,
.tRefresh2Refresh_Ns = MICROPY_HW_SDRAM_TIMING_TRC,
.tAct2Act_Ns = MICROPY_HW_SDRAM_TIMING_TRRD,
.tIdleTimeout_Ns = 0UL,
.refreshPeriod_nsPerRow = MICROPY_HW_SDRAM_TIMING_TREF,
.refreshUrgThreshold = MICROPY_HW_SDRAM_TIMING_TREF,
.refreshBurstLen = MICROPY_HW_SDRAM_RBURST_LENGTH,
#ifdef MICROPY_HW_SDRAM_DELAY_CHAIN
.delayChain = MICROPY_HW_SDRAM_DELAY_CHAIN,
#endif
.tPrescalePeriod_Ns = 160 * (1000000000 / clock_freq),
};
(status_t)SEMC_ConfigureSDRAM(SEMC, kSEMC_SDRAM_CS0, &sdram_cfg, clock_freq);
}
#endif