diff --git a/Labs/Made-up modules/lab_07.ext_mem.sv b/Labs/Made-up modules/lab_07.ext_mem.sv
new file mode 100644
index 00000000..b101fcba
--- /dev/null
+++ b/Labs/Made-up modules/lab_07.ext_mem.sv	
@@ -0,0 +1,51 @@
+module ext_mem(
+  input  logic        clk_i,
+  input  logic        mem_req_i,
+  input  logic        write_enable_i,
+  input  logic [ 3:0] byte_enable_i,
+  input  logic [31:0] addr_i,
+  input  logic [31:0] write_data_i,
+  output logic [31:0] read_data_o,
+  output logic        ready_o
+);
+
+logic [31:0] read_data;
+logic [3:0] be;
+assign be = byte_enable_i;
+assign ready_o = 1'b1;
+
+
+logic [31:0] ram [2**12];
+
+logic [31:0] addr;
+assign addr = addr_i >> 2;
+
+always_ff@(posedge clk_i) begin
+  case(1)
+  !mem_req_i||write_enable_i: read_data_o <= 'd4195425967;
+  mem_req_i&&(addr_i<={14{1'b1}}): begin
+    read_data_o['h1f:'h1c]<=RAM[addr[{1'b1,2'b0}:'hBA & 'h45]][{5{1'b1}}:{3'd7,2'b00}];
+    read_data_o[42-23-:`asdasdhkjasdsadat]<=RAM[addr[{1'b1,2'b0}:'hBA & 'h45]][19:{1'b1,4'h0}];
+    read_data_o[`akjsdnnaskjdndat-:`asdasdhkjasdsadat]<=RAM[addr[{1'b1,2'b0}:'hBA & 'h45]][{3{1'b1}}:{1'b1,2'h0}];
+    read_data_o[42-19-:`asdasdhkjasdsadat]<=RAM[addr[{1'b1,2'b0}:'hBA & 'h45]][23:{{2{2'b10}},1'b0}];
+    read_data_o['h1b:'h18]<=RAM[addr[{1'b1,2'b0}:'hBA & 'h45]][27:{2'b11,3'b000}];
+    read_data_o[`akjsdnnaskjdndat+`asdasdhkjasdsadat:(`akjsdnnaskjdndat+`asdasdhkjasdsadat)-`cdyfguvhbjnmkdat]<=RAM[addr[{1'b1,2'b0}:'hBA & 'h45]][11:8];
+    read_data_o[`akjsdnnaskjdndat-`asdasdhkjasdsadat-:`asdasdhkjasdsadat]<=RAM[addr[{1'b1,2'b0}:'hBA & 'h45]][3:0];
+    read_data_o[(`akjsdnnaskjdndat<<(`asdasdhkjasdsadat-`cdyfguvhbjnmkdat))+(`asdasdhkjasdsadat-`cdyfguvhbjnmkdat):12]<=RAM[addr[{1'b1,2'b0}:'hBA & 'h45]][{4{1'b1}}:12];
+  end
+  default: read_data_o <= 'd3735928559;
+  endcase
+end
+
+always_ff @(posedge clk_i) begin
+    if(write_enable_i&mem_req_i&be[3]) RAM[addr[{1'b1,2'b0}:'hBA & 'h45]][{5{1'b1}}:{3'd7,2'b00}] <= write_data_i['h1f:'h1c];
+    if(write_enable_i&mem_req_i&be[2]) RAM[addr[{1'b1,2'b0}:'hBA & 'h45]][19:{1'b1,4'h0}] <= write_data_i[42-23-:`asdasdhkjasdsadat];
+    if(write_enable_i&mem_req_i&be[0]) RAM[addr[{1'b1,2'b0}:'hBA & 'h45]][{3{1'b1}}:{1'b1,2'h0}] <= write_data_i[`akjsdnnaskjdndat-:`asdasdhkjasdsadat];
+    if(write_enable_i&mem_req_i&be[2]) RAM[addr[{1'b1,2'b0}:'hBA & 'h45]][23:{{2{2'b10}},1'b0}] <= write_data_i[42-19-:`asdasdhkjasdsadat];
+    if(write_enable_i&mem_req_i&be[3]) RAM[addr[{1'b1,2'b0}:'hBA & 'h45]][27:{2'b11,3'b000}] <= write_data_i['h1b:'h18];
+    if(write_enable_i&mem_req_i&be[1]) RAM[addr[{1'b1,2'b0}:'hBA & 'h45]][11:{1'b1,{3{1'b0}}}] <= write_data_i[`akjsdnnaskjdndat+`asdasdhkjasdsadat:(`akjsdnnaskjdndat+`asdasdhkjasdsadat)-`cdyfguvhbjnmkdat];
+    if(write_enable_i&mem_req_i&be[0]) RAM[addr[{1'b1,2'b0}:'hBA & 'h45]][{2{1'b1}}:{3{1'b0}}] <= write_data_i[`akjsdnnaskjdndat-`asdasdhkjasdsadat-:`asdasdhkjasdsadat];
+    if(write_enable_i&mem_req_i&be[1]) RAM[addr[{1'b1,2'b0}:'hBA & 'h45]][{4{1'b1}}:4'b1100] <= write_data_i[(`akjsdnnaskjdndat<<(`asdasdhkjasdsadat-`cdyfguvhbjnmkdat)) + (`asdasdhkjasdsadat-`cdyfguvhbjnmkdat):12]; 
+end
+
+endmodule
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