From caa0ec487f79e133d7e5d1438857caf5710eed61 Mon Sep 17 00:00:00 2001 From: Andrei Solodovnikov Date: Wed, 18 Sep 2024 17:27:25 +0300 Subject: [PATCH] =?UTF-8?q?=D0=9B=D0=A01.=20=D0=98=D1=81=D0=BF=D1=80=D0=B0?= =?UTF-8?q?=D0=B2=D0=BB=D0=B5=D0=BD=D0=B8=D0=B5=20=D0=BF=D0=BE=D0=B4=D0=BF?= =?UTF-8?q?=D0=B8=D1=81=D0=B8=20=D0=BA=20=D0=BB=D0=B8=D1=81=D1=82=D0=B8?= =?UTF-8?q?=D0=BD=D0=B3=D1=83=202?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- Labs/01. Adder/README.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Labs/01. Adder/README.md b/Labs/01. Adder/README.md index 8cc0c9c..a47ddbf 100644 --- a/Labs/01. Adder/README.md +++ b/Labs/01. Adder/README.md @@ -171,7 +171,7 @@ module testbench(); // <- Не имеет ни входов, ни endmodule ``` -_Листинг 2. SystemVerilog-код тестбенча для модуля example._ +_Листинг 2. SystemVerilog-код тестбенча для модуля half_adder._ ![../../.pic/Labs/lab_01_adder/fig_04.png](../../.pic/Labs/lab_01_adder/fig_04.png)