From e9665941f9fb3730ad400a73fae688c18c346dd3 Mon Sep 17 00:00:00 2001
From: Andrei Solodovnikov <voultboy@yandex.ru>
Date: Mon, 9 Sep 2024 12:01:27 +0300
Subject: [PATCH 01/14] =?UTF-8?q?=D0=9E=D0=B1=D0=BD=D0=BE=D0=B2=D0=BB?=
 =?UTF-8?q?=D0=B5=D0=BD=D0=B8=D0=B5=20=D1=82=D0=B5=D1=81=D1=82=D0=B1=D0=B5?=
 =?UTF-8?q?=D0=BD=D1=87=D0=B5=D0=B9?=
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

---
 Labs/01. Adder/lab_01.tb_fulladder.sv         |  49 ++--
 Labs/01. Adder/lab_01.tb_fulladder32.sv       | 119 ++++----
 Labs/01. Adder/lab_01.tb_fulladder4.sv        |  49 ++--
 .../lab_02.tb_alu.sv                          |  28 +-
 .../lab_03.tb_register_file.sv                | 265 +++++++++---------
 .../lab_04.tb_cybercobra.sv                   |   3 +
 Labs/05. Main decoder/lab_05.tb_decoder.sv    |  13 +-
 Labs/06. Main memory/lab_06.tb_data_mem.sv    |  13 +-
 .../lab_07.tb_processor_system.sv             |  21 +-
 Labs/08. Load-store unit/lab_08.tb_lsu.sv     |   3 +
 Labs/Made-up modules/lab_02.alu.sv            |  30 +-
 Labs/Made-up modules/lab_03.data_mem.sv       |  54 ----
 Labs/Made-up modules/lab_03.instr_mem.sv      |   4 +-
 Labs/Made-up modules/lab_03.register_file.sv  |   2 +-
 14 files changed, 306 insertions(+), 347 deletions(-)
 delete mode 100644 Labs/Made-up modules/lab_03.data_mem.sv

diff --git a/Labs/01. Adder/lab_01.tb_fulladder.sv b/Labs/01. Adder/lab_01.tb_fulladder.sv
index a4ec5571..af97903f 100644
--- a/Labs/01. Adder/lab_01.tb_fulladder.sv	
+++ b/Labs/01. Adder/lab_01.tb_fulladder.sv	
@@ -11,33 +11,36 @@ See https://github.com/MPSU/APS/blob/master/LICENSE file for licensing details.
 
 module lab_01_tb_fulladder();
 
-    logic tb_a_i;
-    logic tb_b_i;
-    logic tb_carry_i;
-    logic tb_carry_o;
-    logic tb_sum_o;
-    logic [2:0] test_case;
+  logic tb_a_i;
+  logic tb_b_i;
+  logic tb_carry_i;
+  logic tb_carry_o;
+  logic tb_sum_o;
+  logic [2:0] test_case;
 
-    fulladder DUT (
-        .a_i(tb_a_i),
-        .b_i(tb_b_i),
-        .sum_o(tb_sum_o),
-        .carry_i(tb_carry_i),
-        .carry_o(tb_carry_o)
-    );
+  fulladder DUT (
+    .a_i(tb_a_i),
+    .b_i(tb_b_i),
+    .sum_o(tb_sum_o),
+    .carry_i(tb_carry_i),
+    .carry_o(tb_carry_o)
+  );
 
-    assign {tb_a_i, tb_b_i, tb_carry_i} = test_case;
+  assign {tb_a_i, tb_b_i, tb_carry_i} = test_case;
 
-    initial begin
-      $display("\nTest has been started\n");
+  initial begin
+    $display("\nTest has been started\n");
+    #5ns;
+    test_case = 3'd0;
+    repeat(8) begin
       #5ns;
-      test_case = 3'd0;
-      repeat(8) begin
-        #5ns;
-        test_case++;
-      end
-      $display("\nTest has been finished. Check results at waveform window.\n");
-      $finish();
+      test_case++;
     end
+    $display("\nTest has been finished. Check results at waveform window.\n");
+    $finish();
+    #5;
+    $display("You're trying to run simulation that has finished. Aborting simulation.")
+    $fatal();
+  end
 
 endmodule
diff --git a/Labs/01. Adder/lab_01.tb_fulladder32.sv b/Labs/01. Adder/lab_01.tb_fulladder32.sv
index c1e77681..09606376 100644
--- a/Labs/01. Adder/lab_01.tb_fulladder32.sv	
+++ b/Labs/01. Adder/lab_01.tb_fulladder32.sv	
@@ -11,72 +11,75 @@ See https://github.com/MPSU/APS/blob/master/LICENSE file for licensing details.
 
 module lab_01_tb_fulladder32();
 
-    logic [31:0] tb_a_i;
-    logic [31:0] tb_b_i;
-    logic        tb_carry_i;
-    logic        tb_carry_o;
-    logic [31:0] tb_sum_o;
+  logic [31:0] tb_a_i;
+  logic [31:0] tb_b_i;
+  logic        tb_carry_i;
+  logic        tb_carry_o;
+  logic [31:0] tb_sum_o;
 
-    logic clk = 0;
-    always #5ns clk = ~clk;
+  logic clk = 0;
+  always #5ns clk = ~clk;
 
-    int err_cnt = 0;
+  int err_cnt = 0;
 
-    fulladder32 DUT (
-        .a_i(tb_a_i),
-        .b_i(tb_b_i),
-        .sum_o(tb_sum_o),
-        .carry_i(tb_carry_i),
-        .carry_o(tb_carry_o)
-    );
+  fulladder32 DUT (
+    .a_i(tb_a_i),
+    .b_i(tb_b_i),
+    .sum_o(tb_sum_o),
+    .carry_i(tb_carry_i),
+    .carry_o(tb_carry_o)
+  );
 
-    initial begin
-      $display("Test has been started");
-      sequential_add_test();
-      random_test();
-      $display("\nTest has been finished\nNumber of errors: %d\n", err_cnt);
-      $finish();
-    end
-
-    task sequential_add_test();
-      @(posedge clk);
-      tb_a_i = 0;
-      tb_b_i = 0;
-      tb_carry_i = 0;
-      @(posedge clk);
-      for(int i = 0; i < 16; i++) begin
-        tb_a_i += 256;
-        for(int j = 0; j < 16; j++) begin
-          tb_b_i += 256;
-          tb_carry_i = ~tb_carry_i;
-          @(posedge clk);
-        end
-      end
-    endtask
+  initial begin
+    $display("Test has been started");
+    sequential_add_test();
+    random_test();
+    $display("\nTest has been finished\nNumber of errors: %d\n", err_cnt);
+    $finish();
+    #5;
+    $display("You're trying to run simulation that has finished. Aborting simulation.")
+    $fatal();
+  end
 
-    task random_test();
-      repeat(1e4) begin
-        tb_a_i     = $urandom();
-        tb_b_i     = $urandom();
-        tb_carry_i = $urandom_range(1);
+  task sequential_add_test();
+    @(posedge clk);
+    tb_a_i = 0;
+    tb_b_i = 0;
+    tb_carry_i = 0;
+    @(posedge clk);
+    for(int i = 0; i < 16; i++) begin
+      tb_a_i += 256;
+      for(int j = 0; j < 16; j++) begin
+        tb_b_i += 256;
+        tb_carry_i = ~tb_carry_i;
         @(posedge clk);
       end
-    endtask
+    end
+  endtask
 
-    logic [32:0] reference;
-    assign reference = {1'b0, tb_a_i} + {1'b0, tb_b_i} + tb_carry_i;
+  task random_test();
+    repeat(1e4) begin
+      tb_a_i     = $urandom();
+      tb_b_i     = $urandom();
+      tb_carry_i = $urandom_range(1);
+      @(posedge clk);
+    end
+  endtask
 
-    sum_check: assert property (
-      @(negedge clk)
-      reference === {tb_carry_o, tb_sum_o}
-    )
-    else begin
-      err_cnt++;
-      $error("\noperands : a_i = 0x%08h, b_i = 0x%08h, carry_i = %b\nyour res : sum = 0x%08h, carry_o = %b\nreference: sum = 0x%08h, carry_o = %b",
-             tb_a_i, tb_b_i, tb_carry_i, tb_sum_o, tb_carry_o, reference[31:0], reference [32]);
-      if(err_cnt == 10) begin
-        $display("\nTest has been stopped after 10 errors");
-        $stop();
-      end
+  logic [32:0] reference;
+  assign reference = {1'b0, tb_a_i} + {1'b0, tb_b_i} + tb_carry_i;
+
+  sum_check: assert property (
+    @(negedge clk)
+    reference === {tb_carry_o, tb_sum_o}
+  )
+  else begin
+    err_cnt++;
+    $error("\noperands : a_i = 0x%08h, b_i = 0x%08h, carry_i = %b\nyour res : sum = 0x%08h, carry_o = %b\nreference: sum = 0x%08h, carry_o = %b",
+           tb_a_i, tb_b_i, tb_carry_i, tb_sum_o, tb_carry_o, reference[31:0], reference [32]);
+    if(err_cnt == 10) begin
+      $display("\nTest has been stopped after 10 errors");
+      $stop();
     end
+  end
 endmodule
diff --git a/Labs/01. Adder/lab_01.tb_fulladder4.sv b/Labs/01. Adder/lab_01.tb_fulladder4.sv
index f830f5df..ed0053b3 100644
--- a/Labs/01. Adder/lab_01.tb_fulladder4.sv	
+++ b/Labs/01. Adder/lab_01.tb_fulladder4.sv	
@@ -11,33 +11,36 @@ See https://github.com/MPSU/APS/blob/master/LICENSE file for licensing details.
 
 module lab_01_tb_fulladder4();
 
-    logic [3:0] tb_a_i;
-    logic [3:0] tb_b_i;
-    logic       tb_carry_i;
-    logic       tb_carry_o;
-    logic [3:0] tb_sum_o;
-    logic [8:0] test_case;
+  logic [3:0] tb_a_i;
+  logic [3:0] tb_b_i;
+  logic       tb_carry_i;
+  logic       tb_carry_o;
+  logic [3:0] tb_sum_o;
+  logic [8:0] test_case;
 
-    fulladder4 DUT (
-        .a_i(tb_a_i),
-        .b_i(tb_b_i),
-        .sum_o(tb_sum_o),
-        .carry_i(tb_carry_i),
-        .carry_o(tb_carry_o)
-    );
+  fulladder4 DUT (
+    .a_i(tb_a_i),
+    .b_i(tb_b_i),
+    .sum_o(tb_sum_o),
+    .carry_i(tb_carry_i),
+    .carry_o(tb_carry_o)
+  );
 
-    assign {tb_a_i, tb_b_i, tb_carry_i} = test_case;
+  assign {tb_a_i, tb_b_i, tb_carry_i} = test_case;
 
-    initial begin
-      $display("Test has been started");
+  initial begin
+    $display("Test has been started");
+    #5ns;
+    test_case = 9'd0;
+    repeat(512) begin
       #5ns;
-      test_case = 9'd0;
-      repeat(512) begin
-        #5ns;
-        test_case++;
-      end
-      $display("\nTest has been finished Check results at waveform window.\n");
-      $finish();
+      test_case++;
     end
+    $display("\nTest has been finished Check results at waveform window.\n");
+    $finish();
+    #5;
+    $display("You're trying to run simulation that has finished. Aborting simulation.")
+    $fatal();
+  end
 
 endmodule
diff --git a/Labs/02. Arithmetic-logic unit/lab_02.tb_alu.sv b/Labs/02. Arithmetic-logic unit/lab_02.tb_alu.sv
index 2a2a39a4..4cc6efd8 100644
--- a/Labs/02. Arithmetic-logic unit/lab_02.tb_alu.sv	
+++ b/Labs/02. Arithmetic-logic unit/lab_02.tb_alu.sv	
@@ -63,6 +63,9 @@ initial
     direct_test();
     $display("\nTest has been finished\nNumber of errors: %d\n", err_cnt);
     $finish();
+    #5;
+    $display("You're trying to run simulation that has finished. Aborting simulation.")
+    $fatal();
   end
 
 task X_test();
@@ -247,23 +250,22 @@ end
 
 endmodule
 
-parameter ALUOP_W = 5;
-parameter OP_W = 32;
-parameter SHIFT_W = $clog2(OP_W);
-parameter STAGE_LEN = OP_W+1;
-parameter HASH_LEN = 1000;
-parameter START_CODING = 10366;
-parameter START_MUX = START_CODING+100;
 
 module alu_ref (
-    input  logic [ALUOP_W-1:0] alu_op_i,
-    input  logic [OP_W-1:0]    a_i,
-    input  logic [OP_W-1:0]    b_i,
-    output logic [OP_W-1:0]    result_o,
-    output logic               flag_o
+    input  logic [ 4:0] alu_op_i,
+    input  logic [31:0] a_i,
+    input  logic [31:0] b_i,
+    output logic [31:0] result_o,
+    output logic        flag_o
 );
 
-
+localparam ALUOP_W = 5;
+localparam OP_W = 32;
+localparam SHIFT_W = $clog2(OP_W);
+localparam STAGE_LEN = OP_W+1;
+localparam HASH_LEN = 1000;
+localparam START_CODING = 10366;
+localparam START_MUX = START_CODING+100;
 
 genvar i, j, k;
 
diff --git a/Labs/03. Register file and memory/lab_03.tb_register_file.sv b/Labs/03. Register file and memory/lab_03.tb_register_file.sv
index 6ed9aa27..125c67ec 100644
--- a/Labs/03. Register file and memory/lab_03.tb_register_file.sv	
+++ b/Labs/03. Register file and memory/lab_03.tb_register_file.sv	
@@ -10,146 +10,149 @@ See https://github.com/MPSU/APS/blob/master/LICENSE file for licensing details.
 */
 module lab_03_tb_register_file();
 
-    logic        CLK;
-    logic [ 4:0] RA1;
-    logic [ 4:0] RA2;
-    logic [ 4:0] WA;
-    logic [31:0] WD;
-    logic        WE;
-
-    logic [31:0] RD1;
-    logic [31:0] RD2;
-    logic [31:0] RD1ref;
-    logic [31:0] RD2ref;
-
-    register_file DUT(
-        .clk_i         (CLK),
-        .read_addr1_i  (RA1),
-        .read_addr2_i  (RA2),
-        .write_addr_i  (WA ),
-        .write_data_i  (WD ),
-        .write_enable_i(WE ),
-        .read_data1_o  (RD1),
-        .read_data2_o  (RD2)
-    );
-
-    register_file_ref DUTref(
-        .clk_i         (CLK   ),
-        .read_addr1_i  (RA1   ),
-        .read_addr2_i  (RA2   ),
-        .write_addr_i  (WA    ),
-        .write_data_i  (WD    ),
-        .write_enable_i(WE    ),
-        .read_data1_o  (RD1ref),
-        .read_data2_o  (RD2ref)
-    );
-
-    integer i, err_count = 0;
-
-    parameter CLK_FREQ_MHz   = 100;
-    parameter CLK_SEMI_PERIOD= 1e3/CLK_FREQ_MHz/2;
-
-    parameter address_length = 32;
-
-    initial CLK <= 0;
-    always begin
-        #CLK_SEMI_PERIOD CLK = ~CLK;
-        if (err_count >= 10) begin
-            $display("\n\nThe test was stopped due to errors"); $stop();
-        end
+  logic        CLK;
+  logic [ 4:0] RA1;
+  logic [ 4:0] RA2;
+  logic [ 4:0] WA;
+  logic [31:0] WD;
+  logic        WE;
+
+  logic [31:0] RD1;
+  logic [31:0] RD2;
+  logic [31:0] RD1ref;
+  logic [31:0] RD2ref;
+
+  register_file DUT(
+    .clk_i         (CLK),
+    .read_addr1_i  (RA1),
+    .read_addr2_i  (RA2),
+    .write_addr_i  (WA ),
+    .write_data_i  (WD ),
+    .write_enable_i(WE ),
+    .read_data1_o  (RD1),
+    .read_data2_o  (RD2)
+  );
+
+  register_file_ref DUTref(
+    .clk_i         (CLK   ),
+    .read_addr1_i  (RA1   ),
+    .read_addr2_i  (RA2   ),
+    .write_addr_i  (WA    ),
+    .write_data_i  (WD    ),
+    .write_enable_i(WE    ),
+    .read_data1_o  (RD1ref),
+    .read_data2_o  (RD2ref)
+  );
+
+  integer i, err_count = 0;
+
+  parameter CLK_FREQ_MHz   = 100;
+  parameter CLK_SEMI_PERIOD= 1e3/CLK_FREQ_MHz/2;
+
+  parameter address_length = 32;
+
+  initial CLK <= 0;
+  always begin
+    #CLK_SEMI_PERIOD CLK = ~CLK;
+    if (err_count >= 10) begin
+      $display("\n\nThe test was stopped due to errors"); $stop();
     end
+  end
 
-    initial begin
-      $timeformat (-9, 2, "ns");
-      $display("Test has been started");
-      RA1 = 'b1;
-      @(posedge CLK);
-        if (32'hx !== RD1) begin
-        $display("The register file should not be initialized by the $readmemh function");
-        err_count = err_count + 1;
-      end
-      @(posedge CLK);
-      DUT.rf_mem[32] = 32'd1;
-      if(DUT.rf_mem[32]=== 32'd1) begin
-        $display("invalid memory size");
-        err_count = err_count + 1;
-      end
-      RA1 <= 'b0;
-      RA2 <= 'b0;
-      @(posedge CLK);
-      if( RD1 !== 'b0 ) begin
-        $display("time = %0t. invalid data when reading at address 0: RD1 = %h", $time, RD1);
-        err_count = err_count + 1;
-      end
-      if( RD2 !== 'b0 ) begin
-        $display("time = %0t. invalid data when reading at address 0: RD2 = %h", $time, RD2);
-        err_count = err_count + 1;
-      end
-      @(posedge CLK);
-      WD <= 32'd1;
-      WA <= '0;
-      WE <= 1'b1;
-      @(posedge CLK);
-      WE  <= 'b0;
-      RA1 <= 'b0;
-      @(posedge CLK);
-      if( RD1 !== 'b0 ) begin
-        $display("time = %0t. invalid data when reading at address 0: RD1 = %h", $time, RD1);
-        err_count = err_count + 1;
-      end
-      @(posedge CLK);
-      //------initial
-      CLK <= 'b0;
-      RA1 <= 'b0;
-      RA2 <= 'b0;
-      WA  <= 'b0;
-      WD  <= 'b0;
-      WE  <= 'b0;
-      @(posedge CLK);
-      //----- reset
-      for( i = 1; i < address_length; i = i + 1) begin
-        @(posedge CLK);
-        WA <= i;
-        WD <= 'b0;
-        WE <= 'b1;
-      end
+  initial begin
+    $timeformat (-9, 2, "ns");
+    $display("Test has been started");
+    RA1 = 'b1;
+    @(posedge CLK);
+      if (32'hx !== RD1) begin
+      $display("The register file should not be initialized by the $readmemh function");
+      err_count = err_count + 1;
+    end
+    @(posedge CLK);
+    DUT.rf_mem[32] = 32'd1;
+    if(DUT.rf_mem[32]=== 32'd1) begin
+      $display("invalid memory size");
+      err_count = err_count + 1;
+    end
+    RA1 <= 'b0;
+    RA2 <= 'b0;
+    @(posedge CLK);
+    if( RD1 !== 'b0 ) begin
+      $display("time = %0t. invalid data when reading at address 0: RD1 = %h", $time, RD1);
+      err_count = err_count + 1;
+    end
+    if( RD2 !== 'b0 ) begin
+      $display("time = %0t. invalid data when reading at address 0: RD2 = %h", $time, RD2);
+      err_count = err_count + 1;
+    end
+    @(posedge CLK);
+    WD <= 32'd1;
+    WA <= '0;
+    WE <= 1'b1;
+    @(posedge CLK);
+    WE  <= 'b0;
+    RA1 <= 'b0;
+    @(posedge CLK);
+    if( RD1 !== 'b0 ) begin
+      $display("time = %0t. invalid data when reading at address 0: RD1 = %h", $time, RD1);
+      err_count = err_count + 1;
+    end
+    @(posedge CLK);
+    //------initial
+    CLK <= 'b0;
+    RA1 <= 'b0;
+    RA2 <= 'b0;
+    WA  <= 'b0;
+    WD  <= 'b0;
+    WE  <= 'b0;
+    @(posedge CLK);
+    //----- reset
+    for( i = 1; i < address_length; i = i + 1) begin
       @(posedge CLK);
-      WA  <= 'b0;
-      WD  <= 'b1;
+      WA <= i;
+      WD <= 'b0;
       WE <= 'b1;
+    end
+    @(posedge CLK);
+    WA  <= 'b0;
+    WD  <= 'b1;
+    WE <= 'b1;
+    @(posedge CLK);
+    WE <= 'b0;
+    RA2  <= 'b0;
+    @(posedge CLK);
+    if( RD2 !== 'b0 )begin
+      $display("time = %0t. invalid data when reading at address 0: RD2 = %h", $time, RD2);
+      err_count = err_count + 1;
+    end
+    @(posedge CLK);
+    for( i = 1; i < address_length; i = i + 1) begin
       @(posedge CLK);
-      WE <= 'b0;
-      RA2  <= 'b0;
+      WA <= i;
+      WD <= $urandom;
+      WE <= $urandom % 2;
+    end
+    @(posedge CLK);
+    WE <= 'b0;
+    for( i = 0; i < address_length; i = i + 1) begin
       @(posedge CLK);
-      if( RD2 !== 'b0 )begin
-        $display("time = %0t. invalid data when reading at address 0: RD2 = %h", $time, RD2);
-        err_count = err_count + 1;
-      end
+      RA1  <= i;
+      RA2  <= address_length - (i + 1);
       @(posedge CLK);
-      for( i = 1; i < address_length; i = i + 1) begin
-        @(posedge CLK);
-        WA <= i;
-        WD <= $urandom;
-        WE <= $urandom % 2;
+      if(RD1ref !== RD1) begin
+          $display("time = %0t, address %h, RD1. Invalid data %h, correct data %h", $time, RA1, RD1, RD1ref);
+          err_count = err_count + 1;
       end
-      @(posedge CLK);
-      WE <= 'b0;
-      for( i = 0; i < address_length; i = i + 1) begin
-        @(posedge CLK);
-        RA1  <= i;
-        RA2  <= address_length - (i + 1);
-        @(posedge CLK);
-        if(RD1ref !== RD1) begin
-            $display("time = %0t, address %h, RD1. Invalid data %h, correct data %h", $time, RA1, RD1, RD1ref);
-            err_count = err_count + 1;
-        end
-        if(RD2ref !== RD2) begin
-            $display("time = %0t, address %h, RD2. Invalid data %h, correct data %h", $time, RA2, RD2, RD2ref);
-            err_count = err_count + 1;
-        end
+      if(RD2ref !== RD2) begin
+          $display("time = %0t, address %h, RD2. Invalid data %h, correct data %h", $time, RA2, RD2, RD2ref);
+          err_count = err_count + 1;
       end
-      if( !err_count ) $display("\nregister file SUCCESS!!!\n");
-      $finish();
+    end
+    $display("\nTest has been finished\nNumber of errors: %d\n", err_count);
+    $finish();
+    #5;
+    $display("You're trying to run simulation that has finished. Aborting simulation.")
+    $fatal();
     end
 endmodule
 
diff --git a/Labs/04. Primitive programmable device/lab_04.tb_cybercobra.sv b/Labs/04. Primitive programmable device/lab_04.tb_cybercobra.sv
index 198dcb53..4d142d01 100644
--- a/Labs/04. Primitive programmable device/lab_04.tb_cybercobra.sv	
+++ b/Labs/04. Primitive programmable device/lab_04.tb_cybercobra.sv	
@@ -36,6 +36,9 @@ module lab_04_tb_CYBERcobra();
     #10000;
     $display("\n The test is over \n See the internal signals of the CYBERcobra on the waveform \n");
     $finish;
+    #5;
+    $display("You're trying to run simulation that has finished. Aborting simulation.")
+    $fatal();
     end
 
 endmodule
diff --git a/Labs/05. Main decoder/lab_05.tb_decoder.sv b/Labs/05. Main decoder/lab_05.tb_decoder.sv
index b7a109c8..b7da3703 100644
--- a/Labs/05. Main decoder/lab_05.tb_decoder.sv	
+++ b/Labs/05. Main decoder/lab_05.tb_decoder.sv	
@@ -15,7 +15,7 @@ module lab_05_tb_decoder();
   typedef class riscv_instr;
   riscv_instr instr = new();
 
-  logic clk, test_has_been_finished;
+  logic clk;
   logic [31:0]  fetched_instr_i = '0;
 
   int err_count;
@@ -136,8 +136,10 @@ module lab_05_tb_decoder();
     illegal_instrs_random_test();
 
     $display("\nTest has been finished\nNumber of errors: %d\n", err_count);
-    test_has_been_finished = 1'b1;
     $finish();
+    #5;
+    $display("You're trying to run simulation that has finished. Aborting simulation.")
+    $fatal();
   end
 
   function void randomize_with_given_opcode(input logic[4:0] given_opcode);
@@ -348,17 +350,12 @@ module lab_05_tb_decoder();
   bit test_paused_by_errs;
   initial begin
     clk                     = '0;
-    test_has_been_finished  = '0;
     err_count               = '0;
     test_paused_by_errs     = '0;
   end
 
   always #5 clk = ~clk;
-  always @(posedge clk) begin
-    if(test_has_been_finished) begin
-      $finish();
-    end
-  end
+
 
   always @(posedge clk) begin
     if((err_count >= 10) & !test_paused_by_errs) begin
diff --git a/Labs/06. Main memory/lab_06.tb_data_mem.sv b/Labs/06. Main memory/lab_06.tb_data_mem.sv
index c0cc9ede..055cdb92 100644
--- a/Labs/06. Main memory/lab_06.tb_data_mem.sv	
+++ b/Labs/06. Main memory/lab_06.tb_data_mem.sv	
@@ -30,8 +30,6 @@ module lab_06_tb_data_mem;
 
   int err_cnt = 0;
 
-  static bit  simulation_finished;
-
   data_mem DUT (.*);
 
   task read_request(input logic [31:0] address, output logic [31:0] data);
@@ -173,8 +171,10 @@ module lab_06_tb_data_mem;
     random_test();
 
     $display("\nTest has been finished\nNumber of errors: %d\n", err_cnt);
-    simulation_finished = 1;
     $finish;
+    #5;
+    $display("You're trying to run simulation that has finished. Aborting simulation.")
+    $fatal();
   end
 
   logic [31:0] ram_data;
@@ -275,13 +275,6 @@ module lab_06_tb_data_mem;
     $display("Error at %t. ram[%d][31:24] is unstable without write request", $time(), $sampled(addr_reg));
   end
 
-
-  always @(posedge clk_i) begin
-    if(simulation_finished) begin
-      $finish;
-    end
-  end
-
   always @(posedge clk_i) begin
     if (err_cnt >= 10) begin
       $display("\nTest has been stopped after 10 errors"); $stop();
diff --git a/Labs/07. Datapath/lab_07.tb_processor_system.sv b/Labs/07. Datapath/lab_07.tb_processor_system.sv
index 89327e70..1dc072d4 100644
--- a/Labs/07. Datapath/lab_07.tb_processor_system.sv	
+++ b/Labs/07. Datapath/lab_07.tb_processor_system.sv	
@@ -18,17 +18,20 @@ module lab_07_tb_processor_system();
     .rst_i(rst)
     );
 
-    initial clk = 0;
+  initial clk = 0;
     always #10 clk = ~clk;
     initial begin
-        $display( "\nTest has been started.");
-        rst = 1;
-        #40;
-        rst = 0;
-        #800;
-        $display("\n The test is over \n See the internal signals of the module on the waveform \n");
-        $finish;
-    end
+      $display( "\nTest has been started.");
+      rst = 1;
+      #40;
+      rst = 0;
+      #800;
+      $display("\n The test is over \n See the internal signals of the module on the waveform \n");
+      $finish;
+      #5;
+      $display("You're trying to run simulation that has finished. Aborting simulation.")
+      $fatal();
+  end
 
 stall_seq: assert property (
   @(posedge system.core.clk_i) disable iff ( system.core.rst_i )
diff --git a/Labs/08. Load-store unit/lab_08.tb_lsu.sv b/Labs/08. Load-store unit/lab_08.tb_lsu.sv
index 27206c48..1a819756 100644
--- a/Labs/08. Load-store unit/lab_08.tb_lsu.sv	
+++ b/Labs/08. Load-store unit/lab_08.tb_lsu.sv	
@@ -63,6 +63,9 @@ initial begin
   repeat(3e3)@(posedge clk_i);
   $display("Simulation finished. Number of errors: %d", err_count);
   $finish();
+  #5;
+  $display("You're trying to run simulation that has finished. Aborting simulation.")
+  $fatal();
 end
 
 initial begin
diff --git a/Labs/Made-up modules/lab_02.alu.sv b/Labs/Made-up modules/lab_02.alu.sv
index b3189b23..8ed4dff4 100644
--- a/Labs/Made-up modules/lab_02.alu.sv	
+++ b/Labs/Made-up modules/lab_02.alu.sv	
@@ -1,6 +1,6 @@
 /* -----------------------------------------------------------------------------
 * Project Name   : Architectures of Processor Systems (APS) lab work
-* File           : alu_riscv.sv
+* File           : alu.sv
 * Organization   : National Research University of Electronic Technology (MIET)
 * Department     : Institute of Microdevices and Control Systems
 * Author(s)      : Alexey Kozin
@@ -10,22 +10,22 @@ See LICENSE file for licensing details.
 * ------------------------------------------------------------------------------
 */
 
-parameter ALUOP_W = 5;
-parameter OP_W = 32;
-parameter SHIFT_W = $clog2(OP_W);
-parameter STAGE_LEN = OP_W+1;
-parameter HASH_LEN = 1000;
-parameter START_CODING = 10366;
-parameter START_MUX = START_CODING+100;
-
-module alu_riscv (
-    input  logic [ALUOP_W-1:0] alu_op_i,
-    input  logic [OP_W-1:0]    a_i,
-    input  logic [OP_W-1:0]    b_i,
-    output logic [OP_W-1:0]    result_o,
-    output logic               flag_o
+module alu (
+    input  logic [4:0]   alu_op_i,
+    input  logic [31:0]  a_i,
+    input  logic [31:0]  b_i,
+    output logic [31:0]  result_o,
+    output logic         flag_o
 );
 
+localparam ALUOP_W = 5;
+localparam OP_W = 32;
+localparam SHIFT_W = $clog2(OP_W);
+localparam STAGE_LEN = OP_W+1;
+localparam HASH_LEN = 1000;
+localparam START_CODING = 10366;
+localparam START_MUX = START_CODING+100;
+
 genvar i, j, k;
 
 logic [OP_W-1:0]      skjfbsbgisg [0:STAGE_LEN-1];
diff --git a/Labs/Made-up modules/lab_03.data_mem.sv b/Labs/Made-up modules/lab_03.data_mem.sv
deleted file mode 100644
index ba94f017..00000000
--- a/Labs/Made-up modules/lab_03.data_mem.sv	
+++ /dev/null
@@ -1,54 +0,0 @@
-/* -----------------------------------------------------------------------------
-* Project Name   : Architectures of Processor Systems (APS) lab work
-* Organization   : National Research University of Electronic Technology (MIET)
-* Department     : Institute of Microdevices and Control Systems
-* Author(s)      : Nikita Bulavin
-* Email(s)       : nekkit6@edu.miet.ru
-
-See https://github.com/MPSU/APS/blob/master/LICENSE file for licensing details.
-* ------------------------------------------------------------------------------
-*/
-module data_mem (
-  input  logic         clk_i,
-  input  logic [31:0]  addr_i,
-  input  logic [31:0]  write_data_i,
-  input  logic         write_enable_i,
-  input  logic         mem_req_i,
-  output logic [31:0]  read_data_o
-);
-
-`define akjsdnnaskjdndat  $clog2(128)
-`define cdyfguvhbjnmkdat  $clog2(`akjsdnnaskjdndat)
-`define qwenklfsaklasddat $clog2(`cdyfguvhbjnmkdat)
-`define asdasdhkjasdsadat (34>>`cdyfguvhbjnmkdat)
-
-logic [31:0] RAM [0:4095];
-logic [31:0] addr;
-assign addr = {20'b0, addr_i[13:2]};
-
-always_ff @(posedge clk_i) begin
-    if(write_enable_i&mem_req_i) RAM[addr[13'o10+13'b101:'hBA & 'h45]][{5{1'b1}}:{3'd7,2'b00}] <= write_data_i['h1f:'h1c];
-    if(write_enable_i&mem_req_i) RAM[addr[13'o10+13'b101:'hBA & 'h45]][19:{1'b1,4'h0}] <= write_data_i[42-23-:`asdasdhkjasdsadat];
-    if(write_enable_i&mem_req_i) RAM[addr[13'o10+13'b101:'hBA & 'h45]][{3{1'b1}}:{1'b1,2'h0}] <= write_data_i[`akjsdnnaskjdndat-:`asdasdhkjasdsadat];
-    if(write_enable_i&mem_req_i) RAM[addr[13'o10+13'b101:'hBA & 'h45]][23:{{2{2'b10}},1'b0}] <= write_data_i[42-19-:`asdasdhkjasdsadat];
-    if(write_enable_i&mem_req_i) RAM[addr[13'o10+13'b101:'hBA & 'h45]][27:{2'b11,3'b000}] <= write_data_i['h1b:'h18];
-    if(write_enable_i&mem_req_i) RAM[addr[13'o10+13'b101:'hBA & 'h45]][11:{1'b1,{3{1'b0}}}] <= write_data_i[`akjsdnnaskjdndat+`asdasdhkjasdsadat:(`akjsdnnaskjdndat+`asdasdhkjasdsadat)-`cdyfguvhbjnmkdat];
-    if(write_enable_i&mem_req_i) RAM[addr[13'o10+13'b101:'hBA & 'h45]][{2{1'b1}}:{3{1'b0}}] <= write_data_i[`akjsdnnaskjdndat-`asdasdhkjasdsadat-:`asdasdhkjasdsadat];
-    if(write_enable_i&mem_req_i) RAM[addr[13'o10+13'b101:'hBA & 'h45]][{4{1'b1}}:4'b1100] <= write_data_i[(`akjsdnnaskjdndat<<(`asdasdhkjasdsadat-`cdyfguvhbjnmkdat)) + (`asdasdhkjasdsadat-`cdyfguvhbjnmkdat):12]; 
-end
-always_ff@(posedge clk_i) begin
-  case(1)
-  mem_req_i&&!write_enable_i: begin
-    read_data_o['h1f:'h1c]<=RAM[addr[13'o10+13'b101:'hBA & 'h45]][{5{1'b1}}:{3'd7,2'b00}];
-    read_data_o[42-23-:`asdasdhkjasdsadat]<=RAM[addr[13'o10+13'b101:'hBA & 'h45]][19:{1'b1,4'h0}];
-    read_data_o[`akjsdnnaskjdndat-:`asdasdhkjasdsadat]<=RAM[addr[13'o10+13'b101:'hBA & 'h45]][{3{1'b1}}:{1'b1,2'h0}];
-    read_data_o[42-19-:`asdasdhkjasdsadat]<=RAM[addr[13'o10+13'b101:'hBA & 'h45]][23:{{2{2'b10}},1'b0}];
-    read_data_o['h1b:'h18]<=RAM[addr[13'o10+13'b101:'hBA & 'h45]][27:{2'b11,3'b000}];
-    read_data_o[`akjsdnnaskjdndat+`asdasdhkjasdsadat:(`akjsdnnaskjdndat+`asdasdhkjasdsadat)-`cdyfguvhbjnmkdat]<=RAM[addr[13'o10+13'b101:'hBA & 'h45]][11:8];
-    read_data_o[`akjsdnnaskjdndat-`asdasdhkjasdsadat-:`asdasdhkjasdsadat]<=RAM[addr[13'o10+13'b101:'hBA & 'h45]][3:0];
-    read_data_o[(`akjsdnnaskjdndat<<(`asdasdhkjasdsadat-`cdyfguvhbjnmkdat))+(`asdasdhkjasdsadat-`cdyfguvhbjnmkdat):12]<=RAM[addr[13'o10+13'b101:'hBA & 'h45]][{4{1'b1}}:12];
-  end
-  default: read_data_o <= read_data_o;
-  endcase
-end
-endmodule
diff --git a/Labs/Made-up modules/lab_03.instr_mem.sv b/Labs/Made-up modules/lab_03.instr_mem.sv
index 29f70f6d..f860be40 100644
--- a/Labs/Made-up modules/lab_03.instr_mem.sv	
+++ b/Labs/Made-up modules/lab_03.instr_mem.sv	
@@ -2,8 +2,8 @@
 * Project Name   : Architectures of Processor Systems (APS) lab work
 * Organization   : National Research University of Electronic Technology (MIET)
 * Department     : Institute of Microdevices and Control Systems
-* Author(s)      : Nikita Bulavin
-* Email(s)       : nekkit6@edu.miet.ru
+* Author(s)      : Andrei Solodovnikov
+* Email(s)       : hepoh@org.miet.ru
 
 See https://github.com/MPSU/APS/blob/master/LICENSE file for licensing details.
 * ------------------------------------------------------------------------------
diff --git a/Labs/Made-up modules/lab_03.register_file.sv b/Labs/Made-up modules/lab_03.register_file.sv
index 01135714..1819cec7 100644
--- a/Labs/Made-up modules/lab_03.register_file.sv	
+++ b/Labs/Made-up modules/lab_03.register_file.sv	
@@ -8,7 +8,7 @@
 See https://github.com/MPSU/APS/blob/master/LICENSE file for licensing details.
 * ------------------------------------------------------------------------------
 */
-module rf_riscv(
+module register_file(
   input  logic        clk_i,
   input  logic        write_enable_i,
 

From 8396bb51ab770911366d1adce078216ed159becb Mon Sep 17 00:00:00 2001
From: Andrei Solodovnikov <VoultBoy@yandex.ru>
Date: Mon, 9 Sep 2024 13:39:18 +0300
Subject: [PATCH 02/14] Update lab_02.tb_alu.sv

---
 Labs/02. Arithmetic-logic unit/lab_02.tb_alu.sv | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/Labs/02. Arithmetic-logic unit/lab_02.tb_alu.sv b/Labs/02. Arithmetic-logic unit/lab_02.tb_alu.sv
index 4cc6efd8..8c6b1cd4 100644
--- a/Labs/02. Arithmetic-logic unit/lab_02.tb_alu.sv	
+++ b/Labs/02. Arithmetic-logic unit/lab_02.tb_alu.sv	
@@ -64,7 +64,7 @@ initial
     $display("\nTest has been finished\nNumber of errors: %d\n", err_cnt);
     $finish();
     #5;
-    $display("You're trying to run simulation that has finished. Aborting simulation.")
+    $display("You're trying to run simulation that has finished. Aborting simulation.");
     $fatal();
   end
 

From ffec97f5acf165488eb1660425731ae921386feb Mon Sep 17 00:00:00 2001
From: Andrei Solodovnikov <VoultBoy@yandex.ru>
Date: Mon, 9 Sep 2024 14:35:29 +0300
Subject: [PATCH 03/14] =?UTF-8?q?=D0=9B=D0=A02.=20=D0=98=D1=81=D0=BF=D1=80?=
 =?UTF-8?q?=D0=B0=D0=B2=D0=BB=D0=B5=D0=BD=D0=B8=D0=B5=20=D0=BF=D0=BE=D0=B4?=
 =?UTF-8?q?=D0=BA=D0=BB=D1=8E=D1=87=D0=B5=D0=BD=D0=B8=D1=8F=20=D0=BC=D0=BE?=
 =?UTF-8?q?=D0=B4=D1=83=D0=BB=D1=8F=20=D0=B2=20nexys=5Falu?=
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

---
 Labs/02. Arithmetic-logic unit/board files/nexys_alu.sv | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/Labs/02. Arithmetic-logic unit/board files/nexys_alu.sv b/Labs/02. Arithmetic-logic unit/board files/nexys_alu.sv
index 6f35552f..b5eadd3d 100644
--- a/Labs/02. Arithmetic-logic unit/board files/nexys_alu.sv	
+++ b/Labs/02. Arithmetic-logic unit/board files/nexys_alu.sv	
@@ -45,7 +45,7 @@ module nexys_alu(
   logic [31:0]              result;
   logic                     flag;
 
-  alu_riscv alu_riscv (
+  alu alu_riscv (
     .alu_op_i (operator),
     .a_i      (operand_a),
     .b_i      (operand_b),

From 7b58389d55a132b0ad141fc0c44e4e231c9a6d59 Mon Sep 17 00:00:00 2001
From: Andrei Solodovnikov <VoultBoy@yandex.ru>
Date: Mon, 9 Sep 2024 14:36:28 +0300
Subject: [PATCH 04/14] =?UTF-8?q?=D0=9B=D0=A03.=20=D0=98=D1=81=D0=BF=D1=80?=
 =?UTF-8?q?=D0=B0=D0=B2=D0=BB=D0=B5=D0=BD=D0=B8=D0=B5=20=D0=BF=D0=BE=D0=B4?=
 =?UTF-8?q?=D0=BA=D0=BB=D1=8E=D1=87=D0=B5=D0=BD=D0=B8=D1=8F=20=D0=BC=D0=BE?=
 =?UTF-8?q?=D0=B4=D1=83=D0=BB=D1=8F=20=D0=B2=20nexys=5Frf?=
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

---
 Labs/03. Register file and memory/board files/nexys_rf_riscv.sv | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/Labs/03. Register file and memory/board files/nexys_rf_riscv.sv b/Labs/03. Register file and memory/board files/nexys_rf_riscv.sv
index 02b494cc..686f2a73 100644
--- a/Labs/03. Register file and memory/board files/nexys_rf_riscv.sv	
+++ b/Labs/03. Register file and memory/board files/nexys_rf_riscv.sv	
@@ -34,7 +34,7 @@ module nexys_rf_riscv(
   logic [7:0][3:0] rd1;
   logic [7:0][3:0] rd2;
 
-  rf_riscv rf_riscv (
+  register_file rf_riscv (
     .clk_i            (clk_i),
     .read_addr1_i     (ra1  ),
     .read_addr2_i     (ra2  ),

From d01bbbd4271fae3105d61e402744cdb206f0d334 Mon Sep 17 00:00:00 2001
From: Sergey Chusov <44680536+serge0699@users.noreply.github.com>
Date: Tue, 10 Sep 2024 11:45:39 +0300
Subject: [PATCH 05/14] =?UTF-8?q?=D0=9B=D0=A01:=20=D0=94=D0=BE=D0=B1=D0=B0?=
 =?UTF-8?q?=D0=B2=D0=BB=D0=B5=D0=BD=D0=B8=D0=B5=20=D0=BF=D0=BE=D1=82=D0=B5?=
 =?UTF-8?q?=D1=80=D1=8F=D0=BD=D0=BD=D0=BE=D0=B9=20=D1=82=D0=BE=D1=87=D0=BA?=
 =?UTF-8?q?=D0=B8=20=D1=81=20=D0=B7=D0=B0=D0=BF=D1=8F=D1=82=D0=BE=D0=B9?=
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

---
 Labs/01. Adder/lab_01.tb_fulladder.sv   | 2 +-
 Labs/01. Adder/lab_01.tb_fulladder32.sv | 2 +-
 Labs/01. Adder/lab_01.tb_fulladder4.sv  | 2 +-
 3 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/Labs/01. Adder/lab_01.tb_fulladder.sv b/Labs/01. Adder/lab_01.tb_fulladder.sv
index af97903f..da0ece11 100644
--- a/Labs/01. Adder/lab_01.tb_fulladder.sv	
+++ b/Labs/01. Adder/lab_01.tb_fulladder.sv	
@@ -39,7 +39,7 @@ module lab_01_tb_fulladder();
     $display("\nTest has been finished. Check results at waveform window.\n");
     $finish();
     #5;
-    $display("You're trying to run simulation that has finished. Aborting simulation.")
+    $display("You're trying to run simulation that has finished. Aborting simulation.");
     $fatal();
   end
 
diff --git a/Labs/01. Adder/lab_01.tb_fulladder32.sv b/Labs/01. Adder/lab_01.tb_fulladder32.sv
index 09606376..026bcf6c 100644
--- a/Labs/01. Adder/lab_01.tb_fulladder32.sv	
+++ b/Labs/01. Adder/lab_01.tb_fulladder32.sv	
@@ -37,7 +37,7 @@ module lab_01_tb_fulladder32();
     $display("\nTest has been finished\nNumber of errors: %d\n", err_cnt);
     $finish();
     #5;
-    $display("You're trying to run simulation that has finished. Aborting simulation.")
+    $display("You're trying to run simulation that has finished. Aborting simulation.");
     $fatal();
   end
 
diff --git a/Labs/01. Adder/lab_01.tb_fulladder4.sv b/Labs/01. Adder/lab_01.tb_fulladder4.sv
index ed0053b3..9c2c31c2 100644
--- a/Labs/01. Adder/lab_01.tb_fulladder4.sv	
+++ b/Labs/01. Adder/lab_01.tb_fulladder4.sv	
@@ -39,7 +39,7 @@ module lab_01_tb_fulladder4();
     $display("\nTest has been finished Check results at waveform window.\n");
     $finish();
     #5;
-    $display("You're trying to run simulation that has finished. Aborting simulation.")
+    $display("You're trying to run simulation that has finished. Aborting simulation.");
     $fatal();
   end
 

From 2397237ad34a7a39f592cfaacb0d3b83299e93b5 Mon Sep 17 00:00:00 2001
From: Andrei Solodovnikov <VoultBoy@yandex.ru>
Date: Wed, 11 Sep 2024 19:17:48 +0300
Subject: [PATCH 06/14] Update README.md

---
 Labs/README.md | 4 +---
 1 file changed, 1 insertion(+), 3 deletions(-)

diff --git a/Labs/README.md b/Labs/README.md
index 92b33db2..27b349d5 100644
--- a/Labs/README.md
+++ b/Labs/README.md
@@ -133,9 +133,7 @@ https://github.com/MPSU/APS/assets/17159587/4daac01f-dc9a-4ec8-8d3f-c5dc1ef97119
 
 ## 6. Основная память
 
-Недостатком реализации процессора из предыдущей лабораторной работы была его неспособность выполнять операции `LB`, `LBU`, `SB`, `LH`, `LHU`, `SH`. Отчасти это связано с ограничением реализованной ранее памяти (в этой памяти не было возможности обновить отдельный байт в ячейке памяти).
-
-Данная вспомогательная лабораторная работа позволяет реализовать память без этого ограничения.
+Процессор CYBERcobra 2000 использовал в качестве основного хранилища данных регистровый файл, однако на практике 31-го регистра недостаточно для выполнения сложных программ. Для этих целей используется **основная память**.
 
 ## 7. Тракт данных
 

From 0b181d5797b74db0c5793d4869ba2236961c396e Mon Sep 17 00:00:00 2001
From: Andrei Solodovnikov <VoultBoy@yandex.ru>
Date: Wed, 11 Sep 2024 19:52:56 +0300
Subject: [PATCH 07/14] =?UTF-8?q?=D0=9B=D0=A03.=20=D0=9E=D0=B1=D0=BD=D0=BE?=
 =?UTF-8?q?=D0=B2=D0=BB=D0=B5=D0=BD=D0=B8=D0=B5=20=D1=82=D0=B1?=
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Было добавлено покрытие сценария, когда порты на чтение работали только при we=0.
---
 .../lab_03.tb_register_file.sv                | 30 +++++++++++++++++++
 1 file changed, 30 insertions(+)

diff --git a/Labs/03. Register file and memory/lab_03.tb_register_file.sv b/Labs/03. Register file and memory/lab_03.tb_register_file.sv
index 125c67ec..b3c0f66b 100644
--- a/Labs/03. Register file and memory/lab_03.tb_register_file.sv	
+++ b/Labs/03. Register file and memory/lab_03.tb_register_file.sv	
@@ -148,6 +148,36 @@ module lab_03_tb_register_file();
           err_count = err_count + 1;
       end
     end
+    //Incorrect read check
+    @(posedge CLK);
+    WA <= 5'd1;
+    WD <= 1;
+    WE <= 1'b1;
+    @(posedge CLK);
+    WA <= 5'd2;
+    WD <= 2;
+    WE <= 1'b1;
+    @(posedge CLK);
+    WE  <= 1'b0;
+    RA1 <= 5'd1;
+    RA2 <= 5'd1;
+    @(posedge CLK);
+    WA  <= 5'd31;
+    WE  <= 1'b1;
+    WD  <= 0;
+    RA1 <= 5'd2;
+    RA2 <= 5'd2;
+    @(posedge CLK);
+    RD1ref = 2;
+    RD2ref = 2;
+    if(RD1ref !== RD1) begin
+        $display("time = %0t, address %h, RD1. Invalid data %h, correct data %h", $time, RA1, RD1, RD1ref);
+        err_count = err_count + 1;
+    end
+    if(RD2ref !== RD2) begin
+        $display("time = %0t, address %h, RD2. Invalid data %h, correct data %h", $time, RA2, RD2, RD2ref);
+        err_count = err_count + 1;
+    end
     $display("\nTest has been finished\nNumber of errors: %d\n", err_count);
     $finish();
     #5;

From 4fab0e9814aa13451271db5adbbbcf3410b87d7e Mon Sep 17 00:00:00 2001
From: Andrei Solodovnikov <VoultBoy@yandex.ru>
Date: Wed, 11 Sep 2024 19:55:14 +0300
Subject: [PATCH 08/14] =?UTF-8?q?=D0=9B=D0=A04.=20=D0=98=D1=81=D0=BF=D1=80?=
 =?UTF-8?q?=D0=B0=D0=B2=D0=BB=D0=B5=D0=BD=D0=B8=D0=B5=20=D0=BE=D0=BF=D0=B5?=
 =?UTF-8?q?=D1=87=D0=B0=D1=82=D0=BA=D0=B8=20=D0=B2=20=D1=82=D0=B1?=
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

---
 Labs/04. Primitive programmable device/lab_04.tb_cybercobra.sv | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/Labs/04. Primitive programmable device/lab_04.tb_cybercobra.sv b/Labs/04. Primitive programmable device/lab_04.tb_cybercobra.sv
index 4d142d01..74ed7e57 100644
--- a/Labs/04. Primitive programmable device/lab_04.tb_cybercobra.sv	
+++ b/Labs/04. Primitive programmable device/lab_04.tb_cybercobra.sv	
@@ -37,7 +37,7 @@ module lab_04_tb_CYBERcobra();
     $display("\n The test is over \n See the internal signals of the CYBERcobra on the waveform \n");
     $finish;
     #5;
-    $display("You're trying to run simulation that has finished. Aborting simulation.")
+    $display("You're trying to run simulation that has finished. Aborting simulation.");
     $fatal();
     end
 

From 829555690b6e8cc7bc8dda3edbd76fec234fede0 Mon Sep 17 00:00:00 2001
From: Andrei Solodovnikov <VoultBoy@yandex.ru>
Date: Wed, 11 Sep 2024 19:56:21 +0300
Subject: [PATCH 09/14] =?UTF-8?q?=D0=9B=D0=A05.=20=D0=98=D1=81=D0=BF=D1=80?=
 =?UTF-8?q?=D0=B0=D0=B2=D0=BB=D0=B5=D0=BD=D0=B8=D0=B5=20=D0=BE=D0=BF=D0=B5?=
 =?UTF-8?q?=D1=87=D0=B0=D1=82=D0=BA=D0=B8=20=D0=B2=20=D1=82=D0=B1?=
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

---
 Labs/05. Main decoder/lab_05.tb_decoder.sv | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/Labs/05. Main decoder/lab_05.tb_decoder.sv b/Labs/05. Main decoder/lab_05.tb_decoder.sv
index b7da3703..2019d0be 100644
--- a/Labs/05. Main decoder/lab_05.tb_decoder.sv	
+++ b/Labs/05. Main decoder/lab_05.tb_decoder.sv	
@@ -138,7 +138,7 @@ module lab_05_tb_decoder();
     $display("\nTest has been finished\nNumber of errors: %d\n", err_count);
     $finish();
     #5;
-    $display("You're trying to run simulation that has finished. Aborting simulation.")
+    $display("You're trying to run simulation that has finished. Aborting simulation.");
     $fatal();
   end
 

From 5ff39a8a462d9f5543b3beae75bd6b898574d368 Mon Sep 17 00:00:00 2001
From: Andrei Solodovnikov <VoultBoy@yandex.ru>
Date: Wed, 11 Sep 2024 19:57:11 +0300
Subject: [PATCH 10/14] =?UTF-8?q?=D0=9B=D0=A06.=20=D0=98=D1=81=D0=BF=D1=80?=
 =?UTF-8?q?=D0=B0=D0=B2=D0=BB=D0=B5=D0=BD=D0=B8=D0=B5=20=D0=BE=D0=BF=D0=B5?=
 =?UTF-8?q?=D1=87=D0=B0=D1=82=D0=BA=D0=B8=20=D0=B2=20=D1=82=D0=B1?=
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

---
 Labs/06. Main memory/lab_06.tb_data_mem.sv | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/Labs/06. Main memory/lab_06.tb_data_mem.sv b/Labs/06. Main memory/lab_06.tb_data_mem.sv
index 055cdb92..57e40cab 100644
--- a/Labs/06. Main memory/lab_06.tb_data_mem.sv	
+++ b/Labs/06. Main memory/lab_06.tb_data_mem.sv	
@@ -173,7 +173,7 @@ module lab_06_tb_data_mem;
     $display("\nTest has been finished\nNumber of errors: %d\n", err_cnt);
     $finish;
     #5;
-    $display("You're trying to run simulation that has finished. Aborting simulation.")
+    $display("You're trying to run simulation that has finished. Aborting simulation.");
     $fatal();
   end
 

From 84794a5d87593334a8637c42679e09061d9fe6d3 Mon Sep 17 00:00:00 2001
From: Andrei Solodovnikov <VoultBoy@yandex.ru>
Date: Wed, 11 Sep 2024 19:57:40 +0300
Subject: [PATCH 11/14] =?UTF-8?q?=D0=9B=D0=A07.=20=D0=98=D1=81=D0=BF=D1=80?=
 =?UTF-8?q?=D0=B0=D0=B2=D0=BB=D0=B5=D0=BD=D0=B8=D0=B5=20=D0=BE=D0=BF=D0=B5?=
 =?UTF-8?q?=D1=87=D0=B0=D1=82=D0=BA=D0=B8=20=D0=B2=20=D1=82=D0=B1?=
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

---
 Labs/07. Datapath/lab_07.tb_processor_system.sv | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/Labs/07. Datapath/lab_07.tb_processor_system.sv b/Labs/07. Datapath/lab_07.tb_processor_system.sv
index 1dc072d4..0233ae69 100644
--- a/Labs/07. Datapath/lab_07.tb_processor_system.sv	
+++ b/Labs/07. Datapath/lab_07.tb_processor_system.sv	
@@ -29,7 +29,7 @@ module lab_07_tb_processor_system();
       $display("\n The test is over \n See the internal signals of the module on the waveform \n");
       $finish;
       #5;
-      $display("You're trying to run simulation that has finished. Aborting simulation.")
+        $display("You're trying to run simulation that has finished. Aborting simulation.");
       $fatal();
   end
 

From ea36f923bd57fe367e2e47923191de3a6f1a48f0 Mon Sep 17 00:00:00 2001
From: Andrei Solodovnikov <VoultBoy@yandex.ru>
Date: Wed, 11 Sep 2024 19:58:01 +0300
Subject: [PATCH 12/14] =?UTF-8?q?=D0=9B=D0=A08.=20=D0=98=D1=81=D0=BF=D1=80?=
 =?UTF-8?q?=D0=B0=D0=B2=D0=BB=D0=B5=D0=BD=D0=B8=D0=B5=20=D0=BE=D0=BF=D0=B5?=
 =?UTF-8?q?=D1=87=D0=B0=D1=82=D0=BA=D0=B8=20=D0=B2=20=D1=82=D0=B1?=
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

---
 Labs/08. Load-store unit/lab_08.tb_lsu.sv | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/Labs/08. Load-store unit/lab_08.tb_lsu.sv b/Labs/08. Load-store unit/lab_08.tb_lsu.sv
index 1a819756..bb509363 100644
--- a/Labs/08. Load-store unit/lab_08.tb_lsu.sv	
+++ b/Labs/08. Load-store unit/lab_08.tb_lsu.sv	
@@ -64,7 +64,7 @@ initial begin
   $display("Simulation finished. Number of errors: %d", err_count);
   $finish();
   #5;
-  $display("You're trying to run simulation that has finished. Aborting simulation.")
+  $display("You're trying to run simulation that has finished. Aborting simulation.");
   $fatal();
 end
 

From 3bd2559291339ad19951325da945cba2d8d725db Mon Sep 17 00:00:00 2001
From: Andrei Solodovnikov <VoultBoy@yandex.ru>
Date: Wed, 11 Sep 2024 20:00:39 +0300
Subject: [PATCH 13/14] =?UTF-8?q?=D0=9B=D0=A07.=20=D0=9E=D0=B1=D0=BD=D0=BE?=
 =?UTF-8?q?=D0=B2=D0=BB=D0=B5=D0=BD=D0=B8=D0=B5=20nexys=5Friscv=5Funit.sv?=
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

---
 Labs/07. Datapath/board files/nexys_riscv_unit.sv | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/Labs/07. Datapath/board files/nexys_riscv_unit.sv b/Labs/07. Datapath/board files/nexys_riscv_unit.sv
index ea88c6a1..9d44bdf1 100644
--- a/Labs/07. Datapath/board files/nexys_riscv_unit.sv	
+++ b/Labs/07. Datapath/board files/nexys_riscv_unit.sv	
@@ -98,7 +98,7 @@ module nexys_riscv_unit(
     .O (bufg_clk     )
   );
 
-  riscv_unit unit(
+  processor_system unit(
     .clk_i (bufg_clk),
     .rst_i (!arstn_i)
   );

From 773568589f245390f5a8464a97400dba5fb6b977 Mon Sep 17 00:00:00 2001
From: Andrei Solodovnikov <VoultBoy@yandex.ru>
Date: Wed, 11 Sep 2024 23:18:52 +0300
Subject: [PATCH 14/14] Update lab_03.tb_register_file.sv

---
 Labs/03. Register file and memory/lab_03.tb_register_file.sv | 2 --
 1 file changed, 2 deletions(-)

diff --git a/Labs/03. Register file and memory/lab_03.tb_register_file.sv b/Labs/03. Register file and memory/lab_03.tb_register_file.sv
index b3c0f66b..d3be5eef 100644
--- a/Labs/03. Register file and memory/lab_03.tb_register_file.sv	
+++ b/Labs/03. Register file and memory/lab_03.tb_register_file.sv	
@@ -168,8 +168,6 @@ module lab_03_tb_register_file();
     RA1 <= 5'd2;
     RA2 <= 5'd2;
     @(posedge CLK);
-    RD1ref = 2;
-    RD2ref = 2;
     if(RD1ref !== RD1) begin
         $display("time = %0t, address %h, RD1. Invalid data %h, correct data %h", $time, RA1, RD1, RD1ref);
         err_count = err_count + 1;