diff --git a/.pic/Labs/lab_01_adder/fig_02.drawio.svg b/.pic/Labs/lab_01_adder/fig_02.drawio.svg
index d03e0d2..a646ba0 100644
--- a/.pic/Labs/lab_01_adder/fig_02.drawio.svg
+++ b/.pic/Labs/lab_01_adder/fig_02.drawio.svg
@@ -1,4 +1,4 @@
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\ No newline at end of file
diff --git a/.pic/Labs/lab_01_adder/fig_05.drawio.svg b/.pic/Labs/lab_01_adder/fig_05.drawio.svg
index 8e82d7e..c1a9294 100644
--- a/.pic/Labs/lab_01_adder/fig_05.drawio.svg
+++ b/.pic/Labs/lab_01_adder/fig_05.drawio.svg
@@ -1,4 +1,4 @@
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\ No newline at end of file
diff --git a/Labs/01. Adder/README.md b/Labs/01. Adder/README.md
index a47ddbf..9a72145 100644
--- a/Labs/01. Adder/README.md	
+++ b/Labs/01. Adder/README.md	
@@ -199,7 +199,7 @@ _Рисунок 5. Схема 4-битного сумматора._
 
 _Рисунок 6. Схема 4-битного сумматора, сгенерированная САПР Vivado._
 
-Несмотря на запутанность схемы, если присмотреться, вы увидите, как от шин A, B и S отходят линии к каждому из сумматоров, а бит переноса передаётся от предыдущего сумматора к следующему. Для передачи битов переноса от одного сумматора к другому, потребуется создать вспомогательные провода, которые можно сгруппировать в один [вектор](../../Basic%20Verilog%20structures/Modules.md#векторы).
+Несмотря на запутанность схемы, если присмотреться, вы увидите, как от шин A, B и S отходят линии к каждому из сумматоров, а бит переноса передаётся от предыдущего сумматора к следующему. Для передачи битов переноса от одного сумматора к другому, потребуется создать вспомогательные провода, которые можно сгруппировать в один [вектор](../../Basic%20Verilog%20structures/Modules.md#векторы) (см. сигналы c[0]-c[2] на _рис. 5_).
 
 ## Задание