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custom.cpp
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custom.cpp
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/*
* UAE - The Un*x Amiga Emulator
*
* Custom chip emulation
*
* Copyright 1995-2002 Bernd Schmidt
* Copyright 1995 Alessandro Bissacco
* Copyright 2000-2021 Toni Wilen
*/
#include "sysconfig.h"
#include "sysdeps.h"
#include <ctype.h>
#include <assert.h>
#include <math.h>
#include "options.h"
#include "uae.h"
#include "gensound.h"
#include "audio.h"
#include "sounddep/sound.h"
#include "events.h"
#include "memory.h"
#include "custom.h"
#include "newcpu.h"
#include "cia.h"
#include "disk.h"
#include "blitter.h"
#include "xwin.h"
#include "inputdevice.h"
#include "serial.h"
#include "autoconf.h"
#include "traps.h"
#include "gui.h"
#include "picasso96.h"
#include "drawing.h"
#include "savestate.h"
#include "ar.h"
#include "debug.h"
#include "akiko.h"
#if defined(ENFORCER)
#include "enforcer.h"
#endif
#include "threaddep/thread.h"
#include "luascript.h"
#include "devices.h"
#include "rommgr.h"
#include "specialmonitors.h"
#define FRAMEWAIT_MIN_MS 2
#define FRAMEWAIT_SPLIT 4
#define CYCLE_CONFLICT_LOGGING 0
#define SPEEDUP 1
#define CUSTOM_DEBUG 0
#define SPRITE_DEBUG 0
#define SPRITE_DEBUG_MINY 0
#define SPRITE_DEBUG_MAXY 0x30
#define MAX_SPRITES 8
#define AUTOSCALE_SPRITES 1
#define ALL_SUBPIXEL 1
#define RGA_COPPER_PIPELINE_DEPTH 2
#define RGA_SPRITE_PIPELINE_DEPTH 3
#define REFRESH_FIRST_HPOS 3
#define DMAL_FIRST_HPOS 11
#define SPR_FIRST_HPOS 25
#define COPPER_CYCLE_POLARITY 0
#define SPRBORDER 0
#define EXTRAWIDTH_BROADCAST 15
#define EXTRAHEIGHT_BROADCAST_TOP 0
#define EXTRAHEIGHT_BROADCAST_BOTTOM 0
#define EXTRAWIDTH_EXTREME 33
#define EXTRAHEIGHT_EXTREME 24
#define LORES_TO_SHRES_SHIFT 2
extern uae_u16 serper;
STATIC_INLINE bool nocustom (void)
{
struct amigadisplay *ad = &adisplays[0];
if (ad->picasso_on && currprefs.picasso96_nocustom)
return true;
return false;
}
static void uae_abort (const TCHAR *format,...)
{
static int nomore;
va_list parms;
TCHAR buffer[1000];
va_start (parms, format);
_vsntprintf (buffer, sizeof (buffer) / sizeof(TCHAR) - 1, format, parms );
va_end (parms);
if (nomore) {
write_log (_T("%s\n"), buffer);
return;
}
gui_message (buffer);
nomore = 1;
}
static uae_u32 total_skipped = 0;
extern int cpu_last_stop_vpos, cpu_stopped_lines;
static int cpu_sleepmode, cpu_sleepmode_cnt;
extern int vsync_activeheight, vsync_totalheight;
extern float vsync_vblank, vsync_hblank;
/* Events */
uae_u32 vsync_cycles;
static uae_u32 extra_cycle;
static int rpt_did_reset;
struct ev eventtab[ev_max];
struct ev2 eventtab2[ev2_max];
int vpos, vpos_prev, vposh;
static int hpos_hsync_extra;
static int vpos_count, vpos_count_diff;
int lof_store; // real bit in custom registers
int lof_display; // what display device thinks
static bool lof_lastline, lof_prev_lastline;
static int lol, lol_prev;
static int next_lineno;
static enum nln_how nextline_how;
static int lof_changed = 0, lof_changing = 0, interlace_changed = 0;
static int lof_changed_previous_field;
static int vposw_change;
static bool lof_lace;
static bool bplcon0_interlace_seen;
static int scandoubled_line;
static bool vsync_rendered, frame_rendered, frame_shown;
static int vsynctimeperline;
static int frameskiptime;
static bool genlockhtoggle;
static bool genlockvtoggle;
static bool graphicsbuffer_retry;
static int cia_hsync;
static bool toscr_scanline_complex_bplcon1, toscr_scanline_complex_bplcon1_off;
static int toscr_hend;
int display_reset;
#define LOF_TOGGLES_NEEDED 3
//#define NLACE_CNT_NEEDED 50
static int lof_togglecnt_lace, lof_togglecnt_nlace; //, nlace_cnt;
/* Stupid genlock-detection prevention hack.
* We should stop calling vsync_handler() and
* hstop_handler() completely but it is not
* worth the trouble..
*/
static int vpos_previous, hpos_previous;
static int vpos_lpen, hpos_lpen, hhpos_lpen, lightpen_triggered;
int lightpen_x[2], lightpen_y[2];
int lightpen_cx[2], lightpen_cy[2], lightpen_active, lightpen_enabled, lightpen_enabled2;
static uae_u32 sprtaba[256],sprtabb[256];
static uae_u32 sprite_ab_merge[256];
/* Tables for collision detection. */
static uae_u32 sprclx[16], clxmask[16];
/* T genlock bit in ECS Denise and AGA color registers */
static uae_u8 color_regs_genlock[256];
/*
* Hardware registers of all sorts.
*/
static uae_u16 cregs[256];
uae_u16 intena, intreq;
uae_u16 dmacon;
uae_u16 adkcon; /* used by audio code */
uae_u16 last_custom_value;
static bool dmacon_bpl;
static uae_u32 cop1lc, cop2lc, copcon;
/*
* horizontal defaults
* 0x00 0 HCB
* 0x01 1 HC1 (HSTART)
* 0x09 9 VR1
* 0x12 18 SHS (Horizontal sync start)
* 0x1a 26 VER1 PAL
* 0x1b 27 VER1 NTSC
* 0x23 35 RHS (Horizontal sync end)
* 0x73 115 VR2
* 0x84 132 CEN (HCENTER)
* 0x8c 140 VER2 PAL
* 0x8d 141 VER2 NTSC
* 0xe2 226 HC226 (short line, selected if LOL=1, NTSC only)
* 0xe3 227 HC227 (NTSC long line/PAL)
*
* vertical defaults
*
* PAL
*
* 0 SVB
* 2 VC2
* 3 VC3
* 5 VC5
* 7 VC7
* 8 VC8
* 25 RVB (Vertical blank end)
* 311 VC311 short field (Vertical blank start)
* 312 VC312 long field (Vertical blank start)
*
* Odd field:
*
* HSYNC SHS to RHS
* VSYNC VC2/CEN to VC5/SHS
* CSYNC HSYNC + if VSYNC active: SHS to VER1 and CEN to VER2
*
* Vertical blank = VC312 + HC1 to RVB + HC1
* Vertical equalization = SVB + VR1 to VC7 + VR2
*
* Even field:
*
* HSYNC SHS to RHS
* VSYNC VC3/SHS to VC5/CEN
* CSYNC HSYNC + if VSYNC active: SHS to VER1 and CEN to VER2
*
* Vertical blank = VC311 + HC1 to RVB + HC1
* Vertical equalization start = SVB + VR2 to VC8 + VR1
*
*
* NTSC
*
* 0 SVB
* 3 VC3
* 6 VC6
* 9 VC9
* 20 RVB (Vertical blank end)
* 261 VC261 short field (Vertical blank start)
* 262 VC262 long field (Vertical blank start)
*
* Odd field:
*
* HSYNC SHS to RHS
* VSYNC VC3/SHS to VC6/SHS
* CSYNC HSYNC + if VSYNC active: SHS to VER1 and CEN to VER2
*
* Vertical blank = VC262/HC1 to RVB/HC1
* Vertical equalization = SVB/VR1 to VC9/VR1
*
* Even field:
*
* HSYNC SHS to RHS
* VSYNC VC3/CEN to VC6/CEN
* CSYNC HSYNC + if VSYNC active: SHS to VER1 and CEN to VER2
*
* Vertical blank = VC261/HC1 to RVB/HC1
* Vertical equalization = SVB/VR2 to VC9/VR2
*
*/
/*
* Bitplane DMA enable logic OCS/ECS differences:
*
* OCS: DDFSTRT hard start limit flag is disabled when horizontal hard start position matches.
* It is enabled during active bitplane DMA's last cycle. (Ending due to either DDFSTOP or hardstop match).
* ECS: DDFTSTR/STOP hard limit work as documented.
* It is cleared when hard start matches and set when hard stop matches.
*
* OCS hard start limit bug: if line didn't have BPL DMA active, next line's BPL DMA can start earlier than start limit.
* (See music disk Ode to Ramon by Digital Force, bottom scroller "scanline affect" )
* This feature also prevents multiple DDFSTRT/STOP regions in same scanline. ECS/AGA does not have this limit.
*
* DDFSTRT match is ignored if DMACON BPLEN is not enabled. ECS/AGA allows it. Does not affect DDFSTOP.
* Switch DMACON BPLEN off, wait value to DDFSTRT that matches during current scanline,
* switch BPLEN on: if OCS, bitplane DMA won't start, ECS/AGA: bitplane DMA starts.
*
*
*
*
*
*
*/
int maxhpos = MAXHPOS_PAL;
int maxhpos_short = MAXHPOS_PAL;
int maxvpos = MAXVPOS_PAL;
int maxvpos_nom = MAXVPOS_PAL; // nominal value (same as maxvpos but "faked" maxvpos in fake 60hz modes)
int maxvpos_display = MAXVPOS_PAL; // value used for display size
static int maxhpos_display = AMIGA_WIDTH_MAX;
int maxvpos_display_vsync; // extra lines from top visible in bottom
static int vblank_extraline;
static int maxhposm1;
static bool maxhposeven, maxhposeven_prev;
static int hsyncendpos, hsyncstartpos;
int hsync_end_left_border;
static int hsyncstartpos_start, hsyncstartpos_start_cycles;
static int hsyncstartpos_start_hw;
int hsyncstartpos_hw;
int hsyncendpos_hw;
int hsynctotal;
static int maxvpos_total = 511;
int minfirstline = VBLANK_ENDLINE_PAL;
static int firstblankedline;
static int equ_vblank_endline = EQU_ENDLINE_PAL;
static bool equ_vblank_toggle = true;
float vblank_hz = VBLANK_HZ_PAL, fake_vblank_hz, vblank_hz_stored, vblank_hz_nom;
float hblank_hz;
static float vblank_hz_lof, vblank_hz_shf, vblank_hz_lace;
static int vblank_hz_mult, vblank_hz_state;
static struct chipset_refresh *stored_chipset_refresh;
int doublescan;
int programmedmode;
int syncbase;
static int fmode_saved, fmode;
uae_u16 beamcon0, new_beamcon0;
static uae_u16 beamcon0_saved;
static uae_u16 bplcon0_saved, bplcon1_saved, bplcon2_saved;
static uae_u16 bplcon3_saved, bplcon4_saved;
static int varsync_changed;
uae_u16 vtotal, htotal;
static int maxvpos_stored, maxhpos_stored;
uae_u16 hsstop, hsstop_detect, hsstrt;
static uae_u16 hbstop, hbstrt;
static uae_u16 vsstop, vsstrt;
static uae_u16 vbstop, vbstrt;
static uae_u16 hcenter, hcenter_v2, hcenter_v2_end;
static uae_u16 hbstop_v, hbstrt_v, hbstop_v2, hbstrt_v2, hbstrt_v2o, hbstop_v2o;
static int vsstrt_m, vsstop_m, vbstrt_m, vbstop_m;
static bool vb_state, vb_end_line;
static bool vs_state, vs_state_on, vs_state_hw;
static bool vb_end_next_line;
static int vb_start_line;
static bool ocs_blanked;
static uae_u16 sprhstrt, sprhstop, bplhstrt, bplhstop, hhpos, hhpos_hpos;
static uae_u16 sprhstrt_v, sprhstop_v, bplhstrt_v, bplhstop_v;
static int hhbpl, hhspr;
static int ciavsyncmode;
static int diw_hstrt, diw_hstop;
static int diw_hcounter;
static uae_u16 refptr;
static uae_u32 refptr_val;
#define HSYNCTIME (maxhpos * CYCLE_UNIT)
struct sprite {
uaecptr pt;
int xpos;
int vstart;
int vstop;
int dblscan; /* AGA SSCAN2 */
int armed;
int dmastate;
int dmacycle;
int width;
bool ecs_denise_hires;
uae_u16 ctl, pos;
#ifdef AGA
uae_u16 data[4], datb[4];
#else
uae_u16 data[1], datb[1];
#endif
};
static struct sprite spr[MAX_SPRITES];
static int plfstrt_sprite;
uaecptr sprite_0;
int sprite_0_width, sprite_0_height, sprite_0_doubled;
uae_u32 sprite_0_colors[4];
static uae_u8 magic_sprite_mask = 0xff;
static int hardwired_vbstop;
static int last_sprite_point, nr_armed;
static int sprite_width, sprres;
static int sprite_sprctlmask;
int sprite_buffer_res;
uae_u8 cycle_line_slot[MAX_CHIPSETSLOTS + RGA_PIPELINE_ADJUST];
uae_u16 cycle_line_pipe[MAX_CHIPSETSLOTS + RGA_PIPELINE_ADJUST];
static uae_s16 bpl1mod, bpl2mod, bpl1mod_prev, bpl2mod_prev;
static int bpl1mod_hpos, bpl2mod_hpos;
static uaecptr prevbpl[2][MAXVPOS][MAX_PLANES];
static uaecptr bplpt[MAX_PLANES], bplptx[MAX_PLANES];
static struct color_entry current_colors;
uae_u16 bplcon0;
static uae_u16 bplcon1, bplcon2, bplcon3, bplcon4;
static int bplcon0d, bplcon0d_old;
static bool bplcon0d_change;
static uae_u32 bplcon0_res, bplcon0_planes, bplcon0_planes_limit;
static int diwstrt, diwstop, diwhigh;
static int diwhigh_written;
static int ddfstrt, ddfstop, plfstop_prev;
static int ddfstrt_hpos, ddfstop_hpos;
static int line_cyclebased, diw_change;
static bool bpl_shifter;
#define SET_LINE_CYCLEBASED line_cyclebased = 1;
/* The display and data fetch windows */
enum diw_states
{
DIW_waiting_start, DIW_waiting_stop
};
static int plffirstline, plflastline;
int plffirstline_total, plflastline_total;
int vblank_firstline_hw;
static int autoscale_bordercolors;
static int plfstrt, plfstop;
static int sprite_minx;
static int first_bpl_vpos;
static int last_decide_line_hpos;
static int last_fetch_hpos, last_decide_sprite_hpos;
static int diwfirstword, diwlastword;
static int last_diwlastword;
static int hb_last_diwlastword;
static int last_hdiw;
static enum diw_states diwstate, hdiwstate;
static int diwstate_vpos;
static int bpl_hstart;
static bool exthblank, exthblank_state;
static int last_diw_hpos, last_diw_hpos2;
static int last_recorded_diw_hpos;
static int last_hblank_start;
int first_planes_vpos, last_planes_vpos;
static int first_bplcon0, first_bplcon0_old;
static int first_planes_vpos_old, last_planes_vpos_old;
int diwfirstword_total, diwlastword_total;
int ddffirstword_total, ddflastword_total;
static int diwfirstword_total_old, diwlastword_total_old;
static int ddffirstword_total_old, ddflastword_total_old;
bool vertical_changed, horizontal_changed;
int firstword_bplcon1;
static int last_copper_hpos;
static int copper_access;
/* Sprite collisions */
static unsigned int clxdat, clxcon, clxcon2, clxcon_bpl_enable, clxcon_bpl_match;
enum copper_states {
COP_stop,
COP_waitforever,
COP_read1,
COP_read2,
COP_bltwait,
COP_bltwait2,
COP_wait_in2,
COP_skip_in2,
COP_wait1,
COP_wait,
COP_skip,
COP_skip1,
COP_strobe_delay1,
COP_strobe_delay2,
COP_strobe_delay1x,
COP_strobe_delay2x,
COP_strobe_extra, // just to skip current cycle when CPU wrote to COPJMP
COP_start_delay
};
struct copper {
/* The current instruction words. */
uae_u16 ir[2];
enum copper_states state, state_prev;
/* Instruction pointer. */
uaecptr ip;
// following move does not enable COPRS
int ignore_next;
int vcmp, hcmp;
bool wakecond;
int strobe; /* COPJMP1 / COPJMP2 accessed */
int last_strobe;
int moveaddr, movedata, movedelay;
uaecptr moveptr;
uaecptr vblankip;
};
static struct copper cop_state;
static int copper_enabled_thisline;
/*
* Statistics
*/
unsigned long int frametime = 0, lastframetime = 0, timeframes = 0;
unsigned long hsync_counter = 0, vsync_counter = 0;
unsigned long int idletime;
int bogusframe;
/* Recording of custom chip register changes. */
static int current_change_set;
static struct sprite_entry sprite_entries[2][MAX_SPR_PIXELS / 16];
static struct color_change color_changes[2][MAX_REG_CHANGE];
struct decision line_decisions[2 * (MAXVPOS + MAXVPOS_WRAPLINES) + 1];
static struct draw_info line_drawinfo[2][2 * (MAXVPOS + MAXVPOS_WRAPLINES) + 1];
#define COLOR_TABLE_SIZE (MAXVPOS + MAXVPOS_WRAPLINES) * 2
static struct color_entry color_tables[2][COLOR_TABLE_SIZE];
static int next_sprite_entry = 0;
static int prev_next_sprite_entry;
static int next_sprite_forced = 1;
struct sprite_entry *curr_sprite_entries, *prev_sprite_entries;
struct color_change *curr_color_changes, *prev_color_changes;
struct draw_info *curr_drawinfo, *prev_drawinfo;
struct color_entry *curr_color_tables, *prev_color_tables;
static int next_color_change, last_color_change;
static int next_color_entry, remembered_color_entry;
static int color_src_match, color_dest_match, color_compare_result;
static uae_u32 thisline_changed;
#ifdef SMART_UPDATE
#define MARK_LINE_CHANGED do { thisline_changed = 1; } while (0)
#else
#define MARK_LINE_CHANGED do { ; } while (0)
#endif
static struct decision thisline_decision;
static int fetch_cycle, fetch_modulo_cycle;
static bool ddf_limit, ddf_limit_latch, ddfstrt_match, hwi_old;
static int ddf_stopping, ddf_enable_on;
static int bprun;
static int bprun_cycle;
static int bprun_pipeline_flush_delay;
static bool plane0, plane0p, plane0p_enabled, plane0p_forced, plane0_first_done;
static int last_bpl1dat_hpos;
static bool harddis_v, harddis_h;
static uae_u16 dmal_alloc_mask;
#define RGA_PIPELINE_OFFSET_BPL_WRITE 3
#define RGA_PIPELINE_OFFSET_COPPER 2
#define RGA_PIPELINE_OFFSET_SPRITE 3
#define RGA_PIPELINE_OFFSET_DMAL 2
struct custom_store custom_storage[256];
#define TOSCR_NBITS 16
#define TOSCR_NBITSHR 32
static int out_nbits, out_offs;
static uae_u32 todisplay[MAX_PLANES], todisplay2[MAX_PLANES];
static uae_u32 outword[MAX_PLANES];
static uae_u64 outword64[MAX_PLANES];
static uae_u16 fetched[MAX_PLANES];
static uae_u16 todisplay_fetched;
#ifdef AGA
static uae_u64 todisplay_aga[MAX_PLANES], todisplay2_aga[MAX_PLANES];
static bool todisplay2_lastbit[MAX_PLANES];
static uae_u64 fetched_aga[MAX_PLANES];
static uae_u32 fetched_aga_spr[MAX_PLANES];
#endif
/* Expansions from bplcon0/bplcon1. */
static int toscr_res2p, toscr_res_mult;
static int toscr_res, toscr_res_old;
static int toscr_res_pixels, toscr_res_pixels_shift;
static int toscr_res_pixels_hr, toscr_res_pixels_shift_hr, toscr_res_pixels_mask_hr;
static int toscr_nr_planes, toscr_nr_planes2, toscr_nr_planes3, toscr_nr_planes_agnus;
static bool toscr_nr_changed;
static int toscr_nr_planes_shifter, toscr_nr_planes_shifter_new;
static int fetchwidth;
static int toscr_delay_adjusted[2], toscr_delay_sh[2];
static bool shdelay_disabled;
static int delay_cycles, delay_cycles2;
static int delay_lastcycle[2], delay_hsynccycle;
static int hack_delay_shift;
static bool bplcon1_written;
static bool bplcon0_planes_changed;
static bool sprites_enabled_this_line, sprites_enabled_prev_line;
static int shifter_mask, toscr_delay_shifter[2];
static int out_subpix[2];
static bool speedup_first;
static void events_dmal(int);
static uae_u16 dmal, dmal_hpos;
static uae_u16 dmal_htotal_mask;
static bool dmal_ce;
/* The number of bits left from the last fetched words.
This is an optimization - conceptually, we have to make sure the result is
the same as if toscr is called in each clock cycle. However, to speed this
up, we accumulate display data; this variable keeps track of how much.
Thus, once we do call toscr_nbits (which happens at least every 16 bits),
we can do more work at once. */
static int toscr_nbits;
static int REGPARAM3 custom_wput_1(int, uaecptr, uae_u32, int) REGPARAM;
/*
* helper functions
*/
STATIC_INLINE int ecsshres(void)
{
return bplcon0_res == RES_SUPERHIRES && ecs_denise && !aga_mode;
}
STATIC_INLINE int nodraw(void)
{
struct amigadisplay *ad = &adisplays[0];
return !currprefs.cpu_memory_cycle_exact && ad->framecnt != 0;
}
STATIC_INLINE int diw_to_hpos(int diw)
{
diw /= 4;
diw += DDF_OFFSET;
diw /= 2;
return diw;
}
STATIC_INLINE int hpos_to_diw(int pos)
{
return ((pos + hpos_hsync_extra) * 2 - DDF_OFFSET) * 4;
}
static bool doflickerfix_possible(void)
{
return currprefs.gfx_vresolution && doublescan < 0 && vpos < MAXVPOS;
}
static bool doflickerfix_active(void)
{
return interlace_seen > 0 && doflickerfix_possible();
}
uae_u32 get_copper_address(int copno)
{
switch (copno) {
case 1: return cop1lc;
case 2: return cop2lc;
case 3: return cop_state.vblankip;
case -1: return cop_state.ip;
default: return 0;
}
}
void reset_frame_rate_hack(void)
{
if (currprefs.m68k_speed >= 0) {
return;
}
rpt_did_reset = 1;
events_reset_syncline();
vsyncmintime = read_processor_time() + vsynctimebase;
write_log(_T("Resetting frame rate hack\n"));
}
static void setclr(uae_u16 *p, uae_u16 val)
{
if (val & 0x8000) {
*p |= val & 0x7FFF;
} else {
*p &= ~val;
}
}
static int adjust_hr(int v)
{
if (currprefs.gfx_resolution >= RES_HIRES) {
if (currprefs.chipset_hr) {
v &= ~(3 >> currprefs.gfx_resolution);
} else {
v &= ~3;
}
} else {
v &= ~1;
}
return v;
}
static int adjust_hr2(int v)
{
if (currprefs.gfx_resolution >= RES_HIRES) {
if (currprefs.chipset_hr) {
v &= ~(1 >> currprefs.gfx_resolution);
} else {
v &= ~1;
}
}
return v;
}
static void alloc_cycle(int hpos, int type)
{
#ifdef CPUEMU_13
#if CYCLE_CONFLICT_LOGGING
if (cycle_line_slot[hpos] && cycle_line_slot[hpos] != type) {
write_log(_T("alloc cycle conflict %d: %02x <- %02x\n"), hpos, type, cycle_line_slot[hpos]);
}
#endif
cycle_line_slot[hpos] = type;
#endif
}
static void alloc_cycle_maybe(int hpos, int type)
{
if ((cycle_line_slot[hpos] & CYCLE_MASK) == 0) {
alloc_cycle(hpos, type);
}
}
void alloc_cycle_ext(int hpos, int type)
{
alloc_cycle(hpos, type);
}
void alloc_cycle_blitter(int hpos, uaecptr *ptr, int chnum)
{
if (cycle_line_slot[hpos] & CYCLE_COPPER_SPECIAL) {
if ((currprefs.cs_hacks & 1) && currprefs.cpu_model == 68000) {
uaecptr srcptr = cop_state.strobe == 1 ? cop1lc : cop2lc;
//if (currprefs.cpu_model == 68000 && currprefs.cpu_cycle_exact && currprefs.blitter_cycle_exact) {
// batman group / batman vuelve triggers this incorrectly. More testing needed.
*ptr = srcptr;
//activate_debugger();
}
}
alloc_cycle(hpos, CYCLE_BLITTER);
}
static int expand_sprres(uae_u16 con0, uae_u16 con3)
{
int res;
switch ((con3 >> 6) & 3)
{
default:
res = RES_LORES;
break;
#ifdef ECS_DENISE
case 0: /* ECS defaults (LORES,HIRES=LORES sprite,SHRES=HIRES sprite) */
if (ecs_denise && GET_RES_DENISE(con0) == RES_SUPERHIRES)
res = RES_HIRES;
else
res = RES_LORES;
break;
#endif
#ifdef AGA
case 1:
res = RES_LORES;
break;
case 2:
res = RES_HIRES;
break;
case 3:
res = RES_SUPERHIRES;
break;
#endif
}
return res;
}
STATIC_INLINE uae_u8 *pfield_xlateptr(uaecptr plpt, int bytecount)
{
if (!chipmem_check_indirect(plpt, bytecount)) {
static int count = 0;
if (!count) {
count++;
write_log(_T("Warning: Bad playfield pointer %08x\n"), plpt);
}
return NULL;
}
return chipmem_xlate_indirect(plpt);
}
static void docols(struct color_entry *colentry)
{
#ifdef AGA
if (aga_mode) {
for (int i = 0; i < 256; i++) {
int v = color_reg_get(colentry, i);
if (v < 0 || v > 16777215)
continue;
colentry->acolors[i] = getxcolor(v);
}
} else {
#endif
for (int i = 0; i < 32; i++) {
int v = color_reg_get(colentry, i);
if (v < 0 || v > 4095)
continue;
colentry->acolors[i] = getxcolor(v);
}
#ifdef AGA
}
#endif
}
static void remember_ctable(void)
{
/* This can happen when program crashes very badly */
if (next_color_entry >= COLOR_TABLE_SIZE) {
return;
}
if (remembered_color_entry < 0) {
/* The colors changed since we last recorded a color map. Record a
* new one. */
color_reg_cpy(curr_color_tables + next_color_entry, ¤t_colors);
remembered_color_entry = next_color_entry++;
}
thisline_decision.ctable = remembered_color_entry;
if (color_src_match < 0 || color_dest_match != remembered_color_entry
|| line_decisions[next_lineno].ctable != color_src_match)
{
/* The remembered comparison didn't help us - need to compare again. */
int oldctable = line_decisions[next_lineno].ctable;
int changed = 0;
if (oldctable < 0) {
changed = 1;
color_src_match = color_dest_match = -1;
} else {
color_compare_result = color_reg_cmp(&prev_color_tables[oldctable], ¤t_colors) != 0;
if (color_compare_result) {
changed = 1;
}
color_src_match = oldctable;
color_dest_match = remembered_color_entry;
}
thisline_changed |= changed;
} else {
/* We know the result of the comparison */
if (color_compare_result) {
thisline_changed = 1;
}
}
}
static void remember_ctable_for_border(void)
{
remember_ctable();
}
// This does not need start line check because only OCS Denise modes use this.
static int get_equ_vblank_endline(void)
{
return equ_vblank_endline + (equ_vblank_toggle ? (lof_store ? 1 : 0) : 0);
}
static int output_res(int res)
{
if (currprefs.chipset_hr && res < currprefs.gfx_resolution) {
return currprefs.gfx_resolution;
}
return res;
}
static void reset_bpl_vars()
{
out_subpix[0] = 0;
out_subpix[1] = 0;
out_nbits = 0;
out_offs = 0;
toscr_nbits = 0;
thisline_decision.bplres = output_res(bplcon0_res);
}
STATIC_INLINE bool line_hidden(void)
{
return vpos >= maxvpos_display_vsync && vpos < minfirstline - 1;
}
// hblank start = enable border (bitplane not visible until next BPL1DAT)..
static void hblank_reset(int hblankpos)
{
if (thisline_decision.plfleft < 0) {
return;
}
// border re-enable takes 1 lores pixel
hb_last_diwlastword = hblankpos + 4;
SET_LINE_CYCLEBASED;
}
static void record_color_change2(int hpos, int regno, uae_u32 value)
{
color_change *cc;
if (scandoubled_line || line_hidden() || nocustom()) {
return;
}
int pos = hpos < 0 ? -hpos : hpos_to_diw(hpos);
// AGA has extra hires pixel delay in color changes
if ((regno < RECORDED_REGISTER_CHANGE_OFFSET || regno == RECORDED_REGISTER_CHANGE_OFFSET + 0x10c) && aga_mode) {
if (currprefs.chipset_hr) {
pos += 2;
}
if (regno == RECORDED_REGISTER_CHANGE_OFFSET + 0x10c) {
// BPLCON4:
// Bitplane XOR change: 2 hires pixel delay
// Sprite bank change: 1 hires pixel delay
if (!currprefs.chipset_hr) {
pos += 2;
}
if (value & 0xff00) {
thisline_decision.xor_seen = true;
}
pos += 2;
if ((value & 0x00ff) != (bplcon4 & 0x00ff)) {
// Sprite bank delay
cc = &curr_color_changes[next_color_change];
cc->linepos = pos;
cc->regno = regno | 1;
cc->value = value;
next_color_change++;
}
pos += 2;
}
}
// HCENTER blanking
if (hcenter_v2 && vs_state_on && vpos < maxvpos_display_vsync && lof_display) {
int chpos = pos;
if (hcenter_v2_end == 0xffff && hcenter_v2 < chpos && hcenter_v2 >= last_recorded_diw_hpos) {
cc = &curr_color_changes[next_color_change];
cc->linepos = hcenter_v2;
cc->regno = RECORDED_REGISTER_CHANGE_OFFSET + 0x200;
cc->value = 1;
next_color_change++;
cc[1].regno = -1;
last_recorded_diw_hpos = cc->linepos;
hcenter_v2_end = hcenter_v2;
hcenter_v2_end += ((beamcon0 & 0x20) ? 8 : 9) << CCK_SHRES_SHIFT;
if (hcenter_v2_end >= maxhpos << CCK_SHRES_SHIFT) {
hcenter_v2_end -= maxhpos << CCK_SHRES_SHIFT;
}
if (debug_dma) {
record_dma_event(DMA_EVENT_HBS, diw_to_hpos(cc->linepos), vpos);
}
}
if (!exthblank_state && hcenter_v2_end < chpos && hcenter_v2_end >= last_recorded_diw_hpos) {
cc = &curr_color_changes[next_color_change];
cc->linepos = hcenter_v2_end;
cc->regno = RECORDED_REGISTER_CHANGE_OFFSET + 0x200;
cc->value = 0;
next_color_change++;
cc[1].regno = -1;
last_recorded_diw_hpos = cc->linepos;
hcenter_v2_end = 0xffff;
if (debug_dma) {
record_dma_event(DMA_EVENT_HBE, diw_to_hpos(cc->linepos), vpos);
}
}
}
if (exthblank) {
int chpos = pos;
// inject programmed hblank start and end in color changes
if (hbstrt_v2 < hbstop_v2) {
if (hbstrt_v2 < chpos && hbstrt_v2 >= last_recorded_diw_hpos) {
cc = &curr_color_changes[next_color_change];
cc->linepos = hbstrt_v2;
cc->regno = RECORDED_REGISTER_CHANGE_OFFSET + 0x200;
cc->value = 1;
next_color_change++;
cc[1].regno = -1;
hblank_reset(hbstrt_v2);
exthblank_state = true;
last_recorded_diw_hpos = cc->linepos;
last_hblank_start = cc->linepos;
if (debug_dma) {
record_dma_event(DMA_EVENT_HBS, diw_to_hpos(cc->linepos), vpos);
}
}
if (hbstop_v2 < chpos && hbstop_v2 >= last_recorded_diw_hpos) {
// do_color_changes() HBLANK workaround
if (next_color_change == last_color_change && exthblank_state) {
cc = &curr_color_changes[next_color_change];
cc->linepos = 0;
cc->regno = RECORDED_REGISTER_CHANGE_OFFSET + 0x200;
cc->value = 1;
next_color_change++;
}
cc = &curr_color_changes[next_color_change];
cc->linepos = hbstop_v2;
cc->regno = RECORDED_REGISTER_CHANGE_OFFSET + 0x200;
cc->value = 0;
next_color_change++;