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a2091.cpp
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a2091.cpp
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/*
* UAE - The Un*x Amiga Emulator
*
* A590/A2091/A3000/CDTV SCSI expansion (DMAC/SuperDMAC + WD33C93) emulation
* Includes A590 + XT drive emulation.
* GVP Series I and II
* A2090 SCSI and ST-506
*
* Copyright 2007-2015 Toni Wilen
*
*/
#define GVP_S1_DEBUG_IO 0
#define GVP_S2_DEBUG_IO 0
#define A2091_DEBUG 0
#define A2091_DEBUG_IO 0
#define XT_DEBUG 0
#define A3000_DEBUG 0
#define A3000_DEBUG_IO 0
#define COMSPEC_DEBUG 0
#define WD33C93_DEBUG 0
#define WD33C93_DEBUG_PIO 0
#include "sysconfig.h"
#include "sysdeps.h"
#include "options.h"
#include "uae.h"
#include "memory.h"
#include "rommgr.h"
#include "custom.h"
#include "newcpu.h"
#include "debug.h"
#include "scsi.h"
#include "threaddep/thread.h"
#include "a2091.h"
#include "blkdev.h"
#include "gui.h"
#include "zfile.h"
#include "filesys.h"
#include "autoconf.h"
#include "cdtv.h"
#include "savestate.h"
#include "cpuboard.h"
#include "rtc.h"
#include "devices.h"
#define DMAC_8727_ROM_VECTOR 0x8000
#define CDMAC_ROM_VECTOR 0x2000
#define CDMAC_ROM_OFFSET 0x2000
#define GVP_ROM_OFFSET 0x8000
#define GVP_SERIES_I_RAM_OFFSET_1 0x04000
#define GVP_SERIES_I_RAM_OFFSET_2 0x04000
#define GVP_SERIES_I_RAM_OFFSET_3 0x10000
#define GVP_SERIES_I_RAM_MASK_1 (4096 - 1)
#define GVP_SERIES_I_RAM_MASK_2 (16384 - 1)
#define GVP_SERIES_I_RAM_MASK_3 (16384 - 1)
/* SuperDMAC CNTR bits. */
#define SCNTR_TCEN (1<<5)
#define SCNTR_PREST (1<<4)
#define SCNTR_PDMD (1<<3)
#define SCNTR_INTEN (1<<2)
#define SCNTR_DDIR (1<<1)
#define SCNTR_IO_DX (1<<0)
/* DMAC CNTR bits. */
#define CNTR_TCEN (1<<7)
#define CNTR_PREST (1<<6)
#define CNTR_PDMD (1<<5)
#define CNTR_INTEN (1<<4)
#define CNTR_DDIR (1<<3)
/* ISTR bits. */
#define ISTR_INT_F (1<<7) /* Interrupt Follow */
#define ISTR_INTS (1<<6) /* SCSI or XT Peripheral Interrupt */
#define ISTR_E_INT (1<<5) /* End-Of-Process Interrupt */
#define ISTR_INT_P (1<<4) /* Interrupt Pending */
#define ISTR_UE_INT (1<<3) /* Under-Run FIFO Error Interrupt */
#define ISTR_OE_INT (1<<2) /* Over-Run FIFO Error Interrupt */
#define ISTR_FF_FLG (1<<1) /* FIFO-Full Flag */
#define ISTR_FE_FLG (1<<0) /* FIFO-Empty Flag */
/* GVP models */
#define GVP_GFORCE_040 0x20
#define GVP_GFORCE_040_SCSI 0x30
#define GVP_A1291 0x46
#define GVP_A1291_SCSI 0x47
#define GVP_COMBO_R4 0x60
#define GVP_COMBO_R4_SCSI 0x70
#define GVP_IO_EXTENDER 0x98
#define GVP_GFORCE_030 0xa0
#define GVP_GFORCE_030_SCSI 0xb0
#define GVP_A530 0xc0
#define GVP_A530_SCSI 0xd0
#define GVP_COMBO_R3 0xe0
#define GVP_COMBO_R3_SCSI 0xf0
#define GVP_SERIESII 0xf8
/* wd register names */
#define WD_OWN_ID 0x00
#define WD_CONTROL 0x01
#define WD_TIMEOUT_PERIOD 0x02
#define WD_CDB_1 0x03
#define WD_T_SECTORS 0x03
#define WD_CDB_2 0x04
#define WD_T_HEADS 0x04
#define WD_CDB_3 0x05
#define WD_T_CYLS_0 0x05
#define WD_CDB_4 0x06
#define WD_T_CYLS_1 0x06
#define WD_CDB_5 0x07
#define WD_L_ADDR_0 0x07
#define WD_CDB_6 0x08
#define WD_L_ADDR_1 0x08
#define WD_CDB_7 0x09
#define WD_L_ADDR_2 0x09
#define WD_CDB_8 0x0a
#define WD_L_ADDR_3 0x0a
#define WD_CDB_9 0x0b
#define WD_SECTOR 0x0b
#define WD_CDB_10 0x0c
#define WD_HEAD 0x0c
#define WD_CDB_11 0x0d
#define WD_CYL_0 0x0d
#define WD_CDB_12 0x0e
#define WD_CYL_1 0x0e
#define WD_TARGET_LUN 0x0f
#define WD_COMMAND_PHASE 0x10
#define WD_SYNCHRONOUS_TRANSFER 0x11
#define WD_TRANSFER_COUNT_MSB 0x12
#define WD_TRANSFER_COUNT 0x13
#define WD_TRANSFER_COUNT_LSB 0x14
#define WD_DESTINATION_ID 0x15
#define WD_SOURCE_ID 0x16
#define WD_SCSI_STATUS 0x17
#define WD_COMMAND 0x18
#define WD_DATA 0x19
#define WD_QUEUE_TAG 0x1a
#define WD_AUXILIARY_STATUS 0x1f
/* WD commands */
#define WD_CMD_RESET 0x00
#define WD_CMD_ABORT 0x01
#define WD_CMD_ASSERT_ATN 0x02
#define WD_CMD_NEGATE_ACK 0x03
#define WD_CMD_DISCONNECT 0x04
#define WD_CMD_RESELECT 0x05
#define WD_CMD_SEL_ATN 0x06
#define WD_CMD_SEL 0x07
#define WD_CMD_SEL_ATN_XFER 0x08
#define WD_CMD_SEL_XFER 0x09
#define WD_CMD_RESEL_RECEIVE 0x0a
#define WD_CMD_RESEL_SEND 0x0b
#define WD_CMD_WAIT_SEL_RECEIVE 0x0c
#define WD_CMD_TRANS_ADDR 0x18
#define WD_CMD_TRANS_INFO 0x20
#define WD_CMD_TRANSFER_PAD 0x21
#define WD_CMD_SBT_MODE 0x80
/* paused or aborted interrupts */
#define CSR_MSGIN 0x20
#define CSR_SDP 0x21
#define CSR_SEL_ABORT 0x22
#define CSR_RESEL_ABORT 0x25
#define CSR_RESEL_ABORT_AM 0x27
#define CSR_ABORT 0x28
/* successful completion interrupts */
#define CSR_RESELECT 0x10
#define CSR_SELECT 0x11
#define CSR_TRANS_ADDR 0x15
#define CSR_SEL_XFER_DONE 0x16
#define CSR_XFER_DONE 0x18
/* terminated interrupts */
#define CSR_INVALID 0x40
#define CSR_UNEXP_DISC 0x41
#define CSR_TIMEOUT 0x42
#define CSR_PARITY 0x43
#define CSR_PARITY_ATN 0x44
#define CSR_BAD_STATUS 0x45
#define CSR_UNEXP 0x48
/* service required interrupts */
#define CSR_RESEL 0x80
#define CSR_RESEL_AM 0x81
#define CSR_ATN_ASSERT 0x84
#define CSR_DISC 0x85
#define CSR_SRV_REQ 0x88
/* SCSI Bus Phases */
#define PHS_DATA_OUT 0x00
#define PHS_DATA_IN 0x01
#define PHS_COMMAND 0x02
#define PHS_STATUS 0x03
#define PHS_MESS_OUT 0x06
#define PHS_MESS_IN 0x07
/* Auxialiry status */
#define ASR_INT 0x80 /* Interrupt pending */
#define ASR_LCI 0x40 /* Last command ignored */
#define ASR_BSY 0x20 /* Busy, only cmd/data/asr readable */
#define ASR_CIP 0x10 /* Busy, cmd unavail also */
#define ASR_xxx 0x0c
#define ASR_PE 0x02 /* Parity error (even) */
#define ASR_DBR 0x01 /* Data Buffer Ready */
/* Status */
#define CSR_CAUSE 0xf0
#define CSR_RESET 0x00 /* chip was reset */
#define CSR_CMD_DONE 0x10 /* cmd completed */
#define CSR_CMD_STOPPED 0x20 /* interrupted or abrted*/
#define CSR_CMD_ERR 0x40 /* end with error */
#define CSR_BUS_SERVICE 0x80 /* REQ pending on the bus */
/* Control */
#define CTL_DMA 0x80 /* Single byte dma */
#define CTL_DBA_DMA 0x40 /* direct buffer access (bus master) */
#define CTL_BURST_DMA 0x20 /* continuous mode (8237) */
#define CTL_NO_DMA 0x00 /* Programmed I/O */
#define CTL_HHP 0x10 /* Halt on host parity error */
#define CTL_EDI 0x08 /* Ending disconnect interrupt */
#define CTL_IDI 0x04 /* Intermediate disconnect interrupt*/
#define CTL_HA 0x02 /* Halt on ATN */
#define CTL_HSP 0x01 /* Halt on SCSI parity error */
/* SCSI Messages */
#define MSG_COMMAND_COMPLETE 0x00
#define MSG_SAVE_DATA_POINTER 0x02
#define MSG_RESTORE_DATA_POINTERS 0x03
#define MSG_NOP 0x08
#define MSG_IDENTIFY 0x80
/* XT hard disk controller registers */
#define XD_DATA 0x00 /* data RW register */
#define XD_RESET 0x01 /* reset WO register */
#define XD_STATUS 0x01 /* status RO register */
#define XD_SELECT 0x02 /* select WO register */
#define XD_JUMPER 0x02 /* jumper RO register */
#define XD_CONTROL 0x03 /* DMAE/INTE WO register */
#define XD_RESERVED 0x03 /* reserved */
/* XT hard disk controller commands (incomplete list) */
#define XT_CMD_TESTREADY 0x00 /* test drive ready */
#define XT_CMD_RECALIBRATE 0x01 /* recalibrate drive */
#define XT_CMD_SENSE 0x03 /* request sense */
#define XT_CMD_FORMATDRV 0x04 /* format drive */
#define XT_CMD_VERIFY 0x05 /* read verify */
#define XT_CMD_FORMATTRK 0x06 /* format track */
#define XT_CMD_FORMATBAD 0x07 /* format bad track */
#define XT_CMD_READ 0x08 /* read */
#define XT_CMD_WRITE 0x0A /* write */
#define XT_CMD_SEEK 0x0B /* seek */
/* Controller specific commands */
#define XT_CMD_DTCSETPARAM 0x0C /* set drive parameters (DTC 5150X & CX only?) */
/* Bits for command status byte */
#define XT_CSB_ERROR 0x02 /* error */
#define XT_CSB_LUN 0x20 /* logical Unit Number */
/* XT hard disk controller status bits */
#define XT_STAT_READY 0x01 /* controller is ready */
#define XT_STAT_INPUT 0x02 /* data flowing from controller to host */
#define XT_STAT_COMMAND 0x04 /* controller in command phase */
#define XT_STAT_SELECT 0x08 /* controller is selected */
#define XT_STAT_REQUEST 0x10 /* controller requesting data */
#define XT_STAT_INTERRUPT 0x20 /* controller requesting interrupt */
/* XT hard disk controller control bits */
#define XT_INT 0x02 /* Interrupt enable */
#define XT_DMA_MODE 0x01 /* DMA enable */
#define XT_UNIT 8
#define XT_SECTORS 17 /* hardwired */
#define XT506_UNIT0 8
#define XT506_UNIT1 9
#define MAX_SCSI_UNITS (8 + 2)
static struct wd_state *wd_a2091[MAX_DUPLICATE_EXPANSION_BOARDS];
static struct wd_state *wd_a2090[MAX_DUPLICATE_EXPANSION_BOARDS];
static struct wd_state *wd_a3000;
static struct wd_state *wd_gvps1[MAX_DUPLICATE_EXPANSION_BOARDS];
static struct wd_state *wd_gvps2[MAX_DUPLICATE_EXPANSION_BOARDS];
static struct wd_state *wd_gvps2accel;
static struct wd_state *wd_comspec[MAX_DUPLICATE_EXPANSION_BOARDS];
struct wd_state *wd_cdtv;
static bool configured;
static uae_u8 gvp_accelerator_bank;
static struct wd_state *scsi_units[MAX_SCSI_UNITS + 1];
static void wd_init(void);
static void wd_addreset(void);
static void freencrunit(struct wd_state *wd)
{
if (!wd)
return;
for (int i = 0; i < MAX_SCSI_UNITS; i++) {
if (scsi_units[i] == wd) {
scsi_units[i] = NULL;
}
}
scsi_freenative(wd->scsis, MAX_SCSI_UNITS);
if (wd->rom >= wd->bank.baseaddr && wd->rom < wd->bank.baseaddr + wd->bank.allocated_size)
free_expansion_bank(&wd->bank);
else
xfree (wd->rom);
if (wd->rom2 >= wd->bank2.baseaddr && wd->rom2 < wd->bank2.baseaddr + wd->bank2.allocated_size)
mapped_free(&wd->bank2);
else
xfree (wd->rom2);
xfree(wd->userdata);
wd->rom = NULL;
if (wd->self_ptr)
*wd->self_ptr = NULL;
xfree(wd);
}
static struct wd_state *allocscsi(struct wd_state **wd, struct romconfig *rc, int ch)
{
struct wd_state *scsi;
if (ch < 0) {
freencrunit(*wd);
*wd = NULL;
}
configured = true;
if ((*wd) == NULL) {
scsi = xcalloc(struct wd_state, 1);
for (int i = 0; i < MAX_SCSI_UNITS; i++) {
if (scsi_units[i] == NULL) {
scsi_units[i] = scsi;
if (rc)
rc->unitdata = scsi;
scsi->rc = rc;
scsi->self_ptr = wd;
scsi->id = i;
*wd = scsi;
return scsi;
}
}
}
return *wd;
}
static struct wd_state *getscsi(struct romconfig *rc)
{
if (rc->unitdata)
return (struct wd_state*)rc->unitdata;
return NULL;
}
static struct wd_state *getscsiboard(uaecptr addr)
{
for (int i = 0; scsi_units[i]; i++) {
if (!scsi_units[i]->baseaddress)
return scsi_units[i];
if ((addr & ~scsi_units[i]->board_mask) == scsi_units[i]->baseaddress)
return scsi_units[i];
if (scsi_units[i]->baseaddress2 && (addr & ~scsi_units[i]->board_mask) == scsi_units[i]->baseaddress2)
return scsi_units[i];
}
return NULL;
}
static void reset_dmac(struct wd_state *wd)
{
switch (wd->dmac_type)
{
case GVP_DMAC_S1:
case GVP_DMAC_S2:
wd->gdmac.cntr = 0;
wd->gdmac.dma_on = 0;
break;
case COMMODORE_SDMAC:
case COMMODORE_DMAC:
case COMMODORE_8727:
wd->cdmac.dmac_dma = 0;
wd->cdmac.dmac_istr = 0;
wd->cdmac.dmac_cntr = 0;
break;
}
}
static int isirq(struct wd_state *wd)
{
if (!wd->enabled)
return false;
switch (wd->dmac_type)
{
case GVP_DMAC_S1:
if ((wd->gdmac.cntr & 0x80) && (wd->wc.auxstatus & ASR_INT))
return 1;
break;
case GVP_DMAC_S2:
if (wd->wc.auxstatus & ASR_INT)
wd->gdmac.cntr |= 2;
if ((wd->gdmac.cntr & (2 | 8)) == (2 | 8))
return 1;
break;
case COMMODORE_SDMAC:
if (wd->wc.auxstatus & ASR_INT)
wd->cdmac.dmac_istr |= ISTR_INTS | ISTR_INT_F;
else
wd->cdmac.dmac_istr &= ~ISTR_INT_F;
if ((wd->cdmac.dmac_cntr & SCNTR_INTEN) && (wd->cdmac.dmac_istr & (ISTR_INTS | ISTR_E_INT)))
return 1;
break;
case COMMODORE_DMAC:
if (wd->cdmac.xt_irq)
wd->cdmac.dmac_istr |= ISTR_INTS | ISTR_INT_F;
else if (wd->wc.auxstatus & ASR_INT)
wd->cdmac.dmac_istr |= ISTR_INTS | ISTR_INT_F;
else
wd->cdmac.dmac_istr &= ~ISTR_INT_F;
if ((wd->cdmac.dmac_cntr & CNTR_INTEN) && (wd->cdmac.dmac_istr & (ISTR_INTS | ISTR_E_INT)))
return 1;
break;
case COMMODORE_8727:
if (wd->cdmac.xt_irq)
wd->cdmac.dmac_istr |= ISTR_INTS;
if (wd->wc.auxstatus & ASR_INT)
wd->cdmac.dmac_istr |= ISTR_INTS;
if ((wd->cdmac.dmac_cntr & CNTR_INTEN) && (wd->cdmac.dmac_istr & ISTR_INTS))
return 1;
break;
case COMSPEC_CHIP:
{
int irq = 0;
if ((wd->comspec.status & 0x20) && (wd->wc.auxstatus & ASR_INT))
irq |= 2;
if ((wd->comspec.status & 0x08) && wd->wc.wd_data_avail)
irq |= 1;
return irq;
}
break;
}
return 0;
}
static void set_dma_done(struct wd_state *wds)
{
switch (wds->dmac_type)
{
case GVP_DMAC_S1:
case GVP_DMAC_S2:
wds->gdmac.dma_on = -1;
break;
case COMMODORE_SDMAC:
case COMMODORE_DMAC:
case COMMODORE_8727:
wds->cdmac.dmac_dma = -1;
break;
}
}
static bool is_dma_enabled(struct wd_state *wds)
{
switch (wds->dmac_type)
{
case GVP_DMAC_S1:
return true;
case GVP_DMAC_S2:
return wds->gdmac.dma_on > 0;
case COMMODORE_SDMAC:
case COMMODORE_DMAC:
case COMMODORE_8727:
return wds->cdmac.dmac_dma > 0;
}
return false;
}
static void rethink_a2091(void)
{
if (!configured)
return;
for (int i = 0; i < MAX_SCSI_UNITS; i++) {
if (scsi_units[i]) {
int irq = isirq(scsi_units[i]);
if (irq & 1)
safe_interrupt_set(IRQ_SOURCE_WD, i, false);
if (irq & 2)
safe_interrupt_set(IRQ_SOURCE_WD, i, true);
#if DEBUG > 2 || A3000_DEBUG > 2
write_log (_T("Interrupt_RETHINK:%d\n"), irq);
#endif
}
}
}
static void dmac_scsi_int(struct wd_state *wd)
{
if (!wd->enabled)
return;
if (!(wd->wc.auxstatus & ASR_INT))
return;
devices_rethink_all(rethink_a2091);
}
static void dmac_a2091_xt_int(struct wd_state *wd)
{
if (!wd->enabled)
return;
wd->cdmac.xt_irq = true;
devices_rethink_all(rethink_a2091);
}
void scsi_dmac_a2091_start_dma (struct wd_state *wd)
{
#if A3000_DEBUG > 0 || A2091_DEBUG > 0
write_log (_T("DMAC DMA started, ADDR=%08X, LEN=%08X words\n"), wd->cdmac.dmac_acr, wd->cdmac.dmac_wtc);
#endif
wd->cdmac.dmac_dma = 1;
}
void scsi_dmac_a2091_stop_dma (struct wd_state *wd)
{
wd->cdmac.dmac_dma = 0;
wd->cdmac.dmac_istr &= ~ISTR_E_INT;
}
static void dmac_reset (struct wd_state *wd)
{
#if WD33C93_DEBUG > 0
if (wd->dmac_type == COMMODORE_SDMAC)
write_log (_T("A3000 %s SCSI reset\n"), WD33C93);
else if (wd->dmac_type == COMMODORE_DMAC)
write_log (_T("A2091 %s SCSI reset\n"), WD33C93);
#endif
}
static void incsasr (struct wd_chip_state *wd, int w)
{
if (wd->sasr == WD_AUXILIARY_STATUS || wd->sasr == WD_DATA || wd->sasr == WD_COMMAND)
return;
if (w && wd->sasr == WD_SCSI_STATUS)
return;
wd->sasr++;
wd->sasr &= 0x1f;
}
static void dmac_a2091_cint (struct wd_state *wd)
{
wd->cdmac.dmac_istr = 0;
devices_rethink_all(rethink_a2091);
}
static void doscsistatus(struct wd_state *wd, uae_u8 status)
{
wd->wc.wdregs[WD_SCSI_STATUS] = status;
wd->wc.auxstatus |= ASR_INT;
#if WD33C93_DEBUG > 1
write_log (_T("%s STATUS=%02X\n"), WD33C93, status);
#endif
if (!wd->enabled)
return;
if (wd->cdtv) {
cdtv_scsi_int ();
return;
}
dmac_scsi_int(wd);
#if WD33C93_DEBUG > 2
write_log (_T("Interrupt\n"));
#endif
}
static void set_status_intmask(struct wd_chip_state *wd, uae_u16 intmask)
{
wd->intmask |= intmask;
}
static void set_status (struct wd_chip_state *wd, uae_u8 status, int delay)
{
if (wd->queue_index >= WD_STATUS_QUEUE) {
write_log(_T("WD int queue overflow!\n"));
return;
}
wd->status[wd->queue_index].status = status;
wd->status[wd->queue_index].irq = delay == 0 ? 1 : (delay <= 2 ? 2 : delay);
wd->queue_index++;
}
static void set_status (struct wd_chip_state *wd, uae_u8 status)
{
set_status (wd, status, 0);
}
static uae_u32 gettc (struct wd_chip_state *wd)
{
return wd->wdregs[WD_TRANSFER_COUNT_LSB] | (wd->wdregs[WD_TRANSFER_COUNT] << 8) | (wd->wdregs[WD_TRANSFER_COUNT_MSB] << 16);
}
static void settc (struct wd_chip_state *wd, uae_u32 tc)
{
wd->wdregs[WD_TRANSFER_COUNT_LSB] = tc & 0xff;
wd->wdregs[WD_TRANSFER_COUNT] = (tc >> 8) & 0xff;
wd->wdregs[WD_TRANSFER_COUNT_MSB] = (tc >> 16) & 0xff;
}
static bool decreasetc(struct wd_chip_state *wd)
{
uae_u32 tc = gettc (wd);
if (!tc)
return true;
tc--;
settc (wd, tc);
return tc == 0;
}
static int canwddma(struct wd_state *wds)
{
struct wd_chip_state *wd = &wds->wc;
uae_u8 mode = wd->wdregs[WD_CONTROL] >> 5;
switch(wds->dmac_type)
{
case COMMODORE_8727:
if (mode != 0 && mode != 4) {
write_log (_T("%s weird DMA mode %d!!\n"), WD33C93, mode);
}
return mode == 4;
case COMMODORE_DMAC:
case COMMODORE_SDMAC:
case GVP_DMAC_S2:
if (mode != 0 && mode != 4 && mode != 1) {
write_log (_T("%s weird DMA mode %d!!\n"), WD33C93, mode);
}
return mode == 4 || mode == 1;
case GVP_DMAC_S1:
if (mode != 0 && mode != 2) {
write_log (_T("%s weird DMA mode %d!!\n"), WD33C93, mode);
}
return mode == 2;
case COMSPEC_CHIP:
return -1;
default:
return 0;
}
}
#if WD33C93_DEBUG > 0
static TCHAR *scsitostring (struct wd_chip_state *wd, struct scsi_data *scsi)
{
static TCHAR buf[200];
TCHAR *p;
int i;
p = buf;
p[0] = 0;
for (i = 0; i < scsi->offset && i < sizeof wd->wd_data; i++) {
if (i > 0) {
_tcscat (p, _T("."));
p++;
}
_stprintf (p, _T("%02X"), wd->wd_data[i]);
p += _tcslen (p);
}
return buf;
}
#endif
static void setphase(struct wd_chip_state *wd, uae_u8 phase)
{
wd->wdregs[WD_COMMAND_PHASE] = phase;
}
static bool dmacheck_a2091 (struct wd_state *wd)
{
wd->cdmac.dmac_acr++;
if (wd->cdmac.old_dmac && (wd->cdmac.dmac_cntr & CNTR_TCEN)) {
if (wd->cdmac.dmac_wtc == 0) {
wd->cdmac.dmac_istr |= ISTR_E_INT;
return true;
} else {
if ((wd->cdmac.dmac_acr & 1) == 1)
wd->cdmac.dmac_wtc--;
}
}
return false;
}
static bool dmacheck_a2090 (struct wd_state *wd)
{
int dir = wd->cdmac.dmac_acr & 0x00800000;
wd->cdmac.dmac_acr &= 0x7fffff;
wd->cdmac.dmac_acr++;
wd->cdmac.dmac_acr &= 0x7fffff;
wd->cdmac.dmac_acr |= dir;
wd->cdmac.dmac_wtc--;
return wd->cdmac.dmac_wtc == 0;
}
static bool do_dma_commodore_8727(struct wd_state *wd, struct scsi_data *scsi)
{
int dir = wd->cdmac.dmac_acr & 0x00800000;
if (scsi->direction < 0) {
if (dir) {
write_log(_T("8727 mismatched direction!\n"));
return false;
}
#if WD33C93_DEBUG > 0
uaecptr odmac_acr = wd->cdmac.dmac_acr;
#endif
for (;;) {
uae_u8 v1 = 0, v2 = 0;
int status;
status = scsi_receive_data (scsi, &v1, true);
if (!status)
status = scsi_receive_data(scsi, &v2, true);
dma_put_word((wd->cdmac.dmac_acr << 1) & wd->dma_mask, (v1 << 8) | v2);
if (wd->wc.wd_dataoffset < sizeof wd->wc.wd_data - 1) {
wd->wc.wd_data[wd->wc.wd_dataoffset++] = v1;
wd->wc.wd_data[wd->wc.wd_dataoffset++] = v2;
}
if (decreasetc (&wd->wc))
break;
if (decreasetc (&wd->wc))
break;
if (status)
break;
if (dmacheck_a2090 (wd))
break;
}
#if WD33C93_DEBUG > 0
write_log (_T("%s Done DMA from WD, %d/%d %08X\n"), WD33C93, scsi->offset, scsi->data_len, (odmac_acr << 1) & dma_mask);
#endif
wd->cdmac.c8727_pcsd |= 1 << 7;
return true;
} else if (scsi->direction > 0) {
if (!dir) {
write_log(_T("8727 mismatched direction!\n"));
return false;
}
#if WD33C93_DEBUG > 0
uaecptr odmac_acr = wd->cdmac.dmac_acr;
#endif
for (;;) {
int status;
uae_u16 v = dma_get_word((wd->cdmac.dmac_acr << 1) & wd->dma_mask);
if (wd->wc.wd_dataoffset < sizeof wd->wc.wd_data - 1) {
wd->wc.wd_data[wd->wc.wd_dataoffset++] = v >> 8;
wd->wc.wd_data[wd->wc.wd_dataoffset++] = v;
}
status = scsi_send_data (scsi, v >> 8);
if (!status)
status = scsi_send_data (scsi, v);
if (decreasetc (&wd->wc))
break;
if (decreasetc (&wd->wc))
break;
if (status)
break;
if (dmacheck_a2090 (wd))
break;
}
#if WD33C93_DEBUG > 0
write_log (_T("%s Done DMA to WD, %d/%d %08x\n"), WD33C93, scsi->offset, scsi->data_len, (odmac_acr << 1) & (currprefs.cs_z2dma32bit ? 0xffffffff : 0xffffff));
#endif
wd->cdmac.c8727_pcsd |= 1 << 7;
return true;
}
return false;
}
static bool do_dma_commodore(struct wd_state *wd, struct scsi_data *scsi)
{
if (wd->cdtv)
cdtv_getdmadata(&wd->cdmac.dmac_acr);
if (scsi->direction < 0) {
#if WD33C93_DEBUG || XT_DEBUG > 0
uaecptr odmac_acr = wd->cdmac.dmac_acr;
#endif
bool run = true;
while (run) {
uae_u8 v;
int status = scsi_receive_data(scsi, &v, true);
dma_put_byte(wd->cdmac.dmac_acr & wd->dma_mask, v);
if (wd->wc.wd_dataoffset < sizeof wd->wc.wd_data)
wd->wc.wd_data[wd->wc.wd_dataoffset++] = v;
if (decreasetc (&wd->wc))
run = false;
if (dmacheck_a2091 (wd))
run = false;
if (status)
run = false;
}
#if WD33C93_DEBUG || XT_DEBUG > 0
write_log (_T("%s Done DMA from WD, %d/%d %08X\n"), WD33C93, scsi->offset, scsi->data_len, odmac_acr);
#endif
return true;
} else if (scsi->direction > 0) {
#if WD33C93_DEBUG || XT_DEBUG > 0
uaecptr odmac_acr = wd->cdmac.dmac_acr;
#endif
bool run = true;
while (run) {
int status;
uae_u8 v = dma_get_byte(wd->cdmac.dmac_acr & wd->dma_mask);
if (wd->wc.wd_dataoffset < sizeof wd->wc.wd_data)
wd->wc.wd_data[wd->wc.wd_dataoffset++] = v;
status = scsi_send_data (scsi, v);
if (decreasetc (&wd->wc))
run = false;
if (dmacheck_a2091 (wd))
run = false;
if (status)
run = false;
}
#if WD33C93_DEBUG || XT_DEBUG > 0
write_log (_T("%s Done DMA to WD, %d/%d %08x\n"), WD33C93, scsi->offset, scsi->data_len, odmac_acr);
#endif
return true;
}
return false;
}
static bool do_dma_gvp_s1(struct wd_state *wd, struct scsi_data *scsi)
{
if (scsi->direction < 0) {
for (;;) {
uae_u8 v;
int status = scsi_receive_data(scsi, &v, true);
wd->gdmac.buffer[wd->wc.wd_dataoffset++] = v;
wd->wc.wd_dataoffset &= wd->gdmac.s1_rammask;
if (decreasetc (&wd->wc))
break;
if (status)
break;
}
#if WD33C93_DEBUG > 0
write_log (_T("%s Done DMA from WD, %d/%d\n"), WD33C93, scsi->offset, scsi->data_len);
#endif
return true;
} else if (scsi->direction > 0) {
for (;;) {
int status;
uae_u8 v = wd->gdmac.buffer[wd->wc.wd_dataoffset++];
wd->wc.wd_dataoffset &= wd->gdmac.s1_rammask;
status = scsi_send_data (scsi, v);
wd->gdmac.addr++;
if (decreasetc (&wd->wc))
break;
if (status)
break;
}
#if WD33C93_DEBUG > 0
write_log (_T("%s Done DMA to WD, %d/%d\n"), WD33C93, scsi->offset, scsi->data_len);
#endif
return true;
}
return false;
}
static uae_u32 get_gvp_s2_addr(struct gvp_dmac *g)
{
uae_u32 v = g->addr & g->addr_mask;
if (g->bank_ptr) {
v |= g->bank_ptr[0] << 24;
}
return v;
}
static bool do_dma_gvp_s2(struct wd_state *wd, struct scsi_data *scsi)
{
#if WD33C93_DEBUG > 0
uae_u32 dmaptr = get_gvp_s2_addr(&wd->gdmac);
#endif
if (!is_dma_enabled(wd))
return false;
if (scsi->direction < 0) {
if (wd->gdmac.cntr & 0x10) {
write_log(_T("GVP DMA: mismatched direction when reading!\n"));
return false;
}
for (;;) {
uae_u8 v;
int status = scsi_receive_data(scsi, &v, true);
dma_put_byte(get_gvp_s2_addr(&wd->gdmac) & wd->dma_mask, v);
if (wd->wc.wd_dataoffset < sizeof wd->wc.wd_data)
wd->wc.wd_data[wd->wc.wd_dataoffset++] = v;
wd->gdmac.addr++;
wd->gdmac.addr &= wd->gdmac.addr_mask;
if (decreasetc (&wd->wc))
break;
if (status)
break;
}
#if WD33C93_DEBUG > 0
write_log (_T("%s Done DMA from WD, %d/%d %08x\n"), WD33C93, scsi->offset, scsi->data_len, dmaptr);
#endif
return true;
} else if (scsi->direction > 0) {
if (!(wd->gdmac.cntr & 0x10)) {
write_log(_T("GVP DMA: mismatched direction when writing!\n"));
return false;
}
for (;;) {
int status;
uae_u8 v = dma_get_byte(get_gvp_s2_addr(&wd->gdmac) & wd->dma_mask);
if (wd->wc.wd_dataoffset < sizeof wd->wc.wd_data)
wd->wc.wd_data[wd->wc.wd_dataoffset++] = v;
status = scsi_send_data (scsi, v);
wd->gdmac.addr++;
wd->gdmac.addr &= wd->gdmac.addr_mask;
if (decreasetc (&wd->wc))
break;
if (status)
break;
}
#if WD33C93_DEBUG > 0
write_log (_T("%s Done DMA to WD, %d/%d %08x\n"), WD33C93, scsi->offset, scsi->data_len, dmaptr);
#endif
return true;
}
return false;
}
static bool do_dma(struct wd_state *wd)
{
struct scsi_data *scsi = wd->wc.scsi;
wd->wc.wd_data_avail = 0;
m68k_cancel_idle();
if (scsi->direction == 0)
write_log (_T("%s DMA but no data!?\n"), WD33C93);
switch (wd->dmac_type)
{
case COMMODORE_DMAC:
case COMMODORE_SDMAC:
return do_dma_commodore(wd, scsi);
case COMMODORE_8727:
return do_dma_commodore_8727(wd, scsi);
case GVP_DMAC_S2:
return do_dma_gvp_s2(wd, scsi);
case GVP_DMAC_S1:
return do_dma_gvp_s1(wd, scsi);
}
return false;
}
static void wd_cmd_sel_xfer (struct wd_chip_state *wd, struct wd_state *wds, bool atn);
static bool wd_do_transfer_out (struct wd_chip_state *wd, struct wd_state *wds, struct scsi_data *scsi)
{
#if WD33C93_DEBUG > 0
write_log (_T("%s SCSI O [%02X] %d/%d TC=%d %s\n"), WD33C93, wd->wdregs[WD_COMMAND_PHASE], scsi->offset, scsi->data_len, gettc (wd), scsitostring (wd, scsi));
#endif
if (wd->wdregs[WD_COMMAND_PHASE] < 0x20) {
int msg = wd->wd_data[0];
/* message was sent */
setphase (wd, 0x20);
wd->wd_phase = CSR_XFER_DONE | PHS_COMMAND;
scsi->status = 0;
scsi_start_transfer (scsi);
#if WD33C93_DEBUG > 0
write_log (_T("%s SCSI got MESSAGE %02X\n"), WD33C93, msg);
#endif
scsi->message[0] = msg;
} else if (wd->wdregs[WD_COMMAND_PHASE] == 0x30) {
#if WD33C93_DEBUG > 0
write_log (_T("%s SCSI got COMMAND %02X\n"), WD33C93, wd->wd_data[0]);
#endif
if (scsi->offset < scsi->data_len) {
// data missing, ask for more
wd->wd_phase = CSR_XFER_DONE | PHS_COMMAND;
setphase (wd, 0x30 + scsi->offset);
set_status (wd, wd->wd_phase, 1);
return false;
}
settc (wd, 0);
scsi_start_transfer (scsi);
scsi_emulate_analyze (scsi);
if (scsi->direction > 0) {
/* if write command, need to wait for data */
if (scsi->data_len <= 0 || scsi->direction == 0) {
// Status phase if command didn't return anything and don't want anything
wd->wd_phase = CSR_XFER_DONE | PHS_STATUS;
setphase (wd, 0x46);
} else {
wd->wd_phase = CSR_XFER_DONE | PHS_DATA_OUT;
setphase (wd, 0x45);
}
} else {
scsi_emulate_cmd (scsi);
if (wd->scsi->data_len <= 0 || scsi->direction == 0) {
// Status phase if command didn't return anything and don't want anything
wd->wd_phase = CSR_XFER_DONE | PHS_STATUS;
setphase (wd, 0x46);
} else {
wd->wd_phase = CSR_XFER_DONE | PHS_DATA_IN;
setphase (wd, 0x45); // just skip all reselection and message stuff for now..
}
}
} else if (wd->wdregs[WD_COMMAND_PHASE] == 0x46 || wd->wdregs[WD_COMMAND_PHASE] == 0x45) {
if (wd->scsi->offset < scsi->data_len) {
// data missing, ask for more
wd->wd_phase = CSR_XFER_DONE | (scsi->direction < 0 ? PHS_DATA_IN : PHS_DATA_OUT);
set_status (wd, wd->wd_phase, 10);
return false;
}
settc (wd, 0);
if (scsi->direction > 0) {
/* data was sent */
scsi_emulate_cmd (scsi);
scsi->data_len = 0;
wd->wd_phase = CSR_XFER_DONE | PHS_STATUS;