-
Notifications
You must be signed in to change notification settings - Fork 9
/
iopage.js
executable file
·1489 lines (1423 loc) · 60.1 KB
/
iopage.js
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937
938
939
940
941
942
943
944
945
946
947
948
949
950
951
952
953
954
955
956
957
958
959
960
961
962
963
964
965
966
967
968
969
970
971
972
973
974
975
976
977
978
979
980
981
982
983
984
985
986
987
988
989
990
991
992
993
994
995
996
997
998
999
1000
// Javascript PDP 11/70 Emulator v1.8
// written by Paul Nankervis
// Please send suggestions, fixes and feedback to [email protected]
// I'm particularly interested in hearing from anyone with real experience on a PDP 11/70 front panel
//
// This code may be used freely provided the original author name is acknowledged in any modified source code
//
// http://skn.noip.me/pdp11/pdp11.html
//
// Disk routines need a clean up - specifically the RP11 stuff needs rewriting :-(
//
// Map an 18 bit unibus address to a 22 bit memory address via the unibus map (if active)
//
//
function mapUnibus(unibusAddress) {
var idx = (unibusAddress >> 13) & 0x1f;
if (idx < 31) {
if (CPU.MMR3 & 0x20) {
unibusAddress = (CPU.unibusMap[idx] + (unibusAddress & 0x1fff)) & 0x3fffff;
}
} else {
unibusAddress |= IOBASE_22BIT; // top page always maps to unibus i/o page - apparently.
}
return unibusAddress;
}
// =========== Disk I/O support routines ===========
// getData() is called at the completion of an XMLHttpRequest request to GET disk data.
// It extracts the received data and stores it in the appropriate disk cache.
function getData(xhr, operation, meta, position, address, count) {
var arrayBuffer, byteArray, block, word, base;
arrayBuffer = xhr.response;
if ((xhr.status != 0 && xhr.status != 206) || !arrayBuffer) {
meta.postProcess(1, meta, position, address, count); // NXD - read error?
} else {
byteArray = new Uint8Array(arrayBuffer);
block = ~~(position / meta.blockSize);
for (base = 0; base < byteArray.length;) {
if (typeof meta.cache[block] !== "undefined") {
base += meta.blockSize << 1;
} else {
meta.cache[block] = [];
for (word = 0; word < meta.blockSize; word++) {
if (base < byteArray.length) {
meta.cache[block][word] = (byteArray[base] & 0xff) | ((byteArray[base + 1] << 8) & 0xff00);
} else {
meta.cache[block][word] = 0;
}
base += 2;
}
}
block++;
}
diskIO(operation, meta, position, address, count);
}
}
// diskIO() moves data between memory and the disk cache. If cache blocks are undefined then
// an XMLHttpRequest request is kicked off to get the appropriate disk data from the server.
// Operations supported are: 1: Write, 2: Read, 3: Check (corresponds with RK function codes :-) )
// position is in words and count in bytes (an allowance for tape which can do byte IO)
function diskIO(operation, meta, position, address, count) {
var block, word, data, xhr;
block = ~~(position / meta.blockSize);
if (typeof meta.cache[block] !== "undefined") {
word = position % meta.blockSize;
while (count > 0) {
switch (operation) {
case 1: // Write: write from memory to cache
case 3: // Check: compare memory with disk cache
data = readWordByAddr((meta.mapped ? mapUnibus(address) : address));
if (data < 0) {
meta.postProcess(2, meta, block * meta.blockSize + word, address, count); // NXM
return;
}
if (operation == 1) { // write: put data into disk cache
meta.cache[block][word] = data;
} else { // check: compare memory with disk cache
if (meta.cache[block][word] != data) {
meta.postProcess(3, meta, block * meta.blockSize + word, address, count); // mismatch
return;
}
}
//if (meta.increment) {
address += 2;
//}
count -= 2; // bytes to go.... (currently all write operations are whole words)
break;
case 2: // Read: read to memory from cache
if (count > 1) { // tape can read odd number of bytes - of course it can. :-(
if (writeWordByAddr((meta.mapped ? mapUnibus(address) : address), meta.cache[block][word]) < 0) {
meta.postProcess(2, meta, block * meta.blockSize + word, address, count); // NXM
return;
}
//if (meta.increment) {
address += 2;
//}
count -= 2; // bytes to go....
} else {
if (writeByteByAddr((meta.mapped ? mapUnibus(address) : address), data) < 0) {
meta.postProcess(2, meta, block * meta.blockSize + word, address, count); // NXM
return;
}
//if (meta.increment) {
address += 1;
//}
--count; // bytes to go....
}
break;
case 4: // accumulate a record count into the address field for tape operations
address = (meta.cache[block][word] << 16) | (address >> 16);
count -= 2; // bytes to go....
break;
default:
panic(); // invalid operation - how did we get here?
}
if (++word >= meta.blockSize) {
word = 0;
block++;
if (typeof meta.cache[block] === "undefined") break;
}
}
position = block * meta.blockSize + word;
}
if (count > 0) { // I/O not complete so we need to get some data
word = (~~(position / meta.blockSize)) * meta.blockSize; // Start word
data = (~~((position + (count >> 1) + meta.blockSize - 1) / meta.blockSize)) * meta.blockSize; // End word
xhr = new XMLHttpRequest();
xhr.open("GET", meta.url, true);
xhr.setRequestHeader("Range", "bytes=" + (word << 1) + "-" + ((data << 1) - 1));
xhr.responseType = "arraybuffer";
xhr.onreadystatechange = function() {
if (xhr.readyState == xhr.DONE) {
getData(xhr, operation, meta, position, address, count);
}
};
xhr.send(null);
return;
}
meta.postProcess(0, meta, position, address, count); // success
}
// =========== RK11 routines ===========
var rk11 = {
rkds: 04700, // 017777400 Drive Status
rker: 0, // 017777402 Error Register
rkcs: 0200, // 017777404 Control Status
rkwc: 0, // 017777406 Word Count
rkba: 0, // 017777410 Bus Address
rkda: 0, // 017777412 Disk Address
meta: [],
TRACKS: [406, 406, 406, 406, 406, 406, 406, 0],
SECTORS: [12, 12, 12, 12, 12, 12, 12, 12]
};
function rk11_seekEnd(drive) {
rk11.rkds = (drive << 13) | (rk11.rkds & 0x1ff0);
rk11.rkcs |= 0x2000;
return rk11.rkcs & 0x40;
}
function rk11_commandEnd(drive) {
rk11.rkds = (drive << 13) | (rk11.rkds & 0x1ff0);
rk11.rkcs = (rk11.rkcs & 0xfffe) | 0x80; // turn off go & set done
return rk11.rkcs & 0x40;
}
function rk11_finish(drive) {
if (rk11.rkcs & 0x40) {
interrupt(0, 10, 5 << 5, 0220, rk11_commandEnd, drive);
} else { // if interrupt not enabled just mark completed
rk11_commandEnd(drive);
}
}
function rk11_init() {
rk11.rkds = 04700; // Set bits 6, 7, 8, 11
rk11.rker = 0; //
rk11.rkcs = 0200;
rk11.rkwc = 0;
rk11.rkba = 0;
rk11.rkda = 0;
}
function rk11_go() {
var sector, address, count;
var drive = (rk11.rkda >> 13) & 7;
if (typeof rk11.meta[drive] === "undefined") {
rk11.meta[drive] = {
"cache": [],
"blockSize": 65536,
"postProcess": rk11_end,
"drive": drive,
"mapped": 1,
"maxblock": rk11.TRACKS[drive] * rk11.SECTORS[drive],
"url": "rk" + drive + ".dsk"
};
}
rk11.rkcs &= ~0x2080; // turn off done bit & search complete
rk11.rker &= ~0x03; // turn off soft errors
if (rk11.TRACKS[drive] == 0) {
rk11.rker |= 0x8080; // NXD
} else {
sector = (((rk11.rkda >> 4) & 0x1ff) * rk11.SECTORS[drive] + (rk11.rkda & 0xf));
address = (((rk11.rkcs & 0x30)) << 12) | rk11.rkba;
count = (0x10000 - rk11.rkwc) & 0xffff;
switch ((rk11.rkcs >> 1) & 7) { // function code
case 0: // controller reset
interrupt(1, -1, 5 << 5, 0220);
rk11_init();
break;
case 1: // write
case 2: // read
case 3: // check
if (((rk11.rkda >> 4) & 0x1ff) >= rk11.TRACKS[drive]) {
rk11.rker |= 0x8040; // NXC
break;
}
if ((rk11.rkda & 0xf) >= rk11.SECTORS[drive]) {
rk11.rker |= 0x8020; // NXS
break;
}
sector = (((rk11.rkda >> 4) & 0x1ff) * rk11.SECTORS[drive] + (rk11.rkda & 0xf));
address = (((rk11.rkcs & 0x30)) << 12) | rk11.rkba;
count = (0x10000 - rk11.rkwc) & 0xffff;
diskIO((rk11.rkcs >> 1) & 7, rk11.meta[drive], sector * 256, address, count << 1);
return;
case 4: // Seek - complete immediately
rk11.rkcs |= 0x2000; // Set search complete
interrupt(0, 20, 5 << 5, 0220, rk11_seekEnd, drive);
break;
case 5: // Read Check
break;
case 6: // Drive Reset
rk11.rkds = 04700 | (drive << 13);
rk11.rker = 0; //
rk11.rkcs = 0200;
rk11.rkda &= 0xe000; // keep drive number
interrupt(0, 20, 5 << 5, 0220, rk11_seekEnd, drive);
//rk11.rkcs |= 0x2000; // Set search complete
break;
case 7: // Write Lock - not implemented :-(
break;
default:
break;
}
}
rk11_finish(drive);
}
function rk11_end(err, meta, position, address, count) {
rk11.rkba = address & 0xffff;
rk11.rkcs = (rk11.rkcs & ~0x30) | ((address >> 12) & 0x30);
rk11.rkwc = (0x10000 - (count >> 1)) & 0xffff;
position = ~~(position / 256);
rk11.rkda = (rk11.rkda & 0xe000) | ((~~(position / rk11.SECTORS[meta.drive])) << 4) | (position % rk11.SECTORS[meta.drive]);
switch (err) {
case 1: // read error
rk11.rker |= 0x8100; // Report TE (Timing error)
break;
case 2: // NXM
rk11.rker |= 0x8400; // NXM
break;
case 3: // compare error
rk11.rker |= 0x8001; // Report TE (Write check error)
break;
}
rk11_finish(meta.drive);
}
function accessRK11(physicalAddress, data, byteFlag) {
var result;
switch (physicalAddress & ~1) {
case 017777400: // rk11.rkds
result = rk11.rkds;
break;
case 017777402: // rk11.rker
result = rk11.rker;
break;
case 017777404: // rk11.rkcs
rk11.rkcs &= 0x3fff;
if (rk11.rker & 0x7fff) rk11.rkcs |= 0x8000;
if (rk11.rker & 0x7fc0) rk11.rkcs |= 0x4000;
result = insertData(rk11.rkcs, physicalAddress, data, byteFlag);
if (data >= 0 && result >= 0) {
if ((rk11.rkcs ^ result) & 0x40) { // Has IE bit changed?
if (result & 0x40) {
if (!(result & 1)) {
interrupt(1, 0, 5 << 5, 0220);
}
} else {
rk11.rkcs = (rk11.rkcs & 0xfffe) | 0x80; // turn off go & set done
interrupt(1, -1, 5 << 5, 0220);
}
}
rk11.rkcs = (result & ~0xf080) | (rk11.rkcs & 0xf080); // Bits 7 and 12 - 15 are read only
if (rk11.rkcs & 1) {
rk11.rkcs &= ~0x2080; // turn off done bit & search complete
rk11.rker &= ~0x03; // turn off soft errors
rk11_go();
//setTimeout(rk11_go, 10);
}
}
break;
case 017777406: // rk11.rkwc
result = insertData(rk11.rkwc, physicalAddress, data, byteFlag);
if (result >= 0) rk11.rkwc = result;
break;
case 017777410: // rk11.rkba
result = insertData(rk11.rkba, physicalAddress, data, byteFlag);
if (result >= 0) rk11.rkba = result;
break;
case 017777412: // rk11.rkda
result = insertData(rk11.rkda, physicalAddress, data, byteFlag);
if (result >= 0) rk11.rkda = result;
break;
case 017777414: // rk11.unused
case 017777416: // rk11.rkdb
result = 0;
break;
default:
CPU.CPU_Error |= 0x10;
return trap(4, 134);
}
//console.log("RK11 Access "+physicalAddress.toString(8)+" "+data.toString(8)+" "+byteFlag.toString(8)+" -> "+result.toString(8));
return result;
}
// =========== RL11 routines ===========
var rl11 = {
csr: 0x81, // 017774400 Control status register
bar: 0, // 017774402 Bus address
dar: 0, // 017774404 Disk address
mpr: 0, // 017774406 Multi purpose
DAR: 0, // internal disk address
meta: [], // sector cache
SECTORS: [40, 40, 40, 40], // sectors per track
TRACKS: [1024, 1024, 512, 512], // First two drives RL02 - last two RL01 - cylinders * 2
STATUS: [0235, 0235, 035, 035] // First two drives RL02 - last two RL01
};
function rl11_commandEnd() {
rl11.csr |= 0x81; // turn off go & set ready
return rl11.csr & 0x40;
}
function rl11_finish(drive) {
if (rl11.csr & 0x40) {
interrupt(0, 10, 5 << 5, 0160, rl11_commandEnd);
} else { // if interrupt not enabled just mark completed
rl11_commandEnd();
}
}
function rl11_go() {
var sector, address, count;
var drive = (rl11.csr >> 8) & 3;
rl11.csr &= ~0x1; // ready bit (0!)
if (typeof rl11.meta[drive] === "undefined") {
rl11.meta[drive] = {
"cache": [],
"blockSize": 65536,
"postProcess": rl11_end,
"drive": drive,
"mapped": 1,
"maxblock": rl11.TRACKS[drive] * rl11.SECTORS[drive],
"url": "rl" + drive + ".dsk"
};
}
switch ((rl11.csr >> 1) & 7) { // function code
case 0: // no op
break;
case 1: // write check
break;
case 2: // get status
if (rl11.mpr & 8) rl11.csr &= 0x3f;
rl11.mpr = rl11.STATUS[drive] | (rl11.DAR & 0100); // bit 6 Head Select bit 7 Drive Type 1=rl02
break;
case 3: // seek
if ((rl11.dar & 3) == 1) {
if (rl11.dar & 4) {
rl11.DAR = ((rl11.DAR + (rl11.dar & 0xff80)) & 0xff80) | ((rl11.dar << 2) & 0x40);
} else {
rl11.DAR = ((rl11.DAR - (rl11.dar & 0xff80)) & 0xff80) | ((rl11.dar << 2) & 0x40);
}
rl11.dar = rl11.DAR;
}
break;
case 4: // read header
rl11.mpr = rl11.DAR;
break;
case 5: // write
if ((rl11.dar >> 6) >= rl11.TRACKS[drive]) {
rl11.csr |= 0x9400; // HNF
break;
}
if ((rl11.dar & 0x3f) >= rl11.SECTORS[drive]) {
rl11.csr |= 0x9400; // HNF
break;
}
sector = ((rl11.dar >> 6) * rl11.SECTORS[drive]) + (rl11.dar & 0x3f);
address = rl11.bar | ((rl11.csr & 0x30) << 12);
count = (0x10000 - rl11.mpr) & 0xffff;
diskIO(1, rl11.meta[drive], sector * 128, address, count << 1);
return;
break;
case 6: // read
case 7: // Read data without header check
if ((rl11.dar >> 6) >= rl11.TRACKS[drive]) {
rl11.csr |= 0x9400; // HNF
break;
}
if ((rl11.dar & 0x3f) >= rl11.SECTORS[drive]) {
rl11.csr |= 0x9400; // HNF
break;
}
sector = ((rl11.dar >> 6) * rl11.SECTORS[drive]) + (rl11.dar & 0x3f);
address = rl11.bar | ((rl11.csr & 0x30) << 12);
count = (0x10000 - rl11.mpr) & 0xffff;
diskIO(2, rl11.meta[drive], sector * 128, address, count << 1);
return;
break;
}
rl11_finish();
//setTimeout(rl11_finish,0);
}
function rl11_end(err, meta, position, address, count) {
var sector = ~~(position / 128);
rl11.bar = address & 0xffff;
rl11.csr = (rl11.csr & ~0x30) | ((address >> 12) & 0x30);
rl11.dar = ((~~(sector / rl11.SECTORS[meta.drive])) << 6) | (sector % rl11.SECTORS[meta.drive]);
rl11.DAR = rl11.dar;
rl11.mpr = (0x10000 - (count >> 1)) & 0xffff;
switch (err) {
case 1: // read error
rl11.csr |= 0x8400; // Report operation incomplete
break;
case 2: // NXM
rl11.csr |= 0xa000; // NXM
break;
}
rl11_finish();
}
function accessRL11(physicalAddress, data, byteFlag) {
var result;
switch (physicalAddress & ~1) {
case 017774400: // rl11.csr
result = insertData(rl11.csr, physicalAddress, data, byteFlag);
if (data >= 0 && result >= 0) {
if ((rl11.csr & 0x40) && !(result & 0x40)) { // if IE being reset then kill any pending interrupts
//rl11.csr |= 0x81; // turn off go & set ready
interrupt(1, -1, 5 << 5, 0160);
}
if (!(result & 0x80)) {
rl11.csr = (rl11.csr & ~0x3fe) | (result & 0x3fe);
rl11_go();
} else {
if ((result & 0x40) && !(rl11.csr & 0x40)) {
interrupt(1, 10, 5 << 5, 0160);
}
rl11.csr = (rl11.csr & ~0x3fe) | (result & 0x3fe);
}
}
break;
case 017774402: // rl11.bar
result = insertData(rl11.bar, physicalAddress, data, byteFlag);
if (result >= 0) {
rl11.bar = result & 0xfffe;
}
break;
case 017774404: // rl11.dar
result = insertData(rl11.dar, physicalAddress, data, byteFlag);
if (result >= 0) rl11.dar = result;
break;
case 017774406: // rl11.mpr
result = insertData(rl11.mpr, physicalAddress, data, byteFlag);
if (result >= 0) rl11.mpr = result;
break;
default:
CPU.CPU_Error |= 0x10;
return trap(4, 134);
}
return result;
}
// =========== RP11 routines ===========
var rp11 = {
DTYPE: [020022, 020022, 020020, 020020, 020022, 020020, 020022, 020042], // Drive type rp06, rp06, rp04, rp04...
SECTORS: [22, 22, 22, 22, 22, 22, 22, 50], // sectors per track
SURFACES: [19, 19, 19, 19, 19, 19, 19, 32], //
CYLINDERS: [815, 815, 815, 815, 815, 411, 815, 630],
meta: [], //meta data for drive
rpcs1: 0x880, // Massbus 00 - actual register is a mix of controller and drive bits :-(
rpwc: 0,
rpba: 0, // rpba & rpbae
rpda: [0, 0, 0, 0, 0, 0, 0, 0], // Massbus 05
rpcs2: 0,
rpds: [0x1180, 0x1180, 0x1180, 0x1180, 0, 0, 0, 0], // Massbus 01 Read only
rper1: [0, 0, 0, 0, 0, 0, 0, 0], // Massbus 02
// rpas: 0, // Massbus 04???
rpla: [0, 0, 0, 0, 0, 0, 0, 0], // Massbus 07 Read only
rpdb: 0,
rpmr: [0, 0, 0, 0, 0, 0, 0, 0], // Massbus 03
rpdt: [0, 0, 0, 0, 0, 0, 0, 0], // Massbus 06 Read only
rpsn: [1, 2, 3, 4, 5, 6, 7, 8], // Massbus 10 Read only
rpof: [0, 0, 0, 0, 0, 0, 0, 0], // Massbus 11
rpdc: [0, 0, 0, 0, 0, 0, 0, 0], // Massbus 12
rpcc: [0, 0, 0, 0, 0, 0, 0, 0], // Massbus 13 Read only
rper2: [0, 0, 0, 0, 0, 0, 0, 0], // Massbus 14
rper3: [0, 0, 0, 0, 0, 0, 0, 0], // Massbus 15
rpec1: [0, 0, 0, 0, 0, 0, 0, 0], // Massbus 16 Read only
rpec2: [0, 0, 0, 0, 0, 0, 0, 0], // Massbus 17 Read only
rpcs3: 0
};
function rp11_init() {
rp11.rpcs1 = 0x880;
rp11.rpcs2 = 0;
rp11.rpds = [0x11c0, 0x11c0, 0x11c0, 0x11c0, 0, 0, 0, 0];
rp11.rpda = [0, 0, 0, 0, 0, 0, 0, 0];
rp11.rpdc = [0, 0, 0, 0, 0, 0, 0, 0];
rp11.rper1 = [0, 0, 0, 0, 0, 0, 0, 0];
rp11.rper3 = [0, 0, 0, 0, 0, 0, 0, 0];
rp11.rpas = rp11.rpwc = rp11.rpcs3 = 0;
rp11.rpba = 0;
}
function rp11_attention(drive, flags) {
rp11.rpas |= 1 << drive;
rp11.rpds[drive] |= 0x8000;
if (flags) {
rp11.rper1[drive] |= flags;
rp11.rpds[drive] |= 0x4000;
}
}
//When a Data Transfer command is successfully initiated both RDY
//and DRY become negated. When a non-data transfer command is
//successfully initiated only DRY bit become negated.
//DVA should be set
function rp11_go() {
var sector, count, drive = rp11.rpcs2 & 7;
rp11.rpds[drive] &= 0x7fff; // turn off ATA on go bit
if (typeof rp11.meta[drive] === "undefined") {
rp11.meta[drive] = {
"cache": [],
"blockSize": 65536 * 4, //256, // 32768, // 65536 * 4,
"postProcess": rp11_end,
"drive": drive,
"mapped": 0,
"maxblock": rp11.CYLINDERS[drive] * rp11.SURFACES[drive] * rp11.SECTORS[drive],
"url": "rp" + drive + ".dsk"
};
}
switch (rp11.rpcs1 & 0x3f) { // function code
case 01: // NULL
return;
case 03: // unload
break;
case 05: // seek
break;
case 07: // recalibrate
break;
case 011: // init
rp11.rpds[drive] = 0x11c0; //| 0x8000;
rp11.rpcs1 &= ~0x703f; // Turn off error bits
rp11.rpda[drive] = 0;
rp11.rpdc[drive] = 0;
rp11.rpcs1 = 0x880; // ??
return;
case 013: // release
return;
case 015: // offset
break;
case 017: // return to centreline
break;
case 021: // read in preset
// Read-in Preset - Sets the VV (volume valid) bit, clears the Desired Sector/Track Address register, clears the Desired Cylinder Address register, and clears the FMT, HCI, and ECI bits in the Offset register. Clearing the FMT bit causes the RP04 to be in IS-bit mode.
rp11.rpdc[drive] = rp11.rpda[drive] = 0;
rp11.rpds[drive] = 0x11c0; // |= 0x40; // set VV
rp11.rpof[drive] = 0; // Turn off FMT 0x1000
return;
case 023: // pack ack
rp11.rpds[drive] |= 0x40; // set VV
return;
case 031: // search
break;
case 061: // write
if (rp11.rpdc[drive] >= rp11.CYLINDERS[drive] || (rp11.rpda[drive] >> 8) >= rp11.SURFACES[drive] ||
(rp11.rpda[drive] & 0xff) >= rp11.SECTORS[drive]) {
rp11.rper1[drive] |= 0x400; // invalid sector address
rp11.rpcs1 |= 0xc000; // set SC & TRE
break;
}
rp11.rpcs1 &= ~0x7000; // Turn error bits
rp11.rpcs1 &= ~0x4080; // Turn TRE & ready off
rp11.rpcs2 &= ~0x800; // Turn off NEM (NXM)
rp11.rpds[drive] &= ~0x480; // Turn off LST & DRY
sector = (rp11.rpdc[drive] * rp11.SURFACES[drive] + (rp11.rpda[drive] >> 8)) * rp11.SECTORS[drive] + (rp11.rpda[drive] & 0xff);
diskIO(1, rp11.meta[drive], sector * 256, rp11.rpba, ((0x10000 - rp11.rpwc) & 0xffff) << 1);
return;
break;
case 071: // read
if (rp11.rpdc[drive] >= rp11.CYLINDERS[drive] || (rp11.rpda[drive] >> 8) >= rp11.SURFACES[drive] ||
(rp11.rpda[drive] & 0xff) >= rp11.SECTORS[drive]) {
rp11.rper1[drive] |= 0x400; // invalid sector address
rp11.rpcs1 |= 0xc000; // set SC & TRE
break;
}
rp11.rpcs1 &= ~0x7000; // Turn error bits
rp11.rpcs1 &= ~0x4080; // Turn TRE & ready off
rp11.rpcs2 &= ~0x800; // Turn off NEM (NXM)
rp11.rpds[drive] &= ~0x480; // Turn off LST & DRY
sector = (rp11.rpdc[drive] * rp11.SURFACES[drive] + (rp11.rpda[drive] >> 8)) * rp11.SECTORS[drive] + (rp11.rpda[drive] & 0xff);
diskIO(2, rp11.meta[drive], sector * 256, rp11.rpba, ((0x10000 - rp11.rpwc) & 0xffff) << 1);
return;
break;
default:
panic();
return;
break;
}
interrupt(1, 12, 5 << 5, 0254, function() {
rp11.rpds[drive] |= 0x8000; // ATA
rp11.rpcs1 |= 0x8000; // SC no
if (rp11.rpcs1 & 0x40) return true;
return false;
});
}
function rp11_end(err, meta, position, address, count) {
var sector, block = ~~((position + 255) / 256);
rp11.rpwc = (0x10000 - (count >> 1)) & 0xffff;
rp11.rpba = address & 0x3fffff;
sector = ~~(block / rp11.SECTORS[meta.drive]);
rp11.rpda[meta.drive] = ((sector % rp11.SURFACES[meta.drive]) << 8) | (block % rp11.SECTORS[meta.drive]);
rp11.rpdc[meta.drive] = ~~(sector / rp11.SURFACES[meta.drive]);
if (block >= meta.maxblock) {
rp11.rpds[meta.drive] |= 0x400; // LST
}
if (err) {
rp11.rpds[meta.drive] |= 0x8000; //ATA
rp11.rpcs1 |= 0xc000; // set SC & TRE
switch (err) {
case 1: // read error
rp11.rpcs2 |= 0x200; // MXF Missed transfer
break;
case 2: // NXM
rp11.rpcs2 |= 0x800; // NEM (NXM)
break;
}
}
interrupt(1, 20, 5 << 5, 0254, function() {
rp11.rpds[meta.drive] |= 0x80; // 0x8080 must be for rp0 boot - but manual indicates no?
rp11.rpcs1 |= 0x80; // set ready
if (rp11.rpcs1 & 0x40) return true;
return false;
});
}
function accessRP11(physicalAddress, data, byteFlag) {
var idx, result;
idx = rp11.rpcs2 & 7;
switch (physicalAddress & ~1) { // RH11 always there addresses
case 017776700: // rp11.rpcs1 Control status 1
result = (rp11.rpcs1 & ~0xb01) | ((rp11.rpba >> 8) & 0x300);
if (rp11.rpds[idx] & 0x100) {
result |= 0x800; // DVA depends on drive number
if (!(rp11.rpcs1 & 0x80)) result |= 1; // go is opposite of rdy
} else {
result &= 0xff7f; // rdy off if no dva
}
rp11.rpcs1 = result;
if (data >= 0) {
result = insertData(result, physicalAddress, data, byteFlag);
if (result >= 0) {
rp11.rpba = (rp11.rpba & 0x3cffff) | ((result << 8) & 0x30000);
result = (result & ~0xb880) | (rp11.rpcs1 & 0xb880);
if (!(result & 0x40)) interrupt(1, -1, 0, 0254); //remove pending interrupt if IE not set
if ((data & 0xc0) == 0xc0) interrupt(1, 8, 5 << 5, 0254); // RB:
rp11.rpcs1 = result;
if (result & 1 && (rp11.rpcs1 & 0x80)) {
rp11_go();
}
}
}
break;
case 017776702: // rp11.rpwc Word count
result = insertData(rp11.rpwc, physicalAddress, data, byteFlag);
if (result >= 0) rp11.rpwc = result;
break;
case 017776704: // rp11.rpba Memory address
result = rp11.rpba & 0xffff;
if (data >= 0) {
result = insertData(result, physicalAddress, data, byteFlag);
if (result >= 0) {
rp11.rpba = (rp11.rpba & 0x3f0000) | (result & 0xfffe); // must be even
}
}
break;
case 017776710: // rp11.rpcs2 Control status 2
result = rp11.rpcs2;
if (data >= 0) {
result = insertData(result, physicalAddress, data, byteFlag);
if (result >= 0) {
rp11.rpcs2 = (result & 0x3f) | (rp11.rpcs2 & 0xffc0);
if (result & 0x20) rp11_init();
}
}
break;
case 017776716: // rp11.rpas Attention summary
result = 0;
for (idx = 0; idx < 8; idx++) {
if (rp11.rpds[idx] & 0x8000) {
if (data >= 0 && (data & (1 << idx))) {
rp11.rpds[idx] &= 0x7fff;
} else {
result |= 1 << idx;
}
}
}
if (data > 0) rp11.rpcs1 &= 0x7fff; // Turn off SC
break;
case 017776722: // rp11.rpdb Data buffer
result = 0;
break;
case 017776750: // rp11.rpbae Bus address extension
result = (rp11.rpba >> 16) & 0x3f;
if (data >= 0) {
result = insertData(result, physicalAddress, data, byteFlag);
if (result >= 0) {
rp11.rpba = ((result & 0x3f) << 16) | (rp11.rpba & 0xffff);
}
}
break;
case 017776752: // rp11.rpcs3 Control status 3
// result = insertData(rp11.rpcs3, physicalAddress, data, byteFlag);
// if (result >= 0) rp11.rpcs3 = result;
result = 0;
break;
default:
idx = rp11.rpcs2 & 7; // drive number
if (rp11.rpds[idx] & 0x100) {
switch (physicalAddress & ~1) { // Drive registers which may or may not be present
case 017776706: // rp11.rpda Disk address
result = insertData(rp11.rpda[idx], physicalAddress, data, byteFlag);
if (result >= 0) rp11.rpda[idx] = result & 0x1f1f;
break;
case 017776712: // rp11.rpds drive status
result = rp11.rpds[idx];
break;
case 017776714: // rp11.rper1 Error 1
result = 0; // rp11.rper1[idx];
break;
case 017776720: // rp11.rpla Look ahead
result = 0; // rp11.rpla[idx];
break;
case 017776724: // rp11.rpmr Maintenance
//result = insertData(rp11.rpmr[idx], physicalAddress, data, byteFlag);
//if (result >= 0) rp11.rpmr[idx] = result & 0x3ff;
result = 0;
break;
case 017776726: // rp11.rpdt drive type read only
result = rp11.DTYPE[idx]; // 020022
break;
case 017776730: // rp11.rpsn Serial number read only - lie and return drive + 1
result = idx + 1;
break;
case 017776732: // rp11.rpof Offset register
result = insertData(rp11.rpof[idx], physicalAddress, data, byteFlag);
if (result >= 0) rp11.rpof[idx] = result;
//result = 0x1000;
break;
case 017776734: // rp11.rpdc Desired cylinder
result = insertData(rp11.rpdc[idx], physicalAddress, data, byteFlag);
if (result >= 0) rp11.rpdc[idx] = result & 0x1ff;
break;
case 017776736: // rp11.rpcc Current cylinder read only - lie and used desired cylinder
result = rp11.rpdc[idx];
break;
case 017776740: // rp11.rper2 Error 2
result = 0;
break;
case 017776742: // rp11.rper3 Error 3
result = 0; // rp11.rper3[idx];
break;
case 017776744: // rp11.rpec1 Error correction 1 read only
result = 0; // rp11.rpec1[idx];
break;
case 017776746: // rp11.rpec2 Error correction 2 read only
result = 0; //rp11.rpec2[idx];
break;
default:
CPU.CPU_Error |= 0x10;
return trap(4, 132);
}
} else {
rp11.rpcs2 |= 0x1000; // NED
rp11.rpcs1 |= 0xc000; // SC + TRE
if (rp11.rpcs1 & 0x40) {
interrupt(1, 5, 5 << 5, 0254);
}
result = 0;
}
}
return result;
}
// =========== TM11 routines ===========
var tm11 = {
mts: 0x65, // 17772520 Status Register 6 selr 5 bot 2 wrl 0 tur
mtc: 0x6080, // 17772522 Command Register 14-13 bpi 7 cu rdy
mtbrc: 0, // 17772524 Byte Record Counter
mtcma: 0, // 17772526 Current Memory Address Register
mtd: 0, // 17772530 Data Buffer Register
mtrd: 0, // 17772532 TU10 Read Lines
meta: [] //meta data for drive
};
function tm11_commandEnd() {
tm11.mts |= 1; // tape unit ready
tm11.mtc |= 0x80;
return tm11.mtc & 0x40;
}
function tm11_finish() {
if (tm11.mtc & 0x40) {
interrupt(0, 10, 5 << 5, 0224, tm11_commandEnd);
} else { // if interrupt not enabled just mark completed
tm11_commandEnd();
}
}
function tm11_end(err, meta, position, address, count) {
if (err == 0 && meta.command > 0) {
if (address == 0 || address > 0x80000000) { // tape mark
meta.position = position;
tm11.mts |= 0x4000; // set EOF bit
} else {
switch (meta.command) {
case 1: // read
meta.position = position + 2 + ((address + 1) >> 1);
meta.command = 0;
count = (0x10000 - tm11.mtbrc) & 0xffff;
if (count >= address || count == 0) {
count = address;
tm11.mtbrc = (tm11.mtbrc + count) & 0xffff;
} else {
tm11.mts |= 0x200; // RLE
tm11.mtbrc = 0;
}
address = ((tm11.mtc & 0x30) << 12) | tm11.mtcma;
diskIO(2, meta, position, address, count);
// calculate meta.position set count to reduced amount
return;
case 4: // space forward
position = position + 2 + ((address + 1) >> 1);
meta.position = position;
tm11.mtbrc = (tm11.mtbrc + 1) & 0xffff;
if (tm11.mtbrc) {
diskIO(4, meta, position, 0, 4);
return;
}
break;
case 5: // space reverse
position = position - 4 - ((address + 1) >> 1);
meta.position = position;
tm11.mtbrc = (tm11.mtbrc + 1) & 0xffff;
if (tm11.mtbrc) {
if (position > 0) {
diskIO(4, meta, position - 2, 0, 4);
return;
}
}
break;
default:
panic();
}
}
}
if (meta.command == 0) {
tm11.mtbrc = (tm11.mtbrc - count) & 0xffff;
tm11.mtcma = address & 0xffff;
tm11.mtc = (tm11.mtc & ~0x30) | ((address >> 12) & 0x30);
}
switch (err) {
case 1: // read error
tm11.mts |= 0x100; // Bad tape error
break;
case 2: // NXM
tm11.mts |= 0x80; // NXM
break;
}
tm11_finish();
}
function tm11_init() {
var i;
tm11.mts = 0x65; // 6 selr 5 bot 2 wrl 0 tur
tm11.mtc = 0x6080; // 14-13 bpi 7 cu rdy
for (i = 0; i < 8; i++) {
if (typeof tm11.meta[i] !== "undefined") {
tm11.meta[i].position == 0;
}
}
}
function tm11_go() {
var sector, address, count;
var drive = (tm11.mtc >> 8) & 3;
tm11.mtc &= ~0x81; // ready bit (7!) and go (0)
tm11.mts &= 0x04fe; // turn off tape unit ready
if (typeof tm11.meta[drive] === "undefined") {
tm11.meta[drive] = {
"cache": [],
"blockSize": 65536,
"postProcess": tm11_end,
"drive": drive,
"mapped": 1,
"maxblock": 0,
"position": 0,
"command": 0,
"url": "tm" + drive + ".tap"
};
}
tm11.meta[drive].command = (tm11.mtc >> 1) & 7;
//console.log("TM11 Function "+(tm11.meta[drive].command).toString(8)+" "+tm11.mtc.toString(8)+" "+tm11.mts.toString(8)+" @ "+tm11.meta[drive].position.toString(8));
switch (tm11.meta[drive].command) { // function code
case 0: // off-line
break;
case 1: // read
diskIO(4, tm11.meta[drive], tm11.meta[drive].position, 0, 4);
return;
case 2: // write
case 3: // write end of file
case 6: // write with extended IRG
break;
case 4: // space forward
diskIO(4, tm11.meta[drive], tm11.meta[drive].position, 0, 4);
return;
case 5: // space reverse
if (tm11.meta[drive].position > 0) {
diskIO(4, tm11.meta[drive], tm11.meta[drive].position - 2, 0, 4);
return;
}
break;
case 7: // rewind
tm11.meta[drive].position = 0;
tm11.mts |= 0x20; // set BOT
break;
default:
break;
}
tm11_finish();
}
function accessTM11(physicalAddress, data, byteFlag) {
var result, drive = (tm11.mtc >> 8) & 3;
switch (physicalAddress & ~1) {
case 017772520: // tm11.mts
tm11.mts &= ~0x20; // turn off BOT
if (typeof tm11.meta[(tm11.mtc >> 8) & 3] !== "undefined") {
if (tm11.meta[(tm11.mtc >> 8) & 3].position == 0) {
tm11.mts |= 0x20; // turn on BOT
}
}
result = tm11.mts;
break;
case 017772522: // tm11.mtc
tm11.mtc &= 0x7fff; // no err bit
if (tm11.mts & 0xff80) tm11.mtc |= 0x8000;
result = insertData(tm11.mtc, physicalAddress, data, byteFlag);
if (data >= 0 && result >= 0) {
if ((tm11.mtc & 0x40) && !(result & 0x40)) { // if IE being reset then kill any pending interrupts
interrupt(1, -1, 5 << 5, 0224);
}
if (result & 0x1000) { //init