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Hi, I am not an expert in concurrent programming, but I have learnt "false sharing", which means that, when multi cpu cores write to data in the same cache line, it may be quite slow because they can invalidate caches in other cpu cores. Thus, it seems reasonable to ensure those AtomicUsizes are not in the same cache line, such as by inserting dummy paddings.
The text was updated successfully, but these errors were encountered:
Hi, I am not an expert in concurrent programming, but I have learnt "false sharing", which means that, when multi cpu cores write to data in the same cache line, it may be quite slow because they can invalidate caches in other cpu cores. Thus, it seems reasonable to ensure those AtomicUsizes are not in the same cache line, such as by inserting dummy paddings.
The text was updated successfully, but these errors were encountered: