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Register neg_clk, and ddr_clk clock inputs, ban clock expresions #379

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Jacajack opened this issue Nov 25, 2023 · 0 comments
Open

Register neg_clk, and ddr_clk clock inputs, ban clock expresions #379

Jacajack opened this issue Nov 25, 2023 · 0 comments
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@Jacajack @WojciechPtas
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analyzer Related to semantic & design analyzers codegen Related to codegen implementation elaboration HIRN elaboration phase enhancement New feature or request hirn HIRN related next gen To be delivered in the next generation nice to have Only if we have time

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@Jacajack Jacajack added enhancement New feature or request codegen Related to codegen implementation analyzer Related to semantic & design analyzers hirn HIRN related elaboration HIRN elaboration phase labels Nov 25, 2023
@Jacajack Jacajack added the nice to have Only if we have time label Nov 25, 2023
@Jacajack Jacajack added the next gen To be delivered in the next generation label Dec 4, 2023
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@Jacajack Jacajack

@WojciechPtas WojciechPtas

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analyzer Related to semantic & design analyzers codegen Related to codegen implementation elaboration HIRN elaboration phase enhancement New feature or request hirn HIRN related next gen To be delivered in the next generation nice to have Only if we have time
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@Jacajack @WojciechPtas