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all(...), any(...) builtins equivalent to fold_and(join(...)) and fold_or(join(...)) respectively but all arguments must be wire. This will be helpful when writing long conditions
Internal improvment: represent registers and module instances the same way internally
Ban mixed wire/bus logic & arithmetic. Add to_wire() builtin for bus -> wire conversion and to_bus() for wire -> ubus<1> conversion. This should eliminate strange signedness deductions to unsigned when wire is used in an expression along with buses. (see test case 037_propagate_signedness.hirl)
msb(bus<N>), msb(bus<N>, int) builtins which select a certain number of most significant bits from an expression (analogous to trunc()). Perhaps lsb() could be an alias for trunc().
assertions (two types: as statements and expressions)
// statement form:assert(x ==0);
// embedded in expression (must have conditionals to make sense):wire x = (y ==0) ? z : (y ==1) ? w :unreachable("message");
// should result in following SV assertion being generatedassert(!(y ==1) &&!(y ==0));
ban clock operations
signal matrix operations (a big one)
The text was updated successfully, but these errors were encountered:
hdllang
zeros(n)
andones(n)
builtins #192all(...)
,any(...)
builtins equivalent tofold_and(join(...))
andfold_or(join(...))
respectively but all arguments must bewire
. This will be helpful when writing long conditionswire/bus
logic & arithmetic. Addto_wire()
builtin forbus -> wire
conversion andto_bus()
forwire -> ubus<1>
conversion. This should eliminate strange signedness deductions tounsigned
whenwire
is used in an expression along with buses. (see test case037_propagate_signedness.hirl
)msb(bus<N>)
,msb(bus<N>, int)
builtins which select a certain number of most significant bits from an expression (analogous totrunc()
). Perhapslsb()
could be an alias fortrunc()
.SV Codegen
generate
block namesalways_comb
for assignmentsalways_ff
for registersglobal
unused
keywordunused
#303reg
,bus
,ubus
,uint
Grammar update:unsigned int
#225sbus
andubus
would be really helpful and nicer than having to typeunsigned
/signed
reg
instead ofregister
(also covers 1 SV keyword)register_name.data
)bus
andwire
to be omitted in casts - width cannot be changed anyway (or even disallowbus
/wire
) #419clock
operationsThe text was updated successfully, but these errors were encountered: