Review Layout #69

Informaticore · 2021-01-19T22:54:22Z

MantaRayDeeJay · 2021-01-22T11:40:27Z

I think that we should improve the GND pins position on J9/J10

The goal is to do +3.3V and GND pins close together and to add a " virtual shield" between I2C signals and USB signals

MantaRayDeeJay · 2021-01-22T14:54:01Z

The copper layer 2 should be defined as a "Power Plane"

MantaRayDeeJay · 2021-01-22T15:07:29Z

The Layer 2 is defined as a power plane and should be a TRUE power plane without any tracks.
The GND plane must clean to avoid any "loop" effect.

On the ESP board, move the track on layer 3 or layer 4.
On the Charger board, move the track on layer 4.

MantaRayDeeJay · 2021-01-22T15:38:43Z

3v3_I2C plane shape could be optimized. Only draw the area you need. It will increase insulation distance between other power plane shapes.

MantaRayDeeJay · 2021-01-22T15:56:45Z

SilkScreen Layer : Max input Voltage can't be +20V (TPS63070 only accept 16V max).
PS : I have specified +15V max on the schematic.

#69

Informaticore · 2021-01-23T16:08:47Z

Add Silkscreen RefDes for Connectors

@MantaRayDeeJay they all got naming and description do you really need the ref?

Add more "Net Label" to improve the routing process (especially near the DC-DC converters/charger)

I don't understand what you mean with "Net Label", what are you referring to?

Add one 2pts connector/pads for each ouput voltage (+3.3V, +3.3V_MCU and +5V). We need to have the possibility to power sensors, external boards, display, etc. (even if the ESP board is connected)

I will try to add some

#69

MantaRayDeeJay · 2021-01-23T18:27:10Z

@Informaticore

Add more "Net Label" to improve the routing process (especially near the DC-DC converters/charger)

I don't understand what you mean with "Net Label", what are you referring to?

ANSWER
An example below (with one of the 2 DC-DC converters).
PS : It should be great to do it for the 2 DC-DC converters and for the LTC4162L charger chip
Then, I could continue the review easily on these 3 critical layouts.

Informaticore · 2021-01-23T18:46:46Z

okay - got it

MantaRayDeeJay · 2021-01-23T20:34:26Z

@Informaticore

Add Silkscreen RefDes for Connectors

@MantaRayDeeJay they all got naming and description do you really need the ref?

ANSWER
I think mainly about 2pts connectors because there are 4 on the board.
To avoid any confusion, I should recommend to add it. (sometimes, text on silkscreen and text on schematic are not always synchronized). The Ref. Des. stay the only unique ID for each component.

PS : Always think about newbies. (it should be easy for everyone !!!)

MantaRayDeeJay · 2021-01-23T22:17:03Z

@Informaticore

ESP32 module :
The recommanded layout use 12 vias on the Power GND Pad, I can see only one on the board.
I think, vias should be added at the footprint level.

Informaticore · 2021-01-23T22:34:26Z

@MantaRayDeeJay do you know how to add vias in a footprint?

I didn't try it yet.
I think that you could have a look on the footprint used by the LTC4162L to see how it is build (there are vias)

MantaRayDeeJay · 2021-01-24T09:56:59Z

ESP32 Module : Antenna Clearance

I can see that the recommanded clearances are not fully respected.
It should be 15mm min distance (not only 5mm)

⁣
⁣
Possible solution : Use a Mouting Hole without any copper shape and avoid the usage of metal screw (Nylon should be good).

Informaticore · 2021-01-24T11:02:53Z

We can go back to M2 holes but then we have to go everywhere, also on the charger board.

MantaRayDeeJay · 2021-01-24T11:18:15Z

@Informaticore

We can go back to M2 holes but then we have to go everywhere, also on the charger board.

ANSWER
You don't have enough space on the board to use M2.5 Mtg holes (currently 2.5mm hole diameter without enough clearance space from the edge of the board)
Therefore, we haven't any other choice than using M2 holes (2.2mm hole diameter)

PS : We can keep Mtg holes with copper shape for those on the opposite side of the ESP Module Antenna on the charger board.

Informaticore · 2021-01-24T11:29:07Z

I made all of them M2 (no pad) for consistency

MantaRayDeeJay · 2021-01-24T16:04:25Z

@Informaticore

@MantaRayDeeJay do you know how to add vias in a footprint?

I didn't try it yet.
I think that you could have a look on the footprint used by the LTC4162L to see how it is build (there are vias)

UPDATE

Adding Vias in a footprint is the same way as adding padstacks. (all vias pin numbers must be the same as the EPAD padstack)

I have updated the ESP32 module footprint : Epad 3x3 matrix + vias (as recommended on the datasheet)
ESP32-WROOM-32_EPAD_3x3_ThermalVias.zip

MantaRayDeeJay · 2021-01-24T16:33:07Z

@Informaticore

Schematic - Max USB Current settings

Currently, the max current setting for the USB port is 3A.
But the reverse protection diode can sink only 2A max.
Moreover, Max current used by the board is limited to 500mA (LTC4162 settings) to be compliant with USB2 devices.

I think we should limit the USB current to 1.5A for safety.

MantaRayDeeJay · 2021-01-24T17:58:38Z

@Informaticore

CP2102N : QFN28 footprint

I think you should use the "ThermalVias" Version (I think, only 1 via is not enough)
PS : Via hole diameters are defined with 0.2mm. You should redefine them to 0.3mm. (idem as Sethkaz Review)

MantaRayDeeJay · 2021-01-26T18:04:16Z

@Informaticore

Power Vdd net is not well routed. (track width = 0.25mm)
You should use wider copper tracks and copper shape

MantaRayDeeJay · 2021-01-26T18:30:24Z

@Informaticore

Same thing for the "net-(Q3-Pad1)" between MOSFET (Q3) and Rsense (R13)

MantaRayDeeJay · 2021-01-26T23:04:09Z

@Informaticore

LTC4162-L Layout

Apply the recommended rules from the Datasheet (p. 35)

DC2038A Demo Board Layout

MantaRayDeeJay · 2021-01-27T08:15:46Z

@Informaticore

Vdd Plane shape issue

On layer 4, the "Vdd" plane shape is inner the "GND" plane shape.
As you can see, the "GND" plane is generated first and then the "Vdd" plane is not well generated.

The trick is to increase the "Zone Priority Level" feature on the Filled Zone properties dialog box.

Informaticore · 2021-01-27T08:26:37Z

@Informaticore

LTC4162-L Layout

Apply the recommended rules from the Datasheet (p. 35)

this will be a bigger refactor and change. I will try to do that.

Informaticore · 2021-01-27T08:27:55Z

@Informaticore

Vdd Plane shape issue

On layer 4, the "Vdd" plane shape is inner the "GND" plane shape.
As you can see, the "GND" plane is generated first and then the "Vdd" plane is not well generated.

The trick is to increase the "Zone Priority Level" feature on the Filled Zone properties dialog box.

I know, I forgot about it but strangely the DRC was not warning about it!! That is very bad, it shows 0 issues. Do you see DRC complaining?

MantaRayDeeJay · 2021-01-27T11:15:10Z

@Informaticore

Vdd Plane shape issue

On layer 4, the "Vdd" plane shape is inner the "GND" plane shape.
As you can see, the "GND" plane is generated first and then the "Vdd" plane is not well generated.

The trick is to increase the "Zone Priority Level" feature on the Filled Zone properties dialog box.

I know, I forgot about it but strangely the DRC was not warning about it!! That is very bad, it shows 0 issues. Do you see DRC complaining?

ANSWER

YES, I can see it !!!

⁣
By setting "Zone Priority Level" = 1, DRC is clean as you can see below !!!
⁣

MantaRayDeeJay · 2021-01-28T17:32:44Z

@Informaticore

LTC4162-L Layout

Apply the recommended rules from the Datasheet (p. 35)

this will be a bigger refactor and change. I will try to do that.

NEXT

This is better but it can be improved.

Informaticore · 2021-01-29T08:40:26Z

@MantaRayDeeJay I applied more changes but I am not 100% about you drawings, please describe a bit more what else should be changed. But I think I got most of it, please check. All the thick traces are thick now, should be good.

MantaRayDeeJay · 2021-01-29T19:58:13Z

@Informaticore

@MantaRayDeeJay I applied more changes but I am not 100% about you drawings, please describe a bit more what else should be changed. But I think I got most of it, please check. All the thick traces are thick now, should be good.

ANSWER
I would like VBat Capacitor (C6) and Rsense (R20) as the recommanded layout used on the DEMO Board.
By moving J2, you should have enough place to do it.
Moreover, you should keep the RTC chip and Battery protection circuitry enough away from the inductor. (You can also add a shield GND plane around the Inductorr with some Vias on the layer Top)

MantaRayDeeJay · 2021-01-29T20:12:12Z

@Informaticore

TPS63070 - Footprint Issue

Pin 12-13 copper area is wrong for the soldermask and solderpast layer.
UPDATED (2021-01-30) :
Pin 12-13 seems OK (I don't know what was it happend)

The footprint is SMT !!! (not THT)

You must delete any global solderpast and soldermask layers on all copper pads. (The footprint countains custom solderpast and soldermask copper shapes)
-> Check all copper pads
UPDATED (2021-01-30) :
All pads which countain solderpast layer don't have any custom solderpast copper shape, therefore, we should also create custom solderpast copper shapes (to keep the footprint consistency)

MantaRayDeeJay · 2021-01-30T11:33:11Z

@Informaticore

TPS63070 : Apply the recommanded Layout

Place C1 and C4 as Figure 51 (C19 & C24 for U9 and C21 & C25 for U10)
Route L1 and L2 nets as Figure 51 (use vias under pads)
Add a gnd shield around the inductor on the top layer as Figure 51

#69

MantaRayDeeJay · 2021-01-30T16:07:02Z

@Informaticore

Maybe I found critical signals too near the LTC4162-L inductor without GND shield on top layer.
I recommand to keep away critical signal near inductors.
In this case, it concerns 2 MOSFET gate pin (Q1 and Q5).