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x393_hispi.timing_summary_impl
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x393_hispi.timing_summary_impl
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Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
------------------------------------------------------------------------------------
| Tool Version : Vivado v.2017.4 (lin64) Build 2086221 Fri Dec 15 20:54:30 MST 2017
| Date : Thu Apr 4 13:44:26 2019
| Host : elphel-desktop running 64-bit Ubuntu 14.04.5 LTS
| Command : report_timing_summary -file vivado_build/x393.timing_summary_impl
| Design : x393
| Device : 7z030-fbg484
| Speed File : -1 PRODUCTION 1.11 2014-09-11
------------------------------------------------------------------------------------
Timing Summary Report
------------------------------------------------------------------------------------------------
| Timer Settings
| --------------
------------------------------------------------------------------------------------------------
Enable Multi Corner Analysis : Yes
Enable Pessimism Removal : Yes
Pessimism Removal Resolution : Nearest Common Node
Enable Input Delay Default Clock : No
Enable Preset / Clear Arcs : No
Disable Flight Delays : No
Ignore I/O Paths : No
Timing Early Launch at Borrowing Latches : false
Corner Analyze Analyze
Name Max Paths Min Paths
------ --------- ---------
Slow Yes Yes
Fast Yes Yes
check_timing report
Table of Contents
-----------------
1. checking no_clock
2. checking constant_clock
3. checking pulse_width_clock
4. checking unconstrained_internal_endpoints
5. checking no_input_delay
6. checking no_output_delay
7. checking multiple_clock
8. checking generated_clocks
9. checking loops
10. checking partial_input_delay
11. checking partial_output_delay
12. checking latch_loops
1. checking no_clock
--------------------
There are 16 register/latch pins with no clock driven by root clock pin: DQSL (HIGH)
There are 16 register/latch pins with no clock driven by root clock pin: DQSU (HIGH)
There is 1 register/latch pin with no clock driven by root clock pin: ffclk1p (HIGH)
There is 1 register/latch pin with no clock driven by root clock pin: memclk (HIGH)
There are 436 register/latch pins with no clock driven by root clock pin: sns1_clkp (HIGH)
There are 436 register/latch pins with no clock driven by root clock pin: sns2_clkp (HIGH)
There are 436 register/latch pins with no clock driven by root clock pin: sns3_clkp (HIGH)
There are 436 register/latch pins with no clock driven by root clock pin: sns4_clkp (HIGH)
2. checking constant_clock
--------------------------
There are 0 register/latch pins with constant_clock.
3. checking pulse_width_clock
-----------------------------
There are 0 register/latch pins which need pulse_width check
4. checking unconstrained_internal_endpoints
--------------------------------------------
There are 4100 pins that are not constrained for maximum delay. (HIGH)
There are 0 pins that are not constrained for maximum delay due to constant clock.
5. checking no_input_delay
--------------------------
There are 62 input ports with no input delay specified. (HIGH)
There are 0 input ports with no input delay but user has a false path constraint.
6. checking no_output_delay
---------------------------
There are 95 ports with no output delay specified. (HIGH)
There are 0 ports with no output delay but user has a false path constraint
There are 0 ports with no output delay but with a timing clock defined on it or propagating through it
7. checking multiple_clock
--------------------------
There are 0 register/latch pins with multiple clocks.
8. checking generated_clocks
----------------------------
There are 0 generated clocks that are not connected to a clock source.
9. checking loops
-----------------
There are 0 combinational loops in the design.
10. checking partial_input_delay
--------------------------------
There are 0 input ports with partial input delay specified.
11. checking partial_output_delay
---------------------------------
There are 0 ports with partial output delay specified.
12. checking latch_loops
------------------------
There are 0 combinational latch loops in the design through latch input
------------------------------------------------------------------------------------------------
| Design Timing Summary
| ---------------------
------------------------------------------------------------------------------------------------
WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints
------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- --------------------
0.006 0.000 0 148663 0.022 0.000 0 148663 0.264 0.000 0 60733
All user specified timing constraints are met.
------------------------------------------------------------------------------------------------
| Clock Summary
| -------------
------------------------------------------------------------------------------------------------
Clock Waveform(ns) Period(ns) Frequency(MHz)
----- ------------ ---------- --------------
axi_aclk {0.000 10.000} 20.000 50.000
axihp_clk {0.000 3.333} 6.667 150.000
clk_fb {0.000 10.000} 20.000 50.000
ddr3_clk {0.000 1.250} 2.500 400.000
ddr3_clk_div {0.000 2.500} 5.000 200.000
ddr3_clk_ref {0.000 2.500} 5.000 200.000
ddr3_mclk {1.250 3.750} 5.000 200.000
ddr3_sdclk {0.000 1.250} 2.500 400.000
multi_clkfb {0.000 10.000} 20.000 50.000
sclk {0.000 5.000} 10.000 100.000
xclk {0.000 2.083} 4.167 240.000
ffclk0 {0.000 20.833} 41.667 24.000
clkfb {0.000 20.833} 41.667 24.000
pclk {0.000 2.315} 4.630 215.998
gtrefclk {0.000 3.333} 6.666 150.015
rx_clk {0.000 3.333} 6.666 150.015
txoutclk {0.000 3.333} 6.666 150.015
usrclk2 {0.000 6.666} 13.333 75.002
------------------------------------------------------------------------------------------------
| Intra Clock Table
| -----------------
------------------------------------------------------------------------------------------------
Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints
----- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- --------------------
axi_aclk 14.087 0.000 0 2685 0.055 0.000 0 2685 7.000 0.000 0 737
axihp_clk 0.379 0.000 0 10209 0.055 0.000 0 10209 0.267 0.000 0 3863
clk_fb 18.751 0.000 0 2
ddr3_clk 0.279 0.000 0 45
ddr3_clk_div 0.262 0.000 0 2158 0.137 0.000 0 2158 1.389 0.000 0 755
ddr3_clk_ref 0.264 0.000 0 5
ddr3_mclk 0.131 0.000 0 81699 0.022 0.000 0 81699 1.389 0.000 0 33130
ddr3_sdclk 1.092 0.000 0 3
multi_clkfb 18.751 0.000 0 2
sclk 4.184 0.000 0 2740 0.056 0.000 0 2740 4.090 0.000 0 1349
xclk 0.029 0.000 0 33043 0.043 0.000 0 33043 0.875 0.000 0 13479
ffclk0 40.600 0.000 0 1 0.397 0.000 0 1 10.833 0.000 0 2
clkfb 10.966 0.000 0 2
pclk 0.204 0.000 0 9523 0.042 0.000 0 9523 1.405 0.000 0 4843
gtrefclk 3.851 0.000 0 45 0.253 0.000 0 45 2.553 0.000 0 25
rx_clk 0.312 0.000 0 917 0.087 0.000 0 917 2.423 0.000 0 329
txoutclk 2.057 0.000 0 232 0.179 0.000 0 232 2.666 0.000 0 138
usrclk2 4.647 0.000 0 4576 0.059 0.000 0 4576 5.756 0.000 0 2024
------------------------------------------------------------------------------------------------
| Inter Clock Table
| -----------------
------------------------------------------------------------------------------------------------
From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints
---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- -------------------
ddr3_clk_div ddr3_clk 0.084 0.000 0 23 0.155 0.000 0 23
ddr3_mclk ddr3_clk_div 0.006 0.000 0 146 1.357 0.000 0 146
ddr3_clk_div ddr3_mclk 2.860 0.000 0 76 0.273 0.000 0 76
------------------------------------------------------------------------------------------------
| Other Path Groups Table
| -----------------------
------------------------------------------------------------------------------------------------
Path Group From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints
---------- ---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- -------------------
**async_default** axihp_clk axihp_clk 1.841 0.000 0 23 0.617 0.000 0 23
**async_default** ddr3_mclk ddr3_mclk 0.375 0.000 0 453 0.275 0.000 0 453
**async_default** pclk pclk 0.508 0.000 0 20 0.356 0.000 0 20
**async_default** sclk sclk 5.006 0.000 0 16 0.288 0.000 0 16
**async_default** usrclk2 usrclk2 5.183 0.000 0 7 0.984 0.000 0 7
**async_default** xclk xclk 0.650 0.000 0 72 0.388 0.000 0 72
------------------------------------------------------------------------------------------------
| Timing Details
| --------------
------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
From Clock: axi_aclk
To Clock: axi_aclk
Setup : 0 Failing Endpoints, Worst Slack 14.087ns, Total Violation 0.000ns
Hold : 0 Failing Endpoints, Worst Slack 0.055ns, Total Violation 0.000ns
PW : 0 Failing Endpoints, Worst Slack 7.000ns, Total Violation 0.000ns
---------------------------------------------------------------------------------------------------
Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) : 14.087ns (required time - arrival time)
Source: mcntrl393_i/select_buf3rd_reg/C
(rising edge-triggered cell FDRE clocked by axi_aclk {[email protected] [email protected] period=20.000ns})
Destination: ps7_i/MAXIGP0RDATA[2]
(rising edge-triggered cell PS7 clocked by axi_aclk {[email protected] [email protected] period=20.000ns})
Path Group: axi_aclk
Path Type: Setup (Max at Slow Process Corner)
Requirement: 20.000ns (axi_aclk [email protected] - axi_aclk [email protected])
Data Path Delay: 5.361ns (logic 0.510ns (9.513%) route 4.851ns (90.487%))
Logic Levels: 3 (LUT4=1 LUT5=1 LUT6=1)
Clock Path Skew: 0.034ns (DCD - SCD + CPR)
Destination Clock Delay (DCD): 1.336ns = ( 21.336 - 20.000 )
Source Clock Delay (SCD): 1.391ns
Clock Pessimism Removal (CPR): 0.089ns
Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
Total System Jitter (TSJ): 0.071ns
Total Input Jitter (TIJ): 0.000ns
Discrete Jitter (DJ): 0.000ns
Phase Error (PE): 0.000ns
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
------------------------------------------------------------------- -------------------
(clock axi_aclk rise edge)
0.000 0.000 r
BUFGCTRL_X0Y23 BUFG 0.000 0.000 r clocks393_i/bufg_axi_aclk_i/O
net (fo=738, routed) 1.391 1.391 mcntrl393_i/axi_clk
SLICE_X40Y148 FDRE r mcntrl393_i/select_buf3rd_reg/C
------------------------------------------------------------------- -------------------
SLICE_X40Y148 FDRE (Prop_fdre_C_Q) 0.246 1.637 r mcntrl393_i/select_buf3rd_reg/Q
net (fo=34, routed) 1.849 3.486 cmd_readback_i/lopt_3
SLICE_X70Y139 LUT4 (Prop_lut4_I3_O) 0.158 3.644 r cmd_readback_i/xlnx_opt_LUT_ps7_i_i_59/O
net (fo=1, routed) 1.032 4.676 cmd_readback_i/xlnx_opt_MAXIGP0RDATA[2]_1
SLICE_X56Y139 LUT5 (Prop_lut5_I4_O) 0.053 4.729 r cmd_readback_i/xlnx_opt_LUT_ps7_i_i_59_1/O
net (fo=1, routed) 1.116 5.845 cmd_readback_i/xlnx_opt_MAXIGP0RDATA[2]
SLICE_X41Y150 LUT6 (Prop_lut6_I5_O) 0.053 5.898 r cmd_readback_i/xlnx_opt_LUT_ps7_i_i_59_2/O
net (fo=1, routed) 0.854 6.752 axird_rdata[2]
PS7_X0Y0 PS7 r ps7_i/MAXIGP0RDATA[2]
------------------------------------------------------------------- -------------------
(clock axi_aclk rise edge)
20.000 20.000 r
BUFGCTRL_X0Y23 BUFG 0.000 20.000 r clocks393_i/bufg_axi_aclk_i/O
net (fo=738, routed) 1.336 21.336 axi_aclk
PS7_X0Y0 PS7 r ps7_i/MAXIGP0ACLK
clock pessimism 0.089 21.425
clock uncertainty -0.035 21.390
PS7_X0Y0 PS7 (Setup_ps7_MAXIGP0ACLK_MAXIGP0RDATA[2])
-0.550 20.840 ps7_i
-------------------------------------------------------------------
required time 20.840
arrival time -6.752
-------------------------------------------------------------------
slack 14.087
Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) : 0.055ns (arrival time - required time)
Source: axibram_write_i/wdata_i/inreg_reg[38]/C
(rising edge-triggered cell FDRE clocked by axi_aclk {[email protected] [email protected] period=20.000ns})
Destination: axibram_write_i/wdata_i/ram_reg_0_15_36_41/RAMB/I
(rising edge-triggered cell RAMD32 clocked by axi_aclk {[email protected] [email protected] period=20.000ns})
Path Group: axi_aclk
Path Type: Hold (Min at Fast Process Corner)
Requirement: 0.000ns (axi_aclk [email protected] - axi_aclk [email protected])
Data Path Delay: 0.201ns (logic 0.100ns (49.726%) route 0.101ns (50.274%))
Logic Levels: 0
Clock Path Skew: 0.014ns (DCD - SCD - CPR)
Destination Clock Delay (DCD): 0.857ns
Source Clock Delay (SCD): 0.632ns
Clock Pessimism Removal (CPR): 0.211ns
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
------------------------------------------------------------------- -------------------
(clock axi_aclk rise edge)
0.000 0.000 r
BUFGCTRL_X0Y23 BUFG 0.000 0.000 r clocks393_i/bufg_axi_aclk_i/O
net (fo=738, routed) 0.632 0.632 axibram_write_i/wdata_i/axi_clk
SLICE_X28Y154 FDRE r axibram_write_i/wdata_i/inreg_reg[38]/C
------------------------------------------------------------------- -------------------
SLICE_X28Y154 FDRE (Prop_fdre_C_Q) 0.100 0.732 r axibram_write_i/wdata_i/inreg_reg[38]/Q
net (fo=1, routed) 0.101 0.833 axibram_write_i/wdata_i/ram_reg_0_15_36_41/DIB0
SLICE_X30Y154 RAMD32 r axibram_write_i/wdata_i/ram_reg_0_15_36_41/RAMB/I
------------------------------------------------------------------- -------------------
(clock axi_aclk rise edge)
0.000 0.000 r
BUFGCTRL_X0Y23 BUFG 0.000 0.000 r clocks393_i/bufg_axi_aclk_i/O
net (fo=738, routed) 0.857 0.857 axibram_write_i/wdata_i/ram_reg_0_15_36_41/WCLK
SLICE_X30Y154 RAMD32 r axibram_write_i/wdata_i/ram_reg_0_15_36_41/RAMB/CLK
clock pessimism -0.211 0.646
SLICE_X30Y154 RAMD32 (Hold_ramd32_CLK_I)
0.132 0.778 axibram_write_i/wdata_i/ram_reg_0_15_36_41/RAMB
-------------------------------------------------------------------
required time -0.778
arrival time 0.833
-------------------------------------------------------------------
slack 0.055
Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name: axi_aclk
Waveform(ns): { 0.000 10.000 }
Period(ns): 20.000
Sources: { clocks393_i/bufg_axi_aclk_i/O }
Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin
Min Period n/a RAMB36E1/CLKBWRCLK n/a 2.183 20.000 17.817 RAMB36_X3Y30 cmd_readback_i/ram_reg_0/CLKBWRCLK
Max Period n/a PLLE2_ADV/CLKIN1 n/a 52.633 20.000 32.633 PLLE2_ADV_X1Y2 clocks393_i/pll_base_i/PLLE2_ADV_i/CLKIN1
Low Pulse Width Slow PLLE2_ADV/CLKIN1 n/a 3.000 10.000 7.000 PLLE2_ADV_X1Y2 clocks393_i/pll_base_i/PLLE2_ADV_i/CLKIN1
High Pulse Width Slow PLLE2_ADV/CLKIN1 n/a 3.000 10.000 7.000 PLLE2_ADV_X1Y2 clocks393_i/pll_base_i/PLLE2_ADV_i/CLKIN1
---------------------------------------------------------------------------------------------------
From Clock: axihp_clk
To Clock: axihp_clk
Setup : 0 Failing Endpoints, Worst Slack 0.379ns, Total Violation 0.000ns
Hold : 0 Failing Endpoints, Worst Slack 0.055ns, Total Violation 0.000ns
PW : 0 Failing Endpoints, Worst Slack 0.267ns, Total Violation 0.000ns
---------------------------------------------------------------------------------------------------
Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) : 0.379ns (required time - arrival time)
Source: sync_resets_i/rst_block[6].level_cross_clocks_rst_i/level_cross_clock_block[0].level_cross_clocks_single_i/regs_reg[1]/C
(rising edge-triggered cell FDRE clocked by axihp_clk {[email protected] [email protected] period=6.667ns})
Destination: sata_top/ahci_sata_layers_i/phy/gtx_wrap/drp_other_registers_i/drp_register1_r_reg[11]/R
(rising edge-triggered cell FDRE clocked by axihp_clk {[email protected] [email protected] period=6.667ns})
Path Group: axihp_clk
Path Type: Setup (Max at Slow Process Corner)
Requirement: 6.667ns (axihp_clk [email protected] - axihp_clk [email protected])
Data Path Delay: 5.928ns (logic 0.282ns (4.757%) route 5.646ns (95.243%))
Logic Levels: 0
Clock Path Skew: 0.158ns (DCD - SCD + CPR)
Destination Clock Delay (DCD): 4.739ns = ( 11.406 - 6.667 )
Source Clock Delay (SCD): 4.817ns
Clock Pessimism Removal (CPR): 0.236ns
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
Total System Jitter (TSJ): 0.071ns
Discrete Jitter (DJ): 0.124ns
Phase Error (PE): 0.000ns
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
------------------------------------------------------------------- -------------------
(clock axihp_clk rise edge)
0.000 0.000 r
BUFGCTRL_X0Y23 BUFG 0.000 0.000 r clocks393_i/bufg_axi_aclk_i/O
net (fo=738, routed) 1.602 1.602 clocks393_i/pll_base_i/axi_clk
PLLE2_ADV_X1Y2 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
0.088 1.690 r clocks393_i/pll_base_i/PLLE2_ADV_i/CLKOUT0
net (fo=1, routed) 1.621 3.311 clocks393_i/hclk_i/hclk_pre
BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.120 3.431 r clocks393_i/hclk_i/clk1x_i/O
net (fo=3868, routed) 1.386 4.817 sync_resets_i/rst_block[6].level_cross_clocks_rst_i/level_cross_clock_block[0].level_cross_clocks_single_i/hclk
SLICE_X34Y113 FDRE r sync_resets_i/rst_block[6].level_cross_clocks_rst_i/level_cross_clock_block[0].level_cross_clocks_single_i/regs_reg[1]/C
------------------------------------------------------------------- -------------------
SLICE_X34Y113 FDRE (Prop_fdre_C_Q) 0.282 5.099 r sync_resets_i/rst_block[6].level_cross_clocks_rst_i/level_cross_clock_block[0].level_cross_clocks_single_i/regs_reg[1]/Q
net (fo=335, routed) 5.646 10.745 sata_top/ahci_sata_layers_i/phy/gtx_wrap/drp_other_registers_i/regs_reg[1][0]
SLICE_X106Y2 FDRE r sata_top/ahci_sata_layers_i/phy/gtx_wrap/drp_other_registers_i/drp_register1_r_reg[11]/R
------------------------------------------------------------------- -------------------
(clock axihp_clk rise edge)
6.667 6.667 r
BUFGCTRL_X0Y23 BUFG 0.000 6.667 r clocks393_i/bufg_axi_aclk_i/O
net (fo=738, routed) 1.461 8.128 clocks393_i/pll_base_i/axi_clk
PLLE2_ADV_X1Y2 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
0.083 8.211 r clocks393_i/pll_base_i/PLLE2_ADV_i/CLKOUT0
net (fo=1, routed) 1.538 9.749 clocks393_i/hclk_i/hclk_pre
BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.113 9.862 r clocks393_i/hclk_i/clk1x_i/O
net (fo=3868, routed) 1.544 11.406 sata_top/ahci_sata_layers_i/phy/gtx_wrap/drp_other_registers_i/hclk
SLICE_X106Y2 FDRE r sata_top/ahci_sata_layers_i/phy/gtx_wrap/drp_other_registers_i/drp_register1_r_reg[11]/C
clock pessimism 0.236 11.642
clock uncertainty -0.071 11.570
SLICE_X106Y2 FDRE (Setup_fdre_C_R) -0.446 11.124 sata_top/ahci_sata_layers_i/phy/gtx_wrap/drp_other_registers_i/drp_register1_r_reg[11]
-------------------------------------------------------------------
required time 11.124
arrival time -10.745
-------------------------------------------------------------------
slack 0.379
Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) : 0.055ns (arrival time - required time)
Source: sata_top/ahci_top_i/axi_ahci_regs_i/axibram_read_i/raddr_i/inreg_reg[7]/C
(rising edge-triggered cell FDRE clocked by axihp_clk {[email protected] [email protected] period=6.667ns})
Destination: sata_top/ahci_top_i/axi_ahci_regs_i/axibram_read_i/raddr_i/ram_reg_0_15_6_11/RAMA_D1/I
(rising edge-triggered cell RAMD32 clocked by axihp_clk {[email protected] [email protected] period=6.667ns})
Path Group: axihp_clk
Path Type: Hold (Min at Fast Process Corner)
Requirement: 0.000ns (axihp_clk [email protected] - axihp_clk [email protected])
Data Path Delay: 0.279ns (logic 0.100ns (35.808%) route 0.179ns (64.192%))
Logic Levels: 0
Clock Path Skew: 0.116ns (DCD - SCD - CPR)
Destination Clock Delay (DCD): 2.286ns
Source Clock Delay (SCD): 1.872ns
Clock Pessimism Removal (CPR): 0.298ns
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
------------------------------------------------------------------- -------------------
(clock axihp_clk rise edge)
0.000 0.000 r
BUFGCTRL_X0Y23 BUFG 0.000 0.000 r clocks393_i/bufg_axi_aclk_i/O
net (fo=738, routed) 0.586 0.586 clocks393_i/pll_base_i/axi_clk
PLLE2_ADV_X1Y2 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
0.050 0.636 r clocks393_i/pll_base_i/PLLE2_ADV_i/CLKOUT0
net (fo=1, routed) 0.577 1.213 clocks393_i/hclk_i/hclk_pre
BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 1.239 r clocks393_i/hclk_i/clk1x_i/O
net (fo=3868, routed) 0.633 1.872 sata_top/ahci_top_i/axi_ahci_regs_i/axibram_read_i/raddr_i/hclk
SLICE_X29Y152 FDRE r sata_top/ahci_top_i/axi_ahci_regs_i/axibram_read_i/raddr_i/inreg_reg[7]/C
------------------------------------------------------------------- -------------------
SLICE_X29Y152 FDRE (Prop_fdre_C_Q) 0.100 1.972 r sata_top/ahci_top_i/axi_ahci_regs_i/axibram_read_i/raddr_i/inreg_reg[7]/Q
net (fo=1, routed) 0.179 2.151 sata_top/ahci_top_i/axi_ahci_regs_i/axibram_read_i/raddr_i/ram_reg_0_15_6_11/DIA1
SLICE_X30Y145 RAMD32 r sata_top/ahci_top_i/axi_ahci_regs_i/axibram_read_i/raddr_i/ram_reg_0_15_6_11/RAMA_D1/I
------------------------------------------------------------------- -------------------
(clock axihp_clk rise edge)
0.000 0.000 r
BUFGCTRL_X0Y23 BUFG 0.000 0.000 r clocks393_i/bufg_axi_aclk_i/O
net (fo=738, routed) 0.803 0.803 clocks393_i/pll_base_i/axi_clk
PLLE2_ADV_X1Y2 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
0.053 0.856 r clocks393_i/pll_base_i/PLLE2_ADV_i/CLKOUT0
net (fo=1, routed) 0.643 1.499 clocks393_i/hclk_i/hclk_pre
BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.030 1.529 r clocks393_i/hclk_i/clk1x_i/O
net (fo=3868, routed) 0.757 2.286 sata_top/ahci_top_i/axi_ahci_regs_i/axibram_read_i/raddr_i/ram_reg_0_15_6_11/WCLK
SLICE_X30Y145 RAMD32 r sata_top/ahci_top_i/axi_ahci_regs_i/axibram_read_i/raddr_i/ram_reg_0_15_6_11/RAMA_D1/CLK
clock pessimism -0.298 1.988
SLICE_X30Y145 RAMD32 (Hold_ramd32_CLK_I)
0.108 2.096 sata_top/ahci_top_i/axi_ahci_regs_i/axibram_read_i/raddr_i/ram_reg_0_15_6_11/RAMA_D1
-------------------------------------------------------------------
required time -2.096
arrival time 2.151
-------------------------------------------------------------------
slack 0.055
Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name: axihp_clk
Waveform(ns): { 0.000 3.333 }
Period(ns): 6.667
Sources: { clocks393_i/pll_base_i/PLLE2_ADV_i/CLKOUT0 }
Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin
Min Period n/a GTXE2_CHANNEL/DRPCLK n/a 6.400 6.667 0.267 GTXE2_CHANNEL_X0Y0 sata_top/ahci_sata_layers_i/phy/gtx_wrap/gtxe2_channel_wrapper/gtx_unisims/DRPCLK
Max Period n/a PLLE2_ADV/CLKOUT0 n/a 160.000 6.667 153.333 PLLE2_ADV_X1Y2 clocks393_i/pll_base_i/PLLE2_ADV_i/CLKOUT0
Low Pulse Width Slow RAMD32/CLK n/a 0.910 3.333 2.423 SLICE_X26Y119 sata_top/ahci_top_i/ahci_dma_i/ahci_dma_rd_fifo_i/fifo_ram_reg_0_7_60_63/RAMA/CLK
High Pulse Width Slow RAMD32/CLK n/a 0.910 3.333 2.423 SLICE_X26Y122 sata_top/ahci_top_i/ahci_dma_i/ahci_dma_rd_fifo_i/fifo_ram_reg_0_7_12_17/RAMA/CLK
---------------------------------------------------------------------------------------------------
From Clock: clk_fb
To Clock: clk_fb
Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA
Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA
PW : 0 Failing Endpoints, Worst Slack 18.751ns, Total Violation 0.000ns
---------------------------------------------------------------------------------------------------
Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name: clk_fb
Waveform(ns): { 0.000 10.000 }
Period(ns): 20.000
Sources: { mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKFBOUT }
Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin
Min Period n/a MMCME2_ADV/CLKFBOUT n/a 1.249 20.000 18.751 MMCME2_ADV_X1Y2 mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKFBOUT
Max Period n/a MMCME2_ADV/CLKFBIN n/a 100.000 20.000 80.000 MMCME2_ADV_X1Y2 mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKFBIN
---------------------------------------------------------------------------------------------------
From Clock: ddr3_clk
To Clock: ddr3_clk
Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA
Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA
PW : 0 Failing Endpoints, Worst Slack 0.279ns, Total Violation 0.000ns
---------------------------------------------------------------------------------------------------
Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name: ddr3_clk
Waveform(ns): { 0.000 1.250 }
Period(ns): 2.500
Sources: { mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKOUT1 }
Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin
Min Period n/a BUFR/I n/a 2.221 2.500 0.279 BUFR_X1Y8 mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/clk_bufr_i/I
Max Period n/a MMCME2_ADV/CLKOUT1 n/a 213.360 2.500 210.860 MMCME2_ADV_X1Y2 mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKOUT1
---------------------------------------------------------------------------------------------------
From Clock: ddr3_clk_div
To Clock: ddr3_clk_div
Setup : 0 Failing Endpoints, Worst Slack 0.262ns, Total Violation 0.000ns
Hold : 0 Failing Endpoints, Worst Slack 0.137ns, Total Violation 0.000ns
PW : 0 Failing Endpoints, Worst Slack 1.389ns, Total Violation 0.000ns
---------------------------------------------------------------------------------------------------
Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) : 0.262ns (required time - arrival time)
Source: mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/dly_addr_r_reg[0]/C
(rising edge-triggered cell FDRE clocked by ddr3_clk_div {[email protected] [email protected] period=5.000ns})
Destination: mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/cmd_addr_i/ld_dly_addr_reg[6]/D
(rising edge-triggered cell FDRE clocked by ddr3_clk_div {[email protected] [email protected] period=5.000ns})
Path Group: ddr3_clk_div
Path Type: Setup (Max at Slow Process Corner)
Requirement: 5.000ns (ddr3_clk_div [email protected] - ddr3_clk_div [email protected])
Data Path Delay: 4.587ns (logic 0.322ns (7.020%) route 4.265ns (92.980%))
Logic Levels: 1 (LUT6=1)
Clock Path Skew: -0.137ns (DCD - SCD + CPR)
Destination Clock Delay (DCD): 3.526ns = ( 8.526 - 5.000 )
Source Clock Delay (SCD): 3.919ns
Clock Pessimism Removal (CPR): 0.256ns
Clock Uncertainty: 0.085ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
Total System Jitter (TSJ): 0.071ns
Discrete Jitter (DJ): 0.156ns
Phase Error (PE): 0.000ns
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
------------------------------------------------------------------- -------------------
(clock ddr3_clk_div rise edge)
0.000 0.000 r
BUFGCTRL_X0Y23 BUFG 0.000 0.000 r clocks393_i/bufg_axi_aclk_i/O
net (fo=738, routed) 1.575 1.575 mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/axi_clk
MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT2)
0.088 1.663 r mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKOUT2
net (fo=1, routed) 1.106 2.769 mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/clk_div_pre
BUFR_X1Y9 BUFR (Prop_bufr_I_O) 0.377 3.146 r mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/clk_div_bufr_i/O
net (fo=753, routed) 0.773 3.919 mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/clk_div
SLICE_X71Y123 FDRE r mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/dly_addr_r_reg[0]/C
------------------------------------------------------------------- -------------------
SLICE_X71Y123 FDRE (Prop_fdre_C_Q) 0.269 4.188 f mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/dly_addr_r_reg[0]/Q
net (fo=62, routed) 4.265 8.453 mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/cmd_addr_i/dly_addr_r_reg[6][0]
SLICE_X118Y145 LUT6 (Prop_lut6_I3_O) 0.053 8.506 r mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/cmd_addr_i/ld_dly_addr[6]_i_1/O
net (fo=1, routed) 0.000 8.506 mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/cmd_addr_i/ld_dly_addr[6]_i_1_n_0
SLICE_X118Y145 FDRE r mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/cmd_addr_i/ld_dly_addr_reg[6]/D
------------------------------------------------------------------- -------------------
(clock ddr3_clk_div rise edge)
5.000 5.000 r
BUFGCTRL_X0Y23 BUFG 0.000 5.000 r clocks393_i/bufg_axi_aclk_i/O
net (fo=738, routed) 1.437 6.437 mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/axi_clk
MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT2)
0.083 6.520 r mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKOUT2
net (fo=1, routed) 1.016 7.536 mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/clk_div_pre
BUFR_X1Y9 BUFR (Prop_bufr_I_O) 0.370 7.906 r mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/clk_div_bufr_i/O
net (fo=753, routed) 0.620 8.526 mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/cmd_addr_i/psincdec_reg
SLICE_X118Y145 FDRE r mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/cmd_addr_i/ld_dly_addr_reg[6]/C
clock pessimism 0.256 8.782
clock uncertainty -0.085 8.697
SLICE_X118Y145 FDRE (Setup_fdre_C_D) 0.071 8.768 mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/cmd_addr_i/ld_dly_addr_reg[6]
-------------------------------------------------------------------
required time 8.768
arrival time -8.506
-------------------------------------------------------------------
slack 0.262
Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) : 0.137ns (arrival time - required time)
Source: mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/byte_lane1_i/dq_block[1].dq_i/dq_in_dly_i/fdly_pre_reg[1]/C
(rising edge-triggered cell FDRE clocked by ddr3_clk_div {[email protected] [email protected] period=5.000ns})
Destination: mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/byte_lane1_i/dq_block[1].dq_i/dq_in_dly_i/fdly_reg[1]/D
(rising edge-triggered cell FDRE clocked by ddr3_clk_div {[email protected] [email protected] period=5.000ns})
Path Group: ddr3_clk_div
Path Type: Hold (Min at Fast Process Corner)
Requirement: 0.000ns (ddr3_clk_div [email protected] - ddr3_clk_div [email protected])
Data Path Delay: 0.209ns (logic 0.100ns (47.820%) route 0.109ns (52.180%))
Logic Levels: 0
Clock Path Skew: 0.013ns (DCD - SCD - CPR)
Destination Clock Delay (DCD): 1.740ns
Source Clock Delay (SCD): 1.424ns
Clock Pessimism Removal (CPR): 0.303ns
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
------------------------------------------------------------------- -------------------
(clock ddr3_clk_div rise edge)
0.000 0.000 r
BUFGCTRL_X0Y23 BUFG 0.000 0.000 r clocks393_i/bufg_axi_aclk_i/O
net (fo=738, routed) 0.580 0.580 mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/axi_clk
MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT2)
0.050 0.630 r mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKOUT2
net (fo=1, routed) 0.433 1.063 mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/clk_div_pre
BUFR_X1Y9 BUFR (Prop_bufr_I_O) 0.090 1.153 r mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/clk_div_bufr_i/O
net (fo=753, routed) 0.271 1.424 mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/byte_lane1_i/dq_block[1].dq_i/dq_in_dly_i/psincdec_reg
SLICE_X117Y135 FDRE r mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/byte_lane1_i/dq_block[1].dq_i/dq_in_dly_i/fdly_pre_reg[1]/C
------------------------------------------------------------------- -------------------
SLICE_X117Y135 FDRE (Prop_fdre_C_Q) 0.100 1.524 r mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/byte_lane1_i/dq_block[1].dq_i/dq_in_dly_i/fdly_pre_reg[1]/Q
net (fo=2, routed) 0.109 1.633 mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/byte_lane1_i/dq_block[1].dq_i/dq_in_dly_i/fdly_pre_reg_n_0_[1]
SLICE_X118Y135 FDRE r mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/byte_lane1_i/dq_block[1].dq_i/dq_in_dly_i/fdly_reg[1]/D
------------------------------------------------------------------- -------------------
(clock ddr3_clk_div rise edge)
0.000 0.000 r
BUFGCTRL_X0Y23 BUFG 0.000 0.000 r clocks393_i/bufg_axi_aclk_i/O
net (fo=738, routed) 0.796 0.796 mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/axi_clk
MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT2)
0.053 0.849 r mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKOUT2
net (fo=1, routed) 0.490 1.339 mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/clk_div_pre
BUFR_X1Y9 BUFR (Prop_bufr_I_O) 0.093 1.432 r mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/clk_div_bufr_i/O
net (fo=753, routed) 0.308 1.740 mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/byte_lane1_i/dq_block[1].dq_i/dq_in_dly_i/psincdec_reg
SLICE_X118Y135 FDRE r mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/byte_lane1_i/dq_block[1].dq_i/dq_in_dly_i/fdly_reg[1]/C
clock pessimism -0.303 1.437
SLICE_X118Y135 FDRE (Hold_fdre_C_D) 0.059 1.496 mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/byte_lane1_i/dq_block[1].dq_i/dq_in_dly_i/fdly_reg[1]
-------------------------------------------------------------------
required time -1.496
arrival time 1.633
-------------------------------------------------------------------
slack 0.137
Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name: ddr3_clk_div
Waveform(ns): { 0.000 2.500 }
Period(ns): 5.000
Sources: { mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKOUT2 }
Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin
Min Period n/a BUFR/I n/a 2.221 5.000 2.779 BUFR_X1Y9 mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/clk_div_bufr_i/I
Max Period n/a MMCME2_ADV/CLKOUT2 n/a 213.360 5.000 208.360 MMCME2_ADV_X1Y2 mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKOUT2
Low Pulse Width Slow MMCME2_ADV/PSCLK n/a 1.111 2.500 1.389 MMCME2_ADV_X1Y2 mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/MMCME2_ADV_i/PSCLK
High Pulse Width Slow MMCME2_ADV/PSCLK n/a 1.111 2.500 1.389 MMCME2_ADV_X1Y2 mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/MMCME2_ADV_i/PSCLK
---------------------------------------------------------------------------------------------------
From Clock: ddr3_clk_ref
To Clock: ddr3_clk_ref
Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA
Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA
PW : 0 Failing Endpoints, Worst Slack 0.264ns, Total Violation 0.000ns
---------------------------------------------------------------------------------------------------
Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name: ddr3_clk_ref
Waveform(ns): { 0.000 2.500 }
Period(ns): 5.000
Sources: { clocks393_i/pll_base_i/PLLE2_ADV_i/CLKOUT5 }
Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin
Min Period n/a IDELAYCTRL/REFCLK n/a 3.225 5.000 1.775 IDELAYCTRL_X1Y2 mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/idelay_ctrl_i/idelay_ctrl_i/REFCLK
Max Period n/a IDELAYCTRL/REFCLK n/a 5.264 5.000 0.264 IDELAYCTRL_X1Y2 mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/idelay_ctrl_i/idelay_ctrl_i/REFCLK
---------------------------------------------------------------------------------------------------
From Clock: ddr3_mclk
To Clock: ddr3_mclk
Setup : 0 Failing Endpoints, Worst Slack 0.131ns, Total Violation 0.000ns
Hold : 0 Failing Endpoints, Worst Slack 0.022ns, Total Violation 0.000ns
PW : 0 Failing Endpoints, Worst Slack 1.389ns, Total Violation 0.000ns
---------------------------------------------------------------------------------------------------
Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) : 0.131ns (required time - arrival time)
Source: mcntrl393_i/memctrl16_i/mcontr_sequencer_i/cmd1_buf_i/RAMB36E1_i/CLKARDCLK
(rising edge-triggered cell RAMB36E1 clocked by ddr3_mclk {[email protected] [email protected] period=5.000ns})
Destination: mcntrl393_i/memctrl16_i/mcontr_sequencer_i/cmd1_buf_i/RAMB36E1_i/ENARDEN
(rising edge-triggered cell RAMB36E1 clocked by ddr3_mclk {[email protected] [email protected] period=5.000ns})
Path Group: ddr3_mclk
Path Type: Setup (Max at Slow Process Corner)
Requirement: 5.000ns (ddr3_mclk [email protected] - ddr3_mclk [email protected])
Data Path Delay: 4.384ns (logic 1.013ns (23.106%) route 3.371ns (76.894%))
Logic Levels: 5 (LUT2=1 LUT4=1 LUT5=1 LUT6=2)
Clock Path Skew: -0.025ns (DCD - SCD + CPR)
Destination Clock Delay (DCD): 4.522ns = ( 10.772 - 6.250 )
Source Clock Delay (SCD): 4.878ns = ( 6.128 - 1.250 )
Clock Pessimism Removal (CPR): 0.331ns
Clock Uncertainty: 0.085ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
Total System Jitter (TSJ): 0.071ns
Discrete Jitter (DJ): 0.156ns
Phase Error (PE): 0.000ns
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
------------------------------------------------------------------- -------------------
(clock ddr3_mclk rise edge)
1.250 1.250 r
BUFGCTRL_X0Y23 BUFG 0.000 1.250 r clocks393_i/bufg_axi_aclk_i/O
net (fo=738, routed) 1.575 2.825 mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/axi_clk
MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT3)
0.088 2.913 r mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKOUT3
net (fo=1, routed) 1.628 4.541 mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mclk_pre
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.120 4.661 r mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mclk_i/O
net (fo=33128, routed) 1.467 6.128 mcntrl393_i/memctrl16_i/mcontr_sequencer_i/cmd1_buf_i/CLK
RAMB36_X5Y24 RAMB36E1 r mcntrl393_i/memctrl16_i/mcontr_sequencer_i/cmd1_buf_i/RAMB36E1_i/CLKARDCLK
------------------------------------------------------------------- -------------------
RAMB36_X5Y24 RAMB36E1 (Prop_ramb36e1_CLKARDCLK_DOADO[27])
0.748 6.876 r mcntrl393_i/memctrl16_i/mcontr_sequencer_i/cmd1_buf_i/RAMB36E1_i/DOADO[27]
net (fo=1, routed) 0.635 7.511 mcntrl393_i/memctrl16_i/mcontr_sequencer_i/cmd0_buf_i/RAMB36E1_i_0[26]
SLICE_X92Y129 LUT4 (Prop_lut4_I3_O) 0.053 7.564 r mcntrl393_i/memctrl16_i/mcontr_sequencer_i/cmd0_buf_i/phy_addr_prev[10]_i_1/O
net (fo=13, routed) 0.495 8.059 mcntrl393_i/memctrl16_i/mcontr_sequencer_i/cmd0_buf_i/phy_addr_prev_reg[14][22]
SLICE_X90Y126 LUT2 (Prop_lut2_I1_O) 0.053 8.112 f mcntrl393_i/memctrl16_i/mcontr_sequencer_i/cmd0_buf_i/pause_cntr[7]_i_2/O
net (fo=2, routed) 0.719 8.831 mcntrl393_i/memctrl16_i/mcontr_sequencer_i/cmd0_buf_i/pause_len[7]
SLICE_X88Y125 LUT6 (Prop_lut6_I3_O) 0.053 8.884 f mcntrl393_i/memctrl16_i/mcontr_sequencer_i/cmd0_buf_i/RAMB36E1_i_i_4/O
net (fo=2, routed) 0.472 9.356 mcntrl393_i/memctrl16_i/mcontr_sequencer_i/cmd0_buf_i/RAMB36E1_i_i_4_n_0
SLICE_X88Y126 LUT6 (Prop_lut6_I1_O) 0.053 9.409 f mcntrl393_i/memctrl16_i/mcontr_sequencer_i/cmd0_buf_i/RAMB36E1_i_i_2/O
net (fo=3, routed) 0.371 9.780 mcntrl393_i/memctrl16_i/mcontr_sequencer_i/cmd0_buf_i/RAMB36E1_i_i_2_n_0
SLICE_X87Y127 LUT5 (Prop_lut5_I1_O) 0.053 9.833 r mcntrl393_i/memctrl16_i/mcontr_sequencer_i/cmd0_buf_i/RAMB36E1_i_i_1__0/O
net (fo=2, routed) 0.678 10.512 mcntrl393_i/memctrl16_i/mcontr_sequencer_i/cmd1_buf_i/ren1
RAMB36_X5Y24 RAMB36E1 r mcntrl393_i/memctrl16_i/mcontr_sequencer_i/cmd1_buf_i/RAMB36E1_i/ENARDEN
------------------------------------------------------------------- -------------------
(clock ddr3_mclk rise edge)
6.250 6.250 r
BUFGCTRL_X0Y23 BUFG 0.000 6.250 r clocks393_i/bufg_axi_aclk_i/O
net (fo=738, routed) 1.437 7.687 mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/axi_clk
MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT3)
0.083 7.770 r mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKOUT3
net (fo=1, routed) 1.544 9.314 mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mclk_pre
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.113 9.427 r mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mclk_i/O
net (fo=33128, routed) 1.345 10.772 mcntrl393_i/memctrl16_i/mcontr_sequencer_i/cmd1_buf_i/CLK
RAMB36_X5Y24 RAMB36E1 r mcntrl393_i/memctrl16_i/mcontr_sequencer_i/cmd1_buf_i/RAMB36E1_i/CLKARDCLK
clock pessimism 0.331 11.103
clock uncertainty -0.085 11.017
RAMB36_X5Y24 RAMB36E1 (Setup_ramb36e1_CLKARDCLK_ENARDEN)
-0.375 10.642 mcntrl393_i/memctrl16_i/mcontr_sequencer_i/cmd1_buf_i/RAMB36E1_i
-------------------------------------------------------------------
required time 10.642
arrival time -10.512
-------------------------------------------------------------------
slack 0.131
Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) : 0.022ns (arrival time - required time)
Source: status_router16_top_i/status_router8_89abcdef_i/status_router4_4567_i/status_router2_top_i/fifo_in1_i/ra_reg_rep[1]/C
(rising edge-triggered cell FDRE clocked by ddr3_mclk {[email protected] [email protected] period=5.000ns})
Destination: status_router16_top_i/status_router8_89abcdef_i/status_router4_4567_i/status_router2_top_i/fifo_in1_i/outreg_reg[6]/D
(rising edge-triggered cell FDRE clocked by ddr3_mclk {[email protected] [email protected] period=5.000ns})
Path Group: ddr3_mclk
Path Type: Hold (Min at Fast Process Corner)
Requirement: 0.000ns (ddr3_mclk [email protected] - ddr3_mclk [email protected])
Data Path Delay: 0.416ns (logic 0.154ns (37.031%) route 0.262ns (62.969%))
Logic Levels: 1 (RAMD32=1)
Clock Path Skew: 0.298ns (DCD - SCD - CPR)
Destination Clock Delay (DCD): 2.337ns = ( 3.587 - 1.250 )
Source Clock Delay (SCD): 1.744ns = ( 2.994 - 1.250 )
Clock Pessimism Removal (CPR): 0.295ns
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
------------------------------------------------------------------- -------------------
(clock ddr3_mclk rise edge)
1.250 1.250 r
BUFGCTRL_X0Y23 BUFG 0.000 1.250 r clocks393_i/bufg_axi_aclk_i/O
net (fo=738, routed) 0.580 1.830 mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/axi_clk
MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT3)
0.050 1.880 r mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKOUT3
net (fo=1, routed) 0.559 2.439 mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mclk_pre
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 2.465 r mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mclk_i/O
net (fo=33128, routed) 0.529 2.994 status_router16_top_i/status_router8_89abcdef_i/status_router4_4567_i/status_router2_top_i/fifo_in1_i/mclk
SLICE_X53Y149 FDRE r status_router16_top_i/status_router8_89abcdef_i/status_router4_4567_i/status_router2_top_i/fifo_in1_i/ra_reg_rep[1]/C
------------------------------------------------------------------- -------------------
SLICE_X53Y149 FDRE (Prop_fdre_C_Q) 0.091 3.085 r status_router16_top_i/status_router8_89abcdef_i/status_router4_4567_i/status_router2_top_i/fifo_in1_i/ra_reg_rep[1]/Q
net (fo=12, routed) 0.262 3.347 status_router16_top_i/status_router8_89abcdef_i/status_router4_4567_i/status_router2_top_i/fifo_in1_i/ram_reg_0_15_6_8/ADDRA1
SLICE_X52Y150 RAMD32 (Prop_ramd32_RADR1_O)
0.063 3.410 r status_router16_top_i/status_router8_89abcdef_i/status_router4_4567_i/status_router2_top_i/fifo_in1_i/ram_reg_0_15_6_8/RAMA/O
net (fo=1, routed) 0.000 3.410 status_router16_top_i/status_router8_89abcdef_i/status_router4_4567_i/status_router2_top_i/fifo_in1_i/outreg0__8[6]
SLICE_X52Y150 FDRE r status_router16_top_i/status_router8_89abcdef_i/status_router4_4567_i/status_router2_top_i/fifo_in1_i/outreg_reg[6]/D
------------------------------------------------------------------- -------------------
(clock ddr3_mclk rise edge)
1.250 1.250 r
BUFGCTRL_X0Y23 BUFG 0.000 1.250 r clocks393_i/bufg_axi_aclk_i/O
net (fo=738, routed) 0.796 2.046 mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/axi_clk
MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT3)
0.053 2.099 r mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKOUT3
net (fo=1, routed) 0.623 2.722 mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mclk_pre
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.030 2.752 r mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mclk_i/O
net (fo=33128, routed) 0.835 3.587 status_router16_top_i/status_router8_89abcdef_i/status_router4_4567_i/status_router2_top_i/fifo_in1_i/mclk
SLICE_X52Y150 FDRE r status_router16_top_i/status_router8_89abcdef_i/status_router4_4567_i/status_router2_top_i/fifo_in1_i/outreg_reg[6]/C
clock pessimism -0.295 3.292
SLICE_X52Y150 FDRE (Hold_fdre_C_D) 0.096 3.388 status_router16_top_i/status_router8_89abcdef_i/status_router4_4567_i/status_router2_top_i/fifo_in1_i/outreg_reg[6]
-------------------------------------------------------------------
required time -3.388
arrival time 3.410
-------------------------------------------------------------------
slack 0.022
Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name: ddr3_mclk
Waveform(ns): { 1.250 3.750 }
Period(ns): 5.000
Sources: { mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKOUT3 }
Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin
Min Period n/a RAMB36E1/CLKBWRCLK n/a 2.495 5.000 2.505 RAMB36_X1Y12 sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_histogram_0_i/sens_hist_ram_snglclk_32_i/ramt_var_w_var_r_even_i/RAMB36E1_i/CLKBWRCLK
Max Period n/a MMCME2_ADV/CLKOUT3 n/a 213.360 5.000 208.360 MMCME2_ADV_X1Y2 mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKOUT3
Low Pulse Width Slow MMCME2_ADV/PSCLK n/a 1.111 2.500 1.389 MMCME2_ADV_X0Y0 sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_10398_i/sens_hispi12l4_i/sens_hispi_clock_i/mmcm_or_pll_i/MMCME2_ADV_i/PSCLK
High Pulse Width Slow MMCME2_ADV/PSCLK n/a 1.111 2.500 1.389 MMCME2_ADV_X0Y1 sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_10398_i/sens_hispi12l4_i/sens_hispi_clock_i/mmcm_or_pll_i/MMCME2_ADV_i/PSCLK
---------------------------------------------------------------------------------------------------
From Clock: ddr3_sdclk
To Clock: ddr3_sdclk
Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA
Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA
PW : 0 Failing Endpoints, Worst Slack 1.092ns, Total Violation 0.000ns
---------------------------------------------------------------------------------------------------
Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name: ddr3_sdclk
Waveform(ns): { 0.000 1.250 }
Period(ns): 2.500
Sources: { mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKOUT0 }
Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin
Min Period n/a BUFIO/I n/a 1.408 2.500 1.092 BUFIO_X1Y9 mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/iclk_bufio_i/I
Max Period n/a MMCME2_ADV/CLKOUT0 n/a 213.360 2.500 210.860 MMCME2_ADV_X1Y2 mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKOUT0
---------------------------------------------------------------------------------------------------
From Clock: multi_clkfb
To Clock: multi_clkfb
Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA
Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA
PW : 0 Failing Endpoints, Worst Slack 18.751ns, Total Violation 0.000ns
---------------------------------------------------------------------------------------------------
Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name: multi_clkfb
Waveform(ns): { 0.000 10.000 }
Period(ns): 20.000
Sources: { clocks393_i/pll_base_i/PLLE2_ADV_i/CLKFBOUT }
Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin
Min Period n/a PLLE2_ADV/CLKFBOUT n/a 1.249 20.000 18.751 PLLE2_ADV_X1Y2 clocks393_i/pll_base_i/PLLE2_ADV_i/CLKFBOUT
Max Period n/a PLLE2_ADV/CLKFBIN n/a 52.633 20.000 32.633 PLLE2_ADV_X1Y2 clocks393_i/pll_base_i/PLLE2_ADV_i/CLKFBIN
---------------------------------------------------------------------------------------------------
From Clock: sclk
To Clock: sclk
Setup : 0 Failing Endpoints, Worst Slack 4.184ns, Total Violation 0.000ns
Hold : 0 Failing Endpoints, Worst Slack 0.056ns, Total Violation 0.000ns
PW : 0 Failing Endpoints, Worst Slack 4.090ns, Total Violation 0.000ns
---------------------------------------------------------------------------------------------------
Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) : 4.184ns (required time - arrival time)
Source: event_logger_i/i_imu_spi/sngl_wire_stb_reg[0]/C
(rising edge-triggered cell FDRE clocked by sclk {[email protected] [email protected] period=10.000ns})
Destination: event_logger_i/i_imu_spi/sngl_wire_r_reg[1]/D
(falling edge-triggered cell FDRE clocked by sclk {[email protected] [email protected] period=10.000ns})
Path Group: sclk
Path Type: Setup (Max at Slow Process Corner)
Requirement: 5.000ns (sclk [email protected] - sclk [email protected])
Data Path Delay: 0.682ns (logic 0.269ns (39.450%) route 0.413ns (60.550%))
Logic Levels: 0
Clock Path Skew: -0.027ns (DCD - SCD + CPR)
Destination Clock Delay (DCD): 4.585ns = ( 9.585 - 5.000 )
Source Clock Delay (SCD): 4.987ns
Clock Pessimism Removal (CPR): 0.375ns
Clock Uncertainty: 0.075ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
Total System Jitter (TSJ): 0.071ns
Discrete Jitter (DJ): 0.133ns
Phase Error (PE): 0.000ns
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
------------------------------------------------------------------- -------------------
(clock sclk rise edge) 0.000 0.000 r
BUFGCTRL_X0Y23 BUFG 0.000 0.000 r clocks393_i/bufg_axi_aclk_i/O
net (fo=738, routed) 1.602 1.602 clocks393_i/pll_base_i/axi_clk
PLLE2_ADV_X1Y2 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3)
0.088 1.690 r clocks393_i/pll_base_i/PLLE2_ADV_i/CLKOUT3
net (fo=1, routed) 1.621 3.311 clocks393_i/sync_clk_i/sync_clk_pre
BUFGCTRL_X0Y22 BUFG (Prop_bufg_I_O) 0.120 3.431 r clocks393_i/sync_clk_i/clk1x_i/O
net (fo=1347, routed) 1.556 4.987 event_logger_i/i_imu_spi/camsync_clk
SLICE_X68Y176 FDRE r event_logger_i/i_imu_spi/sngl_wire_stb_reg[0]/C
------------------------------------------------------------------- -------------------
SLICE_X68Y176 FDRE (Prop_fdre_C_Q) 0.269 5.256 r event_logger_i/i_imu_spi/sngl_wire_stb_reg[0]/Q
net (fo=2, routed) 0.413 5.669 event_logger_i/i_imu_spi/sngl_wire_stb_reg_n_0_[0]
SLICE_X71Y175 FDRE r event_logger_i/i_imu_spi/sngl_wire_r_reg[1]/D
------------------------------------------------------------------- -------------------
(clock sclk fall edge) 5.000 5.000 f
BUFGCTRL_X0Y23 BUFG 0.000 5.000 f clocks393_i/bufg_axi_aclk_i/O
net (fo=738, routed) 1.461 6.461 clocks393_i/pll_base_i/axi_clk
PLLE2_ADV_X1Y2 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3)
0.083 6.544 f clocks393_i/pll_base_i/PLLE2_ADV_i/CLKOUT3
net (fo=1, routed) 1.538 8.082 clocks393_i/sync_clk_i/sync_clk_pre
BUFGCTRL_X0Y22 BUFG (Prop_bufg_I_O) 0.113 8.195 f clocks393_i/sync_clk_i/clk1x_i/O
net (fo=1347, routed) 1.390 9.585 event_logger_i/i_imu_spi/camsync_clk
SLICE_X71Y175 FDRE r event_logger_i/i_imu_spi/sngl_wire_r_reg[1]/C (IS_INVERTED)
clock pessimism 0.375 9.960
clock uncertainty -0.075 9.885
SLICE_X71Y175 FDRE (Setup_fdre_C_D) -0.032 9.853 event_logger_i/i_imu_spi/sngl_wire_r_reg[1]
-------------------------------------------------------------------
required time 9.853
arrival time -5.669
-------------------------------------------------------------------
slack 4.184