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more changes for derecho
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@jedwards4b
jedwards4b committed Nov 22, 2023
1 parent 914957b commit 2035266
Showing 1 changed file with 53 additions and 53 deletions.
106 changes: 53 additions & 53 deletions cime_config/testdefs/testlist_drv.xml
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Original file line number Diff line number Diff line change
Expand Up @@ -5,36 +5,36 @@
<!-- A compsets -->
<!-- ======================================= -->

<test compset="A" grid="f19_g17_rx1" name="SMS_Vnuopc_Ln11_D">
<test compset="A" grid="f19_g17_rx1" name="SMS_Ln11_D">
<machines>
<machine name="cheyenne" compiler="intel" category="aux_cmeps"/>
<machine name="derecho" compiler="gnu" category="aux_cmeps"/>
<machine name="izumi" compiler="intel" category="aux_cmeps"/>
</machines>
<options>
<option name="wallclock"> 00:10:00 </option>
</options>
</test>
<test compset="A" grid="f19_g17_rx1" name="ERS_Vnuopc_Ln9_C3">
<test compset="A" grid="f19_g17_rx1" name="ERS_Ln9_C3">
<machines>
<machine name="cheyenne" compiler="intel" category="aux_cmeps"/>
<machine name="derecho" compiler="intel" category="aux_cmeps"/>
<machine name="izumi" compiler="intel" category="aux_cmeps"/>
</machines>
<options>
<option name="wallclock"> 00:10:00 </option>
</options>
</test>
<test compset="ADWAV" grid="ww3a" name="SMS_Vnuopc_Ld2">
<test compset="ADWAV" grid="ww3a" name="SMS_Ld2">
<machines>
<machine name="cheyenne" compiler="intel" category="aux_cmeps"/>
<machine name="derecho" compiler="intel" category="aux_cmeps"/>
<machine name="izumi" compiler="intel" category="aux_cmeps"/>
</machines>
<options>
<option name="wallclock"> 00:10:00 </option>
</options>
</test>
<test compset="A1850DLND" grid="f09_f09_mg17" name="SMS_Vnuopc_Ld3">
<test compset="A1850DLND" grid="f09_f09_mg17" name="SMS_Ld3">
<machines>
<machine name="cheyenne" compiler="intel" category="aux_cmeps"/>
<machine name="derecho" compiler="nvhpc" category="aux_cmeps"/>
<machine name="izumi" compiler="intel" category="aux_cmeps"/>
</machines>
<options>
Expand All @@ -46,18 +46,18 @@
<!-- X compsets -->
<!-- ======================================= -->

<test compset="X" grid="f19_g17" name="SMS_Vnuopc">
<test compset="X" grid="f19_g17" name="SMS">
<machines>
<machine name="cheyenne" compiler="intel" category="aux_cmeps"/>
<machine name="derecho" compiler="gnu" category="aux_cmeps"/>
<machine name="izumi" compiler="intel" category="aux_cmeps"/>
</machines>
<options>
<option name="wallclock"> 00:20:00 </option>
</options>
</test>
<test compset="X" grid="f19_g17" name="ERS_Vnuopc_Ln9">
<test compset="X" grid="f19_g17" name="ERS_Ln9">
<machines>
<machine name="cheyenne" compiler="intel" category="aux_cmeps"/>
<machine name="derecho" compiler="intel" category="aux_cmeps"/>
<machine name="izumi" compiler="intel" category="aux_cmeps"/>
</machines>
<options>
Expand All @@ -69,18 +69,18 @@
<!-- B compsets -->
<!-- ======================================= -->

<test compset="B1850MOM" grid="f09_t061" name="ERR_Vnuopc_Ld5" testmods="allactive/defaultio">
<test compset="B1850MOM" grid="f09_t061" name="ERR_Ld5" testmods="allactive/defaultio">
<machines>
<machine name="cheyenne" compiler="intel" category="aux_cmeps"/>
<machine name="derecho" compiler="intel" category="aux_cmeps"/>
<machine name="izumi" compiler="intel" category="aux_cmeps"/>
</machines>
<options>
<option name="wallclock"> 00:40:00 </option>
</options>
</test>
<test compset="B1850" grid="f19_g17" name="ERS_Vnuopc_Ld5" testmods="allactive/defaultio">
<test compset="BLT1850_v0c" grid="ne30pg3_t232" name="ERS_Ld5" testmods="allactive/defaultio">
<machines>
<machine name="cheyenne" compiler="intel" category="aux_cmeps"/>
<machine name="derecho" compiler="intel" category="aux_cmeps"/>
<machine name="izumi" compiler="intel" category="aux_cmeps"/>
</machines>
<options>
Expand All @@ -92,27 +92,27 @@
<!-- C compsets -->
<!-- ======================================= -->

<test compset="C" grid="T62_g17" name="ERS_Vnuopc_Ld5">
<test compset="CMOM" grid="T62_g17" name="ERS_Ld5">
<machines>
<machine name="cheyenne" compiler="intel" category="aux_cmeps"/>
<machine name="derecho" compiler="gnu" category="aux_cmeps"/>
<machine name="izumi" compiler="intel" category="aux_cmeps"/>
</machines>
<options>
<option name="wallclock"> 00:40:00 </option>
</options>
</test>
<test compset="CMOM" grid="T62_t061" name="SMS_Vnuopc_Ld5">
<test compset="CMOM_JRA" grid="T62_t061" name="SMS_Ld5">
<machines>
<machine name="cheyenne" compiler="intel" category="aux_cmeps"/>
<machine name="derecho" compiler="intel" category="aux_cmeps"/>
<machine name="izumi" compiler="intel" category="aux_cmeps"/>
</machines>
<options>
<option name="wallclock"> 00:40:00 </option>
</options>
</test>
<test compset="CMOM" grid="T62_t061" name="ERS_Vnuopc_Ld5">
<test compset="CMOM" grid="T62_t061" name="ERS_Ld5">
<machines>
<machine name="cheyenne" compiler="intel" category="aux_cmeps"/>
<machine name="derecho" compiler="intel" category="aux_cmeps"/>
<machine name="izumi" compiler="intel" category="aux_cmeps"/>
</machines>
<options>
Expand All @@ -124,27 +124,27 @@
<!-- G compsets -->
<!-- ======================================= -->

<test compset="G" grid="T62_g17" name="ERS_Vnuopc_Ld5">
<test compset="GMOM_JRA" grid="T62_g17" name="ERS_Ld5">
<machines>
<machine name="cheyenne" compiler="intel" category="aux_cmeps"/>
<machine name="derecho" compiler="nvhpc" category="aux_cmeps"/>
<machine name="izumi" compiler="intel" category="aux_cmeps"/>
</machines>
<options>
<option name="wallclock"> 00:10:00 </option>
</options>
</test>
<test compset="GMOM" grid="T62_t061" name="SMS_Vnuopc_Ld5">
<test compset="GMOM" grid="T62_t061" name="SMS_Ld5">
<machines>
<machine name="cheyenne" compiler="intel" category="aux_cmeps"/>
<machine name="derecho" compiler="gnu" category="aux_cmeps"/>
<machine name="izumi" compiler="intel" category="aux_cmeps"/>
</machines>
<options>
<option name="wallclock"> 00:10:00 </option>
</options>
</test>
<test compset="GMOM" grid="T62_t061" name="ERS_Vnuopc_Ld5">
<test compset="GMOM" grid="T62_t061" name="ERS_Ld5">
<machines>
<machine name="cheyenne" compiler="intel" category="aux_cmeps"/>
<machine name="derecho" compiler="intel" category="aux_cmeps"/>
<machine name="izumi" compiler="intel" category="aux_cmeps"/>
</machines>
<options>
Expand All @@ -156,9 +156,9 @@
<!-- D compsets -->
<!-- ======================================= -->

<test compset="DTEST" grid="T62_g37" name="ERS_Vnuopc_Ld5">
<test compset="DTEST" grid="T62_g37" name="ERS_Ld5">
<machines>
<machine name="cheyenne" compiler="intel" category="aux_cmeps"/>
<machine name="derecho" compiler="intel" category="aux_cmeps"/>
<machine name="izumi" compiler="intel" category="aux_cmeps"/>
</machines>
<options>
Expand All @@ -170,24 +170,24 @@
<!-- F/Q compsets -->
<!-- ======================================= -->

<test compset="F2000climo" grid="f09_f09_mg17" name="ERP_Vnuopc_Ln9" testmods="cam/outfrq9s">
<test compset="F2000climo" grid="f09_f09_mg17" name="ERP_Ln9" testmods="cam/outfrq9s">
<machines>
<machine name="cheyenne" compiler="intel" category="aux_cmeps"/>
<machine name="derecho" compiler="nvhpc" category="aux_cmeps"/>
</machines>
<options>
<option name="wallclock">00:10:00</option>
</options>
</test>
<test compset="QPC4" grid="ne16_ne16_mg17" name="ERS_Vnuopc_Ln5" testmods="cam/nuopc_cap">
<test compset="QPC4" grid="ne16_ne16_mg17" name="ERS_Ln5" testmods="cam/nuopc_cap">
<machines>
<machine name="cheyenne" compiler="intel" category="aux_cmeps"/>
<machine name="derecho" compiler="gnu" category="aux_cmeps"/>
<machine name="izumi" compiler="intel" category="aux_cmeps"/>
</machines>
<options>
<option name="wallclock"> 00:10:00 </option>
</options>
</test>
<test compset="QPC6" grid="ne5pg3_ne5pg3_mg37" name="ERP_Vnuopc_Ln9" testmods="cam/outfrq9s_clubbmf">
<test compset="QPC6" grid="ne5pg3_ne5pg3_mg37" name="ERP_Ln9" testmods="cam/outfrq9s_clubbmf">
<machines>
<machine name="izumi" compiler="nag" category="aux_cmeps"/>
</machines>
Expand All @@ -200,36 +200,36 @@
<!-- I compsets -->
<!-- ======================================= -->

<test compset="I2000Clm51Bgc" grid="f19_g17" name="ERS_Vnuopc_Ld5" testmods="clm/default">
<test compset="I2000Clm51Bgc" grid="f19_g17" name="ERS_Ld5" testmods="clm/default">
<machines>
<machine name="cheyenne" compiler="intel" category="aux_cmeps"/>
<machine name="derecho" compiler="intel" category="aux_cmeps"/>
<machine name="izumi" compiler="intel" category="aux_cmeps"/>
</machines>
<options>
<option name="wallclock"> 00:20:00 </option>
</options>
</test>
<test compset="I1850Clm50Sp" grid="f09_g17" name="ERS_Vnuopc_Ld5" testmods="clm/default">
<test compset="I1850Clm50Sp" grid="f09_g17" name="ERS_Ld5" testmods="clm/default">
<machines>
<machine name="cheyenne" compiler="intel" category="aux_cmeps"/>
<machine name="derecho" compiler="intel" category="aux_cmeps"/>
<machine name="izumi" compiler="intel" category="aux_cmeps"/>
</machines>
<options>
<option name="wallclock"> 00:20:00 </option>
</options>
</test>
<test compset="I1850Clm50SpG" grid="f10_f10_mg37" name="ERS_Vnuopc_Lm13">
<test compset="I1850Clm50SpG" grid="f10_f10_mg37" name="ERS_Lm13_P32">
<machines>
<machine name="cheyenne" compiler="intel" category="aux_cmeps"/>
<machine name="derecho" compiler="nvhpc" category="aux_cmeps"/>
<machine name="izumi" compiler="intel" category="aux_cmeps"/>
</machines>
<options>
<option name="wallclock"> 00:20:00 </option>
</options>
</test>
<test compset="I2000Clm50BgcCropRtm" grid="f10_f10_mg37" name="SMS_D_Ld5_Vnuopc" testmods="rtm/default">
<test compset="I2000Clm50BgcCropRtm" grid="f10_f10_mg37" name="SMS_D_Ld5_P32" testmods="rtm/default">
<machines>
<machine name="cheyenne" compiler="intel" category="aux_cmeps"/>
<machine name="derecho" compiler="gnu" category="aux_cmeps"/>
<machine name="izumi" compiler="nag" category="aux_cmeps"/>
</machines>
<options>
Expand All @@ -241,18 +241,18 @@
<!-- TG compsets -->
<!-- ======================================= -->

<test name="SMS_D_Ly1_Vnuopc" grid="f09_g17_gl4" compset="T1850Gg">
<test name="SMS_D_Ly1" grid="f09_g17_gl4" compset="T1850Gg">
<machines>
<machine name="cheyenne" compiler="intel" category="aux_cmeps">
<machine name="derecho" compiler="intel" category="aux_cmeps">
<options>
<option name="wallclock">0:20</option>
</options>
</machine>
</machines>
</test>
<test name="ERS_Ly3_Vnuopc" grid="f09_g17_gl4" compset="T1850Gg">
<test name="ERS_Ly3" grid="f09_g17_gl4" compset="T1850Gg">
<machines>
<machine name="cheyenne" compiler="intel" category="aux_cmeps">
<machine name="derecho" compiler="nvhpc" category="aux_cmeps">
<options>
<option name="wallclock">0:20</option>
</options>
Expand All @@ -263,28 +263,28 @@
<!-- ======================================= -->
<!-- Asyncio tests -->
<!-- ======================================= -->
<test name="ERS_Ln9_Vnuopc" grid="f19_f19_mg17" compset="FHIST" testmods="drv/asyncio1pernode--cam/outfrq9s">
<test name="ERS_Ln9" grid="ne30pg3_ne30pg3_mg17" compset="FHIST" testmods="drv/asyncio1pernode--cam/outfrq9s">
<machines>
<machine name="cheyenne" compiler="intel" category="prealpha">
<machine name="derecho" compiler="intel" category="prealpha">
<options>
<option name="wallclock">0:20</option>
</options>
</machine>
</machines>
</test>
<test name="ERS_C3_Vnuopc" grid="f19_g17" compset="A" testmods="drv/asyncio1pernode">
<test name="ERS_C3" grid="ne30_g17" compset="A" testmods="drv/asyncio1pernode">
<machines>
<machine name="cheyenne" compiler="intel" category="prealpha">
<machine name="derecho" compiler="nvhpc" category="prealpha">
<options>
<option name="wallclock">0:40</option>
</options>
</machine>
</machines>
</test>

<test name="ERS_Ld5_Vnuopc" grid="ne30pg3_t061" compset="B1850MOM" testmods="allactive/defaultio--drv/asyncio1node">
<test name="ERS_Ld5" grid="ne30pg3_t061" compset="B1850MOM" testmods="allactive/defaultio--drv/asyncio1node">
<machines>
<machine name="cheyenne" compiler="intel" category="prealpha">
<machine name="derecho" compiler="gnu" category="prealpha">
<options>
<option name="wallclock">0:40</option>
</options>
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