From c268c64c58c8de47b35a60efeb6c21eea67fdfe1 Mon Sep 17 00:00:00 2001 From: Cheryl Craig Date: Wed, 15 Nov 2023 15:57:09 -0700 Subject: [PATCH 1/8] Update externals to match cesm2_3_alpha16g --- Externals.cfg | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/Externals.cfg b/Externals.cfg index c60ee52605..dfe04d45c4 100644 --- a/Externals.cfg +++ b/Externals.cfg @@ -1,5 +1,5 @@ [ccs_config] -tag = ccs_config_cesm0.0.80 +tag = ccs_config_cesm0.0.82 protocol = git repo_url = https://github.com/ESMCI/ccs_config_cesm local_path = ccs_config @@ -28,7 +28,7 @@ local_path = components/cmeps required = True [cdeps] -tag = cdeps1.0.21 +tag = cdeps1.0.24 protocol = git repo_url = https://github.com/ESCOMP/CDEPS.git local_path = components/cdeps @@ -64,7 +64,7 @@ local_path = libraries/parallelio required = True [cime] -tag = cime6.0.156 +tag = cime6.0.175 protocol = git repo_url = https://github.com/ESMCI/cime local_path = cime @@ -79,7 +79,7 @@ externals = Externals_CISM.cfg required = True [clm] -tag = ctsm5.1.dev139 +tag = ctsm5.1.dev142 protocol = git repo_url = https://github.com/ESCOMP/CTSM local_path = components/clm From a842526658891eb34d2070d9a95b46bb579657f1 Mon Sep 17 00:00:00 2001 From: Cheryl Craig Date: Thu, 16 Nov 2023 10:14:06 -0700 Subject: [PATCH 2/8] Update ccs_config external --- Externals.cfg | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Externals.cfg b/Externals.cfg index dfe04d45c4..579c915beb 100644 --- a/Externals.cfg +++ b/Externals.cfg @@ -1,5 +1,5 @@ [ccs_config] -tag = ccs_config_cesm0.0.82 +tag = ccs_config_cesm0.0.83 protocol = git repo_url = https://github.com/ESMCI/ccs_config_cesm local_path = ccs_config From ca86d0fdb61a5cc261c7fbb3bda381e382924bef Mon Sep 17 00:00:00 2001 From: Cheryl Craig Date: Thu, 16 Nov 2023 14:19:49 -0700 Subject: [PATCH 3/8] Fix failing TMC tests --- cime_config/SystemTests/tmc.py | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/cime_config/SystemTests/tmc.py b/cime_config/SystemTests/tmc.py index 97e96091b1..9fb8a5f7ab 100644 --- a/cime_config/SystemTests/tmc.py +++ b/cime_config/SystemTests/tmc.py @@ -6,6 +6,7 @@ from CIME.SystemTests.system_tests_common import SystemTestsCommon from CIME.test_status import * from CIME.utils import append_testlog +from CIME.baselines.performance import get_latest_cpl_logs import glob, gzip @@ -22,7 +23,7 @@ def run_phase(self): with self._test_status: self._test_status.set_status("COMPARE_MASS", TEST_PEND_STATUS) self.run_indv() - cpllog = ''.join(self._get_latest_cpl_logs()) + cpllog = ''.join(get_latest_cpl_logs(self._case)) atmlog = cpllog.replace("cpl.log","atm.log") atmlog = atmlog.replace("drv.log","atm.log") if '.gz' == atmlog[-3:]: @@ -35,9 +36,9 @@ def run_phase(self): first_val = -9.0 with self._test_status: self._test_status.set_status("COMPARE_MASS", TEST_PASS_STATUS) - use_this_tt_un = False + use_this_tt_un = False for line in lines: - if re.search('vvvvv gmean_mass: before tphysbc DRY',line.decode('utf-8')): + if re.search('vvvvv gmean_mass: before tphysbc DRY',line.decode('utf-8')): use_this_tt_un = True if re.search('TT_UN ',line.decode('utf-8')) and use_this_tt_un: tt_un_flt=re.findall("\d+\.\d+",line.decode('utf-8')) @@ -49,7 +50,7 @@ def run_phase(self): self._test_status.set_status("COMPARE_MASS", TEST_FAIL_STATUS, comments="Mass Not Conserved") comments = "CAM mass conservation test FAILED." append_testlog(comments, self._orig_caseroot) - use_this_tt_un = False + use_this_tt_un = False if first_val == -9.0: with self._test_status: self._test_status.set_status("COMPARE_MASS", TEST_FAIL_STATUS, comments="Failed to find TT_UN in atm.log") From 359360cbb5e8367237b0652b2cfab799673183c2 Mon Sep 17 00:00:00 2001 From: Cheryl Craig Date: Thu, 16 Nov 2023 17:00:20 -0700 Subject: [PATCH 4/8] Update PE layouts for derecho --- cime_config/config_pes.xml | 110 +++++++++++++++++++++++++++++++++++++ 1 file changed, 110 insertions(+) diff --git a/cime_config/config_pes.xml b/cime_config/config_pes.xml index e824b05e35..d6c66ab86c 100644 --- a/cime_config/config_pes.xml +++ b/cime_config/config_pes.xml @@ -734,6 +734,43 @@ + + + + none + + 72 + 72 + 72 + 72 + 72 + 72 + 72 + 72 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + + + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + @@ -1549,6 +1586,44 @@ + + + + none + + 36 + 36 + 36 + 36 + 36 + 36 + 36 + 36 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + + + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + @@ -1627,6 +1702,41 @@ + + + none + + 128 + 128 + 128 + 128 + 128 + 128 + 128 + 128 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + + + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + none From 981b95a4576af3680bcd19e35d229a6e075e1525 Mon Sep 17 00:00:00 2001 From: Cheryl Craig Date: Fri, 17 Nov 2023 10:23:35 -0700 Subject: [PATCH 5/8] back off ccs_config external --- Externals.cfg | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Externals.cfg b/Externals.cfg index 579c915beb..dfe04d45c4 100644 --- a/Externals.cfg +++ b/Externals.cfg @@ -1,5 +1,5 @@ [ccs_config] -tag = ccs_config_cesm0.0.83 +tag = ccs_config_cesm0.0.82 protocol = git repo_url = https://github.com/ESMCI/ccs_config_cesm local_path = ccs_config From c8757122debc9593f7612e29109bd71f9fa494d9 Mon Sep 17 00:00:00 2001 From: Cheryl Craig Date: Fri, 17 Nov 2023 15:17:51 -0700 Subject: [PATCH 6/8] Fix failing derecho test --- cime_config/config_pes.xml | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/cime_config/config_pes.xml b/cime_config/config_pes.xml index d6c66ab86c..1b52b2be50 100644 --- a/cime_config/config_pes.xml +++ b/cime_config/config_pes.xml @@ -739,14 +739,14 @@ none - 72 - 72 - 72 - 72 - 72 - 72 - 72 - 72 + 128 + 128 + 128 + 128 + 128 + 128 + 128 + 128 1 From 9c482b3898ff1c292ef752fcd293b078b9b7f8bb Mon Sep 17 00:00:00 2001 From: Cheryl Craig Date: Fri, 17 Nov 2023 16:11:40 -0700 Subject: [PATCH 7/8] Add derecho testing to ChangeLog template --- doc/ChangeLog_template | 2 ++ 1 file changed, 2 insertions(+) diff --git a/doc/ChangeLog_template b/doc/ChangeLog_template index 3fdfda2367..62d0cb4135 100644 --- a/doc/ChangeLog_template +++ b/doc/ChangeLog_template @@ -31,6 +31,8 @@ appropriate machine below. All failed tests must be justified. cheyenne/intel/aux_cam: +derecho/intel/aux_cam: + izumi/nag/aux_cam: izumi/gnu/aux_cam: From 4cf858194ebaaa4532297d449c54615660b9d57d Mon Sep 17 00:00:00 2001 From: Cheryl Craig Date: Sat, 18 Nov 2023 21:33:43 -0700 Subject: [PATCH 8/8] Update ChangeLog for cam6_3_136 --- doc/ChangeLog | 119 ++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 119 insertions(+) diff --git a/doc/ChangeLog b/doc/ChangeLog index 9436ef69ab..6a3547dbc3 100644 --- a/doc/ChangeLog +++ b/doc/ChangeLog @@ -1,3 +1,122 @@ + +=============================================================== + +Tag name: cam6_3_136 +Originator(s): cacraig, fischer +Date: Nov 18, 2023 +One-line Summary: Update externals to match cesm2_3_alpha16g and fix failing derecho tests +Github PR URL: https://github.com/ESCOMP/CAM/pull/914 + +Purpose of changes (include the issue number and title text for each relevant GitHub issue): +- Fix failing derecho regression tests: https://github.com/ESCOMP/CAM/issues/892 + +Describe any changes made to build system: N/A + +Describe any changes made to the namelist: N/A + +List any changes to the defaults for the boundary datasets: N/A + +Describe any substantial timing or memory changes: N/A + +Code reviewed by: nusbaume + +List all files eliminated: N/A + +List all files added and what they do: N/A + +List all existing files that have been modified, and describe the changes: +M Externals.cfg + - update Externals to match cesm2_3_alpha16g + +M cime_config/SystemTests/tmc.py + - Fix from Chris Fischer for failing TMC regression test + +M cime_config/config_pes.xml + - Update derecho PE layouts + +M doc/ChangeLog_template + - Add derecho regression testing + +If there were any failures reported from running test_driver.sh on any test +platform, and checkin with these failures has been OK'd by the gatekeeper, +then copy the lines from the td.*.status files for the failed tests to the +appropriate machine below. All failed tests must be justified. + +All tests had namelist changes due to externals update + +cheyenne/intel/aux_cam: + ERP_Ln9_Vnuopc.C96_C96_mg17.F2000climo.cheyenne_intel.cam-outfrq9s_mg3 (Overall: FAIL) details: + FAIL ERP_Ln9_Vnuopc.C96_C96_mg17.F2000climo.cheyenne_intel.cam-outfrq9s_mg3 MODEL_BUILD time=3 + ERP_Ln9_Vnuopc.f09_f09_mg17.FCSD_HCO.cheyenne_intel.cam-outfrq9s (Overall: FAIL) details: + FAIL ERP_Ln9_Vnuopc.f09_f09_mg17.FCSD_HCO.cheyenne_intel.cam-outfrq9s COMPARE_base_rest + SMS_Lh12_Vnuopc.f09_f09_mg17.FCSD_HCO.cheyenne_intel.cam-outfrq3h (Overall: DIFF) details: + FAIL SMS_Lh12_Vnuopc.f09_f09_mg17.FCSD_HCO.cheyenne_intel.cam-outfrq3h BASELINE /glade/p/cesm/amwg/cesm_baselines/cam6_3_135: DIFF + - pre-existing failures + + ERP_D_Ln9.ne30pg3_ne30pg3_mg17.FLTHIST.cheyenne_intel.cam-outfrq9s (Overall: DIFF) details: + ERP_D_Ln9_Vnuopc.ne30pg3_ne30pg3_mg17.F2000dev.cheyenne_intel.cam-outfrq9s (Overall: DIFF) details: + ERP_Ld3_Vnuopc.f09_f09_mg17.FWHIST.cheyenne_intel.cam-reduced_hist1d (Overall: DIFF) details: + ERP_Lh12_Vnuopc.f19_f19_mg17.FW4madSD.cheyenne_intel.cam-outfrq3h (Overall: DIFF) details: + ERP_Ln9_Vnuopc.f09_f09_mg17.F1850.cheyenne_intel.cam-outfrq9s (Overall: DIFF) details: + ERP_Ln9_Vnuopc.f09_f09_mg17.F2000climo.cheyenne_intel.cam-outfrq9s (Overall: DIFF) details: + ERP_Ln9_Vnuopc.f09_f09_mg17.F2000dev.cheyenne_intel.cam-outfrq9s_mg3 (Overall: DIFF) details: + ERP_Ln9_Vnuopc.f09_f09_mg17.F2010climo.cheyenne_intel.cam-outfrq9s (Overall: DIFF) details: + ERP_Ln9_Vnuopc.f09_f09_mg17.FHIST_BDRD.cheyenne_intel.cam-outfrq9s (Overall: DIFF) details: + ERP_Ln9_Vnuopc.f19_f19_mg17.FWsc1850.cheyenne_intel.cam-outfrq9s (Overall: DIFF) details: + ERP_Ln9_Vnuopc.ne30_ne30_mg17.FCnudged.cheyenne_intel.cam-outfrq9s (Overall: DIFF) details: + ERP_Ln9_Vnuopc.ne30pg3_ne30pg3_mg17.FW2000climo.cheyenne_intel.cam-outfrq9s_wcm_ne30 (Overall: DIFF) details: + ERS_Ld3_Vnuopc.f10_f10_mg37.F1850.cheyenne_intel.cam-outfrq1d_14dec_ghg_cam_dev (Overall: DIFF) details: + ERS_Ln9_P288x1_Vnuopc.mpasa120_mpasa120.F2000climo.cheyenne_intel.cam-outfrq9s_mpasa120 (Overall: DIFF) details: + ERS_Ln9_P36x1_Vnuopc.mpasa480_mpasa480.F2000climo.cheyenne_intel.cam-outfrq9s_mpasa480 (Overall: DIFF) details: + ERS_Ln9_Vnuopc.f09_f09_mg17.FX2000.cheyenne_intel.cam-outfrq9s (Overall: DIFF) details: + ERS_Ln9_Vnuopc.f19_f19_mg17.FSPCAMS.cheyenne_intel.cam-outfrq9s (Overall: DIFF) details: + ERS_Ln9_Vnuopc.f19_f19_mg17.FXSD.cheyenne_intel.cam-outfrq9s (Overall: DIFF) details: + SMS_D_Ln9.ne30pg3_ne30pg3_mg17.FMTHIST.cheyenne_intel.cam-outfrq9s (Overall: DIFF) details: + SMS_D_Ln9_Vnuopc.f09_f09_mg17.FCts2nudged.cheyenne_intel.cam-outfrq9s_leapday (Overall: DIFF) details: + SMS_D_Ln9_Vnuopc.f09_f09_mg17.FCvbsxHIST.cheyenne_intel.cam-outfrq9s (Overall: DIFF) details: + SMS_D_Ln9_Vnuopc.f09_f09_mg17.FSD.cheyenne_intel.cam-outfrq9s (Overall: DIFF) details: + SMS_D_Ln9_Vnuopc.f19_f19_mg17.FWma2000climo.cheyenne_intel.cam-outfrq9s (Overall: DIFF) details: + SMS_D_Ln9_Vnuopc.f19_f19_mg17.FWma2000climo.cheyenne_intel.cam-outfrq9s_waccm_ma_mam4 (Overall: DIFF) details: + SMS_D_Ln9_Vnuopc.f19_f19_mg17.FXHIST.cheyenne_intel.cam-outfrq9s_amie (Overall: DIFF) details: + SMS_D_Ln9_Vnuopc.ne16_ne16_mg17.FX2000.cheyenne_intel.cam-outfrq9s (Overall: DIFF) details: + SMS_D_Ln9_Vnuopc_P1280x1.ne0ARCTICne30x4_ne0ARCTICne30x4_mt12.FHIST.cheyenne_intel.cam-outfrq9s (Overall: DIFF) details: + SMS_D_Ln9_Vnuopc_P1280x1.ne0CONUSne30x8_ne0CONUSne30x8_mt12.FCHIST.cheyenne_intel.cam-outfrq9s (Overall: DIFF) details: + SMS_D_Ln9_Vnuopc_P1280x1.ne30pg3_ne30pg3_mg17.FCLTHIST.cheyenne_intel.cam-outfrq9s (Overall: DIFF) details: + SMS_Ld1_Vnuopc.f09_f09_mg17.FW2000climo.cheyenne_intel.cam-outfrq1d (Overall: DIFF) details: + SMS_Ld1_Vnuopc.f19_f19.F2000dev.cheyenne_intel.cam-outfrq1d (Overall: DIFF) details: + SMS_Ld1_Vnuopc.ne30pg3_ne30pg3_mg17.FC2010climo.cheyenne_intel.cam-outfrq1d (Overall: DIFF) details: + SMS_Lh12_Vnuopc.f09_f09_mg17.FCSD_HCO.cheyenne_intel.cam-outfrq3h (Overall: DIFF) details: + SMS_Lm13_Vnuopc.f10_f10_mg37.F2000climo.cheyenne_intel.cam-outfrq1m (Overall: DIFF) details: + SMS_Ln9_Vnuopc.f09_f09_mg17.F2010climo.cheyenne_intel.cam-nudging (Overall: DIFF) details: + SMS_Ln9_Vnuopc.f09_f09_mg17.FW1850.cheyenne_intel.cam-reduced_hist3s (Overall: DIFF) details: + SMS_Ln9_Vnuopc.f19_f19.F2000climo.cheyenne_intel.cam-silhs (Overall: DIFF) details: + SMS_Ln9_Vnuopc.f19_f19_mg17.FHIST.cheyenne_intel.cam-outfrq9s_nochem (Overall: DIFF) details: + - Differences due to externals updated + +derecho/intel/aux_cam: no baseline comparisons due to being first official testing on derecho + ERP_Ln9_Vnuopc.C96_C96_mg17.F2000climo.derecho_intel.cam-outfrq9s_mg3 (Overall: PEND) details: + PEND ERP_Ln9_Vnuopc.C96_C96_mg17.F2000climo.derecho_intel.cam-outfrq9s_mg3 SHAREDLIB_BUILD + ERP_Ln9_Vnuopc.f09_f09_mg17.FCSD_HCO.derecho_intel.cam-outfrq9s (Overall: FAIL) details: + FAIL ERP_Ln9_Vnuopc.f09_f09_mg17.FCSD_HCO.derecho_intel.cam-outfrq9s COMPARE_base_rest + - pre-existing failures on cheyenne + + ERP_Ln9_Vnuopc.ne30pg3_ne30pg3_mg17.FW2000climo.derecho_intel.cam-outfrq9s_wcm_ne30 (Overall: PEND) details: + PEND ERP_Ln9_Vnuopc.ne30pg3_ne30pg3_mg17.FW2000climo.derecho_intel.cam-outfrq9s_wcm_ne30 RUN + PEND ERP_Ln9_Vnuopc.ne30pg3_ne30pg3_mg17.FW2000climo.derecho_intel.cam-outfrq9s_wcm_ne30 COMPARE_base_rest + - unknown test failure - repeatable + +izumi/nag/aux_cam: + DAE_Vnuopc.f45_f45_mg37.FHS94.izumi_nag.cam-dae (Overall: FAIL) details: + FAIL DAE_Vnuopc.f45_f45_mg37.FHS94.izumi_nag.cam-dae RUN time=80 + - pre-existing failure + + +izumi/gnu/aux_cam: + SMS_D_Ln9.f10_f10_mg37.2000_CAM%DEV%GHGMAM4_CLM50%SP_CICE%PRES_DOCN%DOM_MOSART_SGLC_SWAV_SESP.izumi_gnu.cam-outfrq9s (Overall: DIFF) details: + SMS_P48x1_D_Ln9_Vnuopc.f19_f19_mg17.FW4madSD.izumi_gnu.cam-outfrq9s (Overall: DIFF) details: + - baseline diffs due to externals update + +=============================================================== =============================================================== Tag name: cam6_3_135