Merge pull request #914 from cacraigucar/cam_derecho_tests

cam6_3_136: Update externals to match cesm2_3_alpha16g and fix failing derecho tests
ESCOMP · Nov 19, 2023 · 7cf5966 · 7cf5966
2 parents 408f014 + 4cf8581
commit 7cf5966
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Showing 5 changed files with 240 additions and 8 deletions.
diff --git a/Externals.cfg b/Externals.cfg
@@ -1,5 +1,5 @@
 [ccs_config]
-tag = ccs_config_cesm0.0.80
+tag = ccs_config_cesm0.0.82
 protocol = git
 repo_url = https://github.com/ESMCI/ccs_config_cesm
 local_path = ccs_config
@@ -28,7 +28,7 @@ local_path = components/cmeps
 required = True
 
 [cdeps]
-tag = cdeps1.0.21
+tag = cdeps1.0.24
 protocol = git
 repo_url = https://github.com/ESCOMP/CDEPS.git
 local_path = components/cdeps
@@ -64,7 +64,7 @@ local_path = libraries/parallelio
 required = True
 
 [cime]
-tag = cime6.0.156
+tag = cime6.0.175
 protocol = git
 repo_url = https://github.com/ESMCI/cime
 local_path = cime
@@ -79,7 +79,7 @@ externals = Externals_CISM.cfg
 required = True
 
 [clm]
-tag = ctsm5.1.dev139
+tag = ctsm5.1.dev142
 protocol = git
 repo_url = https://github.com/ESCOMP/CTSM
 local_path = components/clm

diff --git a/cime_config/SystemTests/tmc.py b/cime_config/SystemTests/tmc.py
@@ -6,6 +6,7 @@
 from CIME.SystemTests.system_tests_common import SystemTestsCommon
 from CIME.test_status import *
 from CIME.utils import append_testlog
+from CIME.baselines.performance import get_latest_cpl_logs
 import glob, gzip
 
 
@@ -22,7 +23,7 @@ def run_phase(self):
         with self._test_status:
             self._test_status.set_status("COMPARE_MASS", TEST_PEND_STATUS)
         self.run_indv()
-        cpllog = ''.join(self._get_latest_cpl_logs())
+        cpllog = ''.join(get_latest_cpl_logs(self._case))
         atmlog  = cpllog.replace("cpl.log","atm.log")
         atmlog  = atmlog.replace("drv.log","atm.log")
         if '.gz' == atmlog[-3:]:
@@ -35,9 +36,9 @@ def run_phase(self):
         first_val = -9.0
         with self._test_status:
             self._test_status.set_status("COMPARE_MASS", TEST_PASS_STATUS)
-        use_this_tt_un = False 
+        use_this_tt_un = False
         for line in lines:
-            if re.search('vvvvv gmean_mass: before tphysbc DRY',line.decode('utf-8')): 
+            if re.search('vvvvv gmean_mass: before tphysbc DRY',line.decode('utf-8')):
                 use_this_tt_un = True
             if re.search('TT_UN ',line.decode('utf-8')) and use_this_tt_un:
                 tt_un_flt=re.findall("\d+\.\d+",line.decode('utf-8'))
@@ -49,7 +50,7 @@ def run_phase(self):
                             self._test_status.set_status("COMPARE_MASS", TEST_FAIL_STATUS, comments="Mass Not Conserved")
                         comments = "CAM mass conservation test FAILED."
                         append_testlog(comments, self._orig_caseroot)
-                use_this_tt_un = False 
+                use_this_tt_un = False
         if first_val == -9.0:
             with self._test_status:
                 self._test_status.set_status("COMPARE_MASS", TEST_FAIL_STATUS, comments="Failed to find TT_UN in atm.log")

diff --git a/cime_config/config_pes.xml b/cime_config/config_pes.xml
@@ -734,6 +734,43 @@
       </pes>
     </mach>
   </grid>
+  <grid name="a%1.9x2.5">
+    <mach name="derecho">
+      <pes pesize='any' compset='any'>
+	<comment>none</comment>
+	<ntasks>
+	  <ntasks_atm>128</ntasks_atm>
+	  <ntasks_lnd>128</ntasks_lnd>
+	  <ntasks_rof>128</ntasks_rof>
+	  <ntasks_ice>128</ntasks_ice>
+	  <ntasks_ocn>128</ntasks_ocn>
+	  <ntasks_glc>128</ntasks_glc>
+	  <ntasks_wav>128</ntasks_wav>
+	  <ntasks_cpl>128</ntasks_cpl>
+	</ntasks>
+	<nthrds>
+	  <nthrds_atm>1</nthrds_atm>
+	  <nthrds_lnd>1</nthrds_lnd>
+	  <nthrds_rof>1</nthrds_rof>
+	  <nthrds_ice>1</nthrds_ice>
+	  <nthrds_ocn>1</nthrds_ocn>
+	  <nthrds_glc>1</nthrds_glc>
+	  <nthrds_wav>1</nthrds_wav>
+	  <nthrds_cpl>1</nthrds_cpl>
+	</nthrds>
+	<rootpe>
+	  <rootpe_atm>0</rootpe_atm>
+	  <rootpe_lnd>0</rootpe_lnd>
+	  <rootpe_rof>0</rootpe_rof>
+	  <rootpe_ice>0</rootpe_ice>
+	  <rootpe_ocn>0</rootpe_ocn>
+	  <rootpe_glc>0</rootpe_glc>
+	  <rootpe_wav>0</rootpe_wav>
+	  <rootpe_cpl>0</rootpe_cpl>
+	</rootpe>
+      </pes>
+    </mach>
+  </grid>
   <grid name="a%1.9x2.5">
     <mach name="any">
       <pes pesize='any' compset='any'>
@@ -1549,6 +1586,44 @@
     </mach>
   </grid>
 
+  <grid name="a%10x15" >
+    <mach name="derecho" >
+      <pes pesize="any" compset="any">
+        <comment>none</comment>
+	      <ntasks>
+	        <ntasks_atm>36</ntasks_atm>
+	        <ntasks_lnd>36</ntasks_lnd>
+	        <ntasks_rof>36</ntasks_rof>
+	        <ntasks_ice>36</ntasks_ice>
+	        <ntasks_ocn>36</ntasks_ocn>
+	        <ntasks_glc>36</ntasks_glc>
+	        <ntasks_wav>36</ntasks_wav>
+	        <ntasks_cpl>36</ntasks_cpl>
+	      </ntasks>
+	      <nthrds>
+	        <nthrds_atm>1</nthrds_atm>
+	        <nthrds_lnd>1</nthrds_lnd>
+	        <nthrds_rof>1</nthrds_rof>
+	        <nthrds_ice>1</nthrds_ice>
+	        <nthrds_ocn>1</nthrds_ocn>
+	        <nthrds_glc>1</nthrds_glc>
+	        <nthrds_wav>1</nthrds_wav>
+	        <nthrds_cpl>1</nthrds_cpl>
+	      </nthrds>
+	      <rootpe>
+	        <rootpe_atm>0</rootpe_atm>
+	        <rootpe_lnd>0</rootpe_lnd>
+	        <rootpe_rof>0</rootpe_rof>
+	        <rootpe_ice>0</rootpe_ice>
+	        <rootpe_ocn>0</rootpe_ocn>
+	        <rootpe_glc>0</rootpe_glc>
+	        <rootpe_wav>0</rootpe_wav>
+	        <rootpe_cpl>0</rootpe_cpl>
+        </rootpe>
+      </pes>
+    </mach>
+  </grid>
+
   <!-- CAM/FV3 grids -->
   <grid name="a%C24" >
     <mach name="any" >
@@ -1627,6 +1702,41 @@
   </grid>
 
   <grid name="a%C96" >
+    <mach name="derecho" >
+      <pes pesize="any" compset="any">
+        <comment>none</comment>
+	      <ntasks>
+	        <ntasks_atm>128</ntasks_atm>
+	        <ntasks_lnd>128</ntasks_lnd>
+	        <ntasks_rof>128</ntasks_rof>
+	        <ntasks_ice>128</ntasks_ice>
+	        <ntasks_ocn>128</ntasks_ocn>
+	        <ntasks_glc>128</ntasks_glc>
+	        <ntasks_wav>128</ntasks_wav>
+	        <ntasks_cpl>128</ntasks_cpl>
+	      </ntasks>
+	      <nthrds>
+	        <nthrds_atm>1</nthrds_atm>
+	        <nthrds_lnd>1</nthrds_lnd>
+	        <nthrds_rof>1</nthrds_rof>
+	        <nthrds_ice>1</nthrds_ice>
+	        <nthrds_ocn>1</nthrds_ocn>
+	        <nthrds_glc>1</nthrds_glc>
+	        <nthrds_wav>1</nthrds_wav>
+	        <nthrds_cpl>1</nthrds_cpl>
+	      </nthrds>
+	      <rootpe>
+	        <rootpe_atm>0</rootpe_atm>
+	        <rootpe_lnd>0</rootpe_lnd>
+	        <rootpe_rof>0</rootpe_rof>
+	        <rootpe_ice>0</rootpe_ice>
+	        <rootpe_ocn>0</rootpe_ocn>
+	        <rootpe_glc>0</rootpe_glc>
+	        <rootpe_wav>0</rootpe_wav>
+	        <rootpe_cpl>0</rootpe_cpl>
+        </rootpe>
+      </pes>
+    </mach>
     <mach name="any" >
       <pes pesize="any" compset="any">
         <comment>none</comment>

diff --git a/doc/ChangeLog b/doc/ChangeLog
@@ -1,3 +1,122 @@
+
+===============================================================
+
+Tag name: cam6_3_136
+Originator(s): cacraig, fischer
+Date: Nov 18, 2023
+One-line Summary: Update externals to match cesm2_3_alpha16g and fix failing derecho tests
+Github PR URL: https://github.com/ESCOMP/CAM/pull/914
+
+Purpose of changes (include the issue number and title text for each relevant GitHub issue):
+- Fix failing derecho regression tests: https://github.com/ESCOMP/CAM/issues/892
+
+Describe any changes made to build system: N/A
+
+Describe any changes made to the namelist: N/A
+
+List any changes to the defaults for the boundary datasets: N/A
+
+Describe any substantial timing or memory changes: N/A
+
+Code reviewed by: nusbaume
+
+List all files eliminated: N/A
+
+List all files added and what they do: N/A
+
+List all existing files that have been modified, and describe the changes:
+M       Externals.cfg
+          - update Externals to match cesm2_3_alpha16g
+
+M       cime_config/SystemTests/tmc.py
+          - Fix from Chris Fischer for failing TMC regression test
+
+M       cime_config/config_pes.xml
+          - Update derecho PE layouts
+
+M       doc/ChangeLog_template
+          - Add derecho regression testing
+
+If there were any failures reported from running test_driver.sh on any test
+platform, and checkin with these failures has been OK'd by the gatekeeper,
+then copy the lines from the td.*.status files for the failed tests to the
+appropriate machine below.  All failed tests must be justified.
+
+All tests had namelist changes due to externals update
+
+cheyenne/intel/aux_cam:
+  ERP_Ln9_Vnuopc.C96_C96_mg17.F2000climo.cheyenne_intel.cam-outfrq9s_mg3 (Overall: FAIL) details:
+    FAIL ERP_Ln9_Vnuopc.C96_C96_mg17.F2000climo.cheyenne_intel.cam-outfrq9s_mg3 MODEL_BUILD time=3
+  ERP_Ln9_Vnuopc.f09_f09_mg17.FCSD_HCO.cheyenne_intel.cam-outfrq9s (Overall: FAIL) details:
+    FAIL ERP_Ln9_Vnuopc.f09_f09_mg17.FCSD_HCO.cheyenne_intel.cam-outfrq9s COMPARE_base_rest
+  SMS_Lh12_Vnuopc.f09_f09_mg17.FCSD_HCO.cheyenne_intel.cam-outfrq3h (Overall: DIFF) details:
+    FAIL SMS_Lh12_Vnuopc.f09_f09_mg17.FCSD_HCO.cheyenne_intel.cam-outfrq3h BASELINE /glade/p/cesm/amwg/cesm_baselines/cam6_3_135: DIFF
+     - pre-existing failures
+
+  ERP_D_Ln9.ne30pg3_ne30pg3_mg17.FLTHIST.cheyenne_intel.cam-outfrq9s (Overall: DIFF) details:
+  ERP_D_Ln9_Vnuopc.ne30pg3_ne30pg3_mg17.F2000dev.cheyenne_intel.cam-outfrq9s (Overall: DIFF) details:
+  ERP_Ld3_Vnuopc.f09_f09_mg17.FWHIST.cheyenne_intel.cam-reduced_hist1d (Overall: DIFF) details:
+  ERP_Lh12_Vnuopc.f19_f19_mg17.FW4madSD.cheyenne_intel.cam-outfrq3h (Overall: DIFF) details:
+  ERP_Ln9_Vnuopc.f09_f09_mg17.F1850.cheyenne_intel.cam-outfrq9s (Overall: DIFF) details:
+  ERP_Ln9_Vnuopc.f09_f09_mg17.F2000climo.cheyenne_intel.cam-outfrq9s (Overall: DIFF) details:
+  ERP_Ln9_Vnuopc.f09_f09_mg17.F2000dev.cheyenne_intel.cam-outfrq9s_mg3 (Overall: DIFF) details:
+  ERP_Ln9_Vnuopc.f09_f09_mg17.F2010climo.cheyenne_intel.cam-outfrq9s (Overall: DIFF) details:
+  ERP_Ln9_Vnuopc.f09_f09_mg17.FHIST_BDRD.cheyenne_intel.cam-outfrq9s (Overall: DIFF) details:
+  ERP_Ln9_Vnuopc.f19_f19_mg17.FWsc1850.cheyenne_intel.cam-outfrq9s (Overall: DIFF) details:
+  ERP_Ln9_Vnuopc.ne30_ne30_mg17.FCnudged.cheyenne_intel.cam-outfrq9s (Overall: DIFF) details:
+  ERP_Ln9_Vnuopc.ne30pg3_ne30pg3_mg17.FW2000climo.cheyenne_intel.cam-outfrq9s_wcm_ne30 (Overall: DIFF) details:
+  ERS_Ld3_Vnuopc.f10_f10_mg37.F1850.cheyenne_intel.cam-outfrq1d_14dec_ghg_cam_dev (Overall: DIFF) details:
+  ERS_Ln9_P288x1_Vnuopc.mpasa120_mpasa120.F2000climo.cheyenne_intel.cam-outfrq9s_mpasa120 (Overall: DIFF) details:
+  ERS_Ln9_P36x1_Vnuopc.mpasa480_mpasa480.F2000climo.cheyenne_intel.cam-outfrq9s_mpasa480 (Overall: DIFF) details:
+  ERS_Ln9_Vnuopc.f09_f09_mg17.FX2000.cheyenne_intel.cam-outfrq9s (Overall: DIFF) details:
+  ERS_Ln9_Vnuopc.f19_f19_mg17.FSPCAMS.cheyenne_intel.cam-outfrq9s (Overall: DIFF) details:
+  ERS_Ln9_Vnuopc.f19_f19_mg17.FXSD.cheyenne_intel.cam-outfrq9s (Overall: DIFF) details:
+  SMS_D_Ln9.ne30pg3_ne30pg3_mg17.FMTHIST.cheyenne_intel.cam-outfrq9s (Overall: DIFF) details:
+  SMS_D_Ln9_Vnuopc.f09_f09_mg17.FCts2nudged.cheyenne_intel.cam-outfrq9s_leapday (Overall: DIFF) details:
+  SMS_D_Ln9_Vnuopc.f09_f09_mg17.FCvbsxHIST.cheyenne_intel.cam-outfrq9s (Overall: DIFF) details:
+  SMS_D_Ln9_Vnuopc.f09_f09_mg17.FSD.cheyenne_intel.cam-outfrq9s (Overall: DIFF) details:
+  SMS_D_Ln9_Vnuopc.f19_f19_mg17.FWma2000climo.cheyenne_intel.cam-outfrq9s (Overall: DIFF) details:
+  SMS_D_Ln9_Vnuopc.f19_f19_mg17.FWma2000climo.cheyenne_intel.cam-outfrq9s_waccm_ma_mam4 (Overall: DIFF) details:
+  SMS_D_Ln9_Vnuopc.f19_f19_mg17.FXHIST.cheyenne_intel.cam-outfrq9s_amie (Overall: DIFF) details:
+  SMS_D_Ln9_Vnuopc.ne16_ne16_mg17.FX2000.cheyenne_intel.cam-outfrq9s (Overall: DIFF) details:
+  SMS_D_Ln9_Vnuopc_P1280x1.ne0ARCTICne30x4_ne0ARCTICne30x4_mt12.FHIST.cheyenne_intel.cam-outfrq9s (Overall: DIFF) details:
+  SMS_D_Ln9_Vnuopc_P1280x1.ne0CONUSne30x8_ne0CONUSne30x8_mt12.FCHIST.cheyenne_intel.cam-outfrq9s (Overall: DIFF) details:
+  SMS_D_Ln9_Vnuopc_P1280x1.ne30pg3_ne30pg3_mg17.FCLTHIST.cheyenne_intel.cam-outfrq9s (Overall: DIFF) details:
+  SMS_Ld1_Vnuopc.f09_f09_mg17.FW2000climo.cheyenne_intel.cam-outfrq1d (Overall: DIFF) details:
+  SMS_Ld1_Vnuopc.f19_f19.F2000dev.cheyenne_intel.cam-outfrq1d (Overall: DIFF) details:
+  SMS_Ld1_Vnuopc.ne30pg3_ne30pg3_mg17.FC2010climo.cheyenne_intel.cam-outfrq1d (Overall: DIFF) details:
+  SMS_Lh12_Vnuopc.f09_f09_mg17.FCSD_HCO.cheyenne_intel.cam-outfrq3h (Overall: DIFF) details:
+  SMS_Lm13_Vnuopc.f10_f10_mg37.F2000climo.cheyenne_intel.cam-outfrq1m (Overall: DIFF) details:
+  SMS_Ln9_Vnuopc.f09_f09_mg17.F2010climo.cheyenne_intel.cam-nudging (Overall: DIFF) details:
+  SMS_Ln9_Vnuopc.f09_f09_mg17.FW1850.cheyenne_intel.cam-reduced_hist3s (Overall: DIFF) details:
+  SMS_Ln9_Vnuopc.f19_f19.F2000climo.cheyenne_intel.cam-silhs (Overall: DIFF) details:
+  SMS_Ln9_Vnuopc.f19_f19_mg17.FHIST.cheyenne_intel.cam-outfrq9s_nochem (Overall: DIFF) details:
+      - Differences due to externals updated
+
+derecho/intel/aux_cam: no baseline comparisons due to being first official testing on derecho
+  ERP_Ln9_Vnuopc.C96_C96_mg17.F2000climo.derecho_intel.cam-outfrq9s_mg3 (Overall: PEND) details:
+    PEND ERP_Ln9_Vnuopc.C96_C96_mg17.F2000climo.derecho_intel.cam-outfrq9s_mg3 SHAREDLIB_BUILD
+  ERP_Ln9_Vnuopc.f09_f09_mg17.FCSD_HCO.derecho_intel.cam-outfrq9s (Overall: FAIL) details:
+    FAIL ERP_Ln9_Vnuopc.f09_f09_mg17.FCSD_HCO.derecho_intel.cam-outfrq9s COMPARE_base_rest
+      - pre-existing failures on cheyenne
+
+  ERP_Ln9_Vnuopc.ne30pg3_ne30pg3_mg17.FW2000climo.derecho_intel.cam-outfrq9s_wcm_ne30 (Overall: PEND) details:
+    PEND ERP_Ln9_Vnuopc.ne30pg3_ne30pg3_mg17.FW2000climo.derecho_intel.cam-outfrq9s_wcm_ne30 RUN
+    PEND ERP_Ln9_Vnuopc.ne30pg3_ne30pg3_mg17.FW2000climo.derecho_intel.cam-outfrq9s_wcm_ne30 COMPARE_base_rest
+      - unknown test failure - repeatable
+
+izumi/nag/aux_cam:
+    DAE_Vnuopc.f45_f45_mg37.FHS94.izumi_nag.cam-dae (Overall: FAIL) details:
+      FAIL DAE_Vnuopc.f45_f45_mg37.FHS94.izumi_nag.cam-dae RUN time=80
+    - pre-existing failure
+
+
+izumi/gnu/aux_cam:
+  SMS_D_Ln9.f10_f10_mg37.2000_CAM%DEV%GHGMAM4_CLM50%SP_CICE%PRES_DOCN%DOM_MOSART_SGLC_SWAV_SESP.izumi_gnu.cam-outfrq9s (Overall: DIFF) details:
+  SMS_P48x1_D_Ln9_Vnuopc.f19_f19_mg17.FW4madSD.izumi_gnu.cam-outfrq9s (Overall: DIFF) details:
+     - baseline diffs due to externals update
+
+===============================================================
 ===============================================================
 
 Tag name: cam6_3_135

diff --git a/doc/ChangeLog_template b/doc/ChangeLog_template
@@ -31,6 +31,8 @@ appropriate machine below.  All failed tests must be justified.
 
 cheyenne/intel/aux_cam:
 
+derecho/intel/aux_cam:
+
 izumi/nag/aux_cam:
 
 izumi/gnu/aux_cam: