i#5365 AArch64 SVE core, part 2: add signals support #6725
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This patch adds SVE support for signals in the core. It is the follow on patch from the SVE core work part 1, in PR #5835 (f646a63) and includes vector address computation for SVE scatter/gather, enabling first-fault load handling. Issue: #5365, #5036 Co-authored-by: Jack Gallagher <[email protected]>
… in runsuite_wrapper.pl
Update VQ/vq, VL/vl and sve_vq_from_vl() to make them more descriptive and readable. Add comment describing rationale of using quadwords.
AssadHashmi
changed the title
Re-requested review. |
derekbruening
approved these changes
Apr 3, 2024
…er addressing modes. Add reference to i#6750 in implementation of reg_is_pointer_sized(). Explicitly remind readers that quadwords in AArch64 are 128 bits. Clarify vector doubleword destination in explanatory comments
A mistake in the original patch flipped the position of the #if and if()
lines:
if (opnd_is_vsib(curop)) {
#ifdef X86
became:
#if defined(X86) || defined(AARCH64)
if (opnd_is_vector_base_disp(curop)) {
which meant the CLIENT_ASSERT() which followed it would always be hit on
ARM or RISCV64.
I have changed it to remove the #if defined(..) lines and provide a
stub implementation of instr_compute_vector_address() for AArch32 and
RISC-V.
abhinav92003
added a commit
that referenced
this pull request
Apr 5, 2024
Fixes the slot used to save and restore FP regs at fcache enter and return events. PR #6725 adjusted the slots used during signal handling in core/unix/signal_linux_aarch64.c but did not adjust the same in fcache enter/exit and attach events. Prior to that the FP regs were simply stored in a continuous manner in signal handling code, and fcache enter/exit routines. The mismatch between slot usage caused failueres in the signalNNN1 tests on some systems.
abhinav92003
added a commit
that referenced
this pull request
Apr 5, 2024
Fixes the slot used to save and restore FP regs at fcache enter and return events. PR #6725 adjusted the slots used during signal handling in core/unix/signal_linux_aarch64.c but did not adjust the same in fcache enter/return and attach events. Prior to that PR, the FP regs were simply stored in a contiguous manner in signal handling code and fcache enter/return routines (instead of in their respective dr_simd_t struct member), which was a bit confusing. The mismatch between slot usage in signal handling and fcache enter/return code caused failures in the signalNNN1 tests on some systems. Verified that those tests pass with this fix. Also fixes the same issue in save_priv_mcontext_helper which is used in the dr_app_start API. Unit tests for this scenario will be added as part of #6759. Issue: #5036, #6755, #5365 Fixes #6758
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This patch adds SVE support for signals in the core. It is the follow on patch from the SVE core work part 1, in PR #5835 (f646a63) and includes vector address computation for SVE scatter/gather, enabling first-fault load handling.
Issue: #5365, #5036
Co-authored-by: Jack Gallagher [email protected]