From d8334581ef43b34fd65ffca548a9b097455340f3 Mon Sep 17 00:00:00 2001 From: Yang Liu Date: Thu, 7 Dec 2023 04:33:56 +0800 Subject: [PATCH] i#3544 RV64: Adds immediate display format via IR (#6489) Instructions created by `INSTR_CREATE_*` macros now automatically set the immediate display format. Also enables tool.drdisas test. Issue #3544 --- clients/drdisas/test_simple.template | 7 + core/arch/mangle_shared.c | 9 +- core/arch/riscv64/emit_utils.c | 13 +- core/arch/riscv64/mangle.c | 99 +++---- core/ir/riscv64/codec.c | 3 +- core/ir/riscv64/codec.py | 93 ++++++- core/ir/riscv64/instr_create_api.h.in | 4 +- core/ir/riscv64/ir_utils.c | 13 +- core/ir/riscv64/isl/README.md | 1 + suite/tests/CMakeLists.txt | 3 + suite/tests/api/ir_riscv64.c | 366 +++++++++----------------- suite/tests/api/ir_riscv64.expect | 17 +- 12 files changed, 279 insertions(+), 349 deletions(-) diff --git a/clients/drdisas/test_simple.template b/clients/drdisas/test_simple.template index 65b3112414e..512e6ad2993 100644 --- a/clients/drdisas/test_simple.template +++ b/clients/drdisas/test_simple.template @@ -22,4 +22,11 @@ disassembly failed: invalid instruction: not enough bytes: 0x88 c4 e2 65 90 14 80 vpgatherdd (%eax,%ymm0,4)[4byte] %ymm3 -> %ymm2 %ymm3 # endif disassembly failed: invalid instruction: not enough bytes: 0x88 +#elif defined(RISCV64) + 853e c.mv zero a5 -> a0 + 4581 c.li zero 0 -> a1 + 1d27b783 ld +466(a5)[8byte] -> a5 + 00f55733 srl a0 a5 -> a4 + 9d89 c.subw a1 a0 -> a1 +disassembly failed: invalid instruction: not enough bytes: 0x88 #endif diff --git a/core/arch/mangle_shared.c b/core/arch/mangle_shared.c index fc3c48df864..d8e5ad4e000 100644 --- a/core/arch/mangle_shared.c +++ b/core/arch/mangle_shared.c @@ -584,12 +584,11 @@ insert_parameter_preparation(dcontext_t *dcontext, instrlist_t *ilist, instr_t * if (opnd_is_reglike(arg)) { /* sd x(...), i*XSP_SZ(sp) */ PRE(ilist, instr, - XINST_CREATE_store( - dcontext, - opnd_add_flags(opnd_create_base_disp(DR_REG_XSP, DR_REG_NULL, 0, + XINST_CREATE_store(dcontext, + opnd_create_base_disp(DR_REG_XSP, DR_REG_NULL, 0, i * XSP_SZ, OPSZ_PTR), - DR_OPND_IMM_PRINT_DECIMAL), - opnd_is_reg(arg) ? arg : opnd_create_reg(DR_REG_ZERO))); + opnd_is_reg(arg) ? arg + : opnd_create_reg(DR_REG_ZERO))); } } # else /* ARM */ diff --git a/core/arch/riscv64/emit_utils.c b/core/arch/riscv64/emit_utils.c index 583dc4abbf5..1809c0ff251 100644 --- a/core/arch/riscv64/emit_utils.c +++ b/core/arch/riscv64/emit_utils.c @@ -866,14 +866,11 @@ emit_indirect_branch_lookup(dcontext_t *dc, generated_code_t *code, byte *pc, /* Now, a1 holds the hash table index, use slli+add to get the table entry. */ ASSERT(4 - HASHTABLE_IBL_OFFSET(ibl_code->branch_type) >= 0); if (4 - HASHTABLE_IBL_OFFSET(ibl_code->branch_type) > 0) { - /* TODO i#3544: Immediate display format should be auto-added by the IR. */ APP(&ilist, INSTR_CREATE_slli( dc, opnd_create_reg(DR_REG_A1), opnd_create_reg(DR_REG_A1), - opnd_add_flags( - opnd_create_immed_int(4 - HASHTABLE_IBL_OFFSET(ibl_code->branch_type), - OPSZ_6b), - DR_OPND_IMM_PRINT_DECIMAL))); + opnd_create_immed_int(4 - HASHTABLE_IBL_OFFSET(ibl_code->branch_type), + OPSZ_6b))); } APP(&ilist, INSTR_CREATE_add(dc, opnd_create_reg(DR_REG_A1), opnd_create_reg(DR_REG_A0), @@ -1076,10 +1073,8 @@ append_fcache_enter_prologue(dcontext_t *dcontext, instrlist_t *ilist, bool abso XINST_CREATE_move(dcontext, opnd_create_reg(REG_DCXT), opnd_create_reg(DR_REG_A0))); APP(ilist, - INSTR_CREATE_lb( - dcontext, opnd_create_reg(DR_REG_A2), - opnd_add_flags(OPND_DC_FIELD(absolute, dcontext, OPSZ_1, SIGPENDING_OFFSET), - DR_OPND_IMM_PRINT_DECIMAL))); + INSTR_CREATE_lb(dcontext, opnd_create_reg(DR_REG_A2), + OPND_DC_FIELD(absolute, dcontext, OPSZ_1, SIGPENDING_OFFSET))); APP(ilist, INSTR_CREATE_bge(dcontext, opnd_create_instr(no_signals), opnd_create_reg(DR_REG_ZERO), opnd_create_reg(DR_REG_A2))); diff --git a/core/arch/riscv64/mangle.c b/core/arch/riscv64/mangle.c index 485883df892..6aab0dceee7 100644 --- a/core/arch/riscv64/mangle.c +++ b/core/arch/riscv64/mangle.c @@ -86,8 +86,7 @@ insert_push_all_registers(dcontext_t *dcontext, clean_call_info_t *cci, PRE(ilist, instr, INSTR_CREATE_addi(dcontext, opnd_create_reg(DR_REG_SP), opnd_create_reg(DR_REG_SP), - opnd_add_flags(opnd_create_immed_int(-max_offs, OPSZ_12b), - DR_OPND_IMM_PRINT_DECIMAL))); + opnd_create_immed_int(-max_offs, OPSZ_12b))); /* Skip X0 slot. */ dstack_offs += XSP_SZ; @@ -98,12 +97,10 @@ insert_push_all_registers(dcontext_t *dcontext, clean_call_info_t *cci, continue; PRE(ilist, instr, - INSTR_CREATE_sd( - dcontext, - opnd_add_flags(opnd_create_base_disp(DR_REG_SP, DR_REG_NULL, 0, - dstack_offs + i * XSP_SZ, OPSZ_8), - DR_OPND_IMM_PRINT_DECIMAL), - opnd_create_reg(DR_REG_START_GPR + i))); + INSTR_CREATE_sd(dcontext, + opnd_create_base_disp(DR_REG_SP, DR_REG_NULL, 0, + dstack_offs + i * XSP_SZ, OPSZ_8), + opnd_create_reg(DR_REG_START_GPR + i))); } dstack_offs += DR_NUM_GPR_REGS * XSP_SZ; @@ -127,12 +124,10 @@ insert_push_all_registers(dcontext_t *dcontext, clean_call_info_t *cci, /* Push FPRs. */ for (int i = 0; i < DR_NUM_FPR_REGS; i++) { PRE(ilist, instr, - INSTR_CREATE_fsd( - dcontext, - opnd_add_flags(opnd_create_base_disp(DR_REG_SP, DR_REG_NULL, 0, - dstack_offs + i * XSP_SZ, OPSZ_8), - DR_OPND_IMM_PRINT_DECIMAL), - opnd_create_reg(DR_REG_F0 + i))); + INSTR_CREATE_fsd(dcontext, + opnd_create_base_disp(DR_REG_SP, DR_REG_NULL, 0, + dstack_offs + i * XSP_SZ, OPSZ_8), + opnd_create_reg(DR_REG_F0 + i))); } dstack_offs += DR_NUM_FPR_REGS * XSP_SZ; @@ -187,11 +182,9 @@ insert_pop_all_registers(dcontext_t *dcontext, clean_call_info_t *cci, instrlist /* Pop FPRs. */ for (int i = 0; i < DR_NUM_FPR_REGS; i++) { PRE(ilist, instr, - INSTR_CREATE_fld( - dcontext, opnd_create_reg(DR_REG_F0 + i), - opnd_add_flags(opnd_create_base_disp(DR_REG_SP, DR_REG_NULL, 0, - current_offs + i * XSP_SZ, OPSZ_8), - DR_OPND_IMM_PRINT_DECIMAL))); + INSTR_CREATE_fld(dcontext, opnd_create_reg(DR_REG_F0 + i), + opnd_create_base_disp(DR_REG_SP, DR_REG_NULL, 0, + current_offs + i * XSP_SZ, OPSZ_8))); } /* Skip pc field. */ @@ -205,11 +198,9 @@ insert_pop_all_registers(dcontext_t *dcontext, clean_call_info_t *cci, instrlist continue; PRE(ilist, instr, - INSTR_CREATE_ld( - dcontext, opnd_create_reg(DR_REG_START_GPR + i), - opnd_add_flags(opnd_create_base_disp(DR_REG_SP, DR_REG_NULL, 0, - current_offs + i * XSP_SZ, OPSZ_8), - DR_OPND_IMM_PRINT_DECIMAL))); + INSTR_CREATE_ld(dcontext, opnd_create_reg(DR_REG_START_GPR + i), + opnd_create_base_disp(DR_REG_SP, DR_REG_NULL, 0, + current_offs + i * XSP_SZ, OPSZ_8))); } } @@ -471,12 +462,10 @@ mangle_stolen_reg_and_tp_reg(dcontext_t *dcontext, instrlist_t *ilist, instr_t * if (opnd_is_reg(curop) && opnd_get_reg(curop) == DR_REG_TP) instr_set_dst(instr, i, opnd_create_reg(scratch_reg)); else if (opnd_is_base_disp(curop) && opnd_get_base(curop) == DR_REG_TP) { - instr_set_dst( - instr, i, - opnd_add_flags(opnd_create_base_disp(scratch_reg, DR_REG_NULL, 0, - opnd_get_disp(curop), - opnd_get_size(curop)), - DR_OPND_IMM_PRINT_DECIMAL)); + instr_set_dst(instr, i, + opnd_create_base_disp(scratch_reg, DR_REG_NULL, 0, + opnd_get_disp(curop), + opnd_get_size(curop))); } } for (i = 0; i < instr_num_srcs(instr); i++) { @@ -484,12 +473,10 @@ mangle_stolen_reg_and_tp_reg(dcontext_t *dcontext, instrlist_t *ilist, instr_t * if (opnd_is_reg(curop) && opnd_get_reg(curop) == DR_REG_TP) instr_set_src(instr, i, opnd_create_reg(scratch_reg)); else if (opnd_is_base_disp(curop) && opnd_get_base(curop) == DR_REG_TP) { - instr_set_src( - instr, i, - opnd_add_flags(opnd_create_base_disp(scratch_reg, DR_REG_NULL, 0, - opnd_get_disp(curop), - opnd_get_size(curop)), - DR_OPND_IMM_PRINT_DECIMAL)); + instr_set_src(instr, i, + opnd_create_base_disp(scratch_reg, DR_REG_NULL, 0, + opnd_get_disp(curop), + opnd_get_size(curop))); } } instr_set_translation(instr, instrlist_get_translation_target(ilist)); @@ -517,12 +504,10 @@ mangle_stolen_reg_and_tp_reg(dcontext_t *dcontext, instrlist_t *ilist, instr_t * if (opnd_is_reg(curop) && opnd_get_reg(curop) == dr_reg_stolen) instr_set_dst(instr, i, opnd_create_reg(scratch_reg)); else if (opnd_is_base_disp(curop) && opnd_get_base(curop) == dr_reg_stolen) { - instr_set_dst( - instr, i, - opnd_add_flags(opnd_create_base_disp(scratch_reg, DR_REG_NULL, 0, - opnd_get_disp(curop), - opnd_get_size(curop)), - DR_OPND_IMM_PRINT_DECIMAL)); + instr_set_dst(instr, i, + opnd_create_base_disp(scratch_reg, DR_REG_NULL, 0, + opnd_get_disp(curop), + opnd_get_size(curop))); } } for (i = 0; i < instr_num_srcs(instr); i++) { @@ -530,12 +515,10 @@ mangle_stolen_reg_and_tp_reg(dcontext_t *dcontext, instrlist_t *ilist, instr_t * if (opnd_is_reg(curop) && opnd_get_reg(curop) == dr_reg_stolen) instr_set_src(instr, i, opnd_create_reg(scratch_reg)); else if (opnd_is_base_disp(curop) && opnd_get_base(curop) == dr_reg_stolen) { - instr_set_src( - instr, i, - opnd_add_flags(opnd_create_base_disp(scratch_reg, DR_REG_NULL, 0, - opnd_get_disp(curop), - opnd_get_size(curop)), - DR_OPND_IMM_PRINT_DECIMAL)); + instr_set_src(instr, i, + opnd_create_base_disp(scratch_reg, DR_REG_NULL, 0, + opnd_get_disp(curop), + opnd_get_size(curop))); } } instr_set_translation(instr, instrlist_get_translation_target(ilist)); @@ -749,10 +732,8 @@ mangle_exclusive_load(dcontext_t *dcontext, instrlist_t *ilist, instr_t *instr, instr_set_opcode(instr, opcode); instr_set_num_opnds(dcontext, instr, 1, 1); instr_set_dst(instr, 0, dst); - instr_set_src( - instr, 0, - opnd_add_flags(opnd_create_base_disp(opnd_get_reg(src0), DR_REG_NULL, 0, 0, opsz), - DR_OPND_IMM_PRINT_DECIMAL)); + instr_set_src(instr, 0, + opnd_create_base_disp(opnd_get_reg(src0), DR_REG_NULL, 0, 0, opsz)); instr_set_translation(instr, instrlist_get_translation_target(ilist)); /* Keep the acquire semantics if needed. */ @@ -773,9 +754,7 @@ mangle_exclusive_load(dcontext_t *dcontext, instrlist_t *ilist, instr_t *instr, PRE(ilist, next_instr, XINST_CREATE_load_int( dcontext, opnd_create_reg(scratch_reg1), - opnd_add_flags( - opnd_create_immed_int(opnd_get_size(instr_get_src(instr, 0)), OPSZ_12b), - DR_OPND_IMM_PRINT_DECIMAL))); + opnd_create_immed_int(opnd_get_size(instr_get_src(instr, 0)), OPSZ_12b))); PRE(ilist, next_instr, instr_create_save_to_tls(dcontext, scratch_reg1, TLS_LRSC_SIZE_SLOT)); @@ -830,8 +809,7 @@ mangle_exclusive_store(dcontext_t *dcontext, instrlist_t *ilist, instr_t *instr, instr_create_restore_from_tls(dcontext, scratch_reg1, TLS_LRSC_SIZE_SLOT)); PRE(ilist, instr, XINST_CREATE_load_int(dcontext, opnd_create_reg(scratch_reg2), - opnd_add_flags(opnd_create_immed_int(opsz, OPSZ_12b), - DR_OPND_IMM_PRINT_DECIMAL))); + opnd_create_immed_int(opsz, OPSZ_12b))); PRE(ilist, instr, INSTR_CREATE_bne(dcontext, opnd_create_instr(fail), opnd_create_reg(scratch_reg1), opnd_create_reg(scratch_reg2))); @@ -863,9 +841,7 @@ mangle_exclusive_store(dcontext_t *dcontext, instrlist_t *ilist, instr_t *instr, /* Write a non-zero value to dst on fail. */ PRE(ilist, next_instr, fail); PRE(ilist, next_instr, - XINST_CREATE_load_int(dcontext, dst, - opnd_add_flags(opnd_create_immed_int(1, OPSZ_12b), - DR_OPND_IMM_PRINT_DECIMAL))); + XINST_CREATE_load_int(dcontext, dst, opnd_create_immed_int(1, OPSZ_12b))); PRE(ilist, next_instr, final); @@ -874,8 +850,7 @@ mangle_exclusive_store(dcontext_t *dcontext, instrlist_t *ilist, instr_t *instr, */ PRE(ilist, next_instr, XINST_CREATE_load_int(dcontext, opnd_create_reg(scratch_reg1), - opnd_add_flags(opnd_create_immed_int(-1, OPSZ_12b), - DR_OPND_IMM_PRINT_DECIMAL))); + opnd_create_immed_int(-1, OPSZ_12b))); PRE(ilist, next_instr, instr_create_save_to_tls(dcontext, scratch_reg1, TLS_LRSC_ADDR_SLOT)); diff --git a/core/ir/riscv64/codec.c b/core/ir/riscv64/codec.c index 484a4e46859..034c6ccfce8 100644 --- a/core/ir/riscv64/codec.c +++ b/core/ir/riscv64/codec.c @@ -1159,7 +1159,8 @@ decode_iimm_0_opnd(dcontext_t *dc, uint32_t inst, int op_sz, byte *pc, byte *ori int idx, instr_t *out) { ASSERT(idx == 1); - opnd_t opnd = opnd_create_immed_int(0, op_sz); + opnd_t opnd = + opnd_add_flags(opnd_create_immed_int(0, op_sz), DR_OPND_IMM_PRINT_DECIMAL); instr_set_src(out, idx, opnd); return true; } diff --git a/core/ir/riscv64/codec.py b/core/ir/riscv64/codec.py index dbad205dc5d..2cad2cb08c9 100755 --- a/core/ir/riscv64/codec.py +++ b/core/ir/riscv64/codec.py @@ -114,9 +114,10 @@ class Field(str, Enum): opsz_def: dict[str, str] | str is_dest: bool is_implicit: bool + as_decimal: bool def __new__(cls, value: int, arg_name: str, is_dest: bool, is_implicit: bool, - opsz_def: dict[str, str] | str, asm_name: str, + as_decimal, opsz_def: dict[str, str] | str, asm_name: str, arg_cmt: str): # Take str as a base object because we need a concrete class. It won't # be used anyway. @@ -128,6 +129,7 @@ def __new__(cls, value: int, arg_name: str, is_dest: bool, is_implicit: bool, obj.arg_cmt = arg_cmt obj.is_dest = is_dest obj.is_implicit = is_implicit + obj.as_decimal = as_decimal return obj # Fields in uncompressed instructions. @@ -135,6 +137,7 @@ def __new__(cls, value: int, arg_name: str, is_dest: bool, is_implicit: bool, 'rd', True, False, + False, 'OPSZ_PTR', '', 'The output register (inst[11:7]).' @@ -143,6 +146,7 @@ def __new__(cls, value: int, arg_name: str, is_dest: bool, is_implicit: bool, 'rd', True, False, + False, 'OPSZ_PTR', '', 'The output floating-point register (inst[11:7]).' @@ -151,6 +155,7 @@ def __new__(cls, value: int, arg_name: str, is_dest: bool, is_implicit: bool, 'rs1', False, False, + False, 'OPSZ_PTR', '', 'The first input register (inst[19:15]).' @@ -159,6 +164,7 @@ def __new__(cls, value: int, arg_name: str, is_dest: bool, is_implicit: bool, 'rs1', False, False, + False, 'OPSZ_PTR', '', 'The first input floating-point register (inst[19:15]).' @@ -167,6 +173,7 @@ def __new__(cls, value: int, arg_name: str, is_dest: bool, is_implicit: bool, 'base', False, False, + False, 'OPSZ_0', '', 'The `base` field in RISC-V Base Cache Management Operation ISA Extensions (inst[19:15]).' @@ -175,6 +182,7 @@ def __new__(cls, value: int, arg_name: str, is_dest: bool, is_implicit: bool, 'rs2', False, False, + False, 'OPSZ_PTR', '', 'The second input register (inst[24:20]).' @@ -183,6 +191,7 @@ def __new__(cls, value: int, arg_name: str, is_dest: bool, is_implicit: bool, 'rs2', False, False, + False, 'OPSZ_PTR', '', 'The second input floating-point register (inst[24:20]).' @@ -191,6 +200,7 @@ def __new__(cls, value: int, arg_name: str, is_dest: bool, is_implicit: bool, 'rs3', False, False, + False, 'OPSZ_PTR', '', 'The third input register (inst[31:27]).' @@ -199,6 +209,7 @@ def __new__(cls, value: int, arg_name: str, is_dest: bool, is_implicit: bool, 'fm', False, False, + False, 'OPSZ_4b', '', 'The fence semantics (inst[31:28]).' @@ -207,6 +218,7 @@ def __new__(cls, value: int, arg_name: str, is_dest: bool, is_implicit: bool, 'pred', False, False, + False, 'OPSZ_4b', '', 'The bitmap with predecessor constraints for FENCE (inst[27:24]).' @@ -215,6 +227,7 @@ def __new__(cls, value: int, arg_name: str, is_dest: bool, is_implicit: bool, 'succ', False, False, + False, 'OPSZ_4b', '', 'The bitmap with successor constraints for FENCE (inst[23:20]).' @@ -223,6 +236,7 @@ def __new__(cls, value: int, arg_name: str, is_dest: bool, is_implicit: bool, 'aqrl', False, False, + False, 'OPSZ_2b', '', 'The acquire-release constraint field (inst[26:25]).' @@ -231,6 +245,7 @@ def __new__(cls, value: int, arg_name: str, is_dest: bool, is_implicit: bool, 'csr', False, False, + False, 'OPSZ_PTR', '', 'The configuration/status register id (inst[31:20]).' @@ -239,6 +254,7 @@ def __new__(cls, value: int, arg_name: str, is_dest: bool, is_implicit: bool, 'rm', False, False, + False, 'OPSZ_3b', '', 'The rounding-mode (inst[14:12]).' @@ -247,6 +263,7 @@ def __new__(cls, value: int, arg_name: str, is_dest: bool, is_implicit: bool, 'shamt', False, False, + True, 'OPSZ_5b', '', 'The `shamt` field (bit range is determined by XLEN).' @@ -255,6 +272,7 @@ def __new__(cls, value: int, arg_name: str, is_dest: bool, is_implicit: bool, 'shamt', False, False, + True, 'OPSZ_6b', '', 'The `shamt` field that uses only 5 bits.' @@ -263,6 +281,7 @@ def __new__(cls, value: int, arg_name: str, is_dest: bool, is_implicit: bool, 'shamt', False, False, + True, 'OPSZ_7b', '', 'The `shamt` field that uses only 6 bits.' @@ -271,6 +290,7 @@ def __new__(cls, value: int, arg_name: str, is_dest: bool, is_implicit: bool, 'imm', False, False, + True, 'OPSZ_12b', '', 'The immediate field in the I-type format.' @@ -279,6 +299,7 @@ def __new__(cls, value: int, arg_name: str, is_dest: bool, is_implicit: bool, 'imm', False, False, + True, 'OPSZ_12b', '', 'The immediate field in the S-type format.' @@ -287,6 +308,7 @@ def __new__(cls, value: int, arg_name: str, is_dest: bool, is_implicit: bool, 'pc_rel', False, False, + False, 'OPSZ_2', '', 'The immediate field in the B-type format.' @@ -295,6 +317,7 @@ def __new__(cls, value: int, arg_name: str, is_dest: bool, is_implicit: bool, 'imm', False, False, + False, 'OPSZ_20b', '', 'The 20-bit immediate field in the U-type format.' @@ -303,6 +326,7 @@ def __new__(cls, value: int, arg_name: str, is_dest: bool, is_implicit: bool, 'imm', False, False, + False, 'OPSZ_20b', '', 'The 20-bit immediate field in the U-type format (PC-relative).' @@ -311,6 +335,7 @@ def __new__(cls, value: int, arg_name: str, is_dest: bool, is_implicit: bool, 'pc_rel', False, False, + False, 'OPSZ_2', '', 'The immediate field in the J-type format.' @@ -319,6 +344,7 @@ def __new__(cls, value: int, arg_name: str, is_dest: bool, is_implicit: bool, 'imm', False, False, + False, 'OPSZ_12b', '', 'The immediate field in PREFETCH instructions.' @@ -327,6 +353,7 @@ def __new__(cls, value: int, arg_name: str, is_dest: bool, is_implicit: bool, 'rd', True, False, + False, 'OPSZ_PTR', '', 'The output register in `CR`, `CI` RVC formats (inst[11:7])' @@ -335,6 +362,7 @@ def __new__(cls, value: int, arg_name: str, is_dest: bool, is_implicit: bool, 'rd', True, False, + False, 'OPSZ_PTR', '', 'The output floating-point register in `CR`, `CI` RVC formats (inst[11:7])' @@ -343,6 +371,7 @@ def __new__(cls, value: int, arg_name: str, is_dest: bool, is_implicit: bool, 'rs1', False, False, + False, 'OPSZ_PTR', '', 'The first input register in `CR`, `CI` RVC formats (inst[11:7]).' @@ -351,6 +380,7 @@ def __new__(cls, value: int, arg_name: str, is_dest: bool, is_implicit: bool, 'rs2', False, False, + False, 'OPSZ_PTR', '', 'The second input register in `CR`, `CSS` RVC formats (inst[6:2]).' @@ -359,6 +389,7 @@ def __new__(cls, value: int, arg_name: str, is_dest: bool, is_implicit: bool, 'rs2', False, False, + False, 'OPSZ_PTR', '', 'The second input floating-point register in `CR`, `CSS` RVC formats (inst[6:2]).' @@ -368,6 +399,7 @@ def __new__(cls, value: int, arg_name: str, is_dest: bool, is_implicit: bool, 'rd', True, False, + False, 'OPSZ_PTR', '', 'The output register in `CIW`, `CL` RVC formats (inst[4:2])' @@ -376,6 +408,7 @@ def __new__(cls, value: int, arg_name: str, is_dest: bool, is_implicit: bool, 'rd', True, False, + False, 'OPSZ_PTR', '', 'The output floating-point register in `CIW`, `CL` RVC formats (inst[4:2])' @@ -384,6 +417,7 @@ def __new__(cls, value: int, arg_name: str, is_dest: bool, is_implicit: bool, 'rs1', False, False, + False, 'OPSZ_PTR', '', 'The first input register in `CL`, `CS`, `CA`, `CB` RVC formats (inst[9:7]).' @@ -392,6 +426,7 @@ def __new__(cls, value: int, arg_name: str, is_dest: bool, is_implicit: bool, 'rs2', False, False, + False, 'OPSZ_PTR', '', 'The second input register in `CS`, `CA` RVC formats (inst[4:2]).' @@ -400,6 +435,7 @@ def __new__(cls, value: int, arg_name: str, is_dest: bool, is_implicit: bool, 'rs2', False, False, + False, 'OPSZ_PTR', '', 'The second input floating-point register in `CS`, `CA` RVC formats (inst[4:2]).' @@ -408,6 +444,7 @@ def __new__(cls, value: int, arg_name: str, is_dest: bool, is_implicit: bool, 'rd', True, False, + False, 'OPSZ_PTR', '', 'The output register in `CA` RVC format (inst[9:7])' @@ -416,6 +453,7 @@ def __new__(cls, value: int, arg_name: str, is_dest: bool, is_implicit: bool, 'shamt', False, False, + True, 'OPSZ_6b', '', 'The `shamt` field in the RVC format.' @@ -424,6 +462,7 @@ def __new__(cls, value: int, arg_name: str, is_dest: bool, is_implicit: bool, 'imm', False, False, + True, 'OPSZ_5b', '', 'The immediate field in a CSR instruction.' @@ -432,6 +471,7 @@ def __new__(cls, value: int, arg_name: str, is_dest: bool, is_implicit: bool, 'imm', False, False, + True, 'OPSZ_10b', '', 'The immediate field in a C.ADDI16SP instruction.' @@ -440,6 +480,7 @@ def __new__(cls, value: int, arg_name: str, is_dest: bool, is_implicit: bool, 'sp_offset', False, False, + True, 'OPSZ_1', '', 'The SP-relative memory location (sp+imm: imm & 0x3 == 0).' @@ -448,6 +489,7 @@ def __new__(cls, value: int, arg_name: str, is_dest: bool, is_implicit: bool, 'sp_offset', False, False, + True, 'OPSZ_9b', '', 'The SP-relative memory location (sp+imm: imm & 0x7 == 0).' @@ -456,6 +498,7 @@ def __new__(cls, value: int, arg_name: str, is_dest: bool, is_implicit: bool, 'imm', False, False, + False, 'OPSZ_6b', '', 'The immediate field in a C.LUI instruction.' @@ -464,6 +507,7 @@ def __new__(cls, value: int, arg_name: str, is_dest: bool, is_implicit: bool, 'sp_offset', True, False, + True, 'OPSZ_1', '', 'The SP-relative memory location (sp+imm: imm & 0x3 == 0).' @@ -472,6 +516,7 @@ def __new__(cls, value: int, arg_name: str, is_dest: bool, is_implicit: bool, 'sp_offset', True, False, + True, 'OPSZ_9b', '', 'The SP-relative memory location (sp+imm: imm & 0x7 == 0).' @@ -480,6 +525,7 @@ def __new__(cls, value: int, arg_name: str, is_dest: bool, is_implicit: bool, 'imm', False, False, + True, 'OPSZ_10b', '', 'The immediate field in a CIW format instruction.' @@ -488,30 +534,35 @@ def __new__(cls, value: int, arg_name: str, is_dest: bool, is_implicit: bool, 'mem', False, False, + True, 'OPSZ_7b', - 'im(rs1)', 'The register-relative memory location (reg+imm: imm & 0x3 == 0).') + 'imm(rs1)', 'The register-relative memory location (reg+imm: imm & 0x3 == 0).') CLD_IMM = (46, 'mem', False, False, + True, 'OPSZ_1', - 'im(rs1)', 'The register-relative memory location (reg+imm: imm & 0x7 == 0).') + 'imm(rs1)', 'The register-relative memory location (reg+imm: imm & 0x7 == 0).') CSW_IMM = (47, 'mem', True, False, + True, 'OPSZ_7b', - 'im(rs1)', 'The register-relative memory location (reg+imm: imm & 0x3 == 0).') + 'imm(rs1)', 'The register-relative memory location (reg+imm: imm & 0x3 == 0).') CSD_IMM = (48, 'mem', True, False, + True, 'OPSZ_1', - 'im(rs1)', 'The register-relative memory location (reg+imm: imm & 0x7 == 0).') + 'imm(rs1)', 'The register-relative memory location (reg+imm: imm & 0x7 == 0).') CIMM5 = (49, 'imm', False, False, + True, 'OPSZ_6b', '', 'The immediate field in a C.ADDI, C.ADDIW, C.LI, and C.ANDI instruction.' @@ -520,6 +571,7 @@ def __new__(cls, value: int, arg_name: str, is_dest: bool, is_implicit: bool, 'pc_rel', False, False, + False, 'OPSZ_2', '', 'The immediate field in a a CB format instruction (C.BEQZ and C.BNEZ).' @@ -528,6 +580,7 @@ def __new__(cls, value: int, arg_name: str, is_dest: bool, is_implicit: bool, 'pc_rel', False, False, + False, 'OPSZ_2', '', 'The immediate field in a CJ format instruction.' @@ -537,6 +590,7 @@ def __new__(cls, value: int, arg_name: str, is_dest: bool, is_implicit: bool, 'mem', False, False, + True, { '': 'OPSZ_0', 'lb': 'OPSZ_1', 'lh': 'OPSZ_2', 'lw': 'OPSZ_4', 'ld': 'OPSZ_8', 'lbu': 'OPSZ_1', 'lhu': 'OPSZ_2', 'lwu': 'OPSZ_4', @@ -544,13 +598,14 @@ def __new__(cls, value: int, arg_name: str, is_dest: bool, is_implicit: bool, 'flw': 'OPSZ_4', 'fld': 'OPSZ_8', 'fsw': 'OPSZ_4', 'fsd': 'OPSZ_8', 'flq': 'OPSZ_16', 'fsq': 'OPSZ_16' }, - 'im(rs1)', + 'imm(rs1)', 'The register-relative memory source location (reg+imm).' ) V_S_RS1_DISP = (53, 'mem', True, False, + True, { '': 'OPSZ_0', 'lb': 'OPSZ_1', 'lh': 'OPSZ_2', 'lw': 'OPSZ_4', 'ld': 'OPSZ_8', 'lbu': 'OPSZ_1', 'lhu': 'OPSZ_2', 'lwu': 'OPSZ_4', @@ -558,13 +613,14 @@ def __new__(cls, value: int, arg_name: str, is_dest: bool, is_implicit: bool, 'flw': 'OPSZ_4', 'fld': 'OPSZ_8', 'fsw': 'OPSZ_4', 'fsd': 'OPSZ_8', 'flq': 'OPSZ_16', 'fsq': 'OPSZ_16' }, - 'im(rs1)', + 'imm(rs1)', 'The register-relative memory target location (reg+imm).' ) IRS1_SP = (54, 'opnd_create_reg(DR_REG_SP)', False, True, + False, 'OPSZ_PTR', 'rs1', 'Implicit rs1, always be sp.' @@ -573,6 +629,7 @@ def __new__(cls, value: int, arg_name: str, is_dest: bool, is_implicit: bool, 'opnd_create_reg(DR_REG_ZERO)', False, True, + False, 'OPSZ_PTR', 'rs1', 'Implicit rs1, always be zero.' @@ -581,6 +638,7 @@ def __new__(cls, value: int, arg_name: str, is_dest: bool, is_implicit: bool, 'opnd_create_reg(DR_REG_ZERO)', False, True, + False, 'OPSZ_PTR', 'rs2', 'Implicit rs2, always be zero.' @@ -589,6 +647,7 @@ def __new__(cls, value: int, arg_name: str, is_dest: bool, is_implicit: bool, 'opnd_create_reg(DR_REG_ZERO)', True, True, + False, 'OPSZ_PTR', 'rd', 'Implicit rd, always be zero.' @@ -597,6 +656,7 @@ def __new__(cls, value: int, arg_name: str, is_dest: bool, is_implicit: bool, 'opnd_create_reg(DR_REG_RA)', True, True, + False, 'OPSZ_PTR', 'rd', 'Implicit rd, always be ra.' @@ -605,6 +665,7 @@ def __new__(cls, value: int, arg_name: str, is_dest: bool, is_implicit: bool, 'opnd_create_reg(DR_REG_SP)', True, True, + False, 'OPSZ_PTR', 'rd', 'Implicit rd, always be sp.' @@ -613,6 +674,7 @@ def __new__(cls, value: int, arg_name: str, is_dest: bool, is_implicit: bool, 'opnd_create_immed_int(0, OPSZ_1)', False, True, + True, 'OPSZ_1', 'imm', 'Implicit imm, always be 0.' @@ -621,6 +683,7 @@ def __new__(cls, value: int, arg_name: str, is_dest: bool, is_implicit: bool, 'Rd', False, True, + False, 'OPSZ_PTR', 'rs1', 'Implicit rs1, same as CRD.' @@ -629,6 +692,7 @@ def __new__(cls, value: int, arg_name: str, is_dest: bool, is_implicit: bool, 'Rd', False, True, + False, 'OPSZ_PTR', 'rs1', 'Implicit rs1, same as CRD__.', @@ -640,8 +704,12 @@ def __str__(self) -> str: def asm_name(self) -> str: return self._asm_name if self._asm_name != '' else self.arg_name - def formatted_name(self) -> str: - return self.arg_name if self.is_implicit else self.arg_name.capitalize() + def formatted_name(self, is_body : bool = False) -> str: + name = self.arg_name if self.is_implicit else self.arg_name.capitalize() + if is_body and self.as_decimal: + return f'opnd_add_flags({ name }, DR_OPND_IMM_PRINT_DECIMAL)' + else: + return name def from_str(fld: str): return Field[fld.upper().replace("(FP)", "FP")] @@ -747,9 +815,10 @@ def __fixup_compressed_inst(self, inst: Instruction): if (opc == 0b00 or opc == 0b10) and funct3 not in [0, 0b100]: # LOAD/STORE instructions dbg(f'fixup: {inst.name} {[f.name for f in inst.flds]}') # Immediate argument will handle the base+disp. - if opc == 0b00: + if opc == 0b00: # non-SP LOAD/STORE instructions inst.flds.pop(1) - inst.flds.reverse() + if funct3 > 0b100: # only reverse for STORE instructions + inst.flds.reverse() dbg(f' -> {" " * len(inst.name)} {[f.name for f in inst.flds]}') elif Field.CB_IMM in inst.flds: # Compare-and-branch instructions need their branch operand moved @@ -980,7 +1049,7 @@ def generate_instr_macros(self, template_file, out_file) -> bool: [f' * \param {f.formatted_name():6} {f.arg_cmt}' for f in flds]) if len(all_flds) > 0: body_args += ', ' - body_args += ', '.join([f.formatted_name() + body_args += ', '.join([f.formatted_name(True) for f in all_flds]) nd = len([f for f in all_flds if f.is_dest]) ns = len(all_flds) - nd diff --git a/core/ir/riscv64/instr_create_api.h.in b/core/ir/riscv64/instr_create_api.h.in index 882edadb34e..db06f3b90e9 100644 --- a/core/ir/riscv64/instr_create_api.h.in +++ b/core/ir/riscv64/instr_create_api.h.in @@ -121,9 +121,7 @@ * \param s The source register opnd. */ #define XINST_CREATE_move(dc, d, s) \ - INSTR_CREATE_addi( \ - dc, d, s, \ - opnd_add_flags(opnd_create_immed_int(0, OPSZ_12b), DR_OPND_IMM_PRINT_DECIMAL)) + INSTR_CREATE_addi(dc, d, s, opnd_create_immed_int(0, OPSZ_12b)) /** * This platform-independent macro creates an instr_t for a multimedia * register load instruction. diff --git a/core/ir/riscv64/ir_utils.c b/core/ir/riscv64/ir_utils.c index c51ca2ea74e..05b60f24aee 100644 --- a/core/ir/riscv64/ir_utils.c +++ b/core/ir/riscv64/ir_utils.c @@ -111,9 +111,7 @@ mov32(dcontext_t *dcontext, instrlist_t *ilist, instr_t *instr, opnd_t dst, int3 if (lo12 != 0 || hi20 == 0) { src = hi20 != 0 ? dst : opnd_create_reg(DR_REG_X0); instr_addiw = - INSTR_CREATE_addiw(dcontext, dst, src, - opnd_add_flags(opnd_create_immed_int(lo12, OPSZ_12b), - DR_OPND_IMM_PRINT_DECIMAL)); + INSTR_CREATE_addiw(dcontext, dst, src, opnd_create_immed_int(lo12, OPSZ_12b)); PRE(ilist, instr, instr_addiw); if (first != NULL && !*first_set) { *first = instr_addiw; @@ -152,17 +150,14 @@ mov64(dcontext_t *dcontext, instrlist_t *ilist, instr_t *instr, opnd_t dst, ptr_ hi52 = ((hi52 >> (shift - 12)) << shift) >> shift; mov64(dcontext, ilist, instr, dst, hi52, first, last, first_set); - tmp = INSTR_CREATE_slli( - dcontext, dst, dst, - opnd_add_flags(opnd_create_immed_int(shift, OPSZ_6b), DR_OPND_IMM_PRINT_DECIMAL)); + tmp = INSTR_CREATE_slli(dcontext, dst, dst, opnd_create_immed_int(shift, OPSZ_6b)); PRE(ilist, instr, tmp); if (last != NULL) *last = tmp; if (lo12) { - tmp = INSTR_CREATE_addi(dcontext, dst, dst, - opnd_add_flags(opnd_create_immed_int(lo12, OPSZ_12b), - DR_OPND_IMM_PRINT_DECIMAL)); + tmp = + INSTR_CREATE_addi(dcontext, dst, dst, opnd_create_immed_int(lo12, OPSZ_12b)); PRE(ilist, instr, tmp); if (last != NULL) *last = tmp; diff --git a/core/ir/riscv64/isl/README.md b/core/ir/riscv64/isl/README.md index b7b7d0114a0..48c95798f3c 100644 --- a/core/ir/riscv64/isl/README.md +++ b/core/ir/riscv64/isl/README.md @@ -139,6 +139,7 @@ If you want to add a new field: - `arg_name`: Name to use in instruction creation macros. - `is_dest`: True if it is a destination operand. - `is_implicit`: True if it is an implicit operand. + - `as_decimal`: True if displayed as decimal. - `opsz_def`: Operand size (`OPSZ_*` value) or if this field decodes into an operand of a different size depending on instruction - dictionary indexed by instruction mnemonic with operand size values. diff --git a/suite/tests/CMakeLists.txt b/suite/tests/CMakeLists.txt index 2cd2a5c0531..594f7b74afe 100644 --- a/suite/tests/CMakeLists.txt +++ b/suite/tests/CMakeLists.txt @@ -2053,6 +2053,8 @@ if (BUILD_CLIENTS) set(drdisas_args "-vl" "256" "00000000" "f94017a0" "a9be7bfd" "e58057a1" "85865e6b" "88") elseif (ARM) set(drdisas_args "6813" "f243" "42c8" "b2db" "88") + elseif (RISCV64) + set(drdisas_args "853e" "4581" "1d27b783" "00f55733" "9d89" "88") else () set(drdisas_args "-syntax" "dr" "66" "90" "c4" "e2" "65" "90" "14" "80" "88") endif () @@ -5915,6 +5917,7 @@ if (RISCV64) code_api|pthreads.pthreads_exit code_api|sample.bbbuf code_api|security-linux.trampoline + code_api|tool.drdisas no_code_api,no_intercept_all_signals|linux.sigaction PROPERTIES LABELS RUNS_ON_QEMU) if (DEBUG) diff --git a/suite/tests/api/ir_riscv64.c b/suite/tests/api/ir_riscv64.c index 27fc2c6faff..03ee76024e3 100644 --- a/suite/tests/api/ir_riscv64.c +++ b/suite/tests/api/ir_riscv64.c @@ -165,121 +165,84 @@ test_integer_load_store(void *dc) instr_t *instr; /* Load */ - instr = INSTR_CREATE_lb( - dc, opnd_create_reg(DR_REG_A0), - opnd_add_flags(opnd_create_base_disp(DR_REG_A1, DR_REG_NULL, 0, 0, OPSZ_1), - DR_OPND_IMM_PRINT_DECIMAL)); + instr = INSTR_CREATE_lb(dc, opnd_create_reg(DR_REG_A0), + opnd_create_base_disp(DR_REG_A1, DR_REG_NULL, 0, 0, OPSZ_1)); test_instr_encoding(dc, OP_lb, instr); - instr = INSTR_CREATE_lbu( - dc, opnd_create_reg(DR_REG_X0), - opnd_add_flags(opnd_create_base_disp(DR_REG_A1, DR_REG_NULL, 0, -1, OPSZ_1), - DR_OPND_IMM_PRINT_DECIMAL)); - test_instr_encoding(dc, OP_lbu, instr); instr = - INSTR_CREATE_lh(dc, opnd_create_reg(DR_REG_A0), - opnd_add_flags(opnd_create_base_disp(DR_REG_A1, DR_REG_NULL, 0, - (1 << 11) - 1, OPSZ_2), - DR_OPND_IMM_PRINT_DECIMAL)); - test_instr_encoding(dc, OP_lh, instr); - instr = INSTR_CREATE_lhu( + INSTR_CREATE_lbu(dc, opnd_create_reg(DR_REG_X0), + opnd_create_base_disp(DR_REG_A1, DR_REG_NULL, 0, -1, OPSZ_1)); + test_instr_encoding(dc, OP_lbu, instr); + instr = INSTR_CREATE_lh( dc, opnd_create_reg(DR_REG_A0), - opnd_add_flags(opnd_create_base_disp(DR_REG_X0, DR_REG_NULL, 0, 0, OPSZ_2), - DR_OPND_IMM_PRINT_DECIMAL)); + opnd_create_base_disp(DR_REG_A1, DR_REG_NULL, 0, (1 << 11) - 1, OPSZ_2)); + test_instr_encoding(dc, OP_lh, instr); + instr = INSTR_CREATE_lhu(dc, opnd_create_reg(DR_REG_A0), + opnd_create_base_disp(DR_REG_X0, DR_REG_NULL, 0, 0, OPSZ_2)); test_instr_encoding(dc, OP_lhu, instr); - instr = INSTR_CREATE_lw( - dc, opnd_create_reg(DR_REG_X31), - opnd_add_flags(opnd_create_base_disp(DR_REG_A1, DR_REG_NULL, 0, -1, OPSZ_4), - DR_OPND_IMM_PRINT_DECIMAL)); + instr = INSTR_CREATE_lw(dc, opnd_create_reg(DR_REG_X31), + opnd_create_base_disp(DR_REG_A1, DR_REG_NULL, 0, -1, OPSZ_4)); test_instr_encoding(dc, OP_lw, instr); - instr = INSTR_CREATE_lwu( - dc, opnd_create_reg(DR_REG_A0), - opnd_add_flags(opnd_create_base_disp(DR_REG_X31, DR_REG_NULL, 0, 0, OPSZ_4), - DR_OPND_IMM_PRINT_DECIMAL)); + instr = + INSTR_CREATE_lwu(dc, opnd_create_reg(DR_REG_A0), + opnd_create_base_disp(DR_REG_X31, DR_REG_NULL, 0, 0, OPSZ_4)); test_instr_encoding(dc, OP_lwu, instr); - instr = INSTR_CREATE_ld( - dc, opnd_create_reg(DR_REG_A0), - opnd_add_flags(opnd_create_base_disp(DR_REG_A1, DR_REG_NULL, 0, 42, OPSZ_8), - DR_OPND_IMM_PRINT_DECIMAL)); + instr = INSTR_CREATE_ld(dc, opnd_create_reg(DR_REG_A0), + opnd_create_base_disp(DR_REG_A1, DR_REG_NULL, 0, 42, OPSZ_8)); test_instr_encoding(dc, OP_ld, instr); /* Store */ - instr = INSTR_CREATE_sb( - dc, - opnd_add_flags(opnd_create_base_disp(DR_REG_A1, DR_REG_NULL, 0, 0, OPSZ_1), - DR_OPND_IMM_PRINT_DECIMAL), - opnd_create_reg(DR_REG_A0)); + instr = + INSTR_CREATE_sb(dc, opnd_create_base_disp(DR_REG_A1, DR_REG_NULL, 0, 0, OPSZ_1), + opnd_create_reg(DR_REG_A0)); test_instr_encoding(dc, OP_sb, instr); - instr = INSTR_CREATE_sh( - dc, - opnd_add_flags(opnd_create_base_disp(DR_REG_X0, DR_REG_NULL, 0, -1, OPSZ_2), - DR_OPND_IMM_PRINT_DECIMAL), - opnd_create_reg(DR_REG_X31)); - test_instr_encoding(dc, OP_sh, instr); instr = - INSTR_CREATE_sw(dc, - opnd_add_flags(opnd_create_base_disp(DR_REG_X31, DR_REG_NULL, 0, - (1 << 11) - 1, OPSZ_4), - DR_OPND_IMM_PRINT_DECIMAL), - opnd_create_reg(DR_REG_X0)); + INSTR_CREATE_sh(dc, opnd_create_base_disp(DR_REG_X0, DR_REG_NULL, 0, -1, OPSZ_2), + opnd_create_reg(DR_REG_X31)); + test_instr_encoding(dc, OP_sh, instr); + instr = INSTR_CREATE_sw( + dc, opnd_create_base_disp(DR_REG_X31, DR_REG_NULL, 0, (1 << 11) - 1, OPSZ_4), + opnd_create_reg(DR_REG_X0)); test_instr_encoding(dc, OP_sw, instr); - instr = INSTR_CREATE_sd( - dc, - opnd_add_flags(opnd_create_base_disp(DR_REG_A1, DR_REG_NULL, 0, 42, OPSZ_8), - DR_OPND_IMM_PRINT_DECIMAL), - opnd_create_reg(DR_REG_A0)); + instr = + INSTR_CREATE_sd(dc, opnd_create_base_disp(DR_REG_A1, DR_REG_NULL, 0, 42, OPSZ_8), + opnd_create_reg(DR_REG_A0)); test_instr_encoding(dc, OP_sd, instr); /* Compressed Load */ - instr = INSTR_CREATE_c_ldsp( - dc, opnd_create_reg(DR_REG_A0), - opnd_add_flags(opnd_create_base_disp(DR_REG_SP, DR_REG_NULL, 0, 0, OPSZ_8), - DR_OPND_IMM_PRINT_DECIMAL)); + instr = + INSTR_CREATE_c_ldsp(dc, opnd_create_reg(DR_REG_A0), + opnd_create_base_disp(DR_REG_SP, DR_REG_NULL, 0, 0, OPSZ_8)); test_instr_encoding(dc, OP_c_ldsp, instr); instr = INSTR_CREATE_c_ld( dc, opnd_create_reg(DR_REG_X8), - opnd_add_flags(opnd_create_base_disp(DR_REG_X15, DR_REG_NULL, 0, - ((1 << 5) - 1) << 3, OPSZ_8), - DR_OPND_IMM_PRINT_DECIMAL)); + opnd_create_base_disp(DR_REG_X15, DR_REG_NULL, 0, ((1 << 5) - 1) << 3, OPSZ_8)); test_instr_encoding(dc, OP_c_ld, instr); instr = INSTR_CREATE_c_lwsp( dc, opnd_create_reg(DR_REG_X0), - opnd_add_flags( - opnd_create_base_disp(DR_REG_SP, DR_REG_NULL, 0, ((1 << 5) - 1) << 2, OPSZ_4), - DR_OPND_IMM_PRINT_DECIMAL)); + opnd_create_base_disp(DR_REG_SP, DR_REG_NULL, 0, ((1 << 5) - 1) << 2, OPSZ_4)); test_instr_encoding(dc, OP_c_lwsp, instr); instr = INSTR_CREATE_c_lw( dc, opnd_create_reg(DR_REG_X8), - opnd_add_flags(opnd_create_base_disp(DR_REG_X15, DR_REG_NULL, 0, - ((1 << 5) - 1) << 2, OPSZ_4), - DR_OPND_IMM_PRINT_DECIMAL)); + opnd_create_base_disp(DR_REG_X15, DR_REG_NULL, 0, ((1 << 5) - 1) << 2, OPSZ_4)); test_instr_encoding(dc, OP_c_lw, instr); /* Compressed Store */ instr = INSTR_CREATE_c_sdsp( - dc, - opnd_add_flags(opnd_create_base_disp(DR_REG_SP, DR_REG_NULL, 0, 0, OPSZ_8), - DR_OPND_IMM_PRINT_DECIMAL), + dc, opnd_create_base_disp(DR_REG_SP, DR_REG_NULL, 0, 0, OPSZ_8), opnd_create_reg(DR_REG_A0)); test_instr_encoding(dc, OP_c_sdsp, instr); instr = INSTR_CREATE_c_sd( dc, - opnd_add_flags(opnd_create_base_disp(DR_REG_X15, DR_REG_NULL, 0, - ((1 << 5) - 1) << 3, OPSZ_8), - DR_OPND_IMM_PRINT_DECIMAL), + opnd_create_base_disp(DR_REG_X15, DR_REG_NULL, 0, ((1 << 5) - 1) << 3, OPSZ_8), opnd_create_reg(DR_REG_X8)); test_instr_encoding(dc, OP_c_sd, instr); instr = INSTR_CREATE_c_swsp( - dc, - opnd_add_flags( - opnd_create_base_disp(DR_REG_SP, DR_REG_NULL, 0, ((1 << 5) - 1) << 2, OPSZ_4), - DR_OPND_IMM_PRINT_DECIMAL), + dc, opnd_create_base_disp(DR_REG_SP, DR_REG_NULL, 0, ((1 << 5) - 1) << 2, OPSZ_4), opnd_create_reg(DR_REG_X0)); test_instr_encoding(dc, OP_c_swsp, instr); instr = INSTR_CREATE_c_sw( dc, - opnd_add_flags(opnd_create_base_disp(DR_REG_X15, DR_REG_NULL, 0, - ((1 << 5) - 1) << 2, OPSZ_4), - DR_OPND_IMM_PRINT_DECIMAL), + opnd_create_base_disp(DR_REG_X15, DR_REG_NULL, 0, ((1 << 5) - 1) << 2, OPSZ_4), opnd_create_reg(DR_REG_X8)); test_instr_encoding(dc, OP_c_sw, instr); } @@ -289,67 +252,47 @@ test_float_load_store(void *dc) { instr_t *instr; - instr = INSTR_CREATE_flw( - dc, opnd_create_reg(DR_REG_F0), - opnd_add_flags(opnd_create_base_disp(DR_REG_A1, DR_REG_NULL, 0, 0, OPSZ_4), - DR_OPND_IMM_PRINT_DECIMAL)); + instr = INSTR_CREATE_flw(dc, opnd_create_reg(DR_REG_F0), + opnd_create_base_disp(DR_REG_A1, DR_REG_NULL, 0, 0, OPSZ_4)); test_instr_encoding(dc, OP_flw, instr); - instr = INSTR_CREATE_fld( - dc, opnd_create_reg(DR_REG_F31), - opnd_add_flags(opnd_create_base_disp(DR_REG_X0, DR_REG_NULL, 0, -1, OPSZ_8), - DR_OPND_IMM_PRINT_DECIMAL)); + instr = + INSTR_CREATE_fld(dc, opnd_create_reg(DR_REG_F31), + opnd_create_base_disp(DR_REG_X0, DR_REG_NULL, 0, -1, OPSZ_8)); test_instr_encoding(dc, OP_fld, instr); - instr = INSTR_CREATE_flq( - dc, opnd_create_reg(DR_REG_F31), - opnd_add_flags(opnd_create_base_disp(DR_REG_X0, DR_REG_NULL, 0, -1, OPSZ_16), - DR_OPND_IMM_PRINT_DECIMAL)); - test_instr_encoding(dc, OP_flq, instr); instr = - INSTR_CREATE_fsw(dc, - opnd_add_flags(opnd_create_base_disp(DR_REG_X31, DR_REG_NULL, 0, - (1 << 11) - 1, OPSZ_4), - DR_OPND_IMM_PRINT_DECIMAL), - opnd_create_reg(DR_REG_F1)); + INSTR_CREATE_flq(dc, opnd_create_reg(DR_REG_F31), + opnd_create_base_disp(DR_REG_X0, DR_REG_NULL, 0, -1, OPSZ_16)); + test_instr_encoding(dc, OP_flq, instr); + instr = INSTR_CREATE_fsw( + dc, opnd_create_base_disp(DR_REG_X31, DR_REG_NULL, 0, (1 << 11) - 1, OPSZ_4), + opnd_create_reg(DR_REG_F1)); test_instr_encoding(dc, OP_fsw, instr); - instr = - INSTR_CREATE_fsd(dc, - opnd_add_flags(opnd_create_base_disp(DR_REG_X31, DR_REG_NULL, 0, - (1 << 11) - 1, OPSZ_8), - DR_OPND_IMM_PRINT_DECIMAL), - opnd_create_reg(DR_REG_F31)); + instr = INSTR_CREATE_fsd( + dc, opnd_create_base_disp(DR_REG_X31, DR_REG_NULL, 0, (1 << 11) - 1, OPSZ_8), + opnd_create_reg(DR_REG_F31)); test_instr_encoding(dc, OP_fsd, instr); - instr = - INSTR_CREATE_fsq(dc, - opnd_add_flags(opnd_create_base_disp(DR_REG_X31, DR_REG_NULL, 0, - (1 << 11) - 1, OPSZ_16), - DR_OPND_IMM_PRINT_DECIMAL), - opnd_create_reg(DR_REG_F31)); + instr = INSTR_CREATE_fsq( + dc, opnd_create_base_disp(DR_REG_X31, DR_REG_NULL, 0, (1 << 11) - 1, OPSZ_16), + opnd_create_reg(DR_REG_F31)); test_instr_encoding(dc, OP_fsq, instr); /* Compressed */ - instr = INSTR_CREATE_c_fldsp( - dc, opnd_create_reg(DR_REG_F0), - opnd_add_flags(opnd_create_base_disp(DR_REG_SP, DR_REG_NULL, 0, 0, OPSZ_8), - DR_OPND_IMM_PRINT_DECIMAL)); + instr = + INSTR_CREATE_c_fldsp(dc, opnd_create_reg(DR_REG_F0), + opnd_create_base_disp(DR_REG_SP, DR_REG_NULL, 0, 0, OPSZ_8)); test_instr_encoding(dc, OP_c_fldsp, instr); instr = INSTR_CREATE_c_fld( dc, opnd_create_reg(DR_REG_F8), - opnd_add_flags(opnd_create_base_disp(DR_REG_X15, DR_REG_NULL, 0, - ((1 << 5) - 1) << 3, OPSZ_8), - DR_OPND_IMM_PRINT_DECIMAL)); + opnd_create_base_disp(DR_REG_X15, DR_REG_NULL, 0, ((1 << 5) - 1) << 3, OPSZ_8)); test_instr_encoding(dc, OP_c_fld, instr); /* There is no c.flw* instructions in RV64. */ instr = INSTR_CREATE_c_fsdsp( - dc, - opnd_add_flags(opnd_create_base_disp(DR_REG_SP, DR_REG_NULL, 0, 0, OPSZ_8), - DR_OPND_IMM_PRINT_DECIMAL), + dc, opnd_create_base_disp(DR_REG_SP, DR_REG_NULL, 0, 0, OPSZ_8), opnd_create_reg(DR_REG_F31)); test_instr_encoding(dc, OP_c_fsdsp, instr); instr = INSTR_CREATE_c_fsd( dc, - opnd_add_flags(opnd_create_base_disp(DR_REG_X15, DR_REG_NULL, 0, - ((1 << 5) - 1) << 3, OPSZ_8), - DR_OPND_IMM_PRINT_DECIMAL), + opnd_create_base_disp(DR_REG_X15, DR_REG_NULL, 0, ((1 << 5) - 1) << 3, OPSZ_8), opnd_create_reg(DR_REG_F8)); test_instr_encoding(dc, OP_c_fsd, instr); /* There is no c.fsw* instructions in RV64. */ @@ -922,64 +865,44 @@ static void test_integer(void *dc) { instr_t *instr; - instr = INSTR_CREATE_addi( - dc, opnd_create_reg(DR_REG_A0), opnd_create_reg(DR_REG_A1), - opnd_add_flags(opnd_create_immed_int(0, OPSZ_12b), DR_OPND_IMM_PRINT_DECIMAL)); + instr = INSTR_CREATE_addi(dc, opnd_create_reg(DR_REG_A0), opnd_create_reg(DR_REG_A1), + opnd_create_immed_int(0, OPSZ_12b)); test_instr_encoding(dc, OP_addi, instr); - instr = INSTR_CREATE_addiw( - dc, opnd_create_reg(DR_REG_A0), opnd_create_reg(DR_REG_A1), - opnd_add_flags(opnd_create_immed_int(0, OPSZ_12b), DR_OPND_IMM_PRINT_DECIMAL)); + instr = INSTR_CREATE_addiw(dc, opnd_create_reg(DR_REG_A0), opnd_create_reg(DR_REG_A1), + opnd_create_immed_int(0, OPSZ_12b)); test_instr_encoding(dc, OP_addiw, instr); - instr = INSTR_CREATE_slti( - dc, opnd_create_reg(DR_REG_A0), opnd_create_reg(DR_REG_A1), - opnd_add_flags(opnd_create_immed_int(-1, OPSZ_12b), DR_OPND_IMM_PRINT_DECIMAL)); + instr = INSTR_CREATE_slti(dc, opnd_create_reg(DR_REG_A0), opnd_create_reg(DR_REG_A1), + opnd_create_immed_int(-1, OPSZ_12b)); test_instr_encoding(dc, OP_slti, instr); - instr = - INSTR_CREATE_sltiu(dc, opnd_create_reg(DR_REG_A0), opnd_create_reg(DR_REG_A1), - opnd_add_flags(opnd_create_immed_int((1 << 11) - 1, OPSZ_12b), - DR_OPND_IMM_PRINT_DECIMAL)); + instr = INSTR_CREATE_sltiu(dc, opnd_create_reg(DR_REG_A0), opnd_create_reg(DR_REG_A1), + opnd_create_immed_int((1 << 11) - 1, OPSZ_12b)); test_instr_encoding(dc, OP_sltiu, instr); - instr = - INSTR_CREATE_xori(dc, opnd_create_reg(DR_REG_A0), opnd_create_reg(DR_REG_A1), - opnd_add_flags(opnd_create_immed_int((1 << 11) - 1, OPSZ_12b), - DR_OPND_IMM_PRINT_DECIMAL)); + instr = INSTR_CREATE_xori(dc, opnd_create_reg(DR_REG_A0), opnd_create_reg(DR_REG_A1), + opnd_create_immed_int((1 << 11) - 1, OPSZ_12b)); test_instr_encoding(dc, OP_xori, instr); - instr = - INSTR_CREATE_ori(dc, opnd_create_reg(DR_REG_A0), opnd_create_reg(DR_REG_A1), - opnd_add_flags(opnd_create_immed_int((1 << 11) - 1, OPSZ_12b), - DR_OPND_IMM_PRINT_DECIMAL)); + instr = INSTR_CREATE_ori(dc, opnd_create_reg(DR_REG_A0), opnd_create_reg(DR_REG_A1), + opnd_create_immed_int((1 << 11) - 1, OPSZ_12b)); test_instr_encoding(dc, OP_ori, instr); - instr = - INSTR_CREATE_andi(dc, opnd_create_reg(DR_REG_A0), opnd_create_reg(DR_REG_A1), - opnd_add_flags(opnd_create_immed_int((1 << 11) - 1, OPSZ_12b), - DR_OPND_IMM_PRINT_DECIMAL)); + instr = INSTR_CREATE_andi(dc, opnd_create_reg(DR_REG_A0), opnd_create_reg(DR_REG_A1), + opnd_create_immed_int((1 << 11) - 1, OPSZ_12b)); test_instr_encoding(dc, OP_andi, instr); instr = INSTR_CREATE_slli(dc, opnd_create_reg(DR_REG_A0), opnd_create_reg(DR_REG_A1), - opnd_add_flags(opnd_create_immed_int((1 << 6) - 1, OPSZ_6b), - DR_OPND_IMM_PRINT_DECIMAL)); + opnd_create_immed_int((1 << 6) - 1, OPSZ_6b)); test_instr_encoding(dc, OP_slli, instr); - instr = - INSTR_CREATE_slliw(dc, opnd_create_reg(DR_REG_A0), opnd_create_reg(DR_REG_A1), - opnd_add_flags(opnd_create_immed_int((1 << 5) - 1, OPSZ_5b), - DR_OPND_IMM_PRINT_DECIMAL)); + instr = INSTR_CREATE_slliw(dc, opnd_create_reg(DR_REG_A0), opnd_create_reg(DR_REG_A1), + opnd_create_immed_int((1 << 5) - 1, OPSZ_5b)); test_instr_encoding(dc, OP_slliw, instr); instr = INSTR_CREATE_srli(dc, opnd_create_reg(DR_REG_A0), opnd_create_reg(DR_REG_A1), - opnd_add_flags(opnd_create_immed_int((1 << 6) - 1, OPSZ_6b), - DR_OPND_IMM_PRINT_DECIMAL)); + opnd_create_immed_int((1 << 6) - 1, OPSZ_6b)); test_instr_encoding(dc, OP_srli, instr); - instr = - INSTR_CREATE_srliw(dc, opnd_create_reg(DR_REG_A0), opnd_create_reg(DR_REG_A1), - opnd_add_flags(opnd_create_immed_int((1 << 5) - 1, OPSZ_5b), - DR_OPND_IMM_PRINT_DECIMAL)); + instr = INSTR_CREATE_srliw(dc, opnd_create_reg(DR_REG_A0), opnd_create_reg(DR_REG_A1), + opnd_create_immed_int((1 << 5) - 1, OPSZ_5b)); test_instr_encoding(dc, OP_srliw, instr); instr = INSTR_CREATE_srai(dc, opnd_create_reg(DR_REG_A0), opnd_create_reg(DR_REG_A1), - opnd_add_flags(opnd_create_immed_int((1 << 6) - 1, OPSZ_6b), - DR_OPND_IMM_PRINT_DECIMAL)); + opnd_create_immed_int((1 << 6) - 1, OPSZ_6b)); test_instr_encoding(dc, OP_srai, instr); - instr = - INSTR_CREATE_sraiw(dc, opnd_create_reg(DR_REG_A0), opnd_create_reg(DR_REG_A1), - opnd_add_flags(opnd_create_immed_int((1 << 5) - 1, OPSZ_5b), - DR_OPND_IMM_PRINT_DECIMAL)); + instr = INSTR_CREATE_sraiw(dc, opnd_create_reg(DR_REG_A0), opnd_create_reg(DR_REG_A1), + opnd_create_immed_int((1 << 5) - 1, OPSZ_5b)); test_instr_encoding(dc, OP_sraiw, instr); instr = INSTR_CREATE_add(dc, opnd_create_reg(DR_REG_A0), opnd_create_reg(DR_REG_A1), @@ -1069,10 +992,8 @@ test_integer(void *dc) test_instr_encoding(dc, OP_remuw, instr); /* Compressed */ - instr = - INSTR_CREATE_c_addiw(dc, opnd_create_reg(DR_REG_A0), - opnd_add_flags(opnd_create_immed_int((1 << 5) - 1, OPSZ_5b), - DR_OPND_IMM_PRINT_DECIMAL)); + instr = INSTR_CREATE_c_addiw(dc, opnd_create_reg(DR_REG_A0), + opnd_create_immed_int((1 << 5) - 1, OPSZ_5b)); test_instr_encoding(dc, OP_c_addiw, instr); instr = INSTR_CREATE_c_addw(dc, opnd_create_reg(DR_REG_A0), opnd_create_reg(DR_REG_A1)); @@ -1081,24 +1002,17 @@ test_integer(void *dc) INSTR_CREATE_c_subw(dc, opnd_create_reg(DR_REG_A0), opnd_create_reg(DR_REG_A1)); test_instr_encoding(dc, OP_c_subw, instr); - instr = - INSTR_CREATE_c_slli(dc, opnd_create_reg(DR_REG_A1), - opnd_add_flags(opnd_create_immed_int((1 << 6) - 1, OPSZ_6b), - DR_OPND_IMM_PRINT_DECIMAL)); + instr = INSTR_CREATE_c_slli(dc, opnd_create_reg(DR_REG_A1), + opnd_create_immed_int((1 << 6) - 1, OPSZ_6b)); test_instr_encoding(dc, OP_c_slli, instr); - instr = - INSTR_CREATE_c_srli(dc, opnd_create_reg(DR_REG_A1), - opnd_add_flags(opnd_create_immed_int((1 << 6) - 1, OPSZ_6b), - DR_OPND_IMM_PRINT_DECIMAL)); + instr = INSTR_CREATE_c_srli(dc, opnd_create_reg(DR_REG_A1), + opnd_create_immed_int((1 << 6) - 1, OPSZ_6b)); test_instr_encoding(dc, OP_c_srli, instr); - instr = - INSTR_CREATE_c_srai(dc, opnd_create_reg(DR_REG_A1), - opnd_add_flags(opnd_create_immed_int((1 << 6) - 1, OPSZ_6b), - DR_OPND_IMM_PRINT_DECIMAL)); + instr = INSTR_CREATE_c_srai(dc, opnd_create_reg(DR_REG_A1), + opnd_create_immed_int((1 << 6) - 1, OPSZ_6b)); test_instr_encoding(dc, OP_c_srai, instr); - instr = INSTR_CREATE_c_andi( - dc, opnd_create_reg(DR_REG_A1), - opnd_add_flags(opnd_create_immed_int(-1, OPSZ_6b), DR_OPND_IMM_PRINT_DECIMAL)); + instr = INSTR_CREATE_c_andi(dc, opnd_create_reg(DR_REG_A1), + opnd_create_immed_int(-1, OPSZ_6b)); test_instr_encoding(dc, OP_c_andi, instr); instr = INSTR_CREATE_c_mv(dc, opnd_create_reg(DR_REG_A1), opnd_create_reg(DR_REG_A1)); @@ -1179,35 +1093,26 @@ test_jump_and_branch(void *dc) test_instr_encoding_jal_or_branch(dc, OP_c_jr, instr); /* There is no c.jal in RV64. */ instr = INSTR_CREATE_c_jalr(dc, opnd_create_reg(DR_REG_A0)); - test_instr_encoding_jal_or_branch(dc, OP_c_jalr, instr); + test_instr_encoding(dc, OP_c_jalr, instr); instr = INSTR_CREATE_c_beqz(dc, opnd_create_pc(pc), opnd_create_reg(DR_REG_X8)); test_instr_encoding_jal_or_branch(dc, OP_c_beqz, instr); instr = INSTR_CREATE_c_bnez(dc, opnd_create_pc(pc), opnd_create_reg(DR_REG_X8)); test_instr_encoding_jal_or_branch(dc, OP_c_bnez, instr); instr = INSTR_CREATE_c_li(dc, opnd_create_reg(DR_REG_A1), - opnd_add_flags(opnd_create_immed_int((1 << 5) - 1, OPSZ_5b), - DR_OPND_IMM_PRINT_DECIMAL)); + opnd_create_immed_int((1 << 5) - 1, OPSZ_5b)); test_instr_encoding(dc, OP_c_li, instr); /* FIXME i#3544: Need to be better formatted. */ - instr = INSTR_CREATE_c_lui( - dc, opnd_create_reg(DR_REG_A1), - opnd_add_flags(opnd_create_immed_int(1, OPSZ_6b), DR_OPND_IMM_PRINT_DECIMAL)); + instr = INSTR_CREATE_c_lui(dc, opnd_create_reg(DR_REG_A1), + opnd_create_immed_int(1, OPSZ_6b)); test_instr_encoding(dc, OP_c_lui, instr); - instr = - INSTR_CREATE_c_addi(dc, opnd_create_reg(DR_REG_A1), - opnd_add_flags(opnd_create_immed_int((1 << 5) - 1, OPSZ_5b), - DR_OPND_IMM_PRINT_DECIMAL)); + instr = INSTR_CREATE_c_addi(dc, opnd_create_reg(DR_REG_A1), + opnd_create_immed_int((1 << 5) - 1, OPSZ_5b)); test_instr_encoding(dc, OP_c_addi, instr); - instr = - INSTR_CREATE_c_addi16sp(dc, - opnd_add_flags(opnd_create_immed_int(1 << 4, OPSZ_10b), - DR_OPND_IMM_PRINT_DECIMAL)); + instr = INSTR_CREATE_c_addi16sp(dc, opnd_create_immed_int(1 << 4, OPSZ_10b)); test_instr_encoding(dc, OP_c_addi16sp, instr); - instr = - INSTR_CREATE_c_addi4spn(dc, opnd_create_reg(DR_REG_X8), - opnd_add_flags(opnd_create_immed_int(1 << 2, OPSZ_10b), - DR_OPND_IMM_PRINT_DECIMAL)); + instr = INSTR_CREATE_c_addi4spn(dc, opnd_create_reg(DR_REG_X8), + opnd_create_immed_int(1 << 2, OPSZ_10b)); test_instr_encoding(dc, OP_c_addi4spn, instr); } @@ -1224,20 +1129,17 @@ test_csr(void *dc) instr = INSTR_CREATE_csrrc(dc, opnd_create_reg(DR_REG_A0), opnd_create_reg(DR_REG_A1), opnd_create_immed_int(0x42, OPSZ_12b)); test_instr_encoding(dc, OP_csrrc, instr); - instr = INSTR_CREATE_csrrwi( - dc, opnd_create_reg(DR_REG_A0), - opnd_add_flags(opnd_create_immed_int(1, OPSZ_5b), DR_OPND_IMM_PRINT_DECIMAL), - opnd_create_immed_int(0x42, OPSZ_12b)); + instr = INSTR_CREATE_csrrwi(dc, opnd_create_reg(DR_REG_A0), + opnd_create_immed_int(1, OPSZ_5b), + opnd_create_immed_int(0x42, OPSZ_12b)); test_instr_encoding(dc, OP_csrrwi, instr); - instr = INSTR_CREATE_csrrsi( - dc, opnd_create_reg(DR_REG_A0), - opnd_add_flags(opnd_create_immed_int(1, OPSZ_5b), DR_OPND_IMM_PRINT_DECIMAL), - opnd_create_immed_int(0x42, OPSZ_12b)); + instr = INSTR_CREATE_csrrsi(dc, opnd_create_reg(DR_REG_A0), + opnd_create_immed_int(1, OPSZ_5b), + opnd_create_immed_int(0x42, OPSZ_12b)); test_instr_encoding(dc, OP_csrrsi, instr); - instr = INSTR_CREATE_csrrci( - dc, opnd_create_reg(DR_REG_A0), - opnd_add_flags(opnd_create_immed_int(1, OPSZ_5b), DR_OPND_IMM_PRINT_DECIMAL), - opnd_create_immed_int(0x42, OPSZ_12b)); + instr = INSTR_CREATE_csrrci(dc, opnd_create_reg(DR_REG_A0), + opnd_create_immed_int(1, OPSZ_5b), + opnd_create_immed_int(0x42, OPSZ_12b)); test_instr_encoding(dc, OP_csrrci, instr); } @@ -1271,8 +1173,7 @@ test_bit(void *dc) test_instr_encoding(dc, OP_sh3add_uw, instr); instr = INSTR_CREATE_slli_uw(dc, opnd_create_reg(DR_REG_A0), opnd_create_reg(DR_REG_A1), - opnd_add_flags(opnd_create_immed_int((1 << 6) - 1, OPSZ_6b), - DR_OPND_IMM_PRINT_DECIMAL)); + opnd_create_immed_int((1 << 6) - 1, OPSZ_6b)); test_instr_encoding(dc, OP_slli_uw, instr); instr = INSTR_CREATE_andn(dc, opnd_create_reg(DR_REG_A0), opnd_create_reg(DR_REG_A1), @@ -1331,8 +1232,7 @@ test_bit(void *dc) opnd_create_reg(DR_REG_A1)); test_instr_encoding(dc, OP_rorw, instr); instr = INSTR_CREATE_rori(dc, opnd_create_reg(DR_REG_A0), opnd_create_reg(DR_REG_A1), - opnd_add_flags(opnd_create_immed_int((1 << 6) - 1, OPSZ_6b), - DR_OPND_IMM_PRINT_DECIMAL)); + opnd_create_immed_int((1 << 6) - 1, OPSZ_6b)); test_instr_encoding(dc, OP_rori, instr); instr = INSTR_CREATE_orc_b(dc, opnd_create_reg(DR_REG_A0), opnd_create_reg(DR_REG_A1)); @@ -1351,34 +1251,26 @@ test_bit(void *dc) instr = INSTR_CREATE_bclr(dc, opnd_create_reg(DR_REG_A0), opnd_create_reg(DR_REG_A1), opnd_create_reg(DR_REG_A1)); test_instr_encoding(dc, OP_bclr, instr); - instr = - INSTR_CREATE_bclri(dc, opnd_create_reg(DR_REG_A0), opnd_create_reg(DR_REG_A1), - opnd_add_flags(opnd_create_immed_int((1 << 6) - 1, OPSZ_6b), - DR_OPND_IMM_PRINT_DECIMAL)); + instr = INSTR_CREATE_bclri(dc, opnd_create_reg(DR_REG_A0), opnd_create_reg(DR_REG_A1), + opnd_create_immed_int((1 << 6) - 1, OPSZ_6b)); test_instr_encoding(dc, OP_bclri, instr); instr = INSTR_CREATE_bext(dc, opnd_create_reg(DR_REG_A0), opnd_create_reg(DR_REG_A1), opnd_create_reg(DR_REG_A1)); test_instr_encoding(dc, OP_bext, instr); - instr = - INSTR_CREATE_bexti(dc, opnd_create_reg(DR_REG_A0), opnd_create_reg(DR_REG_A1), - opnd_add_flags(opnd_create_immed_int((1 << 6) - 1, OPSZ_6b), - DR_OPND_IMM_PRINT_DECIMAL)); + instr = INSTR_CREATE_bexti(dc, opnd_create_reg(DR_REG_A0), opnd_create_reg(DR_REG_A1), + opnd_create_immed_int((1 << 6) - 1, OPSZ_6b)); test_instr_encoding(dc, OP_bexti, instr); instr = INSTR_CREATE_binv(dc, opnd_create_reg(DR_REG_A0), opnd_create_reg(DR_REG_A1), opnd_create_reg(DR_REG_A1)); test_instr_encoding(dc, OP_binv, instr); - instr = - INSTR_CREATE_binvi(dc, opnd_create_reg(DR_REG_A0), opnd_create_reg(DR_REG_A1), - opnd_add_flags(opnd_create_immed_int((1 << 6) - 1, OPSZ_6b), - DR_OPND_IMM_PRINT_DECIMAL)); + instr = INSTR_CREATE_binvi(dc, opnd_create_reg(DR_REG_A0), opnd_create_reg(DR_REG_A1), + opnd_create_immed_int((1 << 6) - 1, OPSZ_6b)); test_instr_encoding(dc, OP_binvi, instr); instr = INSTR_CREATE_bset(dc, opnd_create_reg(DR_REG_A0), opnd_create_reg(DR_REG_A1), opnd_create_reg(DR_REG_A1)); test_instr_encoding(dc, OP_bset, instr); - instr = - INSTR_CREATE_bseti(dc, opnd_create_reg(DR_REG_A0), opnd_create_reg(DR_REG_A1), - opnd_add_flags(opnd_create_immed_int((1 << 6) - 1, OPSZ_6b), - DR_OPND_IMM_PRINT_DECIMAL)); + instr = INSTR_CREATE_bseti(dc, opnd_create_reg(DR_REG_A0), opnd_create_reg(DR_REG_A1), + opnd_create_immed_int((1 << 6) - 1, OPSZ_6b)); test_instr_encoding(dc, OP_bseti, instr); } @@ -1387,19 +1279,13 @@ test_prefetch(void *dc) { instr_t *instr; instr = INSTR_CREATE_prefetch_i( - dc, - opnd_add_flags(opnd_create_base_disp(DR_REG_X0, DR_REG_NULL, 0, 3 << 5, OPSZ_0), - DR_OPND_IMM_PRINT_DECIMAL)); + dc, opnd_create_base_disp(DR_REG_X0, DR_REG_NULL, 0, 3 << 5, OPSZ_0)); test_instr_encoding(dc, OP_prefetch_i, instr); instr = INSTR_CREATE_prefetch_r( - dc, - opnd_add_flags(opnd_create_base_disp(DR_REG_X31, DR_REG_NULL, 0, 5 << 5, OPSZ_0), - DR_OPND_IMM_PRINT_DECIMAL)); + dc, opnd_create_base_disp(DR_REG_X31, DR_REG_NULL, 0, 5 << 5, OPSZ_0)); test_instr_encoding(dc, OP_prefetch_r, instr); instr = INSTR_CREATE_prefetch_w( - dc, - opnd_add_flags(opnd_create_base_disp(DR_REG_A1, DR_REG_NULL, 0, 0, OPSZ_0), - DR_OPND_IMM_PRINT_DECIMAL)); + dc, opnd_create_base_disp(DR_REG_A1, DR_REG_NULL, 0, 0, OPSZ_0)); test_instr_encoding(dc, OP_prefetch_w, instr); } diff --git a/suite/tests/api/ir_riscv64.expect b/suite/tests/api/ir_riscv64.expect index a609f333b3b..b7809fdb4d2 100644 --- a/suite/tests/api/ir_riscv64.expect +++ b/suite/tests/api/ir_riscv64.expect @@ -222,9 +222,10 @@ c.sub fp a5 -> fp test_integer_arith complete lui 0x2a -> a0 0x0000004000018254 -> a0'> -jalr a1 0x2a -> a0 +jalr a1 42 -> a0 +c.jalr a0 0 -> ra c.li zero 31 -> a1 -c.lui 1 -> a1 +c.lui 0x1 -> a1 c.addi a1 31 -> a1 c.addi16sp sp 16 -> sp c.addi4spn sp 4 -> fp @@ -311,15 +312,15 @@ sd a0 -> (a1)[8byte] sb a0 -> (a1)[1byte] sh a0 -> (a1)[2byte] addi a1 0 -> a0 -jalr a0 0x0 -> zero -addi zero 0x2a -> a0 -jalr ra 0x0 -> zero +jalr a0 0 -> zero +addi zero 42 -> a0 +jalr ra 0 -> zero add a0 a1 -> a0 -addi a0 0x2a -> a0 +addi a0 42 -> a0 add a1 a2 -> a0 sub a0 a1 -> a0 -addi a0 0xffffffd6 -> a0 -jalr a0 0x0 -> ra +addi a0 -42 -> a0 +jalr a0 0 -> ra test_xinst complete test_decode_bad_data complete th.icache.iva a0