From 1a5e921a054949b403a498903560e93f51cd13fc Mon Sep 17 00:00:00 2001 From: Marios Asiminakis Date: Wed, 18 Dec 2024 18:38:54 +0200 Subject: [PATCH] i#3544 RV64: Preserve vtype and vl vector registers Renamed VL and VTYPE to CSR_VL and CSR_VTYPE Issue: #3544 --- core/arch/riscv64/emit_utils.c | 8 ++++---- core/arch/riscv64/mangle.c | 8 ++++---- 2 files changed, 8 insertions(+), 8 deletions(-) diff --git a/core/arch/riscv64/emit_utils.c b/core/arch/riscv64/emit_utils.c index 223446029f0..60d79ef65d2 100644 --- a/core/arch/riscv64/emit_utils.c +++ b/core/arch/riscv64/emit_utils.c @@ -55,8 +55,8 @@ #define FCSR 0x003 #define VSTART 0x008 #define VCSR 0x00F -#define VL 0xC20 -#define VTYPE 0xC21 +#define CSR_VL 0xC20 +#define CSR_VTYPE 0xC21 /* Instruction fixed bits constants. */ @@ -890,12 +890,12 @@ append_save_clear_xflags(dcontext_t *dcontext, instrlist_t *ilist, bool absolute APP(ilist, INSTR_CREATE_csrrs(dcontext, opnd_create_reg(DR_REG_A1), opnd_create_reg(DR_REG_ZERO), - opnd_create_immed_int(VL, OPSZ_12b))); + opnd_create_immed_int(CSR_VL, OPSZ_12b))); APP(ilist, SAVE_TO_DC(dcontext, DR_REG_A1, VL_OFFSET)); APP(ilist, INSTR_CREATE_csrrs(dcontext, opnd_create_reg(DR_REG_A1), opnd_create_reg(DR_REG_ZERO), - opnd_create_immed_int(VTYPE, OPSZ_12b))); + opnd_create_immed_int(CSR_VTYPE, OPSZ_12b))); APP(ilist, SAVE_TO_DC(dcontext, DR_REG_A1, VTYPE_OFFSET)); } } diff --git a/core/arch/riscv64/mangle.c b/core/arch/riscv64/mangle.c index bbebda34d5e..b7ce36e8472 100644 --- a/core/arch/riscv64/mangle.c +++ b/core/arch/riscv64/mangle.c @@ -46,8 +46,8 @@ #define FCSR 0x003 #define VSTART 0x008 #define VCSR 0x00F -#define VL 0xC20 -#define VTYPE 0xC21 +#define CSR_VL 0xC20 +#define CSR_VTYPE 0xC21 /* TODO i#3544: Think of a better way to represent these fields in the IR. */ /* Volume I: RISC-V Unprivileged ISA V20191213. @@ -199,7 +199,7 @@ insert_push_all_registers(dcontext_t *dcontext, clean_call_info_t *cci, PRE(ilist, instr, INSTR_CREATE_csrrs(dcontext, opnd_create_reg(DR_REG_A0), opnd_create_reg(DR_REG_ZERO), - opnd_create_immed_int(VL, OPSZ_12b))); + opnd_create_immed_int(CSR_VL, OPSZ_12b))); PRE(ilist, instr, INSTR_CREATE_c_sdsp(dcontext, OPND_CREATE_MEM64(DR_REG_SP, dstack_offs), @@ -212,7 +212,7 @@ insert_push_all_registers(dcontext_t *dcontext, clean_call_info_t *cci, PRE(ilist, instr, INSTR_CREATE_csrrs(dcontext, opnd_create_reg(DR_REG_A0), opnd_create_reg(DR_REG_ZERO), - opnd_create_immed_int(VTYPE, OPSZ_12b))); + opnd_create_immed_int(CSR_VTYPE, OPSZ_12b))); PRE(ilist, instr, INSTR_CREATE_c_sdsp(dcontext, OPND_CREATE_MEM64(DR_REG_SP, dstack_offs),