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Processor.qsf
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Processor.qsf
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# -------------------------------------------------------------------------- #
#
# Copyright (C) 2016 Intel Corporation. All rights reserved.
# Your use of Intel Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Intel Program License
# Subscription Agreement, the Intel Quartus Prime License Agreement,
# the Intel MegaCore Function License Agreement, or other
# applicable license agreement, including, without limitation,
# that your use is for the sole purpose of programming logic
# devices manufactured by Intel and sold by Intel or its
# authorized distributors. Please refer to the applicable
# agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus Prime
# Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition
# Date created = 23:48:43 January 12, 2016
#
# -------------------------------------------------------------------------- #
#
# Notes:
#
# 1) The default values for assignments are stored in the file:
# Processor_assignment_defaults.qdf
# If this file doesn't exist, see file:
# assignment_defaults.qdf
#
# 2) Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus Prime software
# and any changes you make may be lost or overwritten.
#
# -------------------------------------------------------------------------- #
set_global_assignment -name FAMILY "Cyclone IV E"
set_global_assignment -name DEVICE EP4CE115F29C7
set_global_assignment -name TOP_LEVEL_ENTITY PROCESSOR
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 16.1.0
set_global_assignment -name PROJECT_CREATION_TIME_DATE "23:48:43 JANUARY 12, 2016"
set_global_assignment -name LAST_QUARTUS_VERSION "16.1.0 Lite Edition"
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
set_global_assignment -name NOMINAL_CORE_SUPPLY_VOLTAGE 1.2V
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (Verilog)"
set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "VERILOG HDL" -section_id eda_simulation
set_location_assignment PIN_Y2 -to MAIN_CLOCK
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to MAIN_CLOCK
set_global_assignment -name VERILOG_FILE ALU.v
set_global_assignment -name VERILOG_FILE CONTROL_UNIT.v
set_global_assignment -name VERILOG_FILE CPU.v
set_global_assignment -name VERILOG_FILE MUX_FOR_BUS_B.v
set_global_assignment -name VERILOG_FILE PROCESSOR.v
set_global_assignment -name VERILOG_FILE REGISTER.v
set_global_assignment -name QIP_FILE INSTRUCTION_ROM.qip
set_global_assignment -name QIP_FILE RAM.qip
set_global_assignment -name MIF_FILE INSTRUCTION_FILE.mif
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
set_global_assignment -name MIF_FILE IMAGE.mif
set_global_assignment -name QIP_FILE IMAGE_RAM.qip
set_location_assignment PIN_E21 -to PROCESS_DONE
set_instance_assignment -name IO_STANDARD "2.5 V" -to PROCESS_DONE
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top