Update Derecho Port #501
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Update Derecho Port #501
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Update inteloneapi, cray, intel, nvhpc modules/compiler. Changes answers for inteloneapi and cray. Switch default Derecho queue from main to develop to support quicker turn around and lower costs. Develop is a shared queue.
eclare108213
approved these changes
Sep 26, 2024
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PR checklist
Short (1 sentence) summary of your PR:
Update derecho port
Developer(s):
apcraig
Suggest PR reviewers from list in the column to the right.
Please copy the PR test results link or provide a summary of testing completed below.
Test results largely as expected. Updated cray compiler generates an error in the snow physics that needs to be reviewed further. https://github.com/CICE-Consortium/Test-Results/wiki/icepack_by_hash_forks#05ac0ec3ea666080eed36e67f6cf8ce1255b243f
How much do the PR code changes differ from the unmodified code?
Does this PR create or have dependencies on CICE or any other models?
Does this PR add any new test cases?
Is the documentation being updated? ("Documentation" includes information on the wiki or in the .rst files from doc/source/, which are used to create the online technical docs at https://readthedocs.org/projects/cice-consortium-cice/.)
Please document the changes in detail, including why the changes are made. This will become part of the PR commit log.
Update inteloneapi, cray, intel, nvhpc modules/compiler. Changes answers for inteloneapi and cray.
Switch default Derecho queue from main to develop to support quicker turn around and lower costs. Develop is a shared queue.
Error in the snow physics with the cray compiler needs further assessment, but suggest we merge this now as is. That error does not present itself in CICE with snow physics with the same cray compiler.