This repository contains the intelligent partial mapping features from Odin-II wrapped in a plug-in for Yosys.
The project build skeleton is based on the Yosys F4PGA Plugins project.
It is highly recommended to utilize this plugin through the Verilog to Routing (VTR) project.
Now the Parmys frontend is the default elaborator (using Yosys) and partial mapper (using the Parmys plug-in) in the VTR flow (Parmys -> ABC -> VPR).
make VTR_INSTALL_DIR=`path to VTR build/install directory` plugins -j`nproc`
sudo make install
Available paramters are:
-a ARCHITECTURE_FILE
VTR FPGA architecture description file (XML)
-c XML_CONFIGURATION_FILE
Configuration file
-top top_module
set the specified module as design top module
-nopass
No additional passes will be executed.
-exact_mults int_value
To enable mixing hard block and soft logic implementation of adders
-mults_ratio float_value
To enable mixing hard block and soft logic implementation of adders
-vtr_prim
loads vtr primitives as modules, if the design uses vtr prmitives then this flag is mandatory for first run
-viz
visualizes the netlist at 3 different stages: elaborated, optimized, and mapped.
Example for simple partial mapping with parmys:
# run yosys
yosys
# load the plugin
plugin -i parmys
# read verilog files
read_verilog my_verilog.v
# use parmys to read the architecture file and partial mapping
parmys -a simple_vtr_fpga_architecture.xml
- Clone VTR
- Set up the Environment
- Build
- Run the VTR flow
cd vtr_flow/scripts/
# this command runs the vtr flow [yosys+parmys, abc, vpr]
./run_vtr_flow.py my_verilog.v fpga_architecture.xml
For detailed information please refer to the VTR documentation.
Detailed help on the supported command(s) can be obtained by running help parmys
in Yosys.