From b55d587ee6c40a646332f69f1ee5785375e50aec Mon Sep 17 00:00:00 2001
From: mohamedleithy <leithy@aucegypt.edu>
Date: Fri, 2 Jun 2023 13:53:12 +0300
Subject: [PATCH 1/2] dual ported ram fix

---
 models/ram/config.yml | 2 +-
 placeram/data.py      | 3 ++-
 2 files changed, 3 insertions(+), 2 deletions(-)

diff --git a/models/ram/config.yml b/models/ram/config.yml
index cfe04c0..a1256dd 100644
--- a/models/ram/config.yml
+++ b/models/ram/config.yml
@@ -3,4 +3,4 @@ counts: [8, 32, 128, 256, 512, 1024, 2048]
 design_name_template: "RAM{count}{variant}"
 variants:
   - null
-  # - "1RW1R"
+  - "1RW1R"
diff --git a/placeram/data.py b/placeram/data.py
index 49ee648..04e968d 100644
--- a/placeram/data.py
+++ b/placeram/data.py
@@ -310,7 +310,8 @@ def lrplace(
                 elements: Union[List[Instance], Instance] = getattr(self, accessor)
                 if len(elements) == 0:
                     continue
-                element = elements[i]
+                if i < len(elements):
+                    element = elements[i]
                 if isinstance(element, list):
                     column += element
                 else:

From 94c3736904cc63f30afd835a9a556faf0e81c1ae Mon Sep 17 00:00:00 2001
From: Donn <me@donn.website>
Date: Sun, 4 Jun 2023 10:45:31 +0300
Subject: [PATCH 2/2] Enable some test designs

---
 .github/workflows/main.yml | 8 ++++----
 .gitignore                 | 3 ++-
 dffram.py                  | 4 ++--
 3 files changed, 8 insertions(+), 7 deletions(-)

diff --git a/.github/workflows/main.yml b/.github/workflows/main.yml
index cf28c7a..739057f 100644
--- a/.github/workflows/main.yml
+++ b/.github/workflows/main.yml
@@ -75,18 +75,18 @@ jobs:
       matrix:
         include:
           - { count: "32", width: "8", variant: "DEFAULT" }
-          # - { count: "32", width: "8", variant: "1RW1R" }
+          - { count: "32", width: "8", variant: "1RW1R" }
           - { count: "32", width: "16", variant: "DEFAULT" }
-          # - { count: "32", width: "16", variant: "1RW1R" }
+          - { count: "32", width: "16", variant: "1RW1R" }
           - { count: "32", width: "32", variant: "DEFAULT" }
           # - { count: "32", width: "32", variant: "1RW1R" } # Timeout
           - { count: "32", width: "32", variant: "2R1W" }
           - { count: "256", width: "8", variant: "DEFAULT" }
-          # - { count: "256", width: "8", variant: "1RW1R" }
+          - { count: "256", width: "8", variant: "1RW1R" }
           - { count: "256", width: "16", variant: "DEFAULT" }
           # - { count: "256", width: "16", variant: "1RW1R" } # Timeout
           - { count: "256", width: "32", variant: "DEFAULT" }
-          #- { count: "256", width: "32", variant: "1RW1R" } # Timeout
+          # - { count: "256", width: "32", variant: "1RW1R" } # Timeout
     steps:
       - name: Checkout code
         uses: actions/checkout@v3
diff --git a/.gitignore b/.gitignore
index c05a201..7fae7e5 100644
--- a/.gitignore
+++ b/.gitignore
@@ -28,4 +28,5 @@ support/
 *.log
 *.cvcrc
 *.xz
-venv/
\ No newline at end of file
+venv/
+products_path
\ No newline at end of file
diff --git a/dffram.py b/dffram.py
index 7a45005..bbf5da6 100755
--- a/dffram.py
+++ b/dffram.py
@@ -194,7 +194,7 @@ def cl():
 def synthesis(
     design,
     building_blocks,
-    block_deinitions,
+    block_definitions,
     sta_info,
     widths_supported,
     word_width_bytes,
@@ -215,7 +215,7 @@ def synthesis(
             yosys -import
             set SCL {pdk_liberty_dir}/{sta_info["libs"]["typical"]}
             read_liberty -lib -ignore_miss_dir -setattr blackbox $SCL
-            read_verilog {block_deinitions}
+            read_verilog {block_definitions}
             read_verilog {building_blocks}
             {chparam}
             hierarchy -check -top {design}